MB84VB2000-10_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50102-2E

MCP (Multi-Chip Package) FLASH MEMORY

CMOS

8M (× 8/× 16) FLASH MEMORY &

8M (× 8/× 16) FLASH MEMORY

MB84VB2000^-10/MB84VB2001^-10

■ FEATURES

• Contain 2 chips of MBM29LV800A, and each chip have separate CE.

• Power supply voltage of 2.7 to 3.6 V

• High performance

100 ns maximum access time

• Operating Temperature

–40 to +85°C

• Minimum 100,000 write/erase cycles

• Sector erase architecture

One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes × 2 chips

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VB2000: Top sector

MB84VB2001: Bottom sector

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data in another sector within the same device

• Please refer to "MBM29LV800TA/BA" data sheet in detailed function

Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

MB84VB2000^-10/MB84VB2001^-10

■ BLOCK DIAGRAM

V^CC

V^SS

RY/BY

A⁰to A¹⁸

A^-1

RESET

CE¹

8 M bit

Flash Memory

BYTE

DQ⁰to DQ¹⁵

V^CC

V^SS

8 M bit

Flash Memory

CE²

WE

OE

2

MB84VB2000^-10/MB84VB2001^-10

■ CONNECTION DIAGRAM

(Top View)

A

B

C

D

E

F

G

H

6

5

4

3

2

1

N.C.

A¹⁰

V^SS

DQ⁵

DQ⁷

A⁸

DQ¹

DQ²

DQ⁴

A⁵

A¹

A²

A⁴

N.C.

RY/BY

A⁹

A¹⁴

A⁰

A³

A⁷

OE

A¹¹

DQ⁰

DQ⁸

CE¹

V^SS

A⁶

A¹⁸

DQ¹²

V^CC

DQ¹¹

RESET A¹⁵

DQ³

DQ¹⁰

DQ⁹

A¹²

BYTE

A¹³

A¹⁷

N.C.

CE²

A¹⁶

DQ⁶

DQ¹³

DQ¹⁵/A^-1

DQ¹⁴

WE

Table 1 MB84VB2000/MB84VB2001 Pin Configuration

Function

Input/

Output

A^-1, A⁰to A¹⁸

DQ⁰to DQ¹⁵

CE¹

Address Inputs (Common)

Data Inputs/Outputs (Common)

Chip Enable 1

I

I/O

I

CE²

Chip Enable 2

I

OE

Output Enable (Common)

I

WE

Write Enable (Common)

I

RY/BY

RESET

BYTE

N.C.

Ready/Busy Outputs (Common)

Hardware Reset Pin/Sector Protection Unlock (Common)

Selects 8-bit or 16-bit mode (Common)

No Internal Connection

O

I

—

V^SS

Device Ground (Common)

Power

V^CC

Device Power Supply (Common)

3

MB84VB2000^-10/MB84VB2001^-10

■ PRODUCT LINE UP

Part No.

MB84VB2000/MB84VB2001

+0.6 V

–0.3 V

Ordering Part No.

-10

V^CC= 3.0 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

100

40

■ LOGIC SYMBOL

Table 2 MB84VB2000/MB84VB2001 User Bus Operations (BYTE = V^IH)

Operation (5)

CE¹CE²OE WE

A⁰

A¹

A⁶

A⁹

DQ⁰to DQ¹⁵RESET

H

L

H

L

Auto-Select Manufacture’s Code (1)

L

H

L

V^ID

Code

D^OUT

H

L

Auto-Select Device Code (1)

Read (3)

H

L

V^ID

A⁹

H

L

H

L

A⁰

A¹

A⁶

H

X

L

Full Standby

H

X

H

L

X

H

X

H

X

HIGH-Z

H

Output Disable

Write (Program/Erase)

H

V^ID

L

A⁰

L

A¹

H

A⁶

L

A⁹

V^ID

D^IN

X

H

L

H

L

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

H

L

H

L

H

L

H

L

Code

H

X

Temporary Sector Unprotection

Reset (Hardware)/Standby

X

V^ID

L

HIGH-Z

4

MB84VB2000^-10/MB84VB2001^-10

Table 3 MB84VB2000/MB84VB2001 User Bus Operations (BYTE = V^IL)

DQ¹⁵/

A^-1

DQ⁰to

DQ⁷

Operation (5)

CE¹CE²OE WE

A⁰

A¹

A⁶

A⁹

RESET

H

L

H

L

Auto-Select Manufacture’s

Code (1)

L

H

L

V^ID

Code

D^OUT

H

L

Auto-Select Device Code (1)

Read (3)

H

L

V^ID

A⁹

H

L

H

L

A^-1

A⁰

A¹

A⁶

H

X

L

Full Standby

H

X

H

L

X

H

X

H

X

HIGH-Z

H

Output Disable

Write (Program/Erase)

H

V^ID

L

A^-1

L

A⁰

L

A¹

H

A⁶

L

A⁹

V^ID

D^IN

X

H

L

H

L

Enable Sector Protection

(2), (4)

H

L

H

L

Verify Sector Protection

(2), (4)

H

L

H

L

Code

H

Temporary Sector

Unprotection

X

V^ID

L

Reset (Hardware)/Standby

HIGH-Z

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH,

= Pulse input. See DC Characteristics for voltage levels.

Notes: 1.Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 7.

2.Refer to the section on Sector Protection.

3.WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

4.V^CC= 3.3 V ±10%

5.Do not apply CE¹= CE²= V^ILat a time.

5

MB84VB2000^-10/MB84VB2001^-10

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

• One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes × 2.

• Individual-sector, multiple-sector, or bulk-erase capability.

(×8)

(×16)

(×8)

(×16)

FFFFFH 7FFFFH

FC000H 7E000H

FA000H 7D000H

F8000H 7C000H

F0000H 78000H

E0000H 70000H

D0000H 68000H

C0000H 60000H

B0000H 58000H

A0000H 50000H

90000H 48000H

80000H 40000H

70000H 38000H

60000H 30000H

50000H 28000H

40000H 20000H

30000H 18000H

20000H 10000H

10000H 08000H

00000H 00000H

FFFFFH 7FFFFH

16K byte/8K word

8K byte/4K word

64K byte/32K word

32K byte/16K word

8K byte/4K word

F0000H

78000H

E0000H 70000H

D0000H 68000H

C0000H 60000H

B0000H 58000H

A0000H 50000H

8K byte/4K word

32K byte/16K word

64K byte/32K word

90000H

80000H

70000H

60000H

50000H

40000H

30000H

20000H

10000H

08000H

06000H

04000H

00000H

48000H

40000H

38000H

30000H

28000H

20000H

18000H

10000H

08000H

04000H

03000H

02000H

00000H

8K byte/4K word

16K byte/8K word

MB84VB2000 Sector Architecture

MB84VB2001 Sector Architecture

6

MB84VB2000^-10/MB84VB2001^-10

■ FUNCTIONAL DESCRIPTION

Table 4 Sector Address Tables (MB84VB2000)

Sector

Address

A¹⁸

A¹⁷

A¹⁶

A¹⁵

A¹⁴

A¹³

A¹²

Address Range (×8) Address Range (×16)

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

00000H to 0FFFFH

10000H to 1FFFFH

20000H to 2FFFFH

30000H to 3FFFFH

40000H to 4FFFFH

50000H to 5FFFFH

60000H to 6FFFFH

70000H to 7FFFFH

80000H to 8FFFFH

90000H to 9FFFFH

A0000H to AFFFFH

B0000H to BFFFFH

C0000H to CFFFFH

D0000H to DFFFFH

E0000H to EFFFFH

F0000H to F7FFFH

F8000H to F9FFFH

FA000H to FBFFFH

FC000H to FFFFFH

00000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7BFFFH

7C000H to 7CFFFH

7D000H to 7DFFFH

7E000H to 7FFFFH

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

1

0

1

X

7

MB84VB2000^-10/MB84VB2001^-10

Table 5 Sector Address Tables (MB84VB2001)

Sector

A¹⁸

A¹⁷

A¹⁶

A¹⁵

A¹⁴

A¹³

A¹²

Address Range (×8) Address Range (×16)

Address

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

00000H to 03FFFH

04000H to 05FFFH

06000H to 07FFFH

08000H to 0FFFFH

10000H to 1FFFFH

20000H to 2FFFFH

30000H to 3FFFFH

40000H to 4FFFFH

50000H to 5FFFFH

60000H to 6FFFFH

70000H to 7FFFFH

80000H to 8FFFFH

90000H to 9FFFFH

A0000H to AFFFFH

B0000H to BFFFFH

C0000H to CFFFFH

D0000H to DFFFFH

E0000H to EFFFFH

F0000H to FFFFFH

00000H to 01FFFH

02000H to 02FFFH

03000H to 03FFFH

04000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7FFFFH

SA1

SA2

0

1

SA3

1

X

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

8

MB84VB2000^-10/MB84VB2001^-10

Table 6.1 Flash Memory Autoselect Codes

*1

Type

Manufacture’s Code

A⁶

A¹

A⁰

A_-1

V^IL

X

Code (HEX)

04H

V^IL

Byte

Word

Byte

DAH

MB84VB2000

MB84VB2001

V^IL

V^IH

22DAH

5BH

Device Code

V^IL

X

Word

225BH

*1: A^-1is for Byte mode.

Table 6.2 Expanded Autoselect Code Table

Code DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

04H A^-1/0

DAH A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

22DAH

5BH A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

225BH

0

1

0

1

0

1

0

1

0

1

0

1

Manufacture’s Code

(B)

(W)

(B)

MB84VB2000

0

1

0

1

0

Device

Code

MB84VB2001

0

1

0

1

0

(W)

(B): Byte mode

(W): Word mode

9

MB84VB2000^-10/MB84VB2001^-10

Table 7 Flash Memory Command Definitions

Fourth Bus

Read/Write

Cycle

Bus

Write

Cycles

Req’d

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Command

Sequence

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset

1

XXXH F0H

—

555H

AAH

2AAH

555H

2AAH

555H

2AAH

555H

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

3

55H

F0H RA

90H

RD

—

AAAH

555H

AAH

Autoselect

Program

3

4

6

55H

—

AAAH

555H

AAH

A0H PA

PD

AAAH

555H

AAH

555H

80H

2AAH

555H

2AAH

555H

Chip Erase

Sector Erase

AAH

55H

10H

30H

AAAH

555H

AAH

555H

80H

SA

AAAH

Sector Erase Suspend

Sector Erase Resume

Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H)

Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H)

555H

AAAH

XXXH

2AAH

555H

Set to

Fast Mode

3

AAH

A0H

90H

55H

PD

20H

—

AAAH

Fast Program

(Note)

2

PA

—

XXXH

Reset from Fast

2

F0H

—

Mode (Note)

Extended

4

XXXH 60H SPA 60H SPA 40H SPA SD

Sector Protect

Address bits A¹¹to A¹⁷= X = “H” or “L” for all address commands except or Program Address (PA) and Sector

Address (SA).

Bus operations are defined in Tables 2 and 3.

The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A⁰to A¹⁰

Byte Mode: AAAH or 555H to addresses A^-1and A⁰to A¹⁰

Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

RA =Address of the memory location to be read

PA =Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA =Address of the sector to be erased. The combination of A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²will

uniquely select any sector.

RD =Data read from location RA during read operation.

PD =Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

SPA:Sector address to be protected. Set sector address (SA) and (A⁶, A¹, A⁰) = (0, 1, 0).

SD:Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected

sector addresses.

10

MB84VB2000^-10/MB84VB2001^-10

■ ABSOLUTE MAXIMUM RATINGS

Storage Temperature ..................................................................................................–55°C to +125°C

Ambient Temperature with Power Applied ..................................................................–25°C to +85°C

Voltage with Respect to Ground All pins (Note)..........................................................–0.3 V to V^CC+ 0.5 V

V^CCf/V^CCs Supply (Note) ..............................................................................................–0.3 V to +4.6 V

Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative overshoot

V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V^CCf + 0.5 V or V^CCs

+ 0.5 V. During voltage transitions, outputs may positive overshoot to V^CC+ 2.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Commercial Devices

Ambient Temperature (T^A) .........................................................................–40°C to +85°C

V^CCSupply Voltages..................................................................................+2.7 V to +3.6 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

11

MB84VB2000^-10/MB84VB2001^-10

■ DC CHARACTERISTICS

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Max.

Unit

I^LI

Input Leakage Current

Output Leakage Current

V^IN= V^SSto V^CC, V^CC= V^CCMax.

V^OUT= V^SSto V^CC, V^CC= V^CCMax.

–1.0

+1.0

µA

I^LO

A⁹, OE, RESET Inputs Leakage V^CC= V^CCMax.

I^LIT

—

70

µA

Current

A⁹, OE, RESET = 12.5 V

Byte

Word

Byte

22

25

12

15

35

CE = V^IL, OE = V^IH,

f = 10 MHz

mA

I^CC1

V^CCActive Current (Note 1, 5)

CE = V^IL, OE = V^IH,

f = 5 MHz

—

mA

Word

I^CC2

I^CC3

I^CC4

V^CCActive Current (Note 2, 5)

V^CCCurrent (Standby) (Note 5)

CE = V^IL, OE = V^IH

—

mA

V^CC= V^CCMax., CE = V^CC± 0.3 V,

RESET = V^CC± 0.3 V

5

µA

V^CCCurrent (Standby, Reset)

(Note 5)

V^CC= V^CCMax.,

RESET = V^SS± 0.3 V

—

µA

V^CCCurrent

(Automatic Sleep Mode)

(Note 3, 5)

V^CC= V^CCMax., CE = V^SS± 0.3 V,

RESET = V^CC± 0.3 V

V^IN= V^CC± 0.3 V or V^SS± 0.3 V

I^CC5

5

µA

V^IL

V^IH

Input Low Level

Input High Level

—

–0.5

2.0

0.6

V

V^CC+ 0.3

Voltage for Autoselect and Sector

Protection (A⁹, OE, RESET)

(Note 4)

V^ID

—

11.5

12.5

V

V^OL

V^OH1

V^OH2

V^LKO

Output Low Voltage Level

Output High Voltage Level

Low V^CCLock-Out Voltage

I^OL= 4.0 mA, V^CC= V^CCMin.

I^OH= –2.0 mA, V^CC= V^CCMin.

I^OH= –100 µA, V^CC= V^CCMin.

—

2.4

0.45

—

V

V^CC– 0.4

2.3

—

2.5

Notes: 1.The I^CCcurrent listed includes both the DC operating current and the frequency dependent component

(at 10 MHz).

2.I^CCactive while Embedded Algorithm (program or erase) is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. (V^ID– V^CC) do not exceed 9 V.

5. Total power consumption is (condition of Flash 1) + (condition of Flash 2).

12

MB84VB2000^-10/MB84VB2001^-10

■ AC CHARACTERISTICS

• CE Timing

Parameter

Symbols

Description

Test Setup

-10

Unit

JEDEC Standard

—

t^CCR

CE Recover Time

—

Min.

0

ns

• Read Only Operations Characteristics

Parameter

Symbols

-10

(Note)

Test

Setup

Description

Unit

JEDEC Standard

Min.

Max.

t^AVAV

t^AVQV

t^RC

Read Cycle Time

—

100

—

ns

CE = V^IL

OE = V^IL

t^ACC

Address to Output Delay

100

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CE

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

OE = V^IL

—

100

40

ns

—

30

Output Hold Time from Addresses,

CE or OE, Whichever Occurs First

t^AXQX

—

t^OH

—

0

—

20

5

ns

µs

ns

t^READY

RESET Pin Low to Read Mode

—

t^ELFL

t^ELFH

—

CE or BYTE Switching Low or High

Note: Test Conditions–Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

13

MB84VB2000^-10/MB84VB2001^-10

• Erase/Program Operations

Parameter Symbols

Description

-10

Unit

JEDEC

t^AVAV

t^AVWL

t^AVEL

Standard

Min. Typ. Max.

t^WC

t^AS

Write Cycle Time

100

0

—

8

—

15

—

100

90

30

—

ns

µs

sec

µs

ns

µs

ns

Address Setup Time (WE to Addr.)

Address Setup Time (CE to Addr.)

Address Hold Time (WE to Addr.)

Address Hold Time (CE to Addr.)

Data Setup Time

t^AS

0

t^WLAX

t^ELAX

t^AH

t^DS

t^DH

t^OES

50

0

t^DVWH

t^WHDX

—

Data Hold Time

Output Enable Setup Time

0

Read

0

—

t^OEH

Output Enable Hold Time

Toggle and Data Polling

10

0

t^GHEL

t^GHWL

t^WLEL

t^ELWL

t^EHWH

t^WHEH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

t^WHWH1

t^WHWH2

—

t^GHEL

t^GHWL

t^WS

Read Recover Time Before Write (OE to CE)

Read Recover Time Before Write (OE to WE)

WE Setup Time (CE to WE)

CE Setup Time (WE to CE)

WE Hold Time (CE to WE)

0

t^CS

0

t^WH

0

t^CH

CE Hold Time (WE to CE)

0

t^WP

Write Pulse Width

50

30

—

50

500

4

t^CP

CE Pulse Width

t^WPH

t^CPH

t^WHWH1

t^WHWH2

t^VCS

t^VIDR

t^VLHT

t^WPP

t^OESP

t^CSP

t^RB

Write Pulse Width High

CE Pulse Width High

Byte Programming Operation

Sector Erase Operation (Note 1)

V^CCSetup Time

1

—

Rise Time to V^ID(Note 2)

—

Voltage Transition Time (Note 2)

Write Pulse Width (Note 2)

—

100

4

—

OE Setup Time to WE Active (Note 2)

CE Setup Time to WE Active (Note 2)

Recover Time from RY/BY

—

4

—

0

—

t^RP

RESET Pulse Width

500

200

—

30

—

t^RH

RESET Hold Time Before Read

Delay Time from Embedded Output Enable

Program/Erase Valid to RY/BY Delay

BYTE Switching Low to Output High-Z

BYTE Switching High to Output Active

—

t^EOE

t^BUSY

t^FLQZ

t^FLQV

—

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Protection operation.

14

MB84VB2000^-10/MB84VB2001^-10

■ SWITCHING WAVEFORMS

CE¹

CE²

t^CCR

Figure 1 Timing Diagram for Alternating Flash to Flash

15

MB84VB2000^-10/MB84VB2001^-10

t^RC

Addresses

Addresses Stable

t^ACC

CE

OE

t^OE

t^DF

t^OEH

WE

DQ

t^CE

HIGH-Z

Output Valid

t^RC

Addresses

Addresses Stable

t^ACC

t^RH

RESET

DQ

t^OH

HIGH-Z

Output Valid

Figure 2 AC Waveforms for Read Operations

16

MB84VB2000^-10/MB84VB2001^-10

Data Polling

3rd Bus Cycle

555H

Data Polling

Addresses

PA

t

WC

t

RC

t

AS

t

AH

CE

t

CH

t

CS

t

CE

OE

t

WP

t

WPH

t

OE

t

GHWL

t

WHWH1

WE

t

OH

t

DS

t

DH

A0H

PD

DQ

7

D

OUT

DOUT

DQ⁷

Data

Notes: 1.PA is address of the memory location to be programmed.

2.PD is data to be programmed at byte address.

3.DQ⁷is the output of the complement of the data written to the device.

4.D^OUTis the output of the data written to the device.

5.Figure indicates last two bus cycles out of four bus cycle sequence.

6.These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 3 Alternate WE Controlled Program Operation Timings

17

MB84VB2000^-10/MB84VB2001^-10

Data Polling

3rd Bus Cycle

Addresses

PA

555H

tWC

tAS

tAH

WE

tWS

tWH

OE

tGHEL

tCP

tCPH

tWHWH1

CE

tDS

tDH

DQ⁷

DQ7

A0H

PD

D^OUT

Data

Notes: 1.PA is address of the memory location to be programmed.

2.PD is data to be programmed at byte address.

3.DQ⁷is the output of the complement of the data written to the device.

4.D^OUTis the output of the data written to the device.

5.Figure indicates last two bus cycles out of four bus cycle sequence.

6.These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 4 Alternate CE Controlled Program Operation Timings

18

MB84VB2000^-10/MB84VB2001^-10

2AAH

555H

Addresses

555H

2AAH

SA*

tWC

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

10H/

30H

AAH

55H

80H

AAH

55H

Data

tVCS

VCC

* : SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte)

for Chip Erase.

Note: These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)

Figure 5 AC Waveforms Chip/Sector Erase Operations

19

MB84VB2000^-10/MB84VB2001^-10

CE

tCH

tOE

tDF

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

DQ⁷

DQ7

Valid Data

tWHWH1 or 2

DQ0 to DQ6

Valid Data

DQ0 to DQ6

DQ⁰to DQ6 = Output Flag

tEOE

* : DQ⁷= Valid Data (The device has completed the Embedded operation.)

Figure 6 AC Waveforms for Data Polling during Embedded Algorithm Operations

CE

t

OEH

WE

t

OES

OE

*

DQ

6

=

DQ

6

Data

DQ

6

= Toggle

DQ

6

= Toggle

Valid

Stop Toggling

t

OE

* : DQ⁶stops toggling.(The device has completed the Embedded operation.)

Figure 7 AC Waveforms for Toggle Bit during Embedded Algorithm Operations

20

MB84VB2000^-10/MB84VB2001^-10

CE

TThheerriissiinnggeeddggeeoofftthheellaassttWWEEssiiggnnaall

WE

Entire programming

or erase operations

RY/BY

tBUSY

Figure 8 RY/BY Timing Diagram during Write/Erase Operations

WE

RESET

tRP

tRB

RY/BY

tREADY

Figure 9 RESET, RY/BY Timing Diagram

21

MB84VB2000^-10/MB84VB2001^-10

CE

BYTE

Data Output

(DQ⁰to DQ⁷)

Data Output

(DQ⁰to DQ¹⁴)

DQ⁰to DQ¹⁴

t^ELFH

t^FHQV

DQ¹⁵

DQ¹⁵/A^-1

A^-1

Figure 10 Timing Diagram for Word Mode Configuration

CE

BYTE

t^ELFL

DQ⁰to DQ¹⁴

Data Output

(DQ⁰to DQ¹⁴)

Data Output

(DQ⁰to DQ⁷)

DQ¹⁵/A^-1

DQ¹⁵

A^-1

t^FLQZ

Figure 11 Timing Diagram for Byte Mode Configuration

The falling edge of the last WE signal

CE or WE

Input

Valid

BYTE

t^SET

(t^AS)

t^HOLD

(t^AH)

Figure 12 BYTE Timing Diagram for Write Operations

22

MB84VB2000^-10/MB84VB2001^-10

A

18, A17, A16

SAX

SAY

A

15, A14

13, A12

A

0

A

1

6

12 V

3 V

A

9

t

VLHT

12 V

3 V

OE

VLHT

t

VLHT

t

VLHT

t

WPP

WE

t

OESP

t

CSP

CE

Data

01H

t

VCS

t

OE

V

CC

SAX : Sector Address for initial sector

SAY : Sector Address for next sector

Note: A^-1is V^ILon byte mode.

Figure 13 AC Waveforms for Sector Protection Timing Diagram

23

MB84VB2000^-10/MB84VB2001^-10

FAST MODE ALGORITHM

Start

RESET = V^ID

Wait to 4 µs

Device is Operating in

Temporary Sector

Unprotection Mode

No

Extended Sector

Protection Entry?

Yes

To Setup Sector Protection

Write XXXH/60H

PLSCNT = 1

To Sector Protection

Write SPA/60H

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Time Out 150 µs

Increment PLSCNT

To Verify Sector Protection

Write SPA/40H

Setup Next Sector Address

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Read from Sector Address

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

No

Data = 01H?

Yes

PLSCNT = 25?

Yes

Remove V^IDfrom RESET

Write Reset Command

Protection Other Sector

?

No

Remove V^IDfrom RESET

Write Reset Command

Device Failed

Sector Protection

Completed

Figure 14 Extended Sector Protection Algorithm

24

MB84VB2000^-10/MB84VB2001^-10

VCC

t

VIDR

t

VLHT

t

VCS

12 V

3 V

RESET

CE

WE

t

VLHT

t

VLHT

Program or Erase Command Sequence

RY/BY

Figure 15 Temporary Sector Unprotection Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ

6

2

Toggle

DQ2 and DQ6

DQ

2

and DQ

6

with OE

Note: DQ²is read from the erase-suspended sector.

Figure 16 DQ²vs DQ⁶

25

MB84VB2000^-10/MB84VB2001^-10

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1

15

sec

Word Programming Time

Byte Programming Time

—

16

8

5,200

3,600

µs

Excludes system-level

overhead

Chip Programming Time

(1M Byte)

Excludes system-level

overhead

—

8.4

—

50

—

sec

Erase/Program Cycle

100,000

cycles

■ PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

C^IN

Input Capacitance

V^IN= 0

V^OUT= 0

V^IN= 0

TBD

pF

C^OUT

Output Capacitance

Control Pin Capacitance

C^IN2

Note: Test conditions T^A= 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please hadle this package carefully since the sides of package are right angle.

26

MB84VB2000^-10/MB84VB2001^-10

■ PACKAGE

48-pin plastic FBGA

(BGA-48P-M06)

■ PACKAGE DIMENSIONS

48-pin plastic BGA

(BGA-48P-M06)

Note: The actual shape of corners may differ from the dimension.

11.00±0.15(.433±.006)

1.40±0.20

7.00±0.15(.276±.006)

(.055±.008)

0.30±0.10

(.012±.004)

Ø0.40±0.10

(Ø.016±.004)

10.00±0.15

(.394±.006)

5.00±0.15

(.197±.006)

0.15(.006)

1st PIN

INDEX

1.00±0.15

(.039±.006)

Dimension in mm (inches).

C

1998 FUJITSU LIMITED MCM-M001-2-3

27

MB84VB2000^-10/MB84VB2001^-10

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: (044) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: (044) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document presented

as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the

use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9804

FUJITSU LIMITED Printed in Japan

28


型号：	MB84VB2000-10
厂家：	FUJITSU
描述：	8M (x 8/x 16) FLASH MEMORY & 8M (x 8/x 16) FLASH MEMORY 8M （ ×8 / ×16 ）Flash存储器和8M （ ×8 / ×16 ）Flash存储器存储
文件：	总28页 (文件大小：295K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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