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MB84VD2118XA [FUJITSU]

16M ( x 8/ x 16) FLASH MEMORY & 4M ( x 8/ x 16) STATIC RAM; 16M （ ×8 / ×16 ）Flash存储器和4M （ ×8 / ×16 ）静态RAM
MB84VD2118XA
型号： MB84VD2118XA
厂家： FUJITSU    FUJITSU
描述：

16M ( x 8/ x 16) FLASH MEMORY & 4M ( x 8/ x 16) STATIC RAM
16M （ ×8 / ×16 ）Flash存储器和4M （ ×8 / ×16 ）静态RAM

存储
文件： 总55页 (文件大小：833K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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FUJITSU SEMICONDUCTOR  
DATA SHEET  
DS05-50202-2E  
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM  
CMOS  
16M ( × 8/ × 16) FLASH MEMORY &  
4M ( × 8/ × 16) STATIC RAM  
MB84VD2118XA-85/MB84VD2119XA-85  
■ FEATURES  
• Power supply voltage of 2.7 to 3.6 V  
• High performance  
85 ns maximum access time  
• Operating Temperature  
−25 to +85 °C  
• Package 69-ball FBGA, 56-pin TSOP(I)  
(Continued)  
■ PRODUCT LINE UP  
Flash Memory  
SRAM  
+0.6 V  
VCCf, VCCs = 3.0 V  
−0.3 V  
Ordering Part No.  
MB84VD2118XA-85/MB84VD2119XA-85  
Max. Address Access Time (ns)  
Max. CE Access Time (ns)  
Max. OE Access Time (ns)  
85  
85  
35  
85  
85  
45  
■ PACKAGES  
69-ball plastic FBGA  
56-pin plastic TSOP(I)  
(BGA-69P-M02)  
(FPT-56P-M04)  
MB84VD2118XA-85/MB84VD2119XA-85  
(Continued)  
1. FLASH MEMORY  
• Simultaneous Read/Write operations (dual bank)  
Miltiple devices available with different bank sizes (Refer to “PIN DESCRIPTION”)  
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank  
Zero latency between read and write operations  
Read-while-erase  
Read-while-program  
• Minimum 100,000 write/erase cycles  
• Sector erase architecture  
Eight 4 K words and thirty one 32 K words.  
Any combination of sectors can be concurrently erased. Also supports full chip erase.  
• Boot Code Sector Architecture  
MB84VD2118XA : Top sector  
MB84VD2119XA : Bottom sector  
• Embedded EraseTM* Algorithms  
Automatically pre-programs and erases the chip or any sector  
• Embedded ProgramTM* Algorithms  
Automatically writes and verifies data at specified address  
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion  
• Ready-Busy output (RY/BY)  
Hardware method for detection of program or erase cycle completion  
• Automatic sleep mode  
When addresses remain stable, automatically switch themselves to low power mode.  
• Low VCCf write inhibit ≤ 2.5 V  
• Hidden ROM (Hi-ROM) region  
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence  
Factory serialized and protected to provide a secure electronic serial number (ESN)  
• WP/ACC input pin  
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status  
(MB84VD2118XA : SA37, SA38 MB84VD2119XA : SA0, SA1)  
At VIH, allows removal of boot sector protection  
At VACC, program time will reduse by 40%.  
• Erase Suspend/Resume  
Suspends the erase operation to allow a read in another sector within the same device  
• Please refer to “MBM29DL16XTD/BD” data sheet in detailed function  
2. SRAM  
• Power dissipation  
Operating : 40 mA max.  
Standby : 7 µA max.  
• Power down features using CE1s and CE2s  
• Data retention supply voltage : 1.5 V to 3.6 V  
• CE1s and CE2s Chip Select  
• Byte data control : LBs (DQ0 to DQ7) , UBs (DQ8 to DQ15)  
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.  
2
MB84VD2118XA-85/MB84VD2119XA-85  
■ PIN ASSIGNMENTS  
(Top View)  
N.C.  
N.C.  
WE  
N.C.  
N.C.  
N.C.  
A
B
WP/  
ACC  
LBS  
UBS  
A18  
A8  
A19  
A11  
A12  
A13  
A14  
SA  
A7  
A6  
RESET  
RY/BY  
A15  
N.C.  
N.C.  
A16  
A3  
A2  
C
D
E
F
CE2S  
N.C.  
A5  
A9  
A1  
A4  
N.C.  
N.C.  
N.C.  
N.C.  
A17  
A10  
A0  
VSS  
OE  
DQ0  
DQ8  
DQ1  
DQ9  
DQ10  
DQ2  
DQ6  
DQ13  
DQ12  
DQ5  
DQ15/  
A−1  
CIOf  
VSS  
CEf  
CE1S  
DQ3  
VCCf  
DQ11  
DQ4  
VCCs  
CIOS  
G
DQ7  
H
J
DQ14  
N.C.  
1
N.C.  
5
N.C.  
6
N.C.  
10  
K
2
3
4
7
8
9
69-ball FBGA  
3
MB84VD2118XA-85/MB84VD2119XA-85  
(Top View)  
N.C.  
A15  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
A16  
2
CIOf  
VSS  
A14  
3
A13  
4
SA  
A12  
5
DQ15/A-1  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
CIOs  
VCCs  
VCCf  
DQ11  
DQ3  
DQ10  
DQ2  
DQ9  
DQ1  
DQ8  
DQ0  
OE  
A11  
6
A10  
7
A9  
8
A8  
9
A19  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
N.C.  
WE  
CE2s  
RESET  
WP/ACC  
RY/BY  
UBs  
LBs  
A18  
A17  
A7  
A6  
A5  
A4  
A3  
VSS  
A2  
CE1s  
CEf  
A1  
N.C.  
A0  
56-pin TSOP(I)  
4
MB84VD2118XA-85/MB84VD2119XA-85  
■ PIN DESCRIPTION  
Pin  
Function  
Input/Output  
A0 to A17  
A-1, A18, A19  
SA  
Address Inputs (Common)  
I
Address Input (Flash)  
Address Input (SRAM)  
I
I
DQ0 to DQ15  
CEf  
Data Inputs/Outputs (Common)  
Chip Enable (Flash)  
I/O  
I
I
CE1s  
Chip Enable (SRAM)  
CE2s  
Chip Enable (SRAM)  
I
OE  
Output Enable (Common)  
Write Enable (Common)  
I
WE  
I
RY/BY  
UBs  
Ready/Busy Outputs (Flash) Open Drain Output  
Upper Byte Control (SRAM)  
Lower Byte Control (SRAM)  
O
I
LBs  
I
I/O Configuration (Flash)  
CIOf = VIH is Word mode ( × 16), CIOf = VIL is Byte mode ( × 8)  
CIOf  
I
I
I/O Configuration (SRAM)  
CIOs = VIH is Word mode ( × 16), CIOs = VIL is Byte mode ( × 8)  
CIOs  
RESET  
WP/ACC  
N.C.  
Hardware Reset Pin/Sector Protection Unlock (Flash)  
Write Protect / Acceleration (Flash)  
No Internal Connection  
I
I
VSS  
Device Ground (Common)  
Power  
Power  
Power  
VCCf  
Device Power Supply (Flash)  
VCCs  
Device Power Supply (SRAM)  
5
MB84VD2118XA-85/MB84VD2119XA-85  
■ BLOCK DIAGRAM  
VCCf  
VSS  
A0 to A19  
RY/BY  
A0 to A19  
A-1  
WP/ACC  
RESET  
CEf  
16 M bit  
Flash Memory  
DQ0 to DQ15/A-1  
CIOf  
DQ0 to DQ15/A-1  
VCCs  
VSS  
A0 to A17  
DQ0 to DQ15/A-1  
4 M bit  
Static RAM  
SA  
LBs  
UBs  
WE  
OE  
CE1s  
CE2s  
CIOs  
6
MB84VD2118XA-85/MB84VD2119XA-85  
■ DEVICE BUS OPERATIONS  
Table 2.1 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs)  
WP/  
RESET ACC  
(Note5)  
Operation  
(Note 1, 3)  
SA  
(Note6)  
DQ0 to  
DQ7  
DQ8 to  
DQ15  
CEf CE1s CE2s OE WE  
LBs UBs  
H
X
X
L
Full Standby  
H
H
L
X
X
X
X
X
HIGH-Z HIGH-Z  
H
X
H
X
H
X
X
X
X
H
X
H
HIGH-Z HIGH-Z  
HIGH-Z HIGH-Z  
L
H
Output Disable  
H
X
H
X
H
X
H
X
X
L
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
Read from Flash  
(Note 2)  
L
DOUT  
DOUT  
DIN  
H
H
X
X
Write to Flash  
L
H
DIN  
L
H
L
L
L
DOUT  
HIGH-Z  
DOUT  
DOUT  
DOUT  
Read from SRAM  
H
H
X
L
L
X
H
H
X
L
X
X
H
L
X
X
X
H
H
X
X
X
H
L
HIGH-Z  
DIN  
L
DIN  
Write to SRAM  
H
L
L
HIGH-Z  
DIN  
DIN  
H
HIGH-Z  
Temporary Sector  
Group  
Unprotection  
(Note 4)  
X
X
X
X
X
VID  
H
X
X
L
Flash Hardware  
Reset  
X
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
L
X
L
Boot Block Sector  
Write Protection  
X
X
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for  
voltage levels.  
Notes : 1. Other operations except for indicated this column are inhibited.  
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.  
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.  
4. It is also used for the extended sector group protections.  
5. WP/ACC = VIL ; protection of boot sectors.  
WP/ACC = VIH ; removal of boot sectors protection.  
WP/ACC = VACC (9V) ; Program time will reduce by 40%.  
6. SA ; Don’t care or Open.  
7
MB84VD2118XA-85/MB84VD2119XA-85  
Table 2.2 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS)  
WP/  
RESET ACC  
(Note5)  
Operation  
(Note 1, 3)  
LBs  
UBs  
DQ0 to DQ8 to  
DQ7 DQ15  
CEf CE1s CE2s OE WE SA  
(Note6) (Note6)  
H
X
X
L
Full Standby  
H
H
L
X
X
X
X
X
HIGH-Z HIGH-Z  
H
X
H
X
H
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
HIGH-Z HIGH-Z  
L
H
Output Disable  
H
X
H
X
H
X
H
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
X
L
Read from Flash  
(Note 2)  
L
DOUT  
DOUT  
DIN  
H
H
X
X
X
L
Write to Flash  
L
H
DIN  
Read from SRAM  
Write to SRAM  
H
H
H
H
L
H
L
SA  
SA  
X
X
X
X
DOUT  
HIGH-Z  
HIGH-Z  
H
H
X
X
L
X
DIN  
Temporary Sector  
Group  
Unprotection  
(Note 4)  
X
X
X
X
X
X
X
X
X
X
VID  
X
H
X
X
L
Flash Hardware  
Reset  
X
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
L
X
L
Boot Block Sector  
Write Protection  
X
X
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for  
voltage levels.  
Notes : 1. Other operations except for indicated this column are inhibited.  
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.  
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.  
4. It is also used for the extended sector group protections.  
5. WP/ACC = VIL ; protection of boot sectors.  
WP/ACC = VIH ; removal of boot sectors protection.  
WP/ACC = VACC (9V) ; Program time will reduce by 40%.  
6. LBS , UBS ; Don’t care or Open.  
8
MB84VD2118XA-85/MB84VD2119XA-85  
Table 2.3 User Bus Operations (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS)  
WP/  
DQ1/  
A-1  
LBs  
UBs  
DQ0 to DQ8 to  
Operation  
(Note 1, 3)  
CEf CE1s CE2s  
OE WE SA  
RESET ACC  
(Note5)  
(Note6) (Note6)  
DQ7  
DQ14  
H
X
X
L
Full Standby  
H
H
L
X
X
X
X
X
X
HIGH-Z HIGH-Z  
H
X
X
X
X
H
X
H
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
HIGH-Z HIGH-Z  
L
H
Output  
Disable  
H
H
X
H
X
L
A-1  
A-1  
A-1  
H
L
H
H
L
X
X
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
Read from  
Flash  
(Note 2)  
X
L
L
DOUT  
DIN  
X
X
H
H
X
X
X
L
H
X
X
L
Write to  
Flash  
H
Read from  
SRAM  
H
H
L
L
H
H
X
X
L
H
L
SA  
SA  
X
X
X
X
DOUT  
HIGH-Z  
HIGH-Z  
H
H
X
X
Write to  
SRAM  
X
DIN  
Temporary  
Sector Group  
Unprotection  
(Note 4)  
X
X
X
X
X
X
X
X
X
X
X
VID  
X
Flash  
Hardware  
Reset  
H
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z HIGH-Z  
L
X
L
Boot Block  
Sector Write  
Protection  
X
X
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See “ELECTRICAL CHARACTERISTICS 1. DC Characteristics” for  
voltage levels.  
Notes : 1. Other operations except for indicated this column are inhibited.  
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.  
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.  
4. It is also used for the extended sector group protections.  
5. WP/ACC = VIL ; protection of boot sectors.  
WP/ACC = VIH ; removal of boot sectors protection.  
WP/ACC = VACC (9V) ; Program time will reduce by 40%.  
6. LBS, UBS ; Don’t care or Open.  
9
MB84VD2118XA-85/MB84VD2119XA-85  
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY  
• Eight 4 K words, and thirty one 32 K words.  
• Individual-sector, multiple-sector, or bulk-erase capability.  
Word mode Byte mode  
0FFFFFH 1FFFFFH  
0FF000H 1FE000H  
0FE000H 1FC000H  
0FD000H 1FA000H  
0FC000H 1F8000H  
SA38:  
SA37:  
SA36:  
SA35:  
SA34:  
SA33:  
SA32:  
SA31:  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
Bank 1  
MB84VD21181A  
0FB000H  
0FA000H  
0F9000H  
0F8000H  
0F0000H  
1F6000H  
1F4000H  
1F2000H  
1F0000H  
1E0000H  
Bank 1  
MB84VD21182A  
SA30: 64KB (32KW)  
SA29: 64KB (32KW)  
SA28: 64KB (32KW)  
SA27: 64KB (32KW)  
SA26: 64KB (32KW)  
SA25: 64KB (32KW)  
SA24: 64KB (32KW)  
SA23: 64KB (32KW)  
SA22: 64KB (32KW)  
SA21: 64KB (32KW)  
SA20: 64KB (32KW)  
SA19: 64KB (32KW)  
SA18: 64KB (32KW)  
SA17: 64KB (32KW)  
SA16: 64KB (32KW)  
SA15: 64KB (32KW)  
SA14: 64KB (32KW)  
SA13: 64KB (32KW)  
SA12: 64KB (32KW)  
SA11: 64KB (32KW)  
SA10: 64KB (32KW)  
SA9 : 64KB (32KW)  
SA8 : 64KB (32KW)  
SA7 : 64KB (32KW)  
SA6 : 64KB (32KW)  
SA5 : 64KB (32KW)  
SA4 : 64KB (32KW)  
SA3 : 64KB (32KW)  
SA2 : 64KB (32KW)  
SA1 : 64KB (32KW)  
SA0 : 64KB (32KW)  
Bank 1  
MB84VD21183A  
0E8000H 1D0000H  
0E0000H 1C0000H  
0D8000H 1B0000H  
0D0000H 1A0000H  
Bank 1  
MB84VD21184A  
0C8000H  
0C0000H  
0B8000H  
0B0000H  
0A8000H  
0A0000H  
098000H  
090000H  
088000H  
080000H  
078000H  
070000H  
068000H  
060000H  
058000H  
050000H  
048000H  
040000H  
038000H  
030000H  
028000H  
020000H  
018000H  
010000H  
008000H  
000000H  
190000H  
180000H  
170000H  
160000H  
150000H  
140000H  
130000H  
120000H  
110000H  
100000H  
0F0000H  
0E0000H  
0D0000H  
0C0000H  
0B0000H  
0A0000H  
090000H  
080000H  
070000H  
060000H  
050000H  
040000H  
030000H  
020000H  
010000H  
000000H  
Bank 2  
MB84VD21181A  
Bank 2  
MB84VD21182A  
Bank 2  
MB84VD21183A  
Bank 2  
MB84VD21184A  
MB84VD2118XA Sector Architecture (Top Boot Block)  
10  
MB84VD2118XA-85/MB84VD2119XA-85  
• Eight 4 K words, and thirty one 32 K words.  
• Individual-sector, multiple-sector, or bulk-erase capability.  
Word mode Byte mode  
0FFFFFH 1FFFFFH  
SA38: 64KB (32KW)  
0F8000H  
0F0000H  
1F0000H  
1E0000H  
SA37: 64KB (32KW)  
SA36: 64KB (32KW)  
SA35: 64KB (32KW)  
SA34: 64KB (32KW)  
SA33: 64KB (32KW)  
SA32: 64KB (32KW)  
SA31: 64KB (32KW)  
SA30: 64KB (32KW)  
SA29: 64KB (32KW)  
SA28: 64KB (32KW)  
SA27: 64KB (32KW)  
SA26: 64KB (32KW)  
SA25: 64KB (32KW)  
SA24: 64KB (32KW)  
SA23: 64KB (32KW)  
SA22: 64KB (32KW)  
SA21: 64KB (32KW)  
SA20: 64KB (32KW)  
SA19: 64KB (32KW)  
SA18: 64KB (32KW)  
SA17: 64KB (32KW)  
SA16: 64KB (32KW)  
SA15: 64KB (32KW)  
SA14: 64KB (32KW)  
SA13: 64KB (32KW)  
SA12: 64KB (32KW)  
SA11: 64KB (32KW)  
SA10: 64KB (32KW)  
SA9 : 64KB (32KW)  
SA8 : 64KB (32KW)  
0E8000H 1D0000H  
0E0000H 1C0000H  
0D8000H 1B0000H  
0D0000H 1A0000H  
Bank 2  
MB84VD21194A  
Bank 2  
0C8000H  
0C0000H  
0B8000H  
0B0000H  
0A8000H  
0A0000H  
098000H  
090000H  
088000H  
080000H  
078000H  
070000H  
068000H  
060000H  
058000H  
050000H  
048000H  
040000H  
038000H  
030000H  
028000H  
020000H  
018000H  
010000H  
008000H  
007000H  
006000H  
005000H  
004000H  
003000H  
002000H  
001000H  
000000H  
190000H  
180000H  
170000H  
160000H  
150000H  
140000H  
130000H  
120000H  
110000H  
100000H  
0F0000H  
0E0000H  
0D0000H  
0C0000H  
0B0000H  
0A0000H  
090000H  
080000H  
070000H  
060000H  
050000H  
040000H  
030000H  
020000H  
010000H  
00E000H  
00C000H  
00A000H  
008000H  
006000H  
004000H  
002000H  
000000H  
MB84VD21193A  
Bank 2  
MB84VD21192A  
Bank 2  
MB84VD21191A  
Bank 1  
MB84VD21194A  
Bank 1  
MB84VD21193A  
SA7 :  
SA6 :  
SA5 :  
SA4 :  
SA3 :  
SA2 :  
SA1 :  
SA0 :  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
8KB (4KW)  
Bank 1  
MB84VD21192A  
Bank 1  
MB84VD21191A  
MB84VD2119XA Sector Architecture (Bottom Boot Block)  
11  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.1 Sector Address Tables (MB84VD21181)  
Sector Address  
Address Range  
(Byte mode)  
Address Range  
(Word mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0  
SA1  
000000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
Bank 2  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
1F0000H to 1F1FFFH  
1F2000H to 1F3FFFH  
0F8000H to 0F8FFFH  
0F9000H to 0F9FFFH  
0
0
1
0
1
0
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH  
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH  
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH  
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH  
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH  
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH  
0
1
1
Bank 1  
1
0
0
1
0
1
1
1
0
1
1
1
12  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.2 Sector Address Tables (MB84VD21191)  
Sector Address  
Address Range  
(BYTE mode)  
Address Range  
(WORD mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16  
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15  
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14  
0
A13  
0
A12  
0
SA0  
SA1  
000000H to 001FFFH  
002000H to 003FFFH  
004000H to 005FFFH  
006000H to 007FFFH  
008000H to 009FFFH  
00A000H to 00BFFFH  
00C000H to 00DFFFH  
00E000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 000FFFH  
001000H to 001FFFH  
002000H to 002FFFH  
003000H to 003FFFH  
004000H to 004FFFH  
005000H to 005FFFH  
006000H to 006FFFH  
007000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
0
0
1
SA2  
0
1
0
SA3  
0
1
1
Bank 1  
SA4  
1
0
0
SA5  
1
0
1
SA6  
1
1
0
SA7  
1
1
1
SA8  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
Bank 2  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
1F0000H to 1FFFFFH  
0F8000H to 0FFFFFH  
13  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.3 Sector Address Tables (MB84VD21182)  
Sector Address  
Address Range  
(BYTE mode)  
Address Range  
(WORD mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0  
SA1  
000000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
Bank 2  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
1F0000H to 1F1FFFH  
1F2000H to 1F3FFFH  
0F8000H to 0F8FFFH  
0F9000H to 0F9FFFH  
0
0
1
0
1
0
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH  
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH  
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH  
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH  
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH  
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH  
Bank 1  
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
14  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.4 Sector Address Tables (MB84VD21192)  
Sector Address  
Address Range  
(BYTE mode)  
Address Range  
(WORD mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16  
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15  
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14  
0
A13  
0
A12  
0
SA0  
SA1  
000000H to 001FFFH  
002000H to 003FFFH  
004000H to 005FFFH  
006000H to 007FFFH  
008000H to 009FFFH  
00A000H to 00BFFFH  
00C000H to 00DFFFH  
00E000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 000FFFH  
001000H to 001FFFH  
002000H to 002FFFH  
003000H to 003FFFH  
004000H to 004FFFH  
005000H to 005FFFH  
006000H to 006FFFH  
007000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
0
0
1
SA2  
0
1
0
SA3  
0
1
1
SA4  
1
0
0
SA5  
1
0
1
Bank 1  
SA6  
1
1
0
SA7  
1
1
1
SA8  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
Bank 2  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
1F0000H to 1FFFFFH  
0F8000H to 0FFFFFH  
15  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.5 Sector Address Tables (MB84VD21183)  
Sector Address  
Address Range  
(BYTE mode)  
Address Range  
(WORD mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0  
SA1  
000000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
Bank 2  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
1F0000H to 1F1FFFH  
1F2000H to 1F3FFFH  
0F8000H to 0F8FFFH  
0F9000H to 0F9FFFH  
Bank 1  
0
0
1
0
1
0
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH  
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH  
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH  
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH  
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH  
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH  
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
16  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.6 Sector Address Tables (MB84VD21193)  
Sector Address  
Address Range  
(BYTE mode)  
Address Range  
(WORD mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16  
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15  
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14  
0
A13  
0
A12  
0
SA0  
SA1  
000000H to 001FFFH  
002000H to 003FFFH  
004000H to 005FFFH  
006000H to 007FFFH  
008000H to 009FFFH  
00A000H to 00BFFFH  
00C000H to 00DFFFH  
00E000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 000FFFH  
001000H to 001FFFH  
002000H to 002FFFH  
003000H to 003FFFH  
004000H to 004FFFH  
005000H to 005FFFH  
006000H to 006FFFH  
007000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
0
0
1
SA2  
0
1
0
SA3  
0
1
1
SA4  
1
0
0
SA5  
1
0
1
SA6  
1
1
0
SA7  
1
1
1
Bank 1  
SA8  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
Bank 2  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
1F0000H to 1FFFFFH  
0F8000H to 0FFFFFH  
17  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.7 Sector Address Tables (MB84VD21184)  
Sector Address  
Address Range  
(BYTE mode)  
Address Range  
(WORD mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA0  
SA1  
000000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
Bank 2  
SA8  
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
Bank 1  
1F0000H to 1F1FFFH  
1F2000H to 1F3FFFH  
0F8000H to 0F8FFFH  
0F9000H to 0F9FFFH  
0
0
1
0
1
0
1F4000H to 1F5FFFH 0FA000H to 0FAFFFH  
1F6000H to 1F7FFFH 0FB000H to 0FBFFFH  
1F8000H to 1F9FFFH 0FC000H to 0FCFFFH  
1FA000H to 1FBFFFH 0FD000H to 0FDFFFH  
1FC000H to 1FDFFFH 0FE000H to 0FEFFFH  
1FE000H to 1FFFFFH 0FF000H to 0FFFFFH  
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
18  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 3.8 Sector Address Tables (MB84VD21194)  
Sector Address  
Address Range  
(BYTE mode)  
Address Range  
(WORD mode)  
Bank  
Sector  
Bank Address  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16  
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15  
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14  
0
A13  
0
A12  
0
SA0  
SA1  
000000H to 001FFFH  
002000H to 003FFFH  
004000H to 005FFFH  
006000H to 007FFFH  
008000H to 009FFFH  
00A000H to 00BFFFH  
00C000H to 00DFFFH  
00E000H to 00FFFFH  
010000H to 01FFFFH  
020000H to 02FFFFH  
030000H to 03FFFFH  
040000H to 04FFFFH  
050000H to 05FFFFH  
060000H to 06FFFFH  
070000H to 07FFFFH  
080000H to 08FFFFH  
090000H to 09FFFFH  
0A0000H to 0AFFFFH  
0B0000H to 0BFFFFH  
000000H to 000FFFH  
001000H to 001FFFH  
002000H to 002FFFH  
003000H to 003FFFH  
004000H to 004FFFH  
005000H to 005FFFH  
006000H to 006FFFH  
007000H to 007FFFH  
008000H to 00FFFFH  
010000H to 017FFFH  
018000H to 01FFFFH  
020000H to 027FFFH  
028000H to 02FFFFH  
030000H to 037FFFH  
038000H to 03FFFFH  
040000H to 047FFFH  
048000H to 04FFFFH  
050000H to 057FFFH  
058000H to 05FFFFH  
0
0
1
SA2  
0
1
0
SA3  
0
1
1
SA4  
1
0
0
SA5  
1
0
1
SA6  
1
1
0
SA7  
1
1
1
SA8  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9  
SA10  
SA11  
SA12  
SA13  
SA14  
SA15  
SA16  
SA17  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
SA24  
SA25  
SA26  
SA27  
SA28  
SA29  
SA30  
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
Bank 1  
0C0000H to 0CFFFFH 060000H to 067FFFH  
0D0000H to 0DFFFFH 068000H to 06FFFFH  
0E0000H to 0EFFFFH  
0F0000H to 0FFFFFH  
100000H to 10FFFFH  
110000H to 11FFFFH  
120000H to 12FFFFH  
130000H to 13FFFFH  
140000H to 14FFFFH  
150000H to 15FFFFH  
160000H to 16FFFFH  
170000H to 17FFFFH  
070000H to 077FFFH  
078000H to 07FFFFH  
080000H to 087FFFH  
088000H to 08FFFFH  
090000H to 097FFFH  
098000H to 09FFFFH  
0A0000H to 0A7FFFH  
0A8000H to 0AFFFFH  
0B0000H to 0B7FFFH  
0B8000H to 0BFFFFH  
Bank 2  
180000H to 18FFFFH 0C0000H to 0C7FFFH  
190000H to 19FFFFH 0C8000H to 0CFFFFH  
1A0000H to 1AFFFFH 0D0000H to 0D7FFFH  
1B0000H to 1BFFFFH 0D8000H to 0DFFFFH  
1C0000H to 1CFFFFH 0E0000H to 0E7FFFH  
1D0000H to 1DFFFFH 0E8000H to 0EFFFFH  
1E0000H to 1EFFFFH 0F0000H to 0F7FFFH  
1F0000H to 1FFFFFH  
0F8000H to 0FFFFFH  
19  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 4.1 Sector Group Addresses (MB84VD2118XA)  
(Top Boot Block)  
Sector Group  
A19  
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18  
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
A17  
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
A16  
0
A15  
0
A14  
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13  
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12  
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Sectors  
SGA0  
SA0  
0
1
SGA1  
1
0
SA1 to SA3  
1
1
SGA2  
SGA3  
SGA4  
SGA5  
SGA6  
SGA7  
X
X
X
X
X
X
0
X
X
X
X
X
X
0
SA4 to SA7  
SA8 to SA11  
SA12 to SA15  
SA16 to SA19  
SA20 to SA23  
SA24 to SA27  
SGA8  
0
1
SA28 to SA30  
1
0
SGA9  
SGA10  
SGA11  
SGA12  
SGA13  
SGA14  
SGA15  
SGA16  
1
1
SA31  
SA32  
SA33  
SA34  
SA35  
SA36  
SA37  
SA38  
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
20  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 4.2 Sector Group Addresses (MB84VD2119XA)  
(Bottom Boot Block)  
Sector Group  
SGA0  
A19  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A18  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
A17  
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
A16  
0
A15  
0
A14  
0
A13  
0
A12  
0
Sectors  
SA0  
SGA1  
0
0
0
0
1
SA1  
SGA2  
0
0
0
1
0
SA2  
SGA3  
0
0
0
1
1
SA3  
SGA4  
0
0
1
0
0
SA4  
SGA5  
0
0
1
0
1
SA5  
SGA6  
0
0
1
1
0
SA6  
SGA7  
0
0
1
1
1
SA7  
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SGA8  
1
0
SA8 to SA10  
1
1
SGA9  
SGA10  
SGA11  
SGA12  
SGA13  
SGA14  
X
X
X
X
X
X
0
X
X
X
X
X
X
0
SA11 to SA14  
SA15 to SA18  
SA19 to SA22  
SA23 to SA26  
SA27 to SA30  
SA31 to SA34  
SGA15  
SGA16  
0
1
SA35 to SA37  
SA38  
1
0
1
1
21  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 5 Flash Memory Autoselect Codes  
Type  
Manufacturer’s Code  
A12 to A19  
A6  
A1  
A0  
A-1*1  
VIL  
VIL  
X
Code (HEX)  
04H  
X
VIL  
VIL  
VIL  
Byte  
Word  
Byte  
36H  
MB84VD21181A  
MB84VD21191A  
MB84VD21182A  
MB84VD21192A  
MB84VD21183A  
MB84VD21193A  
MB84VD21184A  
MB84VD21194A  
X
X
X
X
X
X
X
X
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIL  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
VIH  
2236H  
39  
VIL  
X
Word  
Byte  
2239H  
2D  
VIL  
X
Word  
Byte  
222DH  
2E  
VIL  
X
Word  
Byte  
222EH  
28H  
Device  
Code  
VIL  
X
Word  
Byte  
2228H  
2BH  
VIL  
X
Word  
Byte  
222BH  
33H  
VIL  
X
Word  
Byte  
2233H  
35  
VIL  
X
VIL  
VIL  
VIL  
VIH  
VIH  
VIL  
Word  
2235H  
Sector Group  
Address  
Sector Group protect  
VIL  
01H*2  
*1 : A-1 is for Byte mode.  
*2 : Output 01H at protected sector address and output 00H at unprotected sector address.  
22  
MB84VD2118XA-85/MB84VD2119XA-85  
Table 6 Flash Memory Command Definitions  
Fourth Bus  
Bus  
Write  
Cycles  
Req’d  
First Bus  
Second Bus  
Write Cycle  
Third Bus  
Fifth Bus  
Sixth Bus  
Read/Write  
Cycle  
Command  
Sequence  
Write Cycle  
Write Cycle  
Write Cycle Write Cycle  
Addr. Data Addr. Data  
Addr. Data Addr. Data Addr. Data Addr. Data  
Read/Reset (Note 1)  
1
3
XXXH F0H  
Word  
555H  
2AAH  
555H  
555H  
Read/Reset  
(Note 1)  
AAH  
AAH  
55H  
55H  
F0H  
90H  
RA  
RD  
Byte  
AAAH  
AAAH  
(BA)  
555H  
Word  
555H  
2AAH  
555H  
Autoselect  
3
(BA)  
AAAH  
Byte  
AAAH  
Word  
Byte  
Word  
Byte  
Word  
Byte  
555H  
AAAH  
555H  
AAAH  
555H  
AAAH  
BA  
2AAH  
555H  
2AAH  
555H  
2AAH  
555H  
555H  
AAAH  
555H  
AAAH  
555H  
AAAH  
Program  
4
6
6
AAH  
AAH  
AAH  
55H  
55H  
55H  
A0H  
80H  
80H  
PA  
PD  
555H  
AAAH  
555H  
AAAH  
2AAH  
555H  
2AAH  
555H  
555H  
Chip Erase  
Sector Erase  
AAH  
AAH  
55H  
55H  
10H  
30H  
AAAH  
SA  
Sector Erase Suspend  
Sector Erase Resume  
1
1
B0H  
30H  
BA  
Word  
Byte  
555H  
AAAH  
2AAH  
555H  
555H  
Set to  
Fast Mode  
3
2
AAH  
55H  
PD  
20H  
AAAH  
Word  
Byte  
Fast Program  
(Note 2)  
XXXH A0H  
PA  
Reset from  
Fast Mode  
(Note 2)  
Word  
F0H  
(Note6)  
2
4
BA  
90H XXXH  
Byte  
Extended  
Sector Group  
Protection  
(Note 3)  
Word  
XXXH 60H SPA  
60H  
SPA  
40H SPA  
SD  
Byte  
Word  
Byte  
55H  
98H  
AAH  
Query  
(Note 4)  
1
3
Word  
Byte  
555H  
AAAH  
555H  
2AAH  
555H  
2AAH  
555H  
AAAH  
555H  
Hi-ROM Entry  
AAH  
AAH  
AAH  
55H  
55H  
55H  
88H  
Hi-ROM  
Program  
(Note 5)  
Word  
4
6
A0H  
80H  
PA  
PD  
Byte  
AAAH  
555H  
AAAH  
Word  
Byte  
555H  
2AAH  
555H  
555H  
555H  
2AAH  
555H  
Hi-ROM Erase  
(Note 5)  
AAH  
55H HRA 30H  
AAAH  
AAAH  
AAAH  
(HRBA)  
555H  
Word  
Byte  
555H  
2AAH  
555H  
Hi-ROM Exit  
(Note 5)  
4
AAH  
55H  
90H XXXH 00H  
(HRBA)  
AAAH  
AAAH  
23  
MB84VD2118XA-85/MB84VD2119XA-85  
Notes : 1 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.  
2 : This command is valid while Fast Mode.  
3 : This command is valid while RESET = VID.  
4 : The valid Address is A0 to A6.  
5 : This command is valid while Hi-ROM mode.  
6 : The data “00H” is also acceptable.  
Address bits A12 to A19 = X = “H” or “L” for all address commands except for Program Address (PA) ,  
Sector Address (SA) , and Bank Address (BA) .  
Bus operations are defined in Table 2 “User Bus Operations”.  
RA = Address of the memory location to be read.  
PA = Address of the memory location to be programmed.  
Addresses are latched on the falling edge of the write pulse.  
SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will  
uniquely select any sector.  
BA = Bank address (A15 to A19)  
SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0).  
HRA = Address of the Hidden-ROM area.  
SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0).  
HRA = Address of the Hidden-ROM area.  
MB84VD2118XA (Top Boot Type)  
Word mode: 0F8000H to 0FFFFFH  
Byte mode: 1F0000H to 1FFFFFH  
MB84VD2119XA (Bottom Boot Type) Word mode: 000000H to 007FFFH  
Byte mode: 000000H to 00FFFFH  
HRBA = Bank addrss of the Hidden-ROM area.  
MB84VD2118XA (Top Boot Type)  
: A15 = A16 = A17 = A18 = A19 = A20 = 1  
MB84VD2119XA (Bottom Boot Type) : A15 = A16 = A17 = A18 = A19 = A20 = 0  
RD = Data read from location RA during read operation.  
PD = Data to be programmed at location PA.  
SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H  
at unprotectedsector addresses.  
The system should generate the following address patterns;  
Word mode : 555H or 2AAH to addresses A0 to A10  
Byte mode : AAAH or 555H to addresses A -1 and A0 to A10  
24  
MB84VD2118XA-85/MB84VD2119XA-85  
■ ABSOLUTE MAXIMUM RATINGS  
Rating  
Parameter  
Symbol  
Unit  
Min.  
Max.  
Storage Temperature  
Tstg  
TA  
−55  
+125  
°C  
°C  
Ambient Temperature with Power  
Applied  
−25  
+85  
Voltage with Respect to Ground All  
pins except A9, OE, RESET,  
WP/ACC (Note 1)  
VCCf + 0.4  
VCCs + 0.4  
VIN, VOUT  
−0.3  
V
VCCf/VCCs Supply (Note 1)  
A9 and OE (Note 2)  
RESET (Note 2)  
VCCf, VCCs  
−0.3  
−0.3  
−0.5  
−0.5  
+4.0  
+13.0  
+13.0  
+10.5  
V
V
V
V
VIN  
VIN  
VIN  
WP/ACC (Note 3)  
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,  
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.  
Notes 1. Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may  
undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf  
+0.4 V or VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0  
V for periods of up to 20 ns.  
2. Minimum DC input voltage on A9 and OE pin is –0.3 V. Minimum DC input voltage on RESET pin is  
–0.5 V. During voltage transitions, A9, OE, and RESET pins may undershoot VSS to –2.0 V for periods of  
up to 20 ns.  
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V.  
Maximum DC input voltage on A9, OE, and RESET pins is +13.0 V which may overshoot to 14.0 V for  
periods of up to 20 ns.  
3. Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may  
undershoot Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5  
V which may overshoot to 12.0 V for periods of up to 20 ns, when VCCf is applied.  
■ RECOMMENDED OPERATING CONDITIONS  
Value  
Parameter  
Symbol  
Unit  
Min.  
−25  
Max.  
+85  
Ambient Temperature  
TA  
°C  
VCCf/VCCs Supply Voltages  
VCCf, VCCs  
+2.7  
+3.6  
V
Operating ranges define those limits between which the functionality of the device is guaranteed.  
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the  
semiconductor device. All of the device’s electrical characteristics are warranted when the device is  
operated within these ranges.  
Always use semiconductor devices within their recommended operating condition ranges. Operation  
outside these ranges may adversely affect reliability and could result in device failure.  
No warranty is made with respect to uses, operating conditions, or combinations not represented on  
the data sheet. Users considering application outside the listed conditions are advised to contact their  
FUJITSU representatives beforehand.  
25  
MB84VD2118XA-85/MB84VD2119XA-85  
■ ELECTRICAL CHARACTERISTICS  
1. DC Characteristics  
Parameter  
Parameter Description  
Test Conditions  
Min.  
Typ.  
Max. Unit  
Symbol  
ILI  
Input Leakage Current  
VIN = VSS to VCCf, VCCs  
−1.0  
−1.0  
+1.0  
+1.0  
µA  
µA  
ILO  
Output Leakage Current VOUT = VSS to VCCf, VCCs  
RESET Inputs Leakage  
Current  
VCCf = VCCf Max, VCCs = VCCs Max,  
RESET = 12.5V  
ILIT  
35  
20  
µA  
ACC Input Leakage  
Current  
VCCf = VCCf Max, VCCs = VCCs Max,  
WP/ACC = VACC Max  
ILIA  
mA  
tCYCLE = 5 MHz Byte  
13  
15  
7
mA  
mA  
Flash VCC Active Current  
(Read)  
(Note 1)  
tCYCLE = 5 MHz Word  
tCYCLE = 1 MHz Byte  
tCYCLE = 1 MHz Word  
CEf = VIL,  
OE = VIH  
ICC1f  
7
Flash VCC Active Current  
(Program/Erase)  
(Note 2)  
ICC2f  
ICC3f  
ICC4f  
ICC5f  
ICC1s  
ICC2s  
CEf = VIL, OE = VIH  
CEf = VIL, OE = VIH  
CEf = VIL, OE = VIH  
35  
mA  
mA  
mA  
mA  
mA  
Flash VCC Active Current  
(Read-While-Program)  
(Note 5)  
Byte  
Word  
Byte  
Word  
48  
50  
48  
50  
Flash VCC Active Current  
(Read-While-Erase)  
(Note 5)  
Flash VCC Active Current  
(Erase-Suspend-Pro-  
gram)  
CEf = VIL, OE = VIH  
VCCs = VCC Max.,  
35  
40  
SRAM VCC Active Current CE1s = VIL,  
CE2s = VIH  
tCYCLE = 10 MHz  
CE1s = 0.2 V,  
SRAM VCC Active Current CE2s = VCCs −  
0.2 V,  
tCYCLE = 10 MHz  
tCYCLE = 1 MHz  
40  
8
mA  
mA  
VCCf = VCC Max., CEf = VCCf ± 0.3 V  
RESET = VCCf ± 0.3 V,  
WP/ACC = VCCf ± 0.3 V  
Flash VCC Standby Cur-  
rent  
ISB1f  
1
1
5
5
µA  
µA  
Flash VCC Standby Cur-  
rent (RESET)  
VCCf = VCC Max., RESET = VSS ± 0.3 V  
WP/ACC = VCCf ± 0.3 V  
ISB2f  
VCCf = VCC Max., CEf = VSS ± 0.3 V  
RESET = VCCf ± 0.3 V,  
WP/ACC = VCCf ± 0.3 V  
Flash VCC Current  
(Automatic Sleep Mode)  
(Note 3)  
ISB3f  
1
5
µA  
VIN = VCCf ± 0.3 V or VSS ± 0.3 V  
SRAM VCC Standby  
Current  
CE1s ≥ VCCs − 0.2V,  
CE2s ≥ VCCs − 0.2V  
ISB1s  
ISB2s  
0.2  
0.2  
7
7
µA  
µA  
SRAM VCC Standby  
Current  
CE2s ≤ 0.2V  
26  
MB84VD2118XA-85/MB84VD2119XA-85  
(Continued)  
(Continued)  
Parameter  
Symbol  
Parameter Description  
Input Low Level  
Test Conditions  
Min.  
−0.3  
2.4  
Typ.  
Max.  
Unit  
V
VIL  
0.5  
VCC +  
0.3*  
VIH  
Input High Level  
V
Voltage for Sector  
Protection, and Temporary  
Sector Unprotection  
(RESET) (Note 4)  
VID  
11.5  
8.5  
12.5  
V
V
Voltage for Program  
Acceleration (WP/ACC)  
(Note4)  
VACC  
9.0  
9.5  
0.4  
VCCf = VCCf Min., VCCs = VCCs Min.,  
IOL = 1.0 mA  
VOL  
VOH  
VLKO  
Output Low Voltage Level  
Output High Voltage Level  
V
V
V
VCCf = VCCf Min., VCCs = VCCs Min.,  
IOH = −0.5 mA  
2.4  
2.3  
Flash Low VCCf Lock-Out  
Voltage  
2.5  
*: VCC indicates lower of VCCf or VCCs.  
Notes : 1. The ICC current listed includes both the DC operating current and the frequency dependent component.  
2. ICC active while Embedded Algorithm (program or erase) is in progress.  
3. Automatic sleep mode enables the low power mode when address remain stable for 150ns.  
4. Applicable for only VCCf applying.  
5. Embedded Alogorithm (program or erase) is in progress. (@5MHz)  
27  
MB84VD2118XA-85/MB84VD2119XA-85  
2. AC Characteristics  
• CE Timing  
Parameter  
Symbols  
Description  
Test Setup  
-85  
Unit  
JEDEC Standard  
tCCR  
CE Recover Time  
Min.  
0
ns  
• Timing Diagram for alternating SRAM to Flash  
CEf  
tCCR  
tCCR  
CE1s  
CE2s  
tCCR  
tCCR  
28  
MB84VD2118XA-85/MB84VD2119XA-85  
• Read Only Operations Characteristics (Flash)  
Parameter  
Symbols  
-85  
(Note)  
Test  
Setup  
Description  
Unit  
JEDEC Standard  
Min.  
85  
Max.  
tAVAV  
tRC  
Read Cycle Time  
ns  
ns  
CEf = VIL  
OE = VIL  
tAVQV  
tACC  
Address to Output Delay  
85  
tELQV  
tGLQV  
tEHQZ  
tGHQZ  
tCEf  
tOE  
tDF  
tDF  
Chip Enable to Output Delay  
Output Enable to Output Delay  
Chip Enable to Output High-Z  
Output Enable to Output High-Z  
OE = VIL  
85  
35  
30  
30  
ns  
ns  
ns  
ns  
Output Hold Time From Addresses,  
CEf or OE, Whichever Occurs First  
tAXQX  
tOH  
0
ns  
tREADY  
RESET Pin Low to Read Mode  
20  
µs  
Note : Test Conditions − Output Load : 1 TTL gate and 30 pF  
Input rise and fall times : 5 ns  
Input pulse levels : 0.0 V to 3.0 V  
Timing measurement reference level  
Input : 1.5 V  
Output : 1.5 V  
29  
MB84VD2118XA-85/MB84VD2119XA-85  
• Read Cycle (Flash)  
tRC  
Addresses Stable  
Addresses  
tACC  
CEf  
tDF  
tOE  
OE  
tOEH  
WE  
tCEf  
HIGH-Z  
HIGH-Z  
DQ  
Output Valid  
tRC  
Addresses  
CEf  
Addresses Stable  
tRH  
tACC  
tRP  
tRH  
tCEf  
RESET  
DQ  
tOH  
HIGH-Z  
Output Valid  
30  
MB84VD2118XA-85/MB84VD2119XA-85  
• Erase/Program Operations (Flash)  
Parameter Symbols  
-85  
Description  
Unit  
JEDEC  
tAVAV  
Standard  
Min. Typ. Max.  
tWC  
tAS  
Write Cycle Time  
85  
0
ns  
ns  
ns  
ns  
tAVWL  
Address Setup Time (WE to Addr.)  
tASO  
tAH  
Address Setup Time to CEf Low During Toggle Bit Polling  
Address Hold Time (WE to Addr.)  
15  
45  
tWLAX  
Address Hold Time from CEf or OE High During Toggle Bit  
Polling  
tAHT  
0
ns  
tDVWH  
tWHDX  
tDS  
tDH  
Data Setup Time  
35  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
s
Data Hold Time  
tOES  
Output Enable Setup Time  
0
Read  
Output Enable Hold Time  
0
tOEH  
Toggle and Data Polling  
10  
20  
20  
0
tCEPH  
tOEPH  
tGHEL  
tGHWL  
tWS  
CEf High During Toggle Bit Polling  
OE High During Toggle Bit Polling  
Read Recover Time Before Write (OE to CEf)  
Read Recover Time Before Write (OE to WE)  
WE Setup Time (CEf to WE)  
CEf Setup Time (WE to CEf)  
WE Hold Time (CEf to WE)  
CEf Hold Time (WE to CEf)  
Write Pulse Width  
tGHEL  
tGHWL  
tWLEL  
tELWL  
tEHWH  
tWHEH  
tWLWH  
tELEH  
tWHWL  
tEHEL  
0
0
tCS  
0
tWH  
0
tCH  
0
tWP  
35  
35  
30  
30  
8
tCP  
CEf Pulse Width  
tWPH  
tCPH  
Write Pulse Width High  
CEf Pulse Width High  
Byte Programming Operation  
Word Programming Operation  
Sector Erase Operation (Note 1)  
tWHWH1  
tWHWH2  
tWHWH1  
tWHWH2  
16  
1
(Continued)  
31  
MB84VD2118XA-85/MB84VD2119XA-85  
(Continued)  
Parameter Symbols  
Description  
-85  
Unit  
JEDEC  
Standard  
Min.  
50  
Typ.  
Max.  
tVCS  
VCCf Setup Time  
µs  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
tVLHT  
tVIDR  
tVACCR  
tRB  
Voltage Transition Time (Note 2)  
Rise Time to VID (Note 2)  
4
500  
500  
0
Rise Time to VACC  
Recover Time from RY/BY  
RESET Pulse Width  
tRP  
500  
tEOE  
Delay Time from Embedded Output Enable  
RESET Hold Time Before Read  
Program/Erase Valid to RY/BY Delay  
Erase Time-out Time (Note 3)  
Erase Suspend Transition Time (Note 4)  
85  
90  
20  
tRH  
200  
50  
tBUSY  
tTOW  
tSPD  
Notes : 1. This does not include the preprogramming time.  
2. This timing is for Sector Protection Operation.  
3. The time between writes must be less than “tTOW” otherwise that command will not be accepted and  
erasure will start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will  
initiate the execution of the Sector Erase command (s) .  
4. When the Erase Suspend command is written during the Sector Erase operation, the device will take a  
maximum of “tSPD” to suspend the erase operation.  
32  
MB84VD2118XA-85/MB84VD2119XA-85  
• Write Cycle (WE control) (Flash)  
3rd Bus Cycle  
Data Polling  
Addresses  
555H  
tWC  
PA  
PA  
tRC  
tAS  
tAH  
CEf  
tCS  
tCH  
tCEf  
OE  
tGHWL  
tOE  
tWHWH1  
tWP  
tWPH  
WE  
tOH  
tDS  
tDH  
A0H  
PD  
DQ7  
DOUT  
DOUT  
DQ  
Notes : 1. PA is address of the memory location to be programmed.  
2. PD is data to be programmed at byte address.  
3. DQ7 is the output of the complement of the data written to the device.  
4. DOUT is the output of the data written to the device.  
5. Figure indicates last two bus cycles out of four bus cycle sequence.  
6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)  
33  
MB84VD2118XA-85/MB84VD2119XA-85  
• Write Cycle (CEf control) (Flash)  
3rd Bus Cycle  
Data Polling  
Addresses  
555H  
tWC  
PA  
PA  
tAS  
tAH  
WE  
tWS  
tWH  
OE  
tGHEL  
tWHWH1  
tCP  
tCPH  
CEf  
tDS  
tDH  
A0H  
PD  
DQ7  
DOUT  
DQ  
Notes : 1. PA is address of the memory location to be programmed.  
2. PD is data to be programmed at byte address.  
3. DQ7 is the output of the complement of the data written to the device.  
4. DOUT is the output of the data written to the device.  
5. Figure indicates last two bus cycles out of four bus cycle sequence.  
6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)  
34  
MB84VD2118XA-85/MB84VD2119XA-85  
• AC Waveforms Chip/Sector Erase Operations (Flash)  
*
SA  
555H  
tWC  
2AAH  
555H  
555H  
2AAH  
Addresses  
tAS  
tAH  
CEf  
tCS  
tCH  
OE  
tWP  
tWPH  
tGHWL  
WE  
tDS  
tDH  
30H for Sector Erase  
10H/  
30H  
AAH  
55H  
80H  
AAH  
55H  
DQ  
tVCS  
VCCf  
* : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.  
Note : These waveforms are for the× 16 mode. (The addresses differ from × 8 mode.)  
35  
MB84VD2118XA-85/MB84VD2119XA-85  
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)  
CEf  
tDF  
tCH  
tOE  
OE  
tOEH  
WE  
tCEf  
*
High-Z  
High-Z  
DQ7 =  
DQ7  
Data In  
Data In  
DQ7  
Valid Data  
tWHWH1 or 2  
DQ  
(DQ0 to DQ6)  
DQ0 to DQ6  
Valid Data  
DQ0 to DQ6 = Output Flag  
tEOE  
tBUSY  
RY/BY  
* : DQ7 = Valid Data (The device has completed the Embedded operation.)  
36  
MB84VD2118XA-85/MB84VD2119XA-85  
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)  
Addresses  
CEf  
tAHT tASO  
tAHT tAS  
tCEPH  
WE  
tOEPH  
tOEH  
tOEH  
OE  
tOE  
tCEf*  
tDH  
Toggle  
Data  
Toggle  
Data  
Toggle  
Data  
Stop  
Toggling  
Output  
Valid  
Data  
DQ6/DQ2  
tBUSY  
RY/BY  
* : DQ6 stops toggling (The device has completed the Embedded operation) .  
37  
MB84VD2118XA-85/MB84VD2119XA-85  
• Back-to-back Read/Write Timing Diagram (Flash)  
Read  
tRC  
Command  
tWC  
Read  
tRC  
Command  
tWC  
Read  
tRC  
Read  
tRC  
BA2  
(555H)  
BA2  
(PA)  
BA2  
(PA)  
BA1  
BA1  
BA1  
Address  
tAS  
tACC  
tCEf  
tAS  
tAH  
tAHT  
CEf  
OE  
tOE  
tCEPH  
tGHWL  
tOEH  
tDF  
tWP  
WE  
tDH  
tDF  
tDS  
Valid  
Output  
Valid  
Input  
Valid  
Output  
Valid  
Input  
Valid  
Output  
DQ  
Status  
(A0H)  
(PD)  
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.  
BA1 : Address of Bank 1.  
BA2 : Address of Bank 2.  
38  
MB84VD2118XA-85/MB84VD2119XA-85  
• RY/BY Timing Diagram during Write/Erase Operations (Flash)  
CEf  
WE  
The rising edge of the last write pulse  
Entire programming  
or erase operations  
RY/BY  
tBUSY  
• RESET, RY/BY Timing Diagram (Flash)  
WE  
RESET  
tRP  
tRB  
RY/BY  
tREADY  
39  
MB84VD2118XA-85/MB84VD2119XA-85  
• Temporary Sector Unprotection (Flash)  
VCCf  
tVIDR  
tVLHT  
tVCS  
VID  
3 V  
3 V  
RESET  
CEf  
WE  
tVLHT  
tVLHT  
Program or Erase Command Sequence  
RY/BY  
Unprotection Period  
40  
MB84VD2118XA-85/MB84VD2119XA-85  
• Extended Sector Protection (Flash)  
VCCf  
tVCS  
RESET  
tVLHT  
tVIDR  
tWC  
tWC  
SGAx  
SGAx  
SGAy  
Addresses  
A0  
A1  
A6  
CEf  
OE  
TIME - OUT  
tWP  
WE  
Data  
60H  
60H  
40H  
01H  
60H  
tOE  
SGAx : Sector Group Address to be protected  
SGAy : Next Group Sector Address to be protected  
TIME-OUT : Time-Out window = 250 µs (min.)  
41  
MB84VD2118XA-85/MB84VD2119XA-85  
• Accelerated Program (Flash)  
VCC  
tVACCR  
tVCS  
tVLHT  
VACC  
3 V  
3 V  
WP/ACC  
CE  
WE  
tVLHT  
tVLHT  
Program or Erase Command Sequence  
Acceleration period  
RY/BY  
42  
MB84VD2118XA-85/MB84VD2119XA-85  
• Read Cycle (SRAM)  
Parameter  
Symbol  
Parameter Description  
Min.  
Max.  
Unit  
tRC  
tAA  
Read Cycle Time  
Address Access Time  
85  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
85  
85  
85  
45  
85  
tCO1  
tCO2  
tOE  
Chip Enable (CE1s) Access Time  
Chip Enable (CE2s) Access Time  
Output Enable Access Time  
tBA  
LBS, UBS to Output Valid  
tCOE  
tOEE  
tBE  
Chip Enable (CE1s Low and CE2s High) to Output Active  
Output Enable Low to Output Active  
UBS, LBS Enable Low to Output Active  
Chip Enable (CE1s High or CE2s Low) to Output High-Z  
Output Enable High to Output High-Z  
UBS, LBS Output Enable to Output High-Z  
Output Data Hold Time  
5
0
0
tOD  
35  
35  
50  
tODO  
tBD  
tOH  
10  
43  
MB84VD2118XA-85/MB84VD2119XA-85  
• Read Cycle (Note) (SRAM)  
tRC  
ADDRESSES  
tAA  
tOH  
tCO1  
CE1s  
tCOE  
tCO2  
tOD  
CE2s  
tOD  
tOE  
OE  
tODO  
tBD  
tOEE  
LBS, UBS  
tBA  
tBE  
tCOE  
DQ  
VALID DATA OUT  
Note : WE remains HIGH for the read cycle.  
44  
MB84VD2118XA-85/MB84VD2119XA-85  
• Write Cycle (SRAM)  
Parameter  
Symbol  
Parameter Description  
Min.  
Max.  
Unit  
tWC  
tWP  
tCW  
tAW  
tBW  
tAS  
Write Cycle Time  
Write Pulse Width  
85  
55  
70  
70  
55  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable to End of Write  
Address valid to End of Write  
UBS, LBS to End of Write  
Address Setup Time  
tWR  
tODW  
tOEW  
tDS  
Write Recovery Time  
WE Low to Output High-Z  
WE High to Output Active  
Data Setup Time  
0
35  
0
35  
0
tDH  
Data Hold Time  
45  
MB84VD2118XA-85/MB84VD2119XA-85  
• Write Cycle (Note 3) (WE control) (SRAM)  
tWC  
Addresses  
tAS  
tWP  
tWR  
WE  
tAW  
tCW  
CE1s  
CE2s  
tCW  
tBW  
LBS, UBS  
tODW  
tOEW  
DOUT  
DIN  
Note 1  
Note 4  
Note 2  
Note 4  
tDS  
tDH  
VALID DATA IN  
Notes : 1. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the  
output will remain at high impedance.  
2. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the  
output will remain at high impedance.  
3. If OE is HIGH during the write cycle, the outputs will remain at high impedance.  
4. Because I/O signals may be in the output state at this time, input signals of reverse  
polarity must not be applied.  
46  
MB84VD2118XA-85/MB84VD2119XA-85  
• Write Cycle (Note 1) (CE1s control) (SRAM)  
tWC  
Addresses  
WE  
tAS  
tWR  
tWP  
tAW  
tCW  
CE1s  
CE2s  
tCW  
tBW  
LBS, UBS  
tBE  
tCOE  
tODW  
DOUT  
DIN  
tDS  
tDH  
VALID DATA IN  
Note 2  
Notes : 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance.  
2. Because I/O signals may be in the output state at this time, input signals of reverse  
polarity must not be applied.  
47  
MB84VD2118XA-85/MB84VD2119XA-85  
• Write Cycle (Note 1) (CE2s Control) (SRAM)  
tWC  
Addresses  
tAS  
tWP  
tWR  
WE  
tCW  
CE1s  
CE2s  
tAW  
tCW  
tBW  
LBS, UBS  
tBE  
tCOE  
tODW  
DOUT  
DIN  
tDS  
tDH  
Note 2  
VALID DATA IN  
Notes : 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance.  
2. Because I/O signals may be in the output state at this time, input signals of reverse  
polarity must not be applied.  
48  
MB84VD2118XA-85/MB84VD2119XA-85  
• Write Cycle (Note 1) (LBs, UBs Control) (SRAM)  
tWC  
Addresses  
WE  
tWP  
tWR  
tCW  
CE1s  
CE2s  
tCW  
tAW  
tBW  
tAS  
LBS, UBS  
tBE  
tCOE  
tODW  
DOUT  
tDS  
tDH  
DIN  
Note 2  
VALID DATA IN  
Notes : 1. If OE is HIGH during the write cycle, the outputs will remain at high impedance.  
2. Because I/O signals may be in the output state at this time, input signals of reverse  
polarity must not be applied.  
49  
MB84VD2118XA-85/MB84VD2119XA-85  
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)  
Limits  
Parameter  
Unit  
Comment  
Min.  
Typ.  
Max.  
Excludes programming time  
prior to erasure  
Sector Erase Time  
1
10  
s
Excludes system-level  
overhead  
Byte Programming Time  
Word Programming Time  
8
300  
360  
50  
µs  
µs  
Excludes system-level  
overhead  
16  
Excludes system-level  
overhead  
Chip Programming Time  
Erase/Program Cycle  
s
100,000  
cycle  
■ DATA RETENTION CHARACTERISTICS (SRAM)  
Parameter  
Parameter Description  
Symbol  
Min.  
Typ.  
Max.  
Unit  
VDH  
IDDS2  
tCDR  
tR  
Data Retention Supply Voltage  
Standby Current  
1.5  
3.6  
7*  
V
VDH = 3.0 V  
0.2  
µA  
ns  
ns  
Chip Deselect to Data Retention Mode Time  
Recovery Time  
0
tRC  
Note : tRC : Read cycle time  
* : 4 µA Max. at TA ≤ 60 °C, 1 µA Max. at TA ≤ 40 °C  
• CE1s Controlled Data Retention Mode (Note 1)  
VCCs  
DATA RETENTION MODE  
2.7 V  
See Note 2  
See Note 2  
tR  
VIH  
VDH  
VCCS −0.2 V  
CE1s  
tCDR  
GND  
50  
MB84VD2118XA-85/MB84VD2119XA-85  
• CE2s Controlled Data Retention Mode (Note 3)  
VCCs  
DATA RETENTION MODE  
2.7 V  
VDH  
VIH  
CE2s  
tCDR  
tR  
VIL  
0.2 V  
GND  
Notes : 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs − 0.2 V or Vss  
to 0.2 V during data retention mode. Other input and input/output pins can be used between −0.3 V and  
Vccs + 0.3 V.  
2. When CE1s is operating at the VIH min. level (2.2 V) , the standby current is given by ISB1s during the  
transition of VCCs from 3.6 to 2.2 V.  
3. In CE2s controlled data retention mode, input and input/output pins can be used between −0.3 V and  
Vccs + 0.3 V.  
■ PIN CAPACITANCE  
Parameter  
Symbol  
Parameter Description  
Test Setup  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
VIN = 0  
11  
12  
14  
17  
14  
16  
16  
20  
pF  
pF  
pF  
pF  
COUT  
CIN2  
CIN3  
Output Capacitance  
VOUT = 0  
VIN = 0  
VIN = 0  
Control Pin Capacitance  
WP/ACC Pin Capacitance  
Note : Test conditions TA = 25 °C, f = 1.0 MHz  
■ HANDLING OF PACKAGE  
Please handle this package carefully since the sides of packages are right angle.  
■ CAUTION  
1. The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not  
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.  
2. For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the  
sector using “Extended sector protect” command.  
51  
MB84VD2118XA-85/MB84VD2119XA-85  
■ ORDERING INFORMATION  
MB84VD2118  
X
A
-85  
-PBS  
PACKAGE TYPE  
PBS = 69-ball FBGA  
PTS = 56-pin TSOP (I)  
SPEED OPTION  
See Product Selector Guide.  
Device Revision  
Bank Size  
1 = 0.5 Mbit / 15.5 Mbit  
2 = 2 Mbit / 14 Mbit  
3 = 4 Mbit / 12 Mbit  
4 = 8 Mbit /  
8 Mbit  
DEVICE NUMBER/DESCRIPTION  
16Mega-bit (2M × 8-bit or 1M × 16-bit) Dual Operation Flash Memory  
3.0 V-only Read, Program, and Erase  
4Mega-bit (512K × 8-bit) SRAM  
BOOT CODE SECTOR ARCHITECTURE  
84VD2118 = Top sector  
84VD2119 = Bottom sector  
52  
MB84VD2118XA-85/MB84VD2119XA-85  
■ PACKAGE DIMENSIONS  
69-ball plastic FBGA  
(BGA-69P-M02)  
7.20(.283)  
11.00±0.10(.433±.004)  
1.25 –+00..1105  
5.60(.220)REF  
0.80(.031)  
(Mounting height)  
(Stand off)  
.049 –+..000046  
0.38±0.10  
(.015±.004)  
10  
9
8
7
6
5
4
3
2
1
0.80(.031)  
8.00±0.10  
(.315±.004)  
5.60(.220)  
REF  
7.20(.283)  
K
J
H
G
F
E
D
C
B
A
INDEX-MARK AREA  
INDEX BALL  
69-Ø0.45 –+00..0150  
69-Ø0.18 –+..000024  
M
0.08(.003)  
0.10(.004)  
C
1999 FUJITSU LIMITED B69002S-1C-1  
Dimension in mm (inches)  
(Continued)  
53  
MB84VD2118XA-85/MB84VD2119XA-85  
(Continued)  
56-pin plastic TSOP (I)  
(FPT-56P-M04)  
14.00±0.20(.551±.008)  
12.40±0.10(.488±.004)  
INDEX  
0.40(.016)  
TYP  
12.00±0.10  
(.472±.004)  
0.18±0.035  
(.007±.001)  
M
0.10(.004)  
Details of "A" part  
0.25(.010)  
"A"  
0°~8°  
1.15±0.05  
(.045±.002)  
(.004±.002) (Mounting height)  
(Stand off)  
0.145 +–00..0035  
.006 +–..000012  
0.10±0.05  
0.08(.003)  
0.45/0.75  
(.018/.030)  
C
1998 FUJITSU LIMITED F56004S-1C-1  
Dimension in mm (inches)  
54  
MB84VD2118XA-85/MB84VD2119XA-85  
FUJITSU LIMITED  
For further information please contact:  
Japan  
All Rights Reserved.  
FUJITSU LIMITED  
Corporate Global Business Support Division  
The contents of this document are subject to change without notice.  
Customers are advised to consult with FUJITSU sales  
representatives before ordering.  
Electronic Devices  
KAWASAKI PLANT, 4-1-1, Kamikodanaka,  
Nakahara-ku, Kawasaki-shi,  
Kanagawa 211-8588, Japan  
Tel: +81-44-754-3763  
The information and circuit diagrams in this document are  
presented as examples of semiconductor device applications, and  
are not intended to be incorporated in devices for actual use. Also,  
FUJITSU is unable to assume responsibility for infringement of  
any patent rights or other rights of third parties arising from the use  
of this information or circuit diagrams.  
Fax: +81-44-754-3329  
http://www.fujitsu.co.jp/  
North and South America  
FUJITSU MICROELECTRONICS, INC.  
3545 North First Street,  
San Jose, CA 95134-1804, U.S.A.  
Tel: +1-408-922-9000  
Fax: +1-408-922-9179  
The contents of this document may not be reproduced or copied  
without the permission of FUJITSU LIMITED.  
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Mon. - Fri.: 7 am - 5 pm (PST)  
Tel: +1-800-866-8608  
FUJITSU semiconductor devices are intended for use in standard  
applications (computers, office automation and other office  
equipments, industrial, communications, and measurement  
equipments, personal or household devices, etc.).  
Fax: +1-408-922-9179  
http://www.fujitsumicro.com/  
CAUTION:  
Europe  
Customers considering the use of our products in special  
applications where failure or abnormal operation may directly  
affect human lives or cause physical injury or property damage, or  
where extremely high levels of reliability are demanded (such as  
aerospace systems, atomic energy controls, sea floor repeaters,  
vehicle operating controls, medical devices for life support, etc.)  
are requested to consult with FUJITSU sales representatives before  
such use. The company will not be responsible for damages arising  
from such use without prior approval.  
FUJITSU MICROELECTRONICS EUROPE GmbH  
Am Siebenstein 6-10,  
D-63303 Dreieich-Buchschlag,  
Germany  
Tel: +49-6103-690-0  
Fax: +49-6103-690-122  
http://www.fujitsu-fme.com/  
Asia Pacific  
FUJITSU MICROELECTRONICS ASIA PTE. LTD.  
#05-08, 151 Lorong Chuan,  
New Tech Park,  
Any semiconductor devices have inherently a certain rate of failure.  
You must protect against injury, damage or loss from such failures  
by incorporating safety design measures into your facility and  
equipment such as redundancy, fire protection, and prevention of  
over-current levels and other abnormal operating conditions.  
Singapore 556741  
Tel: +65-281-0770  
Fax: +65-281-0220  
http://www.fmap.com.sg/  
If any products described in this document represent goods or  
technologies subject to certain restrictions on export under the  
Foreign Exchange and Foreign Trade Control Law of Japan, the  
prior authorization by Japanese government should be required for  
export of those products from Japan.  
Korea  
FUJITSU MICROELECTRONICS KOREA LTD.  
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Kangnam-Gu,Seoul 135-280  
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F0007  
FUJITSU LIMITED Printed in Japan  

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