MB84VD21194EG-85-PBS [FUJITSU]
SPECIALTY MEMORY CIRCUIT, PBGA56, PLASTIC, FBGA-56;
| 型号： | MB84VD21194EG-85-PBS |
| 厂家： | 
FUJITSU |
| 描述： | SPECIALTY MEMORY CIRCUIT, PBGA56, PLASTIC, FBGA-56 静态存储器 内存集成电路 |
| 文件： | 总61页 (文件大小：917K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50220-3E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16 M (×8/×16) FLASH MEMORY &
4 M (×8/×16) STATIC RAM
MB84VD2118XEG-70/85/MB84VD2119XEG-70/85
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.3 V
• High Performance
85 ns maximum access time (Flash)
85 ns maximum access time (SRAM)
(Continued)
■ PRODUCT LINE UP
Flash Memory
SRAM
70
85
VCC = 3.0 V
70
85
+0.3 V
−0.3 V
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
70
70
30
70
70
35
85
85
35
85
85
45
Note : Both VCCf and VCCs must be in recommend operation range when either part is being accessed.
■ PACKAGE
56-ball plastic FBGA
(BGA-56P-M01)
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
• Operating Temperature
−25°C to +85°C
• Package 56-pin FBGA
- FLASH MEMORY
• Simultaneous Read/Write Operations (Dual Bank)
Multiple devices available with different bank sizes (Refer to “Pin Configuration” in “■ PIN DESCRIPTION”)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4 K words and thirty-one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2118X : Top sector
MB84VD2119X : Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for detection of program or erase cycle completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC Write Inhibit ≤ 2.5 V
• Hidden ROM (Hi-ROM) Region
64 K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XEG : SA37, SA38 MB84VD2119XEG : SA0, SA1)
At VIH, allows removal of boot sector protection
At VACC, program time will be reduced by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function
- SRAM
• Power Dissipation
Operating : 40 mA Max
Standby : 7 µA Max
• Power Down Features Using CE1s and CE2s
• Data Retention Supply Voltage : 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control : LBs (DQ7-DQ0) , UBs (DQ15-DQ8)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84VD2118XEG-85/MB84VD2119XEG-85
■ PIN ASSIGNMENT
(TOP VIEW)
Marking Side
B8
C8
D8
E8
F8
G8
A15
N.C.
N.C.
A16
CIOf
VSS
A7
B7
C7
D7
E7
SA
F7
G7
H7
A11
A12
A13
A14
DQ15/A-1 DQ7
DQ14
A6
A8
B6
C6
A9
D6
E6
F6
G6
H6
A19
A10
DQ6
DQ13
DQ12
DQ5
A5
B5
C5
F5
G5
H5
WE
CE2s
N.C.
DQ4
VCCs
CIOs
A4
B4
C4
F4
G4
H4
INDEX
LAND*
WP/ACC RESET RY/BY
DQ3
VCCf
DQ11
A3
B3
C3
D3
E3
F3
G3
H3
LBs
UBs
A18
A17
DQ1
DQ9
DQ10
DQ2
A2
A7
B2
A6
C2
A5
D2
A4
E2
F2
G2
H2
VSS
OE
DQ0
DQ8
B1
A3
C1
A2
D1
A1
E1
A0
F1
G1
CEf
CE1s
(BGA-56P-M01)
* : There is no solder ball. This land should be open electrically.
3
MB84VD2118XEG-85/MB84VD2119XEG-85
■ PIN DESCRIPTION
Pin
A17 to A0
A19 to A18, A-1
SA
Function
Input/Output
Address Inputs (Common)
Address Input (Flash)
Address Input (SRAM)
I
I
I
DQ15 to DQ0
CEf
Data Inputs/Outputs (Common)
Chip Enable (Flash)
I/O
I
I
CE1s
Chip Enable (SRAM)
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
Write Enable (Common)
I
WE
I
RY/BY
UBs
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
O
I
LBs
I
I/O Configulation (Flash)
CIOf = Vccf is Word mode (×16) , CIOf = Vss is Byte mode (×8)
CIOf
I
I
I/O Configulation (SRAM)
CIOs = Vccs is Word mode (×16) , CIOs = Vss is Byte mode (×8)
CIOs
RESET
WP/ACC
N.C.
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
I
I
—
VSS
Device Ground (Common)
Power
Power
Power
VCCf
Device Power Supply (Flash)
VCCs
Device Power Supply (SRAM)
4
MB84VD2118XEG-85/MB84VD2119XEG-85
■ BLOCK DIAGRAM
VCCf
VSS
A19 to A0
RY/BY
A19 to A0
A-1
WP/ACC
RESET
CEf
16 M bit
Flash Memory
DQ15 to DQ0
CIOf
DQ15 to DQ0
VCCs
VSS
A17 to A0
DQ15 to DQ0
4 M bit
SA
LBs
Static RAM
UBs
WE
OE
CE1s
CE2s
CIOs
5
MB84VD2118XEG-85/MB84VD2119XEG-85
■ DEVICE BUS OPERATIONS
User Bus Operations Table (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs)
WP/
LBs UBs DQ7 to DQ0 DQ15 to DQ8 RESET ACC
SA
*
Operation*1, *3
CEf CE1s CE2s OE WE
6
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
High-Z
High-Z
H
H
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
X
H
X
H
X
X
L
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
DOUT
DIN
Read from Flash*2
Write to Flash
L
H
H
X
X
L
H
L
H
L
L
L
DOUT
High-Z
DOUT
DOUT
DOUT
High-Z
DIN
Read from SRAM
Write to SRAM
H
L
H
L
H
X
H
X
H
L
L
DIN
H
X
L
H
X
X
X
L
X
X
H
L
L
High-Z
DIN
DIN
H
X
X
H
High-Z
Temporary Sector
Group
Unprotection*4
X
X
X
X
X
X
VID
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ DC CHARACTERISTICS” for voltage levels.
*1 : Other operations not indicated in this column are prohibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4 : Also used for the extended sector group protections.
*5 : WP/ACC = VIL : protection of boot sectors.
WP/ACC = VIH : removal of boot sectors protection.
WP/ACC = VACC (9 V) : Program time will be reduced by 40%.
*6 : SA : Don’t care.
6
MB84VD2118XEG-85/MB84VD2119XEG-85
User Bus Operations Table (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS)
WP/
LBs UBs
Operation*1, *3
CEf CE1s CE2s OE WE SA
DQ7 to DQ0 DQ15 to DQ8 RESET ACC
6
6
*
*
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
High-Z
High-Z
H
H
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
X
H
X
H
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
DOUT
DIN
X
L
Read from Flash*2
Write to Flash
L
H
H
X
X
X
L
L
H
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
X
X
X
X
DOUT
DIN
High-Z
High-Z
H
H
X
X
L
X
Temporary Sector
Group
Unprotection*4
X
X
X
X
X
X
X
X
X
X
VID
X
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ DC CHARACTERISTICS” for voltage levels.
*1 : Other operations not indicated in this column are prohibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4 : Also used for the extended sector group protections.
*5 : WP/ACC = VIL : protection of boot sectors.
WP/ACC = VIH : removal of boot sectors protection.
WP/ACC = VACC (9 V) : Program time will be reduced by 40%.
*6 : LBS , UBS : Don’t care.
7
MB84VD2118XEG-85/MB84VD2119XEG-85
User Bus Operations Table (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS)
WP/
Operation
LBs UBs
DQ7 to
DQ0
DQ14 to
DQ8
ACC
CEf CE1s CE2s DQ15/A-1 OE WE SA
RESET
6
6
*1, *3
*
*
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
X
High-Z
High-Z
H
X
X
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
H
X
H
X
H
X
L
X
L
A-1
A-1
A-1
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
X
L
Read from
Flash*2
L
X
X
H
H
X
X
X
L
Write to Flash
L
H
Read from SRAM
Write to SRAM
H
H
H
H
X
X
L
H
L
SA
SA
X
X
X
X
DOUT
DIN
High-Z
High-Z
H
H
X
X
L
X
Temporary Sector
Group
Unprotection*4
X
X
X
X
X
X
X
X
X
X
X
VID
X
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ DC CHARACTERISTICS” for voltage levels.
*1 : Other operations not indicated in this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : Also used for the extended sector group protections.
*5 : WP/ACC = VIL : protection of boot sectors.
WP/ACC = VIH : removal of boot sectors protection.
WP/ACC = VACC (9 V) : Program time will be reduced by 40%.
*6 : LBS , UBS : Don’t care.
8
MB84VD2118XEG-85/MB84VD2119XEG-85
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Eight 4 K words, and thirty-one 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Word mode Byte mode
0FFFFFh
0FF000h
0FE000h
0FD000h
0FC000h
0FB000h
0FA000h
0F9000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
000000h
1FFFFFh
1FE000h
1FC000h
1FA000h
1F8000h
1F6000h
1F4000h
1F2000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
SA38 : 8 KB (4 KW)
SA37 : 8 KB (4 KW)
SA36 : 8 KB (4 KW)
SA35 : 8 KB (4 KW)
SA34 : 8 KB (4 KW)
SA33 : 8 KB (4 KW)
SA32 : 8 KB (4 KW)
SA31 : 8 KB (4 KW)
SA30 : 64 KB (32 KW)
SA29 : 64 KB (32 KW)
SA28 : 64 KB (32 KW)
SA27 : 64 KB (32 KW)
SA26 : 64 KB (32 KW)
SA25 : 64 KB (32 KW)
SA24 : 64 KB (32 KW)
SA23 : 64 KB (32 KW)
SA22 : 64 KB (32 KW)
SA21 : 64 KB (32 KW)
SA20 : 64 KB (32 KW)
SA19 : 64 KB (32 KW)
SA18 : 64 KB (32 KW)
SA17 : 64 KB (32 KW)
SA16 : 64 KB (32 KW)
SA15 : 64 KB (32 KW)
SA14 : 64 KB (32 KW)
SA13 : 64 KB (32 KW)
SA12 : 64 KB (32 KW)
SA11 : 64 KB (32 KW)
SA10 : 64 KB (32 KW)
SA9 : 64 KB (32 KW)
SA8 : 64 KB (32 KW)
SA7 : 64 KB (32 KW)
SA6 : 64 KB (32 KW)
SA5 : 64 KB (32 KW)
SA4 : 64 KB (32 KW)
SA3 : 64 KB (32 KW)
SA2 : 64 KB (32 KW)
SA1 : 64 KB (32 KW)
SA0 : 64 KB (32 KW)
Bank 1
MB84VD21181EG
Bank 1
MB84VD21182EG
Bank 1
MB84VD21183EG
Bank 1
MB84VD21184EG
Bank 2
MB84VD21181EG
Bank 2
MB84VD21182EG
Bank 2
MB84VD21183EG
Bank 2
MB84VD21184EG
MB84VD2118XEG Sector Architecture (Top Boot Block)
(Continued)
9
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Word mode Byte mode
0FFFFFh
1FFFFFh
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
00E000h
00C000h
00A000h
008000h
006000h
004000h
002000h
000000h
SA38 : 64 KB (32 KW)
SA37 : 64 KB (32 KW)
SA36 : 64 KB (32 KW)
SA35 : 64 KB (32 KW)
SA34 : 64 KB (32 KW)
SA33 : 64 KB (32 KW)
SA32 : 64 KB (32 KW)
SA31 : 64 KB (32 KW)
SA30 : 64 KB (32 KW)
SA29 : 64 KB (32 KW)
SA28 : 64 KB (32 KW)
SA27 : 64 KB (32 KW)
SA26 : 64 KB (32 KW)
SA25 : 64 KB (32 KW)
SA24 : 64 KB (32 KW)
SA23 : 64 KB (32 KW)
SA22 : 64 KB (32 KW)
SA21 : 64 KB (32 KW)
SA20 : 64 KB (32 KW)
SA19 : 64 KB (32 KW)
SA18 : 64 KB (32 KW)
SA17 : 64 KB (32 KW)
SA16 : 64 KB (32 KW)
SA15 : 64 KB (32 KW)
SA14 : 64 KB (32 KW)
SA13 : 64 KB (32 KW)
SA12 : 64 KB (32 KW)
SA11 : 64 KB (32 KW)
SA10 : 64 KB (32 KW)
SA9 : 64 KB (32 KW)
SA8 : 64 KB (32 KW)
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
Bank 2
MB84VD21194EG
Bank 2
MB84VD21193EG
Bank 2
MB84VD21192EG
Bank 2
MB84VD21191EG
Bank 1
MB84VD21194EG
Bank 1
MB84VD21193EG
SA7
SA6
:
:
:
:
:
:
:
:
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
Bank 1
MB84VD21192EG
SA5
SA4
Bank 1 SA3
MB84VD21191EG
SA2
SA1
SA0
MB84VD2119XEG Sector Architecture (Bottom Boot Block)
10
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21181EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
Bank 2 SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
(Continued)
11
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA34
Bank 1
SA35
SA36
SA37
SA38
12
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21191EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0
1
0
SA3
Bank 1
0
1
1
SA4
1
0
0
SA5
SA6
1
0
1
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
Bank 2 SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
(Continued)
13
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA34
Bank 2
SA35
SA36
SA37
SA38
14
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21182EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
SA13
Bank 2
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
Bank 1 SA29
SA30
(Continued)
15
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA34
Bank 1
SA35
SA36
SA37
SA38
16
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21192EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
SA3
SA4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0
1
0
0
1
1
1
0
0
Bank 1
SA5
SA6
1
0
1
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
Bank 2
(Continued)
17
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA34
Bank 2
SA35
SA36
SA37
SA38
18
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21183EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
SA11
Bank 2
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
Bank 1 SA27
SA28
SA29
SA30
(Continued)
19
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA34
Bank 1
SA35
SA36
SA37
SA38
20
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21193EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Bank 1
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
Bank 2
(Continued)
21
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA34
Bank 2
SA35
SA36
SA37
SA38
22
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21184EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
000000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
SA7
Bank 2
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank 1 SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
(Continued)
23
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1F0000h to 1F1FFFh
1F2000h to 1F3FFFh
1F4000h to 1F5FFFh
1F6000h to 1F7FFFh
1F8000h to 1F9FFFh
1FA000h to 1FBFFFh
1FC000h to 1FDFFFh
1FE000h to 1FFFFFh
0F8000h to 0F8FFFh
0F9000h to 0F9FFFh
0FA000h to 0FAFFFh
0FB000h to 0FBFFFh
0FC000h to 0FCFFFh
0FD000h to 0FDFFFh
0FE000h to 0FEFFFh
0FF000h to 0FFFFFh
SA34
Bank 1
SA35
SA36
SA37
SA38
24
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Address Table (MB84VD21194EG)
Sector Address
Address Range
(Byte mode)
Address Range
(Word mode)
Bank Sector
Bank Address
A19 A18 A17 A16 A15 A14 A13 A12
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
000000h to 001FFFh
002000h to 003FFFh
004000h to 005FFFh
006000h to 007FFFh
008000h to 009FFFh
00A000h to 00BFFFh
00C000h to 00DFFFh
00E000h to 00FFFFh
010000h to 01FFFFh
020000h to 02FFFFh
030000h to 03FFFFh
040000h to 04FFFFh
050000h to 05FFFFh
060000h to 06FFFFh
070000h to 07FFFFh
080000h to 08FFFFh
090000h to 09FFFFh
0A0000h to 0AFFFFh
0B0000h to 0BFFFFh
0C0000h to 0CFFFFh
0D0000h to 0DFFFFh
0E0000h to 0EFFFFh
0F0000h to 0FFFFFh
100000h to 10FFFFh
110000h to 11FFFFh
120000h to 12FFFFh
130000h to 13FFFFh
140000h to 14FFFFh
150000h to 15FFFFh
160000h to 16FFFFh
170000h to 17FFFFh
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
Bank 1 SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
Bank 2
SA27
SA28
SA29
SA30
(Continued)
25
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Sector Address
Address Range
Address Range
(Word mode)
Bank Sector
Bank Address
(Byte mode)
A19 A18 A17 A16 A15 A14 A13 A12
SA31
SA32
SA33
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
180000h to 18FFFFh
190000h to 19FFFFh
1A0000h to 1AFFFFh
1B0000h to 1BFFFFh
1C0000h to 1CFFFFh
1D0000h to 1DFFFFh
1E0000h to 1EFFFFh
1F0000h to 1FFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
SA34
Bank 2
SA35
SA36
SA37
SA38
26
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Group Address Table (MB84VD2118XEG) (Top Boot Block)
Sector Group
A19
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
A15
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Sectors
SGA0
SA0
0
1
SGA1
1
0
SA1 to SA3
1
1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
X
X
X
X
X
X
0
X
X
X
X
X
X
0
SA4 to SA7
SA8 to SA11
SA12 to SA15
SA16 to SA19
SA20 to SA23
SA24 to SA27
SGA8
0
1
SA28 to SA30
1
0
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
1
1
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
27
MB84VD2118XEG-85/MB84VD2119XEG-85
Sector Group Address Table (MB84VD2119XEG) (Bottom Boot Block)
Sector Group
SGA0
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
A16
0
A15
0
A14
0
A13
0
A12
0
Sectors
SA0
SGA1
0
0
0
0
1
SA1
SGA2
0
0
0
1
0
SA2
SGA3
0
0
0
1
1
SA3
SGA4
0
0
1
0
0
SA4
SGA5
0
0
1
0
1
SA5
SGA6
0
0
1
1
0
SA6
SGA7
0
0
1
1
1
SA7
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SGA8
1
0
SA8 to SA10
1
1
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
X
X
X
X
X
X
0
X
X
X
X
X
X
0
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SGA15
SGA16
0
1
SA35 to SA37
SA38
1
0
1
1
28
MB84VD2118XEG-85/MB84VD2119XEG-85
Flash Memory Autoselect Codes Table
A-1*1
VIL
VIL
X
Type
A19 to A12
A6
A1
A0
Code (HEX)
04h
Manufacturer’s Code
X
VIL
VIL
VIL
Byte
Word
Byte
36h
MB84VD21181EG
X
X
X
X
X
X
X
X
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
VIH
2236h
39h
VIL
X
MB84VD21191EG
MB84VD21182EG
MB84VD21192EG
MB84VD21183EG
MB84VD21193EG
MB84VD21184EG
MB84VD21194EG
Word
Byte
2239h
2Dh
VIL
X
Word
Byte
222Dh
2Eh
VIL
X
Word
Byte
222Eh
28h
Device
Code
VIL
X
Word
Byte
2228h
2Bh
VIL
X
Word
Byte
222Bh
33h
VIL
X
Word
Byte
2233h
35h
VIL
X
VIL
VIL
VIH
VIH
VIL
Word
2235h
Sector Group
Address
Sector Group Protect
VIL
VIL
01h*2
*1 : A-1 is for Byte mode.
*2 : Output 01h at protected sector address and output 00h at unprotected sector address.
29
MB84VD2118XEG-85/MB84VD2119XEG-85
Flash Memory Command Definitions Table
Bus
Write
Cy-
cles
Req’d
Second
Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
First Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Command
Sequence
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset*1
1
XXXh F0h
Word
555h
2AAh
555h
555h
Read/Reset*1
3
AAh
AAh
55h
55h
F0h
90h
RA
RD
Byte
AAAh
AAAh
(BA)
555h
Word
555h
2AAh
555h
Autoselect
3
(BA)
AAAh
Byte
AAAh
Word
Byte
Word
Byte
Word
Byte
555h
AAAh
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
555h
AAAh
Program
4
6
6
AAh
AAh
AAh
55h
55h
55h
A0h
80h
80h
PA
PD
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
555h
Chip Erase
Sector Erase
AAh
AAh
55h
55h
10h
30h
AAAh
SA
Sector Erase
Suspend
1
1
BA
BA
B0h
30h
Sector Erase
Resume
Word
Byte
555h
2AAh
555h
555h
Set to
Fast Mode
3
2
2
AAh
55h
20h
AAAh
AAAh
Word
Byte
Fast
Program*2
XXXh A0h
PA
PD
Word
Byte
Reset from
Fast Mode*2
F0h
BA
90h XXXh
6
*
Extended
Word
Sector Group
4
1
XXXh 60h SPA 60h SPA 40h SPA SD
(BA)
55h
98h
(BA)
Byte
Protection*3
Word
Query*4
Byte
AAh
Word
Byte
Word
Byte
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
Hi-ROM
Entry
3
4
AAh
AAh
55h
55h
88h
A0h
Hi-ROM
Program*5
PA
PD
(Continued)
30
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Bus
Write
Cy-
cles
Req’d
Second
Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
First Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Command
Sequence
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Word
Byte
555h
2AAh
555h
555h
555h
2AAh
555h
Hi-ROM
6
4
AAh
55h
80h
AAh
55h hRA 30h
Erase*5
AAAh
AAAh
AAAh
(HRBA)
Word
Byte
555h
2AAh
555h
555h
Hi-ROM
Exit*5
AAh
55h
90h XXXh 00h
(HRBA)
AAAh
AAAh
*1 : Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2 : This command is valid during Fast Mode.
*3 : This command is valid while RESET = VID.
*4 : The valid Address is A6 to A0.
*5 : This command is valid during Hi-ROM mode.
*6 : The data "00h" is also acceptable.
Notes : • Address bits A19 to A12 = X = “H” or “L” for all address commands except for Program Address (PA) ,
Sector Address (SA) , and Bank Address (BA) .
• Bus operations are defined in “■ DEVICE BUS OPERATIONS”.
• RA = Address of the memory location to be read.
• PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
• SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
• BA = Bank address (A19 to A15)
• SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0) .
• HRA = Address of the Hidden-ROM area.
MB84VD2118XEG (Top Boot Type)
Word mode : 0F8000h to 0FFFFFh
Byte mode : 1F0000h to 1FFFFFh
MB84VD2119XEG (Bottom Boot Type) Word mode : 000000h to 007FFFh
Byte mode : 000000h to 00FFFFh
• HRBA = Bank address of the Hidden-ROM area
MB84VD2118XEG (Top Boot Type)
: A19 = A18 = A17 = A16 = A15 = 1
MB84VD2119XEG (Bottom Boot Type) : A19 = A18 = A17 = A16 = A15 = 0
• RD = Data read from location RA during read operation.
• PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
• SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotected sector addresses.
• The system should generate the following address patterns :
Word mode : 555h or 2AAh to addresses A10 to A0
Byte mode : AAAh or 555h to addresses A10 to A0 and A-1
• Command combinations not described in Flash Memory Command Definitions are illegal.
31
MB84VD2118XEG-85/MB84VD2119XEG-85
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
Max
Storage Temperature
Tstg
TA
−55
+125
°C
°C
Ambient Temperature with Power Ap-
plied
−25
+85
VCCf + 0.4
VCCs + 0.4
+4.0
V
V
V
V
V
Voltage with Respect to Ground All
pins except RESET and WP/ACC*1,*2
VIN, VOUT
−0.3
VCCf/VCCs Supply*1
RESET*1,*3
VCCf, VCCs
VIN
−0.3
−0.5
−0.5
+13.0
WP/ACC*1,*4
VIN
+10.5
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is −0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.4 V or VCCs + 0.4 V.
During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCs + 2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on RESET pin is −0.5 V. During voltage transitions, RESET pin may undershoot VSS
to −2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V.
Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
*4 : Minimum DC input voltage on WP/ACC pin is −0.5 V.During voltage transitions, WP/ACC pin may undershoot.
VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
−25
+2.7
Max
+85
Ambient Temperature
TA
°C
VCCf/VCCs Supply Voltages
VCCf, VCCs
+3.3
V
Notes : • Voltage is defined on the basis of VSS = GND = 0 V.
• Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
32
MB84VD2118XEG-85/MB84VD2119XEG-85
■ DC CHARACTERISTICS
Value
Typ
Parameter
Symbol
Test Conditions
Unit
Min
−1.0
−1.0
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
VIN = VSS to VCCf, VCCs
µA
µA
ILO
VOUT = VSS to VCCf, VCCs
RESET Inputs Leakage
Current
VCC = VCC Max,
RESET = 12.5 V
ILIT
35
20
µA
ACC Input Leakage
Current
VCC = VCC Max,
WP/ACC = VACC Max
ILIA
mA
tCYCLE = 5 MHz Byte
13
15
7
mA
tCYCLE = 5 MHz Word
tCYCLE = 1 MHz Byte
tCYCLE = 1 MHz Word
Flash VCC Active Current
(Read) *1
CEf = VIL,
OE = VIH
ICC1f
mA
mA
mA
7
Flash VCC Active Current
(Program/Erase) *2
ICC2f
ICC3f
CEf = VIL, OE = VIH
CEf = VIL, OE = VIH
35
Byte
Word
Byte
48
50
48
50
Flash VCC Active Current
(Read-While-Program) *5
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
ICC5f
CEf = VIL, OE = VIH
CEf = VIL, OE = VIH
mA
mA
Word
Flash VCC Active Current
(Erase-Suspend-
Program)
35
40
VCCs = VCCs Max,
CE1s = VIL,
CE2s = VIH
SRAM VCC Active Current
SRAM VCC Active Current
Flash VCC Standby Current
ICC1s
ICC2s
tCYCLE = 10 MHz
mA
tCYCLE = 10 MHz
40
8
mA
mA
CE1s = 0.2 V,
CE2s = VCCs − 0.2 V,
tCYCLE = 1 MHz
VCCf = VCCf Max, CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
ISB1f
ISB2f
1
1
5
5
µA
µA
Flash VCC Standby Current
(RESET)
VCCf = VCCf Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
VCCf = VCCf Max, CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
Flash VCC Current
(Automatic Sleep Mode) *3
ISB3f
1
5
µA
VIN = VCCf ± 0.3 V or VSS ± 0.3 V
SRAM VCC Standby
Current
ISB1s
ISB2s
CE1s ≥ VCCs − 0.2 V, CE2s ≥ VCCs − 0.2 V
CE2s ≤ 0.2 V
7
7
µA
µA
SRAM VCC Standby
Current
(Continued)
33
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Value
Typ
Parameter
Input Low Level
Symbol
Test Conditions
Unit
Min
Max
VIL
−0.3
0.5
V
V
VCC*6
+ 0.3
Input High Level
VIH
2.4
Voltage for Sector
Protection, and Temporary
Sector Unprotection
(RESET) *4
VID
11.5
12.5
V
V
Voltage for Program
Acceleration (WP/ACC)
(Note4)
VACC
8.5
9.0
9.5
VCCf = VCCf Min, VCCs = VCCs Min
IOL = 4.0 mA
Output Low Voltage Level
Output High VoltageLevel
VOL
VOH
VLKO
0.45
V
V
V
VCCf = VCCf Min, VCCs = VCCs Min
IOL = −0.5 mA
2.4
2.3
Flash Low VCC Lock-Out
Voltage
2.5
*1 : ICC current listed includes both the DC operating current and the frequency dependent component.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4 : Applicable for only VCC applying.
*5 : Embedded Algorithm (program or erase) is in progress (@5 MHz) .
*6 : VCC indicates the lower voltage of VCCf or VCCS.
34
MB84VD2118XEG-85/MB84VD2119XEG-85
■ AC CHARACTERISTICS
• CE Timing
Symbol
Value
Min
0
Parameter
Test Setup
Unit
JEDEC
Standard
CE Recover Time
tCCR
ns
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
CE2s
tCCR
tCCR
35
MB84VD2118XEG-85/MB84VD2119XEG-85
• Read Only Operations Characteristics (Flash)
Symbol
-70
-85
Parameter
Read Cycle Time
Test Setup
Unit
JEDEC Standard
Min
Max
Min
Max
tAVAV
tRC
70
85
ns
ns
CEf = VIL
OE = VIL
Address to Output Delay
tAVQV
tACC
70
85
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
70
25
25
25
85
35
30
30
ns
ns
ns
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
0
0
ns
RESET Pin Low to Read Mode
tREADY
20
20
µs
Test Conditions : Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to 3.0 V
Timing measurement reference level
Input : 0.5 × VCCf
Output : 0.5 × VCCf
36
MB84VD2118XEG-85/MB84VD2119XEG-85
• Read Cycle (Flash)
tRC
Address Stable
Address
tACC
CEf
OE
tDF
tOE
tOEH
WE
DQ
tCE
High-Z
High-Z
Output Valid
• Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
Address Stable
tACC
tRH
CEf
tRP
tRH
tCE
RESET
tOH
High-Z
DQ
Output Valid
37
MB84VD2118XEG-85/MB84VD2119XEG-85
• Erase/Program Operations (Flash)
Symbol
-70
-85
Parameter
Unit
JEDEC Standard Min Typ Max Min Typ Max
Write Cycle Time
tAVAV
tWC
tAS
70
0
85
0
ns
ns
Address Setup Time (WE to Addr.)
tAVWL
Address Setup Time to CEf Low During
Toggle Bit Polling
tASO
tAH
12
45
0
15
45
0
ns
ns
ns
Address Hold Time (WE to Addr.)
tWLAX
Address Hold Time from CEf or OE High
During Toggle Bit Polling
tAHT
Data Setup Time
tDVWH
tDS
tDH
30
0
35
0
ns
ns
ns
ns
Data Hold Time
tWHDX
Output Enable Setup Time
tOES
0
0
Read
0
0
Output Enable Hold
tOEH
Toggle and Data
Time
10
10
ns
Polling
CEf High During Toggle Bit Polling
OE High During Toggle Bit Polling
tCEPH
tOEPH
20
20
20
20
ns
ns
Read Recover Time Before Write
(OE to CEf)
tGHEL
tGHWL
tGHEL
tGHWL
0
0
0
0
ns
ns
Read Recover Time Before Write
(OE to WE)
WE Setup Time (CEf to WE)
CEf Setup Time (WE to CEf)
WE Hold Time (CEf to WE)
CEf Hold Time (WE to CEf)
Write Pulse Width
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tWS
tCS
0
0
0
0
ns
ns
tWH
tCH
0
0
ns
0
0
ns
tWP
tCP
35
35
25
25
35
35
30
30
ns
CEf Pulse Width
ns
Write Pulse Width High
CEf Pulse Width High
Byte Programming Operation
Word Programming Operation
Sector Erase Operation*1
VCCf Setup Time
tWHWL
tEHEL
tWPH
tCPH
ns
ns
8
16
1
8
16
1
µs
tWHWH1
tWHWH1
µs
tWHWH2
tWHWH2
tVCS
s
50
4
50
4
µs
Voltage Transition Time *2
Rise Time to VID *2
tVLHT
tVIDR
tVACCR
tRB
µs
500
500
0
500
500
0
ns
Rise Time to VACC
ns
ns
Recover Time from RY/BY
RESET Pulse Width
tRP
500
500
ns
(Continued)
38
MB84VD2118XEG-85/MB84VD2119XEG-85
(Continued)
Symbols
-70
-85
Parameter
Unit
JEDEC Standard Min Typ Max Min Typ Max
Delay Time from Embedded Output Enable
RESET Hold Time Before Read
Program/Erase Valid to RY/BY Delay
Erase Time-out Time*3
tEOE
tRH
70
90
20
85
90
20
ns
ns
ns
µs
µs
200
50
200
50
tBUSY
tTOW
tSPD
Erase Suspend Transition Time*4
*1 : Do not include the preprogramming time.
*2 : This timing is for Sector Protection Operation.
*3 : The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure
will start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the
execution of the Sector Erase command (s) .
*4 : When the Erase Suspend command is written during the Sector Erase operation, the device will take maximum
of “tSPD” to suspend the erase operation.
39
MB84VD2118XEG-85/MB84VD2119XEG-85
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
Address
CEf
555h
tWC
PA
PA
tRC
tAS
tAH
tCS
tCH
tCE
OE
tGHWL
tOE
tWHWH1
tWP
tWPH
WE
tOH
tDF
tDS
tDH
A0h
PD
DQ7
DOUT
DOUT
DQ
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode (the addresses differ from ×8 mode.)
40
MB84VD2118XEG-85/MB84VD2119XEG-85
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling
555h
tWC
PA
PA
Address
WE
tAS
tAH
tWS
tWH
OE
tGHEL
tWHWH1
tCP
tCPH
CEf
tDS
tDH
A0h
PD
DQ7
DOUT
DQ
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode (the addresses differ from ×8 mode.)
41
MB84VD2118XEG-85/MB84VD2119XEG-85
• AC Waveforms Chip/Sector Erase Operations (Flash)
SA*
Address
CEf
555h
tWC
2AAh
555h
555h
2AAh
tAS
tAH
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
30h for Sector Erase
10h/
30h
AAh
55h
80h
AAh
55h
DQ
tVCS
VCCf
* : SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
42
MB84VD2118XEG-85/MB84VD2119XEG-85
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tDF
tCH
tOE
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
DQ7
Data In
Data In
DQ7
Valid Data
tWHWH1 or 2
DQ
(DQ6 to DQ0)
DQ6 to DQ0
Valid Data
DQ6 to DQ0 = Output Flag
tEOE
tBUSY
RY/BY
* : DQ7 = Valid Data (the device has completed the Embedded operation.)
43
MB84VD2118XEG-85/MB84VD2119XEG-85
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO
tAHT tAS
CEf
WE
tCEPH
tOEH
tOEPH
tOEH
OE
tDH
tOE
*
tCE
Stop
Toggling
DQ6/DQ2
Toggle
Data
Toggle
Data
Toggle
Data
Output
Valid
Data
tBUSY
RY/BY
* : DQ6 stops toggling (the device has completed the Embedded operation) .
44
MB84VD2118XEG-85/MB84VD2119XEG-85
• Bank-to-Bank Read/Write Timing Diagram (Flash)
Read
Command
Read
Command
tWC
Read
tRC
Read
tRC
tRC
tWC
tRC
BA2
(555h)
BA2
(PA)
BA2
(PA)
Address
BA1
BA1
BA1
tACC
tAS
tAH
tAS
tAHT
tCE
CEf
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
tDS
WE
tDH
tDF
Valid
Output
Valid
Output
Valid
Intput
Valid
Output
Valid
Intput
Status
DQ
(A0h)
(PD)
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1.
BA2 : Address corresponding to Bank 2.
45
MB84VD2118XEG-85/MB84VD2119XEG-85
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
46
MB84VD2118XEG-85/MB84VD2119XEG-85
• Temporary Sector Group Unprotection (Flash)
VCCf
VID
tVIDR
tVLHT
tVCS
3 V
RESET
CEf
WE
tVLHT
tVLHT
Program or Erase Command Sequence
Unprotection Period
RY/BY
47
MB84VD2118XEG-85/MB84VD2119XEG-85
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
tWC
SPAX
SPAX
SPAY
Address
A6, A0
A1
CEf
OE
TIME - OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX : Sector Group Address to be protected
SPAY : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
48
MB84VD2118XEG-85/MB84VD2119XEG-85
• Accelerated Program (Flash)
VCCf
tVACCR
tVLHT
tVCS
VACC
VIH
WP/ACC
CEf
WE
tVLHT
tVLHT
Program Command Sequence
Acceleration Period
RY/BY
49
MB84VD2118XEG-85/MB84VD2119XEG-85
• Read Cycle (SRAM)
-70
-85
Parameter
Symbol
Unit
Min
Max
Min
Max
Read Cycle Time
tRC
tAA
70
85
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
70
35
70
85
85
85
45
85
Chip Enable (CE1s) Access Time
Chip Enable (CE2s) Access Time
Output Enable Access Time
UBs, LBs to Output Valid
tCO1
tCO2
tOE
tBA
Chip Enable (CE1s Low and CE2s High)
to Output Active
tCOE
5
5
ns
Output Enable Low to Output Active
UBs, LBs Enable Low to Output Active
tOEE
0
0
0
0
ns
ns
tBE
Chip Enable (CE1s High or CE2s Low)
to Output High-Z
tOD
25
35
ns
Output Enable High to Output High-Z
UBs, LBs Output Enable to Output High-Z
Output Data Hold Time
tODO
tBD
25
25
35
50
ns
ns
ns
tOH
10
10
Note : tAA = tCO1 = tCO2 = 80 ns (Max) , tOE = 38 ns (Max) at VCC = 2.7 V, TA = −30 °C to +60 °C, CL = 30 pF
Test Conditions : Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to 3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
50
MB84VD2118XEG-85/MB84VD2119XEG-85
• Read Cycle* (SRAM)
tRC
Address
CE1s
tAA
tOH
tCO1
tCOE
tOD
tCO2
CE2s
tOD
tOE
OE
tODO
tBD
tOEE
LBS, UBS
tBA
tBE
tCOE
DQ
Valid Data Out
* : WE remains “H” during for the read cycle.
51
MB84VD2118XEG-85/MB84VD2119XEG-85
• Write Cycle (SRAM)
-70
-85
Parameter
Symbol
Unit
Min
70
50
55
55
55
0
Max
Min
85
55
70
70
55
0
Max
Write Cycle Time
tWC
tWP
tCW
tAW
tBW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Address valid to End of Write
UBs, LBs to End of Write
Address Setup Time
Write Recovery Time
WE Low to Output High-Z
WE High to Output Active
Data Setup Time
tWR
tODW
tOEW
tDS
0
0
25
35
0
25
0
0
35
0
Data Hold Time
tDH
52
MB84VD2118XEG-85/MB84VD2119XEG-85
• Write Cycle*1 (WE control) (SRAM)
tWC
Address
WE
tAS
tWP
tWR
tAW
tCW
CE1s
CE2s
tCW
tBW
LBS, UBS
tODW
tOEW
DOUT
DIN
*2
*4
*3
*4
tDS
tDH
Valid Data In
*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2 : If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will remain
at High-Z.
*3 : If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will remain
at High-Z.
*4 : Because I/O signals may be in the output state at this time, input signals of reverse polarity must
not be applied.
53
MB84VD2118XEG-85/MB84VD2119XEG-85
• Write Cycle*1 (CE1s control) (SRAM)
tWC
Address
tAS
tWR
tWP
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LBS, UBS
tBE
tCOE
tODW
DOUT
DIN
tDS
tDH
Valid Data In
*2
*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2 : Because I/O signals may be in the output state at this time, input signals of reverse polarity must
not be applied.
54
MB84VD2118XEG-85/MB84VD2119XEG-85
• Write Cycle*1 (CE2s Control) (SRAM)
tWC
Address
WE
tAS
tWP
tWR
tCW
CE1s
CE2s
tAW
tCW
tBW
LBS, UBS
tBE
tCOE
tODW
DOUT
tDS
tDH
DIN
*2
Valid Data In
*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2 : Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
55
MB84VD2118XEG-85/MB84VD2119XEG-85
• Write Cycle*1 (LBs, UBs Control) (SRAM)
tWC
Address
tWP
tWR
WE
tCW
CE1s
CE2s
tCW
tAW
tBW
tAS
LBS, UBS
tBE
tCOE
tODW
DOUT
tDS
tDH
DIN
*2
Valid Data In
*1 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2 : Because I/O signals may be in the output state at this time, input signals of reverse polarity must
not be applied.
56
MB84VD2118XEG-85/MB84VD2119XEG-85
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limits
Typ
Parameter
Unit
Comment
Min
Max
Excludes programming time
prior to erasure
Sector Erase Time
1
8
10
s
Excludes system-level
overhead
Byte Programming Time
Word Programming Time
300
360
50
µs
µs
Excludes system-level
overhead
16
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
s
100,000
cycle
■ DATA RETENTION CHARACTERISTICS (SRAM)
Value
Unit
Parameter
Symbol
Min
Typ
Max
3.3
7
Data Retention Supply Voltage
VDH
IDDS2
tCDR
tR
1.5
V
Standby Current
VDH = 3.0 V
µA
ns
ns
Chip Deselect to Data Retention Mode Time
Recovery Time
0
tRC
Note : tRC : Read cycle time
• CE1s Controlled Data Retention Mode*1
VCCs
Data Retention Mode
2.7 V
*2
*2
VIH
VDH
VCCS − 0.2 V
CE1s
tCDR
tR
GND
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed VCCs to VCCs − 0.2 V or VSS
to 0.2 V during data retention mode. Other input and input/output pins can be used between −0.3 V to
VCCs + 0.3 V.
*2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition
of VCCs from 3.6 V to VIH Min level.
57
MB84VD2118XEG-85/MB84VD2119XEG-85
• CE2s Controlled Data Retention Mode
VCCs
Data Retention Mode
2.7 V
VDH
VIH
CE2s
tCDR
tR
VIL
0.2 V
GND
Note : In CE2s controlled data retention mode, input and input/output pins can be used between −0.3 V to VCCs
+ 0.3 V.
■ PACKAGE PIN CAPACITANCE
Value
Parameter
Symbol
Test Setup
Unit
Typ
11
Max
14
Input Capacitance
CIN
COUT
CIN2
CIN3
VIN = 0
pF
pF
pF
pF
Output Capacitance
VOUT = 0
VIN = 0
VIN = 0
12
16
Control Pin Capacitance
WP/ACC Pin Capacitance
14
16
17
20
Note : Test conditions TA = +25 °C, f = 1.0 MHz
■ HANDRING OF PACKAGE
Please handle this package carefully since the sides of package are created with acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when use
autoselect and sector Group Protection function are used. Then the high voltage can be applied to RESET.
• Without the high voltage (VID) , Sector Group Protection can be achieved by using “Extended Sector Group
Protection” command.
58
MB84VD2118XEG-85/MB84VD2119XEG-85
■ ORDERING INFORMATION
MB84VD2118
X
EG
-70
-PBS
PACKAGE TYPE
PBS = 56-ball FBGA
SPEED OPTION
Device Revision (Valid Combination)
EG
Bank Size
1 = 0.5 Mbit / 15.5 Mbit
2 = 2 Mbit / 14 Mbit
3 = 4 Mbit / 12 Mbit
4 = 8 Mbit /
8 Mbit
DEVICE NUMBER/DESCRIPTION
16 Mega-bit (2 M × 8-bit or 1 M × 16-bit) Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
4 Mega-bit (512 K × 8-bit or 256 K × 16-bit) SRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2118 = Top sector
84VD2119 = Bottom sector
59
MB84VD2118XEG-85/MB84VD2119XEG-85
■ PACKAGE DIMENSION
56-ball plastic FBGA
(BGA-56P-M01)
7.20±0.10(.283±.004)
1.05 ±+00..1105
.041 –+..000046
(Mounting height)
(Stand off)
5.60(.220)REF
0.38±0.10
(.015±.004)
0.80
(.031)
8
7
6
5
4
3
2
1
5.60(.220)
7.00±0.10
(.276±.004)
REF
0.80
(.031)
H
G
F
E
D
C
B
A
INDEX-MARK AREA
INDEX
56-Ø0.45 –+00..0150
56-Ø.018 –+..000024
M
0.08(.003)
0.10(.004)
C
2000 FUJITSU LIMITED B56001S-1c-1
Dimension in mm (inches)
60
MB84VD2118XEG-85/MB84VD2119XEG-85
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
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assumes no liability for any damages whatsoever arising out of
the use of the information.
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function and schematic diagrams, shall not be construed as license
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party or does Fujitsu warrant non-infringement of any third-party’s
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Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
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equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
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technologies subject to certain restrictions on export under the
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of those products from Japan.
F0302
FUJITSU LIMITED Printed in Japan
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