MB84VD22193EH-90PBS [FUJITSU]
Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA71, PLASTIC, BGA-71;
| 型号： | MB84VD22193EH-90PBS |
| 厂家： | 
FUJITSU |
| 描述： | Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA71, PLASTIC, BGA-71 静态存储器 内存集成电路 |
| 文件： | 总64页 (文件大小：1189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50219-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
32 M (×8/×16) FLASH MEMORY &
4 M (×8/×16) STATIC RAM
MB84VD2218XEA/2218XEH-70/85/90
MB84VD2219XEA/2218XEH-70/85/90
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.3 V
• High Performance
70 ns/85 ns/90 ns maximum access time (Flash)
70 ns/85 ns maximum access time (SRAM)
• Operating Temperature
−25 °C to +85 °C
• Package 71-ball BGA
(Continued)
■ PRODUCT LINE UP
Flash Memory
SRAM
-70
-85
-90
-70
-85/-90
+0.3 V
−0.3 V
+0.3 V
−0.3 V
Power Supply Voltage (V)
VCCf* = 3.0 V
VCCs* = 3.0 V
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
70
70
30
85
85
35
90
90
40
70
70
35
85
85
45
■ PACKAGE
71-ball plastic BGA
(BGA-71P-M02)
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
- FLASH MEMORY
• Simultaneous Read/Write Operations (dual bank)
Multiple devices available with different bank sizes (Refer to ■ PIN DESCRIPTION)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4 K words and sixty three 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2218X : Top sector
MB84VD2219X : Bottom sector
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC Write Inhibit ≤ 2.5 V
• Hidden ROM (Hi-ROM) Region
64 K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2218XEA/H : SA69, SA70 MB84VD2219XEA/H : SA0, SA1)
At VIH, allows removal of boot sector protection
At VACC, program time will reduce by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL32XTE/BE” Datasheet in Detailed Function
- SRAM
• Power Dissipation
Operating : 40 mA Max
Standby : 7 µA Max
• Power Down Features Using CE1s and CE2s
• Data Retention Supply Voltage : 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control : LBs (DQ0-DQ7) , UBs (DQ8-DQ15)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ PIN ASSIGNMENT
(Top View)
Marking side
A8
B8
D8
E8
F8
G8
H8
J8
M8
L8
N.C.
N.C.
A15
N.C.
N.C.
A16
CIOf
VSS
N.C.
N.C.
A7
B7
C7
D7
E7
F7
G7
SA
H7
J7
K7
L7
M7
N.C.
N.C.
A11
A12
A13
A14
DQ15/
A-1
DQ7
DQ14
N.C.
N.C.
C6
A8
D6
E6
A9
F6
G6
H6
J6
K6
A19
A10
DQ6
DQ13
DQ12
DQ5
C5
D5
E5
H5
J5
K5
WE
CE2s
A20
DQ4
VCCs CIOs
C4
D4
E4
H4
J4
K4
WP/ RESET RY/BY
ACC
DQ3
VCCf
DQ11
C3
D3
E3
F3
G3
H3
J3
K3
LBs
UBs
A18
A17
DQ1
DQ9
DQ10
DQ2
A2
C2
A7
D2
A6
E2
A5
F2
A4
G2
H2
J2
K2
L2
M2
N.C.
VSS
OE
DQ0
DQ8
N.C.
N.C.
A1
B1
D1
A3
E1
A2
F1
A1
G1
A0
H1
J1
L1
M1
N.C.
N.C.
CEf
CE1s
N.C.
N.C.
(BGA-71P-M02)
3
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ PIN DESCRIPTION
Pin
A17 to A0
A20 to A18, A-1
SA
Function
Input/Output
Address Inputs (Common)
Address Input (Flash)
Address Input (SRAM)
I
I
I
DQ15 to DQ0
CEf
Data Inputs/Outputs (Common)
Chip Enable (Flash)
I/O
I
I
CE1s
Chip Enable (SRAM)
CE2s
Chip Enable (SRAM)
I
OE
Output Enable (Common)
Write Enable (Common)
I
WE
I
RY/BY
UBs
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
O
I
LBs
I
I/O Configuration (Flash)
CIOf = Vccf is Word mode (×16) , CIOf = Vss Byte mode (×8)
CIOf
I
I
I/O Configuration (SRAM)
CIOs = Vccs is Word mode (×16) , CIOs = Vss is Byte mode (×8)
CIOs
RESET
WP/ACC
N.C.
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect/Acceleration (Flash)
No Internal Connection
I
I
VSS
Device Ground (Common)
Power
Power
Power
VCCf
Device Power Supply (Flash)
VCCs
Device Power Supply (SRAM)
4
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ BLOCK DIAGRAM
VCCf
VSS
A0 to A20
RY/BY
A20 to A0
A-1
WP/ACC
RESET
CEf
32 M bit
Flash Memory
DQ15/A-1 to DQ0
CIOf
DQ15/A-1 to DQ0
VCCs
VSS
A0 to A17
DQ15 to DQ0
4 M bit
SA
LBs
Static RAM
UBs
WE
OE
CE1s
CE2s
CIOs
5
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ DEVICE BUS OPERATION
User Bus Operations Table (Flash = Word mode; CIOf = Vccf, SRAM = Word mode; CIOs = Vccs)
WP/
SA
*
Operation *1, *3
CEf CE1s CE2s OE WE
LBs UBs DQ0 to DQ7 DQ8 to DQ15 RESET ACC
6
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
High-Z
High-Z
H
H
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
X
H
X
H
X
X
L
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
DOUT
DIN
Read from Flash *2
Write to Flash
L
H
H
X
X
L
H
L
H
L
L
L
DOUT
High-Z
DOUT
DOUT
DOUT
High-Z
DIN
Read from SRAM
Write to SRAM
H
L
H
L
H
X
H
X
H
L
L
DIN
H
X
L
H
X
X
X
L
X
X
H
L
L
High-Z
DIN
DIN
H
X
X
H
High-Z
Temporary Sector
Group
Unprotection *4
X
X
X
X
X
X
VID
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ DC CHARACTERISTICS” for voltage levels.
*1: Other operations not indicated in this column are prohibited.
*2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4: Also used for the extended sector group protections.
*5: WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9 V) ; Program time will be reduced by 40%.
*6: SA : Don’t care or Open.
6
MB84VD2218XEA/H/2219XEA/H-70/85/90
User Bus Operations Table (Flash = Word mode; CIOf = Vccf, SRAM = Byte mode; CIOs = Vss)
WP/
LBs UBs
Operation *1, *3
CEf CE1s CE2s OE WE SA
DQ0 to DQ7 DQ8 to DQ15 RESET ACC
6
6
*
*
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
High-Z
High-Z
H
H
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
X
H
X
H
X
L
X
L
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
DOUT
DIN
X
L
Read from Flash *2
Write to Flash
L
H
H
X
X
X
L
L
H
Read from SRAM
Write to SRAM
H
H
H
H
L
H
L
SA
SA
X
X
X
X
DOUT
DIN
High-Z
High-Z
H
H
X
X
L
X
Temporary Sector
Group
Unprotection *4
X
X
X
X
X
X
X
X
X
X
VID
X
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ DC CHARACTERISTICS” for voltage levels.
*1: Other operations not indicated in this column are prohibited.
*2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4: Also used for the extended sector group protections.
*5: WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9 V) ; Program time will be reduced by 40%.
*6: LBS , UBS : Don’t care or Open.
7
MB84VD2218XEA/H/2219XEA/H-70/85/90
User Bus Operations Table (Flash = Byte mode; CIOf = Vss, SRAM = Byte mode; CIOs = Vss)
WP/
LBs UBs
DQ0 to
DQ7
DQ8 to
DQ14
Operation *1, *3
ACC
CEf CE1s CE2s DQ15/A-1 OE WE SA
RESET
6
6
*
*
5
*
H
X
X
L
Full Standby
H
H
L
X
X
X
X
X
X
High-Z
High-Z
H
X
X
X
X
H
X
H
X
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
L
H
Output Disable
H
H
X
H
X
H
X
L
X
L
A-1
A-1
A-1
H
L
H
H
L
X
X
X
X
X
X
X
X
X
High-Z
DOUT
DIN
High-Z
X
L
Read from Flash *2
Write to Flash
L
X
X
H
H
X
X
X
L
L
H
Read from SRAM
Write to SRAM
H
H
H
H
X
X
L
H
L
SA
SA
X
X
X
X
DOUT
DIN
High-Z
High-Z
H
H
X
X
L
X
Temporary Sector
Group
Unprotection *4
X
X
X
X
X
X
X
X
X
X
X
VID
X
H
X
X
L
Flash Hardware
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
X
High-Z
X
L
X
L
Boot Block Sector
Write Protection
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “■ DC CHARACTERISTICS” for voltage levels.
*1: Other operations not indicated in this column are prohibited.
*2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*4: Also used for the extended sector group protections.
*5: WP/ACC = VIL ; protection of boot sectors.
WP/ACC = VIH ; removal of boot sectors protection.
WP/ACC = VACC (9 V) ; Program time will be reduced by 40%.
*6: LBS , UBS : Don’t care or Open.
8
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Eight 4 K words, and sixty three 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Word Mode Byte Mode
1FFFFFh 3FFFFFh
SA70 : 8 KB (4 KW)
1FF000h
3FE000h
SA69 : 8 KB (4 KW)
SA68 : 8 KB (4 KW)
SA67 : 8 KB (4 KW)
SA66 : 8 KB (4 KW)
SA65 : 8 KB (4 KW)
SA64 : 8 KB (4 KW)
SA63 : 8 KB (4 KW)
SA62 : 64 KB (32 KW)
SA61 : 64 KB (32 KW)
SA60 : 64 KB (32 KW)
SA59 : 64 KB (32 KW)
SA58 : 64 KB (32 KW)
SA57 : 64 KB (32 KW)
SA56 : 64 KB (32 KW)
SA55 : 64 KB (32 KW)
SA54 : 64 KB (32 KW)
SA53 : 64 KB (32 KW)
SA52 : 64 KB (32 KW)
SA51 : 64 KB (32 KW)
SA50 : 64 KB (32 KW)
SA49 : 64 KB (32 KW)
SA48 : 64 KB (32 KW)
SA47 : 64 KB (32 KW)
SA46 : 64 KB (32 KW)
SA45 : 64 KB (32 KW)
SA44 : 64 KB (32 KW)
SA43 : 64 KB (32 KW)
SA42 : 64 KB (32 KW)
SA41 : 64 KB (32 KW)
SA40 : 64 KB (32 KW)
SA39 : 64 KB (32 KW)
SA38 : 64 KB (32 KW)
SA37 : 64 KB (32 KW)
SA36 : 64 KB (32 KW)
SA35 : 64 KB (32 KW)
SA34 : 64 KB (32 KW)
SA33 : 64 KB (32 KW)
SA32 : 64 KB (32 KW)
SA31 : 64 KB (32 KW)
SA30 : 64 KB (32 KW)
SA29 : 64 KB (32 KW)
SA28 : 64 KB (32 KW)
SA27 : 64 KB (32 KW)
SA26 : 64 KB (32 KW)
SA25 : 64 KB (32 KW)
SA24 : 64 KB (32 KW)
SA23 : 64 KB (32 KW)
SA22 : 64 KB (32 KW)
SA21 : 64 KB (32 KW)
SA20 : 64 KB (32 KW)
SA19 : 64 KB (32 KW)
SA18 : 64 KB (32 KW)
SA17 : 64 KB (32 KW)
SA16 : 64 KB (32 KW)
SA15 : 64 KB (32 KW)
SA14 : 64 KB (32 KW)
SA13 : 64 KB (32 KW)
SA12 : 64 KB (32 KW)
SA11 : 64 KB (32 KW)
SA10 : 64 KB (32 KW)
SA9 : 64 KB (32 KW)
SA8 : 64 KB (32 KW)
SA7 : 64 KB (32 KW)
SA6 : 64 KB (32 KW)
SA5 : 64 KB (32 KW)
SA4 : 64 KB (32 KW)
SA3 : 64 KB (32 KW)
SA2 : 64 KB (32 KW)
SA1 : 64 KB (32 KW)
SA0 : 64 KB (32 KW)
1FE000h 3FC000h
1FD000h
1FC000h
1FB000h
1FA000h
1F9000h
1F8000h
1F0000h
1E8000h
1E0000h
1D8000h
1D0000h
1C8000h
1C0000h
1B8000h
1B0000h
1A8000h
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
000000h
3FA000h
3F8000h
3F6000h
3F4000h
3F2000h
3F0000h
3E0000h
3D0000h
3C0000h
3B0000h
3A0000h
390000h
380000h
370000h
360000h
350000h
340000h
330000h
320000h
310000h
300000h
2F0000h
2E0000h
2D0000h
2C0000h
2B0000h
2A0000h
290000h
280000h
270000h
260000h
250000h
240000h
230000h
220000h
210000h
200000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
000000h
Bank 1
MB84VD22182EA/H
Bank 1
MB84VD22183EA/H
Bank 1
MB84VD22184EA/H
Bank 2
MB84VD22182EA/H
Bank 2
MB84VD22183EA/H
Bank 2
MB84VD22184EA/H
MB84VD2218XEA/H Sector Architecture (Top Boot Block)
(Continued)
9
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Word Mode Byte Mode
1FFFFFh
3FFFFFh
3F0000h
3E0000h
3D0000h
3C0000h
3B0000h
3A0000h
390000h
380000h
370000h
360000h
350000h
340000h
330000h
320000h
310000h
300000h
2F0000h
2E0000h
2D0000h
2C0000h
2B0000h
2A0000h
290000h
280000h
270000h
260000h
250000h
240000h
230000h
220000h
210000h
200000h
1F0000h
1E0000h
1D0000h
1C0000h
1B0000h
1A0000h
190000h
180000h
170000h
160000h
150000h
140000h
130000h
120000h
110000h
100000h
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
090000h
080000h
070000h
060000h
050000h
040000h
030000h
020000h
010000h
00E000h
00C000h
00A000h
008000h
006000h
004000h
002000h
000000h
SA70 : 64 KB (32 KW)
SA69 : 64 KB (32 KW)
SA68 : 64 KB (32 KW)
SA67 : 64 KB (32 KW)
SA66 : 64 KB (32 KW)
SA65 : 64 KB (32 KW)
SA64 : 64 KB (32 KW)
SA63 : 64 KB (32 KW)
SA62 : 64 KB (32 KW)
SA61 : 64 KB (32 KW)
SA60 : 64 KB (32 KW)
SA59 : 64 KB (32 KW)
SA58 : 64 KB (32 KW)
SA57 : 64 KB (32 KW)
SA56 : 64 KB (32 KW)
SA55 : 64 KB (32 KW)
SA54 : 64 KB (32 KW)
SA53 : 64 KB (32 KW)
SA52 : 64 KB (32 KW)
SA51 : 64 KB (32 KW)
SA50 : 64 KB (32 KW)
SA49 : 64 KB (32 KW)
SA48 : 64 KB (32 KW)
SA47 : 64 KB (32 KW)
SA46 : 64 KB (32 KW)
SA45 : 64 KB (32 KW)
SA44 : 64 KB (32 KW)
SA43 : 64 KB (32 KW)
SA42 : 64 KB (32 KW)
SA41 : 64 KB (32 KW)
SA40 : 64 KB (32 KW)
SA39 : 64 KB (32 KW)
SA38 : 64 KB (32 KW)
SA37 : 64 KB (32 KW)
SA36 : 64 KB (32 KW)
SA35 : 64 KB (32 KW)
SA34 : 64 KB (32 KW)
SA33 : 64 KB (32 KW)
SA32 : 64 KB (32 KW)
SA31 : 64 KB (32 KW)
SA30 : 64 KB (32 KW)
SA29 : 64 KB (32 KW)
SA28 : 64 KB (32 KW)
SA27 : 64 KB (32 KW)
SA26 : 64 KB (32 KW)
SA25 : 64 KB (32 KW)
SA24 : 64 KB (32 KW)
SA23 : 64 KB (32 KW)
SA22 : 64 KB (32 KW)
SA21 : 64 KB (32 KW)
SA20 : 64 KB (32 KW)
SA19 : 64 KB (32 KW)
SA18 : 64 KB (32 KW)
SA17 : 64 KB (32 KW)
SA16 : 64 KB (32 KW)
SA15 : 64 KB (32 KW)
SA14 : 64 KB (32 KW)
SA13 : 64 KB (32 KW)
SA12 : 64 KB (32 KW)
SA11 : 64 KB (32 KW)
SA10 : 64 KB (32 KW)
SA9 : 64 KB (32 KW)
SA8 : 64 KB (32 KW)
1F8000h
1F0000h
1E8000h
1E0000h
1D8000h
1D0000h
1C8000h
1C0000h
1B8000h
1B0000h
1A8000h
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
Bank 2
MB84VD22194EA/H
Bank 2
MB84VD22193EA/H
Bank 2
MB84VD22192EA/H
Bank 1
MB84VD22194EA/H
Bank 1
MB84VD22193EA/H
Bank 1
MB84VD22192EA/H
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
:
:
:
:
:
:
:
:
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
8 KB (4 KW)
MB84VD2219XEA/H Sector Architecture (Bottom Boot Block)
10
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address Table (MB84VD22182EA/H)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 00FFFFh 000000h to 007FFFh
010000h to 01FFFFh 008000h to 00FFFFh
020000h to 02FFFFh 010000h to 017FFFh
030000h to 03FFFFh 018000h to 01FFFFh
040000h to 04FFFFh 020000h to 027FFFh
050000h to 05FFFFh 028000h to 02FFFFh
060000h to 06FFFFh 030000h to 037FFFh
070000h to 07FFFFh 038000h to 03FFFFh
080000h to 08FFFFh 040000h to 047FFFh
090000h to 09FFFFh 048000h to 04FFFFh
0A0000h to 0AFFFFh 050000h to 057FFFh
0B0000h to 0BFFFFh 058000h to 05FFFFh
0C0000h to 0CFFFFh 060000h to 067FFFh
0D0000h to 0DFFFFh 068000h to 06FFFFh
0E0000h to 0EFFFFh 070000h to 077FFFh
0F0000h to 0FFFFFh 078000h to 07FFFFh
100000h to 10FFFFh 080000h to 087FFFh
110000h to 11FFFFh 088000h to 08FFFFh
120000h to 12FFFFh 090000h to 097FFFh
130000h to 13FFFFh 098000h to 09FFFFh
140000h to 14FFFFh 0A0000h to 0A7FFFh
150000h to 15FFFFh 0A8000h to 0AFFFFh
160000h to 16FFFFh 0B0000h to 0B7FFFh
170000h to 17FFFFh 0B8000h to 0BFFFFh
180000h to 18FFFFh 0C0000h to 0C7FFFh
190000h to 19FFFFh 0C8000h to 0CFFFFh
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Bank
2
(Continued)
BA : Bank Address
11
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
200000h to 20FFFFh 100000h to 107FFFh
210000h to 21FFFFh 108000h to 10FFFFh
220000h to 22FFFFh 110000h to 117FFFh
230000h to 23FFFFh 118000h to 11FFFFh
240000h to 24FFFFh 120000h to 127FFFh
250000h to 25FFFFh 128000h to 12FFFFh
260000h to 26FFFFh 130000h to 137FFFh
270000h to 27FFFFh 138000h to 13FFFFh
280000h to 28FFFFh 140000h to 147FFFh
290000h to 29FFFFh 148000h to 14FFFFh
2A0000h to 2AFFFFh 150000h to 157FFFh
2B0000h to 2BFFFFh 158000h to 15FFFFh
2C0000h to 2CFFFFh 160000h to 167FFFh
2D0000h to 2DFFFFh 168000h to 16FFFFh
2E0000h to 2EFFFFh 170000h to 177FFFh
2F0000h to 2FFFFFh 178000h to 17FFFFh
300000h to 30FFFFh 180000h to 187FFFh
310000h to 31FFFFh 188000h to 18FFFFh
320000h to 32FFFFh 190000h to 197FFFh
330000h to 33FFFFh 198000h to 19FFFFh
340000h to 34FFFFh 1A0000h to 1A7FFFh
350000h to 35FFFFh 1A8000h to 1AFFFFh
360000h to 36FFFFh 1B0000h to 1B7FFFh
370000h to 37FFFFh 1B8000h to 1BFFFFh
380000h to 38FFFFh 1C0000h to 1C7FFFh
390000h to 39FFFFh 1C8000h to 1CFFFFh
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
Bank
2
Bank
1
0
0
1
0
1
0
3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
(Continued)
12
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
X
X
X
X
X
3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
3FA000h to 3FAFFFh 1FD000h to 1FDFFFh
3FC000h to 3FCFFFh 1FE000h to 1FEFFFh
3FE000h to 3FFFFFh 1FF000h to 1FFFFFh
Bank
1
13
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address Table (MB84VD22192EA/H)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 001FFFh 000000h to 000FFFh
002000h to 003FFFh 001000h to 001FFFh
004000h to 005FFFh 002000h to 002FFFh
006000h to 007FFFh 003000h to 003FFFh
008000h to 009FFFh 004000h to 004FFFh
00A000h to 00BFFFh 005000h to 005FFFh
00C000h to 00DFFFh 006000h to 006FFFh
00E000h to 00FFFFh 007000h to 007FFFh
010000h to 01FFFFh 008000h to 00FFFFh
020000h to 02FFFFh 010000h to 017FFFh
030000h to 03FFFFh 018000h to 01FFFFh
040000h to 04FFFFh 020000h to 027FFFh
050000h to 05FFFFh 028000h to 02FFFFh
060000h to 06FFFFh 030000h to 037FFFh
070000h to 07FFFFh 038000h to 03FFFFh
080000h to 08FFFFh 040000h to 047FFFh
090000h to 09FFFFh 048000h to 04FFFFh
0A0000h to 0AFFFFh 050000h to 057FFFh
0B0000h to 0BFFFFh 058000h to 05FFFFh
0C0000h to 0CFFFFh 060000h to 067FFFh
0D0000h to 0DFFFFh 068000h to 06FFFFh
0E0000h to 0EFFFFh 070000h to 077FFFh
0F0000h to 0FFFFFh 078000h to 07FFFFh
100000h to 10FFFFh 080000h to 087FFFh
110000h to 11FFFFh 088000h to 08FFFFh
120000h to 12FFFFh 090000h to 097FFFh
130000h to 13FFFFh 098000h to 09FFFFh
140000h to 14FFFFh 0A0000h to 0A7FFFh
150000h to 15FFFFh 0A8000h to 0AFFFFh
160000h to 16FFFFh 0B0000h to 0B7FFFh
170000h to 17FFFFh 0B8000h to 0BFFFFh
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
Bank
1
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Bank
2
(Continued)
14
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
200000h to 20FFFFh 100000h to 107FFFh
210000h to 21FFFFh 108000h to 10FFFFh
220000h to 22FFFFh 110000h to 117FFFh
230000h to 23FFFFh 118000h to 11FFFFh
240000h to 24FFFFh 120000h to 127FFFh
250000h to 25FFFFh 128000h to 12FFFFh
260000h to 26FFFFh 130000h to 137FFFh
270000h to 27FFFFh 138000h to 13FFFFh
280000h to 28FFFFh 140000h to 147FFFh
290000h to 29FFFFh 148000h to 14FFFFh
2A0000h to 2AFFFFh 150000h to 157FFFh
2B0000h to 2BFFFFh 158000h to 15FFFFh
2C0000h to 2CFFFFh 160000h to 167FFFh
2D0000h to 2DFFFFh 168000h to 16FFFFh
2E0000h to 2EFFFFh 170000h to 177FFFh
2F0000h to 2FFFFFh 178000h to 17FFFFh
300000h to 30FFFFh 180000h to 187FFFh
310000h to 31FFFFh 188000h to 18FFFFh
320000h to 32FFFFh 190000h to 197FFFh
330000h to 33FFFFh 198000h to 19FFFFh
340000h to 34FFFFh 1A0000h to 1A7FFFh
350000h to 35FFFFh 1A8000h to 1AFFFFh
360000h to 36FFFFh 1B0000h to 1B7FFFh
370000h to 37FFFFh 1B8000h to 1BFFFFh
380000h to 38FFFFh 1C0000h to 1C7FFFh
390000h to 39FFFFh 1C8000h to 1CFFFFh
Bank
2
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
(Continued)
15
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
Bank
2
BA : Bank Address
16
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address Table (MB84VD22183EA/H)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 00FFFFh 000000h to 007FFFh
010000h to 01FFFFh 008000h to 00FFFFh
020000h to 02FFFFh 010000h to 017FFFh
030000h to 03FFFFh 018000h to 01FFFFh
040000h to 04FFFFh 020000h to 027FFFh
050000h to 05FFFFh 028000h to 02FFFFh
060000h to 06FFFFh 030000h to 037FFFh
070000h to 07FFFFh 038000h to 03FFFFh
080000h to 08FFFFh 040000h to 047FFFh
090000h to 09FFFFh 048000h to 04FFFFh
0A0000h to 0AFFFFh 050000h to 057FFFh
0B0000h to 0BFFFFh 058000h to 05FFFFh
0C0000h to 0CFFFFh 060000h to 067FFFh
0D0000h to 0DFFFFh 068000h to 06FFFFh
0E0000h to 0EFFFFh 070000h to 077FFFh
0F0000h to 0FFFFFh 078000h to 07FFFFh
100000h to 10FFFFh 080000h to 087FFFh
110000h to 11FFFFh 088000h to 08FFFFh
120000h to 12FFFFh 090000h to 097FFFh
130000h to 13FFFFh 098000h to 09FFFFh
140000h to 14FFFFh 0A0000h to 0A7FFFh
150000h to 15FFFFh 0A8000h to 0AFFFFh
160000h to 16FFFFh 0B0000h to 0B7FFFh
170000h to 17FFFFh 0B8000h to 0BFFFFh
180000h to 18FFFFh 0C0000h to 0C7FFFh
190000h to 19FFFFh 0C8000h to 0CFFFFh
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Bank
2
(Continued)
BA : Bank Address
17
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
200000h to 20FFFFh 100000h to 107FFFh
210000h to 21FFFFh 108000h to 10FFFFh
220000h to 22FFFFh 110000h to 117FFFh
230000h to 23FFFFh 118000h to 11FFFFh
240000h to 24FFFFh 120000h to 127FFFh
250000h to 25FFFFh 128000h to 12FFFFh
260000h to 26FFFFh 130000h to 137FFFh
270000h to 27FFFFh 138000h to 13FFFFh
280000h to 28FFFFh 140000h to 147FFFh
290000h to 29FFFFh 148000h to 14FFFFh
2A0000h to 2AFFFFh 150000h to 157FFFh
2B0000h to 2BFFFFh 158000h to 15FFFFh
2C0000h to 2CFFFFh 160000h to 167FFFh
2D0000h to 2DFFFFh 168000h to 16FFFFh
2E0000h to 2EFFFFh 170000h to 177FFFh
2F0000h to 2FFFFFh 178000h to 17FFFFh
300000h to 30FFFFh 180000h to 187FFFh
310000h to 31FFFFh 188000h to 18FFFFh
320000h to 32FFFFh 190000h to 197FFFh
330000h to 33FFFFh 198000h to 19FFFFh
340000h to 34FFFFh 1A0000h to 1A7FFFh
350000h to 35FFFFh 1A8000h to 1AFFFFh
360000h to 36FFFFh 1B0000h to 1B7FFFh
370000h to 37FFFFh 1B8000h to 1BFFFFh
380000h to 38FFFFh 1C0000h to 1C7FFFh
390000h to 39FFFFh 1C8000h to 1CFFFFh
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
Bank
2
Bank
1
0
0
1
0
1
0
3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
(Continued)
18
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
X
X
X
X
X
3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
3FA000h to 3FAFFFh 1FD000h to 1FDFFFh
3FC000h to 3FCFFFh 1FE000h to 1FEFFFh
3FE000h to 3FFFFFh 1FF000h to 1FFFFFh
Bank
1
19
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address Table (MB84VD22193EA/H)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 001FFFh 000000h to 000FFFh
002000h to 003FFFh 001000h to 001FFFh
004000h to 005FFFh 002000h to 002FFFh
006000h to 007FFFh 003000h to 003FFFh
008000h to 009FFFh 004000h to 004FFFh
00A000h to 00BFFFh 005000h to 005FFFh
00C000h to 00DFFFh 006000h to 006FFFh
00E000h to 00FFFFh 007000h to 007FFFh
010000h to 01FFFFh 008000h to 00FFFFh
020000h to 02FFFFh 010000h to 017FFFh
030000h to 03FFFFh 018000h to 01FFFFh
040000h to 04FFFFh 020000h to 027FFFh
050000h to 05FFFFh 028000h to 02FFFFh
060000h to 06FFFFh 030000h to 037FFFh
070000h to 07FFFFh 038000h to 03FFFFh
080000h to 08FFFFh 040000h to 047FFFh
090000h to 09FFFFh 048000h to 04FFFFh
0A0000h to 0AFFFFh 050000h to 057FFFh
0B0000h to 0BFFFFh 058000h to 05FFFFh
0C0000h to 0CFFFFh 060000h to 067FFFh
0D0000h to 0DFFFFh 068000h to 06FFFFh
0E0000h to 0EFFFFh 070000h to 077FFFh
0F0000h to 0FFFFFh 078000h to 07FFFFh
100000h to 10FFFFh 080000h to 087FFFh
110000h to 11FFFFh 088000h to 08FFFFh
120000h to 12FFFFh 090000h to 097FFFh
130000h to 13FFFFh 098000h to 09FFFFh
140000h to 14FFFFh 0A0000h to 0A7FFFh
150000h to 15FFFFh 0A8000h to 0AFFFFh
160000h to 16FFFFh 0B0000h to 0B7FFFh
170000h to 17FFFFh 0B8000h to 0BFFFFh
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Bank
1
Bank
2
(Continued)
20
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
200000h to 20FFFFh 100000h to 107FFFh
210000h to 21FFFFh 108000h to 10FFFFh
220000h to 22FFFFh 110000h to 117FFFh
230000h to 23FFFFh 118000h to 11FFFFh
240000h to 24FFFFh 120000h to 127FFFh
250000h to 25FFFFh 128000h to 12FFFFh
260000h to 26FFFFh 130000h to 137FFFh
270000h to 27FFFFh 138000h to 13FFFFh
280000h to 28FFFFh 140000h to 147FFFh
290000h to 29FFFFh 148000h to 14FFFFh
2A0000h to 2AFFFFh 150000h to 157FFFh
2B0000h to 2BFFFFh 158000h to 15FFFFh
2C0000h to 2CFFFFh 160000h to 167FFFh
2D0000h to 2DFFFFh 168000h to 16FFFFh
2E0000h to 2EFFFFh 170000h to 177FFFh
2F0000h to 2FFFFFh 178000h to 17FFFFh
300000h to 30FFFFh 180000h to 187FFFh
310000h to 31FFFFh 188000h to 18FFFFh
320000h to 32FFFFh 190000h to 197FFFh
330000h to 33FFFFh 198000h to 19FFFFh
340000h to 34FFFFh 1A0000h to 1A7FFFh
350000h to 35FFFFh 1A8000h to 1AFFFFh
360000h to 36FFFFh 1B0000h to 1B7FFFh
370000h to 37FFFFh 1B8000h to 1BFFFFh
380000h to 38FFFFh 1C0000h to 1C7FFFh
390000h to 39FFFFh 1C8000h to 1CFFFFh
Bank
2
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
(Continued)
21
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
Bank
2
BA : Bank Address
22
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address Table (MB84VD22184EA/E)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 00FFFFh 000000h to 007FFFh
010000h to 01FFFFh 008000h to 00FFFFh
020000h to 02FFFFh 010000h to 017FFFh
030000h to 03FFFFh 018000h to 01FFFFh
040000h to 04FFFFh 020000h to 027FFFh
050000h to 05FFFFh 028000h to 02FFFFh
060000h to 06FFFFh 030000h to 037FFFh
070000h to 07FFFFh 038000h to 03FFFFh
080000h to 08FFFFh 040000h to 047FFFh
090000h to 09FFFFh 048000h to 04FFFFh
0A0000h to 0AFFFFh 050000h to 057FFFh
0B0000h to 0BFFFFh 058000h to 05FFFFh
0C0000h to 0CFFFFh 060000h to 067FFFh
0D0000h to 0DFFFFh 068000h to 06FFFFh
0E0000h to 0EFFFFh 070000h to 077FFFh
0F0000h to 0FFFFFh 078000h to 07FFFFh
100000h to 10FFFFh 080000h to 087FFFh
110000h to 11FFFFh 088000h to 08FFFFh
120000h to 12FFFFh 090000h to 097FFFh
130000h to 13FFFFh 098000h to 09FFFFh
140000h to 14FFFFh 0A0000h to 0A7FFFh
150000h to 15FFFFh 0A8000h to 0AFFFFh
160000h to 16FFFFh 0B0000h to 0B7FFFh
170000h to 17FFFFh 0B8000h to 0BFFFFh
180000h to 18FFFFh 0C0000h to 0C7FFFh
190000h to 19FFFFh 0C8000h to 0CFFFFh
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Bank
2
(Continued)
BA : Bank Address
23
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
200000h to 20FFFFh 100000h to 107FFFh
210000h to 21FFFFh 108000h to 10FFFFh
220000h to 22FFFFh 110000h to 117FFFh
230000h to 23FFFFh 118000h to 11FFFFh
240000h to 24FFFFh 120000h to 127FFFh
250000h to 25FFFFh 128000h to 12FFFFh
260000h to 26FFFFh 130000h to 137FFFh
270000h to 27FFFFh 138000h to 13FFFFh
280000h to 28FFFFh 140000h to 147FFFh
290000h to 29FFFFh 148000h to 14FFFFh
2A0000h to 2AFFFFh 150000h to 157FFFh
2B0000h to 2BFFFFh 158000h to 15FFFFh
2C0000h to 2CFFFFh 160000h to 167FFFh
2D0000h to 2DFFFFh 168000h to 16FFFFh
2E0000h to 2EFFFFh 170000h to 177FFFh
2F0000h to 2FFFFFh 178000h to 17FFFFh
300000h to 30FFFFh 180000h to 187FFFh
310000h to 31FFFFh 188000h to 18FFFFh
320000h to 32FFFFh 190000h to 197FFFh
330000h to 33FFFFh 198000h to 19FFFFh
340000h to 34FFFFh 1A0000h to 1A7FFFh
350000h to 35FFFFh 1A8000h to 1AFFFFh
360000h to 36FFFFh 1B0000h to 1B7FFFh
370000h to 37FFFFh 1B8000h to 1BFFFFh
380000h to 38FFFFh 1C0000h to 1C7FFFh
390000h to 39FFFFh 1C8000h to 1CFFFFh
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
3F0000h to 3F1FFFh 1F8000h to 1F8FFFh
3F2000h to 3F3FFFh 1F9000h to 1F9FFFh
Bank
1
0
0
1
0
1
0
3F4000h to 3F5FFFh 1FA000h to 1FAFFFh
(Continued)
24
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
X
X
X
X
X
3F6000h to 3F7FFFh 1FB000h to 1FBFFFh
3F8000h to 3F9FFFh 1FC000h to 1FCFFFh
3FA000h to 3FAFFFh 1FD000h to 1FDFFFh
3FC000h to 3FCFFFh 1FE000h to 1FEFFFh
3FE000h to 3FFFFFh 1FF000h to 1FFFFFh
Bank
1
25
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address Table (MB84VD22194EA/H)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 001FFFh 000000h to 000FFFh
002000h to 003FFFh 001000h to 001FFFh
004000h to 005FFFh 002000h to 002FFFh
006000h to 007FFFh 003000h to 003FFFh
008000h to 009FFFh 004000h to 004FFFh
00A000h to 00BFFFh 005000h to 005FFFh
00C000h to 00DFFFh 006000h to 006FFFh
00E000h to 00FFFFh 007000h to 007FFFh
010000h to 01FFFFh 008000h to 00FFFFh
020000h to 02FFFFh 010000h to 017FFFh
030000h to 03FFFFh 018000h to 01FFFFh
040000h to 04FFFFh 020000h to 027FFFh
050000h to 05FFFFh 028000h to 02FFFFh
060000h to 06FFFFh 030000h to 037FFFh
070000h to 07FFFFh 038000h to 03FFFFh
080000h to 08FFFFh 040000h to 047FFFh
090000h to 09FFFFh 048000h to 04FFFFh
0A0000h to 0AFFFFh 050000h to 057FFFh
0B0000h to 0BFFFFh 058000h to 05FFFFh
0C0000h to 0CFFFFh 060000h to 067FFFh
0D0000h to 0DFFFFh 068000h to 06FFFFh
0E0000h to 0EFFFFh 070000h to 077FFFh
0F0000h to 0FFFFFh 078000h to 07FFFFh
100000h to 10FFFFh 080000h to 087FFFh
110000h to 11FFFFh 088000h to 08FFFFh
120000h to 12FFFFh 090000h to 097FFFh
130000h to 13FFFFh 098000h to 09FFFFh
140000h to 14FFFFh 0A0000h to 0A7FFFh
150000h to 15FFFFh 0A8000h to 0AFFFFh
160000h to 16FFFFh 0B0000h to 0B7FFFh
170000h to 17FFFFh 0B8000h to 0BFFFFh
180000h to 18FFFFh 0C0000h to 0C7FFFh
SA2
0
1
0
SA3
0
1
1
SA4
1
0
0
SA5
1
0
1
SA6
1
1
0
SA7
1
1
1
SA8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Bank
1
(Continued)
26
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
190000h to 19FFFFh 0C8000h to 0CFFFFh
1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
200000h to 20FFFFh 100000h to 107FFFh
210000h to 21FFFFh 108000h to 10FFFFh
220000h to 22FFFFh 110000h to 117FFFh
230000h to 23FFFFh 118000h to 11FFFFh
240000h to 24FFFFh 120000h to 127FFFh
250000h to 25FFFFh 128000h to 12FFFFh
260000h to 26FFFFh 130000h to 137FFFh
270000h to 27FFFFh 138000h to 13FFFFh
280000h to 28FFFFh 140000h to 147FFFh
290000h to 29FFFFh 148000h to 14FFFFh
2A0000h to 2AFFFFh 150000h to 157FFFh
2B0000h to 2BFFFFh 158000h to 15FFFFh
2C0000h to 2CFFFFh 160000h to 167FFFh
2D0000h to 2DFFFFh 168000h to 16FFFFh
2E0000h to 2EFFFFh 170000h to 177FFFh
2F0000h to 2FFFFFh 178000h to 17FFFFh
300000h to 30FFFFh 180000h to 187FFFh
310000h to 31FFFFh 188000h to 18FFFFh
320000h to 32FFFFh 190000h to 197FFFh
330000h to 33FFFFh 198000h to 19FFFFh
340000h to 34FFFFh 1A0000h to 1A7FFFh
350000h to 35FFFFh 1A8000h to 1AFFFFh
360000h to 36FFFFh 1B0000h to 1B7FFFh
370000h to 37FFFFh 1B8000h to 1BFFFFh
380000h to 38FFFFh 1C0000h to 1C7FFFh
390000h to 39FFFFh 1C8000h to 1CFFFFh
Bank
1
Bank
2
3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
(Continued)
27
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Sector Address
Sec-
tor
Address Range
(BYTE mode)
Address Range
(WORD mode)
Bank
Bank Address
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
Bank
2
BA : Bank Address
28
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Group Addresses Table (MB84VD2218XEA/H)
(Top Boot Block)
Sector Group
A20
A19
A18
A17
A16
0
A15
0
A14
A13
A12
Sectors
SGA0
0
0
0
0
X
X
X
SA0
0
1
SGA1
0
0
0
0
1
0
X
X
X
SA1 to SA3
1
1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4 to SA7
SA8 to SA11
SA12 to SA15
SA16 to SA19
SA20 to SA23
SA24 to SA27
SA28 to SA31
SA32 to SA35
SA36 to SA39
SA40 to SA43
SA44 to SA47
SA48 to SA51
SA52 to SA55
SA56 to SA59
SGA16
1
1
1
1
0
1
X
X
X
SA60 to SA62
1
0
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
29
MB84VD2218XEA/H/2219XEA/H-70/85/90
Sector Group Addresses Table (MB84VD2219XEA/H)
(Bottom Boot Block)
Sector Group
SGA0
A20
0
A19
0
A18
0
A17
0
A16
0
A15
0
A14
0
A13
0
A12
0
Sectors
SA0
SGA1
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
1
1
1
SA7
0
1
SGA8
0
0
0
0
1
0
X
X
X
SA8 to SA10
1
1
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SGA23
SGA24
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
SA67 to SA69
SA70
1
0
1
1
30
MB84VD2218XEA/H/2219XEA/H-70/85/90
Flash Memory Autoselect Codes Table
Type
A12 to A19
A6
A1
A0
A-1*1
VIL
VIL
X
Code (HEX)
04h
Manufacturer’s Code
X
VIL
VIL
VIL
Byte
Word
Byte
55h
MB84VD22182EA
MB84VD22182EH
X
X
X
X
X
X
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
2255h
56h
VIL
X
MB84VD22192EA
MB84VD22192EH
Word
Byte
2256h
50h
VIL
X
MB84VD22183EA
MB84VD22183EH
Word
Byte
2250h
53h
Device
Code
VIL
X
MB84VD22193EA
MB84VD22193EH
Word
Byte
2253h
5Ch
VIL
X
MB84VD22184EA
MB84VD22184EH
Word
Byte
225Ch
5Fh
VIL
X
MB84VD22194EA
MB84VD22194EH
VIL
VIL
VIL
VIH
VIH
VIL
Word
225Fh
Sector Group
Address
Sector Group protect
VIL
01h*2
*1 : A-1 is for Byte mode.
*2 : Output 01h at protected sector address and output 00h at unprotected sector address.
31
MB84VD2218XEA/H/2219XEA/H-70/85/90
Flash Memory Command Definitions Table
Bus
Write
Cy-
cles
Req’d
Second
Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
First Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Command
Sequence
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset *1
Read/Reset *1
1
XXXh F0h
Word
Byte
555h
2AAh
555h
555h
3
AAh
AAh
55h
55h
F0h RA
90h
RD
AAAh
AAAh
(BA)
555h
Word
Byte
555h
2AAh
555h
Autoselect
3
(BA)
AAAh
AAAh
Word
Byte
Word
Byte
Word
Byte
555h
AAAh
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
555h
AAAh
Program
4
6
6
AAh
AAh
AAh
55h
55h
55h
A0h PA
PD
555h
80h
2AAh
555h
2AAh
555h
555h
Chip Erase
Sector Erase
AAh
AAh
55h
10h
AAAh
AAAh
555h
80h
55h SA 30h
AAAh
Sector Erase
Suspend
1
1
BA B0h
BA 30h
Sector Erase
Resume
Word
Byte
555h
AAh
2AAh
555h
555h
Set to
Fast Mode
3
2
2
55h
20h
AAAh
AAAh
Word
Byte
Fast Program
XXXh A0h PA
BA 90h XXXh
PD
2
*
Word
Byte
Reset from
Fast Mode *2
F0h
6
*
Extended
Word
Sector Group
4
1
XXXh 60h SPA 60h SPA 40h SPA SD
(BA)
55h
98h
(BA)
Byte
Protection *3
Word
Query *4
Byte
AAh
Word
Byte
Word
Byte
555h
AAAh
555h
AAAh
2AAh
555h
2AAh
555h
555h
AAAh
555h
AAAh
Hi-ROM Entry
3
4
AAh
AAh
55h
55h
88h
Hi-ROM
Program *5
A0h PA
PD
(Continued)
32
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Command
Bus
Write
Cy-
cles
Req’d
Second
Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
First Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle Write Cycle
Sixth Bus
Sequence
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Word
Byte
555h
2AAh
555h
555h
555h
2AAh
555h
Hi-ROMErase
*
6
4
AAh
55h
80h
AAh
55h HRA 30h
5
AAAh
AAAh
AAAh
(HRBA)
Word
Byte
555h
2AAh
555h
555h
Hi-ROM Exit *5
AAh
55h
90h XXXh 00h
(HRBA)
AAAh
AAAh
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET = VID.
*4: Valid Address is A6 to A0.
*5: This command is valid during Hi-ROM mode.
*6: The data “00h” is also acceptable.
Note : The command combinations not described in Command Definitions are illegal.
Address bits A20 to A11 = X = “H” or “L” for all address commands except for Program Address (PA) ,
Sector Address (SA) , and Bank Address (BA) .
Bus operations are defined in ■ DEVICE BUS OPERATION “User Bus Operations” Table.
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank address (A20 to A15)
SPA = Sector group address to be protected. Set sector group address (SPA) and (A6, A1, A0) = (0, 1, 0) .
HRA = Address of the Hidden-ROM area.
MB84VD2218XEA/H (Top Boot Type)
Word mode : 1F8000h to 1FFFFFh
Byte mode : 3F0000h to 3FFFFFh
MB84VD2219XEA/H (Bottom Boot Type) Word mode : 000000h to 007FFFh
Byte mode : 000000h to 00FFFFh
HRBA = Bank address of the Hidden-ROM area
MB84VD2218XEA/H (Top Boot Type)
: A20 = A19 = A18 = A17 = A16 = A15 = 1
MB84VD2219XEA/H (Bottom Boot Type) : A20 = A19 = A18 = A17 = A16 = A15 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotectedsector addresses.
The system should generate the following address patterns :
Word mode : 555h or 2AAh to addresses A10 to A0
Byte mode : AAAh or 555h to addresses A10 to A0 and A-1
33
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min
Max
Storage Temperature
Tstg
TA
−55
+125
°C
°C
Ambient Temperature with Power
Applied
−25
+85
VCCf + 0.3
VCCs + 0.4
+4.0
V
V
V
V
V
Voltage with Respect to Ground All
pins except RESET and WP/ACC*2
VIN, VOUT
−0.3
VCCf/VCCs Supply*1
RESET*1,*3
VCCf, VCCs
VIN
−0.3
−0.5
−0.5
+13.0
WP/ACC*1,*4
VACC
+10.5
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is −0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.4 V.
During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCs + 2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on RESET pin is −0.5 V. During voltage transitions, RESET pin may undershoot VSS
to −2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V.
Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
*4 : Minimum DC input voltage on WP/ACC pin is −0.5 V.During voltage transitions, WP/ACC pin may undershoot
VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
−25
+2.7
Max
+85
Ambient Temperature
TA
°C
VCCf/VCCs Supply Voltages
VCCf, VCCs
+3.3
V
Notes : • Voltage is defined on the basis of VSS = GND = 0 V.
• Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
34
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ DC CHARACTERISTICS
Value
Typ
Parameter
Symbol
Test Conditions
Unit
Min
−1.0
−1.0
Max
+1.0
+1.0
Input Leakage Current
Output Leakage Current
ILI
VIN = VSS to VCC
µA
µA
ILO
VOUT = VSS to VCC
RESET Inputs Leakage
Current
VCC = VCC Max,
RESET = 12.5 V
ILIT
35
20
µA
ACC Input Leakage
Current
VCC = VCC Max,
WP/ACC = VACC Max
ILIA
mA
tCYCLE = 5 MHz Byte
tCYCLE = 5 MHz Word
tCYCLE = 1 MHz Byte
tCYCLE = 1 MHz Word
16
18
7
mA
Flash VCC Active Current
(Read) *1
CEf = VIL,
OE = VIH
ICC1f
mA
mA
mA
7
Flash VCC Active Current
(Program/Erase) *2
ICC2f
ICC3f
CEf = VIL, OE = VIH
CEf = VIL, OE = VIH
35
Byte
Word
Byte
Word
51
53
51
53
Flash VCC Active Current
(Read-While-Program) *5
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
ICC5f
CEf = VIL, OE = VIH
CEf = VIL, OE = VIH
mA
mA
Flash VCC Active Current
(Erase-Suspend-Program)
35
VCCs = VCC Max,
CE1s = VIL,
CE2s = VIH
SRAM VCC Active Current
SRAM VCC Active Current
Flash VCC Standby Current
ICC1s
ICC2s
tCYCLE = 10 MHz
40
mA
CE1s = 0.2 V,
CE2s = VCCs − 0.2 V,
tCYCLE = 10 MHz
40
8
mA
mA
tCYCLE = 1 MHz
VCCf = VCC Max, CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
ISB1f
ISB2f
1
1
5
5
µA
µA
Flash VCC Standby Current
(RESET)
VCCf = VCC Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
VCCf = VCC Max, CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf ± 0.3 V
Flash VCC Current
(Automatic Sleep Mode) *3
ISB3f
1
5
µA
VIN = VCCf ± 0.3 V or VSS ± 0.3 V
SRAM VCC Standby Current
SRAM VCC Standby Current
ISB1s
ISB2s
CE1s ≥ VCCs − 0.2 V, CE2s ≥ VCCs − 0.2 V
CE2s ≤ 0.2 V
7
7
µA
µA
(Continued)
35
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Value
Typ
Parameter
Symbol
Test Conditions
Unit
Min
−0.3
2.4
Max
0.5
Input Low Level
VIL
VIH
V
V
VCC*6 + 0.3
Input High Level
Voltage for Sector
Protection, and Temporary
Sector Unprotection
(RESET) *4
VID
11.5
8.5
12.5
V
Voltage for Program
Acceleration (WP/ACC) *4
VACC
VOL
9.0
9.5
0.4
V
V
V
V
VCCf = VCCs = VCC Min,
IOL = 1.0 mA
Output Low Voltage Level
Output High Voltage Level
VCCf = VCCs = VCC Min,
IOH = −0.5 mA
VOH
VLKO
2.4
2.3
Flash Low VCC Lock-Out
Voltage
2.5
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns.
*4: Applicable for only VCC applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)
*6: VCC indicates the lower voltage of VCCf or VCCS.
36
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ AC CHARACTERISTICS
• CE Timing
Symbol
JEDEC Standard
tCCR
Value
Min
0
Parameter
Test Setup
Unit
CE Recover Time
ns
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
CE2s
tCCR
tCCR
37
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Read Only Operations Characteristics (Flash)
Value
85
Symbol
Test
Parameter
70
90
Unit
Setup
JEDEC Standard
Min Max Min Max Min Max
70 85 90
Read Cycle Time
tAVAV
tAVQV
tRC
ns
ns
CEf = VIL
OE = VIL
Address to Output Delay
tACC
70
85
90
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
OE = VIL
70
30
25
25
85
35
30
30
90
40
30
30
ns
ns
ns
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
0
0
0
ns
RESET Pin Low to Read Mode
tREADY
20
20
20
µs
Test Conditions: Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or 3.0 V
Timing measurement reference level
Input : 0.5 × VCCf
Output : 0.5 × VCCf
38
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Read Cycle (Flash)
tRC
Address Stable
Address
tACC
CEf
OE
tDF
tOE
tOEH
WE
DQ
tCE
High-Z
High-Z
Output Valid
• Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
Address Stable
tACC
tRH
CEf
tRP
tRH
tCE
RESET
tOH
High-Z
DQ
Output Valid
39
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Erase/Program Operations (Flash)
Value
70
Value
85
Value
90
Symbol
Parameter
Unit
JEDEC Standard Min Typ Max Min Typ Max Min Typ Max
Write Cycle Time
tAVAV
tWC
tAS
70
0
85
0
90
0
ns
ns
Address Setup Time (WE to Addr.)
tAVWL
Address Setup Time to CEf Low
During Toggle Bit Polling
tASO
tAH
12
45
0
15
45
0
15
45
0
ns
ns
ns
Address Hold Time (WE to Addr.)
tWLAX
Address Hold Time from CEf or
OE High During Toggle Bit Polling
tAHT
Data Setup Time
tDVWH
tDS
tDH
30
0
35
0
35
0
ns
ns
ns
ns
Data Hold Time
tWHDX
Output Enable Setup Time
tOES
0
0
0
Read
0
0
0
Output Enable
tOEH
Toggle and
Hold Time
10
10
10
ns
Data Polling
CEf High During Toggle Bit Polling
OE High During Toggle Bit Polling
tCEPH
tOEPH
20
20
20
20
20
20
ns
ns
Read Recover Time Before Write
(OE to CEf)
tGHEL
tGHEL
tGHWL
0
0
0
0
0
0
ns
ns
Read Recover Time Before Write
(OE to WE)
tGHWL
WE Setup Time (CEf to WE)
CEf Setup Time (WE to CEf)
WE Hold Time (CEf to WE)
CEf Hold Time (WE to CEf)
Write Pulse Width
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tWS
tCS
0
0
0
0
0
0
ns
ns
tWH
tCH
0
0
0
ns
0
0
0
ns
tWP
tCP
35
35
25
25
35
35
30
30
35
35
25
25
ns
CEf Pulse Width
ns
Write Pulse Width High
CEf Pulse Width High
tWHWL
tEHEL
tWPH
tCPH
ns
ns
Byte Programming Operation
Word Programming Operation
Sector Erase Operation *1
8
8
16
1
8
16
1
µs
tWHWH1
tWHWH1
tWHWH2
12
0.2
µs
s
tWHWH2
(Continued)
40
MB84VD2218XEA/H/2219XEA/H-70/85/90
(Continued)
Value
Parameter
Parameter
Symbol
70
85
90
Unit
JEDEC Standard Min Typ Max Min Typ Max Min Typ Max
VCCf Setup Time
tVCS
tVLHT
tVIDR
tVACCR
tRB
50
4
50
4
50
4
µs
µs
ns
ns
ns
ns
Voltage Transition Time *2
Rise Time to VID *2
500
500
0
500
500
0
500
500
0
Rise Time to VACC
Recover Time from RY/BY
RESET Pulse Width
tRP
500
500
500
Delay Time from Embedded
Output Enable
tEOE
tRH
70
85
90
ns
ns
ns
RESET Hold Time Before Read
200
50
200
50
200
50
Program/Erase Valid to RY/BY
Delay
tBUSY
90
20
90
20
90
20
Erase Time-out Time *3
tTOW
tSPD
µs
µs
Erase Suspend Transition Time *4
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection Operation.
*3: The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command (s) .
*4: When the Erase Suspend command is written during the Sector Erase operation, the device will take maximum
of “tSPD” to suspend the erase operation.
41
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
Address
CEf
555H
tWC
PA
PA
tRC
tAS
tAH
tCS
tCH
tCE
OE
tGHWL
tOE
tWHWH1
tWP
tWPH
WE
tOH
tDS
tDF
tDH
A0h
PD
DQ7
DOUT
DOUT
Data
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode (the addresses differ from ×8 mode.)
42
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling
555h
tWC
PA
PA
Address
WE
tAS
tAH
tWS
tWH
OE
tGHEL
tWHWH1
tCP
tCPH
CEf
tDS
tDH
A0h
PD
DQ7
DOUT
Data
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
43
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling
555H
tWC
PA
PA
Address
WE
tAS
tAH
tWS
tWH
OE
tGHEL
tWHWH1
tCP
tCPH
CEf
tDS
tDH
A0h
PD
DQ7
DOUT
Data
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates the last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×16 mode (the addresses differ from ×8 mode.)
44
MB84VD2218XEA/H/2219XEA/H-70/85/90
• AC Waveforms Chip/Sector Erase Operations (Flash)
SA*
Address
CEf
555h
tWC
2AAh
555h
555h
2AAh
tAS
tAH
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
30h for Sector Erase
10h/
30h
AAh
55h
80h
AAh
55h
DQ
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
Note : These waveform are for the ×16 mode (the addresses differ from ×8 mode.)
45
MB84VD2218XEA/H/2219XEA/H-70/85/90
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tDF
tCH
tOE
OE
tOEH
WE
tCE
*
High-Z
High-Z
DQ7 =
DQ7
Data
Data
DQ7
Valid Data
tWHWH1 or 2
DQ0 to DQ6
Valid Data
DQ6 to DQ0
RY/BY
DQ0 to DQ6 = Output Flag
tEOE
tBUSY
* : DQ7 = Valid Data (the device has completed the Embedded operation.)
46
MB84VD2218XEA/H/2219XEA/H-70/85/90
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO
tAHT tAS
CEf
WE
tCEPH
tOEH
tOEPH
tOEH
OE
tDH
tOE
*
tCE
Stop
Toggling
DQ6/DQ2
Toggle
Data
Toggle
Data
Toggle
Data
Output
Valid
Data
tBUSY
RY/BY
* : DQ6 stops toggling (the device has completed the Embedded operation) .
47
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Bank-to-Bank Read/Write Timing Diagram (Flash)
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
BA2
(555h)
BA2
(PA)
BA2
(PA)
Address
BA1
BA1
BA1
tACC
tAS
tAH
tAS
tAHT
tCE
tOE
CEf
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDH
tDS
tDF
Valid
Output
Valid
Output
Valid
Intput
Valid
Output
Valid
Intput
Status
DQ
(A0h)
(PD)
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1.
BA2 : Address corresponding to Bank 2.
48
MB84VD2218XEA/H/2219XEA/H-70/85/90
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
WE
Rising edge of the last write pulse
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
RY/BY
tRP
tRB
tREADY
49
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Temporary Sector Group Unprotection (Flash)
VCCf
tVIDR
tVLHT
tVCS
VID
VIH
RESET
CEf
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection Period
50
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
tWC
SPAX
SPAX
SPAY
Address
A6, A0
A1
CEf
OE
TIME - OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SPAX : Sector Group Address to be protected
SPAY : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
51
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Accelerated Program (Flash)
VCCf
tVACCR
tVLHT
tVCS
VACC
VIH
WP/ACC
CEf
WE
tVLHT
tVLHT
Program Command Sequence
Acceleration period
RY/BY
52
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Read Cycle (SRAM)
Value
Parameter
Symbol
70
85
90
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tAA
70
85
85
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
70
35
70
85
85
85
45
85
85
85
85
45
85
Chip Enable (CE1s) Access Time
Chip Enable (CE2s) Access Time
Output Enable Access Time
LBs, UBs to Output Valid
tCO1
tCO2
tOE
tBA
Chip Enable (CE1s Low and CE2s High)
to Output Active
tCOE
5
5
5
ns
Output Enable Low to Output Active
UBs, LBs Enable Low to Output Active
tOEE
tBE
0
0
0
0
0
0
ns
ns
Chip Enable (CE1s High or CE2s Low)
to Output High-Z
tOD
tODO
tBD
25
25
25
35
35
35
35
35
35
ns
ns
ns
ns
Output Enable High to Output High-Z
UBs, LBs Output Enable to Output
High-Z
Output Data Hold Time
tOH
10
10
10
Test Conditions − Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCCs
Timing measurement reference level
Input : 0.5 × VCCs
Output : 0.5 × VCCs
53
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Read Cycle (SRAM)
tRC
Address
tAA
tOH
tCO1
CE1s
tCOE
tCO2
tOD
CE2s
tOD
tOE
OE
tODO
tBD
tOEE
LBS, UBS
tBA
tBE
tCOE
DQ
Valid Data Out
Note : WE remains “H” during the read cycle.
54
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle (SRAM)
Value
Parameter
Symbol
70
85
90
Unit
Min
70
55
60
60
60
0
Max
Min
85
60
70
70
70
0
Max
Min
85
60
70
70
70
0
Max
Write Cycle Time
tWC
tWP
tCW
tAW
tBW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Address valid to End of Write
UBs, LBs to End of Write
Address Setup Time
Write Recovery Time
WE Low to Output High-Z
WE High to Output Active
Data Setup Time
tWR
tODW
tOEW
tDS
0
0
0
25
35
35
0
30
0
0
35
0
0
35
0
Data Hold Time
tDH
55
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle *1 (WE control) (SRAM)
tWC
Address
tAS
tWP
tWR
WE
tAW
tCW
CE1s
CE2s
tCW
tBW
LBS, UBS
tODW
tOEW
DOUT
DIN
*2
*4
*3
*4
tDS
tDH
Valid Data In
*1: If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2: If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will remain at High-Z.
*3: IfCE1sgoes“H”(orCE2sgoes“L”)coincidentwithorbeforeWE goes“H”, theoutputwillremainatHigh-Z.
*4: Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be
applied.
56
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle *1 (CE1s control) (SRAM)
tWC
Address
WE
tAS
tWR
tWP
tAW
tCW
CE1s
CE2s
tCW
tBW
LB, UB
tBE
tCOE
tODW
DOUT
DIN
tDS
tDH
Valid Data In
*2
*1: If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2: Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
57
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle *1 (CE2s Control) (SRAM)
tWC
Adrress
tAS
tWP
tWR
WE
tCW
CE1s
CE2s
tAW
tCW
tBW
LBS, UBS
tBE
tCOE
tODW
DOUT
tDS
tDH
DIN
*2
Valid Data In
*1: If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2: Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
58
MB84VD2218XEA/H/2219XEA/H-70/85/90
• Write Cycle *1 (LBs, UBs Control) (SRAM)
tWC
Address
WE
tWP
tWR
tCW
CE1s
CE2s
tCW
tAW
tBW
tAS
LBS, UBS
tBE
tCOE
tODW
DOUT
tDS
tDH
DIN
*2
Valid Data In
*1: If OE is “H” during the write cycle, the outputs will remain at High-Z.
*2: Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
59
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limits
Parameter
Unit
Comment
Min
Typ
Max
Excludes programming time
prior to erasure
Sector Erase Time
1
10
s
Excludes system-level
overhead
Byte Programming Time
Word Programming Time
8
300
360
100
µs
µs
Excludes system-level
overhead
16
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
s
100,000
cycle
■ DATA RETENTION CHARACTERISTICS (SRAM)
Value
Unit
Parameter
Symbol
Min
Typ
Max
3.3
7
Data Retention Supply Voltage
VDH
IDDS2
tCDR
tR
1.5
V
Standby Current
VDH = 3.0 V
1.5
µA
ns
ns
Chip Deselect to Data Retention Mode Time
Recovery Time
0
tRC
Note : tRC : Read cycle time
• CE1s Controlled Data Retention Mode *1
VCCs
DATA RETENTION MODE
2.7 V
*2
*2
VIH
VDH
VCCS − 0.2 V
CE1s
tCDR
tR
GND
*1: In CE1s controlled data retention mode, input level of CE2s should be fixed VCCs to VCCs − 0.2 V or VSS
to 0.2 V during data retention mode. Other input and input/output pins can be used between −0.3 V to
VCCs + 0.3 V.
*2: When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition of
VCCs from 3.3 V to VIH Min level.
60
MB84VD2218XEA/H/2219XEA/H-70/85/90
• CE2s Controlled Data Retention Mode
VCCs
DATA RETENTION MODE
2.7 V
VDH
VIH
CE2s
tCDR
tR
VIL
0.2 V
GND
Note: In CE2s controlled data retention mode, input and input/output pins can be used between −0.3 V to
VCCs + 0.3 V.
■ PACKAGE PIN CAPACITANCE
Value
Parameter
Symbol
Test Setup
Unit
Typ
11
Max
14
Input Capacitance
CIN
VIN = 0
pF
pF
pF
pF
Output Capacitance
COUT
CIN2
CIN3
VOUT = 0
VIN = 0
VIN = 0
12
16
Control Pin Capacitance
WP/ACC Pin Capacitance
14
16
21.5
26
Note : Test conditions TA = +25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package are created with acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when
autoselect and sector group protection function are used, then the high voltage (VID) can be applied to RESET.
• Without the high voltage (VID) , Sector group protection can be achieved by using “Extended Sector Group
Protection” command.
61
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ ORDERING INFORMATION
MB84VD2218
X
EA
-85
PBS
PACKAGE TYPE
PBS = 71-ball BGA
SPEED OPTION
Device Revision (Valid Combination)
EA
EH
Bank Size
2 = 4 Mbit / 28 Mbit
3 = 8 Mbit / 24 Mbit
4 = 16 Mbit / 16 Mbit
DEVICE NUMBER/DESCRIPTION
32 Mega-bit (4 M × 8-bit or 2 M × 16-bit) Dual Operation Flash Memory
3.0 V-only Read, Program, and Erase
4 Mega-bit (512 K × 8-bit or 256 K × 16-bit) SRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2218 = Top sector
84VD2219 = Bottom sector
62
MB84VD2218XEA/H/2219XEA/H-70/85/90
■ PACKAGE DIMENSION
71-ball plastic BGA
(BGA-71P-M02)
8.80(.346)
7.20(.283)
11.00±0.10(.433±.004)
1.05 ±+00..1105
.041 –+..000046
(Mounting height)
(Stand off)
5.60(.220)REF
0.38±0.10
(.015±.004)
0.80
(.031)
8
7
6
5
4
3
2
1
5.60(.220)
7.00±0.10
(.276±.004)
REF
0.80
(.031)
M
L K J H G F E D C B A
INDEX-MARK AREA
71-Ø0.45 –+00..0150
71-Ø.018 –+..000024
M
0.08(.003)
0.10(.004)
C
2000 FUJITSU LIMITED B71002S-1c-1
DImensions in mm (inches).
63
MB84VD2218XEA/H/2219XEA/H-70/85/90
FUJITSU LIMITED
For further information please contact:
Japan
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FUJITSU LIMITED
Marketing Division
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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Tel: +81-3-5322-3353
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The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
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North and South America
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3545 North First Street,
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The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
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extremely high reliability (i.e., submersible repeater and artificial
satellite).
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Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
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Asia Pacific
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
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Korea
FUJITSU MICROELECTRONICS KOREA LTD.
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Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0204
FUJITSU LIMITED Printed in Japan
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