MB86612 [FUJITSU]
IEEE 1394 Bus Controller (for MPEG, DVC); IEEE 1394总线控制器（用于MPEG ， DVC ）
| 型号： | MB86612 |
| 厂家： | 
FUJITSU |
| 描述： | IEEE 1394 Bus Controller (for MPEG, DVC) |
| 文件： | 总40页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-22001-1E
ASSP Communication Control
IEEE 1394 Bus Controller
(for MPEG, DVC)
MB86612
■ DESCRIPTION
The MB86612 is 1394 serial bus controller exclusively for MPEG and DVC data transfer, compatible with the
IEEE 1394 “FireWire” standard (IEEE Standard 1394-1995). Two built-in ports plus a differential transceiver and
comparator are provided to enable formation of networks in a 1394 cable environment. The MB86612 supports
s100 data transfer speeds.
By integrating the physical layer and link layer on one chip, The MB86612 is designed to reduce mounting area
as well as power consumption.
TheMB86612hasanexclusivedataportforisochronoustransfer, providesautomaticpacketizingandseparation
of header and data units, and is optimized for continuity of transfer processing.
The MB86612 supports MPEG and DVC AV/C protocols, and includes the necessary built-in automatic
operations and CSR’s for providing the necessary operations for MPEG and DVC data transfer.
■ FEATURES
• Compatible with IEEE 1394 high-performance serial bus standards
• Physical layer and link layer integrated on one chip
• 2 cable ports
• Supports s100 transfer speed (98.304 Mbit/sec)
• 3.3V single power supply operation
• Built-in PLL (for crystal oscillator) for internal clock signal generation
• Power saving modes
1) Forced sleep mode at instruction from MPU
2) Automatic sleep mode for non-connected ports
• Header and data units automatically separated at receiving and automatic packetizing for sending
• Supports cycle master functions
(Continued)
■ PACKAGES
100-pin plastic LQFP
120-pin plastic FBGA
(FPT-100P-M05)
(BGA-120P-M01)
MB86612
(Continued)
• Built-in CSR's to provide isochronous resource manager functions
• 32-bit CRC generation and check functions
• General purpose port for asynchronous transfer and control (16-bit MPU bus)
• Exclusive built-in ports for isochronous transfer (8-bit bus)
• Built-in CRS's and automatic processes to support AV/C protocol (MPEG, DVC)
1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending.
2) Automatic generation of source packet headers (time stamp).
3) Source packet header (time stamp) match detection
4) DBC area automatic increment function
5) Empty packet sending and receiving
6) On-chip PCR (input/output 1 channel each)
7) Each CSR with automatic C&S lock processing and read processing
8) Automatic processing of late packet generation
• Compatible with 4-core or 6-core cables
• Packages: LQFP-100, FBGA-120
2
MB86612
■ PIN ASSIGNMENTS
1. LQFP-100
RESET
INT
VDD
1
2
75 AVDD
74 AVSS
73 TPA0
72 TPB0
71 TPA0
70 TPB0
69 AVDD
68 AVSS
67 TPBIAS0
66 AVDD
65 AVSS
64 RO0
63 AVSS
62 AVDD
61 TPA1
60 TPB1
59 TPA1
58 TPB1
57 AVSS
56 AVDD
55 TPBIAS1
54 AVSS
53 AVDD
52 RO1
51 N.C.
3
VSS
4
ALE
D15
D14
D13
D12
D11
D10
D9
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D8
VDD
VSS
D7
D6
AD5
AD4
AD3
AD2
AD1
D0
VDD
VSS
3
MB86612
2. FBGA-120
13
12
11
10
9
8
7
6
5
4
3
2
1
WR
(DS)
N.C.
AVDD
AVSS
VCOIN TESTP
XO
OCLK PMODE
A3
A5
VDD
N.C.
N
M
L
RD
(R/W)
N.C.
AVDD
AVSS
RO1
AVSS
AVSS
TPB1
AVDD
RO0
N.C.
CHPO
ROP
AVSS
AVDD
X1
VDD
VSS
CTR
N.C.
A2
A1
A4
VSS
CS
VSS
VDD
TP-
BIAS1
N.C.
N.C.
N.C.
AD1
AD4
N.C.
VDD
TPB1
N.C.
AVSS
AVSS
N.C.
TPB0
N.C.
PWR3
VSS
D0
AD2
AD5
D7
K
J
TPA1
TPA1
N.C.
AD3
D6
I
TOP VIEW
VSS
D8
H
G
E
D
C
B
TP-
BIAS0
AVDD
AVSS
N.C.
D11
D13
ALE
N.C.
D9
D10
N.C.
D15
VDD
AVDD
TPB0
AVSS
D12
D14
VSS
TPA0
TPA0
AVDD
PWR1
ID7
N.C.
ID4
ID5
ID6
ID1
ID2
ID3
VSS
ID0
IDIR
ICLK
VDD
IV
LINKON
TS
PWR2
N.C.
N.C.
INT
N.C.
BUSRST
VDD
N.C.
ILWRE
IERR MODE0 MODE1 RESET A
1 pin
4
MB86612
■ PIN LIST
1. LQFP-100
NO.
1
I/O
ID
Pin Name
RESET
INT
NO.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
I/O
IU
O
O
—
—
I/O
I
—
—
—
I
O
O
Pin Name
PMODE
CTR
2
O
3
—
VDD
OCLK
VDD
4
—
VSS
5
ID
ALE
D15
D14
D13
D12
D11
D10
D9
VSS
X0
6
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
—
7
X1
8
TESTP
AVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
AVDD
VCOIN
CHPO
ROP
AVSS
AVDD
D8
VDD
—
—
—
O
—
—
O
—
—
I/O
I/O
I/O
I/O
—
—
O
—
—
O
—
—
I/O
—
VSS
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
—
D7
N.C.
D6
RO1
AD5
AD4
AD3
AD2
AD1
D0
AVDD
AVSS
TPBIAS1
AVDD
AVSS
TPB1
TPA1
TPB1
TPA1
AVDD
AVSS
RO0
VDD
—
VSS
ID
WR(DS)
RD (R/W)
VDD
ID
—
—
VSS
ID
CS
AVSS
ID
A5
AVDD
ID
A4
TPBIAS0
AVSS
ID
A3
ID
A2
AVDD
ID
A1
TPB0
(Continued)
5
MB86612
(Continued)
NO.
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
I/O
Pin Name
TPA0
TPB0
TPA0
AVSS
NO.
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
ID/O
ID/O
ID/O
ID/O
—
Pin Name
ID3
I/O
I/O
I/O
—
ID2
ID1
ID0
—
AVDD
PWR1
PWR2
VDD
VSS
I
—
VDD
I
ID
ICLK
IDIR
—
ID
—
VSS
O
ILWRE
IV
I
PWR3
BUSRST
ID7
ID
I
O
IERR
TS
ID/O
ID/O
ID/O
ID/O
ID/O
O
ID6
LINKON
MODE0
MODE1
ID5
ID
ID4
ID
6
MB86612
2. FBGA-120
Pin
No.
Ball
No.
Pin
No.
Ball
No.
Pin
No.
Ball
No.
I/O
Pin Name
I/O
Pin Name
I/O
Pin Name
1
A1
B1
B2
C1
C2
C3
D1
D2
D3
E1
E2
E3
F1
F2
F3
G1
G2
G3
H1
H2
H3
J1
ID
—
RESET
N.C.
INT
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
N4
M4
ID
ID
—
ID
ID
ID
IU
O
A5
A4
73
74
H13
H12
H11
G13
G12
G11
F13
F12
F11
E13
E12
E11
D13
D12
D11
C13
C12
B13
A13
A12
B12
A11
B11
C11
A10
B10
C10
A9
I/O
—
TPA1
AVDD
AVSS
N.C.
RO0
AVSS
AVDD
TPBIAS0
N.C.
AVSS
AVDD
TPB0
TPA0
TPB0
N.C.
TPA0
AVSS
AVDD
PWR1
N.C.
PWR2
VDD
2
3
O
L4
N.C.
A3
75
—
4
—
VDD
N5
76
—
5
—
VSS
M5
A2
77
—
6
ID
ALE
D15
D14
D13
N.C.
D12
D11
D10
D9
L5
A1
78
—
7
ID/O
ID/O
ID/O
—
N6
PMODE
CTR
N.C.
OCLK
VDD
79
—
8
M6
80
—
9
L6
—
O
81
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
N7
82
—
ID/O
ID/O
ID/O
ID/O
—
M7
—
—
I/O
I
83
—
L7
VSS
84
I/O
I/O
I/O
—
N8
X0
85
M8
X1
86
N.C.
D8
L8
—
O
N.C.
TESTP
AVSS
AVDD
VCOIN
CHPO
ROP
AVSS
N.C.
AVDD
N.C.
N.C.
RO1
AVDD
AVSS
TPBIAS1
AVDD
AVSS
TPB1
TPA1
TPB1
N.C.
87
ID/O
—
N9
88
I/O
—
VDD
M9
—
—
I
89
—
VSS
L9
90
—
ID/O
—
D7
N10
M10
L10
N11
M11
N12
N13
M13
M12
L13
L12
L11
K13
K12
K11
J13
J12
J11
91
I
N.C.
D6
O
92
—
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
—
O
93
I
AD5
AD4
AD3
AD2
AD1
D0
—
—
—
—
—
O
94
—
J2
95
—
VSS
J3
96
I
PWR3
BUSRST
N.C.
ID7
K1
K2
K3
L1
97
I
98
—
99
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
ID/O
—
VDD
—
—
O
100
101
102
103
104
105
106
107
108
ID6
L2
—
N.C.
VSS
B9
ID5
M1
N1
N2
M2
N3
M3
L3
—
C9
ID4
ID
WR (DS)
N.C.
RD (R/W)
VDD
—
—
I/O
I/O
I/O
—
A8
ID3
—
B8
ID2
ID
C8
ID1
—
A7
N.C.
ID0
—
VSS
B7
ID/O
—
ID
CS
C7
VSS
(Continued)
7
MB86612
(Continued)
Pin
No.
Ball
No.
Pin
No.
Ball
No.
Pin
No.
Ball
No.
I/O
Pin Name
I/O
Pin Name
I/O
Pin Name
109
110
111
112
A6
B6
C6
A5
—
ID
ID
O
VDD
ICLK
IDIR
113
114
115
116
B5
C5
A4
B4
—
ID
N.C.
IV
117
118
119
120
C4
A3
B3
A2
O
ID
—
ID
LINKON
MODE0
N.C.
O
IERR
TS
ILWRE
ID/O
MODE1
8
MB86612
■ PIN DESCRIPTION
1. 1394 Interface
Pin name
TPA0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Function
Cable port 0 TPA positive signal I/O pin
TPA0
Cable port 0 TPA negative signal I/O pin
Cable port 0 TPB positive signal I/O pin
TPB0
TPB0
Cable port 0 TPB negative signal I/O pin
Cable port 1 TPA positive signal I/O pin
TPA1
TPA1
Cable port 1 TPA negative signal I/O pin
Cable port 1 TPB positive signal I/O pin
TPB1
TPB1
Cable port 1 TPB negative signal I/O pin
Cable port 0 common voltage reference voltage output pin
Cable port 1 common voltage reference voltage output pin
Connect to GND through 4.7 kΩ resistance
Connect to GND through 4.7 kΩ resistance
TPBIAS0
TPBIAS1
RO0
O
O
RO1
O
2. Isochronous-data Interface
Pin name
I/O
Function
Isochronous data interface CLK signal input pin (DC to 16 MHz).
ICLK
I
Note: When this clock is stopped, transfer is stopped. Also the “Data FIFO init
(63h)” instruction (operand: 21) is invalid.
Isochronous transfer sending/receiving switching signal input pin.
0 input: Clear ISO FIFO, go to sending mode.
Sending starts after receiving 1 packet of data.
1 input: Clear ISO FIFO, go to receiving mode. If a ‘1’ signal is entered during
packet sending, receiving mode begins after sending of the current packet.
The ILWRE signal is asserted after receiving 1 packet.
IDIR
I
Note: This signal should normally be left at ‘1’, and switched to ‘0’ only when
sending.
Isochronous FIFE access enable signal output pin.
Sending: Asserted when 1 or more empty source packets are present in ISO
FIFO.
When negated, the data output up to the leading edge for the next ICLX.
Receiving: Asserted when receiving of 1 source packet of data is completed.
Negate conditions for this signal are determined by the ilwre-mode bit (bit 11) in
the mode-control register.
ILWRE
O
ID7 to ID0
IV
I/O
I
Isochronous transfer data input/output bits. (MSB is ID7, LSB is ID0)
ID7 to ID0 enable signal input pin.
Sending: While this signal is active, data from the ID7 to ID0 pins is loaded into
ISO FIFO memory at the rising edge of the ICLK signal.
Receiving: While this signal is active, data from ISO FIFO memory is sent to the
ID7 to ID0 pins. Data is switched at the falling edge of the ICLK signal.
(Continued)
9
MB86612
(Continued)
Pin name
I/O
Function
Sending: DVC mode time stamp trigger signal input pin.
(Input) The cycle timer value when this signal is asserted is added to the sending
offset value and becomes the sending time stamp.
Receiving: Time stamp match detect signal.
(output) In MPEG mode, this signal is negative after reading 1 source packet of
data.
TS
I/O
In DVC mode, this signal is asserted for the duration of 32 ticlk (32 periods of the
ICLK signal).
If an error is detected in a receiving isochronous packet this signal is not output.
This signal is output when an error is detected in a receiving isochronous packet.
When an error is detected the TS signal is not output, so that this signal should
be used to trigger reading of the receiving packet.
If an error such as causing discarding of received packets within a device, this
signal is not output.
IERR
CTR
O
This signal is output when the cycle timer value is changed.
This signal may be output or not output, according to the CTR bit (bit 0) in the
mode-control register.
O
O
Cycle timer clock output (24.576 MHz).
This signal may be output or not output, according to the CTR bit (bit 0) in the
mode-control register.
OCLK
3. System Interface
Pin name
I/O
Function
CS
I
Input pin for signals used by the MPU to select the MB86612 as an I/O device.
Address input pins for internal register selection.
Valid only in non-multiplexed mode.
A5 to A1
I
If multiplexed mode is selected these pins should be fixed at ‘0’.
D15 to D6, D0
AD5 to AD1
I/O
I/O
16-bit data bus input/output pins (MSB is D15, LSB is D0).
16-bit data bus input/output pins (MSB is AD5, LSB is AD1). Used for address
input signals when multiplexed mode is selected.
80-series mode: Read strobe signal input pin, used to output data from the
MB86612 to the data bus.
68-series mode: Control signal input pin, used for data input/output operations to
the MB86612.
RD (R/W)
WR (DS)
I
I
80-series mode: Write strobe signal input pin, used to input data from the data
bus to the MB86612.
68-series mode: DS signal input pin, output when data bus is enabled.
ALE signal input pin, for signal output when addresses are enabled in multiplexed
mode. In non-multiplexed mode, this signal should be fixed at ‘0’.
ALE
INT
I
O
Interrupt output pin.
10
MB86612
4. Other
Pin name
I/O
I/O
I
Function
X0
X1
External crystal connection pins for oscillator circuits.
VCOIN
CHPO
ROP
I
VCO input pin for internal PLL.
O
O
Charge pump output pin for internal PLL.
Connect to GND through 4.7 kΩ resistance.
Reset signal input pin.
RESET
MODE0
MODE1
PMODE
I
I
I
I
This signal should be set to ‘0’ when the system power supply is off.
Input ‘0’ for 80-series mode.
Input ‘1’ for 68-series mode.
Input ‘0’ for non-multiplexed mode.
Input ‘1’ for multiplexed mode.
For cable power supply, set to ‘0’ for power startup.
Set to ‘1’ when cable power supply is off or until system power is on.
When operating from cable power supply, these pins determine the value of the
‘POWER_CLASS’ area of Self-ID packets.
When operating from system power supply, these pins correspond to the power
bit in the Self-ID-PKT-param setting register.
PWR1 to PWR3
I
When the MB86612 is started from the power supply this bit determines whether
a bus reset is applied automatically.
Input ‘0’ for no bus reset.
Input ‘1’ for bus reset.
When this bit is set to ‘1’, a bus reset is executed 200 µs after the int-reset bit (bit
9) in the flag & status register (address 02h) is set to ‘1’.
BUSRST
LINKON
I
Link-on packet receiving detection pin. Outputs an ‘H’ signal for 1 to 2 tclk (1 to 2
cycles of the crystal oscillator input signal) when a link-0n packet is received.
When this signal is not used, leave it open.
O
AVDD
AVSS
VDD
—
—
—
—
—
Analog power supply
Analog ground
Digital power supply
Digital ground
VSS
TESTP
Test pin. Do not connect.
11
MB86612
■ BLOCK DIAGRAM
IDIR
ICLK
ISO
TPA0
TPA0
sending
packet
control
ILWRE
ID7 to ID0
IV
TPB0
TPB0
TPBIAS0
TS
PHY
layer
control
circuit
IERR
CTR
ISO
receiving
packet
control
OCLK
LINK
layer
TPA1
TPA1
control
circuit
TPB1
TPB1
ASYNC
send-only
FIFO
ASYNC
sending
packet
TPBIAS1
CS
(128 byte)
processing
A5 to A1
D15 to D6, D0
AD5 to AD1
ASYNC
receive-only
FIFO
ASYNC
receiving
packet
Cycle mask
(128 byte)
processing
RD (R/W)
WR (DS)
ALE
INT
Transaction circuit block
PLL circuit
Register block
CSR
12
MB86612
■ BLOCK DESCRIPTIONS
• PHY Layer Control Circuit
This block contains the IEEE 1394 physical layer control circuits.
Both asynchronous transfer and isochronous transfer in a cable environment are supported.
The transfer speed is 98.304 Mbit/sec.
Two analog transceiver/receiver ports are built-in.
This block provides bus status monitoring initialization operation after a bus reset is applied, as well as
arbitration and encoding/decoding functions for data sending and receiving.
• LINK Layer Control Circuit
This block controls the generation and transfer of IEEE 1394 standard packets.
32-bit CRC generation and checking is performed for packet headers and data.
A 32-bit cycle timer register is built-in to provide cycle master functions.
• Sending/Receiving FIFO
Contains built-in 4-byte FIFO areas, used for isochronous smoothing and rate conversion for both sending
and receiving.
Contains independent sending and receiving 128-byte FIFO areas for asynchronous transfer.
• Packet Processing
Sending: Performs packetizing of headers, data and CRC. Automatically generates and attaches CRC.
Receiving: Separates 1394 packet headers and data, strips CRC.
• Special Transaction Circuits
These circuits operate with the packet processing block in handling data from the isochronous interface,
packetizing for MPEG and DVC transfer as well as rebuilding receiving data for the isochronous interface.
• Register Block
This block contains various device control registers, as well as registers for setting parameters required for
1394 transfer, AVC protocol registers and CSR.
The built-in CSR provides isochronous resource manager functions.
• PLL Circuit
This block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating
clock and transfer clock signals.
Reference oscillator frequency: 8.192 MHz.
13
MB86612
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min.
VSS – 0.5
VSS – 0.5
VSS – 0.5
–55
Max.
4.0
Power supply voltage*1
Input voltage*1
VDD
VI
V
V
VDD + 0.5
VDD + 0.5
+125
Output voltage*1
Strage temperature
Operating temperature*2
Output current*3
Overshoot*4
VO
Tst
Top
IO
V
°C
°C
mA
V
–40
+85
–14
+14
—
—
VDD + 1.0
VSS – 1.0
Undershoot*4
—
—
V
*1: Voltage values are based on Vss = 0 V.
*2: Not warranted for continuous operation.
*3: Normal output current flow (Minimum at Vo = 0 V, maximum at Vo = VDD).
*4: 50 ns or less.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Power supply voltage*
Symbol
Unit
Min.
3.0
Max.
3.6
VDD
VIH
VIL
V
V
V
“H” level input voltage
“L” level input voltage
CMOS input
CMOS input
VDD × 0.65
VSS
VDD
VDD × 0.25
Differential input voltage
(for data transfer)
Cable input
Cable input
VID
142
173
260
260
mV
mV
Differential input voltage
(for arbitration)
VIDA
Common mode input voltage
Receiving input jitter
Cable input
Cable input
Cable input
CMOS output
TPBIAS
VCM
—
1.165
—
2.515
1.08
0.8
V
ns
Receiving input skew
—
—
ns
IOH/IOL
Iot
–4
–2
0
4
mA
mA
°C
Output current
10
Operating temperature
Ta
+70
* : Voltage values are based on Vss = 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
14
MB86612
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
1.1 System Interface, etc
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C)
Value
Unit
Parameter
Symbol Conditions
Min.
VDD × 0.65
VSS
Typ.
—
Max.
VDD
“H” level input voltage
“L” level input voltage
“H” level output voltage
“L” level output voltage
VIH
VIL
VOH
VOL
ILI
CMOS
CMOS
V
V
—
VDD × 0.25
VDD
IOH = –4 mA
IOL = –4 mA
VDD – 0.5
VSS
—
V
—
0.4
V
Input pins
–5
—
5
µA
Input leak current
VI = 0V to VDD
3-state pin
input
ILZ
Rp
–5
25
—
—
50
—
5
µA
kΩ
mA
Input pull-up/pull down resistance
VIH = VDD
200
220
No port
IDDS0
connected*1
1 port
IDDS1
IDDS2
IDDSS
—
—
—
—
—
—
270
300
50
mA
mA
mA
connected*1
2 ports
connected*1
Power supply current
Forced
sleep*1
Non
IDDCN
IDDCR
—
—
—
—
220
240
mA
mA
repeating*2
Repeating*2
*1: Operating from system power supply
*2: Operating from cable power supply
1.2 1394 Interface Driver
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C)
Value
Unit
Parameter
Symbol
Conditions
Min.
172
Max.
265
Differential output voltage
Common phase current
Off state voltage
VOD
ICM
R1 = 56 Ω
Driver enabled
Driver disabled
—
mV
mA
mV
V
–0.81
—
0.44
20
VOFF
VO
TPBIAS output voltage
1.665
2.015
15
MB86612
1.3 1394 Interface - Comparator
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70°C)
Value
Unit
Parameter
Symbol
Conditions
Min.
Max.
Common phase input current
IIC
Driver disabled
Driver disabled
–20
20
µA
Arbitration comparator “H” level
threshold voltage
VSCH
168
–30
—
—
30
mV
Arbitration comparator “Z” level
threshold voltage
VSEZ
VSCL
VSD
Driver disabled
Driver disabled
Driver disabled
Driver disabled
mV
mV
V
Arbitration comparator “L” level
threshold voltage
–168
—
Port status comparator disconnection
detect voltage
0.6
—
Port status comparator connection
detect voltage
VSC
1.0
V
16
MB86612
2. AC Characteristics
2.1 System Clock
Value
Typ.
8.192
1/fc
Parameter
Symbol
Unit
Min.
—
Max.
Clock frequency
Clock cycle time
fC
—
—
MHz
ns
tCLF
—
tCLCH
tCLCL
Clock pulse width
Clock rise/fall time
50
—
—
—
—
5
ns
ns
tCR
tCF
tCLCH
tCLF
tCF
tCR
0. 65 VDD
0. 25 VDD
CLK
tCLCL
2.2 System Reset
Parameter
Value
Symbol
Unit
ns
Min.
4 tclf
Max.
Reset (RESET) “L” level pulse width
tWRSL
—
tWRSL
RESET
17
MB86612
2.3 Driver
Value
Parameter
Symbol
Unit
Min.
—
Max.
±0.8
±0.8
3.2
Sending jitter
tJT
tSK
tDR
tDF
ns
ns
ns
ns
Sending skew
—
Sending rise time*
Sending fall time*
—
—
3.2
* : 10 to 90% value.
18
MB86612
2.4 System Interface
(1) 68-Series Register Write Operation (multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
10
5
Max.
tAWSM
tAWHM
tCWSM
tCWHM
tDWSM
tDWHM
tRWSM
tRWHM
tDWD
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
CS setup time
10
5
CS hold time
Data setup time
10
0
Data hold time
R/W setup time
5
R/W hold time
5
ALE fall to DS fall time
DS rise to ALE rise time
ALE “H” level pulse width
DS “L” level pulse width
10
5
tLWD
tALE
10
20
tDSM
tCWSM
tCWHM
tRWHM
CS
tRWSM
R/W
ALE
DS
tLWD
tALE
tDWD
tDSM
tAWSM
tAWHM
tDWSM
tDWHM
D15 to D6, D0
AD5 to AD1
Address
Data
19
MB86612
(2) 68-System Register Read Operation (multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
10
5
Max.
—
tARSM
tARHM
tCRSM
tCRHM
tRLDM
tRHDM
tRWSM
tRWH
tDRD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
—
CS setup time
10
5
—
CS hold time
—
Data output definition time
Data output disabled time
R/W setup time
—
0
15
—
5
—
R/W hold time
5
—
ALE fall to DS fall time
DS rise to ALE rise time
ALE “H” level pulse width
DS “L” level pulse width
10
5
—
tLRD
—
tALE
10
20
—
tDSM
—
tCRSM
tCRHM
CS
R/W
ALE
DS
tRWSM
tRWH
tLRD
tALE
tDRD
tDSM
tARSM
tARHM
tRLDM
tRHDM
D15 to D6, D0
AD5 to AD1
Address
Defined data
20
MB86612
(3) 68-Series Register Write Operation (non-multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
5
Max.
tAWS
tCWS
tCWH
tDWS
tDWH
tDS
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS setup time
5
CS hold time
5
Data setup time
Data hold time
10
0
DS “L” level pulse width
R/W setup time
20
5
tRWS
tRWH
tAWH
R/W hold time
5
DS rise to address hold time
5
tCWS
tRWS
tCWH
tRWH
CS
R/W
tDS
DS
tAWS
tAWH
A5 to A0
Address
tDWS
tDWH
D15 to D6, D0
AD5 to AD1
Data
21
MB86612
(4) 68-Series Register Read Operation (non-multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
5
Max.
—
tARS
tCRS
tCRH
tRLD
tRHD
tDS
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS setup time
5
—
CS hold time
5
—
Data output definition time
Data output disabled time
DS “L” level pulse width
R/W setup time
—
0
15
—
20
5
—
tRWS
tRWH
tARH
—
R/W hold time
5
—
Address hold time
5
—
tCRS
tRWS
tCRH
tRWH
CS
R/W
tDS
DS
tARS
tARH
A5 to A0
Address
tRLD
tRHD
D15 to D6, D0
AD5 to AD1
Defined data
22
MB86612
(5) 80-Series Register Write Operation (multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
10
5
Max.
tAWSM
tAWHM
tCWSM
tCWHM
tDWSM
tDWHM
tDWD
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
CS setup time
10
5
CS hold time
Data setup time
10
0
Data hold time
ALE fall to WR fall time
WR rise to ALE rise time
ALE “H” level pulse width
WR “L” level pulse width
10
5
tLWD
tALE
10
20
tWRM
tCWSM
tCWHM
CS
ALE
WR
tALE
tDWD
tLWD
tWRM
tAWSM
tAWHM
tDWSM
tDWHM
D15 to D6, D0
AD5 to AD1
Address
Data
23
MB86612
(6) 80-Series Register Read Operation (multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
10
5
Max.
—
tARSM
tARAHM
tCRSM
tCRHM
tRLDM
tRHDM
tDRD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
—
CS setup time
10
5
—
CS hold time
—
Data output definition time
Data output disabled time
ALE fall to RD fall time
RD rise to ALE rise time
ALE “H” level pulse width
RD “L” level pulse width
—
0
15
—
10
5
—
tLRD
—
tALE
10
20
—
tRDM
—
tCRSM
tCRHM
CS
ALE
RD
tALE
tDRD
tLRD
tRDM
tARSM
tARAHM
tRLDM
tRHDM
D15 to D6, D0
AD5 to AD1
Address
Defined data
24
MB86612
(7) 80-Series Register Write Operation (non-multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
5
Max.
tAWS
tCWS
tCWH
tDWS
tDWH
tWR
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
CS setup time
5
CS hold time
5
Data setup time
Data hold time
10
0
WR “L” level pulse width
Address hold time
20
5
tAWH
tCWS
tCWH
CS
tWR
WR
tAWS
tAWH
A5 to A0
Address
tDWS
tDWH
D15 to D6, D0
AD5 to AD1
Data
25
MB86612
(8) 80-Series Register Read Operation (non-multiplexed)
Value
Parameter
Address setup time
Symbol
Unit
Min.
5
Max.
—
tARS
tCRS
tCRH
tRLD
tRHD
tRD
ns
ns
ns
ns
ns
ns
ns
CS setup time
5
—
CS hold time
5
—
Data output definition time
Data output disabled time
RD “L” level pulse width
Address hold time
—
0
15
—
20
5
—
tARH
—
tCRS
tCRH
CS
RD
tRD
tARS
tARH
A5 to 0
Address
tRLD
tRHD
D15 to D6, D0
AD5 to AD1
Defined data
26
MB86612
2.5 Isochronous Interface
2.5.1 ICLK
Value
Parameter
Symbol
Unit
Min.
DC
Max.
Clock frequency
Clock cycle time
—
16
MHz
ns
tICLK
62.5
∞
tICLH
tICLL
Clock pulse width
Clock rise/fall time
10
—
—
ns
ns
tICR
tICF
10
tICLK
tICLH
tICF
tICR
0. 65 VDD
0. 25 VDD
ICLK
tICLL
27
MB86612
2.5.2 Sending Operation
(1) Start Sending Operation
Value
Parameter
Symbol
Unit
Min.
Max.
IDIR fall to ILWRE fall
ICLK rise to ILWRE fall
ILWRE fall to IV fall
IV fall to ICLK rise
Data setup time
tDLLL
tCHLL
tLLVL
tVLCH
tIDS
—
4 ticlk + 10
ns
ns
ns
ns
ns
ns
ns
ns
—
40
1 ticlk + 10
—
20
20
0
—
—
Data hold time
tIDH
—
TS input setup time*
TS input hold time*
tTSS
tTSH
20
20
1 ticlk – 10
1 ticlk – 10
ICLK
IDIR
tCHLL
tDLLL
ILWRE
IV
tVLCH
tLLVL
tTSS
tTSH
TS
tIDS
tIDH
3
1
2
ID7 to ID0
* : Specifications tIDH and tTSS are valid in DVC mode only. TS input is not used in MPEG mode.
28
MB86612
(2) End Sending Operation
Parameter
Value
Symbol
Unit
Min.
—
Max.
ICLK rise to ILWRE rise
ILWRE rise to IV rise
ILWR negate time*
tCHLH
tLHVH
tLWH
40
—
—
ns
ns
ns
1 ticlk + 10
2 ticlk – 10
ICLK
IDIR
tCHLH
tLWH
ILWRE
IV
tLHVH
N - 2
N
1
ID7 to ID0
N - 1
* : The MB86612 operates in ‘negate mode’, in which the ILWRE signal is negated for each source packet received,
as well as ‘assert mode’, in which the ILWRE signal is continuously asserted as long as ISO sending and receiving
FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or more packets
of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again asserted.Note that
even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the ILWRE signal is negated
according to the timing shown above, and re-asserted when writing is again enabled.
29
MB86612
(3) IV Temporary Negation in Sending Operation
Value
Parameter
ICLK rise to IV rise
Symbol
Unit
Min.
0
Max.
1 ticlk – 20
—
tCHVH
tIDS
ns
ns
ns
Date setup time
Data hold time
20
0
tIDH
—
ICLK
IDIR
ILWRE
IV
tCHVH
tIDS
tIDH
N − 1
N
N + 1
ID7 to ID0
30
MB86612
2.5.3 Receiving Operation
(1) Start Receiving Operation
Value
Parameter
Symbol
Unit
Min.
Max.
ICLK rise to ILWRE fall
ILWRE fall to IERR fall*1
ILWRE fall to IV fall
tCHLL
tLLEL
—
40
ns
ns
ns
ns
ns
ns
ns
—
1 ticlk + 10
tLLVL
1 ticlk + 10
—
—
20
10
—
IV fall to ICLK rise
tVLCH
tVLIDV
tCLIDX
tTSWL
20
Data output definition time
Data output disable time
TS output assert time*2
—
0
32 ticlk – 10
ICLK
IDIR
tCHLL
ILWRE
tLLEL
IERR
tTSWL
3
TS*
tLLVL
tVLCH
IV
tCLIDX
tVLIDV
ID7 to ID0
Hi − Z
1
2
*1: The IERR signal is output when an error is detected in receiving data.
*2: Specification tD is valid only in DVC mode. It does not apply to MPEG mode.
*3: The TS signal is output in synchronization with the rise of the ICLK pulse at the time the receiving packet time
stamp match is detected.
31
MB86612
(2) End Receiving Operation
Parameter
Value
Symbol
Unit
Min.
—
Max.
40
ICLK rise to ILWRE rise
ILWRE rise to IV rise
tCHLH
tLHVH
tVHIDX
tLWH
ns
ns
ns
ns
1 ticlk + 10
—
—
Final data output disable time
ILWRE negate time*1
20
2 ticlk – 10
—
ICLK
IDIR
tCHLH
tLWH
ILWRE
2
IERR*
2
TS*
tLHVH
IV
tVHIDX
ID7 to ID0
N - 2
N - 1
N
Hi − Z
*1: The MB86612 operates in ‘negate mode’, in which the ILWRE signal is negated for each source packet received,
as well as ‘assert mode’, in which the ILWRE signal is continuously asserted as long as ISO sending and
receiving FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or
more packets of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again
asserted.Note that even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the
ILWRE signal is negated according to the timing shown above, and re-asserted when writing is again enabled.
*2: The TS (in MPEG mode) and IERR signals are negated in synchronization with the ILWRE signal.
32
MB86612
(3) IV Temporary Negation in Receiving Operation
Value
Parameter
IV rise to ICLK rise
Symbol
Unit
Min.
Max.
tVHCH
40
—
ns
ICLK
IDIR
ILWRE
IV
tVHCH
N − 1
N
Hi − Z
N + 1
ID7 to ID0
33
MB86612
■ INTERNAL REGISTERS
The MB86612 internal registers have 3-bank construction, with 16-bit access to all registers.
Bank 0 contains registers necessary for IEEE 1394 settings and transfer, bank 1 contains registers necessary
for AV/C (MPEG, DVC) operation, and bank 2 contains CSR’s.
In addition each bank has registers used in common for MB86612 device control.
1. Bank Common Registers
The following registers can be accessed in any bank from bank 0 to bank 2.
Address
Write operation
Read operation
HEX A5 A4 A3 A2 A1
00
02
04
06
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
mode-control register
(reserved)
←
flag & status register
←
instruction fetch register
interrupt mask register
interrupt code register
Receiving acknowledge display
register
08
0
0
1
0
0
(reserved)
0A
0C
0E
3E
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
ASYNC data port (sending)
(reserved)
ASYNC data port (receiving)
←
←
←
(reserved)
bank select register
34
MB86612
2. Bank 0 Registers
Bank 0 contains the registers required for 1394 settings and transfers.
Access to this bank is enabled by writing ‘0000h’ to the bank select register (3Eh).
Address
Write operation
Read operation
HEX A5 A4 A3 A2 A1
Sending ISO PKT header
setting register (high)
Receiving ISO PKT header
display register (high)
10
12
14
16
18
1A
1C
1E
20
22
24
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Sending ISO PKT header
setting register (low)
Receiving ISO PKT header
display register (low)
Sending ASYNC des ID
setting register
(reserved)
Sending ASYNC PKT param
setting register
Receiving ASYNC PKT param
display register
Sending ASYNC data length
setting register
Receiving ASYNC data length
display register
Sending ASYNC ex tcode
setting register
Receiving ASYNC ex tcode
display register
Sending ASYNC source ID
setting register
Receiving ASYNC source ID
display register
Sending ASYNC resp param
setting register
Receiving ASYNC resp param
display register
Sending ASYNC des offset
setting register (high)
Receiving ASYNC des offset
display register (high)
Sending ASYNC des offset
setting register (middle)
Receiving ASYNC des offset
display register (middle)
Sending ASYNC des offset
setting register (low)
Receiving ASYNC des offset
display register (low)
26
28
2A
2C
2E
30
1
1
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
(reserved)
(reserved)
←
PHY ID display register
(reserved)
NODE config display register
PORT config display register (port0)
PORT config display register (port1)
root ID display register
(reserved)
(reserved)
state clear setting register
ISO resource manager ID
display register
32
1
1
0
0
1
Self ID PKT param setting register
34
36
1
1
1
1
0
0
1
1
0
1
(reserved)
(reserved)
←
←
cycle timer monitor
display register (high)
38
1
1
1
0
0
(reserved)
cycle timer monitor
display register (low)
3A
3C
1
1
1
1
1
1
0
1
1
0
(reserved)
(reserved)
←
35
MB86612
3. Bank 1 Registers
Bank 1 contains the registers required for AV/C (MPEG, DVC) protocols.
Access to this bank is enabled by writing ‘0001h’ to the bank select register (3Eh).
Address
Write operation
Read operation
HEX A5 A4 A3 A2 A1
Sending time stamp offset
setting register
Receiving time stamp
display register (high)
10
12
14
16
18
1A
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Sending time stamp offset
setting register
Receiving time stamp
display register (low)
Sending CIP header
setting register (highest)
Receiving CIP header
display register (highest)
Sending CIP header
setting register (high)
Receiving CIP header
display register (high)
Sending CIP header
setting register (low)
Receiving CIP header
display register (low)
Sending CIP header
setting register (lowest)
Receiving CIP header
display register (lowest)
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OMPR (high)
OMPR (low)
OPCR0 (high)
OPCR0 (low)
(reserved)
←
←
←
←
←
(reserved)
←
(reserved)
←
(reserved)
←
IMPR (high)
IMPR (low)
←
←
IPCR0 (high)
IPCR0 (low)
(reserved)
←
←
←
(reserved)
←
(reserved)
←
←
(reserved)
AV mode setting register
AV status register
36
MB86612
4. Bank 2 Registers
Bank 2 contains CSR’s.
Access to this bank is enabled by writing ‘0002h’ to the bank select register (3Eh).
Address
Write operation
Read operation
HEX A5 A4 A3 A2 A1
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
bus manager ID register (high)
bus manager ID register (low)
bandwidth available register (high)
bandwidth available register (low)
channels available high register (high)
channels available high register (low)
channels available low register (high)
channels available low register (low)
(reserved)
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
37
MB86612
■ ORDERING INFORMATION
Partnumber
Package
Remarks
100-pin plastic LQFP
(FPT-100P-M05)
MB86612PFV
120-pin plastic FBGA
(BGA-120P-M01)
MB86612PBT
38
MB86612
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
(FPT-100P-M05)
1.50−+00..2100
.059 −+..000048
16.00±0.20(.630±.008)SQ
(Mounting height)
75
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
0.15(.006)
100
26
0.15(.006)MAX
0.40(.016)MAX
"B"
1
25
LEAD No.
"A"
0.50(.0197)TYP
0.18−+00..0038
0.127 +−00..0025
.005−+..000012
M
Details of "B" part
0.08(.003)
.007 −+..000013
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0~10˚
C
Dimensions in mm (inches)
1995 FUJITSU LIMITED F100007S-2C-3
120-pin plastic FBGA
(BGA-120P-M01)
9.60(.378)REF
0.80(.031)TYP
12.00±0.10(.472±.004)SQ
1.25 +–00..1200 .049 –+..000048
(Mounting height)
0.38±0.10(.015±.004)
(Stand off)
13
12
11
10
9
8
7
6
0.10(.004)
5
4
3
INDEX
2
1
N
M
L
K
J
H
G
F
E
D
C
B
A
C0.80(.031)
120-Ø0.45±0.10
(120-Ø.018±.004)
M
0.08(.003)
C
Dimensions in mm (inches)
1998 FUJITSU LIMITED B120001S-1C-1
39
MB86612
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9901
FUJITSU LIMITED Printed in Japan
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