MB88146A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-13513-1E

Linear IC Converter

CMOS

D/AConverterforDigitalTuning

(12-channel, 8-bit, on-chip OP amp., low-voltage)

MB88146A

■ DESCRIPTION

The MB88146A is an 8-bit D/A converter with twelve built-in channels. The 12 analog outputs each have a built-

in OP amplifier with large current drive-capability.

The data input/output format is CS (chip select) with serial bus connection available.

A built-in 12-bit I/O expander enables serial ↔ parallel conversion (8 of the 12 bits can also be used for analog

output).

This product can be used for microcontroller port expansion, electronic level adjustment, replacement of semi-

fixed resistance for tuning, etc.

■ FEATURES

• Ultra low power consumption (1.2 mW/chl: typical)

• Ultra compact package

• Built-in 12-channel R-2R type 8-bit D/A converter

• Built-in 12-bit I/O expander (8 bits also function as analog output)

• Built-in analog output amplifier (sink current 1.0 mA maximum, source current 1.0 mA maximum)

• Built-in power-on detection circuit (initialized at detection of VccD power-on)

• MCU interface compatible with 3 V to 5 V systems

• Power divided into MCU interface power supply (VccD) and OP amplifier power supply (VccA), D/A converter

power supply (VccD)

• Analog output capability from 0 V to VccA

• Serial data I/O operates to maximum of 2.5 MHz (in cascade connection, up to 2.5 MHz when VccD = 5 V, up

to 1.5 MHz when VccD = 3 V)

• CMOS process

• Choice of two packages: SDIP-24 pin and SSOP-24 pin.

■ PACKAGES

24-pin Plastic DIP

(DIP-24P-M02)

24-pin Plastic SSOP

(FPT-24P-M03)

MB88146A

■ PIN ASSIGNMENT

(TOP VIEW)

AO¹

AO²

1

24

23

22

21

20

19

18

17

16

15

14

13

GND

V^CCA

CS

SO

SI

2

AO3

3

AO4

4

D11/AO5

D10/AO6

D9/AO7

D8/AO8

D7/AO9

D6/AO10

D5/AO11

D4/AO12

5

6

CLK

D⁰

7

8

D1

9

D2

10

11

12

D3

VCCD

V^DD

DIP-24, SSOP-24

2

MB88146A

■ PIN DESCRIPTION

Pin no.

Pin name

Description

1 to 4

AO¹to AO⁴

D/A converter analog output pins (V^DDto GND output).

(Default: output #00 setting level)

5 to 12

D¹¹/AO⁵to

D⁴/AO¹²

These pins may be used either as I/O expander parallel input/output (V^CCA/

GND output 0.5 V^CCA/0.2 V^CCA input) or D/A converter analog output (V^DDto

GND output).

Pin status is controlled by input data.

See “■Data Configuration”. (Default: Input mode, Hi-Z state)

V^DD*¹

V^CCD*¹

D³toD⁰

D/A converter reference power pin.

13

14

MCU interface power supply pin (power supply for I/O expander).

I/O expander parallel input/output pins.

15 to 18

(V^CCD/GND output: When V^CCD

When V^CCD < 4.0 V, 2 V/0.2 V^CCD input)

Pin status is controlled by input data.

4.0 V, 0.5 V^CCD/0.2 V^CCD input,

See “■Data Configuration.” (Default: Input mode, Hi-Z state)

CLK*²

19

Shift clock signal input pin.

When CS = “L,” SI data is loaded into the shift register at the rising edge of the

shift clock.

SI*²

SO

20

21

Data input pin (serial input pin).

Used for 16-bit serial data input.

Data output pin (serial output pin).

The first bit (LSB) data of the 16-bit shift register is output simultaneously with

the falling edge of the shift clock.

When CS output = “H,” this pin goes to high impedance state.

CS*²

22

Chip select signal input pin.

Input to shift registers is enabled when the CS signal falling edges. Shift register

contents can be executed when the CS signal rising edges.

V^CCA*¹

GND

Analog unit power supply pin (OP amplifier power supply).

Common GND pin.

23

24

*1: Be sure that V^CCA

V^CCD, and that V^CCA

V^DD.

*2: Do not leave this pin in floating state.

3

MB88146A

■ BLOCK DIAGRAM

CS

SI

SO

16-bit shift register and controller

CLK

V^CCD

DF DE DD DC DB BA D9 D8 D7 D6 D5 D4

CNTL

D⁰

D1

D2

D3

DF DE DD DC DB BA D9 D8 D7 D6 D5 D4

I/O expander

DF DE

D5 D4

12

DF

D8

DF

D8

DF

D8

DF

D8

8-bit latch

DF

V^DD

R-2R

rudder circuit

R-2R

rudder circuit

R-2R

rudder circuit

R-2R

rudder circuit

GND

−

+

−

+

−

+

−

+

VCCA

8

AO1

AO4

D11/AO5

D4/AO12

4

MB88146A

■ DATA CONFIGURATION

1. Data Configuration

MSB (last)

LSB (first)

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Setting data

Channel select

2. Channel Select

D3

0

D2

0

D1

0

D0

0

Function

Don’t Care/special function

0

1

AO¹selected

0

1

0

AO²selected

to

1

to

0

to

1

to

1

to

AO¹¹selected

1

0

AO¹²selected

1

0

1

I/O expander (serial → parallel)

I/O expander (parallel → serial)

Expander status register (ESR)

1

0

1

5

MB88146A

3. Setting Data

• Don’t Care/special function (Channel select = “0000”)

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4

Analog output voltage level

Don’t Care

to to to to to to to to to to to to Don’t Care

×

0

×

0

×

0

×

0

×

0

×

0

×

0

×

0

1

×

0

1

0

1

0

1

0

1

0

Don’t Care

GND (all channels)

V^DD/256 × 1 (all channels)

V^DD/256 × 2 (all channels)

to to to to to to to to to to to to to

1

×

1

×

1

×

1

×

1

×

1

×

1

×

0

1

×

1

0

1

0

1

0

1

V^DD/256 × 254 (all channels)

V^DD/256 × 255 (all channels)

Hi-Z (I/O expander state)*

Reset (state when power is ON)

Don’t Care

×: Don’t care *: Hi-Z output on all channels of AO⁵through AO¹²

• D/A Converter (Channel select = “0001” to “1100”)

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4

Analog output voltage level

0

1

0

1

0

1

0

GND

V^DD/256 × 1

V^DD/256 × 2

V^DD/256 × 3

to to to to to to to to to to to to to

1

×

1

×

1

×

1

×

1

×

1

×

0

1

×

1

0

1

×

0

1

0

1

0

V^DD/256 × 253

V^DD/256 × 254

V^DD/256 × 255

Hi-Z (I/O expander state)*

Don’t Care

to to to to to to to to to to to to Don’t Care

Don’t Care

×

1

×: Don’t care *: Only AO⁵through AO¹²output is valid

6

MB88146A

• I/O Expander [Channel select = “1101”]: Serial → Parallel Conversion

Performs parallel conversion of data bits D4 to DF for output on pins D⁰to D¹¹.

Note that only those pins designated for output in the ESR (expander status register) are output.

Shift register

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

↓

Parallel I/O pins (output state)

D¹¹D¹⁰D⁹

D⁸

D⁷

D⁶

D⁵

D⁴

D³

D²

D¹

D⁰

• I/O Expander [Channel select = “1110”]: Parallel → Serial Conversion

Writes data from D⁰to D¹¹pins to bits D4 to DF in the shift register.

Data is output to the SO pin on the shift clock (CLK) signal (The first 4 bits output data D0 to D3, so the

converted output should be read as data bits 5 through 16.).

Note that the data value is “0” for pins designated for output in the ESR (expander status register) as well as

analog output pins.

Shift register

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

↑

Parallel I/O pins (output state)

D¹¹D¹⁰D⁹

D⁸

D⁷

D⁶

D⁵

D⁴

D³

D²

D¹

D⁰

• Expander Status Register [Channel select = “1111”]

Shift register

ESR

DF DE DD DC DB DA D9 D8 D7 D6 D5 D4

↓

D¹¹D¹⁰D⁹

D⁸

D⁷

D⁶

D⁵

D⁴

D³

D²

D¹

D⁰

This register sets the status of each pin.

Setting

“0”

Pin status

• Input standby status (Hi-Z output)

• D¹¹to D⁴pins used for analog output should be set to “0.”

“1”

• Output state

7

MB88146A

Note: After power V^CCD is turned on, the state of pins and registers is as follows.

State

AO¹to AO⁴

“L” output

D¹¹/AO⁵to D⁴/AO¹²

D³to D⁰

Hi-Z state (input state)

Register

Shift register

State

Bits DF to D8 are “0,” and D7 to D0 are not defined (retain prior state).

All reset to “0.”

D/A register

Parallel output register

Not defined (retain prior state).

Expander status register (ESR) All reset to “0.”

• ESR settings have priority in determining pin states. Switching between input standby state and analog output

state is enabled even when the ESR value is “1.” When the ESR value returns to “0”, the pin returns to its

previously defined state.

• In input standby state with AO set for Hi-Z output, the AO output setting can be used for transition to AO output

state.

8

MB88146A

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Conditions

Unit

Min.

–0.3

—

Max.

+7.0

V^CCA

V^CCD

V^DD

V

Based on GND

(Ta = +25°C)

Power supply voltage

V^CCA*

V

Input voltage 1

Vⁱⁿ1

V^out1

Vⁱⁿ2

V^out2

P^D

V^CCD + 0.3

V^CCA + 0.3

250

V

SI, CLK, CS,

SO, D⁰to D³

Output voltage 1

Input voltage 2

V

D⁴to D¹¹

Output voltage 2

Power consumption

Operating temperature

Storage temperature

V

—

mW

°C

Ta

–20

–55

+85

T^stg

+150

* : V^CCA

V^CCD, V^CCA

V^DD

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Power supply voltage

Analog output current

Symbol

Conditions

Unit

Min.

4.5

Typ.

5.0

—

Max.

5.5

V^CCA

V^CCD

—

V

2.7

V^CCA

V^CCD

V^DD

GND

I^AL

2.0

—

0

V^CCA

—

V

—

Source current

Sink current

—

1.0

mA

I^AH

Oscillation limit output

capacity

C^OL

Ta

—

1.0

µF

°C

Operation temperature

–20

+85

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

9

MB88146A

■ ELECTRICAL CHARACTERISTIC

1. DC Characteristics

(1) Digital section

(V^CCD

V^CCA, Ta = –20°C to +85°C)

Value

Unit

Parameter

Symbol Pin name

Conditions

Min.

Typ.

Max.

Power supply voltage

Power supply current

V^CCD

—

2.7

5.0

5.5

V

CLK =1 MHz,

(Unloaded)

I^CCD

—

0.2

0.5

mA

V^CCD

CLK, SI, CS Stop

Vⁱⁿ= V^CCD or

GND

Standby current

I^CCS

–10

—

+10

µA

Input leak current

I^ILK1

Vⁱⁿ= 0 to V^CCD

—

+10

—

µA

V

CLK, SI,

CS,

D⁰to D³

0.5 × V^CCD

V^CCD

4.0 V

“H” level input voltage

V^IH1

V^CCD < 4.0 V

—

2.0

—

V

“L” level input voltage

V^IL1

I^OLK

0.2 × V^CCD

V

High-impedance leak

current

SO

Vⁱⁿ= 0 to V^CCD

–10

—

+10

µA

“H” level output voltage

“L” level output voltage

V^OH1

V^OL1

I^OH= –0.4 mA

I^OL= 2.5 mA

V^CCD − 0.4

—

V

SO,

D⁰to D³

—

0.4

(2) D/A converter section

(V^CCA= 5 V ± 10%, Ta = –20°C to +85°C)

Value

Unit

Parameter

Symbol Pin name

Conditions

Min.

Typ.

Max.

Power supply voltage

V^DD

I^DD

2.0

5.0

5.5

V

V^DD

V^CCA

Power supply current

Resolution

—

1.2

8

2.5

—

mA

bits

Res

Unload

Monotonic increase

Nonlinearity error

Rem

—

8

—

bits

V^DD= V^CCA – 0.1 V

Digital value: #06

to #FF

AO¹to AO¹²

LE

–1.5

–1.0

—

+1.5

+1.0

LSB

Differential linearity error DLE

Nonlinearity error:

Deviation (error) in input/output

curves with respect to an ideal

straight line connecting output

voltage at “06” and output voltage

at “FF.”

Ideal straight line

Non linearity error

VAOH

Differential linearity Deviation (error) in amplification with

VAOL

Digital setting

error:

respect to theoretical increase in

amplification per 1-bit increase in

digital value.

#06

#FF

Note: The value of V^AOHand VDD, and the value of VAOL

and GND are not necessarily equivalent.

10

MB88146A

(3) Operational Amplifier/Analog output section

(V^DD= V^CCA = 5.0 V, Ta = –20°C to +85°C)

Value

Unit

Parameter

Symbol Pin name

Conditions

Min.

Typ.

Max.

Power supply voltage

Power supply current

Input leak current

V^CCA

—

4.5

5.0

5.5

V

mA

µA

V

V^CCA

#80 setting

(Unloaded)

I^CCA

—

–10

1.0

—

3.7

+10

—

I^ILK2

V^IH2

Vⁱⁿ= 0 to V^CCA

“H” level digital input

voltage

—

0.5 × V^CCA

—

“L” level digital input

voltage

V^IL2

—

0.2 × V^CCA

—

V

D⁴to D¹¹

“H” level digital output

voltage

V^OH2

V^OL2

I^OH= –0.4 mA

I^OL= 2.5 mA

V^CCA − 0.4

—

“L” level digital output

voltage

—

0.4

Analog output minimum

voltage 1

I^AL= 0 A

#00 setting

V^AOL1

V^AOL2

GND

—

0.1

Analog output minimum

voltage 2

I^AL= 0.5 mA

#00 setting

–0.2

GND

—

0.2

Analog output minimum

voltage 3

I^AH= 0.5 mA

#00 setting

V^AOL3

V^AOL4

V^AOL5

V^AOH1

V^AOH2

V^AOH3

V^AOH4

V^AOH5

AO¹to AO¹²

GND

0.2

Analog output minimum

voltage 4

I^AL= 1.0 mA

#00 setting

–0.3

GND

—

0.3

Analog output minimum

voltage 5

I^AH= 1.0 mA

#00 setting

GND

0.3

Analog output

maximum voltage 1

I^AL= 0 A

#FF setting

V^CCA − 0.1

V^CCA − 0.2

V^CCA − 0.3

—

V^CCA

V^CCA+ 0.2

V^CCA

V^CCA+ 0.3

Analog output

maximum voltage 2

I^AL= 0.5 mA

#FF setting

—

Analog output

maximum voltage 3

I^AH= 0.5 mA

#FF setting

AO¹to AO¹²

V^CCA

—

Analog output

maximum voltage 4

I^AL= 1.0 mA

#FF setting

Analog output

maximum voltage 5

I^AH= 1.0 mA

#FF setting

V^CCA

Note: I^AH: Analog output sink current I^AL: Analog output source current

11

MB88146A

2. AC Characteristics

• For operation at V^CCD = 5.0 V

(V^DD= V^CCA = 5.0 V, Ta = –20°C to +85°C)

Value

Unit

Parameter

Symbol

Conditions

Min.

200

—

Typ.

—

Max.

—

Clock “L” level pulse width

Clock “H” level pulse width

Clock rise time

t^CKL

t^CKH

t^Cr

—

ns

µs

ms

—

200

—

Clock fall time

t^Cf

—

Serial input setup time

Serial input hold time

Serial output delay time

CS input setup time

t^SSU

t^SHD

t^SOD

t^CSU

t^CCH

t^CSH

t^SO

—

30

—

60

—

See “Load condition 1”

0

80

—

170

—

100

200

100

—

CS hold time

—

CS “H” level hold time

Data output enable time

Data output float time

Parallel input setup time

Parallel input hold time

Parallel output delay time

Analog output delay time

Power supply rise time

—

200

—

t^SOZ

t^PSU

t^PHD

t^POD

t^AOD

t^R

—

30

—

60

—

See “Load condition 1”

See “Load condition 2”

—

100

30

—

170

100

50

—

Power-on reset non-startup power

supply variation

∆V^R

—

–10

—

10

V/µs

• For operation at V^CCD = 3.0 V *¹

(V^CCD = 3.0 V, Ta = –20°C to +85°C)

Value

Unit

Parameter

Symbol

Conditions

Min.

0

Typ.

120

Max.

300

Serial output delay time

Parallel output delay time

t^SOD

t^POD

See “Load condition 1”*²

See “Load condition 2”*³

ns

—

300

*1: Items not listed are identical to characteristics for V^CCD = 5.0 V.

*2: Cascade connection enabled at 1.5 MHz.

*3: Applied to D0 to D3 operating at V^CCD.

Load Conditions

• Load condition 1

• Load condition 2

Measurement point

RAL = 10 kΩ

CAL = 50 pF

CL = 20 pF to 100 pF

12

MB88146A

• Input/Output Timing (CS method)

tCr

tCKH

tCf

CLK

SI

tCKL

tCSH

tSSU

tSHD

tCCH

tCSU

CS

tSO

tSOD

tSOZ

SO

tPSU

tPHD

D⁰to D11 (For input)

D⁰to D11 (For output)

AO¹to AO12

tPOD

tAOD

90 %

10 %

The decision level for CLK, SI, CS, SO, and D0 to D3 is 80% and 20% of VCCD. The decision level for D4 to D11 is 80%

and 20% of V^CCA, and for AO1 to AO12 is 90% and 10% of VCCA.

• Power Supply Timing

• Power-On Timing

tR

2.0 V

V^CCD

0.2 V

• Power-On Reset Non-Startup Supply Variation

Upper limit, 5.5V

∆V

V^CCD

∆V

∆T

∆VR =

∆T

2.7V, lower limit

13

MB88146A

3. Analog Output Noise Characteristic

(V^DD= V^CCD = V^CCA = 5.0 V, Ta = +25°C)

Value

Measurement

Unit

Parameter

Symbol

Conditions

f^NOISE= 1 kHz

condition

Min. Typ. Max.

Digital supply noise

reduction ratio

P^SRD

P^SRA

1

—

20

0

dB

Analog supply noise

reduction ratio

f^NOISE= 1 kHz

D/A supply noise

reduction ratio

P^SRDA

• During serial transfer

• During analog operation

• During Hi-Z commands.

See “Operating Noise V^N1.”

Operating noise

V^N1

2

–30

—

30 mV

• Serial → parallel conversion

See “I/O Expander Operating

Noise 1 V^N2.”

During digital-only pin operation

• During parallel → serial conversion

• ESR setting

I/O expander operating

noise 1

V^N2

2

–30

—

30 mV

During digital input/digital output

switching

• During serial → parallel conversion

See “I/O Expander Operating

Noise 2 V^N3.”

During digital/analog capable pin

operation

I/O expander operating

noise 2

V^N3

2

–0.1

—

0.1

V

• ESR setting

During digital output/digital output

switching

• Measurement condition 1

• Measurement condition 2

V^CCD = 5.0 V,VCCA = 5.0 V,VDD = 5.0 V

V^CCD,VCCA,VDD

Measurement point

AO

Pattern

input

DUT

C^AL= 30 pF

CLK = 2.5 MHz

SI

Input wave form

Sine wave

Offset

Amplitude

5.0 V

0.1 V

CS

Temperature 25°C

Frequency 1 kHz

14

MB88146A

• Analog Output Noise Description

• Output Noise V^N1

Noise to analog output during serial data transfer, analog operation, Hi-Z commands.

CLK

SI

Analog operation commands, Hi-Z commands

CS

Analog output

Digital input*

AO×

D¹¹/AO5

to

D0/AO12

analog output

AO1

to

AO12

V^N1

VN1

* Hi-Z state = digital input state.

• I/O Expander Operation Noise 1 V^N2

Noise to analog output during parallel → serial conversion commands, serial → parallel conversion command for

digital-only pins, or ESR setting commands for switching between digital input and digital output.

CLK

SI

Parallel → serial conversion, serial → parallel conversion, ESR setting commands

CS

D3

to

D0

Parallel output

Digital input

D¹¹

to

digital output

D0

AO1

to

AO12

VN2

(Continued)

15

MB88146A

(Continued)

• I/O Expander Operation Noise 2 V^N3

Noise to analog output during serial → parallel switching commands for digital-only pins, or ESR setting commands

for switching between digital output and analog output.

CLK

SI

Serial → parallel switching commands, ESR setting commands

CS

D11

to

D4

Parallel output

Digital output

D¹¹/AO5

D0/AO12

analog output

AO1

to

AO12

VN3

16

MB88146A

■ DATA INPUT/OUTPUT TIMING

MB88146A Data Input/Output Timing (Serial Bus Format)

• D/A converter operation, and I/O expander (serial → parallel conversion) operation, and ESR writing operation.

SI

D0

D1

D2

DE

DF

CLK

1

2

3

15

16

CS

AO×

D××

SO

Data input is enabled at the falling edge of the CS signal. 16-bit data is input, and the shift register command is

executed at the rising edge of CS.

In D/A converter operation, the analog output selected at the rising edge of CS is the conversion result. In serial

→ parallel conversion, the digital output selected at the rising edge of CS is the conversion result. In ESR write

operation, ESR data is set and pin status determined at the rising edge of CS.

• I/O expander (parallel → serial conversion) operation

SI

D0

DF

CLK

1

2

16

CS

D××

Retrieved parallel data

D0

DF

SO

Parallel-to-serial → Conversion result output

Data input is enabled at the falling edge of the CS signal. 16-bit data (parallel → serial conversion commands)

is input and commands accepted at the rising edge of CS. At the falling edge of CS, data from the parallel input

is loaded into bits D4 to DF of the shift register, and output from the SO pin timed to the falling edge of the CLK

signal.

17

MB88146A

■ USAGE PRECAUTIONS

1. Preventing Latch-Up

A condition known as “latch-up” may occur when the input or output pins of a CMOS IC device are exposed to

voltages higher then V^CCD or V^CCA or lower than GND voltage, or when voltages are applied to the device in

excess of rated values for V^CCD, VccA, or V^DDto GND voltages. Latchup produces a rapid increase in power

supply current, and may result in thermal destruction of elements. Users should take sufficient precautions to

ensure that absolute maximum ratings are not exceeded at any time during use.

2. Power Supply Pins

The power supply should be connected to the V^CCD, V^CCA, V^DD, and GND terminals of the MB88146A with as

low an impedance as possible.

In addition, it is recommended that ceramic capacitors or approximately 0.1 µF be connected as bypass

capacitors between the V^CCD, V^CCA, and V^DDterminals and the GND terminals.

■ ORDERING INFORMATION

Part number

MB88146AP

MB88146APFV

Package

Remarks

24-pin Plastic DIP

(DIP-24P-M02)

24-pin Plastic SSOP

(FPT-24P-M03)

18

MB88146A

■ PACKAGE DIMENSIONS

24-pin Plastic DIP

(DIP-24P-M02)

+0.20

+.008

30.20

^–0.301.189^–.012

INDEX-1

13.55±0.25

(.533±.010)

INDEX-2

0.51(.020)MIN

4.96(.195)

MAX

3.00(.118)

MIN

0.25±0.05

(.010±.002)

+0.50

–0

+0.50

0.98

1.50

–0

0.45±0.08

(.018±.003)

.059⁺^–0^.020

+.020

.039^–0

15°MAX

15.24(.600)

TYP

1.27(.050)

MAX

2.54(.100)

TYP

C

1994 FUJITSU LIMITED D24015S-2C-3

Dimensions in mm (inches)

24-pin Plastic SSOP

* : These dimensions do not include resin protrusion.

(FPT-24P-M03)

7.75±0.10(.305±.004)

1.25^–⁺⁰⁰^.^.¹²⁰⁰

*

Mounting height

.049⁺^–.^.⁰⁰⁰⁰⁴⁸

0.10(.004)

*

5.60±0.10

7.60±0.20

6.60(.260)

NOM

(.220±.004) (.299±.008)

INDEX

"A"

0.22^–⁺⁰⁰^.^.⁰¹⁵⁰

.009^–⁺^.^.⁰⁰⁰⁰²⁴

0.15^–⁺⁰⁰^.^.⁰⁰²⁵

Details of "A" part

0.65±0.12(.0256±.0047)

.006–⁺.^.0⁰0⁰1²

0.10±0.10(.004±.004)

(STAND OFF)

7.15(.281)REF

0

10°

0.50±0.20

(.020±.008)

C

1994 FUJITSU LIMITED F24018S-2C-2

Dimensions in mm (inches)

19

MB88146A

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9811

FUJITSU LIMITED Printed in Japan

20


型号：	MB88146A
厂家：	FUJITSU
描述：	D/A Converter for Digital Tuning (12-channel, 8-bit, on-chip OP amp., low-voltage) D / A转换器，用于数字调谐（ 12通道， 8位，片上运算放大器，低电压）转换器运算放大器
文件：	总20页 (文件大小：260K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB88146A [FUJITSU]

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