MB89130_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12510-9E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89130/130A Series

MB89131/P131/133A/P133A/135A/

MB89P135A/PV130A

■ DESCRIPTION

The MB89130/130A series has been developed as a general-purpose version of the F²MC*-8L family consisting

of proprietary 8-bit, single-chip microcontrollers.

In addition to a compact instruction set, the microcontrollers contain a great variety of peripheral functions such

as timers, a serial interface, an A/D converter, and external interrupts. The MB89130A series also include a

remote control transmitting output and wake-up interrupt function.

* : F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• F²MC-8L family CPU core

• Low-voltage operation (when an A/D converter is not used)

• Low current consumption (applicable to the dual-clock system)

• Minimum execution time : 0.95 µs at 4.2 MHz

• 21-bit timebase timer

• I/O ports : max. 36 ports

• External interrupt 1 : 3 channels

• External interrupt 2 (wake-up function) : 8 channels (only for the MB89130A series)

• 8-bit serial I/O : 1 channel

(Continued)

■ PACKAGE

48-pin plastic QFP

48-pin plastic SH-DIP

48-pin ceramic MQFP

(FPT-48P-M13)

(DIP-48P-M01)

(MQP-48C-P01)

MB89130/130A Series

(Continued)

• 8/16-bit timer/counter : 1 channel

• 8-bit A/D converter : 4 channels

• Remote control transmitting frequency generator (for the MB89130A series only)

• Low-power consumption modes (stop, sleep, and watch mode)

• QFP-48 package, SH-DIP-48 package

• CMOS technology

■ PRODUCT LINEUP

Part number

MB89131

MB89133A

MB89135A

MB89P133A

MB89P131

Item

Mass-produced products

(mask ROM products)

Classification

One-time PROM products

8 K × 8 bits

4 K × 8 bits

(internal PROM, (internal PROM,

4 K × 8 bits

(internal mask

ROM)

8 K × 8 bits

(internal mask

ROM)

16 K × 8 bits

(internal mask

ROM)

to be

programmed

with general-

to be

programmed

with general-

ROM size

purpose EPROM purpose EPROM

programmer)

RAM size

128 × 8 bits

256 × 8 bits

128 × 8 bits

The number of instructions :

Instruction bit length :

Instruction length :

Data bit length :

Minimum execution time :

136

8 bits

1 to 3 bytes

1, 8, 16 bits

0.95 µs at 4.2 MHz

CPU functions

Minimum interrupt processing time : 8.57 µs at 4.2 MHz

Output ports (N-ch open-drain

ports) :

4 (All also serve as peripherals.)

Output ports (CMOS) :

I/O ports (CMOS) :

8

Ports

24 (8 ports also serve as peripherals. For

MB89130A, 16 ports also serve as.)

36

Total :

8/16-bit timer/

counter

8-bit timer/counter × 2 channels or a 16-bit event counter

8 bits

8-bit serial I/O

LSB/MSB first selectable

8-bit resolution × 4 channels

A/D conversion mode (minimum conversion time : 42 µs at 4.2 MHz)

Sense mode (minimum conversion time : 11.4 µs at 4.2 MHz)

Capable of continuous activation by an internal timer

Reference voltage input

8-bit A/D converter

3 independent channels (edge selection, interrupt vector, source flag)

Rising/falling both edges selectable

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in the stop

mode.)

External interrupt 1

(Continued)

2

MB89130/130A Series

Part number

MB89131

MB89133A

MB89135A

MB89P133A

MB89P131

Item

External interrupt 2

(wake-up function)

8 channels (only for level detection)

Remote control

transmitting gener-

ator

1 channel

(Pulse width and cycle selectable by program)

Standby mode

Process

Sleep, stop, and clock mode

CMOS

2.2 to 4.0 V (with the dual-clock option)

2.2 to 6.0 V (with the single-clock option)

Operating voltage*

2.7 V to 6.0 V

* : Varies with conditions such as the operating frequency. (See “■ ELECTRICAL CHARACTERISTICS”.)

(Continued)

3

MB89130/130A Series

(Continued)

Part number

MB89P135

Item

MB89PV130A

Classification

One-time PROM products

Piggyback/evaluation product

16 K × 8 bits

(internal PROM, to be programmed with

general-purpose EPROM programmer)

32 K × 8 bits

(external ROM)

ROM size

RAM size

512 × 8 bits

1 K × 8 bits

The number of instructions

Instruction bit length

: 136

: 8 bits

Instruction length

Data bit length

: 1 to 3 bytes

: 1, 8, 16 bits

CPU functions

Minimum execution time

Minimum interrupt processing time

: 0.95 µs at 4.2 MHz

: 8.57 µs at 4.2 MHz

Output ports (N-ch open-drain ports)

Output ports (CMOS)

: 4 (All also serve as peripherals.)

: 8

I/O ports (CMOS)

: 24 (8 ports also serve as peripherals. For

Ports

MB89130A, 16 ports also serve as

peripherals.)

: 36

Total

8/16-bit timer/

counter

8-bit timer/counter × 2 channels or a 16-bit event counter

8 bits

8-bit serial I/O

LSB/MSB first selectable

8-bit resolution × 4 channels

A/D conversion mode (minimum conversion time : 42 µs at 4.2 MHz)

Sense mode (minimum conversion time : 11.4 µs at 4.2 MHz)

Capable of continuous activation by an internal timer

Reference voltage input

8-bit A/D converter

3 independent channels (selectable edge, interrupt vector, source flag)

Rising/falling both edges selectable

Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in the

stop mode.)

External interrupt 1

External interrupt 2

(wake-up function)

8 channels (only for level detection)

Remote control

transmitting

frequency

1 channel

(Pulse width and cycle selectable by program)

generator

Standby mode

Process

Sleep, stop, and clock mode

CMOS

Operating voltage

EPROM for use

2.7 V to 6.0 V

MBM27C256A-20TVM

4

MB89130/130A Series

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

FPT-48P-M13

DIP-48P-M01

MQP-48C-P01

MB89131

MB89133A

MB89135A

MB89P133A

MB89P131

×

Package

FPT-48P-M13

DIP-48P-M01

MQP-48C-P01

MB89P135A

MB89PV130A

×

: Available,

: Not available

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that

will actually be used. Take particular care on the following points :

• The number of register banks available is different among the MB89131, MB89133A/135A and MB89P135A/

PV130A.

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

• When operated at low speed, the product with an OTPROM will consume more current than the product with

a mask ROM.

However, the same is current consumption in sleep/stop modes. (For more information, see “■ ELECTRICAL

CHARACTERISTICS”.)

• In the case of the MB89PV130A, added is the current consumed by the EPROM which is connected to the

top socket.

3. Mask Options

Functions that can be selected as options and how to designate these options vary with product.

Before using options, check “■ MASK OPITONS”.

Take particular care on the following point :

• P40 to P43 must be set to no pull-up resistor when an A/D converter is used.

• For MB89P135A, pull-up resistor option cannot be set for P40 to P43.

• Each option is fixed on the MB89PV130A.

5

MB89130/130A Series

■ PIN ASSIGNMENT

(TOP VIEW)

AVCC

RST

MOD0

MOD1

X0

X1

VCC

X0A

X1A

P27

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

P36/INT2

P37/BZ/(RCO)

P00/(INT20)

P01/(INT21)

P02/(INT22)

P03/(INT23)

P04/(INT24)

P05/(INT25)

P06/(INT26)

P07/(INT27)

P10

9

10

11

12

P26

P25

P11

(FPT-48P-M13)

Note : Parenthesized function is available only for the MB89130A series.

6

MB89130/130A Series

(TOP VIEW)

VSS

P16

P15

P14

P13

P12

P11

P10

P07/(INT27)

P06/(INT26)

P05/(INT25)

P04/(INT24)

P03/(INT23)

P02/(INT22)

P01/(INT21)

P00/(INT20)

P37/BZ/(RCO)

P36/INT2

P35/INT1

P34/TO/INT0

P33/EC/SCO

P32/SI

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

P17

P20

P21

P22

P23

P24

P25

P26

P27

X1A

X0A

VCC

X1

X0

MOD1

MOD0

RST

AVCC

P40/AN0

P41/AN1

P42/AN2

P43/AN3

AVR

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P31/SO

P30/SCK

AVSS

(DIP-48P-M01)

Note : Parenthesized function is available only for the MB89130A series.

7

MB89130/130A Series

(TOP VIEW)

AVCC

RST

MOD0

MOD1

X0

X1

VCC

X0A

X1A

P27

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

P36/INT2

P37/BZ/(RCO)

P00/INT20

P01/INT21

P02/INT22

P03/INT23

P04/INT24

P05/INT25

P06/INT26

P07/INT27

P10

70

69

70

71

72

73

74

75

61

59

68

57

56

55

54

53

9

10

11

12

P26

P25

P11

(MQP-48C-P01)

• Pin assignment on package top

Pin no.

49

Pin name

V^PP

Pin no.

57

Pin name

Pin no.

Pin name

Pin no.

73

Pin name

OE

N.C.

A2

65

66

67

68

69

70

71

72

O4

O5

50

A12

A7

58

74

N.C.

A11

A9

51

59

A1

O6

75

52

A6

60

A0

O7

76

53

A5

61

O1

O2

O3

V^SS

O8

77

A8

54

A4

62

CE

A10

N.C.

78

A13

A14

VCC

55

A3

63

79

56

N.C.

64

80

N.C. : Internally connected. Do not use.

8

MB89130/130A Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

SH-DIP^*1

QFP^*2

35

36

38

39

33

34

5

6

8

9

3

4

X0

X1

A

B

C

Main clock crystal oscillator pins (max. 4.2 MHz)

Subclock crystal oscillator pins (32.768 kHz)

X0A

X1A

MOD0

MOD1

Operation mode selecting pins

Connect directly to V^SS.

Reset I/O pin

This pin is of N-ch open-drain output type with pull-up re-

sistor, and a hysteresis input type. The internal circuit is

initialized by the input of “L”. “L” is output from this pin by

an internal reset source as a option.

32

2

RST

D

I

General-purpose I/O ports

On the MB89130A series, these ports also serve as an ex-

ternal interrupt input.

P00 (INT20)

to

P07 (INT27)

16 to 9

34 to 27

External interrupt inputs are of hysteresis input type.

8 to 2, 48 26 to 20, 18

P10 to P17

P20 to P27

E

General-purpose I/O ports

47 to 40

17 to 10

G

General-purpose output ports

General-purpose I/O port

24

42

P30/SCK

P31/SO

P32/SI

F

Also serves as the clock I/O for the 8-bit serial I/O. This

port is of hysteresis input type.

General-purpose I/O port

Also serves as a 8-bit serial I/O data output. This port is of

hysteresis input type.

23

22

41

40

General-purpose I/O port

Also serves as a 8-bit serial I/O data input. This port is of

hysteresis input type.

General-purpose I/O port

Also serves as the external clock input for the 8-bit

timer/counter. This port is of hysteresis input type. The

system clock output is provided as an option.

21

20

39

38

P33/EC/SCO

P34/TO/INT0

F

General-purpose I/O port

Also serve as the overflow output for the 8-bit timer/

counter and an external interrupt input. This port is of hys-

teresis input type.

F

General-purpose I/O ports

Also serves as an external interrupt input. These ports are

of hysteresis input type.

19,

18

37,

36

P35/INT1,

P36/INT2

*1 : DIP-48P-M01

*2 : FPT-48P-M13

(Continued)

9

MB89130/130A Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

General-purpose I/O port

SH-DIP^*1

QFP^*2

Also serves as a buzzer output. This port is of hysteresis

input type. On the MB89130A series, this port also serves

as a remote control output.

17

35

P37/BZ/(RCO)

F

P40/AN0 to

P43/AN3

N-ch open-drain output ports

Also serve as an analog input for the A/D converter.

30 to 27

48 to 45

H

37

1

7

V^CC

Power supply pin

19

VSS

Power supply (GND) pin

A/D converter power supply pin

Use this pin at the same voltage as VCC.

31

26

25

1

AV^CC

AVR

AVSS

44

43

A/D converter reference voltage input pin

A/D converter power supply pin

Use this pin at the same voltage as VSS.

*1 : DIP-48P-M01

*2 : FPT-48P-M13

10

MB89130/130A Series

• External EPROM pins (MB89PV130A only)

Pin no.

Pin name

I/O

Function

49

V^PP

O

“H” level output pin

50

51

52

53

54

55

58

59

60

A12

A7

A6

A5

A4

A3

A2

A1

A0

O

Address output pins

61

62

63

O1

O2

O3

I

Data input pins

64

V^SS

O

Power supply (GND) pin

65

66

67

68

69

O4

O5

O6

O7

O8

I

Data input pins

ROM chip enable pin

Outputs “H” during standby.

70

71

73

CE

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

75

76

77

78

79

A11

A9

A8

A13

A14

O

Address output pins

80

V^CC

EPROM power supply pin

56

57

72

74

Internally connected pins

Be sure to leave them open.

N.C.

11

MB89130/130A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Crystal or ceramic oscillation type (main clock)

Circuit for the MB89P133A/P131/P135A/PV130A

ExternalclockinputselectingversionsofMB89131/

133A/135A

X1

X0

Oscillation feedback resistor of approximately

1 MΩ/5 V

Standby control signal

A

• Crystal or ceramic oscillation type (main clock)

Crystal or ceramic oscillation selecting versions of

MB89131/133A/135A

Oscillation feedback resistor of approximately

1 MΩ/5 V

X1

X0

Standby control signal

• Crystal and ceramic oscillation type (subclock)

Circuit for the MB89131/133A/135A

Oscillation feedback resistor of approximately

4.5 MΩ/5 V

X1A

X0A

Standby control signal

X1A

B

• Crystal and ceramic oscillation type (subclock)

Circuit for the MB89P131/P133A/P135A/PV130A

Oscillation feedback resistor of approximately

4.5 MΩ/5 V

X0A

Standby control signal

C

D

• Output pull-up resistor (P-ch) of approximately

50 kΩ/5 V

• Hysteresis input

R

P-ch

N-ch

(Continued)

12

MB89130/130A Series

(Continued)

Type

Circuit

Remarks

• CMOS output

R

• CMOS input

P-ch

N-ch

E

• Pull-up resistor optional

• CMOS output

R

• Hysteresis input

P-ch

N-ch

F

• Pull-up resistor optional

• CMOS output

P-ch

N-ch

G

• N-ch open-drain output

• Analog input

R

P-ch

H

N-ch

• Pull-up resistor optional

Analog input

• CMOS output

• CMOS input

P-ch

• The interrupt input is a hysteresis input (available

only for the MB89130A series) .

P-ch

N-ch

I

Interrupt input

Only for MB89130A series

• Pull-up resistor optional

13

MB89130/130A Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D Converter

Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although operation is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the

voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC

is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctu-

ations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz)

and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when

power is switched.

6. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

wake-up from stop mode.

7. Turning on the supply voltage (only for the MB89P135A)

Power on sharply up to the option enabling voltage (2 V) within 13 clock cycles after starting of oscillation.

14

MB89130/130A Series

■ PROGRAMMING TO THE EPROM ON THE MB89P131

The MB89P131 is an OTPROM version of the MB89131.

1. Features

• 4-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

EPROM mode

(Corresponding addresses on the EPROM programmer)

Address

0000H

Single chip

I/O

0080H

00C0H

Not available

RAM

0140H

0000H

Not available

7000H

F000H

PROM

4 KB

EPROM

32 KB

FFFFH

7FFFH

3. Programming to the EPROM

In EPROM mode, the MB89P131 functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 7000^Hto 7FFFH (note that addresses F000H to FFFFH

while operating as a single chip correspond to 7000H to 7FFFH in EPROM mode) .

(3) Program with the EPROM programmer.

15

MB89130/130A Series

■ PROGRAMMING TO THE EPROM ON THE MB89P133A

The MB89P133A is an OTPROM version of the MP89133A.

1. Features

• 8-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

Address

0000H

Single chip

I/O

EPROM mode

(Corresponding addresses on the EPROM programmer)

0080H

0180H

RAM

0000H

Not available

E000H

FFFFH

6000H

PROM

8 KB

EPROM

32 KB

7FFFH

3. Programming to the EPROM

In EPROM mode, the MB89P133A functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 6000^Hto 7FFFH (note that addresses E000H to FFFFH

while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode) .

(3) Program with the EPROM programmer.

16

MB89130/130A Series

■ PROGRAMMING TO THE EPROM ON THE MB89P135A

The MB89P135A is an OTPROM version of the MB89133A/135A.

1. Features

• 16-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

Address

0000H

Single chip

I/O

EPROM mode

(Corresponding addresses on the EPROM programmer)

0080H

0280H

RAM

Not available

8000H

0000H

Vacancy

(Read value FFH)

BFF0H

BFF6H

3FF0H

Option area

3FF6H

Not available

Vacancy

(Read value FF^H)

C000H

4000H

PROM

16 KB

EPROM

16 KB

7FFFH

FFFFH

3. Programming to the EPROM

In EPROM mode, the MB89P135A functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 4000^Hto 7FFFH (note that addresses C000H to FFFFH

while operating as a single chip correspond to 4000H to 7FFFH in EPROM mode) .

(3) Load option data into the EPROM programmer at 3FF0H to 3FF6H.

(4) Program with the EPROM programmer.

17

MB89130/130A Series

4. Setting OTPROM Options (MB89P135A Only)

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map :

• OTPROM option bit map

Ad-

dress

Bit 7

Bit 6

Bit 5

Bit 4

Clock

Bit 3

Bit 2

Bit 1

Bit 0

Oscillation

Vacancy

mode

selection

stabilization time

Reset pin

output

1 : Yes

0 : No

Power-on

reset

1 : Yes

0 : No

3FF0^HReadable Readable Readable 1 : Single

00 : 2²/FCH 10 : 2¹⁶/FCH

01 : 2¹²/FCH 11 : 2¹⁸/FCH

and

writable

and

writable

and

writable

clock

0 : Dual

clock

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1 : Yes

0 : No

Pul-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

3FF1H

3FF2^H

3FF3^H

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1 : No

0 : Yes

Pull-up

1 : No

0 : Yes

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Pull-up

1 : Yes

0 : No

Vacancy

3FF4^HReadable Readable Readable Readable Readable Readable Readable Readable

and

writable

Vacancy

3FF5^HReadable Readable Readable Readable Readable Readable Readable Readable

and

writable

Vacancy

3FF6^HReadable Readable Readable Readable Readable Readable Readable Readable

and

writable

Note : Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is selected.

18

MB89130/130A Series

■ HANDLING THE MB89P131/P133A/P135A

1. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure.

Program, verify

Aging

+150 °C, 48 h

Data verification

Assembly

2. Programming Yield

Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test.

For this reason, a programming yield of 100% cannot be assured at all times.

3. EPROM Programmer Socket Adapter

Recommended programmer manufacturer

and programmer name

Minato Electronics Inc.

1890A

Compatible socket adapter

Sun Hayato Co., Ltd.

Part no.

Package

MB89P131PF

MB89P133APFM

MB89P133AP

Recommended

QFP-48

ROM-48QF2-28DP-8L

ROM-48SD-28DP-8L2

SH-DIP-48

Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403

FAX (81) -3-5396-9106

Minato Electronics Inc. : TEL : USA (1) -916-348-6066

JAPAN (81) -45-591-5611

19

MB89130/130A Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato

Co., Ltd.) listed below :

Package

Socket adapter part number

LCC-32 (Square)

ROM-32LC-28DP-S

Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403

FAX (81) -3-5396-9106

3. Memory Space

Memory space in each mode, such as 32-Kbyte PROM is diagrammed below.

Address

0000H

Single chip

Corresponding addresses on the EPROM programmer

I/O

0080H

0480H

RAM

Not available

8000H

0000H

PROM

32 KB

EPROM

32 KB

7FFFH

FFFFH

4. Programming to the EPROM

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH.

(3) Program with the EPROM programmer.

20

MB89130/130A Series

■ BLOCK DIAGRAM

X0

X1

Timebase timer

Reset circuit

Main clock oscillator

Clock controller

RST

(WDT)

X0A

X1A

Subclock oscillator

(32.768 kHz)

8-bit timer/counter

P34/TO/INT0

P33/EC/SCO

8

CMOS I/O port

P00/ (INT20)

to P07/ (INT27)

*

External interrupt 2

(wake-up function)

P30/SCK

P32/SI

P31/SO

8

8-bit serial I/O

P10 to P17

P35/INT1

P36/INT2

External interrupt 1

8

Remote control*

transmitting

frequency generator

P20 to P27

Buzzer output

CMOS output port

P37/BZ/(RCO)

CMOS I/O port

N-ch open-drain output port

RAM

4

P40/AN0

to P43/AN3

8-bit A/D converter

F²MC-8L

CPU

AVR

ROM

AVCC

AVSS

The other pins

MOD0, MOD1, VCC, VSS

* : Only for the MB89130A series.

Note : Parenthesized pin function is only for the MB89130A series.

21

MB89130/130A Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89130/130A series offer a memory space of 64 Kbytes for storing all of I/O, data,

and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately

abovetheI/Oarea. Thedataareacanbedividedintoregister, stack, anddirectareasaccordingtotheapplication.

The program area is allocated from exactly the opposite end, that is, near the highest address. The tables of

interrupt reset vectors and vector call instructions are allocated from the highest address within the program

area. The memory space of the MB89130/130A series is structured as illustrated below.

• Memory Space

MB89P133A

MB89133A

MB89P131

MB89131

MB89135A

I/O

MB89P135A

I/O

MB89PV130A

I/O

0000H

I/O

007FH

0080H

007FH

0080H

007FH

0080H

007FH

0080H

007FH

00C0H

Vacancy

RAM

256 B

RAM

256 B

RAM

512 B

RAM

1 KB

RAM

128 B

00FFH

0100H

00FFH

0100H

00FFH

0100H

00FFH

0100H

Register

013FH

0140H

017FH

0180H

017FH

0180H

01FFH

0200H

01FFH

0200H

027FH

0280H

Vacancy

047FH

0480H

Vacancy

7FFFH

8000H

BFFFH

C000H

BFFFH

C000H

External

ROM

32 KB

DFFFH

E000H

ROM

16 KB

ROM

16 KB

EFFFH

F000H

ROM

8 KB

ROM

4 KB

FFFFH

22

MB89130/130A Series

2. Registers

The F²MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose

memory registers. The following registers are provided :

Program counter (PC) :

A 16-bit register for indicating the instruction storage positions.

Accumulator (A) :

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T) : A 16-bit register which is used for arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is

used.

Index register (IX) :

Extra pointer (EP) :

Stack pointer (SP) :

Program status (PS) :

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit pointer for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

PC

Initial value

FFFDH

: Program counter

: Accumulator

A

T

Indeterminate

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

The other bit values are Indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR) . (See the diagram below.)

• Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

23

MB89130/130A Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

• Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and

bits for control of CPU operations at the time of an interrupt.

H-flag : Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag : Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’.

Cleared to ‘0’ at the reset.

IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level

is higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag : Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.

Z-flag : Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise.

V-flag : Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag : Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise.

Set to the shift-out value in the case of a shift instruction.

24

MB89130/130A Series

The following general-purpose registers are provided :

General-purpose registers : An 8-bit resister for storing data

The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains

eight registers. Up to a total of 8 banks can be used on the MB89131/P131 and a total of 16 banks can be used

on the MB89133A/P133A/135A and a total of 32 banks can be used on the MB89P135A/PV130A. The bank

currently in use is indicated by the register bank pointer (RP) .

• Register Bank Configuration

This address = 0100H + 8 × (RP)

R0

R1

R2

R3

R4

R5

R6

R7

8 banks (MB89131/P131)

16 banks (MB89133A/P133A/135A)

32 banks (MB89P135A/PV130A)

Memory area

25

MB89130/130A Series

■ I/O MAP

Address

00^H

01^H

02H

03^H

04^H

05H

06^H

07^H

08H

09^H

0AH

0B^H

0CH

0DH

0E^H

0FH

10^H

11H

12H

13^H

14H

15H

16^H

17H

18H

19H

1A^H

1BH

1CH

1D^H

1EH

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

PDR2

Vacancy

(R/W)

(W)

SYCC

STBC

WDTC

TBTC

WPCR

PDR3

DDR3

PDR4

BZCR

System clock control register

Standby control register

Watchdog timer control register

Timebase timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Port 4 data register

Buzzer register

(R/W)

Vacancy

(R/W)

SCGC

Peripheral control clock register

Vacancy

(R/W)

RCR1

RCR2

Remote control transmitting control register 1*

Remote control transmitting control register 2*

Vacancy

(R/W)

T2CR

T1CR

T2DR

T1DR

SMR

Timer 2 control register

Timer 1 control register

Timer 2 data register

Timer 1 data register

Serial mode register

Serial data register

SDR

Vacancy

(Continued)

26

MB89130/130A Series

(Continued)

Address

Read/write

(R/W)

Register name

ADC1

Register description

A/D converter control register 1

A/D converter control register 2

A/D converter data register

External interrupt 1 control register 1

External interrupt 1 control register 2

Vacancy

20^H

21^H

(R/W)

ADC2

22^H

(R/W)

ADCD

23H

(R/W)

EIC1

24^H

(R/W)

EIC2

25^H

26H to 31H

32^H

Vacancy

(R/W)

EIE2

EIF2

External interrupt 2 enable register*

External interrupt 2 flag register*

Vacancy

33^H

34H to 7BH

7CH

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7DH

7E^H

7FH

* : Only for the MB89130A series

Note : Do not use vacancies.

27

MB89130/130A Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

AVCC

VSS − 0.3 VSS + 7.2

VSS − 0.6 VSS + 13.0

V

*

Power supply voltage

Program voltage

AVR

V^PP

AVR must not exceed VCC + 0.3 V

Only for the MB89P131/P133A/

P135A

Input voltage

V^I

VO

I^OL

VSS − 0.3 VCC + 0.3

10

V

Output voltage

“L” level maximum output current

mA

Average value (operating current ×

operating rate)

“L” level average output current

I^OLAV

4

mA

“L” level total maximum output cur-

rent

ΣI^OL

100

“L” level total average output cur-

rent

Average value (operating current ×

operating rate)

ΣIOLAV

IOH

20

–10

–2

mA

“H” level maximum output current

Average value (operating current ×

operating rate)

“H” level average output current

I^OHAV

“H” level total maximum output cur-

rent

ΣIOH

–30

mA

“H” level total average output cur-

rent

Average value (operating current ×

operating rate)

ΣI^OHAV

–10

200

Power consumption

Operating temperature

Storage temperature

PD

TA

mW

°C

−40

−55

+85

Tstg

+150

°C

* : Use AV^CCand VCC set to the same voltage.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

28

MB89130/130A Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation assurance range*

MB89131/133A/135A

2.2*

2.7*

6.0*

V

V^CC

AVCC

Normal operation assurance range*

MB89P131/P133A/135A/PV130A

6.0*

Power supply voltage

Operating temperature

1.5

2.0

−40

6.0

AV^CC

+85

V

Retains the RAM state in the stop mode

AVR

T^A

V

°C

* : These values vary with the operating frequencies and the analog assurance range. See Figure 1 and 2, and

“5. A/D Converter Electrical Characteristics.”

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

(MB89P131/P133A/P135A/PV130A, and single-clock MB89131/133/133A/135/135A)

6

5

Operation assurance range

4

3

2

1

2

3

4

Main clock oprating frequency (at an instruction cycle of 4/FCH) (MHz)

4.0

2.0

1.0

Minimum execution time (Instruction cycle) (µs)

Note : The shaded area is assured only for the MB89131/133/133A/135/135A.

29

MB89130/130A Series

Figure 2 Operating Voltage vs. Main Clock Operating Frequency

(Dual-clock MB89131/133/133A/135/135A)

6

5

4

Operation assurance range

3

2

1

2

3

4

Main clock oprating frequency (at an instruction cycle of 4/FCH) (MHz)

4.0

2.0

1.0

Minimum execution time (Instruction cycle) (µs)

Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/F^CH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the oper-

ating speed is switched using a gear.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

30

MB89130/130A Series

3. DC Characteristics

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Sym-

Parameter

bol

Condition

Unit

Remarks

Min.

Typ.

Max.

P00 to P07,

P10 to P17

VCC +

0.3

V^IH

0.7 VCC

V

INT20 to INT27

are available

only for the

MB89130A se-

ries.

“H” level

input voltage

RST,

P30 to P37,

INT20 to

INT27

VCC +

3.0

VIHS

0.8 VCC

V

P00 to P07,

P10 to P17

VSS −

0.3

VIL

0.3 VCC

0.2 VCC

INT20 to INT27

are available

only for the

MB89130A se-

ries.

“L” level

input voltage

RST,

P30 to P37

INT20 to

INT27

VSS −

0.3

V^ILS

Open-drain

output pin

applied

voltage

VCC −

0.3

VCC +

0.3

VD

P40 to P43

V

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37

“H” level

V^OH

I^OH= −2.0 mA

2.4

output voltage

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P43

V^OL

I^OL= 1.8 mA

IOL = 4.0 mA

0.4

0.6

V

“L” level

output voltage

V^OL2

RST

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P43,

MOD0, MOD1

Input leakage

current

(Hi-z output

leakage current)

Without pull-up

resistor

I^LI1

0.0 V < V^I< VCC

±5

µA

kΩ

P00 to P07,

P10 to P17,

R^PULLP30 to P37,

P40 to P43,

RST

Pull-up

resistance

VI = 0.0 V

25

50

100

(Continued)

31

MB89130/130A Series

(Continued)

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

MB89131/

Min.

Typ.

Max.

4

7

mA

F^CH= 4.00 MHz

VCC = 5.0 V

133A/135A

ICC1

MB89P131/

P133A/P135A

*2

tinst = 1.0 µs

6

10

FCH = 4.00 MHz

VCC = 5.0 V

tinst^*2= 1.0 µs

Main clock sleep

mode

I^CCS1

2

5

mA

MB89131/

133A/135A

50

1

100

3

µA

FCL = 32.768 kHz

VCC = 3.0 V

Subclock mode

I^CCL

MB89P131/

P133A/P135A

mA

VCC (External

clock opera-

tion)

FCL = 32.768 kHz

VCC = 3.0 V

Subclock sleep

mode

I^CCLS

25

50

15

µA

FCL = 32.768 kHz

VCC = 3.0 V

• Watch mode

• Main clock stop

mode in dual-

clock system

Power supply

current^*1

I^CCT

TA = +25 °C

• Subclock stop

mode

• Main clock stop

mode in single-

clock system

I^CCH

1

µA

FCH = 4 MHz,

when A/D

conversion is op-

erating

I^A

AVCC

1

3

1

mA

FCH = 4 MHz,

TA = +25 °C,

when A/D

I^AH

µA

conversion is not

operating

Other than

AVCC, AVSS,

VCC, and VSS

Input

capacitance

C^IN

f = 1 MHz

10

pF

*1 : The power supply current is measured at the external clock.

*2 : For information on t^inst, see “ (4) Instruction Cycle” in “4. AC Characteristics.”

32

MB89130/130A Series

4. AC Characteristics

(1) Reset Timing

(V^CC= +5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

48 tHCYL*

ns

* : t^HCYLis the oscillation cycle (1/FCH) to input to the X0 pin.

tZLZH

0.8 VCC

0.2 VCC

RST

0.2 VCC

(2) Power-on Reset

(AV^SS= VSS = 0.0 V, TA = −40 °C to +85 °C)

Unit Remarks

Value

Symbol Condition

Parameter

Min.

Max.

Power supply rising time

Power supply cut-off time

t^R

50

ms Power-on reset function only

ms Due to repeated operations

t^OFF

1

Note : Make sure that power supply rises within the oscillation stabilization time selected.

For example, when the main clock is operating at 3 MHz (F^CH) and the oscillation stabilization time selecting

option has been set to 2¹²/FCH, the oscillation stabilization time is 1.4 ms. Therefore, the maximum value of

power supply rising time is about 1.4 ms.

Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be

varied in the course of operation, a smooth voltage rise is recommended.

tOFF

tR

2.0 V

VCC

0.2 V

33

MB89130/130A Series

(3) Clock Timing

(V^SS= 0.0 V, TA = −40 °C to +85 °C)

Value

Typ.

Symbol

Unit

Remarks

Parameter

Input clock frequency

Clock cycle time

Min.

Max.

F^CH

F^CL

X0, X1

X0A, X1A

X0, X1

1

4.2

MHz Main clock

kHz Subclock

ns Main clock

µs Subclock

32.768

30.5

tHCYL

tLCYL

238

30

1000

24

X0A, X1A

P^WH1

PWL1

Input clock pulse width

X0

ns External clock

t^CR1

tCF1

Input clock rising/falling time

• X0 and X1 Timing and Conditions of Applied Voltage

tHCYL

PWH1

PWL1

tCF1

tCR1

0.8 VCC

0.2 VCC

0.8 VCC

X0

0.2 VCC

• Main Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0 X1

X0

X1

FCH

C1

Open

C0

FCH

34

MB89130/130A Series

• X0A and X1A Timing and Conditions of Applied Voltage

tLCYL

0.8 VCC

X0A

• Subclock Conditions

When a crystal

or

When a single-clock option is used

ceramic resonator is used

X0A X1A

X0A

X1A

Open

Rd

FCL

C1

C0

(4) Instruction Cycle

Parameter

Symbol

Value

Unit

Remarks

(4/FCH) tinst = 1.0 µs when operating at

FCH = 4 MHz

4/FCH, 8/FCH, 16/FCH, 64/FCH

2/FCL

µs

Instruction cycle

(minimum execution time)

t^inst

tinst = 61.036 µs when operating at

FCL = 32.768 kHz

µs

35

MB89130/130A Series

(5) Recommended Resonator Manufacturers

• Sample Application of Piezoelectric Resonator (FAR Family) for Main Clock Oscillation Circuit

X0

X1

R

1

2

C1

C2

Temperature

characteristics of

FAR frequency

Initial deviation of

FAR frequency

(T^A= +25 °C)

FAR part number*¹

(built-incapacitortype)

Frequency Dumping

Loading

(MHz)

resistor

capacitors*²

(T^A=−20°Cto+60°C)

1000 Ω

510 Ω

±0.5%

FAR-C4CC-02000-L00

2.00

3.00

FAR-C4 C-02000- 20

FAR-C4 A-03000- 20

FAR-C4 A-04000- 01

FAR-C4 A-04000- 21

FAR-C4CB-04000-M00

FAR-C4 B-04000- 00

FAR-C4 B-04194- 00

1 kΩ

750 Ω

Built-in

4.00

4.194

Inquiry : FUJITSU MEDIA DEVICES LIMITED

36

MB89130/130A Series

• Sample Application of Ceramic Resonator for Main Clock Oscillation Circuit

X0

X1

R

C1

C2

• Mask ROM products

Resonator

manufacturer*

Resonator

KBR-4.0MKS

Frequency (MHz)

C1 (pF)

C2 (pF)

R

Kyocera Corporation

4.00

1.00

33

Not required

33 (Built-in) 33(Built-in) 1.5 kΩ

Matsushita Electronic

Components Co,. Ltd.

EFOV4004B

CSBF1000J

100

30

100

30

6.8 kΩ

CSA4.00MG

CST4.00MGW

CSA4.00MGU

Not required

Built-in

30

Built-in

30

Murata Mfg. Co., Ltd. CST4.00MGWU

Built-in

100

Built-in

100

4.00

CSA4.00MGU040

CST4.00MGWU040

CSTCS4.00MG

Built-in

CSTCS4.00MGWOC5

CCR4.0MC3

TDK Corporation

(Continued)

37

MB89130/130A Series

(Continued)

• One-time PROM products

Resonator

Frequency (MHz) C1 (pF)

C2 (pF)

R

manufacturer*

CSA3.00MG040

CST3.00MGW040

CSA4.00MG

100

Built-in

30

Not required

3.00

Built-in

30

CSA4.00MGU

Murata Mfg. Co., Ltd.

30

CST4.00MGWU

Built-in

100

4.00

100

CSA4.00MGU040

CST4.00MGWU040

CSTCS4.00MG

Built-in

Inquiry : Kyocera Corporation

• AVX Corporation

North American Sales Headquarters : TEL 1-803-448-9411

• AVX Limited

European Sales Headquarters : TEL 44-1252-770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters : TEL 852-363-3303

Matsushita Electronic Components Co., Ltd.

• North America

Panasonic Industrial Co. : TEL 1-201-348-7000

• Canada

Matsushita Electric of Canada Ltd. : TEL 905-238-2436

• Europe

Panasonic Industrial Europe (Continental) : TEL 49-40-8549-2048

Panasonic Industrial Europe (Nlederlassung Munchen) : TEL 49-89-4800-7150

• Asia

Panasonic Industry of Asia, Company : TEL 65-299-8400

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc. : TEL 1-404-436-1300

• Murata Europe Management GmbH : TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd. : TEL 65-758-4233

TDK Corporation

• TDK Corporation of America

Chicago Regional Office : TEL 1-708-803-6100

• TDK Electronics Europe GmbH

Components Division : TEL 49-2102-9450

• TDK Singapore (PTE) Ltd. : TEL 65-273-5022

• TDK Hongkong Co., Ltd. : TEL 852-736-2238

• Korea Branch, TDK Corporation : TEL 82-2-554-6633

38

MB89130/130A Series

• Sample Application of Crystal Resonator for Subclock Oscillation Circuit

X0A

X1A

Rd

C1

C2

• Mask ROM products

Resonator manufacturer*

SII

Resonator

Frequency (kHz)

C1 (pF)

C2 (pF)

Rd (kΩ)

DS-VT-200

32.768

24

680

Inquiry : SII

• Seiko Instruments Inc. (Japan) : TEL 81-43-211-1219

• Seiko Instruments U.S.A. Inc. : TEL 310-517-7770

• Seiko Instruments GmbH : TEL 49-6102-297-122

(6) Serial I/O Timing

Parameter

(V^CC= +5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Condition

Unit

Remarks

Min.

2 tinst*

−200

200

Max.

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

tSLOV

tIVSH

tSHIX

tSHSL

tSLSH

tSLOV

tIVSH

tSHIX

SCK

µs

ns

µs

ns

SCK, SO

SI, SCK

SCK, SI

200

Internal shift

clock mode

Valid SI → SCK ↑

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

200

1 t^inst*

1 tinst*

0

SCK

External shift

clock mode

SCK, SO

SI, SCK

SCK, SI

200

Valid SI → SCK ↑

200

SCK ↑ → valid SI hold time

200

* : For information on t^inst, see “ (4) Instruction Cycle.”

39

MB89130/130A Series

• Internal Shift Clock Mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SI

• External Shift Clock Mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

40

MB89130/130A Series

(7) Peripheral Input Timing

Parameter

(V^CC= +5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Condition

Unit Remarks

Min.

2 t^inst*

2 tinst*

Max.

Peripheral input “H” level pulse width 1

Peripheral input “L” level pulse width 1

t^ILIH1

t^IHIL1

µs

EC,

INT0 to INT2

* : For information on t^inst, see “ (4) Instruction Cycle.”

tIHIL1

tILIH1

0.8 VCC

0.2 VCC

EC,

INT0 to INT2

0.2 VCC

41

MB89130/130A Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to +6.0 V, FCH = 3 MHz, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Typ.

Re-

marks

Parameter

Resolution

Symbol Pin

Condition

Unit

Min.

Max.

8

AVR = AV^CC= 5.0 V

bit

Total error

±1.5

±1.0

LSB

Linearity error

Differential

linearity error

±0.9

LSB

mV

LSB

µs

Zero transition

voltage

AVSS −

AVSS +

AVR = AV^CC

V^OT

1.0 LSB 0.5 LSB 2.0 LSB

1LSB =

AVR/256

—

Full-scaletransition

voltage

AVR −

3.0 LSB 1.5 LSB

AVR −

V^FST

AVR

0.5

Interchannel

disparity

A/D mode

conversion time

44 t^inst*

Sense mode

conversion time

12 tinst*

µs

Analog port input

current

I^AIN

10

µA

AN0

to

AN3

Analog input

voltage

0

AVR

AV^CC

V

Reference voltage

2.0

AVR = AVCC = 5.0 V,

I^R

when A/D conversion

AVR is operating

100

300

1

µA

Reference voltage

supply current

AVR = AVCC = 5.0 V,

when A/D conversion

is not operating

I^RH

* : For information on t^inst, see “ (4) Instruction Cycle” in “4. AC Characteristics.”

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable by the A/D converter.

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit : LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit : LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

42

MB89130/130A Series

• Total error (unit : LSB)

The difference between theoretical and actual conversion values

Digital output

Theoretical conversion value

1111 1111

Actual conversion value

1111 1110

AVR

256

1 LSB =

(1 LSB × N + VOT)

VNT − (1 LSB × N + VOT)

Linearity error =

1 LSB

V(N+1)T − VNT

− 1

Differential linearity error =

Total error =

1 LSB

Linearity error

VNT − (1 LSB × N + 1 LSB)

1 LSB

0000 0010

0000 0001

0000 0000

VOT

VNT V(N+1)T

VFST Analog input

43

MB89130/130A Series

7. Notes on Using A/D Converter

• lnput impedance of the analog input pins

The A/D converter used for the MB89130/130A series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ) .

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.

0.1 µF for the analog input pin.

• Analog Input Equivalent Circuit

Sample hold circuit

.

C = 28 pF

.

Analog input pin

Comparator

.

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

R = 9 kΩ

.

Close for 8 instruction cycles after starting

A/D conversion.

Analog channel selector

• Error

The smaller the | AVR − AV^SS|, the greater the error would become relatively.

44

MB89130/130A Series

■ EXAMPLE CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

VOL vs. IOL

VOL (V)

VCC – VOH vs. IOH

VCC – VOH (V)

VCC = 2.2 V

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VCC = 2.5 V

TA = +25 °C

VCC = 3.0 V

VCC = 4.0 V

VCC = 3.0 V

VCC = 5.0 V

VCC = 6.0 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

TA = +25 °C

10

IOL (mA)

0

1

2

3

4

5

6

7

8

9

0.0

−0.5 −1.0 −1.5 −2.0 −2.5

−3.0

IOH (mA)

(3) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(4) “H” Level Input Voltage/“L” Level Input

Voltage (Hysteresis Input)

VIN vs. VCC

V^IN(V)

VIN vs. VCC

V^IN(V)

5.0

4.5

4.0

4.5

TA = +25 °C

4.0

VIHS

3.5

3.0

2.5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2.0

VILS

1.5

1.0

0.5

0

1

2

3

4

5

6

7

V^CC(V)

0

1

2

3

4

5

6

7

V^CC(V)

V^IHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

VILS : Threshold when input voltage in hysteresis

characteristics is set to “L” level

(5) Pull-up Resistance

RPULL vs. VCC

RPULL (kΩ)

1000

TA = +25 °C

300

100

50

10

0

1

2

3

4

5

6

7

VCC (V)

45

MB89130/130A Series

(6) Power Supply Current (External Clock)

ICC1 vs. VCC

ICCS1 vs. VCC

ICC (mA)

5.0

ICCS1 (mA)

3

Divide by 4(ICC1)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

FCH = 4.0 MHz

TA = +25 °C

FCH = 4.0 MHz

TA = +25 °C

Divide by 4(ICCS1)

Divide by 64

2.5

2

1.5

1

Divide by 64

1.0

0.5

0.0

0.5

0.0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

ICCLS vs. VCC

ICCL vs. VCC

ICCL (µA)

ICCLS (µA)

200

50

TA = +25 °C

45

40

35

30

25

20

15

180

160

140

120

100

80

60

40

10

5

20

0

1.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

ICCT vs. VCC

IR vs. AVR

IR (µA)

ICCT (µA)

200

30

TA = +25 °C

180

160

25

20

15

10

5

140

120

100

80

60

40

20

0

1.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

AVR (V)

(Continued)

46

MB89130/130A Series

(Continued)

ICCH vs. VCC

IA vs. AVCC

IA (mA)

5.0

ICCH (µA)

2.0

1.8

1.6

TA = +25 °C

FCH = 4 MHz

TA = +25 °C

4.5

4.0

3.5

3.0

1.4

1.2

2.5

2.0

1.0

0.8

1.5

1.0

0.6

0.4

0.5

0

0.2

0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

VCC (V)

AVCC (V)

47

MB89130/130A Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

AH

AL

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

Lower 8 bits of accumulator A (8 bits)

T

TH

TL

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

IX

EP

PC

SP

PS

dr

CCR

RP

Ri

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

( × )

(( × ))

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~:

#:

The number of instructions

The number of bytes

Operation: Operation of an instruction

TL, TH, AH:

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

48

MB89130/130A Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

–

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

AL

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

–

F0

Note: During byte transfer to A, T ← A is restricted to low bytes.

Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

49

MB89130/130A Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

(A) − (Ri)

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

50

MB89130/130A Series

(Continued)

Mnemonic

~

#

Operation

(A) ← (AL) ( (EP) )

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

51

MB89130/130A Series

■ INSTRUCTION MAP

52

MB89130/130A Series

■ MASK OPTIONS

MB89133A

MB89135A

MB89P131

MB89P133A

Part number

Specifying procedure

MB89131

No.

Specify when

ordering masking ordering masking

Specify when

ordering masking

Selectable by pin Selectable by pin

Selectable by pin

(P40 to P43 must be (P40 to P43 must be (P40 to P43 must be

fixed to no pull-up fixed to no pull-up fixed to no pull-up

resistor option when resistor option when resistor option when

an A/D converter is an A/D converter is an A/D converter is

Pull-up resistors

1

2

•P00 to P07, P10 to P17,

•P30 to P37, P40 to P43

used.)

Power-on reset

•Power-on reset provided

•No power-on reset

Selectable

Selection of oscillation stabilization

time

•The oscillation stabilization time ini-

tial value is selectable from 4 types

given below.

3

Selectable

0 : Oscillation stabilization 2²/FCH

1 : Oscillation stabilization 2¹²/FCH

2 : Oscillation stabilization 2¹⁶/FCH

3 : Oscillation stabilization 2¹⁸/FCH

Reset pin output

4

5

6

•Reset output enabled

•Reset output disabled

Selectable

Not required^*1

Clock mode selection

•Single-clock mode

•Dual-clock mode

Selection of oscillation circuit type

•Crystal or ceramic oscillation type Selectable

•External clock input type

Peripheral control clock output func-

tion^*2

7

Selectable

Not required^*3

•Not used

•Used

*1 : Both external clock and oscillation resonator can be used on the OTPROM product.

*2 : “Used” must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output.

*3 : The peripheral control clock output function can be used only by software.

53

MB89130/130A Series

Part number

No.

MB89P135A

MB89PV130A

Specifying procedure

Set with EPROM programmer

Setting not possible

Pull-up resistors

Selectable by pin

(P40 to P43 must be fixed to no

pull-up resistor option.)

All pins fixed to no pull-up resis-

tor option

1

2

•P00 to P07, P10 to P17,

•P30 to P37, P40 to P43

Power-on reset

•Power-on reset provided

•No power-on reset

Selectable

Power-on reset provided

Selection of oscillation stabilization

wait time

•The oscillation stabilization time ini-

tial value is selectable from 4 types

given below.

3

Oscillation stabilization 2¹⁸/FCH

0 : Oscillation stabilization 2²/FCH

1 : Oscillation stabilization 2¹²/FCH

2 : Oscillation stabilization 2¹⁶/FCH

3 : Oscillation stabilization 2¹⁸/FCH

Reset pin output

4

5

6

•Reset output enabled

•Reset output disabled

Selectable

Reset output enabled

Dual-clock mode

Not required^*1

Selection of clock mode selection

•Single-clock mode

•Dual-clock mode

Selection of oscillation circuit type

•Crystal or ceramic oscillation type Not required^*1

•External clock input type

Peripheral control clock output func-

tion^*2

7

Not required^*3

•Not used

•Used

*1 : Both external clock and oscillation resonator can be used.

*2 : “Used” must be selected when P33 (39 pin) is used as SCO for the peripheral control clock output.

*3 : The peripheral control clock output function can be used only by software.

54

MB89130/130A Series

■ MB89P131/P133A STANDARD OPTIONS

No.

1

Product option

Pull-up resistor

MB89P131-101

MB89P133A-201

Not provided for any port

Provided

Not provided for any port

Provided

2

Power-on reset

Selection of oscillation stabiliza-

tion time

3

2 : Oscillation stabilization 2¹⁶/FCH 2 : Oscillation stabilization 2¹⁶/FCH

4

5

Reset pin output

Enabled

Disabled

Selection of clock mode

Dual-clock mode

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89131PFM

MB89133APFM

MB89135APFM

48-pin Plastic QFP

(FPT-48P-M13)

MB89P131PFM-101

MB89P133APFM-201

MB89P135APFM

MB89133AP

MB89P133AP-201

48-pin Plastic SH-DIP

(DIP-48P-M01)

48-pin Ceramic MQFP

(MQP-48C-P01)

MB89PV130ACF-ES

55

MB89130/130A Series

■ PACKAGE DIMENSION

48-pin Plastic QFP

(FPT-48P-M13)

13.10±0.40 SQ

(.516±.016)

2.35(.093)MAX

(Mounting height)

10.00±0.20 SQ

(.394±.008)

0(0)MIN

(STAND OFF)

36

25

Details of "A" part

37

24

0.15(.006)

0.20(.008)

8.80

(.346)

REF

11.50±0.30

(.453±.012)

INDEX

"A"

0.18(.007)MAX

0.53(.021)MAX

48

13

Details of "B" part

1

12

LEAD No.

0.80(.0315)TYP

0.15±0.05

(.006±.002)

0.30±0.10

(.012±.004)

M

0.16(.006)

0~10°

"B"

0.80±0.30

(.031±.012)

0.10(.004)

C

1994 FUJITSU LIMITED F48023S-1C-1

Dimensions in mm (inches)

(Continued)

56

MB89130/130A Series

48-pin Plastic SH-DIP

(DIP-48P-M01)

43.69 ⁺^–0⁰^.^.³²⁰⁰

1.720 ⁺^–.^.⁰⁰¹⁰²⁸

INDEX-1

INDEX-2

13.80±0.25

(.543±.010)

0.51(.020)MIN

5.25(.207)

MAX

0.25±0.05

(.010±.002)

3.00(.118)

MIN

1.00 –⁺0^0.50

.039 ⁺^–0^.020

0.45±0.10

(.018±.004)

15.24(.600)

TYP

15°MAX

1.778±0.18

(.070±.007)

1.778(.070)

MAX

40.894(1.610)REF

C

1994 FUJITSU LIMITED D48002S-3C-3

Dimensions in mm (inches)

(Continued)

57

MB89130/130A Series

(Continued)

48-pin Ceramic MQFP

(MQP-48C-P01)

17.20(.677)TYP

15.00±0.25

(.591±.010)

1.50(.059)TYP

1.00(.040)TYP

8.80(.346)REF

PIN No.1 INDEX

14.82±0.35

(.583±.014)

0.80±0.22

(.0315±.0087)

PIN No.1 INDEX

1.02±0.13

(.040±.005)

10.92 –⁺0⁰.^.0¹³

.430 –⁺0^.005

8.71(.343)

TYP

7.14(.281)

TYP

PAD No.1 INDEX

4.50(.177)TYP

1.10 ⁺^–0⁰^.^.²⁴⁵⁵

.043 ⁺^–.^.⁰⁰¹¹⁰⁸

0.40±0.08

(.016±.003)

0.60(.024)TYP

0.30(.012)TYP

8.50(.335)MAX

0.15±0.05

(.006±.002)

C

1994 FUJITSU LIMITED M48001SC-4-2

Dimensions in mm (inches)

58

MB89130/130A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0008

FUJITSU LIMITED Printed in Japan


型号：	MB89130
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总59页 (文件大小：689K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89130 [FUJITSU]

相关型号：

MB89130A

MB89130_01

MB89131

MB89131PFM

MB89133

MB89133A

MB89133AP

MB89133AP-SH

MB89133APFM

MB89135

MB89135A

MB89135APFM