MB89145V2P-SH [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有
| 型号： | MB89145V2P-SH |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontroller |
| 文件： | 总50页 (文件大小：700K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12522-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89140 Series
MB89145/146 and MB89P147/PV140
■ DESCRIPTION
The MB89140 series is a line of single-chip microcontrollers that use the F2MC*-8L CPU core which can operate
at low voltage but at high speed. The MB89140 series contains a variety of peripheral functions, such as timers,
a serial interface, an A/D converter, and an external interrupt. The MB89140 series is applicable to a wide range
of applications from welfare products to industrial equipment, including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Minimum execution time: 0.5 µs/8-MHz oscillation
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
(Continued)
■ PACKAGE
64-pin Plastic SH-DIP
64-pin Plastic QFP
64-pin Ceramic MDIP
64-pin Ceramic MQFP
(DIP-64P-M01)
(FPT-64P-M06)
(MDP-64C-P02)
(MQP-64C-P01)
MB89140 Series
(Continued)
• Low-voltage operation (when an A/D converter is not used)
• Low current consumption (compatible with dual-clock system)
• High-voltage ports on chip
• Five types of timers
8-bit PWM timer (also usable as a reload timer)
12-bit MPG timer (also usable as a PPG output, PWM output, and reload timer)
8/16-bit timer (also usable as two 8-bit timers)
21-bit time-base timer
• One serial interface
Swichable transfer direction allows communication with various equipment.
• 10-bit A/D converter: 12 channels
Successive approximation type
• External interrupt: 2 channels
Two channels are independent and capable of wake-up from low-power consumption modes. (Rising edge,
falling edge/both edges selectability)
–0.3 V to +7.0 V can be applied to INT1 (N-ch open-drain)
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
Subclock mode
Watch mode
• Reset output and power-on reset selectability
2
MB89140 Series
■ PRODUCT LINEUP
Part number
MB89145
MB89146
MB89P147
MB89PV140
Piggyback/
Parameter
Classification
Mass production products
(mask ROM products)
One-time PROM/
EPROM product
evaluation product
(for evaluation and
development)
ROM size
16 K × 8 bits
(internal mask
ROM)
24 K × 8 bits
(internal mask
ROM)
32 K × 8 bits
(internal PROM)
32 K × 8 bits
(external ROM)
RAM size
512 × 8 bits
768 × 8 bits
1 K × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
Minimum execution time:
Interrupt processing time:
Note:
0.5 µs/8 MHz to 8.0 µs/8 MHz, 61 µs/32.768 kHz
4.5 µs/8 MHz to 72.0 µs/8 MHz, 562.5 µs/32.768 kHz
The above times change according to the gear function.
Ports
High-voltage output port
(P-ch open-drain):
8 (P60 to P67, for heavy current) 16 (P40 to P47, P50 to
P57 for low current)
Buzzer output
(P-ch open-drain, high-voltage): 1 (heavy current)
Output ports (CMOS):
Input ports (CMOS):
4 (P20 to P23)
2 (P70 and P71, function as X0A and XIA pins when
dual-clock system is used.)
I/O ports (CMOS):
I/O ports (N-ch open-drain):
Total:
23 (P00 to P07, P10 to P17, P30, and P32 to P37)
1 (P31)
55
Clock timer
21 bits × 1 (in main clock mode), 15 bits × 1 (at 32.768 kHz)
8-bit PWM timer
(timer 1)
8-bit timer operation
(toggled output capable, operating clock: 1, 2, 8, 16 system clock cycles)
8-bit resolution PWM operation
(conversion cycle: 128 µs to 2.0 ms at 8.0-MHz oscillation, and highest gear speed)
12-bit MPG
(timer 4)
12-bit resolution PWM operation (maximum conversion cycle of 2048.4 µs to 16.4 ms at
8.0 MHz-oscillation, and highest gear speed)
12-bit resolution reload timer operation (toggled output capable)
12-bit resolution PPG operation (minimum resolution of 0.5 µs at 8.0-MHz oscillation, and
highest gear speed)
8/16-bit timer
counter
(timer 2, 3)
8/16-bit timer operation (operating clock, internal clock, external trigger)
8/16-bit event counter operation (Rising edge/falling edge/both edges selectability)
(Continued)
3
MB89140 Series
(Continued)
Part number
MB89145
Parameter
MB89146
MB89P147
MB89PV140
8-bit serial I/O
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles)
10-bit A/D
converter
10-bit resolution × 12 channels
A/D conversion mode (conversion time of 16.5 µs/8 MHz, and highest gear speed)
Sense mode (conversion time of 9.0 µs/8 MHz, and highest gear speed)
External activation capable
External interrupt
2 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge/both edges selectability
Built-in analog noise canceller
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby mode
Process
Sleep mode, stop mode, watch mode, and subclock mode
CMOS
Operating
voltage*
2.7 V to 6.0 V
EPROM for use
MBM27C256A-20TV
MBM27C256A-20CZ
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89145
Package
MB89146
MB89PV140
MB89P147
DIP-64P-M01
DIP-64C-A06
FPT-64P-M06
MDP-64C-P02
MQP-64C-P01
×
×
×
×
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89140 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89P147, the program area starts from address 8007H but on the MB89PV140 starts from 8000H.
(On the MB89P147, addresses 8000H to 8006H comprise the option setting area, option settings can be read
by reading these addresses. On the MB89PV140, addresses 8000H to 8006H could also be used as a program
ROM. However, do not use these addresses in order to maintain compatibility of the MB89P147.)
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV140, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using
options check section “■ Mask Options.”
Take particular care on the following points:
• Options are fixed on the MB89PV140.
• OntheMB89P147, MB89145, andMB89146, thepull-downresistoroptioncaneitherbeselectedforallaffected
pins, or for no pin; it is not possible to specify the pull-down resistor option for individual pins.
4. Subclock Oscillation Feedback Resistor
A built-in oscillation feedback resistor is provided for the subclock oscillator pin on the MB89PV140, but it is not
provided for the MB89145, MB89146, MB89P147. Therefor these products should be connected to an external
oscillation feedback resistor.
5
MB89140 Series
■ PIN ASSIGNMENT
(Top view)
1
2
3
4
5
6
7
8
VCC
AVCC
AVSS
BZ
P67
P66
P65
P64
P63
P62
P61
P60
VFDP
P57
P56
P55
P54
P53
P52
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VCC
A14
A13
A8
A15/VPP
A12
A7
92
91
90
89
88
87
86
85
84
83
82
81
80
79
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
P10/AN8
P11/AN9
P12/ANA
P13/ANB
P14
A6
A5
A4
A3
A2
A1
A0
O1
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
O2
O3
VSS
P15
P16
P51
P50
P47
P46
P45
P44
P43
P42
P41
Each pin inside the dashed line
is for the MB89PV140 only.
P17/ADST
P30/INT0/TRG
P31/INT1
P32/SCK
P33/SO
P34/SI
P35/EC
P36/PWO1
P37/DTT1
P20
P40
P23/WDG
RST
MODA
X0
P21/PWO0
P22
P70/X0A*
P71/X1A*
X1
VSS
(DIP-64P-M01)
(MDP-64C-P02)
*: When dual-clock system is selected.
6
MB89140 Series
(Top view)
P61
P60
VFDP
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P03/AN3
P04/AN4
P05/AN5
P06/AN6
P07/AN7
P10/AN8
P11/AN9
P12/ANA
P13/ANB
P14
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
9
10
11
12
13
14
15
16
17
18
19
P15
P16
P17/ADST
P30/INT0/TRG
P31/INT1
P32/SCK
P33/SO
P34/SI
P35/EC
Each pin inside the dashed line
is for the MB89PV140 only.
(FPT-64P-M06)
(MQP-64C-P01)
*: When dual-clock system is selected.
• Pin assignment on package top (MB89PV140 only)
Pin no.
65
Pin name
N.C.
A15/VPP
A12
Pin no.
73
Pin name
A2
Pin no.
81
Pin name
N.C.
O4
Pin no.
89
Pin name
OE
66
74
A1
82
90
N.C.
A11
A9
67
75
A0
83
O5
91
68
A7
76
N.C.
O1
84
O6
92
69
A6
77
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
A14
VCC
71
A4
79
O3
87
CE
95
72
A3
80
VSS
88
A10
96
N.C.: Internally connected. Do not use.
7
MB89140 Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
SDIP*1
MDIP*2
QFP*3
MQFP*4
30
31
29
23
24
22
X0
X1
A
C
Main clock crystal oscillator pins
MODA
Operating mode selection pin
Connect directly to VSS in normal operation. This pin
functions as the VPP pin in EPROM products.
28
21
RST
D
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up
resistor, and a hysteresis input type.
“L” is output from this pin by an internal reset source
when the option is set. The internal circuit is initialized
by the input of “L”.
This pin is with a noise canceller.
54 to 61
47 to 54 P07/AN7 to
P00/AN0
G
J
General-purpose I/O ports
The input is a hysteresis input type and with a built-in
noise canceller. Although these ports also serve as an
analog input, analog input does not pass through the
hysteresis input noise canceller.
46
39
P17/ADST
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as an A/D converter
external activation.
47 to 49
50 to 53
40 to 42 P16 to P14
J
General-purpose I/O ports
The input is a hysteresis input type and with a built-in
noise canceller.
43 to 46 P13/ANB to
P10/AN8
G
General-purpose I/O ports
The input is a hysteresis input type and with a built-in
noise canceller. Although these ports also serves as an
analog input, analog input does not pass through the
hysteresis input noise canceller.
34,
33
27,
26
P70/X0A,
P71/X1A
B/K
General-purpose I/O ports with a built-in noise
canceller
(single-clock operation)
Function as subclock crystal oscillator pins. (dual-clock
operation)
35
27
28
20
P22
E
E
General-purpose output port
P23/WDG
General-purpose output port
Also serves as a watchdog output.
36
29
30
P21/PWO0
P20
E
E
General-purpose output port
Also serves as the PWM output for the 8-bit PWM timer.
37
General-purpose output port
(Continued)
*1: DIP-64P-M01
*2: MDP-64C-P02
*3: FPT-64P-M06
*4: MQP-64C-P01
8
MB89140 Series
Pin no.
Circuit
type
Pin name
P37/DTTI
Function
SDIP*1
QFP*3
MDIP*2
MQFP*4
38
31
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. When overcurrent is detected, the 12-
bit MPG output can be inactivated by the external edge
input.
39
40
32
33
P36/PWO1
P35/EC
J
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as a 12-bit MPG output.
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the external clock input
for the 8/16-bit timer/counter.
41
42
43
44
34
35
36
37
P34/SI
J
J
J
F
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the serial data input for
the 8-bit serial interface.
P33/SO
P32/SCK
P31/INT1
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the serial data output
for the 8-bit serial interface.
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serves as the serial transfer clock
for the 8-bit serial interface.
General-purpose I/O port
The output is an N-ch open-drain type. The input is a
hysteresis input type and with a built-in noise canceller.
Also serves as an external interrupt. The interrupt
input is also a hysteresis input type and with a built-in
noise canceller.
45
1
38
58
P30/INT0/TRG
J
General-purpose I/O port
The input is a hysteresis input type and with a built-in
noise canceller. Also serve as an external interrupt or
as an MPG trigger input. The interrupt input is also a
hysteresis input type and with a built-in noise canceller.
BZ
I
Buzzer output-only pin
P-ch high-voltage open-drain output port
19 to 26,
11 to 18
12 to 19,
4 to 11
P47 to P40,
P57 to P50
H
Low-current P-ch high-voltage open-drain output ports
Products with and without a built-in pull-down resistor
between these pins and the VFDP pin are provided.
(Continued)
*1: DIP-64P-M01
*2: MDP-64C-P02
*3: FPT-64P-M06
*4: MQP-64C-P01
9
MB89140 Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
SDIP*1
MDIP*2
QFP*3
MQFP*4
2 to 9
59 to 64
1, 2
P67 to P60
H
Heavy-current P-ch high-voltage open-drain output
port
Products with and without a built-in pull-down resistor
between these pins and the VFDP pin are provided.
10
3
VFDP
—
Voltage supply pin for connection to a pull-down
resistor for ports 4, 5, and 6. In products without a
built-in pull-down resistor and in the MB89PV140, this
pin should be left open.
64
32
63
57
25
56
VCC
—
—
—
Power supply pin
VSS
Power supply (GND) pin
AVCC
A/D converter power supply pin
Use this pin at the same voltage as VCC.
62
55
AVSS
—
A/D converter power supply (GND) pin
Use this pin at the same voltage as VSS.
*1: DIP-64P-M01
*2: MDP-64C-P02
*3: FPT-64P-M06
*4: MQP-64C-P01
10
MB89140 Series
• External EPROM pins (MB89PV140 only)
Pin no.
Pin name
I/O
Function
SDIP*3
MDIP*4
QFP*1
MQFP*2
65
66
A15/VPP
O
O
“H” level output pin
Address output pins
66
67
68
69
70
71
72
73
74
67
68
69
70
71
72
73
74
75
A12
A7
A6
A5
A4
A3
A2
A1
A0
75
76
77
77
78
79
O1
O2
O3
I
Data input pins
78
80
VSS
O
I
Power supply (GND) pin
Data input pins
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
84
87
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
86
88
89
A10
OE
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
Address output pins
90
91
92
—
94
95
96
A13
A14
VCC
O
EPROM power supply pin
65
76
81
90
N.C.
—
Internally connected pins
Be sure to leave them open.
*1: DIP-64P-M01
*2: MDP-64C-P02
*3: FPT-64P-M06
*4: MQP-64C-P01
11
MB89140 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Standby control signal
Standby control signal
Remarks
A
• Crystal or ceramic oscillation type (main clock)
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
X1
X0
B
• Crystal or ceramic oscillation type (subclock)
• At an oscillation feedback resistor of approximately
4.5 MΩ/5.0 V
(The built-in feedback resistor is not provided except
on the MB89PV140-102.)
X1A
X0A
C
D
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
R
• CMOS hysteresis input
(with noise canceller)
P-ch
N-ch
Hysteresis input (with noise canceller)
E
F
• CMOS output
P-ch
N-ch
• N-ch open-drain output
• CMOS hysteresis input
(with noise canceller)
N-ch
Hysteresis input (with noise canceller)
(Continued)
12
MB89140 Series
(Continued)
Type
Circuit
Remarks
G
• CMOS output
• CMOS hysteresis input
P-ch
(with noise canceller, except analog input)
N-ch
Port
Hysteresis input (with noise canceller)
Analog input
H
• P-ch high-voltage open-drain output
• Products with and without a built-in pull-down resistor
are provided (except the MB89PV140).
P-ch
VFDP
I
• P-ch high-voltage open-drain output
P-ch
J
• CMOS output
• CMOS hysteresis input
(with noise canceller)
• Pull-up resistor optional
P-ch
N-ch
Port
Hysteresis input (with noise canceller)
K
• CMOS hysteresis input
(with noise canceller)
Port
Hysteresis input (with noise canceller)
13
MB89140 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. (However, up to 7.0 V can be
applied to P31/INT pin, regardless of VCC)
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
4. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
5. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
14
MB89140 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P147
The MB89P147 is an OTPROM version of the MB89140 series.
1. Features
• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.
Address
0000H
Single chip
EPROM mode
(Corresponding addresses on the EPROM programmer)
I/O
0080H
0480H
RAM
Not available
Not available
8000H
8007H
0000H
Option area
0007H
PROM
32 KB
EPROM
32 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P147 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the PROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH
while operating as a single chip assign to 0007H to 7FFFH in EPROM mode).
Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each
corresponding option, see “5. Setting OTPROM Options.” in section “■ Programming to the EPROM with
Piggyback/evaluation Device” )
(3) Program to 0000H to 7FFFH with the EPROM programmer.
15
MB89140 Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
DIP-64P-M01
FPT-64P-M06
Compatible socket adapter
ROM-64SD-28DP-8L4
ROM-64QF-28DP-8L4
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
16
MB89140 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV, MBM27C256A-20CZ
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
ROM-32LC-28DP-YG
ROM-32LC-28DP-S
LCC-32 (Rectangle)
LCC-32 (Square)
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address
0000H
Single chip
Corresponding addresses on the EPROM programmer
I/O
0080H
0480H
RAM
Not available
Not available
8000H
8007H
0000H
Option area
0007H
PROM
32 KB
EPROM
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0007H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
17
MB89140 Series
5. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming values at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
• OTPROM option bit map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vacancy
Vacancy
Vacancy
Single/dual-
clock system
Reset pin
output
1: Yes
Power-on
reset
1: Yes
0: No
Reserved
(Write 1 bit (Write 1 bit
to this bit.) to this bit.)
Reserved
8000H
Readable and Readable and Readable and 1: Dual clock
(0000H)
writable
writable
writable
0: Single clock
0: No
Vacancy
Vacancy
Vacancy
Vacancy
P17
P16
P15
P14
8001H
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable and Readable and Readable and Readable and
(0001H)
writable
writable
writable
writable
Vacancy
Vacancy
P37
P36
P35
P34
P33
P32
8002H
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable and Readable and
(0002H)
writable
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
8003H
Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and
(0003H)
writable
writable
writable
writable
writable
writable
writable
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
8004H
Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and
(0004H)
writable
writable
writable
writable
writable
writable
writable
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
8005H
Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and
(0005H)
writable
writable
writable
writable
writable
writable
writable
writable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
8006H
Readable and Readable and Readable and Readable and Readable and Readable and Readable and Readable and
(0006H)
writable
writable
writable
writable
writable
writable
writable
writable
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
• The parenthesized addresses are the corresponding addresses on the EPROM programmer.
18
MB89140 Series
■ BLOCK DIAGRAM
X0
X1
Main clock oscillator
Clock controller
Time-base timer
Buzzer
BZ
8
8
8
P70, P71
X0A
Subclock oscillator
(32.768 kHz)
High-voltage port 6
High-voltage port 5
High-voltage port 4
P60 to P67
X1A
CMOS input port
CMOS output port
P50 to P57
P23/WDG
P22
P21/PWO0
P20
P40 to P47
VFDP
8-bit PWM timer
P32/SCK
P33/SO
P34/SI
8-bit serial interface
Mode control
MODA
AVCC
AVSS
10-bit A/D converter
P30/TRG/INT0
P37/DTTI
12-bit MPG
P36/PWO1
P17/ADST
4
P14 to P16
4
8/16-bit
P13/ANB to
P10/AN8
8
P07/AN7 to
P00/AN0
P35/EC
timer/counter
CMOS I/O port
External
interrupt
P31/INT1
(N-ch open-drain)
RAM
CMOS I/O port
Reset circuit
F2MC-8L
CPU
RST
ROM
Other pins
VCC, VSS
19
MB89140 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89140 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89140 series is structured as illustrated below.
Memory Space
MB89PV140
I/O
MB89145
I/O
MB89146
I/O
MB89P147
I/O
0000H
0080H
0000H
0080H
0000H
0080H
0000H
0080H
RAM
RAM
RAM
RAM
0100H
0200H
0100H
0100H
0200H
0380H
0100H
0200H
Register
Register
Register
Register
0200H
0280H
0480H
8000H
8006H
0480H
8000H
8006H
Not available
Not available
Not available
Not available
*
*
A000H
C000H
External ROM
32 KB
PROM
32 KB
ROM
24 KB
ROM
16 KB
FFFFH
FFFFH
FFFFH
FFFFH
*: Since addresses 8000H to 8005H for the MB89P147 comprise an option area, do not use this area for the MB89PV140.
20
MB89140 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
16 bits
PC
Initial value
FFFDH
: Program counter
: Accumulator
A
T
Undefined
Undefined
Undefined
Undefined
Undefined
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
21
MB89140 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
22
MB89140 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used in the MB89140 series. The bank currently in use is
indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
23
MB89140 Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Port 0 data register
DDR0
Port 0 data direction register
Port 1 data register
(R/W)
(W)
PDR1
DDR1
Port 1 data direction register
Port 2 data register
(R/W)
PDR2
Vacancy
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
SYCC
STBC
WDTC
TBCR
WPCR
PDR3
DDR3
BUZR
EIC
System clock control register
Standby control register
Watchdog timer control register
Time-base timer control register
Watch prescaler control register
Port 3 data register
Port 3 data direction register
Buzzer register
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R)
External interrupt control register
Port 4 data register
PDR4
PDR5
PDR6
PDR7
Port 5 data register
Port 6 data register
Port 7 data register
Vacancy
Vacancy
(W)
COMR
CNTR
T3CR
T2CR
T3DR
T2DR
SMR
8-bit PWM timer compare register
8-bit PWM timer control register
Timer 3 control register
Timer 2 control register
Timer 3 data register
Timer 2 data register
Serial mode register
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
SDR
Serial data register
ADC1
ADC2
A/D converter control register 1
A/D converter control register 2
(Continued)
24
MB89140 Series
(Continued)
Address
Read/write
(R/W)
(R/W)
(W)
Register name
ADDH
Register description
20H
21H
A/D converter data register (H)
ADDL
A/D converter data register (L)
Port input control register 0
Port input control register 1
MPG control register
MPG interrupt status register
MPG compare clear buffer register H
MPG compare clear buffer register L
MPG output buffer register H
MPG output buffer register L
Vacancy
22H
PCR0
23H
(W)
PCR1
24H
(R/W)
(R/W)
(W)
MCNT
25H
INTSTR
26H
CMCLBR (H)
CMCLBR (L)
OUTCBR (H)
OUTCBR (L)
27H
(W)
28H
(W)
29H
(W)
2AH
2BH
2CH
2DH
2EH
2FH
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
30H to 77H
78H
Vacancy
Vacancy
79H
Vacancy
7AH
7BH
7CH
7DH
7EH
7FH
Vacancy
Vacancy
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
Note: Do not use vacancies.
25
MB89140 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VSS + 7.0
VSS + 7.0
VCC + 0.3
7
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS – 0.3
VCC
V
V
V
V
Power supply voltage
AVCC
*2
VIO1
Except P31
P31
I/O voltage
VIO2
Average value (operating current ×
“H” level total average output current ΣIOH
—
—
–120
–12
mA
mA
operating rate)
P00 to P07, P10 to P17,
P20 to P23, P30, P32 to P37
“H” level maximum output current
“H” level average output current
IOH
—
—
–20
–36
mA P40 to P47, P50 to P57
mA P60 to P67, BZ
P00 to P07, P10 to P17,
P20 to P23, P30, P32 to P37
—
–6
mA
Average value (operating current ×
operating rate)*1
P40 to P47, P50 to P57
mA Average value (operating current ×
operating rate)*1
IOHAV
—
—
–10
–18
P60 to P67, BZ
mA Average value (operating current ×
operating rate)*1
Average value (operating current ×
“L” level total average output current
“L” level maximum output current
ΣIOLAV
—
—
150
12
mA
operating rate)*1
P00 to P07, P10 to P17,
mA
IOL
P20 to P23, P30 to P37
P00 to P07, P10 to P17,
P20 to P23, P30 to P37
“L” level average output current
IOLAV
—
6
mA
Average value (operating current ×
operating rate)*1
Power consumption
Operating temperature
Storage temperature
PD
—
500
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
*1: The total average output current is defined as the average current that flows through all of the relevant pins in
a 100 ms period. The output peak current is defined as the peak value of any one of the relevant pins. The
average output current is defined as the average current that flows through any one of the relevant pins in a
100 ms period.
*2: Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
26
MB89140 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
2.7*
6.0*
V
V
Normal operation assurance range*
VCC
In watch mode or subclock operation (Only for
the MB89P147, the minimum value is 2.7 V.)
2.2
1.5
6.0
6.0
AVCC
Power supply voltage
V
V
Retains the RAM state in stop mode
VFDP
VCC – 40 VCC + 0.3
–40 +85
Operating temperature TA
°C
* : These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter
Electrical Characteristics.”
6
5
Operation assurance range
4
3
2
1
2
3
4
5
6
7
8
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
2.0
0.8
0.5
Minimum execution time (instruction cycle) (µs)
Figure 1 Operating Voltage vs. Main Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
27
MB89140 Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
“H” level input
voltage
P30 to P37,
VCC + 0.3
Hysteresis input
VIHS
0.7 VCC
—
V
P70, P71,
X0, X1, RST, MODA
—
P00 to P07,
P10 to P17,
“L” level input
voltage
P30 to P37,
VSS – 0.3
Hysteresis input
VILS
—
—
0.2 VCC
V
V
P70, P71,
X0, X1, RST, MODA
P00 to P07,
P10 to P17,
P20 to P23,
P30, P32 to P37
VOH1
IOH = –2.0 mA
2.4
—
“H” level output
voltage
P40 to P47,
P50 to P57
VOH2
VOH3
IOH = –10 mA
IOH = –18 mA
3.0
3.0
—
—
—
—
V
V
P60 to P67, BZ
P00 to P07,
P10 to P17,
P20 to P23,
P30, P32 to P37
VOL1
IOL = 1.8 mA
IOL = 4.0 mA
—
—
—
—
0.4
0.6
V
V
“L” level output
voltage
VOL2
RST
P00 to P07,
P10 to P17,
P30 to P37,
P70, P71,
MODA
Without pull-up
resistor for P14
to P17 and P32
to P37
0.45 V < VI < VCC
VI = 0.0 V
ILI1
—
—
±5
µA
Input leakage
current
With pull-up
resistor
P14 to P17,
P32 to P37
ILI2
–200
—
–100
—
–50
–10
–20
µA
µA
µA
P40 to P47,
P50 to P57
VI = VFDP
= VCC – 40 V
ILO1
ILO2
Output leakage
current
VI = VFDP
= VCC – 40 V
P60 to P67, BZ
—
—
RST
P14 to P17,
P32 to P37
With pull-up
resistor
Pull-up
resistance
RPULU
VI = 0.0 V
25
50
50
100
150
kΩ
kΩ
P40 to P47,
P50 to P57,
P60 to P67
With pull-down
resistor optional
Pull-down
resistance
RPULD
VOH = 5.0 V
100
(Continued)
28
MB89140 Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
FCH = 8 MHz
VCC = 5.0 V
tinst*2 = 0.5 µs
Output open
ICC1
—
9
15
mA
FCH = 8 MHz
VCC = 3.2 V
tinst*2 = 8.0 µs
Output open
—
—
1.5
2.5
2
mA
ICC2
5.0
mA MB89P147
FCH = 8 MHz
VCC = 5.0 V
ICCS1
ICCS2
ICCL
—
—
3
1
7
mA
mA
tinst*2 = 0.5 µs
FCH = 8 MHz
VCC = 3.2 V
tinst*2 = 8.0 µs
1.5
VCC
Subclock mode
FCL = 32.768 kHz
VCC = 3.0 V
—
—
50
1
150
3
µA
Power supply
current*1
mA MB89P147
Subclock sleep mode
ICCLS
—
25
50
µA
FCL = 32.768 kHz
VCC = 3.0 V
Watch mode
FCL = 32.768 kHz
VCC = 3.0 V
ICCT
ICCH
IA
—
—
—
3
15
10
4
µA
µA
Stop mode
TA = +25°C
—
FCH = 8 MHz,
when A/D conversion
is activated
1.5
mA
AVCC
TA = +25°C,
when A/D conversion
is stopped
IAH
—
—
1
5
µA
Other than AVCC,
AVSS, VCC, and
VSS
Input capacitance CIN
f = 1 MHz
10
—
pF
*1: The power supply current is measured at the external clock.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Note: FCH indicates the main clock oscillation frequency. When FCH = 8 MHz, the 4/FCH execution time is 0.5 µs, and
the 64/FCH execution time is 8 µs.
29
MB89140 Series
4. AC Characteristics
(1) Reset Timing
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Condition
Unit Remarks
Min.
16 tXCYL
30
Typ.
—
Max.
—
RST “L” pulse width
RST noise limit width
tZLZH
tZLNC
ns
ns
—
50
80
Note: TXCYL is the oscillation cycle (1/FCH) to input to the X0 pin.
tZLZH
tZLNC
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Condition
Unit
Remarks
Parameter
Min.
—
Max.
50
Power supply rising time
Power supply cut-off time
tR
ms
ms
Power-on reset function only
Due to repeated operations
—
tOFF
1
—
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
2.0 V
0.2 V
0.2 V
0.2 V
VCC
30
MB89140 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Symbol
Pin
Condition
Unit
Remarks
Parameter
Clock frequency
Clock cycle time
Min.
2
Max.
8
FCH
X0, X1
MHz
kHz
ns
FCL
X0A, X1A
X0, X1
—
32.768
—
—
tXCYL
tLXCYL
125
—
500
—
X0A, X1A
30.5
µs
—
PWH
PWL
X0
30
—
—
—
15.2
—
—
—
10
ns
µs
ns
Input clock pulse width
External clock
External clock
PWHL
PWLL
X0A
Input clock rising/falling
time
tCR
tCF
X0, X0A
X0 and X1 Timing and Conditions
tXCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0
X1
X0
X1
Open
C0
C1
31
MB89140 Series
X0A and X1A Timing and Conditions
tLXCYL
PWHL
PWLL
tCF
tCR
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
Subclock Conditions
MB89PV140
When a crystal or ceramic resonator is used
When an external clock is used
RF = approx. 2 MΩ
X0A
X1A
X0A
C0
X1A
C1
Open
RD
Mask ROM products and MB89P147
When a crystal or ceramic resonator is used
When an external clock is used
X0A
X1A
X0A
X1A
Open
RF
RD
C0
C1
Note: The subclock oscillator feedback resistor is connected externally in dual-clock mask ROM products and in the
MB89P147. (The subclock oscillator feedback resistor is connected internally in the MB89PV140-102.)
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
Remarks
(4/FCH) tinst = 0.5 µs when operating at
FCH = 8 MHz
4/FCH, 8/FCH, 16/FCH, 64/FCH µs
Instruction cycle
(minimum execution time)
tinst
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
2/FCL
µs
32
MB89140 Series
(5) Serial I/O Timing
Parameter
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
SCK
Condition
Unit Remarks
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
SCK
200
—
Internal shift
clock mode
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External shift
clock mode
SCK, SO
SI, SCK
SCK, SI
200
—
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.3 VCC
SI
0.3 VCC
External Shift Clock Mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SO
SI
tIVSH
tSHIX
0.8 VCC
0.3 VCC
0.8 VCC
0.3 VCC
33
MB89140 Series
(6) Peripheral Input Timing
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Parameter
Min.
Max.
TRG, DTTI
ADST, EC
Peripheral input “H” pulse width 1
tILIH1
—
2 tinst*
—
µs
INT0 to INT1
TRG, DTTI
ADST, EC
Peripheral input “L” pulse width 1
tIHIL1
—
2 tinst*
—
µs
INT0 to INT1
* : For information on tinst, see “(4) Instruction Cycle.”
(7) Peripheral Input Noise Limit Width
(AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
tIHNC1
Condition
Unit
Remarks
Parameter
Min.
7
Typ.
15
Max.
30
MB89P147/PV140
ns
ns
ns
ns
ns
ns
ns
ns
Peripheral input “H”
level noise limit width 1
All inputs except
INT1 and INT0
Except MB89P147/PV140
MB89P147/PV140
15
7
30
60
15
30
Peripheral input “L”
level noise limit width 1
All inputs except
INT1 and INT0
tILNC1
Except MB89P147/PV140
MB89P147/PV140
15
30
50
30
50
30
60
50
100
250
100
250
Interrupt “H” level noise
limit width 2
tIHNC2
INT1, INT0
INT1, INT0
Except MB89P147/PV140
MB89P147/PV140
100
50
Interrupt “L” level noise
limit width 2
tILNC2
Except MB89P147/PV140
100
tIHIL1
tILIH1
TRG
DTTI
ADST
INT0 to INT1
EC
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tILNC1
tILNC2
tIHNC1
tIHNC2
P00 to P07, P01 to P17
0.8 VCC
0.2 VCC
0.8 VCC
P30 to P37, P70, P71
TRG, SCK, SI,
EC, DTTI, ADST
INT1, INT0
0.2 VCC
34
MB89140 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 5.0 V+10%, FCH = 8 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Remarks
Parameter
Resolution
Pin
Unit
Min.
—
Typ.
—
Max.
10
—
bit
Total error
—
—
±3.0
±2.0
±1.5
LSB
LSB
LSB
—
—
AVCC = VCC
= 5.0 V
Linearity error
—
—
Differential linearity error
—
—
AN0 to
ANB
AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC + 0.5 LSB
Zero transition voltage
VOT
—
mV
AN0 to
ANB
Full-scale transition
voltage
VFST
—
—
mV
LSB
tinst*
Interchannel disparity
—
—
—
4
—
—
At 8-MHz
oscillation
A/D mode conversion
time
33
—
AN0 to AVCC = VCC
Analog port input current IAIN
Analog input voltage
—
—
—
10
µA
ANB
= 5.0 V
AN0 to
ANB
—
—
0.0
AVCC
V
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
Notes: • The smaller AVCC, the greater the error would become relatively.
• The output impedance of the external circuit connected to an analog input block should be no more than
several kΩ. If the output impedance is too high, the analog voltage sampling time might be insufficient.
Sample hold circuit
R ≤ 10 kΩ is
recommended.
AN
.
C = 60 pF
.
Comparator
.
R = 3 kΩ
.
Analog channel
selector
Close for approx. 15 to 72 instruction cycles after
activating A/D conversion. (The close time
depends on the register settings.)
When R > 10 kΩ, it is
recommended to connect
an external capacitor of
approx. 0.1 µF.
35
MB89140 Series
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error
The difference between theoretical and actual values
This error is caused by the zero transition error, full-scale transition error, linearity error, quantization error and
noise.
Theoretical I/O characteristics
VFST
Total error
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
value
1.5 LSB
{1 LSB × N + 0.5 LSB}
004
003
002
001
004
003
002
001
VNT
VOT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VFST – VOT
VNT – {1 LSB × N + 0.5 LSB}
1 LSB =
(V)
Total error for digital output N =
1022
1 LSB
(Continued)
36
MB89140 Series
(Continued)
Zero transition error
Full-scale transition error
Theoretical value
004
003
002
001
Actual conversion
value
3FF
3FE
3FD
3FC
Actual conversion
value
VFST
(measured value)
Actual conversion
value
Actual conversion
value
VOT (measured value)
Analog input
AVSS
AVR
Analog input
Linearity error
Differential linearity error
3FF
3FE
3FD
Theoretical value
Actual conversion
value
N + 1
{1 LSB × N + VOT}
Actual conversion
value
V(N + 1) T
VFST
(measured
value)
N
VNT
004
003
002
001
N – 1
N – 2
VNT
Actual conversion
value
Actual conversion
value
Theoretical value
VOT (measured value)
AVSS
AVR
AVSS
AVR
– 1
Analog input
Analog input
V(N + 1) T – VNT
VNT – {1 LSB × N + VOT}
Linearity error for digital output N =
Differential linearity error for digital output N =
1 LSB
1 LSB
37
MB89140 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
(2) “H” Level Output Voltage
VOL vs. IOL
VCC – VOH vs. IOH
VCC – VOH (V)
1.0
VOL (V)
0.5
VCC = 2.5 V
TA = +25°C
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.5 V
VCC = 3.0 V
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
0.3
0.2
0.1
0.0
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.0
–0.5 –1.0 –1.5 –2.0 –2.5 –3.0
IOH (mA)
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)
CMOS hysteresis input
VIN (V)
5.0
TA = +25°C
4.5
4.0
3.5
VIHS
3.0
2.5
VILS
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level
38
MB89140 Series
(4) Power Supply Current (External Clock)
ICC1 vs. VCC, ICC2 vs. VCC
ICC (mA)
ICCS1 vs. VCC, ICCS2 vs. VCC
ICCS (mA)
4.0
FCH = 8 MHz
FCH = 8 MHz
TA = +25°C
16
Divide by 4 (ICCS1)
TA = +25°C
Divide by 4 (ICC1)
14
12
10
8
3.0
2.0
1.0
Divide by 64 (ICCS2)
6
4
Divide by 64 (ICC2)
2
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
VCC (V)
ICCL vs. VCC
ICCLS vs. VCC
ICCL (µA)
ICCLS (µA)
50
200
180
160
140
120
100
80
TA = +25°C
TA = +25°C
40
30
20
10
60
40
20
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
VCC (V)
(Continued)
39
MB89140 Series
(Continued)
ICCT vs. VCC
ICCH vs. VCC
ICCT (µA)
ICCH (µA)
1.8
18
16
14
TA = +25°C
TA = +25°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
12
10
8
6
4
2
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
VCC (V)
(5) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
50
TA = +85°C
TA = +25°C
TA = –40°C
10
1
2
3
4
5
6
7
VCC (V)
40
MB89140 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir: b
rel
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
AH
AL
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
T
TH
TL
IX
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
(Continued)
41
MB89140 Series
(Continued)
Symbol
Meaning
EP
PC
SP
PS
dr
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
CCR
RP
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
( × )
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
~:
Assembler notation of an instruction
Number of instructions
Number of bytes
#:
Operation:
TL, TH, AH:
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
42
MB89140 Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
–
–
–
–
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics are
written. (Reverse arrangement of F2MC-8 family)
43
MB89140 Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
A
C
←
C ← A
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
44
MB89140 Series
(Continued)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
45
MB89140 Series
■ INSTRUCTION MAP
46
MB89140 Series
■ MASK OPTIONS
Part number
MB89145V1
MB89146V1
MB89145V2
MB89146V2
MB89PV140 MB89PV140
-101 -102
MB89P147V1 MB89P147V2
No.
Parameter
Power-on reset
With power-on reset
Without power-on reset
Fixed to with power-on reset
Specify when ordering masking
Specify when ordering masking
Specify when ordering masking
Set with EPROM programmer
1
Reset pin output
With reset output
Without reset output
Clock mode selection
Single-clock mode
Dual-clock mode
Pull-up resistors
P14 to P17
Fixed to with power-on reset
Set with EPROM programmer
Set with EPROM programmer
2
3
4
Single clock
Dual clock
Specify when ordering masking
(specify by pin)
Set with EPROM programmer
(specify by pin)
Fixed to without pull-up resistor
Fixed to without pull-up resistor
P32 to P37
Pull-down resistors
P47 to P40
All pins with
Without pull-
All pins with
Without pull-
pull-down
pull-down
5
down resistor
resistor
down resistor
resistor
P57 to P50
P67 to P60
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89145V1P-SH
MB89145V2P-SH
MB89146V1P-SH
MB89146V2P-SH
MB89P147V1P-SH
MB89P147V2P-SH
64-pin Plastic SH-DIP
(DIP-64P-M01)
MB89145V1PF
MB89145V2PF
MB89146V1PF
MB89146V2PF
MB89P147V1PF
MB89P147V2PF
64-pin Plastic QFP
(FPT-64P-M06)
MB89PV140C-101-ES-SH
MB89PV140C-102-ES-SH
64-pin Ceramic MDIP
(MDP-64C-P02)
MB89PV140CF-101-ES
MB89PV140CF-102-ES
64-pin Ceramic MQFP
(MQP-64C-P01)
47
MB89140 Series
■ PACKAGE DIMENSIONS
64-pin Plastic SH-DIP
(DIP-64P-M01)
58.00+–00..5252
2.283–+..002028
INDEX-1
INDEX-2
17.00±0.25
(.669±.010)
5.65(.222)MAX
3.00(.118)MIN
0.25±0.05
(.010±.002)
1.00–+00.50
0.45±0.10
(.018±.004)
0.51(.020)MIN
19.05(.750)
TYP
.039–+0.020
15°MAX
1.778±0.18
(.070±.007)
1.778(.070)
MAX
55.118(2.170)REF
C
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm (inches)
64-pin Plastic QFP
(FPT-64P-M06)
24.70±0.40(.972±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
51
33
0.05(.002)MIN
(STAND OFF)
52
32
14.00±0.20 18.70±0.40
(.551±.008) (.736±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
64
20
"A"
1
19
LEAD No.
0.15±0.05(.006±.002)
Details of "B" part
1.00(.0394)
TYP
0.40±0.10
(.016±.004)
M
0.20(.008)
Details of "A" part
0.25(.010)
"B"
0.30(.012)
0.18(.007)MAX
0.63(.025)MAX
0.10(.004)
18.00(.709)REF
22.30±0.40(.878±.016)
0
10°
1.20±0.20
(.047±.008)
C
1994 FUJITSU LIMITED F64013S-3C-2
Dimensions in mm (inches)
48
MB89140 Series
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
19.05±0.30
(.750±.012)
INDEX AREA
2.54±0.25
(.100±.010)
0.25±0.05
(.010±.002)
33.02(1.300)REF
1.27±0.25
(.050±.010)
10.16(.400)MAX
+0.13
3.43±0.38
(.135±.015)
1.778±0.25
(.070±.010)
0.46–0.08
0.90±0.13
(.035±.005)
.018+–..000035
55.12(2.170)REF
C
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches)
64-pin Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
INDEX AREA
1.00±0.25
(.039±.010)
1.20–+00..2400
.047 –+..000186
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.00(.709)
TYP
10.16(.400)
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20+–00..2400
.047 +–..000186
10.82(.426)
MAX
0.15±0.05
(.006±.002)
0.50(.020)TYP
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED M64004SC-1-3
49
MB89140 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
All Rights Reserved.
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Com-
plete information sufficient for construction purposes is not nec-
essarily given.
Tel: (06103) 690-0
Fax: (06103) 690-122
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu as-
sumes no responsibility for inaccuracies.
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
The information contained in this document does not convey any
license under the copyrights, patent rights or trademarks claimed
and owned by Fujitsu.
#06-04 to #06-07
Singapore 189554
Tel: 336-1600
Fujitsu reserves the right to change products or specifications
without notice.
Fax: 336-1609
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
The information contained in this document are not intended for
use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear con-
trol systems or medical equipments for life support.
F9603
FUJITSU LIMITED Printed in Japan
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