MB89165A-PFS [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有
| 型号： | MB89165A-PFS |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontroller |
| 文件： | 总59页 (文件大小：826K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12405-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89160/160A Series
MB89161/163/165/P165/PV160/W165
MB89161A/163A/165A
■ DESCRIPTION
The MB89160 series is a line of the general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers contain a variety of peripheral functions such as an LCD controller/driver,
an A/D converter, timers, a serial interface, PWM timers, and external interrupts.
■ FEATURES
• F2MC-8L family CPU core
• Dual-clock control system
• Maximum memory size: 16-Kbyte ROM, 512-byte RAM (max.)
• Minimum execution time: 0.95 µs/4.2 MHz
• I/O ports: max. 54 channels
• 21-bit time-base counter
• 8/16-bit timer/counter: 2 or 1 channels
• 8-bit serial I/O: 1 channel
• External interrupts (wake-up function): Four channels with edge selection plus eight level-interrupt channels
• 8-bit A/D converter: 8 channels
• 8-bit PWM timers: 2 channels
• Watch prescaler (15 bits)
• LCD controller/driver: 24 segments × 4 commons (max. 96 pixels)
• LCD driving reference voltage generator and booster (option)
• Remote control transmission output
• Buzzer output
• Power-on reset function (option)
• Low-power consumption modes (stop, sleep, and watch mode)
• CMOS technology
MB89160/160A Series
■ PACKAGE
80-pin Plastic QFP
80-pin Plastic SQFP
80-pin Plastic QFP
(FTP-80P-M06)
(FTP-80P-M05)
(FTP-80P-M11)
80-pin Ceramic QFP
80-pin Ceramic MQFP
(FPT-80C-A02)
(MQP-80C-P01)
2
MB89160/160A Series
■ PRODUCT LINEUP
Part number
MB89161/
MB89163/
MB89165/
MB89P165 MB89W165 MB89PV160
Parameter
MB89161A*1 MB89163A*1 MB89165A*1
Classification
Mass production products
(mask ROM products)
One-time
PROM
product
EPROM
product
Piggyback/
evaluation
product (for
development)
ROM size
4 K × 8 bits
(internal
mask ROM)
8 K × 8 bits
(internal mask (internal
ROM)
16 K × 8 bits
16 K × 8 bits
32 K × 8 bits
(external
ROM)
(internal PROM, programming
with general-purpose EPROM
programmer)
mask ROM)
RAM size
128 × 8 bits
256 × 8 bits
512 × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
136
8 bits
1 to 3 bytes
1, 8,16 bits
0.95 µs/4.2 MHz
Interrupt processing time: 9 µs/4.2 MHz
Ports
I/O port (N-ch open-drain): 8 (6 ports also serve as peripherals, 3 ports
are a heavy-current drive type.)
Output ports (N-ch open-drain): 28 (16 ports also serve as segment pins, 2 ports
serve as booster capacitor connection pins,
2 ports serve as common pins.)*3
(8 ports also serve as an A/D input)
I/O ports (CMOS):
Output ports (CMOS):
Total:
16 (12 ports also serve as an external interrupt)
2 (Also serve as peripherals)
54 (max.)
Timer/counter
Serial I/O
8-bit timer operation (toggled output capable, operating clock cycle 1.9 µs to 486 µs)
16-bit timer operation (toggled output capable, operating clock cycle 1.9 µs to 486 µs)
8 bits
LSB first/MSB first selectability
One clock selectable from four operation clocks
(one external shift clock, three internal shift clocks: 1.9 µs, 7.6 µs, 30.4 µs)
LCD controller/
driver
Common output:
Segment output:
Bias power supply pins:
LCD display RAM size:
Booster for LCD driving:
4 (max.)
24 (max.) *3
4
Without a
booster for
LCD driving
24 × 4 bits
Built-in (product with a booster)*3
Dividing resistor for LCD driving: Built-in (an external resistor
selectability)
A/D converter
8-bit resolution × 8 channels
A/D conversion mode (conversion time 43 µs/4.2 MHz (44 instruction cycles))
Sense mode (conversion time 11.9 µs/4.2 MHz)
Continuous activation by an internal timer capable
Reference voltage input
(Continued)
3
MB89160/160A Series
(Continued)
Part number
Parameter
MB89161/
MB89163/
MB89165/
MB89P165 MB89W165 MB89PV160
MB89161A*1 MB89163A*1 MB89165A*1
PWM timer 1,
PWM timer 2
8 bits × 2 channels
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.95 µs to
124 ms)
8-bit resolution PWM operation (conversion cycle: 243 µs to 32 s)
External interrupt 1
(wake-up function)
4 independent channels (edge selectability)
Rising edge/falling edge selectability
Used also for wake-up from stop/sleep mode.
(Edge detection is also permitted in stop mode.)
External interrupt 2
Buzzer output
“L” level interrupts × 8 channels
1 (7 frequencies are selectable by the software.)
Remote control
transmission
output
1 (Pulse width and cycle are software selectable.)
Standby modes
Process
Subclock mode, sleep mode, stop mode, and watch mode
CMOS
Operating voltage*2
2.2 V to 6.0 V (single clock)/
2.7 V to 6.0 V
2.2 V to 4.0 V (dual clock)
MBM27C256A-
20TV
EPROM for use
—
*1: Products with an internal booster.
*2: Varies with conditions such as the operating frequency. (The operating voltage of the A/D converter is assured
separately. See section “■ Electrical Characteristics.”)
*3: See section “■ Mask Options.”
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89161
MB89161A
MB89163
MB89163A
MB89165
MB89165A
Package
MB89PW165 MB89W165
MB89PV160
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
FPT-80C-A02
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89160/160A Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89161/A and MB89163/A, the upper half of each register bank cannot be used.
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV160, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in the sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-up resistor cannot be set for P20 to P27 on the MB89P165.
• A pull-up resistor is not selectable for P40 to P47 and P60 to P67 if they are used as LCD pins.
• Options are fixed on the MB89PV160.
5
MB89160/160A Series
■ PIN ASSIGNMENT
(Top view)
P46/SEG22*7
P47/SEG23*7
AVSS
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
COM0
V3
VCC
V2
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
VSS
P57/AN7
X1
X0
MOD1
9
10
11
12
13
14
15
16
17
18
19
20
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
X0A
P27/PWM2*3
P26*3
MOD0
RST
P00/INT20
P25/SCK
(FPT-80P-M11)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section ■ Mask Options."
6
MB89160/160A Series
(Top view)
P44/SEG20*7
P45/SEG21*7
P46/SEG22*7
P47/SEG23*7
AVSS
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG3
SEG2
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
COM0
V3
VCC
V2
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
X0A
P27/PWM2*3
P26*3
P25/SCK
P24/SO
P23/SI
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
VSS
P57/AN7
X1
X0
MOD1
MOD0
RST
P00/INT20
P01/INT21
P02/INT22
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(FPT-80P-M06)
(FPT-80C-A02)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section “■ Mask Options.”
7
MB89160/160A Series
(Top view)
P46/SEG22*7
P47/SEG23*7
AVSS
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
COM0
V3
VCC
V2
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
VSS
P57/AN7
X1
X0
MOD1
9
10
11
12
13
14
15
16
17
18
19
20
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
X0A
P27/PWM2*3
P26*3
MOD0
RST
P00/INT20
P25/SCK
(FPT-80P-M05)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section “■ Mask Options.”
8
MB89160/160A Series
(Top view)
P44/SEG20*7
P45/SEG21*7
P46/SEG22*7
P47/SEG23*7
AVSS
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG3
SEG2
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
COM0
V3
101
102
103
104
105
106
107
108
109
93
92
91
90
89
88
87
86
85
9
V
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V2
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
V
SS
P57/AN7
X1
X0
MOD1
MOD0
RST
P00/INT20
P01/INT21
P02/INT22
X0A
P27/PWM2*3
P26*3
P25/SCK
P24/SO
P23/SI
(MQP-80C-P01)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section “■ Mask Options.”
• Pin assignment on package top (MB89PV160 only)
Pin no.
81
Pin name
N.C.
VPP
Pin no.
89
Pin name
A2
Pin no.
97
Pin name
N.C.
O4
Pin no.
105
Pin name
OE
82
90
A1
98
106
N.C.
A11
A9
83
A12
A7
91
A0
99
O5
107
84
92
N.C.
O1
100
101
102
103
104
O6
108
85
A6
93
O7
109
A8
86
A5
94
O2
O8
110
A13
A14
VCC
87
A4
95
O3
CE
111
88
A3
96
VSS
A10
112
N.C.: Internally connected. Do not use.
9
MB89160/160A Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
SQFP*1
MQFP*3
Pin name
Function
QFP*2
QFP*4
16
15
18
17
19
18
17
20
19
21
X0
X1
A
Main clock crystal oscillator pins
CR oscillation selectability (mask products only)
MOD0
MOD1
RST
C
D
Operating mode selection pins
Connect directly to VSS.
Reset I/O pin
This pin is an N-ch open-drain output type with a
pull-up resistor, and a hysteresis input type. “L” is
output from this pin by an internal reset source. The
internal circuit is initialized by the input of “L”.
20 to 27
28 to 31
22 to 29
30 to 33
P00/INT20 to
P07/INT27
E
E
General-purpose I/O ports
Also serve as an external interrupt 2 input (wake-up
function).
External interrupt 2 input is hysteresis input.
P10/INT10 to
P13/INT13
General-purpose I/O ports
Also serve as an external interrupt 1 input. External
interrupt 1 input is hysteresis input.
32 to 35
36
34 to 37
38
P14 to P17
P20/EC
F
General-purpose I/O ports
H
N-ch open-drain general-purpose I/O port
Also serves as the external clock input for the timer.
The peripheral is a hysteresis input type.
37
38
39
40
P21
I
I
N-ch open-drain general-purpose I/O port
P22/TO
N-ch open-drain general-purpose I/O port
Also serves as a timer output.
39
41
P23/SI
H
N-ch open-drain general-purpose I/O port
Also serves as the data input for the serial I/O. The
peripheral is a hysteresis input type.
40
41
42
43
P24/SO
I
N-ch open-drain general-purpose I/O port
Also serves as the data output for the serial I/O.
P25/SCK
H
N-ch open-drain general-purpose I/O port
Also serves as the clock I/O for the serial I/O. The
peripheral is a hysteresis input type.
42
43
44
45
P26
I
I
N-ch open-drain general-purpose I/O port
P27/PWM2
N-ch open-drain general-purpose I/O port
Also serves as the square wave or PWM wave
output for the 8-bit PWM timer 2.
49
51
P33
C0
J
Functions as an N-ch open-drain general-purpose
output port only in the products without a booster.
—
Functions as a capacitor connection pin in the
products with a booster.
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M11
*3: MQP-80C-P01
*4: FPT-80P-M06
10
MB89160/160A Series
(Continued)
Pin no.
Circuit
type
SQFP*1
MQFP*3
Pin name
P32
Function
QFP*2
QFP*4
48
50
J
Functions as an N-ch open-drain general-purpose
output port only in the products without a booster.
C1
—
G
Functions as a capacitor connection pin in the
products with a booster.
47
46
49
48
P31/PWM1
General-purpose output-only port
Also serves as the square wave or PWM wave
output for the 8-bit PWM timer 1.
P30/RCO/BUZ
G
General-purpose output-only port
Also serves as a buzzer output and a remote
control transmission frequency output.
14,
12 to 6
16,
14 to 8
P57/AN7 to
P50/AN0
L
N-ch open-drain general-purpose output ports
Also serve as an analog input.
2, 1,
80 to 75
4 to 1
80 to 77
P47/SEG23 to
P40/SEG16
J/K
J/K
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver segment
output. Switching between port and segment output
is done by the mask option.
74 to 67
76 to 69
P67/SEG15 to
P60/SEG8
66 to 59
68 to 61
SEG7 to SEG0
K
LCD controller/driver segment output pins
58,
57
60,
59
P71/COM3,
P70/COM2
J/K
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver common
output. Switching between port and common output
is done by the mask option.
56,
55
58,
57
COM1,
COM0
K
—
B
LCD controller/driver common output-only pins
54,
52 to 50
56,
54 to 52
V3,
V2 to V0
LCD driving power supply pins
44
45
53
13
5
46
47
55
15
7
X0A
X1A
VCC
Subclock crystal oscillator pins (32.768 KHz)
—
—
—
Power supply pin
VSS
Power supply (GND) pin
AVSS
A/D converter power supply pin
Use this pin at the same voltage as VCC.
4
3
6
5
AVR
—
—
A/D converter reference voltage input pin
AVSS
A/D converter power supply pin
Use this pin at the same voltage as VSS.
*1: FPT-80P-M05
*2: FPT-80P-M11
*3: MQP-80C-P01
*4: FPT-80P-M06
11
MB89160/160A Series
• External EPROM pins (MB89PV160 only)
Pin no.
Pin name
I/O
O
Function
82
VPP
“H” level output pin
Address output pins
83
84
85
86
87
88
89
90
91
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
93
94
95
O1
O2
O3
I
Data input pins
96
VSS
O
I
Power supply (GND) pin
Data input pins
98
99
100
101
102
O4
O5
O6
O7
O8
103
CE
O
ROM chip enable pin
Outputs “H” during standby.
104
105
A10
OE
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
107
108
109
A11
A9
A8
O
Address output pins
110
111
112
A13
A14
VCC
O
O
O
EPROM power supply pin
81
92
97
N.C.
—
Internally connected pins
Be sure to leave them open.
106
12
MB89160/160A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Main clock
• At an oscillation feedback resistor of approximately
X1
1 MΩ/5.0 V
• CR oscillation is selectable (MB8916X/A only).
X0
Standby control signal
B
Subclock
• At an oscillation feedback resistor of approximately
4.5 MΩ/5.0 V
X1A
X0A
Standby control signal
C
D
• At an output pull-up resistor of approximately
50 kΩ/5.0 V
R
• Hysteresis input
P-ch
N-ch
E
• CMOS I/O
• The peripheral is a hysteresis input type.
R
P-ch
P-ch
N-ch
Port
• Pull-up resistor optional
Peripheral
(Not available on the MB89PV160.)
(Continued)
13
MB89160/160A Series
(Continued)
Type
Circuit
Remarks
F
• CMOS I/O
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(Not available on the MB89PV160)
G
• CMOS output
P-ch
• P-ch output is a heavy-current drive type.
N-ch
Port
H
• N-ch open-drain I/O
• CMOS input
R
• The peripheral is a hysteresis input type.
• P21, P26, and P27 are a heavy-current drive type.
• Pull-up resistor optional
P-ch
(Not available on the MB89P165/A, MB89W165/A
and MB89PV160)
N-ch
Port
Peripheral
I
• N-ch open-drain output
• CMOS input
R
P-ch
N-ch
• Pull-up resistor optional
(Not available on the MB89P165/A, MB89W165/A
and MB89PV160)
Port
J
• N-ch open-drain output
• Pull-up resistor optional
R
(Not available on the MB89P165/A, MB89W165/A
and MB89PV160)
P-ch
• P32 and P33 are not provided with a pull-up resistor.
N-ch
(Continued)
14
MB89160/160A Series
(Continued)
Type
Circuit
Remarks
K
• LCD controller/driver segment output
P-ch
N-ch
P-ch
N-ch
L
• N-ch open-drain output
• Analog input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
Analog input
(Not available on the MB89PV160)
15
MB89160/160A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “ 1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC to VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
16
MB89160/160A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P165
The MB89P165 is an OTPROM version of the MB89160 series.
1. Features
• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.
Address
0000H
Single-chip
I/O
EPROM mode
(Corresponding addresses on the EPROM programmer)
0080H
0280H
RAM
Not available
8000H
0000H
Not available
Not available
Not available
3FF0H
Option area
3FF6H
Not available
Not available
C000H
FFFFH
4000H
PROM
16 KB
EPROM
16 KB
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P165 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating area for a single chip is 16 Kbyte (C000H to FFFFH) the PROM can be programmed as follows:
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program into the EPROM programmer at 4000H to 7FFFH.
(Note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM
mode.)
Load option data into address 3FF0H to 3FF5H of the EPROM programmer.
(For information about each corresponding option, see “8. Setting OTPROM Options.”)
(3) Program with the EPROM programmer.
17
MB89160/160A Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Adapter Socket
Package
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
Compatible adapter socket
ROM-80SQF-28DP-8L
ROM-80QF-28DP-8L3
ROM-80QF2-28DP-8L2
7. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This
dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity
of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all
filters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having
wavelengths shorter than 4000Å. Although erasure time will be much longer than with UV source at 2537Å,
nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and
exposure to them should be prevented to realize maximum system reliability. If used in such an environment,
the package windows should be covered by an opaque label or substance.
18
MB89160/160A Series
8. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming value at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
• OTPROM option bit map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vacancy
Vacancy
Vacancy
Reset pin
output
1: Yes
Clock mode Power-on
selection reset
1: Dual clock 1: Yes
Oscillation stabilization time
3FF0H
WTM1
WTM0
Readable Readable
Readable
0: No
0: Single
clock
0: No
See section “■ Mask Option.”
P07
P06
P05
P04
P03
P02
P01
P00
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
3FF1H
3FF2H
3FF3H
3FF4H
3FF5H
P17
P16
P15
P14
P13
P12
P11
P10
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
P57
P56
P55
P54
P53
P52
P51
P50
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable Readable
Vacancy Vacancy
Readable
Vacancy
Readable
Vacancy
Readable
Vacancy
Readable
Vacancy
Readable
Vacancy
Readable
Vacancy
Readable Readable
Readable
Readable
Readable
Readable
Readable
Readable
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
19
MB89160/160A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
Adapter socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Corresponding addresses on the EPROM programmer
Single chip
Address
0000H
I/O
0080H
0280H
RAM
Not available
8000H
0000H
PROM
32 KB
EPROM
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
20
MB89160/160A Series
■ BLOCK DIAGRAM
Main clock
oscillator
X0
X1
Time-base timer
Clock controller
8-bit timer/counter
P22/TO
Subclock oscillator
(32.768 KHz)
X0A
X1A
8-bit timer/counter
8-bit PWM timer 2
P20/EC
Watch prescaler timer
Reset circuit
(WDT)
P27/PWM2*4
RST
8
8
P25/SCK
P24/SO
P23/SI
External interrupt 2
(Wake-up)
P00/INT20
to P07/INT27
8-bit serial
CMOS I/O port
P21*4, P26*4
N-ch open-drain I/O port
4
4
4
4
External interrupt 1
(Wake-up)
P10/INT10
to P13/INT13
P40/SEG16*3
to P43/SEG19
N-ch open-drain output port
8
4
P14 to P17
P44/SEG20*3
to P47/SEG23
CMOS I/O port
4
4
8
P60/SEG8*3
RAM
to P63/SEG11
LCD
P64/SEG12*3
to P67/SEG15
2
controller/driver
F2MC-8L
CPU
2
P70/COM2*3,
P71/COM3
8
2
4
SEG0 to SEG7
COM0, COM1
V0 to V3
ROM
24 × 4 bits
VRAM
N-ch open-drain output port
P33/C0*2
P32/C1*2
8
8
Reference voltage
P50/AN0
to P57/AN7
1
generator and booster*
8-bit A/D converter
AVCC
AVR
AVSS
8-bit PWM timer 1
P31/PWM1
Remote control output
P30/RCO/BUZ
Buzzer output
Other pins
MOD0, MOD1, VCC, VSS
N-ch open-drain I/O port
(P30 and P31 are a CMOS
output type.)
*1: Selected by mask option
*2: Used as ports without a reference voltage generator and booster
*3: Functions selected by mask option. (For information on selecting procedure, see section “■Mask Options.”)
*4: Heavy-current drive type
21
MB89160/160A Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89160 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89160 series is structured as illustrated below.
Memory Space
MB89165/A
MB89PV160
I/O
MB89161/A
I/O
MB89163/A
I/O
MB89P165
0000H
0080H
0000H
0080H
0000H
0080H
0000H
0080H
I/O
Not available
00C0H
RAM
256 B
RAM
512 B
RAM
256 B
RAM
128 B
0100H
0100H
0140H
0100H
0180H
0100H
Register
Register
Register
Register
0200H
0280H
0200H
0280H
Not available
Not available
Not available
Not available
8000H
C000H
E000H
FFFFH
External ROM
32 KB
ROM
16 KB
F000H
FFFFH
ROM
8 KB
ROM
4 KB
FFFFH
FFFFH
22
MB89160/160A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 18-bit data processing instruction, the lower byte is used.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Undefined
Undefined
Undefined
Undefined
Undefined
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divide into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
Vacancy
Vacancy
PS
RP
Vacancy
H
IL1, 0
N
V
C
RP
CCR
23
MB89160/160A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set the shift-out value in the case of a shift instruction.
24
MB89160/160A Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 16 banks can be used on the MB89163 (RAM 256 × 8 bits), and a total of 32
banks can be used on the MB89165 (RAM 256 × 8 bits). The bank currently in use is indicated by the register
bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuraiton
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
16 banks (MB89163)
32 banks (MB89165)
Memory area
25
MB89160/160A Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Read/write
(R/W)
(W)
Register name
PDR0
Register description
Port 0 data register
DDR0
Port 0 data direction register
Port 1 data register
(R/W)
(W)
PDR1
DDR1
Port 1 data direction register
Port 2 data register
(R/W)
(W)
PDR2
DDR2
Port 2 data direction register
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
SYCC
STBC
WDTE
TBTC
WPCR
PDR3
System clock control register
Standby control register
Watchdog timer control register
Time-base timer control register
Watch prescaler control register
Port 3 data register
Vacancy
(R/W)
(R/W)
(R/W)
PDR4
PDR5
BUZR
Port 4 data register
Port 5 data register
Buzzer register
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
PDR6
PDR7
RCR1
RCR2
Port 6 data register
Port 7 data register
Remote control transmission register 1
Remote control transmission register 2
Vacancy
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
T2CR
T1CR
T2DR
T1DR
SMR
Timer 2 control register
Timer 1 control register
Timer 2 data register
Timer 1 data register
Serial mode register
Serial data register
SDR
CNTR1
COMP1
PWM 1 control register
PWM 1 compare register
(Continued)
26
MB89160/160A Series
(Continued)
Address
Read/write
(R/W)
Register name
CNTR2
Register description
PWM 2 control register
20H
21H
(W)
COMP2
PWM 2 compare register
Vacancy
22H to 2CH
2DH
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
ADC1
ADC2
ADCD
EIE1
A/D converter control register 1
A/D converter control register 2
A/D converter data register
External interrupt 1 enable register 1
External interrupt 1 flag register 1
External interrupt 2 enable register 2
External interrupt 2 flag register 2
Vacancy
2EH
2FH
30H
31H
EIF1
32H
EIE2
33H
EIF2
34H to 5FH
60H to 6BH
6CH to 71H
72H
(R/W)
(R/W)
VRAM
LCDR
Display data RAM
Vacancy
LCD controller/driver control register 1
Vacancy
73H to 7BH
7CH
(W)
(W)
ILR1
ILR2
ILR3
ITR
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt test register
7DH
7EH
(W)
Access prohibited
7FH
Note: Do not use vacancies.
27
MB89160/160A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
VSS – 0.3 VSS + 7.0
VSS – 0.3 VSS + 7.0
VSS – 0.3 VSS + 7.0
V
V
V
Power supply voltage
AVCC
AVR
AVCC must not exceed VCC + 0.3 V.
AVR must not exceed AVCC + 0.3 V.
V0 to V3 on the product without
booster must not exceed VCC.
LCD power supply voltage
V0 to V3 VSS – 0.3 VSS + 7.0
V
V
V
VI1 must not exceed VSS + 7.0 V.
All pins except P20 to P27 without
a pull-up resistor
VI1
VI2
VSS – 0.3 VCC + 0.3
VSS – 0.3 VSS + 7.0
Input voltage
P20 to P27 without a pull-up
resistor
VO1 must not exceed VSS + 7.0 V.
All pins except P20 to P27, P32,
P33, P40 to P47, and P60 to P67
without a pull-up resistor
VO1
VSS – 0.3 VCC + 0.3
V
V
Output voltage
P20 to P27, P32, P33, P40 to P47,
and P60 to P67 without a pull-up
resistor
VO2
VSS – 0.3 VSS + 7.0
IOL1
10
20
mA All pins except P21, P26, and P27
mA P21, P26, and P27
“L” level maximum output current
IOL2
All pins except P21, P26, P27, and
power supply pins
Average value (operating current ×
operating rate)
IOLAV1
4
8
mA
“L” level average output current
“L” level total maximum output current
P21, P26, and P27
mA Average value (operating current ×
operating rate)
IOLAV2
ΣIOL
100
40
mA Peak value
Average value (operating current ×
“L” level total average output current ΣIOLAV
mA
operating rate)
All pins except P30, P31, and
power supply pins
IOH1
–5
mA
“H” level maximum output current
IOH2
–10
mA P30 and P31
(Continued)
28
MB89160/160A Series
(Continued)
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
All pins except P30, P31, and
power supply pins
Average value (operating current ×
operating rate)
IOHAV1
—
–2
mA
“H” level average output current
P30 and P31
mA Average value (operating current ×
IOHAV2
—
–4
operating rate)
“H” level total maximum output current
“H” level total average output current
ΣIOH
—
—
–50
–10
mA Peak value
Average value (operating current ×
ΣIOHAV
mA
operating rate)
Power consumption
Operating temperature
Storage temperature
PD
—
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
Precautions: Parmanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func-
tional operation should be restricted to the conditions as detailed in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
2.2*1
2.2*1
Max.
6.0*1
4.0
Normal operation assurance range*1
Dual-clock mask ROM products
V
V
VCC
AVCC
Normal operation assurance range for
MB89P165/A and MB89W165/A
Power supply voltage
2.7
6.0
V
1.5
2.0
6.0
V
V
Retains the RAM state in stop mode
Normal operation assurance range
AVR
AVCC
V0 to V3 pins on the products without a
booster
LCD power supply range
(The optimum value dependent on the
LCD element in use.)
LCD power supply voltage V0 to V3
VSS
VCC
V
EPROM program power
VPP
—
VSS + 13.0
+85
V
MOD1 pin of the MB89P165
supply voltage
Operating temperature
TA
–40
°C
*1: The minimum operating power supply voltage varies with the execution time (instruction cycle time) setting for
the operating frequency.
A/D converter assurance accuracy varies with the operating power supply voltage.
*2: P32 and P33 are applicable only for procucts of the MB89160 series (without “A” suffix).
P40 to P47 and P60 to P67 are applicable when selected as ports.
29
MB89160/160A Series
6
5
Analog accurancy
assured in the AVCC
= VCC = 3.5 V to 6.0 V
range
Operation assurance range
4
3
2
1
(MHz)
1
2
3
4
Main clock operating frequency
(µs)
4.0
2.0
1.0
Minimum execution time (instruction cycle)
Note: The shaded area is assured only for the MB8916X/A.
Figure 1 Operating Voltage vs. Main Clock Operating Frequency
(Single-clock MB8916X/A and MB89P165/PV160)
30
MB89160/160A Series
6
5
4
3
2
1
Analog accurancy
assured in the
AVCC = VCC = 3.5 V
to 6.0 V range
Operation assurance range
(MHz)
1
2
3
4
Main clock operating frequency
(µs)
4.0
2.0
1.0
Minimum execution time (instruction cycle)
Figure 2 Operating Voltage vs. Main Clock Operating Frequency (Dual-clock MB8916X/A)
Figures 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
31
MB89160/160A Series
3. DC Characteristics
(1) Pin DC characteristics (VCC = +5.0 V)
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
Symbol
Parameter
Pin
Condition
Unit
Remarks
Min.
Max.
P00 to P07,
P10 to P17,
P20 to P27
VIH
0.7 VCC
VCC + 0.3
V
“H” level input
voltage
RST,
MOD0, MOD1,
EC, SI, SCK,
INT10 to INT13,
INT20 to INT27
VIHS
0.8 VCC
VSS − 0.3
VSS − 0.3
VCC + 0.3
0.3 VCC
0.2 VCC
V
V
V
P00 to P07,
P10 to P17,
P20 to P27
VIL
“L” level input
voltage
RST,
MOD0, MOD1,
EC, SI, SCK,
INT10 to INT13,
INT20 to INT27
VILS
P20 to P27,
P33, P32,
P40 to P47,
P60 to P67
P20toP27, P40to
P47, and P60 to
P67 without pull-
up resistor only
Open-drain
output pin
application
voltage
VSS − 0.3
VSS + 6.0*2
VCC + 0.3
V
VD1
VSS − 0.3
2.4
VD2
P50 to P57
V
V
V
P00 to P07,
P10 to P17
VOH1
VOH2
IOH = –2.0 mA
IOH = –6.0 mA
“H” level output
voltage
P30, P31
4.0
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P33,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P71
VOL
IOL = 1.8 mA
0.4
V
“L” level output
voltage
VOL2
VOL3
P21, P26, P27
RST
IOL = 8.0 mA
IOL = 4.0 mA
0.4
0.6
V
V
P00 to P07,
P10 to P17,
MOD0, MOD1,
P30, P31
Input leakage
current (Hi-z output
leakage current)
Without pull-
up resistor
ILI1
0.45 V < VI < VCC
±5
µA
(Continued)
32
MB89160/160A Series
(Continued)
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin
Condition
Unit
Remarks
Min.
Typ.
Max.
P20 to P27,
P32, P33,
P40 to P47,
P60 to P67,
P70, P71
Without pull-
up resistor
0.45 V < VI < 6.0 V
0.45 V < VI < VCC
ILO1
—
—
±1
µA
µA
Open-drain
output leakage
current
Without pull-
up resistor
ILO2
P50 to P57
—
—
±1
P00 to P07,
P10 to P17,
P20 to P27,
Pull-up
resistance
With pull-up
resistor
RPULL P40 to P47,
P50 to P57,
P60 to P67,
RST
VI = 0.0 V
25
50
100
kΩ
Common output
impedance
RVCOM COM0 to COM3
RVSEG SEG0 to SEG24
—
—
—
—
2.5
15
kΩ
kΩ
V1 to V3 = +5.0 V
Segment output
impedance
Products
without
a booster only
LCD divided
resistance
Between VCC and V0
RLCD
—
300
—
500
—
750
kΩ
µA
V0 to V3,
COM0 to COM3,
SEG0 to SEG23
LCD controller/driver
leakage current
ILCDL
—
±1
VOV3
VOV2
V3
V2
4.3
2.9
4.5
3.0
4.7
3.1
V
V
Booster for LCD
driving output voltage
V1 = 1.5 V
Products with
a booster only
Reference output
voltage for LCD
driving
VOV1
V1
IIN = 0 µA
1.27
1.5
1.73
V
Reference voltage
input impedance
Procucts with
a booster only
RRIN
V1
—
600
—
1000
10
1400
—
kΩ
Other than
VCC, VSS
Input capacitance CIN
f = 1 MHz
pF
Note: For pins which serve as the segment (SEG8 to SEG24) and ports (P40 to P47, P50 to P57, and P60 to P67),
see the port parameter when these pins are used as ports and the segment parameter when they are used
as segments. P32 and P33 are applicable only for products of the MB89160 series (without “A” suffix).
Applicable as external capacitor connection pins for products of the MB89160A series (with “A” suffix).
33
MB89160/160A Series
(2) Pin DC Characteristics (VCC = +3.0 V)
(VCC = 3.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin
Condition
Unit
Remarks
Min.
2.4
Typ.
Max.
—
P00 to P07,
P10 to P17
VOH1
VOH2
IOH = –1.0 mA
IOH = –3.0 mA
—
V
V
“H” level output
voltage
P30, P31
2.4
—
—
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P33,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P71
VOL
IOL = 1.8 mA
—
—
0.4
V
“L” level output
voltage
VOL2
VOL3
RST
IOL = 1.8 mA
—
—
—
—
0.4
0.4
V
V
P21, P26, P27 IOL = 3.6 mA
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57,
P60 to P67,
RST
Pull-up
resistance
With pull-up
resistor
RPULL
VI = 0.0 V
50
100
150
kΩ
34
MB89160/160A Series
(3) Power Supply Current Characteristics (MB8916X)
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Parameter
Pin
Condition
Unit
Remarks
Min. Typ. Max.
MB8916X/A,
MB89PV160
FCH = 4.2 MHz, VCC = 5.0 V
tinst*2 = 4/FCH
Main clock operation mode
—
—
—
—
—
—
5.0
8.0
1.5
2.4
0.05
1.0
10.0 mA
ICC1
15.0 mA MB89PV165
MB8916X/A,
MB89PV160
FCH = 4.2 MHz, VCC = 3.0 V
tinst*2 = 64/FCH
Main clock operation mode
2.0
2.8
0.1
3.0
mA
ICC2
mA MB89P165
MB8916X/A,
mA
FCL = 32.768 kHz, VCC = 3.0 V
tinst*2 = 2/FCL
Subclock operation mode
MB89PV160
ICCL
mA MB89PV165
FCH = 4.2 MHz, VCC = 5.0 V
tinst*2 = 4/FCH
Main clock sleep mode
ICCS1
ICCS2
ICCSL
ICCT
—
—
—
—
2.5
1.0
25
5.0
1.5
50
mA
FCH = 4.2 MHz, VCC = 3.0 V
tinst*2 = 64/FCH
Main clock sleep mode
MB8916X/A,
mA MB89PV160,
MB89PV165
VCC
Power supply
current*1
FCL = 32.768 kHz, VCC = 3.0 V
tinst*2 = 2/FCL
Subclock sleep mode
µA
MB8916X,
MB89P165-1XX,
MB89PV160
FCL = 32.768 kHz, VCC = 3.0 V
Watch mode
10
15
µA
µA
FCL = 32.768 kHz, VCC = 3.0 V
• Watch mode
• During reference voltage
generator and booster operation
MB8916XA,
MB89P165-2XX
ICCT2
—
250
400
—
—
0.1
0.1
1.0
10
µA MB8916X
MB89PV160,
TA = +25°C, VCC = 5.0 V
Stop mode
ICCH
µA
MB89P165-1XX
When A/D
mA conversion is
activated
IA
AVCC
FCH = 4.2 MHz, VCC = 5.0 V
—
1.0
3.0
*1: The power supply current is measured at the external clock, open output pins, and the external LCD dividing
resistor (or external input for the reference voltage). In the case of the MB89PV160, the current consumed by
the connected EPROM and ICE is not included.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
35
MB89160/160A Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V ±10 %, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min.
Max.
—
RST “L” pulse width
RST “H” pulse width
tZLZH
tZHZL
48 tXCYL
24 tXCYL
ns
ns
—
—
tZLZH
tZHZL
R S T
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Min.
Max.
Power-on reset
function only
Power supply rising time
Power supply cut-off time
tR
—
—
—
50
ms
ms
Due to repeated
operations
tOFF
1
—
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage
needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
2.0 V
0.2 V
0.2 V
0.2 V
V
CC
36
MB89160/160A Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
FCH
Pin
X0, X1
Unit
Remarks
Min.
1
Typ.
—
Max.
4.2
MHz Main clock
kHz Subclock
Clock frequency
FCL
X0A, X1A
X0, X1
—
32.768
—
—
tHCYL
tLCYL
238
—
1000
—
ns
Main clock
Subclock
Clock cycle time
X0A, X1A
30.5
µs
PWH
PWL
Input clock pulse width
X0
X0
20
—
—
—
—
ns
ns
External clock
Input clock rising/falling
time
tCR
tCF
24
Main Clock Timing and Conditions
t
HCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
t
CR
t
CF
Main Clock Conditions
When a crystal
or
ceramic resonator is used
When the CR
oscillation option is used
When an external clock is used
X0
X1
X0
X1
X0
X1
Open
FCH
C1
FCH
FCH
R
C0
C
37
MB89160/160A Series
Subclock Timing and Conditions
t
LCYL
0.8 VCC
X0A
Subclock Conditions
When a crystal
or
ceramic oscillator is used
When the single-clock option is used
X0A
X1A
X0A
X1A
FCL
Rd
Open
C0
C1
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
µs
Remarks
4/FCH, 8/FCH, 16/FCH,
64/FCH
(4/FCH) tinst = 1.0 µs at FCH = 4 MHz
tinst = 62 µs at FCL = 32.768 kHz
Instruction cycle
(minimum execution time)
tinst
2/FCL
µs
38
MB89160/160A Series
(5) Serial I/O Timing
Parameter
(VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
SCK
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
200
—
Internal clock
operation
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External
SCK, SO clock
200
—
operation
Valid SI → SCK ↑
SI, SCK
SCK, SI
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Clock Operation
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SO
2.4 V
0.8 V
tIVSH
tSHIX
SI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
External Clock Operation
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO
SI
2.4 V
0.8 V
tIVSH
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
39
MB89160/160A Series
(6) Peripheral Input Timing
(VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Unit
Remarks
Parameter
Min.
1 tinst*
1 tinst*
2 tinst*
2 tinst*
Max.
—
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
Peripheral input “H” pulse width 2
Peripheral input “L” pulse width 2
tILIH1
tIHIL1
tILIH2
tIHIL2
µs
µs
µs
µs
INT10 to INT13, EC
INT20 to INT27
—
—
—
* : For information on tinst, see “(4) Instruction Cycle.”
t IHIL1
t ILIH1
INT10 to 13,
EC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t IHIL2
t ILIH2
INT20 to 27
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
40
MB89160/160A Series
5. A/D Converter Electrical Characteristics
(3 MHz, AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Resolution
Symbol
Pin
Condition
Unit Remarks
Min.
—
Typ.
—
Max.
8
—
bit
Total error
—
—
±1.5
±1.0
±0.9
LSB
LSB
LSB
mV
—
Linearity error
—
—
Differential linearity error
Zero transition voltage
—
—
AVR = AVCC
AVSS – 1.0 LSB AVSS + 0.5 LSB AVSS + 2.0 LSB
VOT
—
Full-scale transition
voltage
AVR – 3.0 LSB AVR – 1.5 LSB
VFST
AVR
mV
Interchannel disparity
—
—
—
0.5
—
LSB
A/D mode conversion time
44 tinst
µs
—
Sense mode
conversion time
—
12 tinst
—
µs
—
Analog port input current
Analog input voltage
Reference voltage
IAI
—
—
—
—
10
µA
V
AN0 to
AN7
—
—
0.0
2.0
AVR
AVCC
V
AVR = 5.0 V,
when A/D
conversion
is activated
IR
—
—
100
—
—
1
µA
µA
AVR
Reference voltage
supply current
AVR = 5.0 V,
when A/D
conversion
is stopped
IRH
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 8, analog voltage can be divided into 28=256.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
41
MB89160/160A Series
Digital output
AVR
256
1111 1111
1111 1110
Actual conversion value
1 LSB =
•
•
•
Theoretical conversion value
VNT − (1 LSB × N + VOT)
Linearity error =
1 LSB
•
•
•
V(N+1)T − VNT
− 1
(1 LSB × N + VOT)
Defferential linearity error =
1 LSB
•
•
•
•
VNT − (1 LSB × N + 1 LSB)
Total error =
1 LSB
Linearity error
•
0000 0010
0000 0001
0000 0000
VOT
VNT V(N + 1)T
VFST
Analog input
(2) Precautions
• Input impedance of analog input pins
The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the
sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Analog Input Equivalent Circuit
Sample hold circuit
.
C = 33 pF
.
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R = 6 kΩ
.
Close for 8 instruction cycles after
activating A/D conversion.
Analog channel selector
• Error
The smaller the |AVR – AVSS|, the greater the error would become relatively.
42
MB89160/160A Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
VOL1 vs. IOL
VOL2 vs. IOL
VOL1 (V)
VCC = 2.5 V
VOL2 (V)
VCC = 3.0 V
VCC = 2.5 V
VCC = 2.0 V
VCC = 2.0 V
VCC = 3.0 V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC = 4.0 V
TA = +25°C
TA = +25°C
VCC = 5.0 V
VCC = 6.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0
2
4
6
8
10 12 14 16 18 20
IOL (mA)
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(2) “H” Level Output Voltage
VCC – VOH1 vs. IOH
VCC – VOH1 (V)
VCC – VOH2 vs. IOH
VCC = 2.5 V VCC = 3.0 V
VCC – VOH2 (V)
1.0
VCC = 2.5 V VCC = 3.0 V
VCC = 2.0 V
VCC = 2.0 V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = +25°C
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCC = 4.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
VCC = 5.0 V
VCC = 6.0 V
0
–1
–2
–3
–4
–5
IOH (mA)
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
IOH (mA)
43
MB89160/160A Series
(3) “H” Level Input Voltage/“L” level Input Voltage
CMOS input
CMOS hysteresis input
VIN (V)
VIN (V)
5.0
5.0
TA = +25°C
TA = +25°C
4.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VIHS
VILS
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(4) Power Supply Current (External Clock)
ICC1 vs. VCC (Mask ROM products)
ICC2 vs. VCC (Mask ROM products)
ICC2 (mA)
ICC1 (mA)
7
TA = +25°C
TA = +25°C
6
FCH = 4.2 MHz
2.0
5
4
3
2
FCH = 4.2 MHz
FCH = 3 MHz
FCH = 3 MHz
1.0
FCH = 1 MHz
FCH = 1 MHz
1
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
(Continued)
44
MB89160/160A Series
ICC2S vs. VCC (Mask ROM products)
ICC1S vs.VCC (Mask ROM products)
ICC2S (mA)
ICC1S (mA)
3.0
TA = +25°C
TA = +25°C
FCH = 4.2 MHz
2.0
1.0
0
FCH = 3 MHz
FCH = 4.2 MHz
FCH = 3 MHz
2.0
1.0
FCH = 1 MHz
FCH = 1 MHz
0
1
1
2
3
4
5
6
7
2
3
4
5
6
7
VCC (V)
VCC (V)
ICCT vs. VCC
ICCL vs. VCC (Mask ROM products)
ICCL (µA)
ICCT (µA)
30
200
TA = +25°C
TA = +25°C
180
160
140
120
100
80
25
20
15
10
5
FCL = 32.768 kHz
FCL = 32.768 kHz
60
40
20
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
VCC (V)
VCC (V)
(Continued)
45
MB89160/160A Series
(Continued)
ICCT2 vs. VCC
ICCSL vs. VCC
ICCSL (µA)
ICCT2 (µA)
1,000
200
TA = +25°C
TA = +25°C
180
900
800
700
600
500
400
300
200
100
160
140
120
100
FCL = 32.768 kHz
FCL = 32.768 kHz
80
60
40
20
0
0
1
1
2
3
4
5
6
7
2
3
4
5
6
7
VCC (V)
VCC (V)
IR vs. AVR
IA vs. AVCC
IR (µA)
200
IA (mA)
5.0
TA = +25°C
FCH = 4 MHz
TA = +25°C
180
160
4.5
4.0
140
120
3.5
3.0
100
80
2.5
2.0
60
40
1.5
1.0
20
0
1.5
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
AVR (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
AVCC (V)
(5) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
50
TA = +85°C
TA = +25°C
TA = –40°C
10
1
2
3
4
5
6
7
VCC (V)
46
MB89160/160A Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation for instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir: b
rel
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
AH
AL
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
T
TH
TL
IX
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
(Continued)
47
MB89160/160A Series
(Continued)
Symbol
Meaning
EP
PC
SP
PS
dr
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
CCR
RP
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
( × )
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
~:
Assembler notation of an instruction
Number of instructions
Number of bytes
#:
Operation:
TL, TH, AH:
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
48
MB89160/160A Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
–
–
–
–
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
49
MB89160/160A Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
C
A
←
←
C
A
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
50
MB89160/160A Series
(Continued)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
51
MB89160/160A Series
■ INSTRUCTION MAP
52
MB89160/160A Series
■ MASK OPTIONS
Part number
MB89161/3/5
MB89P165
MB89PV160
Specify when
ordering masking
Set with EPROM
programmer
Specifying procedure
Setting not possible
Slectable per pin
Pull-up resistors (SEG)
P00 to P07, P10 to P17,
P20 to P27, P40 to P47,
P50 to P57, P60 to P67
Can be set per pin
(P20 to P27, P40 to
P47, and P60 to P67
are available only for
without a pull-up
resistor.)
(The pull-up resistors for
P40 to P47 and P60 to
P67 are only selectable
when these pins are not
set as segment outputs.
When the A/D is used,
P50 to P57 are must not
selected.)
Fixed to without
pull-up resistor
Power-on reset (POR)
With power-on reset
Without power-on reset
Fixed to with power-on
reset
Selectable
Selectable
Selection of oscillation stabilization
time (OSC)
Selectable
OSC
0
1
2
3
Selectable
WTM1 WTM0
• The initial value of the oscillation
stabilization time for the main clock
can be set by selecting the values of
the WTM1 and WTM0 bits on the
right.
Fixed to oscillation
stabilization time of
216/FCH
: 22/FCH
: 212/FCH
: 216/FCH
: 218/FCH
0
0
1
1
0
1
0
1
: 22/FCH
: 212/FCH
: 216/FCH
: 218/FCH
Main clock oscillation type (XSL)
Crystal or ceramic resonator
CR
Fixed to crystal or
ceramic
Selectable
Selectable
Selectable
Crystal or ceramic only
Selectable
Reset pin output (RST)
With reset output
Fixed to with reset
output
Without reset output
Clock mode selection (CLK)
Dual-clock mode
Fixed to dual-clock
mode
Selectable
Single-clock mode
53
MB89160/160A Series
• Segment Options
Part number
MB89161/3/5
MB89P165
MB89PV160
No.
Specify when
ordering masking
Select by version
number
Select by version
number
Specifying procedure
7
Specify by the option
combinations listed
below
LCD output pin configuration
choices
SEG = 4:
Specify as SEG = 4
–101 : SEG 24 pins
–201 COM 4 pins
–101 : SEG 24 pins
COM 4 pins
P40 to P47 segment output
P60 to P67 segment output
P70, P71 common output
SEG = 3:
Specify as SEG = 3
–102 : SEG 20 pins
–202 COM 4 pins
–102 : SEG 20 pins
COM 4 pins
P40 to P43 segment output
P44 to P47 port output
P60 to P67 segment output
P70, P71 common output
SEG = 2:
Specify as SEG = 2
Specify as SEG = 1
–103 : SEG 16 pins
–203 COM 4 pins
–103 : SEG 16 pins
COM 4 pins
P40 to P47 port output
P60 to P67 segment output
P70, P71 common output
SEG = 1:
–104 : SEG 12 pins
COM 2 pins
–104 : SEG 12 pins
COM 2 pins
P40 to P47 port output
P60 to P63 segment output
P64 to P67 port output
P70, P71 port output
SEG = 0:
Specify as SEG = 0
–105 : SEG 8 pins
COM 2 pins
–105 : SEG 8 pins
COM 2 pins
P40 to P47 port output
P60 to P67 port output
P70, P71 port output
■ VERSIONS
Version
Features
Mass production
product
One-time PROM
product
Piggyback/evaluation Number of segment
Booster
product
pins
MB89P165-201
-202
24 (4 commons)
20 (4 commons)
16 (4 commons)
MB89160A series
—
Yes
-203
MB89P165-101
MB89PV160-101
24 (4 commons)
20 (4 commons)
16 (4 commons)
12 (2 commons)
8 (2 commons)
-102
-103
-104
-105
-102
-103
-104
-105
MB89160 series
No
54
MB89160/160A Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89161-PFV
MB89161A-PFV
MB89163-PFV
MB89163A-PFV
MB89165-PFV
80-pin Plastic SQFP
(FPT-80P-M05)
MB89165A-PFV
MB89P165-×××-PFV
MB89161-PF
MB89161A-PF
MB89163-PF
MB89163A-PF
MB89165-PF
80-pin Plastic QFP
(FPT-80P-M06)
MB89165A-PF
MB89P165-×××-PF
MB89161-PFS
MB89161A-PFS
MB89163-PFS
MB89163A-PFS
MB89165-PFS
80-pin Plastic QFP
(FPT-80P-M11)
MB89165A-PFS
MB89P165-×××-PFS
80-pin Ceramic QFP
(FPT-80C-A02)
MB89W165-×××-PF
MB89PV160-×××-PF
80-pin Ceramic MQFP
(MQP-80C-P01)
Note: For information on ×××, see section “■ Versions.”
55
MB89160/160A Series
■ PACKAGE DIMENSIONS
80-pin plastic LQFP
(FPT-80P-M05)
14.00±0.20(.551±.008)SQ
1.50 –+00..1200
.059 +–..000048
(Mounting height)
12.00±0.10(.472±.004)SQ
60
41
61
40
13.00
(.512)
NOM
9.50
(.374)
REF
INDEX
80
21
1
20
LEAD No.
Details of "A" part
"A"
0.50±0.08
(.0197±.0031)
0.18 –+00..0038
.007 +–..000013
0.127 +–00..0025
.005 +–..000012
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0
10°
Dimensions in mm (inches).
C
1995 FUJITSU LIMITED F80008S-2C-5
80-pin plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
64
41
65
40
12.00(.472)
16.30±0.40
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
REF
(.642±.016)
INDEX
80
25
"A"
1
24
LEAD No.
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.16(.006)
Details of "A" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10°
0.18(.007)MAX
0.58(.023)MAX
18.40(.724)REF
0.80±0.20
(.031±.008)
22.30±0.40(.878±.016)
Dimensions in mm (inches).
C
1994 FUJITSU LIMITED F80010S-3C-2
56
MB89160/160A Series
80-pin plastic LQFP
(FPT-80P-M11)
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
1.50 –+00..1200
(Mounting height)
.059 +–..000048
60
61
41
40
15.00
(.591)
NOM
12.35
(.486)
REF
1 PIN INDEX
80
21
1
Details of "A" part
0.10±0.10
LEAD No.
"A"
0.127 +–00..0025
.005 +–..000012
20
(STAND OFF)
0.65(.0256)TYP
0.30±0.10
(.012±.004)
M
(.004±.004)
0.13(.005)
0.50±0.20
(.020±.008)
0.10(.004)
0
10°
Dimensions in mm (inches).
C
1995 FUJITSU LIMITED F80016S-1C-3
80-pin ceramic QFP
(FPT-80C-A02)
0.51(.020) TYP
17.91(.705)
TYP
12.00(.472)
REF
16.31(.642)
TYP
8.50(.335)TYP
16.00(.630)
14.00±0.25
(.551±.010)
TYP
INDEX AREA
0.80±0.10
0.35 +–00..0078
0.80±0.10
0.15±0.05
(.0315±.0040)
(.014±.003)
(.0315±.0040)
(.006±.002)
18.40(.725) REF
1.60(.063) TYP
20.00±0.25
(.787±.010)
4.45(.175)MAX
23.90(.941) TYP
22.00(.866) TYP
22.30(.878) TYP
0.80(.0315) TYP
Dimensions in mm (inches).
C
1994 FUJITSU LIMITED F80014SC-1-2
57
MB89160/160A Series
(Continued)
80-pin ceramic MQFP
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
1.50(.059)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.00(.040)TYP
0.80±0.25
(.0315±.010)
INDEX AREA
1.20 –+00..2400
4.50(.177)
TYP
.047 –+..000186
0.80±0.25
(.0315±.010)
1.27±0.13
(.050±.005)
INDEX AREA
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.40(.724)
REF
10.16(.400)
TYP
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
INDEX
6.00(.236)
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
0.40±0.10
(.016±.004)
1.20 –+00..2400
.047 –+..000186
1.50(.059)
TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
1.00(.040)
TYP
0.15±0.05 8.70(.343)
(.006±.002) MAX
Dimensions in mm (inches).
C
1994 FUJITSU LIMITED M80001SC-4-2
58
MB89160/160A Series
FUJITSU LIMITED
For further information please contact:
Japan
All Rights Reserved.
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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The information and circuit diagrams in this document are
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are requested to consult with FUJITSU sales representatives before
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You must protect against injury, damage or loss from such failures
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over-current levels and other abnormal operating conditions.
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If any products described in this document represent goods or
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F0004
FUJITSU LIMITED Printed in Japan
59
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