MB89567HC [FUJITSU]
8-bit Proprietary Microcontroller CMOS; 8位微控制器的专有CMOS
| 型号： | MB89567HC |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontroller CMOS |
| 文件： | 总52页 (文件大小：990K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89560H Series
MB89567H/567HC/P568/PV560
■ DESCRIPTION
The MB89560H series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as
I2C interface, timers, 2 ch PWM timers, 8/16-bit timer, 21bit timebase timer, 8 bit PWC timer , 17-bit Watch
prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster),
Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8L family CPU core
• Low-voltage operation (when an A/D converter is not used)
• Low current consumption (applicable to the dual-clock system)
• Minimum execution time: 0.32 µs at 12.5 MHz
• I2C interface circuit
• LCD controller/driver : 24 segments x 4 commons (max. 96 pixels, duty LCD mode and Static LCD mode)
• LCD booster function (option)
• Wild register (max. 6 different address locations)
• 10-bit A/D converter: 8 channels
(Continued)
■ PACKAGE
80-pin Plastic QFP
80-pin Plastic LQFP
80-pin Plastic LQFP
80-pin Ceramic MQFP
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
MB89560H Series
(Continued)
• Three types of Serial Interface:
High Speed UART (Transfer rate from 300 to 192000 bps /10 MHz main clock)
8-bit Serial I/O (SIO)
UART/SIO
• Two type of Programmable Pulse Generator(PPG) : 6-bit PPG and 12-bit PPG
• Six types of timer
8 bit PWM 2 channels timers
8/16 bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel)
21bit timebase timer
8 bit PWC timer operation
Watch prescaler(17 bits)
Watch-dog timer
• I/O ports: max. 50 channels
• External interrupt 1: 8 channels
• External interrupt 2 (wake-up function): 4 channels
• Low-power consumption modes (stop mode, sleep mode, and watch mode)
• LQFP-80 and QFP-80 package
• CMOS technology
■ PRODUCT LINEUP
Part number
MB89567H
MB89567HC
MB89P568
MB89PV560
Parameter
Classification
Mass production products
(mask ROM products)
OTP
Piggy-back
ROM size
32 K × 8 bits
(internal mask ROM)
48 K × 8 bits
(internal PROM)
56 K × 8 bits
(external ROM)
RAM size
1K × 8 bits
1K × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Minimum interrupt processing time:
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, 16 bits
: 0.4 µs/10 MHz
: 3.6 µs/10 MHz
General-purpose I/O ports (N-channel open drain) : 20 pins (2 shared with I2C inputs, 16 shared
with LCD, 2 shared with other resources)
Ports
General-purpose I/O ports (CMOS)
Total
: 30 pins (shared with resources)
: 50 pins
21 bits
21-bit timebase
timer
Interrupt cycle: 211, 213, 216 or 220 tinst *5
Reset generate cycle: min. 220 tinst for main clock, min. 213 tinst for sub clock
Watchdog timer
17 bits
Watch prescaler
Interrupt cycle: 0.50s, 1.00s, 2.00s, 4.00s/32.768 KHz for subclock
Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its own
independent operating clock cycle), or as one 16-bit timer/counter
In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and
square wave output capable
8/16-bit timer/
counter
8-bit interval timer operation (square wave output capable, operating clock cycle: 1, 8, 16, 64 tinst)
8-bit resolution PWM operation (conversion cycle: 256 to 256 x 64 tinst)
8/16-bit timer/counter output for counter clock selectability
8-bit PWM 2 ch
timer
2
MB89560H Series
Part number
Parameter
MB89567H
MB89567HC
MB89P568
MB89PV560
8-bit timer operation (count clock cycle: 1, 4, 32 tinst)
8-bit reload timer operation (toggle output possible, operating clock cycle: 1 - 32 tinst)
8-bit pulse width measurement (continuous measurement possible: High and Low widths, H to H, L
to L, period & H at same time and High & rising to rising)
PWC timer
10-bit resolution × 8 channels
A/D conversion function (conversion time: 60 tinst)
Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable.
10-bit A/D con-
verter*2
Internal 6-bit counter
Pulse width and cycle are program selectable
6 bit PPG
Internal 12-bit counter
Pulse width and cycle are program selectable
12 bit PPG
I2C interface*4
1 channel
Not
Available
Use a 2-wire protocol to communicate with other device
Transfer data length: 4, 6, 7, 8 bits
High speed UART Transfer rate (300 to 192000 bps /10 MHz main clock)
support sub-clock mode
Transfer data length: 7, 8 bits for UART, 8 bits for SIO
UART/SIO
Transfer rate (1201 to 78125 bps / 10 MHz main clock)
support sub-clock mode
8 bits, LSB first/MSB first selectability
8-bit serial I/O
One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks:
2, 8, 32 tinst)
Common output: 4 (max.)
Segment output: 24 (max.)
LCD driving power (bias) pins: 4
LCD display RAM size: 12 bytes (24 × 4 bits, max. 96 pixels)
Duty LCD mode and Static LCD mode
Booster for LCD driving: option
LCD
Dividing resister for LCD driving: Built-in*1
Maximum of 6-byte data can be assigned in 6 different address.
Wild register
Used to replace any data in the ROM when specific address and data are assigned in Wild register.
Wild register can be set up by using different communication methods through the device.
8 independent channels (interrupt vector, request flag, request output enable)
Edge selectability (rising/falling)
Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.)
External interrupt 1
(wake-up function)
External interrupt 2 4 channels (“L” level interrupts, independent input enable).
(wake-up function) Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop mode.)
Sleep mode, stop mode and clock mode
Standby mode
Process
CMOS
2.7 to 5.5 V*3
Operating voltage*
3.5 V to 5.5 V
3.5 V to 5.5 V
2.7 to 5.5 V
* :Varies with conditions such as the operating frequency. (See “■ Electrical Characteristics.”)
*1 : When booster is used, the bias is reduced by 1/3. it can be selected by mask option.
*2 : When the A/D converter is used, operating voltage must be 3.5V to 5.5V.
*3 : Use MBM27C512-20 as the external ROM (operating voltage: 4.5 V to 5.5 V)
*4 : I2C is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I2C specification.
*5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock if main
clock mode is selected , or 1/2 of the subclock if subclock mode is selected
3
MB89560H Series
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89567H
MB89567HC
MB89P568-101
MB89P568-102
MB89PV560-101
MB89PV560-102
Package
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
MQP-80C-P01
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually
be used. Take particular care on the following points:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket.
• When operating at low speed, the current consumed by the one-time PROM product is greater than for the mask ROM
product. However, the current consumption is roughly the same in sleep or stop mode.
• (For more information, see “■ Electrical Characteristics.”)
3. Mask Options
The functions available as options and the method of specifying options differ between products.
Before using options check “■ Mask Options.”
4. Functionalities different between products in MB89560H series
Functionalities
MB89567H
MB89567HC
MB89P568
MB89PV560
Regulator stab. time +
Regulator recovery. time +
Osc. stab. time
Regulator stab. time +
Osc. stab. time
Power-on reset wait time
Wait time for
external reset in stop/sub/clock mode
or
wait time for external interrupt trigger
recover from main stop mode
Osc. stab. time
Regulator recovery time +
Osc. stab. time
Osc. stab. time
Port pin pullup resistors
AD conversion time
Selectable by software.
Not available.
60 tINST *
33 tINST *
Not available when
ICCR:DMBP bit is
asserted.
Always available independent of
ICCR:DMBP bit selection.
I2C noise cancelling circuit
—
Note: For more information on tINST see “■ Electrical Characteristics (4) Instruction cycles"
* : Instruction cycle
4
MB89560H Series
■ PIN ASSIGNMENT
(Top view)
SEG07
1
2
3
4
5
6
7
8
P44/UCK/SCK1
P43/PWM2/PPG2
P42/PWM1/EC1
P41/HCK/TO12
P40/WTO/TO11
P31/SDA
P30/SCL
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P50/SEG08
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
Vss
P63/SEG19
P64/SEG20
P65/SEG21
P64/SEG22
P67/SEG23
AVR
Vcc
9
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/SCK
P21/SO
P20/SI
X1
X0
MODA
10
11
12
13
14
15
16
17
18
19
20
AVcc
X1A
(FPT-80P-M05)
(FPT-80P-M11)
5
MB89560H Series
(Top view)
SEG05
SEG06
SEG07
1
2
3
4
5
6
7
P46/UI/SI1
P45/UO/SO1
P44/UCK/SCK1
P43/PWM/PPG2
P42/PWM1/EC1
P41/HCK/TO12
P40/WTO/TO11
P31/SDA
P30/SCL
Vcc
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/SCK
P21/SO
P20/SI
X1
X0
MODA
X1A
X0A
RST
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P50/SEG08
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
Vss
P63/SEG19
P64/SEG20
P65/SEG21
P66/SEG22
P67/SEG23
AVR
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVcc
P07/AN7
P06/AN6
FPT-80P-M06
6
MB89560H Series
(Top view)
SEG05
SEG06
SEG07
1
2
3
4
5
6
7
P46/UI/SI1
P45/UO/SO1
P44/UCK/SCK1
P43/PWM/PPG2
P42/PWM1/EC1
P41/HCK/TO12
P40/WTO/TO11
P31/SDA
P30/SCL
Vcc
P27/INT23
P26/INT22
P25/INT21
P24/INT20
P23/PPG1
P22/SCK
P21/SO
P20/SI
X1
X0
MODA
X1A
X0A
RST
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P50/SEG08
P51/SEG09
P52/SEG10
P53/SEG11
P54/SEG12
P55/SEG13
P56/SEG14
P57/SEG15
P60/SEG16
P61/SEG17
P62/SEG18
Vss
P63/SEG19
P64/SEG20
P65/SEG21
P66/SEG22
P67/SEG23
AVR
*1
8
9
93
101
102
103
104
105
106
107
108
109
92
91
90
89
88
87
86
85
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVcc
P07/AN7
P06/AN6
(MQP-80C-P01)
*1 :Pin assignment on package top (MB89PV560 only)
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
81
82
83
84
85
86
87
88
N.C.
A15
A12
AD7
AD6
AD5
AD4
AD3
89
90
91
92
93
94
95
96
AD2
AD1
AD0
N.C.
O1
97
98
N.C.
04
105
106
107
108
109
110
111
112
OE
N.C.
A11
A9
99
O5
O6
07
100
101
102
103
104
A8
O2
O8
CE
A10
A13
A14
VCC
O3
VSS
N.C.: Internally connected. Do not use.
7
MB89560H Series
■ PIN DESCRIPTION
Pin no.
I/O circuit
type
Pin name
Function
LQFP*1 MQFP*3
LQFP*2
QFP*4
43
45
X0
X1
Crystal or other resonator connector pins for the main clock.
The external clock can be connected to X0. When this is done,
be sure to leave X1 open.
A
C
44
42
46
44
CR oscillation selectability in model with a mask ROM only.
Memory access mode setting pins.
Connect directly to VSS.
Hysteresis input type.
MODA
RST
Reset I/O pin
This pin is a CMOS output type with a pull-up resistor, and a
hysteresis input type.
39
41
D
“L” is output from this pin by an internal reset request (optional).
The internal circuit is initialized by the input of “L”.
General-purpose CMOS I/O ports
P24/INT20 to
P27/INT23
Also serve as an external interrupt 2 input (wake-up function).
External interrupt 2 input is hysteresis input.
Selectable pull-up resistor.
49 to 52 51 to 54
E
E
General-purpose CMOS I/O ports
30 to 36
,38
32 to
38,40
P10/INT10 to
P17/INT17
Also serve as input for external interrupt 1 input.
External interrupt 1 input is hysteresis input.
Selectable pull-up resistor.
General-purpose CMOS I/O ports
Also serve as the clock I/O for the High-speed UART and
Serial IO.
The peripheral is a hysteresis input type.
Selectable pull-up resistor.
P44/UCK/
SCK1
60
62
E
General-purpose CMOS I/O ports
Also serves as the data output for the High-speed UART and
Serial I/O.
The peripheral is a hysteresis input type.
Selectable pull-up resistor.
61
62
63
64
P45/UO/SO1
F
N-ch open drain general-purpose I/O ports
Also serves as the data input for the High-speed UART and
Serial I/O.
P46/UI/SI1
P47/PWC
G
The peripheral is a hysteresis input type.
N-ch open drain general-purpose I/O port
Also serve as the external clock input for PWC.
The peripheral is a hysteresis input.
63
56
65
58
G
F
General-purpose CMOS I/O port
Also serves as an 8/16-bit timer/counter output and PWC output.
P40/WTO/
TO11
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M11
*3: MQP-80C-P01
*4: FPT-80P-M06
8
MB89560H Series
(Continued)
Pin no.
I/O circuit
type
LQFP*1
MQFP*3
QFP*4
Pin name
Function
LQFP*2
General-purpose CMOS I/O port
Also serves as an 8/16-bit timer/counter output.
and half of main clock output
P41/HCK/
TO12
57
59
47
F
E
Selectable pull-up resistor.
General-purpose CMOS I/O port
Also serves as the data input for the serial I/O.
The peripheral is a hysteresis input type.
Selectable pull-up resistor.
45
P20/SI
General-purpose CMOS I/O port
Also serves as the data output for the serial I/O.
Selectable pull-up resistor.
46
47
48
48
49
50
P21/SO
P22/SCK
P23/PPG1
F
E
F
General-purpose CMOS I/O port
Also serves as the clock I/O for the serial I/O.
The peripheral is a hysteresis input type.
Selectable pull-up resistor.
General-purpose CMOS I/O port
Also serves as the 6 bit programmable pulse generator.
Selectable pull-up resistor.
N-ch open-drain general-purpose I/O port
Data I/O pin for I2C interface
54
55
65
64
56
57
67
66
P30/SCL
P31/SDA
C0
G
G
N-ch open-drain general-purpose I/O port
Data I/O pin for I2C interface
Function as capacitor connection pin in the products with a
booster.
—
—
Function as capacitor connection pin in the products with a
booster.
C1
General-purpose CMOS I/O port
P43/PWM2/
PPG2
Also serves PWM wave output for the 8-bit PWM timer 1 and
as 12 bit programmable pulse generator output.
Selectable pull-up resistor.
59
61
F
General-purpose CMOS I/O port
P42/PWM1/
EC1
Also serves as the PWM wave output and external clock for
the 8/16 bit timer counter.
Selectable pull-up resistor.
58
60
E
J
General-purpose CMOS I/O ports
Also serve as the analog input for the A/D converter.
Selectable pull-up resistor.
P00/AN0 to
P07/AN7
21 to 28
23 to 30
P60/SEG16
to
P67/SEG23
10 to 12
14 to 18
12 to 14
16 to 20
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver segment output.
H/I
H/I
P50/SEG8 to
P57/SEG15
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver segment output.
2 to 9
4 to 11
(Continued)
*1: FPT-80P-M05
*2: FPT-80P-M11
*3: MQP-80C-P01
*4: FPT-80P-M06
9
MB89560H Series
(Continued)
Pin no.
I/O circuit
type
Pin name
Function
LQFP*1 MQFP*3
LQFP*2
QFP*4
74 to 80,
1
1 to 3
76 to 80
SEG0 to
SEG7
I
LCD controller/driver segment output-only pins
COM0
to
COM3
70 to 73 72 to 75
68 to 71 70 to 73
I
LCD controller/driver common output-only pins
V0 to V3
—
LCD driving power supply pins.
42
43
44
45
X0A
X1A
Crystal or other resonator connector pins for the subclock
(Subclock: 32.768 kHz)
The external clock can be connected to X0A.
When this is done, Be sure to leave X1A open.
B
55
39
15
22
21
57
41
17
24
23
Vcc
C
—
—
—
—
—
Power supply pin
Capacitor connection pin *5
Power supply (GND) pin
Vss
AVcc
AVR
A/D converter power supply pin
A/D converter reference voltage input pin
A/D converter power supply pin
Use this pin at the same voltage as VSS.
31
33
AVss
—
*1: FPT-80P-M05
*2: FPT-80P-M11
*3: MQP-80C-P01
*4: FPT-80P-M06
*5: When MB89PV560-101 or MB89PV560-102 is used, this pin will become a NC pin without internal
connection.
When MB89P568-101 or MB89P568-102 is used, this pin will be select a regulator stabilization
delay time.
If 5V used in MB89P568-101 or MB89P568-102, this pin must be connected to Vss.
If 3V used in MB89P568-101 or MB89P568-102, this pin must be connected to Vcc.
If MB89567H or MB89567HC is used, 0.1µF capacitor should connect to this pin.
10
MB89560H Series
■ PIN DESCRIPTION FOR EXTERNAL EPROM SOCKET (MB89PV560 ONLY)
Pin no.
Pin name
I/O
Function
82
83
84
85
86
87
88
89
90
91
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
93
94
95
O1
O2
O3
I
Data input pins
96
Vss
O
Power supply (GND) pin
Data input pins
98
99
100
101
102
O4
O5
O6
O7
O8
I
ROM chip enable pin
Outputs “H” during standby.
103
104
105
CE
A10
O
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
OE/Vpp
107
108
109
A11
A9
A8
O
Address output pins
110
111
112
A13
A14
Vcc
O
O
O
EPROM power supply pin
81
92
97
Internally connected pins
Be sure to leave them open.
N.C.
—
106
11
MB89560H Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Main clock (main clock crystal
oscillator)
N-ch P-ch
• At an oscillation feedback
resistor of approximately 1
MΩ/5.0 V
• CR oscillation is selectable
(mask products only)
P-ch
N-ch
X0
A
N-ch
X1A
Subclock (subclock crystal
oscillator)
• At an oscillation feedback
resistor of approximately 4.5
MΩ/5.0 V
N-ch P-ch
P-ch
N-ch
X0A
B
N-ch
C
D
• Hysteresis input
R
• CMOS output
P-ch
• Hysteresis input
• At an output pull-up resistor
(P-ch) of approximately 50
kΩ/5.0 V
N-ch
• CMOS output
• CMOS input
• The peripheral is a hysteresis
input type.
R
P-ch
P-ch
Pull up resistor register
E
• Selectable pull-up resistor
(P-ch) of approximately 50
kΩ/5.0 V
N-ch
Port
Peripheral
(Continued)
12
MB89560H Series
(Continued)
Type
Circuit
Remarks
R
P-ch
Pull up resistor register
• CMOS output
P-ch
N-ch
• CMOS input
F
• Selectable pull-up resistor
(P-ch) of approximately 50
kΩ/5.0 V
Port
• N-ch open-drain input/output
• CMOS input
• The peripheral is a hysteresis
input type.
N-ch
G
Port
Peripheral
• N-ch open-drain output
• CMOS input
H
N-ch
Port
P-ch
N-ch
• LCD controller/driver
common/segment output
I
P-ch
N-ch
R
P-ch
• General CMOS I/O
• Analog input (A/D converter)
• Selectable pull-up resistor
(P-ch) of approximately 50
kΩ/5.0 V
• Pull-up resistors must be
disabled when used as an
analog input).
Pull up resistor register
P-ch
N-ch
ADEN
J
Port
Analog input
13
MB89560H Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up
from stop mode.
14
MB89560H Series
■ PROGRAMMING TO THE EPROM ON THE MB89P568
The MB89P568 is an OTPROM version of the MB89567H and MB89567HC.
1. Features
• 48-Kbyte PROM on chip
• Equivalency to the MBM271001A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Normal operation
0000H
I/O
0080H
RAM
0480H
Not
available
EPROM mode
(Corresponding addresses
on the EPROM programmer
4000H
4000H
FFFFH
Program
area
(PROM)
Program
area
(PROM)
FFFFH
3. Programming to the EPROM
In EPROM mode, the MB89P568 functions equivalent to the MBM27C1001A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C1001A.
(2) Load program data into the EPROM programmer at 4000H to FFFFH
(3) Program with the EPROM programmer.
15
MB89560H Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
ROM-80SQF-32DP-8LA
ROM-80QF-32DP-8LA2
ROM-80SQF-32DP-8LA
FPT-80P-M05
FPT-80P-M06
FPT-80P-M11
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
16
MB89560H Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adaptor
To program to the PROM using an EPROM programmer, use the socket adaptor (manufacturer:
Sun Hayato Co., Ltd.) listed below.
Package
Adaptor socket part number
LCC-32 (Rectangle)
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-5396-9106
3. Memory Space
Normal operation
(Corresponding addresses on the
EPROM programmer)
0000H
0080H
I/O
RAM
0480H
2000H
Not available
2000H
Program area
(PROM)
Program area
(PROM)
FFFFH
FFFFH
4. Programming to EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 2000H to FFFFH.
(3) Program to 2000H to FFFFH with the EPROM programmer.
17
MB89560H Series
■ BLOCK DIAGRAM
I2C*2
P30/SCL
P31/SDA
Main clock
X0
X1
Oscillator
N-ch open drain I/O port
SIO
Clock controller
P40/WTO/TO11
P41/HCK*1/TO12
P42/PWM1/EC1
High-speed
UART
Subclock
Low-power oscillator
(32.768 kHz)
X0A
X1A
12 bit PPG
PWC
Watch prescaler
P43/PWM2/PPG2
*4
Reset circuit
(Watchdog timer)
8-bit
RST
timer/counter 1
(Timer 1)
P44/UCK/SCK1
P45/UO/SO1
*4
21-bit Time-base
timer
8-bit
timer/counter 2
(Timer 2)
8
8
P10/INT10
External interrupt 1
CMOS I/O port
8-bit PWM timer 2
8-bit PWM timer 1
to P17/INT17
P46/UI/SI1
P47/PWC
CMOS I/O port
(P46 and P47 are N-ch
Open-diran I/O Type)
6 bit PPG
P24/INT20
to P27/INT23
4
4
External interrupt 2
(wake-up function)
4
4
N-ch open-drain
I/O port
P60/SEG16 to
P63/SEG19
P64/SEG20 to
P67/SEG23
P23/PPG1
8
P20/SI
P21/SO
P22/SCK
UART/SIO
8
4
4
LCD controller/
P50/SEG8 to
P53/SEG11
driver
CMOS I/O port
P54/SEG12 to
P57/SEG15
8
4
Display RAM
(12 bytes)
SEG0 to SEG7
COM0 to COM3
V0 to V3
1K Byte RAM
4
2
F MC-8L
CPU
C0*3
Option
C1*3
Booster
Wild register
CMOS I/O port
8
P00/AN0
48K Byte ROM
to P07/AN7
8
Other pins
MODA, C, VCC, VSS
10-bit A/D converter
AVCC
AVSS
AVR
*1: Output of Main clock/2.
*2 : I2C is not available in MB89567 and MB89567H.
*3 : Selected by mask option
*4 : Can be used as a 16-bit timer/counter by connecting Timer 1 output to Timer 2 input.
18
MB89560H Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89560H series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/
O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89560H series is structured as illustrated below.
Memory Space
MB89567H,
MB89567HC
MB89PV560-101,102
0000H
MB89P568-101,102
0000H
0000H
0080H
I/O
I/O
I/O
RAM
0080H
0100H
0080H
0100H
RAM
RAM
0100H
Registers
Registers
*2
Registers
0200H
0480H
0492H
0200H
0480H
0492H
0200H
0480H
0492H
*2
*2
Access
prohibited
Access
prohibited
2000H
Access
prohibited
4000H
8000H
External*1
ROM
External*1
ROM
ROM
FFC0H
FFFFH
FFC0H
FFFFH
FFC0H
FFFFH
*1: MB89P568-101,102 has OTP ROM inside
*2 : Wild register setting registers
19
MB89560H Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating specifies instruction storage positions.
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
When theinstructionisan 8-bitdata processing instruction, thelowerbyte isused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFD
H
Undefined
Undefined
Undefined
Undefined
Undefined
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
Vacancy
Vacancy
PS
RP
Vacancy
H
IL1, 0
N
V
C
RP
CCR
20
MB89560H Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
21
MB89560H Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit resister for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 32 banks can be used on MB89567H and MB89567HC. The bank currently in
use is indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100 + 8 ´ (RP)
H
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks (MB89567H/567HC)
Memory area
22
MB89560H Series
■ I/O MAP
Address
00H
Register name
PDR0
Register Description
Port 0 data register
Read/Write
Initial value
XXXXXXXXB
00000000B
R/W
W
01H
DDR0
Port 0 data direction register
Port 1 data register
02H
PDR1
R/W
W
XXXXXXXXB
00000000B
03H
DDR1
Port 1 data direction register
04H - 06H
07H
(Vacancy)
SYCC
STBC
WDTC
TBTC
System clock control register
Standby control register
R/W
R/W
W
XXXMM100B
00010XXXB
0XXXXXXXB
00XXX000B
08H
09H
Watchdog timer control register
0AH
R/W
Timebase timer control register
Watch prescaler control register
Port 2 data register
0BH
0CH
WPCR
PDR2
R/W
R/W
00XX0000B
XXXXXXXXB
0DH
0EH
DDR2
PDR3
PDR4
DDR4
PDR5
R/W
R/W
R/W
R/W
R/W
00000000B
XXXXXX11B
XXXXXXXXB
00000000B
00000000B
Port 2 data direction register
Port 3 data register
Port 4 data register
Port 4 direction register
Port 5 data register
(Vacancy)
0FH
10H
11H
12H
13H
PDR6
Port 6 data register
(Vacancy)
R/W
00000000B
14H - 19H
1AH
T2CR
T2DR
T1CR
T1DR
Timer2 control register
Timer2 data register
Timer1 control register
Timer1 data register
(Vacancy)
R/W
R/W
R/W
R/W
X000XXX0B
XXXXXXXXB
X000XXX0B
XXXXXXXXB
1BH
1CH
1DH
1EH - 21H
22H
SMC11
SRC1
SSD1
UART1 mode control register 1
UART1 mode data register
UART1 status/data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
00000000B
XX011000B
00100X1XB
XXXXXXXXB
XX100001B
00000000B
000X0000B
X000XXXXB
XXXXXXXXB
XXXXXXXXB
000XX000B
00000000B
XXXXXXXXB
00000000B
00000000B
23H
24H
25H
SIDR1/SODR1 UART1 data register
26H
SMC12
CNTR1
CNTR2
CNTR3
COMR1
COMR2
PCR1
UART1 mode control register 2
27H
PWM control register 1
28H
PWM control register 2
29H
PWM control register 3
2AH
PWM compare register 1
2BH
PWM compare register 2
W
2CH
2DH
2EH
PWC pulse width control register 1
PWC pulse width control register 2
PWC reload buffer register
UART2/SIO mode control register
UART2/SIO mode control register 2
R/W
R/W
R/W
R/W
R/W
PCR2
RLBR
2FH
SMC21
SMC22
30H
(Continued)
23
MB89560H Series
(Continued)
Address
31H
Register name
Register Description
Read/Write
R/W
Initial value
00001XXXB
XXXXXXXXB
XXXXXXXXB
X00000X0B
X0000001B
XXXXXXXXB
XXXXXXXXB
00000000B
0X000000B
XX000000B
XX000000B
SSD2
UART2/SIO status/data register
32H
SIDR2/SODR2 UART2/SIO data register
R/W
33H
SRC2
ADC1
UART2/SIO rate control register
A/D control register 1
R/W
34H
R/W
35H
ADC2
A/D control register 2
R/W
36H
ADDL
A/D data register L
R/W
37H
ADDH
RCR21
RCR23
RCR22
RCR24
A/D data register H
R/W
38H
PPG control register 1(PPG2)
PPG control register 2(PPG2)
PPG control register 3(PPG2)
PPG control register 4(PPG2)
(Vacancy)
R/W
39H
R/W
3AH
3BH
3CH - 3EH
3FH
R/W
R/W
EIC1
EIC2
EIC3
EIC4
External interrupt 1 control register 1
External interrupt 1 control register 2
External interrupt 1 control register 3
External interrupt 1 control register 4
(Vacancy)
I2C bus status register
I2C bus control register
I2C clock control register
I2C address register
I2C data register
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
40H
41H
42H
43H - 50H
51H
IBSR
IBCR
ICCR
IADR
IDAR
EIE2
R
00000000B
00000000B
000XXXXXB
XXXXXXXXB
XXXXXXXXB
XXXX0000B
XXXXXXX0B
00000000B
0X000000B
00000000B
00010000B
00000000B
XX000000B
XXXXXXXXB
52H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
53H
54H
55H
56H
External interrupt 2 enable register
External interrupt 2 flag register
PPG control register 1(PPG1)
PPG control register 2(PPG1)
Clock Output control register
LCD controller/driver control register 1
LCD controller/driver control register 1
LCD controller/driver control register 1
LCD data register 1
57H
EIF2
58H
RCR1
RCR2
CKR
59H
5AH
5BH
5CH
5DH
5EH
5FH
LCR1
LCR2
LCR3
LDR1
(Vacancy)
60H - 6FH
70H
VRAM
SMR
Display RAM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
00000000B
XXXXXXXXB
11111111B
11111111B
11111111B
XX111111B
Serial I/O mode register
Serial I/O data register
71H
SDR
72H
PURR0
PURR1
PURR2
PURR4
Pull-up resister register 0
Pull-up resister register 1
Pull-up resister register 2
Pull-up resister register 4
(Vacancy)
73H
74H
75H
76H
(Continued)
24
MB89560H Series
(Continued)
Address
Register name
WREN
Register Description
Wild register enable register
Wild register data test register
A/D port input enable register
(Vacancy)
Read/Write
R/W
Initial value
XX000000B
XX000000B
11111111B
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
WROR
R/W
ADEN
R/W
ILR1
ILR2
ILR3
ILR4
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
W
W
W
W
11111111B
11111111B
11111111B
11111111B
Access
Prohibited
7FH
ITR
Interrupt test register
11111111B
■ EXTEND I/O MAP
Address Register name Register description
Read/Write Initial value
480H
481H
482H
483H
484H
485H
486H
487H
488H
489H
48AH
48BH
48CH
48DH
48EH
48FH
490H
491H
WRARH1
Wild register high-byte address register1
Wild register low-byte address register1
Wild register data register1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register high-byte address register2
Wild register low-byte address register2
Wild register data register2
WRARH3
WRARL3
WRDR3
Wild register high-byte address register3
Wild register low-byte address register3
Wild register data register3
WRARH4
WRARL4
WRDR4
Wild register high-byte address register4
Wild register low-byte address register4
Wild register data register4
WRARH5
WRARL5
WRDR5
Wild register high-byte address register5
Wild register low-byte address register5
Wild register data register5
WRARH6
WRARL6
WRDR6
Wild register high-byte address register6
Wild register low-byte address register6
Wild register data register6
● Read/write access symbols
R/W: Readable and writable
R: Read-only
W: Write-only
● Initial value symbols
0: The initial value of this bit is “0”.
1: The initial value of this bit is “1”.
X: The initial value of this bit is undefined.
M: The initial value of this bit is determined by mask option.
Note:Do not use vacancies.
25
MB89560H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
AVCC
VSS – 0.3
VSS + 6.0
VSS + 6.0
V
MB89567H, MB89567HC,
MB89P568 and MB89PV560
Power supply voltage
AVR
VPP
VSS – 0.3
V
V
Program voltage
Input voltage
VSS – 0.6 VSS +13.0
VSS – 0.3 VCC + 0.3
Only for the MB89P568
For pins other than P30 and P31
For P30 and P31
V
VI
VSS – 0.3
VSS + 6.0
V
VSS – 0.3 VCC + 0.3
V
For pins other than P30 and P31
For P30 and P31
Output voltage
VO
VSS – 0.3
VSS + 6.0
V
“H” level maximum output current IOL
15
mA
Average value (operating current
× operating rate)
“L” level average output current
IOLAV
4
mA
mA
“L” level total maximum output
current
∑IOL
100
“L” level total average output
current
Average value (operating current
× operating rate)
∑IOLAV
40
–15
–4
mA
mA
mA
“H” level maximum output current IOH
Average value (operating current
× operating rate)
“H” level average output current
IOHAV
“H” level total maximum output
current
∑IOH
–50
–20
mA
mA
“H” level total average output
current
Average value (operating current
× operating rate)
∑IOHAV
Power consumption
Operating temperature
Storage temperature
PD
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
* : Use AVCC and VCC set at the same voltage.
Take care so that AVR and AVCC + 0.3V does not exceed VCC, such as when power is turned on.
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
26
MB89560H Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
3.5*
3.0
5.5*
V
V
V
V
For MB89567H and MB89567HC
Retains the RAM state in stop mode
for MB89567H and MB89567HC
5.5
5.5*
5.5
VCC
AVCC
Power supply voltage
2.7*
1.5
For MB89PV560 and MB89P568
Retains the RAM state in stop mode
for MB89PV560 and MB89P568
A/D converter reference input
voltage
AVR
TA
3.5
AVCC
+85
V
Operating temperature
–40
°C
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, Figure 2,
Figure 3 and “5. A/D Converter Electrical Characteristics.”
: MB89P568, MB89PV560
: MB89567H, MB89P567HC
Operating
Voltage (V)
A/D Converter accuracy assurance range : Vcc = AVcc =3.5V~5.5V
5.5
5.0
Operation assurance range
4.0
3.5
3.0
2.7
2.0
Main clock
operating Freq. (MHz)
1.0
4.0
2.0
2.0
3.0
4.0
5.0
0.8
6.0
7.0
8.0
9.0 10.0 12.0 11.0 12.5
Min execution
time (inst. cycle) (µs)
0.4
0.32
Figure 1 Operating Voltage vs. Main Clock Operating Frequency
27
MB89560H Series
3. DC Characteristics
(AVCC = VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37
P40 to P45
VIH
—
0.7 VCC
—
VCC + 0.3
V
RST, MODA
INT10 to INT17,
INT20 to INT23,
SI,SCK,EC1,UCK,
SCK1,UI,SI1,PWC
“H” level
input voltage
VIHS
—
0.8 VCC
—
VCC + 0.3
V
SMB input
buffer selected
VIHSMB
VIHI2C
—
—
VSS +1.4
0.7 VCC
—
—
VSS + 5.5
VCC + 0.3
V
V
SDL, SDA
I2C input
buffer selected
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P45
VIL
—
—
VSS − 0.3
VSS − 0.3
—
—
0.3 VCC
0.2 VCC
V
V
RST, MODA
INT10 to INT17,
INT20 to INT23,
SI,SCK,EC1,UCK,
SCK1,UI,SI1,PWC
“L” level
input voltage
VILS
SMB input
buffer selected
VILSMB
VILI2C
—
—
VSS - 0.3
—
—
VSS + 0.6
0.3 VCC
V
V
SCL, SDA
I2C input
buffer selected
VSS − 0.3
Open-drain
output pin
application
voltage
P60 to P67
P50 to P57
P46, P47
VD
—
VSS − 0.3
—
—
VCC + 0.3
V
V
P30, P31
P00 to P07,
P10 to P17,
P40 to P45
IOH = –2.0 mA
“H” level
output voltage
VOH
4.0
—
P20 to P27
IOH = –15.0 mA
P00 to P07,
P10 to P17,
P30 to P31,
P40 to P47,
P50 to P57,
P60 to P67, RST
IOL = 4.0 mA
“L” level
output voltage
VOL
—
—
0.4
V
P20 to P27
IOL = 15.0 mA
(Continued)
28
MB89560H Series
(Continued)
(AVCC = VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
FCH = 10.0 MHz
VCC = 5.0 V
tinst*3 = 0.4 µs
Main clock run
mode
MB89PV560
MB89P568
—
15
20
ICC1
mA
mA
mA
mA
—
MB89567H
MB89567HC
6
5
10
8.5
3
FCH = 10.0 MHz
VCC = 5.0 V
tinst*3 = 6.4 µs
Main clock run
mode
MB89PV560
MB89P568
—
—
ICC2
MB89567H
MB89567HC
1.5
5
FCH = 10.0 MHz
VCC = 5.0 V
tinst*3 = 0.4 µs
Main clock sleep
mode
MB89PV560
MB89P568
—
—
—
—
7
ICCS1
MB89567H
MB89567HC
2
4
FCH = 10.0 MHz
VCC = 5.0 V
tinst*3 = 6.4 µs
Main clock sleep
mode
MB89PV560
MB89P568
1.5
1
3
ICCS2
MB89567H
MB89567HC
2
VCC ‘
MB89PV560
MB89P568
—
—
—
—
3
7
mA
FCL = 32.768 kHz
VCC = 5.0
Subclock mode
Power supply
current
ICCL
MB89567H
MB89567HC
20
30
15
50
50
30
µA
MB89PV560
MB89P568
FCL = 32.768 kHz
VCC = 5.0 V
Subclock sleep
mode
ICCLS
µA
MB89567H
MB89567HC
FCL = 32.768 kHz
VCC = 3.0 V
• Watch mode
• Main clock stop
mode
ICCT
—
5
15
µA
µA
TA = +25°C
• Subclock stop
mode
ICCH
—
—
—
3
4
1
10
6
when A/D
IA
FCH = 10.0 MHz,
mA conversion
is activated
AVCC
when A/D
µA conversion
is stopped
FCH = 10.0 MHz,
TA = +25°C,
IAH
5
(Continued)
29
MB89560H Series
(Continued)
(AVCC = VCC = 5.0V, , AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P45,
P50 to P57,
P60 to P67
Without
pull-up
Resister
-5
—
+5
µA
Input leakage
current
ILI
0.0V < VI < VCC
MODA
-10
—
—
—
+10
+5
µA
µA
Open-drain output
leakage current
P30, P32
P46, P47
0.0V < VI < Vss +
5.5V
ILIOD
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P31,
P40 to P45,
RST
When pull-
up resistor
selected
Pull-up
resistance
RPULL
VI = 0.0 V
25
50
100
kΩ
except RST
LCD divided
resistance
Between VCC and
VSS
RLCD
—
300
—
500
—
750
2.5
15
kΩ
kΩ
kΩ
COM0 to COM3
output impedance
RVCOM
RVSEG
COM0 to 3
SEG0 to 23
V1 to V3 = 5.0V
SEG0 to 23 output
impedance
—
—
LCD controller/
driver leakage
current
V0 to V3,
COM0 to 3
SEG0 to 23
ILCDL
CIN
—
—
—
—
+1
—
µA
Other than
AVCC, AVSS, VCC, f = 1 MHz
and VSS
Input
capacitance
10
pF
30
MB89560H Series
4. AC Characteristics
(1) Reset Timing
(VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
48 tHCYL*
—
ns
* : tHCYL is the oscillation cycle (1/FC) to input to the X0 pin.
t
ZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min. Max.
Symbol Condition
Unit
Remarks
Power supply rising time
Power supply cut-off time
tR
0.5
1
50
—
ms
ms
—
tOFF
Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time.
For example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select
option has been set to 218/FCH, the oscillation stabilization delay time is 26.2 ms. Therefore, the maximum
value of power supply rising time is about 26.2 ms.
Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be
varied in the course of operation, a smooth voltage rise is recommended.
t
OFF
t
R
3.5 V
0.2 V
0.2 V
0.2 V
V
CC
31
MB89560H Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Symbol
Pin
Unit
Remarks
Parameter
Min.
1
Max.
FCH
FCL
X0, X1
12.5 MHz Main clock
Clock frequency
X0A, X1A
X0, X1
—
32.768
—
—
1000
—
kHz Subclock
tHCYL
tLCYL
80
—
ns
Main clock
Subclock
Clock cycle time
X0A, X1A
30.5
µs
PWH
PWL
X0
20
—
—
—
15.2
—
—
—
10
ns
µs
ns
External clock
External clock
External clock
Input clock pulse width
PWH
PWL
X0A
X0
tCR
tCF
Input clock rising/falling time
X0 and X1 Timing and Conditions
t
HCYL
P
WH
P
WL
t
CR
t
CF
0.8 VCC
0.8 VCC
X 0
0.2 VCC
0.2 VCC
0.2 VCC
Main Clock Conditions
When a crystal
or
ceramic reasonator is used
When an external clock is used
X0
X1
X0
X1
Open
F
CH
F
CH
C1
C2
32
MB89560H Series
X0A and X1A Timing and Conditions
t
LCYL
PWLH
PWLL
t
CR
t
CF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
Subclock Conditions
When a crystal
or
ceramic reasonator is used
When an external clock is used
X0A
X1A
X0A
X1A
Open
FCL
FCL
C1
C2
(4) Instruction Cycle
Symbol
Value
Unit
Remarks
Parameter
tinst = 0.32µs when operating at
FCH = 12.5 MHz (4/FCH)
4/FCH, 8/FCH, 16/FCH, 64/FCH
2/FCL
µs
Instruction cycle
(minimum execution time)
tinst
tinst = 61.036 µs when operating at
FCL = 32.768 kHz
µs
33
MB89560H Series
(5) Serial I/O Timing
(Vcc = 5.0V, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Parameter
Min.
Max.
SCK, SCK1,
UCK
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
2 tinst*
—
µs
ns
ns
ns
SCK, SO, SCK1,
SO1, UCK, UO
–200
200
200
—
Internal
shift clock
mode
SI, SCK, SI1,
SCK1, UI, UCK
Valid SI → SCK ↑
SCK, SI, SCK1,
SI1, UCK, UI
SCK ↑ → valid SI hold time
200
—
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
1 tinst*
1 tinst*
—
—
µs
µs
SCK, SCK1,
UCK
SCK, SO, SCK1,
SO1, UCK, UO
SCK ↓ → SO time
tSLOV
tIVSH
tSHIX
External
shift clock
mode
0
200
—
ns
ns
ns
SI, SCK, SI1,
SCK1, UI, UCK
Valid SI → SCK ↑
200
200
SCK, SI, SCK1,
SI1, UCK, UI
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Shift Clock Mode
t
SCYC
SCK
SCK1
2.4 V
UCK
0.8 V
0.8 V
t
SLOV
SO
SO1
UO
2.4 V
0.8 V
t
IVSH
tSHIX
SI
SI1
U1
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
External Shift Clock Mode
t
SLSH
tSHSL
SCK
SCK1
UCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t
SLOV
SO
SO1
UO
2.4 V
0.8 V
t
IVSH
t
SHIX
SI
SI1
UI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
34
MB89560H Series
(6) Peripheral Input Timing
Parameter
(Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Condition
Unit Remarks
Min.
Max.
Peripheral input “H” pulse width 1 tILIH1
Peripheral input “L” pulse width 1 tIHIL1
INT10 to INT17,
INT20 to INT23,
EC, PWC
2 tinst*
—
µs
µs
—
2 tinst*
—
* : For information on tinst, see “(4) Instruction Cycle.”
t
IHIL1
t
ILIH1
INT10 to 17,
INT20 to INT23
EC, PWC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
35
MB89560H Series
(7) I2C timing
(Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin Condition
Unit Remarks
Parameter
Min.
Max.
SCL
SDA
1/4tINST x
m x n - 20
1/4tINST x
m x n + 20
master
mode
Start condition output tSTA
Stop condition output tSTO
Start condition detect tSTA
ns
ns
ns
ns
ns
ns
ns
SCL
SDA
1/4tINST x
(m x n + 8) - 20 (m x n + 8) + 20
1/4tINST x
master
mode
SCL
SDA
1/4tINST x 6 + 40
1/4tINST x 6 + 40
—
—
SCL
SDA
Stop condition detect tSTO
Re-start condition
SCL
SDA
1/4tINST x
(m x n + 8) - 20
1/4tINST x
(m x n + 8) + 20
master
mode
tSTASU
tSTASU
tLOW
tHIGH
tDO
output
Re-start condition
detect
SCL
SDA
1/4tINST x 4 + 40
—
SCL output LOW
width
1/4tINST x
m x n - 20
1/4tINST x
m x n + 20
master
mode
SCL
SCL output HIGH
width
1/4tINST x
(m x n + 8) - 20
1/4tINST x
(m x n + 8) + 20
master
mode
SCL
SDA
SDA
ns
ns
ns
SDA output delay
1/4tINST x 4 - 20
1/4tINST x 4 + 20
SDA output setup
time after interrupt
tDOSU
1/4tINST x 4 - 20
—
SCL input LOW
pulse width
tLOW
tHIGH
SCL
SCL
1/4tINST x 6 + 40
1/4 tINST x 2 + 40
—
—
ns
ns
SCL input HIGH
pulse width
SDA input setup time tSU
SDA hold time tHO
SDA
SDA
40
0
—
—
ns
ns
• For information in tINST, see "(4) Instruction Cycle".
• m is defined in the ICCR CS4 and CS3 (bit 4 to bit 3)
• n is defined in the ICCR CS2 to CS0 (bit 2 to bit 0)
Data transmit (master/slave)
tSU
tHO
tDO
tDO
tDOSU
SDA
ACK
tSTASU
tSTA
tLOW
tHO
SCL
1
9
Data receive (master/slave)
tSU
tHO
tDO
tDO
tDOSU
SDA
ACK
9
tLOW
tHIGH
tSTO
SCL
6
7
8
36
MB89560H Series
5. A/D Converter Electrical Characteristics
(1) For MB89567H A/D Converter
(AVcc=3.5~5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Condition
Value
Parameter
Resolution
Symbol Pin
Unit
Remarks
Min.
—
Typ.
—
Max.
10
—
bit
Total error
—
—
±5.0
±2.5
LSB
LSB
—
1LSB = AVR/1024
Non-linearity error
—
—
Differential linearity
error
—
—
±1.9
LSB
mV
mV
AVR=AVCC
AVR -
AVR +
AVR +
Zero transition voltage VOT
—
3.5 LSB 0.5 LSB 4.5 LSB
Full-scale transition
VFST
AVR –
6.5 LSB
AVR –
1.5 LSB
AVR +
1.5 LSB
voltage
Interchannel disparity
A/D mode conversion
—
—
—
—
—
4
LSB 1LSB = AVR/1024
—
60 tinst*1
16 tinst*1
—
—
—
10
µs
time *3
A/D Sampling time
Analog port input
current
—
AN0
to
IAIN
µA
AN7
Analog input voltage
Reference voltage
VAIN
AVss
—
—
AVR
AVCC
V
V
—
AVss+3.5
A/D is
Activated
IR
—
—
400
—
—
5
µA
AVR
Reference voltage
supply current
A/D is
Stopped
*2
IRH
µA
* : 1 For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
* : 2 When A/D conversion is not in operation, and the CPU is in STOP mode.
* : 3 Included sampling time
37
MB89560H Series
(2) For MB89P568 A/D Converter
(AVcc=3.5~5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Condition
Value
Parameter
Resolution
Symbol Pin
Unit
Remarks
Min.
—
Typ.
—
Max.
10
—
bit
Total error
—
—
±3.0
±2.5
LSB
LSB
—
1LSB = AVR/1024
Non-linearity error
—
—
Differential linearity
error
—
—
±1.9
LSB
mV
mV
AVR=AVCC
AVR -
AVR +
AVR +
Zero transition voltage VOT
—
1.5 LSB 0.5 LSB 2.5 LSB
Full-scale transition
VFST
AVR –
3.5 LSB
AVR –
1.5 LSB
AVR +
1.5 LSB
voltage
Interchannel disparity
A/D mode conversion
—
—
—
—
—
4
LSB 1LSB = AVR/1024
—
60 tinst*1
16 tinst*1
—
—
—
10
µs
time *3
A/D Sampling time
Analog port input
current
—
AN0
to
IAIN
µA
AN7
Analog input voltage
Reference voltage
VAIN
AVss
—
—
AVR
AVCC
V
V
—
AVss+3.5
A/D is
Activated
IR
—
—
400
—
—
5
µA
AVR
Reference voltage
supply current
A/D is
Stopped
*2
IRH
µA
* : 1 For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
* : 2 When A/D conversion is not in operation, and the CPU is in STOP mode.
* : 3 Included sampling time
* :
38
MB89560H Series
(3) Precautions
• The smaller the | AVR–AVSS |, the greater the error would become relatively.
• The output impedance of the externalcircuit for the analog input must satisfy the following conditions:
Output impedance of the external circuit < Approx. 10 kΩ
• If the output impedance of the external circuit is too high, an analog voltage sampling time might be
insufficient (sampling time = 6 µs at 10MHz oscillation.)
Sample hold circuit
Analog Input Circuit Model
.
C = 33 pF
.
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kW, it is
recommended to
connect an external
capacitor of approx.
0.1 mF.
.
R = 6 kW
.
Close for 8 instruction cycles after
activating A/D conversion.
Analog channel selector
(4) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values caused by the zero transition error, full-scale
transition error, linearity error, quantization error, and noise
Theoretical I/O characteristics
Total error
3FF
3FE
3FD
3FF
3FE
3FD
V
FST
Actual conversion
value
1.5 LSB
{1 LSB × N + 0.5 LSB}
004
003
002
001
004
003
002
001
V
NT
V
OT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVR
AVR
AVSS
AVSS
Analog input
Analog input
V
FST – VOT
V
NT – {1 LSB × N + 0.5 LSB}
Digital output N total error =
1 LSB =
(V)
1022
1 LSB
(Continued)
39
MB89560H Series
(Continued)
Zero transition error
Full-scale transition error
004
003
002
001
Theoretical value
Actual conversion
value
3FF
3FE
3FD
3FC
Actual conversion
value
VFST
(Actual
measurement)
Actual conversion
value
Actual conversion value
VOT (Actual measurement)
Analog input
AVR
AVSS
Analog input
Differential linearity error
Theoretical value
Linearity error
3FF
3FE
3FD
Actual conversion
N + 1
value
Actual conversion
value
{1 LSB × N + VOT}
V(N + 1)T
VFST
(Actual
N
V
NT
measurement)
004
003
002
001
N – 1
N – 2
VNT
Actual conversion value
Theoretical value
Actual conversion value
VOT (Actual measurement)
AVR
– 1
AVSS
AVR
AVSS
Analog input
Analog input
VNT – {1 LSB × N + VOT}
V(N + 1)T – VNT
Digital output N differential linearity error =
Digital output N linearity error =
1 LSB
1 LSB
40
MB89560H Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir: b
rel
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
AH
AL
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
T
TH
TL
IX
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
(Continued)
41
MB89560H Series
(Continued)
Symbol
Meaning
EP
PC
SP
PS
dr
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
CCR
RP
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
( × )
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
~:
Assembler notation of an instruction
Number of instructions
Number of bytes
#:
Operation:
TL, TH, AH:
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
42
MB89560H Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH N ZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
88 to 8F
D5
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
MOVW A,@IX +off
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
AL
AL
–
–
–
–
AH
–
–
–
XCHW A,T
dH
dH
dH
dH
dH
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
–
–
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
43
MB89560H Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH N ZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
INC Ri
INCW EP
INCW IX
INCW A
C8 to CF
C3
C2
C0
D8 to DF
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
–
–
D3
D2
D0
01
11
63
73
53
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
(TL) − (AL)
(T) − (A)
12
13
03
CMPW A
RORC A
–
–
→
→
A
C
←
C ← A
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
64
65
AND A,#d8
AND A,dir
(A) ← (AL) (dir)
(Continued)
44
MB89560H Series
(Continued)
Mnemonic
~
#
Operation
TL
TH AH N ZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH N ZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH
NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
45
MB89560H Series
■ INSTRUCTION MAP
46
MB89560H Series
■ MASK OPTION
MB89567H
MB89567HC
Model
MB89P568
MB89PV560
NO.
Specify when
ordering mask.
Setting
unavailable.
Specification method
Setting unavailable.
Main clock oscillation
stabilization delay time initial
value* selection (FCH = 10
MHz)
• 01: 212/FCH (Approx. 0.41 ms)
• 10: 216/FCH (Approx. 6.55 ms)
• 11: 218/FCH (Approx. 26.2 ms)
18
2 /FCH (approx.
218/FCH (Approx.
26.2 ms)
1
2
Selectable
26.2ms)
-101
Internal voltage
divider
-102
On-chip voltage
booster
LCD driving power supply
•
On-chip voltage booster
Internal voltage divider
Internal voltage Selectable by
booster version number
•
(external divider resistors
can be used)
47
MB89560H Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89567HPFV
MB89567HCPFV
MB89P568PFV-101
Without Booster
Resistor divider
80-pin Plastic LQFP
(FPT-80P-M05)
MB89567HPFV
MB89567HCPFV
With Booster
MB89P568PFV-102
MB89567HPF
MB89567HCPF
MB89P568PF-101
Without Booster
Resistor divider
80-pin Plastic QFP
(FPT-80P-M06)
MB89567HPF
MB89567HCPF
With Booster
MB89P568PF-102
MB89567HPFM
MB89567HCPFM
MB89P568PFM-101
Without Booster
Resistor divider
80-pin Plastic LQFP
(FPT-80P-M11)
MB89567HPFM
MB89567HCPFM
With Booster
MB89P568PFM-102
Without Booster
Resistor divider
MB89PV560CF-101
MB89PV560CF-102
80-pin Ceramic MQFP
(MQP-80C-P01)
With Booster
48
MB89560H Series
■ PACKAGE DIMENSIONS
80-pin Plastic LQFP
(FPT-80P-M05)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
1.50 +–00..1200
.059 +–..000048
(Mounting height)
60
41
61
40
13.00
(.512)
NOM
9.50
(.374)
REF
INDEX
80
21
1
20
LEAD No.
Details of "A" part
"A"
0.50±0.08
(.0197±.0031)
0.18 +–00..0038
.007 +–..000013
0.127 +–00..0025
.005 +–..000012
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
Dimension in mm (inches)
0.10(.004)
0
10˚
C
1994 FUJITSU LIMITED F80008S-2C-4
80-pin Plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
64
41
65
40
12.00(.472)
REF
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
16.30±0.40
(.642±.016)
INDEX
80
25
"A"
1
24
LEAD No.
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.15±0.05(.006±.002)
M
0.16(.006)
Details of "A" part
Details of "B" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10˚
0.18(.007)MAX
0.58(.023)MAX
18.40(.724)REF
0.80±0.20
(.031±.008)
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F80010S-3C-2
Dimension in mm (inches)
49
MB89560H Series
80-pin Plastic LQFP
(FPT-80P-M11)
16.00±0.20(.630±.008)SQ
1.50+0.01.020
.059 +.0.00408
(Mounting height)
60
61
41
40
14.00±0.10(.551±.004)SQ
15.00
(.591)
12.35
(.486)
REF NOM
1 PIN INDEX
80
21
1
Details of "A" part
0.10±0.10
LEAD No.
"A"
0.127 +0.00.205
.005+.0.00102
20
(STAND OFF)
0.65(.0256)TYP
0.30±0.10
(.012±.004)
M
(.004±.004)
0.13(.005)
0.50±0.20
(.020±.008)
0.10(.004)
0
10˚
C
1995 FUJITSU LIMITED F80016S-1C-3
Deminsion in mm (inches)
80-pin Ceramic MQFP
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.50(.059)TYP
1.00(.040)TYP
0.80±0.25
(.0315±.010)
INDEX AREA
1.20 +–00..2400
4.50(.177)
TYP
.047 +–..000186
0.80±0.25
(.0315±.010)
1.27±0.13
(.050±.005)
INDEX AREA
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.40(.724)
REF
10.16(.400)
TYP
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
INDEX
6.00(.236)
TYP
0.40±0.10
(.016±.004)
1.50(.059)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20 +–00..2400
.047 +–..000186
TYP
1.00(.040)
TYP
0.15±0.05 8.70(.343)
(.006±.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
50
MB89560H Series
MEMO
51
MB89560H Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
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Tel: (044) 754-3763
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http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
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Fax: (408) 737-5999
Mon. - Fri.: 7 am - 5 pm (PST)
Toll Free: (800) 866-8608
http://www.fma.fujitsu.com/
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications.
Complete information sufficient for construction purposes is not
necessarily given.
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
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New Tech Park
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use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear
control systems or medical equipments for life support.
F9806
FUJITSU LIMITED Printed in Japan
52
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