MB89647PFM_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12505-3E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89640 Series

MB89643/645/646/647/P647/PV640

■ DESCRIPTION

The MB89640 series has been developed as a general-purpose version of the F²MC*-8L family consisting of

proprietary 8-bit, single-chip microcontrollers.

In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as

dual-clock control system, five operating speed control stages, timers, a PWM timer, serial interface, an A/D

converter, a D/A converter, an external interrupt, and a watch prescaler.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

Bit manipulation instructions, etc.

(Continued)

■ PACKAGE

80-pin Ceramic MQFP

80-pin Plastic QFP

(FPT-80P-M11)

(FPT-80P-M06)

(MQP-80C-P01)

MB89640 Series

(Continued)

• Six types of timers

8-bit PWM timer: 2 channels (also usable reload timer)

8-bit pulse width counter (continuous measurement capable and applicable to remote control)

16-bit timer/counter

21-bit time-base counter

15-bit watch prescaler

• Two 8-bit serial I/O

Swichable transfer direction allows communication with various equipment.

• 8-bit A/D converter: 8 channels

Sense mode function enabling comparison at 12 instructions

Activation by external input capable

• External interrupt 1, external interrupt 2: 9 channels

• 8-bit D/A converter: 2 channels

8-bit R-2R type

• Low-power consumption modes (stop mode, sleep mode, watch mode, subclock mode)

• Bus interface functions

Including hold and ready functions

2

MB89640 Series

■ PRODUCT LINEUP

Part number

MB89643

MB89645

MB89646

MB89647

MB89P647

MB89PV640

Parameter

Piggyback/

Classification

Mass production products

(mask ROM products)

One-time

PROM product

evaluation product

for evaluation and

development

32 K × 8 bits

(internal PROM,

programming with

general-purpose

programmer)

ROM size

8 K × 8 bits

16 K × 8 bits

24 K × 8 bits 32 K × 8 bits

32 K × 8 bits

(external ROM)

(internalmask (internalmask (internalmask (internalmask

ROM)

RAM size

256 × 8 bits

512 × 8 bits

768 × 8 bits

1 K × 8 bits

CPU functions

Number of instructions:

Instruction bit length:

Instruction length:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

Data bit length:

Minimum execution time:

0.4 µs/10 MHz to 6.4 µs/10 MHz,

or 61.0 µs/32.768 kHz

Interrupt processing time:

3.6 µs/10 MHz to 57.6 µs/10 MHz,

or 562.5 µs/32.768 kHz

Ports

Input ports (CMOS):

Output ports (CMOS):

I/O ports (CMOS):

9 (All also serve as a external interrupt.)

8 (All also serve as a bus control.)

24 (8 ports also serve as peripherals,

16 ports also serve as a bus control.)

8 (All also serve as peripherals.)

I/O ports (N-ch open-drain):

Output ports (N-ch open-drain): 16 (8 ports also serve as peripherals.)

Total:

65

Clock timer

21 bits × 1 (in main clock mode), 15 bits × 1 (at 32.768 kHz)

8-bit PWM

timer

8-bit reload timer operation × 2 channels

7/8-bit resolution PWM operation × 2 channels

8-bit PPG operation × 1 channel

8-bit pulse

width counter

8-bit timer operation (overflow output capable)

8-bit reload timer operation (toggled output capable)

8-bit pulse width measurement operation

(Continuous measurement capable, measurement of “H” width/“L” width/from ↑ to ↓/from ↓ to ↑ capable)

16-bit timer/

counter

16-bit timer operation

16-bit event counter operation

8-bit serial I/O

8 bits × 2 channels

LSB first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

8-bit A/D

converter

8-bit resolution × 8 channels

A/D conversion mode (conversion time: 44 instructions)

Sense mode (conversion time: 12 instructions)

Continuous activation by an external activation or an internal timer capable

Reference voltage input

(Continued)

3

MB89640 Series

(Continued)

Part number

MB89643

MB89645

MB89646

MB89647

MB89P647

MB89PV640

Parameter

8-bit D/A

converter

8-bit resolution × 2 channels, R-2R type

External interrupt 1,

External interrupt 2

9 channels

Standby modes

Process

Watch mode, subclock mode, sleep mode, and stop mode

CMOS

Operating

voltage*¹

2.2 V to 6.0 V

2.7 V to 6.0 V

EPROM for use

MBM27C256A

-20TV

*1: Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89643

MB89645

MB89646

MB89647

MB89P647

Package

MB89PV640

FPT-80P-M11

FPT-80P-M06

MQP-80C-P01

×

: Available

× : Not available

Note: For more information about each package, see section “■ External Dimensions.”

4

MB89640 Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

• On the MB89643 register banks 16 to 32 cannot be used.

• On the MB89P647, the program area starts from address 8007^Hbut on the MB89PV640 and MB89647 starts

from 8000H.

(On the MB89P647, addresses 8000H to 8006H comprise the option setting area, option settings can be read

by reading these addresses. On the MB89PV640 and MB89647, addresses 8000H to 8006H could also be

used as a program ROM. However, do not use these addresses in order to maintain compatibility of the

MB89P647.)

• The stack area, etc., is set at the upper limit of the RAM.

• The external areas are used.

2. Current Consumption

• In the case of the MB89PV640, add the current consumed by the EPROM which is connected to the top socket.

• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume

more current than the product with a mask ROM.

• However, the current consumption in sleep/stop modes is the same. (For more information, see sections

“■ Electrical Characteristics” and “■ Example Characteristics.”)

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

Take particular care on the following points:

• A pull-up resistor cannot be set for P40 to P47 and P50 to P57 on the MB89P647.

• For all products, P60 to P67 are available for no pull-up resistor when an A/D converter is used.

• For all products, P50 to P57 are available for no pull-up resistor when a D/A converter is used.

• Options are fixed on the MB89PV640.

5

MB89640 Series

■ PIN ASSIGNMENT

(Top view)

P71/LI1

P70/LI0

P83/INT3

P82/INT2

P81/INT1

P80/INT0

X0A

1

2

3

4

5

6

7

8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P54/BZ

P55/SCK2

P56/SO2

P57/SI2

V^SS

P40

P41

V^CC

P42

P43

P44

P45

P46

X1A

MOD0

MOD1

X0

X1

V^SS

RST

9

10

11

12

13

14

15

16

17

18

19

20

P47

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P30/ADST

P31/SCK1

P32/SO1

P33/SI1

P34/EC

P35/PWC

(FPT-80P-M11)

6

MB89640 Series

(Top view)

P73/LI3

P72/LI2

P71/LI1

P70/LI0

P83/INT3

P82/INT2

P81/INT1

P80/INT0

X0A

1

2

3

4

5

6

7

8

64

P52/PWM

P53/PTO2

P54/BZ

P55/SCK2

P56/SO2

P57/SI2

V^SS

P40

P41

V^CC

P42

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

101

102

103

104

105

106

107

108

109

93

92

91

90

89

88

87

86

85

9

X1A

MOD0

MOD1

X0

X1

V^SS

RST

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P43

P44

P45

P46

P47

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

P30/ADST

P31/SCK1

P32/SO1

P33/SI1

P34/EC

P35/PWC

P36/WTO

P37/PTO1

Each pin inside the dashed line is for the

MB89PV640 only.

(FPT-80P-M06)

(MQP-80C-P01)

• Pin assignment on package top (MB89PV640 only)

Pin no.

81

Pin name

N.C.

VPP

Pin no.

89

Pin name

A2

Pin no.

97

Pin name

N.C.

O4

Pin no.

Pin name

OE

105

106

107

108

109

110

111

112

82

90

A1

98

N.C.

A11

A9

83

A12

A7

91

A0

99

O5

84

92

N.C.

O1

100

101

102

103

104

O6

85

A6

93

O7

A8

86

A5

94

O2

O8

A13

A14

VCC

87

A4

95

O3

CE

88

A3

96

V^SS

A10

N.C.: Internally connected. Do not use.

7

MB89640 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

QFP^*2

QFP^*1

MQFP^*3

11

12

9

13

14

11

12

16

X0

A

C

D

Main clock crystal oscillator pins (Max. 10 MHz)

X1

MOD0

MOD1

RST

Operating mode selection pins

Connect directly to V^CCor VSS.

10

14

Reset I/O pin

This pin is an N-ch open-drain output type with pull-up

resistor, and a hysteresis input type. “L” is output from this

pin by an internal reset source. The internal circuit is

initialized by the input of “L”.

38 to 31

30 to 23

40 to 33

32 to 25

P00/AD0 to

P07/AD7

E

General-purpose I/O ports

Also serve as multiplex pins of lower address output and

data I/O.

P10/A08 to

P17/A15

E

General-purpose I/O ports

Also serve as an upper address output.

22,

21,

18,

15

24,

23,

20,

17

P20/BUFC,

P21/HAK,

P24/CLK,

P27/ALE

G

General-purpose output-only ports

Also serve as a bus control signal output.

20,

19

22,

21

P22/HRQ,

P23/RDY

E

F

General-purpose output-only ports

Also serve as a bus control signal input.

17,

16

19,

18

P25/WR,

P26/RD

General-purpose output-only ports

Also serve as a bus control signal output.

46

48

P30/ADST

General-purpose I/O port

Also serves as an A/D converter external activation. This

port is a hysteresis input type.

45

47

P31/SCK1

F

General-purpose I/O port

Also serves as the clock I/O for the serial I/O 1. This port

is a hysteresis input type.

44,

43

46,

45

P32/SO1,

P33/SI1

General-purpose I/O ports

Also serve as the data output for the serial I/O 1. These

ports are a hysteresis input type.

42

44

P34/EC

General-purpose I/O port

Also serves as the external clock input for the 16-bit timer/

counter. This port is a hysteresis input type.

(Continued)

*1: FPT-80P-M11

*2: FPT-80P-M06

*3: MQP-80C-P01

8

MB89640 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

QFP^*2

QFP^*1

MQFP^*3

41

43

42

41

P35/PWC

F

General-purpose I/O port

Also serves as the measured pulse input for the 8-bit pulse

width counter. This port is a hysteresis input type.

40

39

P36/WTO

P37/PTO1

General-purpose I/O port

Also serves as the toggle output for the 8-bit pulse width

counter. This port is a hysteresis input type.

General-purpose I/O port

Also serves as the toggle output for the 1-channel PWM

timer.

55, 54,

52 to 47

57, 56,

54 to 49

P40 to P47

P50/DA1

L

N-ch medium-voltage open-drain output-only ports

64

66

65

64

63

62

61

60

59

K

N-ch open-drain I/O port

Also serves as a D/A channel 1 output. This port is a

hysteresis input type.

63

P51/DA2

P52/PWM

P53/PTO2

P54/BZ

K

H

I

N-ch open-drain I/O port

Also serves as a D/A channel 2 output. This port is a

hysteresis input type.

62

N-ch open-drain I/O port

Also serves as the PWM output by the two PWM timers.

This port is a hysteresis input type.

61

N-ch open-drain I/O port

Also serves as the toggle output for the 2-channel PWM

timer. This port is a hysteresis input type.

60

N-ch open-drain I/O port

Also serves as a buzzer output. This port is a hysteresis

input type.

59

P55/SCK2

P56/SO2

P57/SI2

N-ch open-drain I/O port

Also serves as the clock I/O for the serial I/O 2. This port

is a hysteresis input type.

58

N-ch open-drain I/O port

Also serves as the data output for the serial I/O 2. This

port is a hysteresis input type.

57

N-ch open-drain I/O port

Also serves as the data input for the serial I/O 2. This port

is a hysteresis input type.

77 to 70

79 to 72 P60/AN0 to

P67/AN7

N-ch open-drain output-only ports

Also serve as the analog input for the A/D converter.

These ports are a hysteresis input type.

2, 1,

80 to 78

4 to 1, 80 P70/LI0 to

P74/LI4

J

Input-only ports

Also serve as external interrupt 1 input. These ports are a

hysteresis input type.

*1: FPT-80P-M11

*2: FPT-80P-M06

*3: MQP-80C-P01

9

MB89640 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

QFP^*2

QFP^*1

MQFP^*3

7

8

9

10

X0A

X1A

V^CC

B

Subclock oscillator pins (32.768 kHz)

53

55

Power supply pin

13, 56

66

15, 58

68

V^SS

Power supply (GND) pin

AV^CC

A/D converter power supply pin

Use this pin at the same voltage as VCC.

67, 68

65

69, 70

67

AVRH, AVRL

DAVC

A/D converter reference voltage input pins

D/A converter power supply pin

Use this pin at the same voltage as V^CC.

69

71

AVSS

Analog circuit power supply pin

Use this pin at the same voltage as VSS.

3 to 6

5 to 8

P83/INT3 to

P80/INT0

J

Input-only ports

Also serve as an external interrupt 2 input. These ports

are a hysteresis input type.

*1: FPT-80P-M11

*2: FPT-80P-M06

*3: MQP-80C-P01

10

MB89640 Series

• External EPROM pins (MB89PV640 only)

Pin no.

Pin name

V^PP

I/O

O

Function

82

“H” level output pin

Address output pins

83

84

85

86

87

88

89

90

91

A12

A7

A6

A5

A4

A3

A2

A1

A0

O

93

94

95

O1

O2

O3

I

Data input pins

96

V^SS

O

I

Power supply (GND) pin

Data input pins

98

99

100

101

102

O4

O5

O6

O7

O8

103

CE

O

ROM chip enable pin

Outputs “H” during standby.

104

105

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

107

108

109

A11

A9

A8

O

Address output pins

110

111

112

A13

A14

V^CC

O

EPROM power supply pin

81

92

N.C.

—

Internally connected pins

Be sure to leave them open.

97

106

11

MB89640 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Standby control signal

Remarks

A

Main clock

X1

X0

• At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

B

Subclock

X1A

X0A

• At an oscillation feedback resistor of approximately

4.5 MΩ/5.0 V

C

D

• At an output pull-up resistor (P-ch) of approximately

R

50 kΩ/5.0 V

• Hysteresis input

P-ch

N-ch

E

• CMOS output

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional

(Continued)

12

MB89640 Series

(Continued)

Type

Circuit

Remarks

F

• CMOS output

• Hysteresis input

R

P-ch

N-ch

• Pull-up resistor optional

• CMOS output

G

R

P-ch

N-ch

• Pull-up resistor optional

H

• N-ch open-drain output

• Hysteresis input

R

P-ch

N-ch

• Pull-up resistor optional

I

• N-ch open-drain output

• Analog input

R

P-ch

N-ch

Analog input

• Pull-up resistor optional

• Hysteresis input

J

R

• Pull-up resistor optional

(Continued)

13

MB89640 Series

(Continued)

Type

Circuit

Remarks

• N-ch open-drain output

K

R

• Hysteresis input

• Analog output

P-ch

N-ch

Analog output

Enable

• Pull-up resistor optional

L

• N-ch open-drain output

• Medium voltage

R

P-ch

N-ch

• Pull-up resistor optional

14

MB89640 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVRH) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVRH = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

15

MB89640 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P647

The MB89P647 is an OTPROM version of the MB89640 series.

1. Features

• 32-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

EPROM mode

(Corresponding addresses on the EPROM programmer)

I/O

0080H

RAM

0180H

Not available

8000H

8007H

0000H

Option area

0007H

PROM

32 KB

EPROM

32 KB

FFFFH

7FFFH

• Precautions

(1) The program area of the MB89P647 is 7 bytes smaller than that of the MB89PV640 and MB89647 to provide

an option area. Note this point during program development.

(2) During normal operation, the option data is read when the option area is read from the CPU.

3. Programming to the EPROM

In EPROM mode, the MB89P647 functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007^Hto 7FFFH (note that addresses 8007H to FFFFH

while operating as internal ROM mode assign to 0007H to 7FFFH in EPROM mode).

Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each

corresponding option, see “7. Setting OTPROM Options.”)

(3) Program with the EPROM programmer.

16

MB89640 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Package

Compatible socket adapter

ROM-80QF-28DP-8L2

FPT-80P-M06

FPT-80P-M11

ROM-80QF2-28DP-8L

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between V^PPand VSS or VCC

and VSS can stabilize programming operations.

17

MB89640 Series

7. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vacancy

Single/dual-

clock system

Oscillation stabilization time

Reset pin

output

1: Yes

Power-on

reset

1: Yes

2: No

00: 2⁴/FCH 10: 2¹⁴/FCH

01: 2¹⁷/FCH 11: 2¹⁸/FCH

Readable and Readable and Readable and 1: Dual clock

writable

0000^H

0001^H

0002^H

0003^H

0004^H

0005^H

0006^H

writable

2: Single clock

2: No

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P67

P66

P65

P64

P63

P62

P61

P60

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P74

P73

P72

P71

P70

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable and Readable and Readable and

writable

Vacancy

P83

P82

P81

P80

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable and Readable and Readable and Readable and

writable writable writable writable

Notes: • Set each bit to 1 to erase.

• Do not write 0 to the vacant bit.

The read value of the vacant bit is 1, unless 0 is written to it.

18

MB89640 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TV

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below.

Package

Adapter socket part number

LCC-32 (Rectangle)

ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

3. Memory Space

Memory space in each mode, such as 32-Kbyte PROM is diagrammed below.

Address

0000H

Single chip

Corresponding addresses on the EPROM programmer

I/O

0080H

0480H

RAM

Not available

8000H

8007H

0000H

Not available

0007H

PROM

32 KB

EPROM

32 KB

7FFF^H

FFFF^H

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007^Hto 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

19

MB89640 Series

■ BLOCK DIAGRAM

Main clock

oscillator

X0

X1

CMOS I/O port

Clock controller

8-bit pulse width

counter

P36/WTO

P35/PWC

Subclock oscillator

(32.768 kHz)

X0A

X1A

16-bit timer/counter

Serial I/O 1

P34/EC

Reset circuit

RST

P33/SI1

P32/SO1

P31/SCK1

P30/ADST

P37/PTO1

P52/PWM

P53/PTO2

P57/SI2

P56/SO2

P55/SCK2

Time-base

timer

2-channel 8-bit

PWM timer

Watch prescaler

Serial I/O 2

Buzzer output

P54/BZ

P51/DA2

P50/DA1

P00/AD0

to P07/AD7

2-channel 8-bit

D/A converter

CMOS I/O ports

8

P10/A08

to P17/A15

N-ch open-drain I/O port

DAVC

Port 4

Medium-voltage N-ch

open-drain output port

MOD0

MOD1

External bus

interface

P40 to P47

P27/ALE

P26/RD

P67/AN7

P66/AN6

P65/AN5

P64/AN4

P63/AN3

P62/AN2

P61/AN1

P60/AN0

AVRH

N-ch open-drain output port

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

8

8-bit A/D converter

CMOS output port

ROM

AVRL

AV ^CC

AV SS

F²MC-8L

CPU

P74/LI4

P73/LI3

P72/LI2

P71/LI1

P70/LI0

CMOS input port

5

4

External interrupt 1

RAM

P83/INT3

P82/INT2

P81/INT1

P80/INT0

External interrupt 2

CMOS input port

Other pins

V ^CC, V SS

20

MB89640 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89640 series offer a memory space of 64 Kbytes for storing all of I/O, data, and

program areas. The I/O area is located at the lowest address. The data area is provided immediately above the

I/O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89640 series is structured as illustrated below.

Memory Space

MB89P647

MB89647

MB89PV640

I/O

MB89643

I/O

MB89645

I/O

MB89646

I/O

0000 ^H

0080 H

0000 H

0080 H

0000 ^H

0080 H

0000 ^H

0080 H

0100 H

0000 ^H

0080 H

I/O

RAM

1 KB

RAM

1 KB

RAM

256 B

RAM

512 B

RAM

768 B

0100 H

0200 H

0100 H

0200 H

0100 H

0180 H

0100 H

0200 H

Register

0200 H

0280 ^H

Not available

0280 ^H

0380 H

0480 H

8000 H

8007 H

0480 H

8000 H

8007 H

External area

Not available

External area

Not available

External area

A000 H

FFFF H

ROM

32 KB

External ROM

32 KB

C000 H

FFFF H

C000 H

E000 H

ROM

24 KB

Not available

ROM

16 KB

ROM

8 KB

FFFF H

FFFF ^H

FFFF H

Note: Since addresses 8000^Hto 8006^Hfor the MB89P647 comprise an option area, do not use this area for the

MB89PV640 and MB89647.

21

MB89640 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

PC

Initial value

FFFD^H

: Program counter

: Accumulator

A

T

Undefined

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

22

MB89640 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

RP

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

23

MB89640 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers. Up to a total of 16 banks can be used on the MB89643 and a total of 32 banks can be used on

the MB89645/646/647/P647/PV640. The bank currently in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

Register Bank Configuration

This address = 0100 H + 8 × (RP)

R0

R1

R2

R3

R4

R5

R6

R7

32 banks

Memory area

24

MB89640 Series

■ I/O MAP

Address

00^H

01^H

02^H

03H

04^H

05^H

06H

07^H

08H

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

11^H

12H

13H

14^H

15H

16H

17^H

18^H

19H

1AH

1B^H

1CH

1DH

1E^H

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

External bus control register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

(W)

PDR2

BCTR

(R/W)

(W)

SYCC

STBC

WDTC

TBCR

WPCR

PDR3

DDR3

PDR4

BUZR

PDR5

PDR6

PDR7

PDR8

System clock control register

Standby control register

Watchdog timer control register

Time-base timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Port 4 data register

Buzzer register

(R/W)

(R)

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Vacancy

(R)

Vacancy

(R/W)

TMCR

TCHR

TCLR

16-bit timer control register

16-bit timer count register (H)

16-bit timer count register (L)

Vacancy

(R/W)

SMR1

SDR1

SMR2

SDR2

Serial 1 mode register

Serial 1 data register

Serial 2 mode register

Serial 2 data register

(Continued)

25

MB89640 Series

(Continued)

Address

20H

Read/write

(R/W)

Register name

ADC1

Register description

A/D converter control register 1

A/D converter control register 2

A/D converter data register

Vacancy

21H

(R/W)

ADC2

22^H

(R/W)

ADCD

23^H

24H

(R/W)

(W)

DACR

DADR1

DADR2

D/A converter control register

D/A converter data register 1

D/A converter data register 2

Vacancy

25^H

26^H

(W)

27H

28^H

(R/W)

(W)

CNTR1

CNTR2

CNTR3

COMR1

COMR2

PCR1

PWM timer control register 1

PWM timer control register 2

PWM timer control register 3

PWM timer compare register 1

PWM timer compare register 2

PWC pulse width control register 1

PWC pulse width control register 2

PWC reload buffer register

Vacancy

29H

2A^H

2BH

2CH

2D^H

2EH

2FH

(W)

(R/W)

PCR2

RLBR

30^H

31H

(R/W)

EIC1

EIC2

EIE2

EIF2

External interrupt 1 control register 1

External interrupt 1 control register 2

External interrupt 2 enable register

External interrupt 2 flag register

Vacancy

32^H

33H

34H

35^Hto 7AH

7BH

7CH

7D^H

7E^H

7FH

Vacancy

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

Note: Do not use vacancies.

26

MB89640 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

AVCC

DAVC

Power supply voltage

VSS – 0.3

V^SS– 0.3

VSS + 7.0

V

*

AVRH must not exceed AV^CC+

0.3 V.

AVRH

VSS + 7.0

A/D converter reference input

voltage

AVRL

V^PP

V^SS– 0.3

VSS – 0.3

VSS + 7.0

13.0

V

AVRL must not exceed AVRH.

MOD1 pin on MB89P647

Program voltage

Input voltage

P52 to P57 with a pull-up

resistor and other input ports

V^I

VSS – 0.3

VCC + 0.3

VSS + 7.0

V

P52 to P57 without a pull-up

resistor

V^I2

P40 to P47 and P52 to P57 with

a pull-up resistor and other

output ports

V^O

VSS – 0.3

VCC + 0.3

V

Output voltage

P40 to P47 without a pull-up

resistor

VSS – 0.3

VSS + 17.0

VSS + 7.0

20

V

V^O2

P52 to P57 without a pull-up

resistor

V^O3

V

“L” level maximum output

current

I^OL

mA

Average value (operating

current × operating rate)

“L” level average output current

I^OLAV

∑IOLAV

∑I^OL

I^OH

4

“L” level total average output

current

Average value (operating

current × operating rate)

40

“L” level total maximum output

current

100

“H” level maximum output

current

–20

Average value (operating

current × operating rate)

“H” level average output current

IOHAV

∑I^OHAV

–4

“H” level total average output

current

Average value (operating

current × operating rate)

–20

“H” level total maximum output

current

∑I^OH

–50

500

mA

Power consumption

P^D

mW

(Continued)

27

MB89640 Series

(Continued)

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

–40

–55

Max.

+85

Operating temperature

Storage temperature

T^A

°C

Tstg

+150

* : Use DAVC and AVCC and VCC set at the same voltage.

Take care so that DAVC and AVCC does not exceed VCC, such as when power is turned on.

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation assurance range*

(MB89643/645/646/647)

2.2*

6.0*

V

V^CC

AVCC

DAVC

Power supply voltage

Normal operation assurance range*

(MB89P647/PV640)

2.7*

6.0*

1.5

3.0

0.0

–40

6.0

AV^CC

2.0

V

Retains the RAM state in stop mode

AVRH

AVRL

T^A

A/D converter reference input

voltage

V

Operating temperature

+85

°C

* : These values vary with the operating frequency and analog assurance range. See Figure 1, “5. A/D Converter

Electrical Characteristics,” and “6. D/A Converter Electrical Characteristics.”

28

MB89640 Series

6

5

Analog accuracy assured in the

VCC = AVCC = DAVC = 3.5 V to 6.0 V range.

Operation assurance range

4

3

2

1

1.0

5.0

10.0

Main clock operating frequency (at an instruction cycle of 4/F^CH) (MHz)

4.0 2.0

1.0 0.8

0.5

0.4

Minimum execution time (instruction cycle) (µs)

Note: The shaded area is assured only for the MB89643/645/646/647.

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F^CH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

29

MB89640 Series

3. DC Characteristics

(AVCC = DAVC = VCC = +5.0 V, AVSS = VSS = 0.0 V, FCH = 10 MHz, FCL = 32.768 kHz, TA = –40°C to +85°C)

Value

Typ.

Symbol

Parameter

Condition

Unit Remarks

Min.

Max.

P00 to P07, P10 to

P17, P22, P23

VCC + 0.3

VIH

0.7 V^CC

V

RST, P30 to P37,

P50, P51, P70 to P74,

P80 to P83

“H” level input

voltage^*1

VCC + 0.3

VIHS

0.8 VCC

V

With pull-up

resistor

P52 to P57

Without pull-

up resistor

VSS + 6.0

0.3 VCC

V^IHS2

0.8 VCC

V

P00 to P07, P10 to

P17, P22, P23

V^SS− 0.3

VIL

V

“L” level input

voltage^*1

RST, P30 to P37,

P50 to P57, P70 to

P74, P80 to P83

V^SS− 0.3

V^ILS

0.2 VCC

Without pull-

up resistor

V^SS− 0.3

V^SS+ 15.0

VSS + 6.0

V^D

P40 to P47

V

Without pull-

up resistor

Open-drain output

pin application

voltage

V^D2

P52 to P57

P60 to P67

V

V^SS− 0.3

VCC + 0.3

V^D3

V^OH

V

P40 to P47, P52 to

P57

With pull-up

resistor

“H” level output

voltage

P00 to P07, P10 to P17,

P20 to P27, P30 to P37

IOH = –2.0 mA

2.4

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P50 to P57,

P60 to P67

V^OL

IOL = +1.8 mA

IOL = +4.0 mA

0.4

V

“L” level output

voltage

V^OL2

RST

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P50 to P57, P70 to P74,

P80 to P83, MOD0,

MOD1

Input leakage

current (Hi-z output I^LI1

leakage current)

Without pull-

up resistor

0.45 V < VI < VCC

±5

µA

(Continued)

30

MB89640 Series

(AV^CC= DAVC = VCC = +5.0 V, AVSS = VSS = 0.0 V, FCH = 10 MHz, FCL = 32.768 kHz, TA = –40°C to +85°C)

Value

Symbol

Parameter

Condition

Unit Remarks

Min.

Typ.

Max.

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P57, P60 to P64,

P70 to P74, P80 to P83,

RST

Without pull-

kΩ

Pull-up resistance

R^PULL

VI = 0.0 V

25

50

100

up resistor

VCC = +5.0 V

—

10

11

20

23

2

mA

• Main clock

operation

I^CC1

MB89P647

mA

• High speed^*2

only

VCC = +3.0 V

1.5

2.5

mA

• Main clock

operation

I^CC2

MB89P647

5

mA

• Low speed^*3

only

V^CC= +5.0 V

• Main clock sleep

• High speed^*2

I^CS1

—

3

7

mA

Power supply

current

VCC

V^CC= +3.0 V

• Main clock sleep

• Low speed^*3

I^CS2

—

1

1.5

50

mA

V^CC= +3.0 V

Subclock sleep

I^CS3

25

µA

TA = +25°C

Subclock stop

ICCH

—

50

1

10

100

3

µA

V^CC= +3.0 V

Subclock operation

(32.768 kHz)

I^CSB

MB89P647

only

mA

VCC = +3.0 V

Watch mode

(32.768 kHz)

I^CCT

VCC

—

15

3

µA

Power supply

current

• Main clock

operation

• High speed^*2

I^A

AVCC

—

1

mA

pF

Other than AVCC,

AVSS, VCC, and VSS

Input capacitance

C^IN

f = 1 MHz

10

*1: Connect MOD0 and MOD1 to VCC or VSS.

*2: High-speed operation is the operation when the system clock is set to the maximum speed by the system clock

select bit at 10-MHz clock.

*3: Low-speed operation is the operation when the system clock is set to the maximum speed by the system clock

select bit at 10-MHz clock.

31

MB89640 Series

4. AC Characteristics

(1) Reset Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

—

48 tXCYL

—

ns

* : tXCYL is the oscillation cycle (1/FCH) to input to the X0 pin.

tZLZH

RST

0.2 V CC

(2) Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Min. Max.

Symbol Condition

Unit

Remarks

Parameter

Power supply rising time

Power supply cut-off time

t^R

—

1

50

—

ms

—

t^OFF

Due to repeated operation

Note: Make sure that power supply rises within the selected oscillation stabilization time.

For example, when the main clock is operating at 10 MHz (F^CH) and the oscillation stabilization time select

option has been set to 2¹⁴/FCH, the oscillation stabilization delay time is 1.6 ms and accordingly the maximum

value of power supply rising time is about 1.6 ms.

Keep in mind that abrupt changes in power supply voltage may cause a power-on reset. If power supply

voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

tOFF

t^R

2.0 V

VCC

0.2 V

32

MB89640 Series

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Typ.

—

Symbol

Condition

Unit

Remarks

Parameter

Clock frequency

Clock cycle time

Min.

1

Max.

10

F^CH

X0, X1

MHz

kHz

ns

F^CL

X0A, X1A

X0, X1

—

32.768

—

t^XCYL

t^LXCYL

100

—

1000

—

X0A, X1A

30.5

µs

—

P^WH

PWL

X0

20

—

30.5

—

10

ns

µs

ns

External clock

Input clock pulse width

P^WHL

PWLL

X0A

X0

tCR

tCF

Input clock rising/falling time

X0 and X1 Timing and Conditions

tXCYL

PWH

PWL

tCR

tCF

0.8 VCC

0.2 VCC

X0

0.2 VCC

Main Clock Conditions

When a crystal

or

ceramic resonator is used.

When an external clock is used.

X0

X1

X0

X1

Open

33

MB89640 Series

X0A and X1A Timing and Conditions

tLXCYL

PWHL

PWLL

tCR

tCF

0.8 VCC

X0A

0.2 VCC

Subclock Conditions

When a crystal

or

ceramic resonator is used.

When an external clock is used.

X0A

X1A

X0A

X1A

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

t^inst= 0.4 µs when operating at FCH =

10 MHz

4/F^CHsystem clock selection 11

8/F^CHsystem clock selection 10

16/F^CHsystem clock selection 01

64/F^CHsystem clock selection 00

µs

t^inst= 0.8 µs when operating at FCH =

10 MHz

µs

Instruction cycle

(minimum execution time)

t^inst

t^inst= 1.6 µs when operating at FCH =

10 MHz

t^inst= 6.4 µs when operating at FCH =

10 MHz

34

MB89640 Series

(5) Recommended Resonator Manufacturers

Sample Application of Piezoelectric Resonator (FAR series)

X0

X1

FAR*

* : Fujitsu Acoustic Resonator

C1 = C2 = 20 pF±8 pF (built-in FAR)

C1

C2

Initial deviation of

FAR frequency

(T^A= +25°C)

Temperature characteristic of

FAR part number

(built-in capacitor type)

Frequency

FAR frequency

(T^A= –20°C to +60°C)

FAR-C4CB-08000-M02

FAR-C4CB-10000-M02

8.00 MHz

±0.5%

10.00 MHz

Inquiry: FUJITSU LIMITED

35

MB89640 Series

Sample Application of Ceramic Resonator

X0

X1

*

C1

C2

Resonator manufacturer*

Kyocera Corporation

Resonator

Frequency

7.68 MHz

8.0 MHz

C1 (pF)

33

C2 (pF)

33

R (kΩ)

KBR-7.68MWS

KBR-8.0MWS

CSA8.00MTZ

33

Murata Mfg. Co., Ltd.

8.0 MHz

30

Inquiry: Kyocera Corporation

• AVX Corporation

North American Sales Headquarters: TEL 1-803-448-9411

• AVX Limited

European Sales Headquarters: TEL 44-1252-770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters: TEL 852-363-3303

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL 1-404-436-1300

• Murata Europe Management GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

(6) Clock Output Timing

(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Cycle time

CLK ↑→ CLK ↓

Symbol

Condition

Unit

Remarks

Min.

Max.

t^XCYL× 2 at 10 MHz

oscillation

t^CYC

CLK

200

—

ns

—

Approx. t^CYL/2 at

10 MHz oscillation

t^CHCL

30

100

tCYC

tCHCL

2.4 V

CLK

0.8 V

36

MB89640 Series

(7) Bus Read Timing

Parameter

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

Min.

Max.

—

RD, A15 to

08, AD7 to 0

1/4 tinst* – 64 ns

1/2 tinst* – 20 ns

1/2 t^inst*

Valid address → RD ↓ time

tAVRL

tRLRH

t^AVDV

ns

RD pulse width

RD

—

ns

AD7 to 0,

A15 to 08

Valid address → read data

time

200

ns No wait

1/2 tinst* – 80 ns

RD ↓ → read data time

RD ↑ → data hold time

RD ↑ → ALE ↑ time

tRLDV

tRHDX

tRHLH

tRHAX

tRLCH

tCLRH

tRLBL

RD, AD7 to 0

AD7 to 0, RD

RD, ALE

120

—

ns No wait

0

ns

—

1/4 tinst* – 40 ns

0

RD, A15 to 08

RD, CLK

RD ↑ → address invalid time

RD ↓ → CLK ↑ time

CLK ↓ → RD ↑ time

RD, CLK

RD ↓ → BUFC ↓ time

RD, BUFC

–5

A15 to 08,

AD7 to 0, BUFC

BUFC ↑→ Valid address time tBHAV

5

—

ns

* : For information on tinst, see “(4) Instruction Cycle.”

2.4 V

CLK

0.8 V

tRHLH

ALE

0.8 V

0.7 V^CC

2.4 V

0.8 V

0.7 VCC

0.3 VCC

AD

0.8 V

0.3 VCC

tAVDV

t^RHDX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

A

tRLCH

tRLDV

tCLRH

tRHAX

tAVRL

tRLRH

2.4 V

RD

0.8 V

tRLBL

tBHAV

2.4 V

BUFC

0.8 V

37

MB89640 Series

(8) Bus Write Timing

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

AD7 to 0, ALE,

A15 to 08

1/4 t^inst*1– 64 ns^*2

Valid address → ALE ↓ time

t^AVLL

—

ns

AD7 to 0, ALE,

A15 to 08

ALE ↓ → address invalid time t^LLAX

5

—

ns *2

1/4 t^inst*1– 60 ns

1/2 t^inst*1– 20 ns

1/2 t^inst*1– 60 ns

1/4 t^inst*1– 40 ns

0

Valid address → WR ↓ time

WR pulse width

tAVWL

tWLWH

tDVWH

tWHAX

tWHDX

tWHLH

tWLCH

tCLWH

tLHLL

WR, ALE

WR

—

ns

Write data → WR ↑ time

WR ↑ → address invalid time

WR ↑ → data hold time

WR ↑ → ALE ↑ time

WR ↓ → CLK ↑ time

CLK ↓ → WR ↑ time

ALE pulse width

AD7 to 0, WR

WR, A15 to 08

AD7 to 0, WR

WR, ALE

WR, CLK

ALE

—

1/4 t^inst*1– 35 ns^*2

1/4 t^inst*1– 30 ns^*2

ALE ↓ → CLK ↑ time

t^LLCH

ALE, CLK

*1: For information on tinst, see “(4) Instruction Cycle.”

*2: These characteristics are also applicable to the bus read timing.

2.4 V

CLK

0.8 V

tLHLL

tLLCH

tWHLH

2.4 V

ALE

AD

A

0.8 V

tAVLL

tLLAX

2.4 V

2.4 V 2.4 V

0.8 V 0.8 V

2.4 V

0.8 V

tWHDX

tDVWH

2.4 V

0.8 V

2.4 V

0.8 V

tCLWH

tWHAX

tWLCH

t^AVWL

tWLWH

2.4 V

WR

0.8 V

38

MB89640 Series

(9) Ready Input Timing

Parameter

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

Min.

60

Max.

—

RDY valid → CLK ↑ time

CLK ↑ → RDY invalid time

t^YVCH

RDY, CLK

ns

*

—

tCHYX

0

—

* : These characteristics are also applicable to the read cycle.

2.4 V

CLK

ALE

AD

A

Address

Data

WR

tYVCH tCHYX

RDY

tYVCH tCHYX

Note: The bus cycle is also extended in the read cycle in the same manner.

39

MB89640 Series

(10) Serial I/O Timing

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

t^SCYC

t^SLOV

t^IVSH

t^SHIX

Condition

Unit Remarks

Parameter

Min.

Max.

Serial clock cycle time

SCK1, SCK2

2 t^inst*

—

µs

SCK1, SO1

SCK2, SO2

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

–200

200

—

ns

Internal shift

clock mode

SI1, SCK1

SI2, SCK2

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑

1/2 t^inst*

µs

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

—

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

SCK1, SCK2

1 tinst*

—

µs

tSLSH

SCK1, SO1

SCK2, SO2

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

t^SLOV

t^IVSH

t^SHIX

0

200

—

ns

µs

External shift

clock mode

SI1, SCK1

SI2, SCK2

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑

1/2 t^inst*

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

—

* : For information on tinst, see “(4) Instruction Cycle.”

40

MB89640 Series

Internal Shift Clock Mode

t^SCYC

2.4 V

SCK1

SCK2

0.8 V

tSLOV

2.4 V

SO1

SO2

0.8 V

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK1

SCK2

0.2 VCC

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

41

MB89640 Series

(11) Peripheral Input Timing

(VCC = +5.0 V±10%, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit Remarks

Parameter

Min.

Max.

PWC, EC,

INT0 to INT3

Peripheral input pulse “H”

width 1

t^ILIH1

2 t^inst*

—

µs

—

PWC, EC,

INT0 to INT3

Peripheral input pulse “L”

width 1

t^IHIL1

t^ILIH2

t^IHIL2

t^ILIH2

t^IHIL2

2 t^inst*

32 tinst*

8 tinst*

—

µs

Peripheral input pulse “H”

width 2

ADST

A/D mode

Peripheral input pulse “L”

width 2

Peripheral input pulse “H”

width 2

Sense mode

Peripheral input pulse “L”

width 2

8 tinst*

* : For information on tinst, see “(4) Instruction Cycle.”

tIHIL1

tILIH1

0.8 VCC

0.2 VCC

PWC

EC

0.2 VCC

INT0 to 3

tIHIL2

tILIH2

0.8 VCC

0.2 VCC

ADST

0.2 VCC

42

MB89640 Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to +6.0 V, FCH = 10 MHz, AVSS = VSS = AVRL = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Parameter

Resolution

Condition

Unit Remarks

Min.

—

Typ.

—

Max.

8

—

bit

Total error

—

±3.0

±1.0

LSB

—

Linearity error

—

Differential linearity

error

—

±0.9

LSB

AVRH = AV^CC

Zero transition voltage V^OT

–1.0

+0.5

+2.0

—

Full-scale transition

V^FST

AVRH – 4.5 AVRH – 1.5 AVRH + 1.5 LSB

voltage

Interchannel disparity

—

0.5

—

LSB

t^inst*

A/D mode conversion

time

44

—

Sense mode

conversion time

—

12

—

t^inst*

—

Analog port input

current

I^AIN

10

µA

AN0 to

AN7

Analog input voltage

Reference voltage

—

0

—

AVRH

AV^CC

V

When A/D

conversion is

activated

AVRH = 5.0 V

I^R

—

100

—

µA

AVRH

Reference voltage

supply current

When A/D

conversion is

stopped

I^RH

1

AVRH = 5.0 V

* : For information on tinst, see “(4) Instruction Cycle.”

43

MB89640 Series

(1) A/D Glossary

• Resolution

Analog changes that are identifiable with the A/D converter.

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

Digital output

Theoretical conversion value

Actual conversion value

1111 1111

1111 _•1110

•

(1 LSB × N + V^OT)

AVRH – AVRL

256

1 LSB =

V^NT– (1 LSB × N + VOT)

Linearity error =

1 LSB

V( N + 1 ) T – VNT

– 1

Differential linearity error =

Total error =

1 LSB

Linearity error

VNT – (1 LSB × N + 1 LSB)

1 LSB

0000 ^•0010

0000 0001

0000 0000

VOT

VNT

V(N + 1)T

VFST

Analog input

(2) Precautions

• Input impedance of the analog input pins

The A/D converter used for the MB89640 series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

44

MB89640 Series

Analog Input Equivalent Circuit

Sample hold circuit

.

C = 33 pF

.

Analog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

contact an external

capacitor of about

0.1 µF.

.

R = 6 kΩ

.

Close for 8 instruction cycles after activating

A/D conversion.

Analog channel selector

• Error

The smaller the | AVRH – AVRL |, the greater the error would become relatively.

6. D/A Converter Electrical Characteristics

(DAVC = VCC = +3.5 V to +6.0 V, FCH=10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Typ.

—

Parameter

Resolution

Symbol

Unit

Remarks

Min.

—

Max.

8

bit

Linearity error

—

±1.0

±0.9

—

LSB

kΩ

—

DAVC = V^CC= 5.0 V

At no load and

Differential linearity error

Output impedance

—

20

I^DINA

I^DINS

—

0.1

mA conversion cycle of

D/A analog power supply

current (for one channel)

5 µs

—

µA

During power down

45

MB89640 Series

■ EXAMPLES CHARACTERISTICS

(1) “L” Level Output Voltage (P00 to P07, P10

to P17, P20 to P27, P30 to P37, P50 to P57,

P60 to P67)

(2) “H” Level Output Voltage (P00 to P07, P10 to

P17, P20 to P27, P30 to P37)

V^OL(V)

0.6

VOL vs. IOL

V^CC–VOH (V)

1.0

VCC–VOH vs. IOH

V^CC= 2.5 V

TA = +25°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 2.5 V

TA = +25°C

0.5

0.4

0.3

0.2

0.1

V^CC= 3.0 V

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

V^CC= 3.0 V

V^CC= 4.0 V

V^CC= 5.0 V

VCC = 6.0 V

0.0

0

0.0

–0.5 –1.0 –1.5 –2.0 –2.5 –3.0

I^OH(mA)

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

(3) “L” Level Output Voltage (P40 to P47)

(4) “H” Level Input Voltage/“L” Level Input Voltage

(CMOS Input)

VIN vs. VCC

V^IN(V)

5.0

VOL vs. IOL

V^OL(mV)

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

TA = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V^CC= 5 V

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

I^OL(mA)

0

1

2

3

4

5

6

7

V^CC(V)

46

MB89640 Series

(5) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)

VIN vs. VCC

V^IN(V)

5.0

TA = +25°C

4.5

4.0

3.5

V^IHS

3.0

2.5

VILS

2.0

1.5

1.0

0.5

0.0

0

1

2

3

4

5

6

7

V^CC(V)

VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level

VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level

(6) Power Supply Current (External Clock)

ICC vs. VCC

I^CCvs. VCC

Main clock operation mode (4/FCH instruction)

Main clock operation mode (64/FCH instruction)

I^CC(mA)

XTAL

15

14

3

2

1

10 MHz

TA = +25°C

13

12

11

10

9

8 MHz

6 MHz

4 MHz

10 MHz

8 MHz

6 MHz

4 MHz

8

7

6

5

4

3

2

2 MHz

1 MHz

2 MHz

1 MHz

1

0

2

3

4

5

6

2

3

4

5

6

V^CC(V)

(Continued)

47

MB89640 Series

(Continued)

ICS1 vs. VCC

I^CS2vs. VCC

Main clock sleep mode (4/FCH instruction)

Main clock sleep mode (64/FCH instruction)

I^CS2(µA)

ICS1 (mA)

4

XTAL

10 MHz

XTAL

10 MHz

1,500

1,000

500

0

TA = +25°C

8 MHz

6 MHz

4 MHz

3

2

1

6 MHz

4 MHz

2 MHz

1 MHz

2 MHz

1 MHz

0

2

3

4

5

6

3

4

5

6

V^CC(V)

ICS3 vs. VCC

Subclock mode

ICS3 (µA)

120

TA = +25°C

Operation

100

80

60

40

20

Sleep

Watch

0

2

3

4

5

6

V^CC(V)

(7) Pull-up Resistance

RPULL vs. VCC

R^PULL(kΩ)

1000

TA = +25°C

100

10

1

2

3

4

5

6

V^CC(V)

48

MB89640 Series

■ INSTRUCTIONS

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

#vct

#d8

#d16

dir: b

rel

@

Register indirect (Example: @A, @IX, @EP)

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

T

TH

TL

IX

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

(Continued)

49

MB89640 Series

(Continued)

Symbol

Meaning

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

CCR

RP

Ri

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

Number of instructions

Number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

50

MB89640 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

51

MB89640 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

A

C

←

C ← A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

52

MB89640 Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

53

MB89640 Series

■ INSTRUCTION MAP

54

MB89640 Series

■ MASK OPTIONS

MB89643

MB89645

MB89646

MB89647

Part number

MB89P647

MB89PV640

No.

Specify when

ordering

Set with EPROM

programmer

Setting not

possible

Specifying procedure

Pull-up resistors

masking

Selectable per pin

(P60 to P67 must be set to

without a pull-up resistor

when an A/D converter is

used. P51 and P50 are

must be set to without a

pull-up resistor when a D/A

converter is used.)

P00 to P07, P10 to P17,

P30 to P37, P40 to P47,

P50 to P57, P60 to P67,

P70 to P74, P80 to P83

Can be set per pin

(Only P40 to P47

and P50 to P57

are without a pull-

up resistor.)

Fixed to without

pull-up resistor

1

2

3

Power-on reset

Fixed to with

power-on reset

With power-on reset

Without power-on reset

Selectable

Setting possible

Main clock oscillation stabilization time

selection (when operating at 10 MHz)

Approx. 2¹⁸/FCH (Approx. 26.2 ms)

Approx. 2¹⁷/FCH (Approx. 13.1 ms)

Approx. 2¹⁴/FCH (Approx. 1.6 ms)

Approx. 2⁴/FCH (Approx. 0 ms)

Fixed to approx.

2¹⁸/FCH (Approx.

26.2 ms)

Selectable

F^CH: Main clock frequency

Reset pin output

With reset output

Without reset output

Fixed to with

reset output

4

5

Selectable

Setting possible

Selection either single- or dual-clock

system

Fixed to dual-

clock system

Single clock

Dual clock

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89647PFM

MB89646PFM

MB89645PFM

MB89643PFM

MB89P647PFM

80-pin Plastic QFP

(FPT-80P-M11)

MB89647PF

MB89646PF

MB89645PF

MB89643PF

MB89P647PF

80-pin Plastic QFP

(FPT-80P-M06)

80-pin Ceramic MQFP

(MQP-80C-P01)

MB89PV640CF

55

MB89640 Series

■ PACKAGE DIMENSIONS

80-pin Plastic QFP

(FPT-80P-M11)

16.00±0.20(.630±.008)SQ

1.50⁺^–0⁰^.^.¹²⁰⁰

.059⁺^–.^.⁰⁰⁰⁰⁴⁸

60

61

41

40

14.00±0.10(.551±.004)SQ

15.00

(.591)

NOM

12.35

(.486)

REF

1 PIN INDEX

80

21

1

Details of "A" part

0.10±0.10

LEAD No.

"A"

0.127^–⁺⁰⁰^.^.⁰⁰²⁵

20

(STAND OFF)

0.65(.0256)TYP

0.30±0.10

(.012±.004)

M

(.004±.004)

0.13(.005)

.005–⁺.^.0⁰0⁰1²

0.50±0.20

(.020±.008)

0.10(.004)

0

10°

C

1994 FUJITSU LIMITED F80016S-1C-2

Dimensions in mm (inches)

56

MB89640 Series

80-pin Plastic QFP

(FPT-80P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

0.05(.002)MIN

(STAND OFF)

64

41

65

40

12.00(.472)

16.30±0.40

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

REF

(.642±.016)

INDEX

80

25

"A"

1

24

LEAD No.

0.80(.0315)TYP

0.35±0.10

(.014±.004)

0.15±0.05(.006±.002)

M

0.16(.006)

Details of "A" part

Details of "B" part

0.25(.010)

"B"

0.10(.004)

0.30(.012)

0

10°

0.18(.007)MAX

0.58(.023)MAX

18.40(.724)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

1994 FUJITSU LIMITED F80010S-3C-2

Dimensions in mm (inches)

57

MB89640 Series

80-pin Ceramic MQFP

(MQP-80C-P01)

18.70(.736)TYP

12.00(.472)TYP

16.30±0.33

(.642±.013)

15.58±0.20

(.613±.008)

1.50(.059)TYP

1.00(.040)TYP

0.80±0.25

(.0315±.010)

INDEX AREA

1.20⁺^–0⁰^.^.²⁴⁰⁰

4.50(.177)

TYP

0.80±0.25

(.0315±.010)

.047⁺^–.^.⁰⁰⁰¹⁸⁶

1.27±0.13

(.050±.005)

INDEX AREA

18.12±0.20

(.713±.008)

22.30±0.33

(.878±.013)

12.02(.473)

TYP

18.40(.724)

REF

10.16(.400)

14.22(.560)

TYP

0.30(.012)

24.70(.972)

TYP

INDEX

6.00(.236)

TYP

0.40±0.10

(.016±.004)

+0.40

1.27±0.13

(.050±.005)

0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.40±0.10

(.016±.004)

1.20^–0.20

1.50(.059)

TYP

+.016

.047^–.008

1.00(.040)

TYP

0.15±0.05 8.70(.343)

(.006±.002) MAX

C

1994 FUJITSU LIMITED M80001SC-4-2

Dimensions in mm (inches)

58

MB89640 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

KAWASAKI PLANT, 4-1-1, Kamikodanaka,

Nakahara-ku, Kawasaki-shi,

Kanagawa 211-8588, Japan

Tel: +81-44-754-3763

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

Fax: +81-44-754-3329

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0005

FUJITSU LIMITED Printed in Japan

59


型号：	MB89647PFM
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总59页 (文件大小：725K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89647PFM [FUJITSU]

相关型号：

MB89650AR

MB89653APF

MB89653APFV

MB89653AR

MB89655APF

MB89655APFV

MB89655AR

MB89656APF

MB89656APFV

MB89656AR

MB89657A

MB89657APF