MB89920 [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有型号: | MB89920 |
厂家: | FUJITSU |
描述: | 8-bit Proprietary Microcontroller |
文件: | 总46页 (文件大小:611K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12526-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89920 Series
MB89923/925/P928/PV920
■ DESCRIPTION
The MB89920 series is a line of single-chip microcontrollers using the F2MC*-8L CPU core which can operate
at low voltage but at high speed.
The microcontrollers in this series contain peripheral functions such as a PWM timer, an input capture/output
compare control counter, an LCD controller/driver, an A/D converter, and a UART.
The MB89920 series can suit a wide range of applications such as analog input conversion, pulse input
measurement/pulse output control, serial communications control, and display control.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• High speed processing at low voltage
Minimum execution time: 0.5 µs/8.0 MHz
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• 8-bit PWM timer: 2 channels (also usable as a reload timer)
• 16-bit input capture: 2 channels / 16-bit output compare: 2 channels
(Continued)
■ PACKAGE
80-pin Plastic QFP
80-pin Ceramic MQFP
(FPT-80P-M06)
(MQP-80C-P01)
MB89920 Series
(Continued)
• 20-bit time-base counter
• UART: 1 channel (with asynchronous transfer mode and 8-bit synchronous serial mode)
• 8-bit serial interface: 1 channel (LSB first/MSB first selectability)
• 10-bit A/D converter: 8 channels
• LCD controller/driver: 28 segments × 4 commons (max. 112 pixels)
• Low-voltage detection reset
• Watchdog timer reset
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from the low-power consumption mode (with edge
detection function)
• Buzzer output/clock output
• Low-power consumption modes:
Stop mode (The software stops oscillation to minimize the current consumption.)
Sleep mode (The CPU stops to reduce current consumption to approx. 1/3 of normal.)
Hardware standby mode (The pin input stops oscillation.)
2
MB89920 Series
■ PRODUCT LINEUP
Part number
MB89925
Mass production products
(mask ROM products)
8 K × 8 bits 16 K × 8 bits
(internal mask ROM) (internal mask ROM)
256 × 8 bits 512 × 8 bits
MB89P928
MB89PV920
MB89923
Parameter
Classification
Piggyback/evaluation
product (for development)
One-time PROM product
(for development)
ROM size
48 K × 8 bits
(internal PROM)
48 K × 8 bits
(external ROM)
RAM size
1024 × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.5 µs/8 MHz
4.5 µs/8 MHz
Ports
I/O ports (CMOS):
I/O ports (N-ch open-drain):
Total:
35 (25 ports also serve as peripherals.)
34 (All also serve as peripherals.)
69
Set with EPROM programmer
Options
Specify with mask options
None
20-bit time-base
timer
20 bits (interval time selection: 4.10 ms, 16.38 ms, 65.54 ms, 262 ms/8 MHz)
Real-time I/O
16-bit timer: operating clock cycle (0.5 µs, 1.0 µs, 2.0 µs, 4.0 µs), overflow interrupt
Input capture: 16 bits × 2 channels, external trigger edge selectability
Output compare: 16 bits × 2 channels
LCD controller/
driver
Common output: 4 (selectable from 2 to 4 by software)
Segment output: 28 (can be switched to ports in 4-pin unit by software)
Bias power supply pins: 3
LCD display RAM size: 14 × 8 bits
Dividing resistor for LCD driving: bult-in (external resistor selectability)
8-bit PWM timer
UART
8 bits × 2-channel reload timer operation
8 bits × 2-channel PWM operation (4 cycles selectable)
8 bits × 1-channel PPG operation (4 oscillation clocks selectable)
Variable data length (7 or 8 bits), internal baud rate generator, error detection function,
full-duplex with internal double buffer, NRZ transmission formation,
Clock synchronous/asynchronous transfer capable
8-bit serial I/O
8 bits, LSB first/MSB first selectability,
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 1.0 µs, 4.0 µs, 16.0 µs)
10-bit A/D
converter
10-bit resolution × 8 channels
A/D conversion mode (conversion time: 16.5 µs (33 instruction cycles))
Sense mode (conversion time: 9.0 µs (18 instruction cycles))
Continuous activation by an internal clock capable
Watchdog timer
Interval time: approx. 130 to 260 ms
Low-voltage
detection reset
Reset activation voltage: 3.0 to 4.3 V
Reset release voltage: 3.1 to 4.5 V
Hardware standby
Buzzer/clock output
External interrupt
Package
Stop the clock oscillation by pin input
1 channel (output a frequency from 1 KHz, 2 KHz, 4 KHz, and divided clock frequency)
4 channels (rising edge/falling edge selectability)
QFP-80
MQFP-80
Operating voltage
EPROM for use
2.2 to 6.0 V*
2.7 to 6.0 V*
2.7 to 6.0 V*
MBM27C512-20TV
(LCC package)
* : The minimum operating voltage varies with conditions such as the operating frequencies, functions, and
development tool.
3
MB89920 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89923
Package
MB89925
MB89PV920
MB89P928
FPT-80P-M06
MQP-80C-P01
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• The stack area, etc., is set at the upper limit of the RAM.
• The external area is used.
2. Current Consumption
• In the case of the MB89PV920, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
4
MB89920 Series
■ PIN ASSIGNMENT
(Top view)
P72/SEG18
1
2
3
4
5
6
7
8
64
P51/SEG1
P50/SEG0
P40/COM0
P41/COM1
P42/COM2
P43/COM3
P44/V1
P45/V2
V3
VCC
AVCC
P73/SEG19
P74/SEG20
P75/SEG21
P76/SEG22
P77/SEG23
P80/SEG24
P81/SEG25
P82/SEG26
P83/SEG27
P90/RTO0
P91/RTO1
P92/CLK
P93/PWM0
VSS
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Lead pitch: 0.80 mm)
(Body size: 20 mm × 14 mm)
AVR
AVSS
P10/AN0
P11/AN1
P12/AN2
P13/AN3
P14/AN4
P15/AN5
P16/AN6
P17/AN7
P00/INT0
P01/INT1
P02/INT2
MODA
X1
X0
P94/PWM1
HST
RST
P95/SCK
P96/SO
P97/SI
(FPT-80P-M06)
(Only for mass production or one-time PROM products)
5
MB89920 Series
(Top view)
P72/SEG18
P73/SEG19
P74/SEG20
P75/SEG21
P76/SEG22
P77/SEG23
P80/SEG24
P81/SEG25
P82/SEG26
P83/SEG27
P90/RTO0
P91/RTO1
P92/CLK
P93/PWM0
VSS
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P51/SEG1
P50/SEG0
P40/COM0
P41/COM1
P42/COM2
P43/COM3
P44/V1
P45/V2
V3
V CC
AV CC
101
102
103
104
105
106
107
108
109
93
92
91
90
89
88
87
86
85
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AVR
AVSS
P10/AN0
P11/AN1
P12/AN2
P13/AN3
P14/AN4
P15/AN5
P16/AN6
P17/AN7
P00/INT0
P01/INT1
P02/INT2
MODA
X1
X0
P94/PWM1
HST
RST
P95/SCK
P96/SO
P97/SI
(MQP-80C-P01)
• Pin assignment on package top (only for piggyback/evaluation product)
Pin no.
81
Pin name
N.C.
A15
Pin no.
89
Pin name
AD2
AD1
AD0
N.C.
O1
Pin no.
97
Pin name
N.C.
O4
Pin no.
105
Pin name
OE/VPP
N.C.
A11
82
90
98
106
83
A12
91
99
O5
107
84
AD7
92
100
101
102
103
104
O6
108
A9
85
AD6
93
O7
109
A8
86
AD5
94
O2
O8
110
A13
87
AD4
95
O3
CE
111
A14
88
AD3
96
VSS
A10
112
VCC
N.C.: Internally connected. Do not use.
(Only for piggyback/evaluation product)
6
MB89920 Series
■ PIN DESCRIPTION
Circuit
type
Pin no.
Pin name
Function
17
18
16
X1
X0
A
Clock oscillator pins
MODA
B
Operation mode selection input pin
Connect this pin to VSS (GND).
20
21
HST
RST
B
C
Hardware standby input pin
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up resistor,
and a hysteresis input type.
“L” is output from this pin by an internal reset source. The internal
circuit is initialized by the input of “L”.
11,
12
P90/RTO0,
P91/RTO1
D
General-purpose I/O ports
A pull-up resistor option is provided. Also serve as an output
compare data output.
13
14
P92/BUZ/CLK
P93/PWM0
D
D
General-purpose I/O port
Also serves as a buzzer/clock output.
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as an 8-bit PWM output.
19
22
P94/PWM1
P95/SCK
D
E
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as an 8-bit PWM output.
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as the clock I/O (SCK) for the serial I/O. The SCK
input is a hysteresis input.
The output type can be switched between N-ch open-drain and
CMOS.
23
P96/SO
D
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as the data output (SO) for the serial I/O. The output
type can be switched between N-ch open-drain and CMOS.
24
25
P97/SI
E
E
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as the data input (SI) for the serial I/O.
P32/UCK
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as a UART clock I/O (UCK). The UCK input is
hysteresis input.
The output type can be switched between N-ch open-drain and
CMOS.
26
P31/UO
D
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as a UART data output (UO).
The output type can be switched between N-ch open-drain and
CMOS.
(Continued)
7
MB89920 Series
(Continued)
Circuit
type
Pin no.
Pin name
P30/UI
Function
27
E
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as a UART data input (UI).
General-purpose I/O ports
A pull-up resistor option is provided.
28 to 31
32
P27 to P24
P23/RTI1
D
E
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as an input capture data input.
33,
34
P22,
P21
General-purpose I/O ports
A pull-up resistor option is provided.
D
E
35
P20/RTI0
General-purpose I/O port
A pull-up resistor option is provided.
Also serves as an input capture data input.
36 to 39
40 to 43
P07 to P04
D
E
General-purpose I/O ports
A pull-up resistor options is provided.
P03/INT3 to
P00/INT0
General-purpose I/O ports
A pull-up resistor options is provided.
Also serve as an external interrupt input (INT0 to INT3).
44 to 51
P17/AN7 to
P10/AN0
G
F
CMOS I/O ports
Also serve as an A/D converter analog input.
57,
58
P45/V2,
P44/V1
LCD driving power supply pins
These pins can be used as an N-ch open-drain general-purpose
I/O when not used as an LCD driving power supply.
59 to 62
63 to 70
71 to 78
P43/COM3 to
P40/COM0
F
F
F
F
F
F
LCD common output pins
These pins can be used as an N-ch open-drain general-purpose
I/O when not used as an LCD common output.
P50/SEG0 to
P57/SEG7
LCD segment output pins
These pins can be used as an N-ch open-drain general-purpose
I/O when not used as an LCD segment output.
P60/SEG8 to
P67/SEG15
LCD segment output pins
These pins can be used as an N-ch open-drain general-purpose
I/O when not used as an LCD segment output.
79,
80
P70/SEG16,
P71/SEG17
LCD segment output pins
These pins can be used as an N-ch open-drain general-purpose
I/O when not used as an LCD segment output.
1 to 6
P72/SEG18 to
P77/SEG23
LCD segment output pins
These pins can be used as an N-ch open-drain general-purpose
I/O when not used as an LCD segment output.
7 to 11
P80/SEG24 to
P83/SEG27
LCD segment output pins
These pins can be used as an N-ch open-drain general-purpose
I/O when not used as an LCD segment output.
52
53
54
55
56
15
AVSS
AVR
AVCC
VCC
A/D converter power supply (GND) pin
A/D converter reference power supply pin
A/D converter power supply pin
Power supply pin
V3
LCD driving power supply pin
Power supply (GND) pin
VSS
8
MB89920 Series
• External EPROM pins (the MB89PV920 only)
Pin no.
Pin name
A15
I/O
Function
82
83
84
85
86
87
88
89
90
91
O
Address output pins
A12
A7
A6
A5
A4
A3
A2
A1
A0
93
94
95
O1
O2
O3
I
Data input pins
96
VSS
O
I
Power supply (GND) pin
Data input pins
98
99
100
101
102
O4
O5
O6
O7
O8
103
CE
O
ROM chip enable pin
Outputs “H” during standby.
104
105
A10
O
O
Address output pin
OE/VPP
ROM output enable pin
Outputs “L” at all times.
107
108
109
A11
A9
A8
O
Address output pins
110
111
112
A13
A14
VCC
O
O
Address output pin
Address output pin
O
EPROM power supply pin
81
92
N.C.
—
Internally connected pins
Be sure to leave them open.
97
106
9
MB89920 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• At an oscillation feedback resistor of approximately
1 MΩ (1 to 8 MHz)
X1
X0
Standby control signal
B
C
• At an output pull-up resistor of approximately 50 KΩ
(5.0 V)
R
P-ch
• Hysteresis input
N-ch
D
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
E
• CMOS output
• CMOS input
• Hysteresis input (peripheral input)
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(Continued)
10
MB89920 Series
(Continued)
Type
Circuit
Remarks
F
• N-ch open-drain I/O
• Also serves as LCD controller/driver common/
segment output.
N-ch
P-ch
N-ch
P-ch
N-ch
G
• CMOS I/O
• Analog input
P-ch
N-ch
Analog input
11
MB89920 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
12
MB89920 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P928
The MB89P928 is an OTPROM version of the MB89920 series.
1. Features
• 48-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C1001A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
EPROM mode
Address
Normal operating mode
(Corresponding addresses on the EPROM programmer)
0000H
0080H
0000H
I/O
Vacancy
(Read value undefined)
0100H
0200H
RAM
Register
0480H
0FE4H
Option area
1000H
Not available
Vacancy
(Read value undefined)
4000H
4000H
Program area
(EPROM)
ROM
FFFFH
FFFFH
Vacancy
(Read value undefined)
1FFFH
13
MB89920 Series
3.Programming to the EPROM
In EPROM mode, the MB89P928 functions equivalent to the MBM27C1001A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C1001A.
(2) Load program data into the EPROM programmer at 0FE4H to FFFFH.
(3) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150 °C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
FPT-80P-M06
ROM-80QF-32DP-8LA
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or VCC
and VSS can stabilize programming operations.
14
MB89920 Series
7. PROM Option Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Vacancy
Vacancy
Vacancy
Oscillation Reset pin
stabilization output
time
Power-on
reset
Vacancy
Vacancy
0FE4H
Readable
Readable
Readable
1: Crystal
0: Ceramic 0: No
1: Yes
1: Yes
0: No
Readable
Readable
P07
P06
P05
P04
P03
P02
P01
P00
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
0FE8H
0FECH
0FF0H
0FF4H
P27
P26
P25
P24
P23
P22
P21
P20
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
P32
P31
P30
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Readable
Readable
Readable
Readable
Readable
P97
P96
P95
P94
P93
P92
P91
P90
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Pull-up
1: No
0: Yes
Vacancy
Vacancy
WDT/low-
voltage
Low-voltage detection Low-voltage Low-voltage Watchdog
voltage
reset
detection
timer (WDT)
control
0FF8H Readable
Readable
1: Register
0: Option
EPROM
1: Yes
0: No
1:
1:
00: —
10: 3.6 V
01: 3.3 V
11: 4.0 V
Automatic Automatic
0: 0:
Prohibited Prohibited
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
0FFCH
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
• Write the same value as each option register to the 3-byte vacant address that follows above option
registers.
Example: In the case of 0FE4H, write the same value to 0FE5H, 0FE6H and 0FF7H.
• This optional information is taken into the OTPROM while the oscillation is being reset. Therefore, if the
hardwarestateisinitiallyshiftedtostandbystateafterthepowersupplyisturnedon, theoptionalinformation
will not be valid during the transition (in a state of the initial value 1).
After the hardware standby state is cleared, the oscillation starts and the optional information becomes
valid.
Note that if the hardware is shifted to the standby or stop state in the course of a normal operation
(oscillation), the contents of the optional register are valid since the option data has already been taken
into the OTPROM.
15
MB89920 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
LCC-32(Rectangle) ROM-32LC-28DP-YG
LCC-32(Square) ROM-32LC-28DP-S
Adapter socket part number
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode is diagrammed below.
Normal operating mode
I/O
Corresponding addresses on the EPROM programmer
Address
0000H
0000H
0080H
RAM
Not available
0480H
4000H
Not available
4000H
PROM
48 KB
EPROM
48 KB
FFFFH
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512.
(2) Load program data into the EPROM programmer at 4000H to FFFFH.
(3) Program to 4000H to FFFFH with the EPROM programmer.
16
MB89920 Series
■ BLOCK DIAGRAM
X0
X1
Operating mode
Oscillator
MODA
control
HST
Clock control
Time-base timer
Watchdog timer
CMOS I/O port
Output compare
Reset circuit
RST
P91/RTO1
P90/RTO0
Low-voltage detection
16-bit
free run counter
RAM
P23/RTI1
P20/RTI0
Input capture
UART
2
F MC-8L
CPU
P32/UCK
P31/UO
P30/UI
ROM
P95/SCK
P96/SO
P97/SI
Serial I/O
4
P80/SEG24 to
P83/SEG27
N-ch open-drain I/O port
28
8
P70/SEG16 to
P77/SEG23
2-channel
8-bit PWM timer
8
P60/SEG8 to
P67/SEG15
P50/SEG0 to
P57/SEG7
8-bit timer #2
8-bit timer #1
P94/PWM1
P93/PWM0
8
LCD controller
/driver
V3
2
2
4
P44/V1,
P45/V2
AVR
4
P40/COM0 to
P43/COM3
10-bit
8
8
A/D converter
P10/AN0 to
P17/AN7
N-ch open-drain I/O port
CMOS I/O port
6
P21 to P22
P24 to P27
Buzzer/clock
output
P92/CLK
4
P04 to P07
CMOS I/O port
4
4
P00/INT0 to
P03/INT3
External interrupt
CMOS I/O port
17
MB89920 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89920 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89920 series is structured as illustrated below.
Memory Space
MB89923
MB89925
MB89P928
MB89PV920
0000H
0080H
0000H
0080H
0000H
0080H
0000H
0080H
I/O
I/O
I/O
RAM
I/O
RAM
RAM
RAM
0100H
0180H
0100H
0100H
0200H
0100H
0200H
Register
Register
Register
Register
0200H
0280H
0480H
0480H
Not available
Not available
Not available
Not available
4000H
4000H
C000H
Program ROM
Program ROM
E000H
FFFFH
ROM
ROM
FFFFH
FFFFH
FFFFH
18
MB89920 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whenthe instructionisan8-bitdataprocessinginstruction,thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
PC
A
: Program counter
: Accumulator
FFFDH
Undefined
Undefined
Undefined
Undefined
Undefined
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
Vacancy Vacancy Vacancy
PS
RP
H
IL1, 0
N
V
C
RP
CCR
19
MB89920 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
20
MB89920 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 16 banks can be used on the MB89925. Up to a total of 16 banks can be
used on the MB89923. The bank currently in use is indicated by the register bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
21
MB89920 Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Read/write
(R/W)
(W)
Register
PDR0
Register description
Port 0 data register
Intial value
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
DDR0
PDR1
Port 0 data direction register
Port 1 data register
Port 1 data direction register
Vacancy
(R/W)
(W)
DDR1
Vacancy
Vacancy
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
STBC
WDTE
TBCR
LVRC
PDR3
DDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
DDR9
PDR2
DDR2
BUZR
ADC1
ADC2
ADCH
ADCL
SMR
Standby control register
Watchdog timer control register
Time-base timer control register
0 0 0 1 X X X X B
X X X X X X X X B
X X X 0 0 0 0 0 B
Low-voltage detection reset control register 0 X 1 1 X 0 0 X B
Port 3 data/peripheral I/O control register
Port 3 data direction register
Port 4 data register
0 0 0 0 – X X X B
– – – – – 0 0 0 B
– – 1 1 1 1 1 1 B
1 1 1 1 1 1 1 1 B
1 1 1 1 1 1 1 1 B
1 1 1 1 1 1 1 1 B
– – – – 1 1 1 1 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X X X X 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X 0 0 0 0 0 0 1 B
– – – – – – X X B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port 9 data direction register
Port 2 data register
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Port 2 data direction register
Buzzer control register
AD converter control register 1
AD converter control register 2
AD converter data register “H”
AD converter data register “L”
Serial mode register
SDR
Serial data register
Vacancy
(W)
ICR1
Port 1 input control register
0 0 0 0 0 0 0 0 B
(Continued)
–: Unused X: Undefined
Note: Do not use vacancies
22
MB89920 Series
Address
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Read/write
(R/W)
(R/W)
(R/W)
(W)
Register
CNTR1
CNTR2
CNTR3
COMR2
COMR1
Register description
Initial value
PWM timer control register 1
PWM timer control register 2
PWM timer control register 3
PWM timer compare register 2
PWM timer compare register 1
Vacancy
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 X 0 0 0 0 B
X X X X X X X X B
X X X X X X X X B
(W)
Vacancy
Vacancy
(R/W)
(R)
TMCR
TCHR
TCLR
Timer control register
Timer count register (H)
Timer count register (L)
Output control register
Output compare register 0 (H)
Output compare register 0 (L)
Output compare register 1 (H)
Output compare register 1 (L)
Input capture control register
Input capture interrupt control register
Input capture register 0 (H)
Input capture register 0 (L)
Input capture register 1 (H)
Input capture register 1 (L)
Vacancy
0 0 X X 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X 0 0 0 X 0 0 0 B
X 0 0 0 0 X 0 0 B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
(R)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R)
OPCR
CPR0H
CPR0L
CPR1H
CPR1L
ICCR
ICIC
ICR0H
ICR0L
ICR1H
ICR1L
(R)
(R)
(R)
Vacancy
(R/W)
(R/W)
EIC1
EIC2
External interrupt control register 1
External interrupt control register 2
Vacancy
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
–: Unused X: Undefined
(Continued)
Note: Do not use vacancies
23
MB89920 Series
(Continued)
Address
40H
Read/write
(R/W)
Register
USMR
USCR
Register description
UART mode register
Initial value
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 1 X X X B
41H
(R/W)
UART control register
UART status register
42H
(R/W)
USTR
(R)
(W)
RXDR
TXDR
UART receiver data register
UART transmitter data register
X X X X X X X X B
X X X X X X X X B
43H
44H
45H
Vacancy
(R/W)
RRDR
Baud rate generator/reload data register
Vacancy
X X X X X X X X B
46H
47H
Vacancy
48 to 5FH
60 to 6DH
70H
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
VRAM
LCR1
LCR2
LCR3
Display data RAM
X X X X X X X X B
0 0 0 0 0 0 0 0 B
0 0 0 – – – – – B
0 0 0 0 0 0 0 0 B
LCD controller/driver control register 1
LCD controller/driver control register 2
LCD controller/driver control register 3
Vacancy
71H
72H
73 to 7BH
7CH
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
1 1 1 1 1 1 1 1 B
1 1 1 1 1 1 1 1 B
1 1 1 1 1 1 1 1 B
7DH
7EH
7FH
–: Unused X: Undefined
Note: Do not use vacancies
24
MB89920 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
VSS – 0.3
VSS – 0.3
VSS + 7.0
VCC + 0.3
V
V
1
AVCC
*
Power supply voltage
AVR must not exceed AVCC + 0.3
V.
AVR
VSS – 0.3
VSS + 7.0
V
VSS + 7.0
VCC + 0.3
V
V
V1 ≤ V2 ≤ V3 *2
LCD power supply voltage
Input voltage
V1 to V3 VSS – 0.3
VI1
VSS – 0.3
P00 to P07, P10 to P17, P20 to
P27, P30 to P32, P90 to P97
VO1
VSS – 0.3
VCC + 0.3
VSS + 7.0
V
V
Output voltage
P40 to P45, P50 to P57, P60 to
P67, P70 to P77, P80 to P83
Must not exceed “V3 + 0.3 V”
VO2
VSS – 0.3
“L” level maximum output
current
IOL
20
4
mA Peak value
mA Average value
mA Peak value
“L” level average output current
IOLAV
∑IOL
“L” level total maximum output
current
100
“L” level total average output
current
∑IOLAV
40
mA Average value
“H” level maximum output
current
IOH
–20
–4
mA Peak value
mA Average value
mA Peak value
“H” level average output current
IOHAV
∑IOH
“H” level total maximum output
current
–50
“H” level total average output
current
∑IOHAV
–20
mA Average value
Power consumption
Operating temperature
Storage temperature
PD
300
+85
mW
°C
TA
–40
–55
Tstg
+150
°C
*1: Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
*2: VCC must not exceed V3.
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Func-
tional operation should be restricted to the conditions as detailed in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
25
MB89920 Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
2.2*1
2.7*1
1.5
Max.
6.0
V
V
V
Normal operation assurance range
MB89PV920/P928
Power supply voltage
VCC
6.0
6.0
Retains the RAM state in stop mode
A/D converter reference input
voltage
AVR
3.0
AVCC
V
V1 ≤ V2 ≤ V3*2
LCD power supply voltage
Operating temperature
V1 to V3
VSS
VSS + 6.0
+85
V
TA
–40
°C
*1: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics.”
*2: VCC must not exceed V3.
6
Analog accuracy assured in the
AVCC = 3.5 V to 6.0 V range
5
Operation assurance range
4
3
2
1
10.0
Clock operating frequency (at an instruction cycle of 4/FC) (MHz)
1.0
5.0
8.0 9.0
2.0
3.0 4.0
6.0 7.0
4.0
0.8
0.5
2.0
Minimum execution time (instruction cycle) (µs)
Note: The shaded area is assured only for the MB89923/925.
Figure 1 Operating Voltage vs. Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
26
MB89920 Series
3. DC Characteristics
(VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
Parameter
bol
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
P00 to P07, P10 to P17,
P20 to P27, P30 to P32,
P40 to P45, P50 to P57,
P60 to P67, P70 to P77,
P80 to P83, P90 to P97
VCC +
0.3
VIH
—
—
—
—
—
0.7 VCC
—
V
V
V
V
V
“H” level input
voltage
Peripheral input
of the port 0, 2,
3, and 9
VCC +
0.3
RST, MODA, HST
VIHS
0.8 VCC
—
—
—
—
P00 to P07, P10 to P17,
P20 to P27, P30 to P32,
P40 to P45, P50 to P57,
P60 to P67, P70 to P77,
P80 to P83, P90 to P97
VSS −
0.3
VIL
0.3 VCC
0.2 VCC
“L” level input
voltage
Peripheral input
of the port 0, 2,
3, and 9
VSS −
0.3
RST, MODA, HST
VILS
Open-drain
output
pin application
P40 to P45, P50 to P57,
P60 to P67, P70 to P77,
P80 to P83*1
VSS −
0.3
VSS +
6.0
VD
voltage
P00 to P07, P10 to P17,
P30 to P32, P90 to P97
VOH1
IOH = –2.0 mA
IOH = –5.0 mA
4.0
2.4
—
—
—
—
V
V
“H” level output
voltage
P20 to P27
VOH2
P00 to P07, P10 to P17,
P30 to P32, P40 to P45,
P50 to P57, P60 to P67,
P70 to P77, P80 to P83,
P90 to P97
VOL1
IOL = 4.0 mA
—
—
0.4
V
“L” level output
voltage
P20 to P27
RST
VOL2
VOL3
IOL = 5.0 mA
IOL = 4.0 mA
—
—
—
—
0.4
0.4
V
V
Input leakage
current
(Hi-z output
leakage
P00 to P07, P10 to P17,
P20 to P27, P30 to P32,
P40 to P45, P50 to P57,
P60 to P67, P70 to P77,
P80 to P83, P90 to P97,
MODA
0.45 V < VI <
VCC
Without pull-
up resistor
ILI1
—
—
±5
µA
kΩ
current)
Pull-up
resistance
Without pull-
up resistor
P00 to P07, P20 to P27,
P30 to P32, P90 to P97
RPULU
VI = 0.0 V
25
50
100
(Continued)
27
MB89920 Series
(VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
Parameter
bol
Pin
Condition
VCC = 5.0 V
Unit Remarks
Min.
Typ.
Max.
ICC
—
12
20
mA tinst = 0.5 µs
Sleep mode
mA
ICCS
ICCH
VCC
VCC = 5.0 V
—
—
3
7
1
tinst = 0.5 µs
TA = +25°C
—
µA Stop mode
when A/D
conversion is
activated
Power supply
current*2
IA
—
6
8
mA
AVCC
when A/D
conversion is
stopped
IAH
—
—
1
µA
TA = +25°C
LCD divided
resistance
RLCD
Between V3 and VSS
COM0 to 3
200
—
300
—
450
2.5
kΩ
kΩ
COM0 to 3 output
impedance
RVCOM
V1 to V 3 = 5.0 V
V1 to V 3 = 5.0 V
SEG0 to 27
output
RVSEG
SEG0 to 27
—
—
15
kΩ
impedance
LCD controller/
driver leakage
current
V1 to V3, COM0 to
3,
SEG0 to 27
ILCDL
V1 to V 3 = 5.0 V
f = 1 MHz
—
—
—
±1
µA
Other than AVCC,
AVSS, VCC, and VSS
Input capacitance CIN
10
—
pF
*1: VD must not exceed V3.
*2: The measurement conditions of power supply current are as follows: the external clock and TA = +25°C.
In the case of the MB89PV920, the current consumed by the connected EPROM and ICE is not included.
Note: For pins which serve as the LCD and ports (P40 to P45, P50 to P57, P60 to P67, P70 to P77, and P80 to
P83), see the port parameter when these pins are used as ports and the LCD parameter when they are used
as LCD pins.
28
MB89920 Series
4. AC Characteristics
(1) Reset Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
Max.
RST “L” pulse width
tZLZH
—
48 tHCYL
—
ns
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Min. Max.
Symbol Condition
Unit
Remarks
Power supply rising time
Power supply cut-off time
tR
—
1
50
—
ms
ms
Power-on reset function only
Due to repeated operations
—
tOFF
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tR
tOFF
2.0 V
0.2 V
0.2 V
0.2 V
VCC
29
MB89920 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
FC
Pin
Condition
Unit
Remarks
Parameter
Min.
1
Max.
8
Clock frequency
Clock cycle time
X0, X1
X0, X1
MHz
ns
tXCYL
125
1000
PWH
PWL
—
Input clock pulse width
X0
X0
20
—
—
ns
ns
External clock
External clock
Input clock rising/falling
time
tCR
tCF
10
X0 and X1 Timing and Conditions
tXCYL
PWH
PWL
tCF
tCR
0.8 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Clock Conditions
When a crystal
or
ceramic resonator is used
When an external clock is used
X0
X1
X0
X1
FC
Open
C1
C2
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
Remarks
Instruction cycle
(minimum execution time)
(4/FC) tinst = 0.5 µs when operating at
FC = 8 MHz
tinst
4/FC
µs
30
MB89920 Series
(5) Serial I/O Timing
Parameter
(AVCC = VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
SCK
Condition
Unit Remarks
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
SCK
200
—
Internal shift
clock mode
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External shift
clock mode
SCK, SO
SI, SCK
SCK, SI
200
—
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
SI
0.2 VCC
External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
2.4 V
0.8 V
SO
tIVSH
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
SI
31
MB89920 Series
(6) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin
Unit Remarks
Parameter
Min.
2 tinst*
2 tinst*
Max.
—
Peripheral input “H” pulse width 1
Peripheral input “L” pulse width 1
tILIH1
tIHIL1
INT0 to INT3, RTI0, 1
INT0 to INT3, RTI0, 1
—
—
—
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1
tILIH1
RTI0, 1
INT0 to 3
0.8 VCC
0.8 V CC
0.2 VCC
0.2 VCC
32
MB89920 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 8 MHZ, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
bol
Parameter
Resolution
Pin
Condition
Unit
Min.
—
Typ.
—
Max.
10
bit
Linearity error
—
—
±2.0
±1.5
±3.0
LSB
LSB
LSB
mV
—
—
Differential linearity error
Differential total error
—
—
—
—
AVCC = AVR =
VCC
AN0 to AN7
AN0 to AN7
AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
Zero transition voltage VOT
Full-scale transition
VFST
AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB
mV
voltage
Interchannel disparity
—
—
—
—
—
—
—
4
LSB
µs
µA
V
—
—
A/D mode conversion time
Analog port input current
Analog input voltage
Reference voltage
16.5
10
AN0 to AN7
AN0 to AN7
AVR
At 8-MHZ oscillattion
VAIN
—
0.0
0.0
AVR
AVCC
—
V
Reference voltage
supply current
IR
AVR
AVR = 5.0 V
—
200
µA
Precautions: • The smaller | AVR – AVSS |, the greater the error would become relatively.
• The output impedance of the external circuit for the analog input must satisfy the following conditions:
Output impedance of the external circuit < Approx. 10 kΩ
If the output impedance of the external circuit is too high, an analog voltage sampling time might be
insufficient (sampling time = 7.5 µs at 8 MHz oscillation).
An analog input equivalent circuit is shown below.
Sample hold circuit
R ≤ 10 kΩ is
recommended.
.
C = 60 pF
.
AN
Comparator
.
R = 3 kΩ
.
Analog channel selector
Close for approx. 15 instruction cycles
after activating A/D conversion.
If R > 10 kΩ, it is recommended
to connect an external capacitor
of approx. 0.1 µF.
Microcontroller’s internal circuit
Since the A/D converter contains sample hold circuit, the level of the analog input pin might not stabilize within the
sampling period after A/D activation, resulting in inaccurate A/D conversion values, if the input impedance to the
analog pin is too high. Be sure to maintain an appropriate input impedance to the analog pin.
It is recommended to keep the input impedance to the analog pin not exceed 10 kΩ. If it exceeds 10 kΩ, it is
recommended to connect a capacitor of about 0.1 µF for the analog input pin.
ExceptforthesamplingperiodafterA/Dactivation, theinputleakagecurrentoftheanaloginputpinislessthan10µA.
33
MB89920 Series
(1) A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error
The difference between theoretical and actual conversion values, caused by the zero transition error, full-scale
transition error, linearity error, quantization error, and noise.
Theoreticall I/O characteristics
VFST
Total error
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
value
1.5 LSB
{1 LSB × N + 0.5 LSB}
004
003
002
001
004
003
002
001
VNT
VOT
Actual conversion
value
1 LSB
Theoretical value
0.5 LSB
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VFST − VOT
VNT
−
{1 LSB × N + 0.5 LSB}
1 LSB =
(V)
Total error of digital output N =
1022
1 LSB
(Continued)
34
MB89920 Series
(Continued)
Zero transition error
Full-scale transition error
Theoretical value
004
003
002
001
Actual conversion
3FF
3FE
3FD
3FC
value
Actual conversion
value
VFST (Actual
measured value)
Theoretical
value
Actual conversion
value
Actual conversion
value
VOT (Actual measured value)
Analog input
AVSS
AVR
Analog input
Linearity error
Differential linearity error
3FF
3FE
3FD
Theoretical value
Actual conversion
value
N + 1
{1 LSB × N + VOT}
Actual conversion
value
V(N + 1)T
VFST (Actual
measured
value)
N
VNT
004
003
002
001
N – 1
N – 2
VNT
Actual conversion
value
Actual conversion
value
Theoretical value
VOT (Actual measured value)
Analog input
AVSS
AVR
AVSS
AVR
– 1
Analog input
VNT – {1 LSB × N + VOT}
V(N+1)T – VNT
Linearity error of digital output N =
Differential linearity error of digital output N =
1 LSB
1 LSB
35
MB89920 Series
6. Low-voltage Detection Reset
Parameter
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit Remarks
Min.
3.00
3.30
3.70
3.10
3.40
3.80
0.10
0.3
Max.
3.60
3.90
4.30
3.80
4.10
4.50
—
VDL1
VDL2
VDL3
VDH1
VDH2
VDH3
∆V
V
V
Voltage detected at power supply
voltage drop
V
1
*
V
Voltage detected at power supply
voltage rise
V
V
Hysteresis width
V
Reset ignore time
tL
—
µs
ns
µs
V/µs
Reset sense time
tLW
16 tXCYL
—
—
Reset detection deley time
Voltage regulation (V∆/t∆)
tD
2.0
VCR
—
0.10
*1: VDH and VDL can be set for the MB89923 and MB89925 by mask options; for the MB89PV920 and MB89P928
by registers.
Power supply voltage
VCC
t∆
VDH*
V∆
∆V
VDL*
tD
tOSC
tOSC
tD
RUN
RESET
tOSC oscillation stabilization time 219 = 65.5 ms (f = 8 MHz)
Power supply voltage
VCC
less than tL
over than tLW
VDH*
VDL*
t
t
RUN
RESET
Not reset
Reset
36
MB89920 Series
■ INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
#vct
#d8
#d16
dir: b
rel
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
Register indirect (Example: @A, @IX, @EP)
@
A
AH
AL
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
Lower 8 bits of accumulator A (8 bits)
T
TH
TL
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
IX
EP
PC
SP
PS
dr
CCR
RP
Ri
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
( × )
(( × ))
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic: Assembler notation of an instruction
~:
#:
The number of instructions
The number of bytes
Operation: Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH prior to the instruction executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
37
MB89920 Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
AL
AL
–
–
–
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
–
–
F0
Note During byte transfer to A, T ← A is restricted to low bytes.
Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
38
MB89920 Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
C
A
A
←
←
C
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
(A) − (Ri)
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
39
MB89920 Series
(Continued)
Mnemonic
~
#
Operation
(A) ← (AL) ( (EP) )
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
40
MB89920 Series
■ INSTRUCTION MAP
41
MB89920 Series
■ MASK OPTIONS
MB89923
MB89925
Part number
MB89P928
MB89PV920
No.
Specify when
ordering
Set with EPROM
programmer
Setting not
possible
Specifying procedure
masking
P00 to P07, P20 to P27,
P30 to P32, P90 to P97
Pull-up resistors
1
2
P00 to P07, P20 to P27,
P30 to P32, P90 to P97
Can be set per pin No pull-up resistor
: Selectable by pin
Power-on reset
With power-on
Power-on reset provided
No power-on reset
Selectable
Can be set
reset
Oscillation stabilization time slection (at 8 HZ)
Cystal oscillator
(32.8 ms/8MHZ)
Ceramic oscillator
(2.05 ms/8 MHZ)
Crystal oscillator
Can be set
3
Selectable
(32.8 ms/8 MHZ)
Reset pin output
Reset output provided
No reset output
4
5
6
7
Selectable
Selectable
Selectable
Selectable
Can be set
Can be set
Can be set
Can be set
With reset output
Watchdog timer
Inactive by default
(Can be activated
by software)
Activation prohibited
Automatic activation
Low-voltage detection reset circuit
Activation prohibited
Inactive by default
(Can be activated
by software)
Automatic activation
Low-voltage detection reset output
Output disabled
Inactive by default
(Can be activated
by software)
Output enabled
Low-voltage detection voltage
3.3 V ± 0.3 V
8
9
Selectable
Selectable
Can be set
Can be set
Register setting
3.6 V ± 0.3 V
4.0 V ± 0.3 V
Low-voltage detection reset/watchdog
timer function selection
Register setting valid
Fixed to register
setting
Option setting valid
42
MB89920 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89923PF
MB89925PF
MB89P928PF
80-pin Plastic QFP
(FPT-80P-M06)
80-pin Ceramic MQFP
(MQP-80C-P01)
MB89PV920CF
43
MB89920 Series
■ PACKAGE DIMENSIONS
80-pin Plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
0.05(.002)MIN
(STAND OFF)
64
41
65
40
12.00(.472)
REF
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
16.30±0.40
(.642±.016)
INDEX
80
25
"A"
1
24
LEAD No.
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.16(.006)
Details of "A" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10°
0.18(.007)MAX
0.58(.023)MAX
18.40(.724)REF
0.80±0.20
(.031±.008)
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F80010S-3C-2
Dimensions in mm (inches)
44
MB89920 Series
80-pin Ceramic MQFP
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.50(.059)TYP
1.00(.040)TYP
0.80±0.25
(.0315±.010)
INDEX AREA
1.20+–00..2400
4.50(.177)
TYP
.047 +–..000186
0.80±0.25
(.0315±.010)
1.27±0.13
(.050±.005)
INDEX AREA
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.40(.724)
REF
10.16(.400)
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
TYP
INDEX
6.00(.236)
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20+–00..2400
.047+–..000186
1.50(.059)
TYP
1.00(.040)
TYP
0.15±0.05 8.70(.343)
(.006±.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches)
45
MB89920 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0005
FUJITSU LIMITED Printed in Japan
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