MB89P173_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12518-8E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89170/170A/170L Series

MB89173/P173/174A/P175A/PV170A

MB89173L/174L

■ DESCRIPTION

The MB89170/170A/170L series has been developed as a general-purpose version of the F²MC*-8L family

consisting of proprietary 8-bit, single-chip microcontrollers.

In addition to a compact instruction set, the microcontrollers contain a great variety of peripheral functions such

as timers, a serial interface, a DTMF generator, and external interrupts, making it suitable for circuit control

such as required in telephones.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• F²MC-8L family CPU core

• Maximum memory space: 64 Kbytes

• Minimum execution time/interrupt processing time

MB89170 series: 1.1 µs/10 µs (at 3.58 MHz oscillation)

MB89170A/170L series: 0.6 µs/5.4 µs (at 7.16 MHz oscillation)

• Dual-clock control system (MB89170/170A series only)

• I/O ports: max. 37 ports

• 21-bit timebase counter

• Watch prescaler (MB89170/170A series only)

• Watchdog timer

• 8/16-bit timer/counter: 1 channel

(Continued)

■ PACKAGE

48-pin Plastic QFP

48-pin Ceramic MQFP

(MQP-48C-P01)

(FPT-48P-M16)

MB89170/170A/170L Series

(Continued)

• 8-bit serial I/O: 1 channel

• DTMF generator (MB89170/170A series only)

Selectable oscillation frequency (MB89170A series only)

• External interrupt 1: 3 channels

Three channels are independent and capable of using for wake-up from low-power consumption modes (with

an edge detection function).

• External interrupt 2 (wake-up): 8 channels

Eight channels are independent and capable of using for wake-up from low-power consumption modes (with

an “L” level detection function).

• Low-power consumption modes(stop mode, sleep mode, watch mode, and subclock mode)

• CMOS technology

2

MB89170/170A/170L Series

■ PRODUCT LINEUP

Part number

MB89173

MB89P173

MB89174A

MB89P175A

MB89PV170A

Item

Classification

Mass-produced One-time PROM Mass-produced One-time PROM Piggyback/

evaluation

product

(EPROM product)

product (for

evaluation and

development)

(mask ROM

product)

(EPROM product) (mask ROM

product)

ROM size

8 K × 8 bits

(internal mask

ROM)

8 K × 8 bits

(internal PROM,

to be programmed ROM)

with general-

12 K × 8 bits

(internal mask

16 K × 8 bits

(internal PROM,

to be programmed

with general-

32 K × 8 bits

(external ROM)

purpose EPROM

programmer)

purpose EPROM

programmer)

RAM size

384 × 8 bits

The number of instructions:

512 × 8 bits

1 K × 8 bits

CPU functions

136

Instruction bit length:

Instruction length:

Data bit length:

8 bits

1 to 3 bytes

1, 8, 16 bits

Minimum execution time:

Minimum instruction execution time:

1.1 to 17.6 µs at 3.58 MHz, 61 µs at 32.768 kHz 0.6 to 9.6 µs at 7.16 MHz, 61 µs at 32.768 kHz

Interrupt processing time:

5.4 to 86.4 µs at 7.16 MHz, 562.5 µs at 32.768 kHz

10 to 160

µs at 3.58 MHz, 562.5

µs at 32.768 kHz

Ports

Output ports (N-ch open-drain):

Output ports (CMOS):

I/O ports (CMOS):

Total:

5

8

24 (16 ports also serve as peripherals.)

37

8/16-bit timer/

counter

8 bits × 2 ch or 16 bits × 1 ch, capable of rectangular wave output

One clock selectable from four operation clocks

(one external shift clock, three internal shift clocks: 2.2 µs, 35.2 µs, 563.2 µs; when operating at 3.58 MHz)

8-bit serial I/O

8 bits

LSB/MSB first selectable

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 2.2 µs, 8.8 µs, 35.2 µs; when operating at 3.58 MHz)

DTMF generator

All ITU-T (the old name: CCITT)

tones selectable as output

Fixed to oscillation frequency(3.58 MHz)

All ITU-T (the old name: CCITT) tones selectable as output

Selectable oscillation frequency(3.58 MHz or 7.16 MHz)

External interrupt 1

3 independent channels (selectable edge, interrupt vector, source flag)

Rising/falling/both edges selectable

Used also for wake-up from the watch/stop/sleep mode.

(Edge detection is also permitted in the watch/stop mode.)

External interrupt 2

(wake-up)

8 independent channels (“L” level interrupt)

Used also for wake-up from the watch/stop/sleep mode.

(Edge detection is also permitted in the watch/stop mode.)

Standby mode

Process

Sleep mode, stop mode, watch mode, and subclock mode

CMOS

Operating voltage*

EPROM for use

2.2 V to 6.0 V

2.7 V to 6.0 V

2.2 V to 6.0 V

2.7 V to 6.0 V

MBM27C256A

-20TVM

* : Varies with conditions such as the operating frequency and the assurance range for the DTMF generator.(See

“■ Electrical Characteristics.”)

3

MB89170/170A/170L Series

Part number

MB89173L

Item

MB89P174L

Classification

Mass-produced product

(mask ROM product)

ROM size

8 K × 8 bits

(internal mask ROM)

12 K × 8 bits

(internal mask ROM)

RAM size

384 × 8 bits

512 × 8 bits

CPU functions

The number of instructions:

Instruction bit length:

Instruction length:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

Data bit length:

Minimum instruction execution time: 0.6 to 9.6 µs at 7.16 MHz,

Interrupt processing time:

5.4 to 86.4 µs at 7.16 MHz,

Ports

Output ports (N-ch open-drain):

Output ports (CMOS):

I/O ports (CMOS):

Total:

5

8

24 (16 ports also serve as peripherals.)

37

8/16-bit timer/

counter

8 bits × 2 ch or 16 bits × 1 ch, capable of rectangular wave output

One clock selectable from four operation clocks

(one external shift clock, three internal shift clocks: 2.2 µs, 35.2 µs, 563.2 µs; when operating at 3.58 MHz)

8-bit serial I/O

8 bits

LSB/MSB first selectable

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 2.2 µs, 8.8 µs, 35.2 µs; when operating at 3.58 MHz)

DTMF generator

External interrupt 1

3 independent channels (selectable edge, interrupt vector, source flag)

Rising/falling/both edges selectable

Used also for wake-up from the stop/sleep mode.

(Edge detection is also permitted in the stop mode.)

External interrupt 2

(wake-up)

8 independent channels (“L” level interrupt)

Used also for wake-up from the stop/sleep mode.

(Edge detection is also permitted in the stop mode.)

Standby mode

Process

Sleep mode, stop mode

CMOS

Operating voltage*

EPROM for use

2.2 V to 6.0 V

* : Varies with conditions such as the operating frequency and the assurance range for the DTMF generator.(See

“■ ELECTRICAL CHARACTERISTICS.”)

4

MB89170/170A/170L Series

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89173

MB89P173

MB89174A

MB89P175A

MB89173L

MB89174L

Package

MB89PV170A

FPT-48P-M16

MQP-48C-P01

×

: Available

× : Not available

Note: For more information about each package, see “■ Package Dimensions.”

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

2. Current Consumption

In the case of the MB89PV170A, added is the current consumed by the EPROM which is connected to the top

socket.

3. Mask Options

Functions that can be selected as options and how to designate these options vary with the product.

Before using options, check “■ Mask Options.”

Take particular care on the following points:

• Pull-up resistor option cannot be set for P40 to P44 on the MB89P175A.

• Each option is fixed on the MB89PV170A.

5

MB89170/170A/170L Series

■ PIN ASSIGNMENT

(Top view)

DTMF

RST

MOD0

MOD1

X0

X1

V^CC

X0A

X1A

P27

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

P36/INT2

P37/BZ

P00/INT20

P01/INT21

P02/INT22

P03/INT23

P04/INT24

P05/INT25

P06/INT26

P07/INT27

P10

MB89170/170A series

9

10

11

12

P26

P25

P11

(FPT-48P-M16)

(TOP VIEW)

N.C.

RST

MOD0

MOD1

X0

X1

V^CC

N.C.

P27

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

P36/INT2

P37/BZ

P00/INT20

P01/INT21

P02/INT22

P03/INT23

P04/INT24

P05/INT25

P06/INT26

P07/INT27

P10

MB89170L series

9

10

11

12

P26

P25

P11

(FPT-48P-M16)

6

MB89170/170A/170L Series

(Top view)

DTMF

RST

MOD0

MOD1

X0

X1

V^CC

X0A

X1A

P27

1

2

3

4

5

6

7

8

36

35

34

33

32

31

30

29

28

27

26

25

P36/INT2

P37/BZ

P00/INT20

P01/INT21

P02/INT22

P03/INT23

P04/INT24

P05/INT25

P06/INT26

P07/INT27

P10

69

70

71

72

73

74

75

76

60

59

58

57

56

55

54

53

9

10

11

12

P26

P25

P11

(MQP-48C-P01)

• Pin assignment on package top (MB89PV170A only)

Pin no.

49

Pin name

V^PP

Pin no.

57

Pin name

N.C.

A2

Pin no.

65

Pin name

O4

Pin no.

73

Pin name

OE

50

A12

A7

58

66

O5

74

N.C.

A11

A9

51

59

A1

67

O6

75

52

A6

60

A0

68

O7

76

53

A5

61

O1

69

O8

77

A8

54

A4

62

O2

70

CE

78

A13

A14

VCC

55

A3

63

O3

71

A10

N.C.

79

56

N.C.

64

V^SS

72

80

N.C.: Internally connected. Do not use.

7

MB89170/170A/170L Series

■ PIN DESCRIPTION

Pin no.

Pin name

Circuit type

Function

Main clock crystal oscillator pins

QFP^*1

MQFP^*2

5

6

8

9

3

4

2

X0

A

X1

X0A

X1A

B

C

D

Subclock oscillation pins (32.768 kHz)

MOD0

MOD1

RST

Operation mode selecting pins

Connect directly to V^CCor VSS.

Reset I/O pin

This pin is of an N-ch open-drain output type with pull-up

resistor and of hysteresis input type.

“L” is output from this pin by an internal reset source (optional

function).

The internal circuit is initialized by the input of “L”.

34 to 27

P00/INT20 to

P07/INT27

E

General-purpose I/O ports

Also serve as an external interrupt 2 input (wake-up function).

External interrupt input is a hysteresis input.

26 to 20, 18 P10 to P17

F

H

G

General-purpose I/O ports

17 to 10

42

P20 to P27

P30/SCK

General-purpose output ports

General-purpose I/O port

Also serves as the clock I/O for the 8-bit serial I/O.

This port is of hysteresis input type.

41

40

39

P31/SO

P32/SI

G

General-purpose I/O port

Also serves as the data output for the 8-bit serial I/O.

This port is of hysteresis input type.

General-purpose I/O port

Also serves as the data input for the 8-bit serial I/O.

This port is of hysteresis input type.

P33/EC

General-purpose I/O port

Also serves as an external clock input for a 8-bit timer/

counter.

This port is of hysteresis input type.

38

P34/TO/INT0

G

General-purpose I/O port

Also serves as the overflow output for the 8-bit timer/counter

and an external interrupt 1 input.

This port is of hysteresis input type.

36,

37

P36/INT2,

P35/INT1

General-purpose I/O ports

Also serve as an external interrupt 1 input.

These ports are of hysteresis input type.

(Continued)

*1: FPT-48P-M16

*2: MQP-48C-P01

Notes: On the MB89170L series, DTMF pin (Pin No.:1), X0A pin (Pin No.:8) and X1A pin (Pin No.:9) are N.C. pins.

Please connect them with GND.

8

MB89170/170A/170L Series

(Continued)

Pin no.

Pin name

P37/BZ

Circuit type

Function

QFP^*1

MQFP^*2

35

G

General-purpose I/O port

Also serves as a buzzer output.

This port is of hysteresis input type.

48 to 44

P40 to P44

DTMF

V^CC

I

N-ch open-drain output ports

DTMF signal output pin

Power supply pin

1

7

J

—

19, 43

V^SS

Power supply (GND) pin

*1: FPT-48P-M16

*2: MQP-48C-P01

Notes: On the MB89170L series, DTMF pin (Pin No.:1), X0A pin (Pin No.:8) and X1A pin (Pin No.:9) are N.C. pins.

9

MB89170/170A/170L Series

• External EPROM pins (the MB89PV170A only)

Pin no.

Pin name

I/O

Function

MQFP^*

49

VPP

O

“H” level output pin

Address output pins

50

51

52

53

54

55

58

59

60

A12

A7

A6

A5

A4

A3

A2

A1

A0

61

62

63

O1

O2

O3

I

Data input pins

64

V^SS

O

I

Power supply (GND) pin

Data input pins

65

66

67

68

69

O4

O5

O6

O7

O8

70

CE

O

ROM chip enable pin

Outputs “H” during standby.

71

73

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

75

76

77

78

79

A11

A9

A8

A13

A14

O

Address output pins

80

VCC

O

EPROM power supply pin

56

57

72

74

N.C.

—

Internally connected pin

Be sure to leave them open.

* : MQP-48C-P01

10

MB89170/170A/170L Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

Main clock

X1

• Oscillation feedback resistor of approximately

1 MΩ/5 V

X0

Standby control signal

B

Subclock

X1A

X0A

• Oscillation feedback resistor of approximately

4.5 MΩ/5 V

• When single clock mode is selected, the switch is

open.

Standby control signal

C

D

• Output pull-up resistor (P-ch) of approximately

50 kΩ/5 V

• Hysteresis input

R

P-ch

N-ch

E

• CMOS output

• CMOS input

• Hysteresis input

R

P-ch

N-ch

Port

Resource

• Pull-up resistor optional

(Continued)

11

MB89170/170A/170L Series

(Continued)

Type

Circuit

Remarks

F

• CMOS output

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional

G

• CMOS output

• Hysteresis input

R

P-ch

N-ch

• Pull-up resistor optional

• CMOS output

H

P-ch

N-ch

I

• N-ch open-drain output

R

P-ch

N-ch

• Pull-up resistor optional

• DTMF analog output

J

OPAMP

12

MB89170/170A/170L Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in “■ Electrical Characteristics” is applied between VCC to VSS.

When latchup occurs, power supply current increases rapidly and might thermally damaged elements. When

using, take great care not to exceed the absolute maximum ratings.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

registor.

3. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

4. Power Supply Voltage Fluctuations

Although operating is assured within the rated range of VCC power supply voltage, a rapid fluctuation of the

voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC

is therefore important. As stabilization guidelines, it is recommended to control power so that V^CCripple

fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60

Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as

when power is switched.

5. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

wake-up from stop mode.

6. Turning on the supply voltage (only for the MB89P175A)

Power on sharply up to the option enabling voltage (2 V) within 13 clock cycles after starting of oscillation.

13

MB89170/170A/170L Series

■ PROGRAMMING TO THE EPROM ON THE MB89P173 AND MB89P175A

The MB89P173 is an OTPROM (one-time PROM) versions of the MB89170/170L series, and the MB89P175A

is of the MB89170A/170L series.

1. Features

• 8-Kbyte (MB89P173), 16-Kbyte (MB89P175A) PROM on chip

• Options can be set using the EPROM programmer (MB89P175A only).

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 8-Kbyte PROM,16-Kbyte PROM and option area is diagrammed below.

MB89P173

Address

MB89P175A

Address

Single chip

EPROM mode

Single chip

EPROM mode

(Corresponding addresses

on the EPROM programmer)

(Corresponding addresses

on the EPROM programmer)

0000

H

0000

H

I/O

0080

0280

H

0080

0200

H

RAM

Not available

8000

H

8000

H

0000

H

0000

H

Vacancy

(Read value

Not available

FF )

H

BFF0

BFF6

H

3FF0

3FF6

H

Option area

Vacancy

(Read value

Not available

FF )

H

Vacancy

(Read value

FF )

H

C000

FFFF

H

4000

7FFF

H

E000

FFFF

H

6000

7FFF

H

PROM

16 KB

EPROM

16 KB

EPROM

8 KB

PROM

8 KB

H

14

MB89170/170A/170L Series

3. Programming to the EPROM

In EPROM mode, the MB89P173 and MB89P175A functions equivalent to the MBM27C256A. This allows the

PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot

be used) by using the dedicated socket adapter.

• Programming procedure (MB89P173)

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 6000^Hto 7FFFH (note that addresses E000H to 0FFFFH

while operating as a single chip correspond to 6000H to 7FFFH in EPROM mode).

(3) Program the data to the EPROM with the EPROM programmer.

• Programming procedure (MB89P175A)

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 4000^Hto 7FFFH (note that addresses C000H to 0FFFFH

while operating as a single chip assign to 4000H to 7FFFH in EPROM mode).

Load option data into addresses 3FF0^Hto 3FF6H of the EPROM programmer. (For information about each

corresponding option, see “7. Setting OTPROM Options (MB89P175A Only).”)

(3) Program the data to the EPROM with the EPROM programmer.

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+ 150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming

yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Compatible socket adapter

Part number

Package

QFP-48P

Sun Hayato Co., Ltd.

MB89P175A

ROM-48QF-28DP-8L

Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

15

MB89170/170A/170L Series

7. Setting OTPROM Options (MB89P175A Only)

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Addre

ss

Bit 7

Vacancy

Readable

Bit 6

Vacancy

Readable

Bit 5

Vacancy

Readable

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Clock mode Reset pin

select output

1: 1 clock 1: Yes

Power-on

reset

1: Yes

0: No

Oscillation stabilization time

3FF0^H

00 2³/FCH

01 2¹²/FCH

10 2¹⁶/FCH

11 2¹⁸/FCH

and writable and writable and writable 0: 2 clocks 0: No

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

3FF1H

3FF2^H

3FF3^H

3FF4^H

3FF5^H

3FF6^H

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Pull-up

1: Yes

0: No

Vacancy

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Vacancy

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Vacancy

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is selected.

16

MB89170/170A/170L Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

To program to the EPROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below.

Package

Socket adapter part number

LCC-32(Square)

ROM-32LC-28DP-S

Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

3. Memory Space

Memory space in each mode, such as 32-Kbyte EPROM, is diagrammed below.

Address

0000 H

Single chip

Corresponding address on the EPROM programmer

I/O

0080 H

0480 H

8000 H

RAM

Not available

0000 H

EPROM

32 KB

PROM

32 KB

7FFF ^H

FFFF ^H

4. Programming to the EPROM

(1) Set the EPROM programmer for the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH.

(3) Program with the EPROM programmer.

17

MB89170/170A/170L Series

■ BLOCK DIAGRAM

1. MB89170/170A series

Main clock

oscillator

X0

X1

Timebase timer

Watch prescalar

Clock controller

X0A

X1A

Subclock oscillator

Reset circuit

CMOS I/O port

RST

16-bit timer/counter

P34/TO/INT0

P33/EC

8-bit timer/counter

8-bit serial I/O

CMOS I/O ports

8

P00/INT20

to P07/INT27

External interrupt 2

(wake-up)

P10 to P17

P30/SCK

P32/SI

P31/SO

P35/INT1

P36/INT2

External interrupt 1

Buzzer output

8

P20 to P27

P37/BZ

CMOS output port

N-ch open-drain output port

RAM

5

P40 to P44

F²MC-8L

CPU

ROM

DTMF generator

DTMF

The other pins

MOD1, MOD0, V^CC, VSS × 2

18

MB89170/170A/170L Series

2. MB89170L series

Main clock

oscillator

X0

X1

Timebase timer

Clock controller

RST

Reset circuit

(Watch dog timer)

CMOS I/O port

16-bit timer/counter

P34/TO/INT0

P33/EC

8-bit timer/counter

8-bit serial I/O

CMOS I/O ports

8

P00/INT20

to P07/INT27

External interrupt 2

(wake-up)

8

P10 to P17

P30/SCK

P32/SI

P31/SO

P35/INT1

P36/INT2

External interrupt 1

Buzzer output

8

P20 to P27

P37/BZ

CMOS output port

N-ch open-drain output port

RAM

5

P40 to P44

F²MC-8L

CPU

ROM

The other pins

MOD1, MOD0, V^CC, VSS × 2, N.C. × 2

19

MB89170/170A/170L Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89170/170A/170L series offer 64 Kbytes of memory for storing all of I/O, data,

and program areas. The I/O area is allocated from the lowest address. The data area is allocated immediately

abovetheI/Oarea. Thedataareacanbedividedintoregister, stack, anddirectareasaccordingtotheapplication.

The program area is allocated from exactly the opposite end of I/O area, that is, near the highest address. The

tables of interrupt reset vectors and vector call instructions are allocated from the highest address within the

program area. The memory space of the MB89170/170A/170L series is structured as illustrated below.

Memory Space

MB89P173

MB89173L

MB89173

MB89174A

MB89174L

MB89PV170A

I/O

MB89P175A

I/O

0000 ^H

0080 H

0000 ^H

0080 H

0000 ^H

0080 H

0000 ^H

0080 H

I/O

RAM

1 KB

RAM

512 B

384 B

0100 H

0200 H

0100 H

0200 H

Register

0200 H

0280 H

0200 H

0280 H

0480 H

8000 H

Not available

C000 H

External ROM

32 KB

D000 H

FFFF H

ROM

E000 H

FFFF H

ROM

16 KB

ROM

8 KB

12 KB

FFFF H

20

MB89170/170A/170L Series

2. Registers

The F²MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose

memory registers. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating the instruction storage positions

A 16-bit temporary register for arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which is used for arithmetic operations with the accumulator

Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.

Index register (IX):

Extra pointer (EP) :

Stack pointer (SP) :

Progam status (PS) :

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit pointer for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

Initial value

16 bits

PC

: Program counter

: Accumulator

FFFD^H

A

T

Indeterminate

: Temporary accumulator Indeterminate

IX

: Index register

: Extra pointer

: Stack pointer

: Program status

Indeterminate

EP

SP

PS

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

Vacancy

PS

RP

H

IL1, 0

N

V

C

RP

CCR

21

MB89170/170A/170L Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of arithmetic operation. Cleared

to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise.

Z-flag: Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.

22

MB89170/170A/170L Series

The following general-purpose registers are provided:

General-purpose register: An 8-bit register for storing data

The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89170/170A/170L series . The bank currently

in use is indicated by the register bank pointer(RP).

Register Bank Configuraiton

This address = 0100 H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

}

Memory area

23

MB89170/170A/170L Series

■ I/O MAP

1. MB89170/170A series

Address

00^H

01H

02^H

03^H

04H

05^H

06^H

07H

08H

09H

0A^H

0BH

0CH

0D^H

0EH

0F^H

10H

11H

12^H

13H

14H

15^H

16^H

17H

18H

19^H

1AH

1BH

1C^H

1DH

1EH

1F^H

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

PDR2

Vacancy

(R/W)

SYCC

STBC

WDTC

TBTC

WPCR

PDR3

DDR3

PDR4

BZCR

System clock control register

Standby control register

Watchdog control register

Timebase timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Port 4 data register

Buzzer register

Vacancy

(R/W)

T2CR

T1CR

T2DR

T1DR

SMR

Timer 2 control register

Timer 1 control register

Timer 2 data register

Timer 1 data register

Serial mode register

Serial data register

Vacancy

SDR

Vacancy

(Continued)

24

MB89170/170A/170L Series

(Continued)

Address

Read/write *

(R/W)

Register name

Register description

DTMF control register

20^H

21H

DTMC

DTMD

(R/W)

DTMF data register

22^H

Vacancy

23^H

(R/W)

EIC1

EIC2

External interrupt control register 1

External interrupt control register 2

Vacancy

24H

25^Hto 31H

32^H

(R/W)

EIE2

EIF2

External interrupt 2 enable register

External interrupt 2 flag register

Vacancy

33H

34^Hto 7BH

7CH

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7D^H

7EH

7FH

* R/W: Readable and writable

R: Read only

W: Write only

Note: Do not use vacancies.

25

MB89170/170A/170L Series

2. MB89170L series

Address

00^H

01^H

02H

03^H

04^H

05H

06^H

07^H

08H

09^H

0AH

0B^H

0CH

0DH

0E^H

0FH

10^H

11H

12H

13^H

14H

15H

16^H

17H

18H

19H

1A^H

1BH

1CH

1D^H

1EH

1FH

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Vacancy

(R/W)

(W)

PDR1

DDR1

(R/W)

PDR2

Vacancy

(R/W)

SYCC

STBC

WDTC

TBTC

System clock control register

Standby control register

Watchdog control register

Timebase timer control register

Vacancy

(R/W)

PDR3

DDR3

PDR4

BZCR

Port 3 data register

Port 3 data direction register

Port 4 data register

Buzzer register

Vacancy

(R/W)

T2CR

T1CR

T2DR

T1DR

SMR

Timer 2 control register

Timer 1 control register

Timer 2 data register

Timer 1 data register

Serial mode register

Serial data register

Vacancy

SDR

Vacancy

(Continued)

26

MB89170/170A/170L Series

(Continued)

Address

Read/write *

Register name

Register description

20^H

21H

Vacancy

22^H

23^H

(R/W)

EIC1

EIC2

External interrupt control register 1

External interrupt control register 2

Vacancy

24H

25^Hto 31H

32^H

(R/W)

EIE2

EIF2

External interrupt 2 enable register

External interrupt 2 flag register

Vacancy

33H

34^Hto 7BH

7CH

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7D^H

7EH

7FH

* R/W: Readable and writable

R: Read only

W: Write only

Note: Do not use vacancies.

AsforMB89170Lseries, WPCRregister(0B^H), DTMCregister(20H)andDTMDregister(21H)becomeVacancy.

27

MB89170/170A/170L Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Power supply voltage

V^CC

V^I

VSS – 0.3

VSS + 7.0

VCC + 0.3

V

Except P40 to P44

P40 to P44

(with pull-up option)

VSS – 0.3

VCC + 0.3

V

Input voltage

V^I2

V^O

P40 to P44

(without pull-up option)

V^SS– 0.3

VSS – 0.3

VSS + 7.0

VCC + 0.3

V

Except P40 to P44

P40 to P44

(with pull-up option)

Output voltage

V^O2

P40 to P44

(without pull-up option)

VSS – 0.3

VSS + 7.0

10

V

“L” level maximum output

current

I^OL

mA

Average value (operating

current × operating rate)

“L” level average output current

IOLAV

ΣI^OL

ΣI^OLAV

I^OH

4

“L” level total maximum output

current

100

20

“L” level total average output

current

Average value (operating

current × operating rate)

“H” level maximum output

current

–10

–2

Average value (operating

current × operating rate)

“H” level average output current

IOHAV

ΣI^OH

ΣI^OHAV

“H” level total maximum output

current

–25

–10

“H” level total average output

current

Average value (operating

current × operating rate)

Power consumption

Operating temperature

Storage temperature

P^D

200

+85

mW

°C

TA

–40

–55

Tstg

+150

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

28

MB89170/170A/170L Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation assurance range*

MB89174A/173/174L/173L

2.2*

6.0*

V

Normal operation assurance range*

MB89PV170A/P175A/P173

Power supply voltage

Operating temperature

V^CC

2.7*

6.0*

Retains the RAM state in the stop

mode

1.5

6.0

V

T^A

–40

+85

°C

* : These values vary with the operating frequency, instruction cycle, and the assurance range for the DTMF gen-

erator. See Figure 1 and “(7) Electrical Characteristics of DTMF Generator” in “4. AC characteristics.”

Figure 1 Operating Voltage vs. Main Clock Operating Frequency(MB89170/170A series)

6

5

Operating assurance range

Assurance range

for DTMF generator

4

3

2

1

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.5

Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)

4.0

2.0

1.33

1.0

0.8

0.67

0.57

Minimum execution time (instruction cycle) (µs)

Note: The shaded area is assured only for the MB89170A series.

29

MB89170/170A/170L Series

Figure 2 Operating Voltage vs. Main Clock Operating Frequency(MB89170L series)

6

5

Operating assurance range

4

3

2

1

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.5

Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)

4.0

2.0

1.33

1.0

0.8

0.67

0.57

Minimum execution time (instruction cycle) (µs)

Figure 1 and figure 2 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F^CH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

30

MB89170/170A/170L Series

3. DC Characteristics

(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Sym-

bol

Parameter

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

V^CC+

0.3

P00 to P07,

P10 to P17

V^IH

0.7 V^CC

V

“H” level input

voltage

RST,

V^CC+

0.3

MOD0, MOD1,

P30 to P37,

INT20 to INT27

V^IHS

0.8 VCC

V

V^SS−

0.3

P00 to P07,

PI0 to PI7

V^IL

0.3 V^CC

0.2 V^CC

“L” level input

voltage

RST,

VSS −

0.3

MOD0, MOD1,

P30 to P37,

INT20 to INT27

V^ILS

Open-drain output

pin applied voltage

V^SS−

0.3

V^SS+

6.0

V^D

P40 to P44

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37

“H” level output

voltage

V^OH

I^OH= –2.0 mA

2.4

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P44

V^OL1

I^OL= 1.8 mA

IOL = 4.0 mA

0.4

0.6

V

“L” level output

voltage

V^OL2

RST

P00 to P07,

P10 to P17,

P20 to P27,

P30 to P37,

P40 to P44,

MOD0, MOD1

Input leakage

current (Hi-z

output leakage

current)

Without pull-

up resistor

I^LI1

0.0 V < V^I< VCC

±5

µA

kΩ

P00 to P07,

P10 to P17,

P30 to P37,

P40 to P44,

RST

With pull-up

resistor

Pull-up resistance R^PULL

VI = 0.0 V

25

50

100

(Continued)

31

MB89170/170A/170L Series

(Continued)

(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min.

Typ.

Max.

V^CC= 5.0 V

FCH = 3.58 MHz

• Main clock

operation

MB89173/

mA 174A/173L/

174L

—

3.5

8

ICC

mode

• Highest gear

speed

MB89P173/

P175A

—

6.5

2

10

5

mA

VCC = 5.0 V

FCH = 3.58 MHz

• Main clock

sleep mode

• Highest gear

speed

I^CCS1

mA

VCC = 3.0 V

F^CL= 32.768

kHz

• Subclock

sleep

I^CCS2

—

25

—

50

µA

VCC

(when DTMF is

not operating)

mode

TA = +25°C

• Subclock stop

mode

• Main clock

stop mode in

single clock

system

Power supply

voltage*

I^CCH

1

µA

VCC = 3.0 V

F^CL= 32.768

kHz

• Subclock

operation

mode

MB89173/

174A

—

50

1

100

3

µA

I^CSB

MB89P173/

mA

P175A

VCC = 3.0 V

• Watch mode

I^CCT

—

15

10

µA

V^CC= 5.0 V

FCH = 3.58 MHz

• Main clock

operation

mode

• Highest gear

speed

MB89173/

174A

5.5

mA

VCC

I^D

(when DTMF is

operating)

MB89P173/

mA

—

8.5

10

13

—

P175A

Other than VCC,

VSS

Input capacitance C^IN

f = 1 MHz

pF

* : The power supply current is measured at the external clock.

32

MB89170/170A/170L Series

4. AC Characteristics

(1) Reset Timing

(V^CC= 5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

tZLZH

—

48 tHCYL

—

ns

tZLZH

RST

0.2 VCC

(2) Power-on Reset

Parameter

(V^SS= 0.0 V, TA = –40°C to +85°C)

Value

Min. Max.

Symbol Condition

Unit

Remarks

Power supply rising time

Power supply cut-off time

t^R

—

1

50

—

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

Note: Make sure that power supply rises within the oscillation stabilization time selected.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is

recommended.

tOFF

t^R

2.0 V

VCC

0.2 V

33

MB89170/170A/170L Series

(3) Clock Timing

(V^SS= 0.0 V, TA = –40°C to +85°C)

Value

Typ.

Symbol Pin name Condition

Unit

Remarks

Parameter

Min.

Max.

MB89173/

P173

1

—

3.58 MHz

7.16 MHz

MB89174A/

P175A/

PV170A/

173L/174L

F^CH

X0, X1

Clock frequency

1

—

F^CL

X0A, X1A

X0, X1

—

32.768

—

kHz Subclock

MB89173/

P173

280

1000

ns

MB89174A/

t^HCYL

—

Clock cycle time

P175A/

140

—

1000

ns

PV170A/

173L/174L

t^LCYL

X0A, X1A

X0

—

30.5

—

µs

Subclock

PWH

PWL

20

ns

External clock

Input clock pulse

width

P^WHL

PWLL

X0A

—

15.2

—

µs

External clock

Input clock rising/

falling time

t^CR

tCF

X0, X0A

10

ns

• Main Clock Timing Condition

tHCYL

PWH

PWL

tCR

tCF

0.8 VCC

X0

0.2 VCC

• Main Clock Configurations

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

34

MB89170/170A/170L Series

• Subclock Timing Condition

tLCYL

PWHL

PWLL

tCR

tCF

0.8 VCC

X0A

0.2 VCC

• Subclock Configurations

When a crystal

or

When an external clock is used

When a single clock option is used

ceramic resonator is used

X0A

X1A

X0A

X1A

X0A

X1A

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

Remarks

(4/F^C) tinst = 1.1 µs when operating at

F^C= 3.58 MHz

4/FCH, 8/FCH, 16/FCH, 64/FCH µs

Instruction cycle

(minimum execution time)

t^inst

tinst = 61.036 µs when operating at FCL

µs = 32.768 kHz

2/FCL

(MB89170/170A series only)

35

MB89170/170A/170L Series

(5) Recommend Resonator Manufacturers

• Sample Application of Piezoelectric Resonator (FAR Family)

(MB89170 series only)

X0

X1

FAR^*1

C1^*2

C2^*2

*1: Fujitsu Acoustic Resonator

Temperature

Initial deviation of FAR

frequency

Loading

FAR part number

(built-in capacitor type)

Frequency

(MHz)

characteristics of

FAR frequency

capacitors*²

(T^A= +25°C)

(T^A= –20°C+60°C)

3.58

±0.5%

Built-in

FAR-C4 A-03580- 01

Inquiry: FUJITSU LIMITED

(6) Serial I/O Timing

(VCC = +5.0 V±10%, VSS= 0.0 V, TA = –40°C to +85°C)

Value

Symbol

SCK

Condition

Unit Remarks

Parameter

Min.

2 tinst*

–200

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

tSLOV

tIVSH

tSHIX

tSHSL

tSLSH

tSLOV

tIVSH

tSHIX

µs

ns

µs

ns

µs

SCK, SO

SI, SCK

SCK, SI

200

—

Internal shift

clock mode

Valid SI → SCK

0.5 tinst*

1 t^inst*

1 tinst*

0

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

—

SCK

—

External shift

clock mode

SCK, SO

SI, SCK

SCK, SI

200

—

Valid SI → SCK ↑

0.5 tinst*

SCK ↑ → valid SI hold time

—

* : For information on t^inst, see “(4) Instruction Cycle.”

36

MB89170/170A/170L Series

• Internal Shift Clock Mode

t^SCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SI

• External Shift Clock Mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

2.4 V

0.8 V

SO

SI

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

37

MB89170/170A/170L Series

(7) Peripheral Input Timing

(V^CC= +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Unit Remarks

Parameter

Min.

2 tinst*

Max.

—

Peripheral input “H” pulse width 1

Peripheral input “L” pulse width 1

t^ILIH1

t^IHIL1

µs

EC, INT0 to INT2,

INT20 to INT27

—

* : For information on t^inst,see “(4) Instruction Cycle.”

tIHIL1

tILIH1

0.8 VCC

0.2 VCC

0.8 VCC

EC

INT0 to INT2

0.2 VCC

INT20 to INT27

(8) Electrical Characteristics of DTMF Generator

(V^SS= 0.0 V, FCH = 3.579545 MHz, TA = –30°C to + 60°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min. Typ. Max.

3.0

2.4

2.7

30

—

6.0

—

V

MB89P173

Operating voltage

range

—

MB89173/174A

MB89P175A

VCC = 4.5 V to 6.0 V

kΩ Defined when the DTMF

pin is connected to a pull-

down resistor for the

V^CC= 3.0 V to 4.5 V 200

—

kΩ

MB89P173.

Output load

requirements

R^O

Defined when the DTMF

pin is connected to a pull-

down resistor for the

MB89173/174A

V^CC= 2.4 V to 6 V

30

—

kΩ

V^CC= 2.7 V to 6 V

MB89P175A

When the DTMF pin is

—

2.4

0.6

—

V

open for MB89P173.

DTMF output offset

voltage (at signal

output)

V^MOF

VCC = 5.0 V

When the DTMF pin is

open for the MB89173/

174A/P175A.

—

V

DTMF output

amplitude (COL

single tone)

V^MFOC

VCC = 5.0 V

450

530

600

mVP-P

DTMF output

amplitude (ROW

single tone)

When DTMF pin is open.

V^MFOR

VCC = 5.0 V

—

350

1.6

420

2.0

480

2.4

mVP-P

Difference between

COL and ROW levels

R^MF

dB

38

MB89170/170A/170L Series

■ EXAMPLE CHARACTERISTICS

(2) “H” Level Output Voltage

(1) “L” Level Output Voltage

VOL vs. IOL

V^CC= 2.5 V

VCC – VOH vs. IOH

VCC – VOH (V)

1.1

V^CC= 2.2 V

V^CC= 2.5 V

VOL (V)

1.1

V^CC= 2.2 V

V^CC= 3.0 V

TA = +25°C

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

TA = +25°C

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 3.0 V

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

0.0

–0.5 –1.0 –1.5 –2.0 –2.5 –3.0

I^OH(mA)

0

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

(3) “H” Level Input Voltage/“L”ow Level Input

Voltage (CMOS Input)

(4) “H” Level Input Voltage/“L” Level Input

Voltage (Hysteresis Input)

VIN vs. VCC

V^IN(V)

5.0

VIN vs. VCC

V^IN(V)

5.0

4.5

TA = +25°C

4.0

4.5

VIHS

TA = +25°C

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VILS

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00

V^CC(V)

VIHS : Threshold when input voltage in hysteresis characteristics

is set to “H” level

VILS : Threshold when input voltage in hysteresis characteristics

is set to “L” level

0

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00

V^CC(V)

39

MB89170/170A/170L Series

(5) Power Supply Current

I D vs. V CC

I CC vs. V CC

I D (mA)

I CC (mA)

6

5

4

3

2

1

0

Divide-by-4 (I D)

F CH = 3.58 MHz

T A = +25°C

F CH = 3.58 MHz

T A = +25°C

5

4

3

2

1

0

Divide-by-4 (I ^CC)

Divide-by-8

Divide-by-16

Divide-by-64

Divide-by-8

Divide-by-16

Divide-by-64

1

2

3

4

5

6

7

1

2

3

4

5

6

7

V ^CC(V)

(6) Pull-up Resistance

RPULL vs. VCC

R^PULL(kΩ)

1000

TA = +25°C

300

100

50

10

0

1

2

3

4

5

6

7

VCC (V)

40

MB89170/170A/170L Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

T

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

TH

TL

IX

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

CCR

RP

Ri

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

41

MB89170/170A/170L Series

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

The number of instructions

The number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

42

MB89170/170A/170L Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

43

MB89170/170A/170L Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

44

MB89170/170A/170L Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

45

MB89170/170A/170L Series

■ INSTRUCTION MAP

46

MB89170/170A/170L Series

■ MASK OPTIONS

MB89P173

MB89173L

MB89174L

Part number

No.

MB89173

MB89P173-201 MB89P175A MB89PV170A

MB89174A

Specifywhen Specifywhen

Standard

option

Set with

EPROM

programmer

Setting not

possible

Specifying procedure

ordering

masking

ordering

masking

product

Can be set

per pin

(However,

P40 to P44

are available

only for no

pull-up

All ports

Fixed to no

pull-up

Pull-up resistors

Can be

selected per

Can be

selected per

All ports

Fixed to no pull-

up resistor

1

2

•

P00 to P07, P10 to P17

P30 to P37, P40 to P44

resistor option

resistor.)

Power-on reset

Fixed to no

power-on reset

option

Fixed to

power-on

reset option

Setting

possible

•

Power-on reset provided

No power-on reset

Selectable

Selection of oscillation

stabilization

time initial value (when

operating at

Fixed to 2¹⁸/

F^CH

Setting

possible

Fixed to 2¹⁶/FCH

F^CH= 3.58 MHz)

3

3: 2¹⁸/FCH (approx. 73.2 ms)

2: 2¹⁶/FCH (approx. 18.3 ms)

1: 2¹²/FCH (approx. 1.1 ms)

0: 2³/FCH (approx. 0 ms)

Reset pin output

Setting

possible

Fixed to reset

output option

Fixed to reset

output option

4

5

•

Reset output enabled

Reset output disabled

Selectable

Clock mode selection

Fixed to

single-clock

mode

Fixed to dual-

clock mode

Setting

possible

Fixed to dual-

clock mode

•

Dual-clock mode

Single-clock mode

Note: Reset is input asynchronized with the internal clock whether power-on reset is provided or not.

■ ORDERING INFORMATION

Part number

MB89173PF

Package

Remarks

MB89174APF

MB89P173PF

MB89P175APF

MB89173LPF

MB89174LPF

48-pin Plastic QFP

(FPT-48P-M16)

48-pin Ceramic MQFP

(MQP-48C-P01)

MB89PV170ACF

47

MB89170/170A/170L Series

■ PACKAGE DIMENSION

48-pin Plastic QFP

(FPT-48P-M16)

17.20±0.40 SQ

2.70(.106)MAX

(Mounting height)

(.677±.016)

12.00 ⁺^–0⁰^.^.¹³⁰⁰SQ

.472 –⁺.^.0⁰0¹4²

0.05(.002)MIN

(STAND OFF)

36

25

Details of "A" part

37

24

0.15(.006)

0.20(.008)

8.80

(.346)

REF

13.60±0.40

(.535±.016)

0.15(.006)MAX

0.50(.020)MAX

INDEX

"A"

48

13

Details of "B" part

1

12

LEAD No.

0.15 –⁺0⁰.^.0⁰1⁵

.006 ⁺^–.^.⁰⁰⁰⁰⁰²⁴

0.80(.0315)TYP

0.30±0.06

(.012±.002)

M

0.16(.006)

0~10°

"B"

1.80±0.30

(.071±.012)

0.15(.006)

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED F48026S-1C-1

48

MB89170/170A/170L Series

48-pin Ceramic MQFP

(MQP-48C-P01)

17.20(.677)TYP

15.00±0.25

(.591±.010)

1.50(.059)TYP

1.00(.040)TYP

8.80(.346)REF

PIN No.1 INDEX

14.82±0.35

(.583±.014)

0.80±0.22

(.0315±.0087)

PIN No.1 INDEX

1.02±0.13

(.040±.005)

10.92 –⁺0⁰.^.0¹³

.430 –⁺0^.005

8.71(.343)

TYP

7.14(.281)

TYP

PAD No.1 INDEX

4.50(.177)TYP

1.10 ⁺^–0⁰^.^.²⁴⁵⁵

.043 ⁺^–.^.⁰⁰¹¹⁰⁸

0.40±0.08

(.016±.003)

0.60(.024)TYP

0.30(.012)TYP

8.50(.335)MAX

0.15±0.05

(.006±.002)

C

Dimensions in mm (inches)

1994 FUJITSU LIMITED M48001SC-4-2

49

MB89170/170A/170L Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and

Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

measurement equipment, personal or household devices, etc.).

CAUTION:

Fax: (408) 922-9179

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded

(such as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

http://www.fmap.com.sg/

F9910

FUJITSU LIMITED Printed in Japan


型号：	MB89P173
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总50页 (文件大小：583K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P173 [FUJITSU]

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