MB89P965APF [FUJITSU]
Microcontroller, 8-Bit, OTPROM, F2MC-8L CPU, 10MHz, CMOS, PQFP48, 0.80 MM PITCH, PLASTIC, QFP-48;
| 型号： | MB89P965APF |
| 厂家： | 
FUJITSU |
| 描述： | Microcontroller, 8-Bit, OTPROM, F2MC-8L CPU, 10MHz, CMOS, PQFP48, 0.80 MM PITCH, PLASTIC, QFP-48 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总48页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12545-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89960 Series
MB89965/P965A/F969A/
MB89PV960
■ DESCRIPTION
The MB89960 series is a single-chip microcontroller that utilizes the F2MC-8L core for low voltage and high speed
performance. The microcontroller contains a range of peripheral functions including timers, a serial interface, I2C
interface, A/D converter, and external interrupts. The internal I2C interface complies with the SM bus standard
and supports an SM bus battery controller.
■ FEATURES
• Range of package options
• QFP and MQFP packages (0.8 mm pitch)
• LQFP package (0.5 mm and 0.65 mm pitch)
• High speed operation at low voltage
Minimum instruction execution time = 0.4 µs (for a 10 MHz oscillation)
• F2MC-8L CPU core
Instruction set optimized for controller applications
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Dual-clock control system
• Main clock : 10 MHz max.
(Four speed settings available, oscillation halts in sub-clock mode)
• Sub-clock : 32.768 kHz (Operation clock for sub-clock mode)
• Four channels
• 8/16-bit timer/counter (8-bit × 2 channels or 16-bit × 1 channel)
• 21-bit timebase timer
• Clock prescaler (15-bit)
• Serial I/O
Selectable transfer format (MSB-first or LSB-first) supports communications with a wide range of devices.
• A/D converter
10-bit × 4 channels
MB89960 Series
• External interrupts
• External interrupt 1 (3 channels)
Three independent interrupt inputs can be used to recover from low-power consumption modes (with edge-
detection function)
• External interrupt 2 (1 channel with 8 inputs)
Eight inputs can be used to recover from low-power consumption modes (with “L” level detection function)
• Low-power consumption modes (standby modes)
• Stop mode (As all oscillations halt in sub-clock mode, current consumption falls to almost zero.)
• Sleep mode (The CPU stops to reduce the current consumption to approximately 1/3 of normal.)
• Clock mode (All operation halts other than the clock prescaler resulting in very low power consumption.)
• I2C interface*
• Supports Intel SM bus and Philips I2C bus standards.
• Uses a two-wire data transfer protocol.
• Max. 35 I/O ports
• Output-only ports (N-ch open drain)
• General-purpose I/O ports (CMOS)
• Output-only ports (CMOS)
: 6
: 21
: 8
* : I2C license
The customer is licensed to use the Philips I2C patent when using this product in an I2C system that complies
with the Philips I2C standard specifications.
■ PACKAGE
Plastic LQFP, 48-pin
Plastic QFP, 48-pin
Plastic QFP, 48-pin
(FPT-48P-M05)
(FPT-48P-M13)
(FPT-48P-M16)
Ceramic MQFP, 48-pin
Plastic LQFP, 64-pin
(MQP-48C-P01)
(FPT-64P-M09)
2
MB89960 Series
■ PRODUCT LINEUP
Part No.
MB89965
MB89P965A
MB89F969A
MB89PV960
Prameter
Piggyback/
evaluation product
for testing and
development
Mass-produced
products
(mask ROM products)
Classification
One-time product
Flash product
32 K × 8-bit
(External ROM) *
ROM size
RAM size
16 K × 8-bit (Internal mask ROM)
512 × 8-bit
60 K × 8-bit
1024 × 8-bit
Number of instructions
Instruction bit length
Instruction length
: 136
: 8-bit
: 1 to 3 bytes
: 1-, 8-, 16bits
CPU functions
Data bit length
Minimum execution time
Interrupt processing time
: 0.4 µs (at 10 MHz)
: 3.6 µs (at 10 MHz)
Output-only ports (N-ch open drain)
: 6 (4 pins are shared with analog inputs)
(2 pins are shared with resource I/O)
: 8
: 21 (shared with resource I/O)
35 (max.)
Ports
Output-only ports (CMOS)
General-purpose I/O ports (CMOS)
Total
21-bit
Timebase timer Four interrupt intervals selectable 0.82 ms, 3.3 ms, 26.2 ms, or 419.4 ms (approx.) (for
main clock)
Reset trigger period : 419.4 ms (10 MHz main clock)
Watchdog timer
500 ms (32.768 MHz sub-clock)
One channel. Supports Intel SM bus (version 1.0) and Philips I2C bus standards.
Uses a 2-wire protocol for communications with other devices.
Included/Not included
I2C interface
Pe-
riph-
eral
(Specified when order-
Included
ing. See “Ordering In-
formation” for details.)
func-
tions
2 channel 8-bit timer/counter operation (independent operation clocks for timer 1 and
timer 2) or 16-bit timer/counter operation (operation clock period : 0.8 µs to 204.8 µs)
can execute an event counter operation and output a square wave using an external
Clock.
8/16-bit timer/
counter Timer
1 or 16-bit timer/counter operation mode
8 bits
Serial I/O
LSB-first or MSB-first selectable
Transfer clocks : External or three internal clocks (0.8 µs, 3.2 µs, 12.8 µs)
Selectable edge detection (rising, falling, or either edge)
3 independent channels
These can also be used to recover from standby modes (edge detection is still available
in stop mode) .
External
interrupt 1
(edge)
External
interrupt 2
(level)
1 channel with 8 inputs (“L” level interrupts, independent input enable)
This can also be used to recover from standby modes (level detection is still available in
stop mode) .
(Continued)
3
MB89960 Series
(Continued)
Part No.
MB89965
MB89P965A
MB89F969A
MB89PV960
Prameter
4 channel × 10-bit resolution
A/D conversion time : 15.2 µs (MB89965, MB89P965A, MB89F969A)
13.2 µs (MB89PV960)
Continuous activation is available using the output from the 8/16-bit timer/counter or
timebase timer.
Reference voltage input (AVR)
Pe-
riph-
eral
func-
tions
A/D converter
15-bit
Clock prescaler
Interrupt interval : 31.25 ms, 0.25 s, 0.50 s, 1.00 s (for a 32.768 kHz sub-clock)
Low power consump-
tion (standby modes)
Sleep mode, stop mode, and clock mode
Process
CMOS
Operating voltage
3.5 V to 5.5 V
* : Use the MBM27C256A-20TVM as the external ROM (Operating voltage : 4.5 V to 5.5 V)
Note : Unless otherwise stated, clock periods and conversion times are for 10 MHz operation with the main clock
operating at maximum speed.
■ PACKAGES AND CORRESPONDING PRODUCTS
Part No.
MB89965
MB89P965A
MB89F969A
MB89PV960
Package
×
×
×
×
×
×
×
FPT-48P-M05
FPT-48P-M13
FPT-48P-M16
FPT-64P-M09
MQP-48C-P01
×
×
×
×
×
: Available
: Not available
×
4
MB89960 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Space
Please take note of the differences among products before testing and developing software for the MB89960
series.
• The RAM and ROM configurations differ among products.
• If the bottom stack address is set at the top RAM address, this will need to be relocated if changing to a different
product.
2. Current Consumption
• In the case of the MB89PV960, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, one-time PROM and EPROM products will consume more current than mask
ROM products. However, the current consumption in sleep/stop modes is the same.
3. Functional Differences Between MB89960 Series
MB89965/P965A/F969A
MB89PV960
Regulator stabilization delay time,
regulator recovery time,
Power-on reset delay time
Oscillation stabilization delay time
oscillation stabilization delay time
External reset delay time in stop/
sub-clock mode or external
interrupt delay time in main stop
mode
Regulator recovery time,
oscillation stabilization delay time
Oscillation stabilization delay time
Port pin pull-up resistors
A/D conversion time
Software-selectable
38 instruction cycles
Not available
33 instruction cycles
Always present regardless of ICCR :
DMPB bit setting
I2C noise elimination circuit
Disabled if ICCR : DMPB bit = “1”
4. Mask Options
Functions that can be selected as options and the methods used to specify these options vary by the product.
Before using mask options, check section “ Mask Options”.
5
MB89960 Series
■ PIN ASSIGNMENT
(TOP VIEW)
AVCC
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
P34/TO/CLK
C
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
9
10
11
12
P26
P25
(FPT-48P-M05)
(FPT-48P-M13)
(FPT-48P-M16)
(Continued)
6
MB89960 Series
(Continued)
(TOP VIEW)
AVCC
RST
MOD0
MOD1
X0
X1
VCC
X0A
X1A
P27
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
P34/TO/CLK
N.C.
69
70
71
72
73
74
75
76
60
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
59
58
57
56
55
54
53
9
10
11
12
P26
P25
(MQP-48C-P01)
* : Pin assignment on package top (MB89PV960)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin No.
Pin No.
Pin No.
Pin No.
49
50
51
52
53
54
55
56
VPP
A12
A7
57
58
59
60
61
62
63
64
N.C.
A2
65
66
67
68
69
70
71
72
O4
73
74
75
76
77
78
79
80
OE
O5
N.C.
A11
A9
A1
O6
A6
A0
O7
A5
O1
O2
O3
VSS
O8
A8
A4
CE
A13
A14
VCC
A3
A10
N.C.
N.C.
N.C. : Internally connected. Do not use.
(Continued)
7
MB89960 Series
(Continued)
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TEST
MOD2
AVCC
RST
MOD0
MOD1
X0
N.C.
N.C.
P34/TO/CLK
C
P00/INT20
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
N.C.
X1
VCC
X0A
X1A
P27
P26
P25
N.C.
N.C.
N.C.
(FPT-64P-M09)
8
MB89960 Series
■ PIN DESCRIPTIONS
Pin No.
Circuit
Type
LQFP-48*1
MQFP-48*3
Pin Name
Function
LQFP-64*4
QFP-48*2
5
6
8
5
6
8
7
X0
X1
Oscillator connection pins for the main clock os-
cillator (crystal oscillator or similar) .
When using an external clock, input the clock
signal to X0 and leave X1 open.
A
8
10
X0A
Oscillator connection pins for the sub-clock os-
cillator (crystal oscillator or similar) .
When using an external clock (low speed :
32.768 kHz) , input the clock signal to X0A and
leave X1A open.
B
C
9
9
11
X1A
3
4
3
4
5
6
MOD0
MOD1
Input pins for setting the memory access mode.
Connect directly to VSS.
Reset I/O pin
This is an N-ch open-drain output type with pull-
up resistor and a hysteresis input type. The pin
outputs “L” when an internal reset is present.
Similarly, inputting “L” initializes the internal cir-
cuits.
2
2
4
RST
D
General-purpose I/O ports
P00/INT20
to
P07/INT27
Also serves as the external interrupt 2 inputs
(wakeup inputs) . The external interrupt 2 inputs
are hysteresis inputs.
27 to 34
24 to 26
27 to 34
24 to 26
37 to 44
E
E
General-purpose I/O ports
30,
35,
36
P10/INT10
to
P12/INT12
Also serves as the external interrupt 1 inputs
(wakeup inputs) . The external interrupt 1 inputs
are hysteresis inputs.
P13
to
P17
18,
20 to 23
18,
20 to 23
24,
26 to 29
E
G
F
General-purpose I/O ports
P20
to
P27
12 to 14
19 to 23
10 to 17
40
10 to 17
40
General-purpose outoput-only ports
General-purpose I/O port
Also serves as the serial clock I/O.
A hysteresis input.
54
53
P30/SCK
P31/SO
General-purpose I/O port
Also serves as the serial I/O data output.
A hysteresis input.
39
39
F
*1 : FPT-48P-M05
(Continued)
*2 : FPT-48P-M16, FPT-48P-M13
*3 : MQP-48C-P01
*4 : FPT-64P-M09
9
MB89960 Series
(Continued)
Pin No.
Circuit
Type
LQFP-48*1
Pin Name
Function
MQFP-48*3
LQFP-64*4
QFP-48*2
General-purpose I/O port
38
38
52
51
P32/SI
F
F
Also serves as the serial I/O data input.
A hysteresis input.
General-purpose I/O port
Also serves as the external clock input for the 8/
16-bit timer/counter. A hysteresis input.
37
36
37
36
P33/EC
General-purpose I/O port
P34/TO/
CLK
Also serves as the overflow output for the 8/16-
bit timer/counter and the CLK clock
output. A hysteresis input.
46
F
Connect a 0.1 µF capacitor on the MB89965,
MB89P965A, and MB89F969A.
35
45
C
P40/AN0
to
P43/AN3
General-purpose Nch open-drain outputs.
Also serves as the A/D converter analog inputs.
45 to 48
45 to 48
59 to 62
H
General-purpose Nch open-drain output.
Also serves as the I2C interface data output.
42
41
42
41
56
55
P44/SDA
P45/SCL
I
I
General-purpose Nch open-drain output.
Also serves as the I2C interface clock I/O.
7
7
9
VCC
Power supply pin
19
19
25
VSS
Power supply (GND) pin
A/D converter power supply pin
Use this pin at the same voltage as VCC.
1
1
3
AVCC
AVR
AVSS
44
43
44
43
58
57
A/D converter reference voltage input pin
A/D converter power supply pin
Use this pin at the same voltage as VSS.
15 to 18
31 to 34
47 to 50
63, 64
These pins are not connected.
Do not connect these on the MB89PV960.
35
N.C.
TEST
MOD2
TEST pin. Connect directly to VSS.
Only used on the MB89F969A.
Treat as an N.C. pin on the MB89965.
1
C
C
Memory access mode setting pin. Connect di-
rectly to VSS.
Only used on the MB89F969A.
Treat as an N.C. pin on the MB89965.
2
*1 : FPT-48P-M05
*2 : FPT-48P-M16, FPT-48P-M13
*3 : MQP-48C-P01
*4 : FPT-64P-M09
10
MB89960 Series
• Pin Descriptions for External EPROM (MB89PV960 only)
Pin No.
Pin Name
I/O
Function
49
Vpp
O
“H” level output pin
Address output pins
50
51
52
53
54
55
A12
A7
A6
A5
A4
A3
O
58
59
60
A2
A1
A0
O
I
Address output pins
61
62
63
O1
O2
O3
Data input pins
64
VSS
Power supply (GND) pin
65
66
67
68
69
O4
O5
O6
O7
O8
I
Data input pins
ROM chip enable pin
Outputs “H” during standby mode.
70
71
73
CE
A10
OE
O
O
O
Address output pin
ROM output enable pin
Always outputs “L”.
75
76
77
78
79
A11
A9
A8
A13
A14
O
Address output pins
80
VCC
EPROM power supply pin
56
57
72
74
Internally connected pins
Always leave open circuit.
N.C.
11
MB89960 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Nch Pch
Pch
X0
High speed clock (main clock oscillation)
• Oscillation feedback resistor
A
Nch
Main clock control signal
X1A
Nch Pch
Pch
Nch
X0A
Low speed clock (sub-clock oscillation)
• Oscillation feedback resistor
B
Nch
Sub-clock control signal
• CMOS input
C
D
R
Pch
• Output pull-up resistor (Pch)
approx. 50 kΩ (at 5 V)
• Hysteresis input
Nch
R
Pch
Pull-up
Pch
Nch
• CMOS output
• CMOS input
• Selectable pull-up resistor
approx. 50 kΩ (at 5 V)
E
Port
Resource
(Continued)
12
MB89960 Series
(Continued)
Type
Circuit
Remarks
R
Pch
Pull-up
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approx. 50 kΩ (at 5 V)
Pch
Nch
F
Resource
Pch
Nch
• CMOS output
G
R
• Nch-open drain output
Pch
Pull-up
• Analog input (A/D converter)
• Selectable pull-up resistor
• (The pull-up resistor cannot be used
when used as an analog input.)
approx. 50 kΩ (at 5 V)
H
Nch
Analog input
• Nch open drain output
• Selectable SMB or I2C
input buffer
Nch
SMB buffer
I2C buffer
I
SMB input
I2C input
13
MB89960 Series
■ HANDLING DEVICES
1. Do not exceed maximum rated voltage (to prevent latch-up)
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input or output pins
other than medium- and high voltage pins or if the voltage applied between VCC and VSS higher the rating.
If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements.
Therefore, ensure that maximum ratings are not exceeded in circuit operation.
Similarly, when turning the analog power supply on or off, ensure the analog power supply voltages (AVCC and
AVR) and analog input voltages do not exceed the digital power supply (VCC) .
2. Power supply voltage fluctuations
Rapid fluctuation of the voltage may cause the device to misoperate, even if the voltage remains within the
allowed operating range.
The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the mains supply frequency
(50 to 60 Hz) of 10% or less of VCC and a transient voltage change rate of 0.1 V/ms or less such as when turning
the power supply on or off.
3. Treatment of unused input pins
Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to
latchup. Always pull-up or pull-down unused input pins using a 2 kΩ or larger resistor.
If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same
way as input pins.
4. Treatment of N.C. pins
Always leave N.C. (internally connected) pins open.
5. Treatment of power supply pins on microcontrollers with an A/D converter
Even if not using the A/D converter, connect to be AVCC = VCC and AVSS = AVR = VSS.
6. Precautions on using an external clock
An oscillation stabilization delay occurs after a power-on reset or when recovering from sub-clock or stop mode,
even if an external clock is used.
14
MB89960 Series
■ PROGRAMMING SPECIFICATIONS FOR ONE-TIME PROM PRODUCTS
The MB89P965A has a “PROM mode” that enables the microcontroller to be programmed using a general-
purpose ROM programmer via a special adaptor. Note, however, that electronic signature mode is not available.
1. ROM Programmer Adaptor and Recommended ROM Writers
Adaptor Part No.
Recommended Programmer Manufacturer and Model
Package Name
Sun Hayato Co. Ltd.
Ando Denki Co. Ltd.
FPT-48P-M05
FPT-48P-M13
ROM2-48LQF-32DP-8LA
ROM2-48QF2-32DP-8LA
ROM2-48QF-32DP-8LA
AF9708 (ver 1.44 or later)
AF9709 (ver 1.44 or later)
FPT-48P-M16
• Enquiries
Sun Hayato Co. Ltd. : TEL 03-3986-0403
Ando Denki Co. Ltd. : TEL 044-549-7300
2. PROM Mode Memory Map
Normal operating mode
0000H
0080H
I/O
RAM
0100H
General-
purpose
registers
0200H
0280H
Not available
PROM mode
(addresses on ROM programmer)
0000H
C000H
FFFFH
Program
area
(PROM)
Program
area
(PROM)
3FFFH
3. PROM Programming Procedure (When using an Ando EPROM programmer)
1) Set the EPROM programmer type code to 17209.
2) Load the program data into addresses 0000H to 3FFFH in the EPROM programmer.
3) Use the EPROM programmer to program to addresses C000H to FFFFH.
4. Programming Yield
Due to the nature of OTPROM memory, a program test to all bits on a blank OTPROM microcontroller cannot
be performed at Fujitsu. For this reason, a programming yield of 100% cannot be assured at all times.
15
MB89960 Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F969A
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
• 60 K byte × 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors)
• Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
• Includes an erase pause and restart function
• Data polling and toggle bit for detection of program/erase completion
• Detection of program/erase completion via CPU interrupt
• Compatible with JEDEC-standard commands
• Sector Protection (sectors can be combined in any combination)
• No. of program/erase cycles : 10,000 (min.)
Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Control status register (FMCS)
Address
002EH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
INTE RDYINT WE
RDY Reserved Reserved
Reserved 000X00-0B
R/W
R/W
R/W
R/W
R
R/W
R/W
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access a flash memory programming.
• Sector configuration of flash memory
Flash Memory
16 K bytes
8 K bytes
CPU Address
FFFFH to C000H
BFFFH to A000H
9FFFH to 8000H
7FFFH to 1000H
Programmer Address
1FFFFH to 1C000H
1BFFFH to 1A000H
19FFFH to 18000H
17FFFH to 11000H
8 K bytes
28 K bytes
* : Programmer address
The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a general-
purpose parallel programmer.
16
MB89960 Series
6. ROM Programmer Adaptor and Recommended ROM Programmers
Adaptor Part No.
Recommended Programmer Manufacturer and Model
Package Name
Sun Hayato Co. Ltd.
Ando Denki Co. Ltd.
AF9708 (ver 1.60 or later)
AF9709 (ver 1.60 or later)
FPT-64P-M09
• Enquiries
FLASH-64QF2-32DP-8LF
Sun Hayato Co. Ltd. : TEL 03-3986-0403
Ando Denki Co. Ltd. : TEL 044-549-7300
17
MB89960 Series
■ PROGRAMMING A PIGGYBACK/EVALUATION EPROM
1. EPROM Type
MBM27C256A-20TVM
2. Programming Adaptor
Use the following programming adaptor (made by Sun Hayato Co. Ltd.) to program the EPROM using a ROM
programmer.
• Programming adaptor
Package
Adaptor Socket Part No.
LCC-32 (Square)
ROM-32LC-28DP-S
Enquiries Sun Hayato Co. Ltd. : TEL03-3986-0403
3. Memory Space
Normal operating mode
0000H
0080H
I/O
RAM
0280H
8000H
Not available
EPROM mode
(addresses on ROM programmer)
0000H
Program
area
Program
area
(PROM)
(PROM)
FFFFH
7FFFH
4. EPROM Programming Procedure
(1) Setup the EPROM programmer to the MBM27C256A.
(2) Load the program data into addresses 0000H to 7FFFH in the EPROM programmer.
(3) Use the ROM programmer to program to addresses 0000H to 7FFFH.
18
MB89960 Series
■ BLOCK DIAGRAM
Main clock
High speed
oscillator circuit
(Max. 10 MHz)
X0
X1
Timebase timer
Reset circuit
(watchdog timer)
Clock control
RST
Sub-clock
Low speed
oscillator circuit
(32.768 kHz)
16-bit
timer/counter
X0A
X1A
8-bit
timer/counter 2
P34/TO/CLK
P33/EC
Clock prescaler
CMOS I/O port
8-bit
timer/counter 1
8
P00/INT20
to P07/INT27
8
3
External interrupt 2
(Level)
P32/SI
P31/SO
P30/SCK
8-bit
serial I/O
3
5
External interrupt 1
(edge)
P10/INT10
to P12/INT12
CMOS I/O port
P13 to P17
AVR
AVCC
AVSS
CMOS I/O port
8
P20 to P27
CMOS output port
4
4
10-bit
A/D converter
P40/AN0
P43/AN3
R A M
P44/SDA
P45/SCL
I2C interface
F2MC-8L
C P U
Nch open drain
output port
R O M
Other pins
MOD0, MOD1, Vcc, Vss, C
19
MB89960 Series
■ CPU CORE
1. Memory Space
(1) Structure of memory space
• I/O area (address : 0000H to 007FH)
• Assign the control registers, data registers, and similar of the internal peripheral functions.
• As the I/O area is allocated as part of the memory space, it can be accessed in the same way as memory.
Direct addressing also provides high speed access.
• RAM area
• Static RAM is provided as an internal data area.
• The size of internal RAM differs between products.
• Addresses 80H to FFH provide high speed access using direct addressing.
• Addresses 100H to 1FFH are used as the general-purpose register area.
• The initial value of RAM after a reset is undefined.
• ROM area
• ROM memory is provided as the internal program area.
• The size of internal ROM differs between products.
• Addresses FFC0H to FFFFH are used for the vector table and similar.
(2) Memory map
MB89965
MB89P965A
MB89F969A
I/O
MB89PV960
I/O
0000H
0080H
0100H
0000H
0080H
0000H
0080H
0100H
I/O
RAM
RAM
RAM
0100H
0200H
Registers
Registers
Registers
0200H
0480H
0200H
0280H
0480H
1000H
Not available
Not available
Not available
8000H
C000H
ROM
ROM
ROM
FFC0H
FFFFH
FFC0H
FFFFH
FFC0H
FFFFH
Vector table
(Reset, interrupt, vector call instruction)
20
MB89960 Series
2. Registers
The MB89960 series provides two types of registers: dedicated registers in the CPU and general-purpose
registers. The dedicated registers are as follows.
Program counter (PC)
Accumulator (A)
: A 16-bit register for indicating the instruction storage positions.
: A 16-bit register that provides temporary storage for arithmetic operations and
similar. Instructions that operate on 8-bit data use the lower byte.
Temporaryaccumulator(T) : A 16-bit register used for arithmetic operations with the accumulator. Instructions
that operate on 8-bit data use the lower byte.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register used for index modification.
: A 16-bit pointer used for indicating a memory address .
: A 16-bit register used for indicating a stack area.
: A 16-bit register used to store a register pointer and condition code.
16 bits
Initial value
FFFDH
PC
A
: Program counter
: Accumulator
Undefined
Undefined
Undefined
Undefined
Undefined
T
: Temporary accumulator
: Index register
IX
EP
SP
: Extra pointer
: Stack pointer
RP
CCR
: Program status
I flag = 0, IL1, IL0 = 11
Other bits are undefined
PS
The upper 8 bits of the PS contain the register bank pointer (RP) and the lower 8 bits contain the condition code
register (CCR) . (See the diagram below.)
RP
CCR
CCR Initial value
X011XXXXB
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R4
R3 R2 R1 R0
−
−
−
H
I
IL1 IL0
N
Z
PS
C
V
Half carry flag
Interrupt enable flag
Interrupt level bits
Negative flag
Zero flag
Overflow flag
Carry flag
X : Undefined
21
MB89960 Series
The RP contains the address of the currently used register bank. The conversion diagram below shows the
relationship between the RP value and actual address.
Rules for converting of actual addresses of the general-purpose register area
Upper (RP)
Lower (op code)
b1 b0
"0" "0" "0" "0" "0" "0" "0" "1"
A15 A14 A13 A12 A11 A10 A9 A8
R4 R3 R2 R1 R0 b2
Actual address
A7 A6 A5 A4 A3 A2 A1 A0
CCR contains bits that indicate the result of an arithmetic operation or information about transfer data and bits
used to control CPU operation when an interrupt occurs.
H-flag : Set to “1” when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an
arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions and
should be ignored for operations other than addition and subtraction.
I-flag
: Interrupts are enabled when this flag is set to “1” and disabled when the flag is set to “0”. Cleared
to “0” by a reset.
IL1, 0
: Indicates the level of interrupts currently allowed. The CPU only processes interrupts with a re-
quest level higher than the value indicated by these bits.
IL1 IL0 Interrupt Level
Priority
0
0
1
1
0
1
0
1
High
1
2
3
Low = No interrupt
N-flag : Set to “1” when the MSB of the result of an arithmetic operation is “1” and cleared to “0” when the
MSB is “0”.
Z-flag
V-flag
: Set to “1” when the result of an arithmetic operation is zero. Cleared to “0” otherwise
: Set to “1” when a 2’s complement overflow occurs as the result of an arithmetic operation. Cleared
to “0” if no 2’s complement overflow occurs.
C-flag : Set to “1” when a carry from bit 7 or a borrow to bit 7 occurs as the result of an arithmetic opera-
tion. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
22
MB89960 Series
The following general-purpose registers are provided :
General-purpose registers : 8-bit resisters for storing data
The general-purpose registers are 8-bit registers and are allocated in the register banks of the memory. Each
bank contains 8 registers and all 32 banks can be used on MB89960 series microcontrollers.
The register bank pointer (RP) specifies the bank that is currently in use.
Register bank structure
Address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
23
MB89960 Series
■ I/O MAP
Address Abbreviation
Register Name
Port 0 data register
Port 0 direction register
Port 1 data register
Port 1 direction register
Port 2 data register
Read/Write
Initial Value
XXXXXXXXB
0 0 0 0 00 0 0B
XXXXXXXXB
0 0 0 0 00 0 0B
0 0 0 0 00 0 0B
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
PDR0
DDR0
PDR1
DDR1
PDR2
R/W
W
R/W
W
R/W
(Unused area)
SYCC
STBC
WDTC
TBTC
WPCR
PDR3
DDR3
PDR4
System clock control register
Standby control register
Watchdog control register
Timebase timer control register
Clock prescaler control register
Port 3 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X - -MM1 0 0B
0 00 1 0 -- -B
0 - -- XXXXB
00- -- 0 0 0B
00- -- 0 0 0B
- --XXXXXB
- - 00 0 0 0 0B
-- 11 1 1 1 1B
Port 3 direction register
Port 4 data register
(Unused area)
IBSR
IBCR
ICCR
IADR
IDAR
I2C bus status register
I2C bus control register
I2C clock control register
I2C address register
R
0 0 0 0 00 0 0B
0 0 0 1 10 0 0B
0 00XXXXXB
-XXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
I2C data register
(Unused area)
T2CR
T1CR
T2DR
T1DR
SMR
Timer 2 control register
Timer 1 control register
Timer 2 data register
Timer 1 data register
Serial mode register
Serial data register
R/W
R/W
R/W
R/W
R/W
R/W
X0-- XXX0B
X00 0XXX0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 00 0 0B
XXXXXXXXB
SDR
(Unused area)
ADC1
ADC2
ADDH
A/D control register 1
A/D control register 2
A/D data register H
R/W
R/W
R/W
0 0 0 0 0 0- 0B
- 0 0 00 0 0 1B
- - - - - - XXB
(Continued)
24
MB89960 Series
(Continued)
Address
Abbreviation
ADDL
Register Name
A/D data register L
Read/Write
R/W
Initial Value
XXXXXXXXB
0 0 00 0 0 0 0B
- - -- 00 0 0B
23H
24H
EIC1
External interrupt 1 control register 1
External interrupt 1 control register 2
(Unused area)
R/W
25H
EIC2
R/W
26H to 27H
Pull-up resistor register 1
(MB89965, P965A, and F969A only)
28H
29H
2AH
2BH
PURR1
PURR2
PURR3
PURR4
R/W
R/W
R/W
R/W
1 1 11 1 1 1 1B
1 1 11 1 1 1 1B
XXX11 1 1 1B
XXXX1 1 11B
Pull-up resistor register 2
(MB89965, P965A, and F969A only)
Pull-up resistor register 3
(MB89965, P965A, nd F969A only)
Pull-up resistor register 4
(MB89965, P965A, and F969A only)
2CH to 31H
32H
(Unused area)
External interrupt 2 control register
External interrupt 2 flag register
(Unused area)
EIE2
EIF2
R/W
R/W
0 0 00 0 0 0 0B
- - - - - - - 0B
33H
34H to 7BH
7CH
ILR1
ILR2
ILR3
ITR
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt test register
W
1 1 11 1 1 1 1B
1 1 11 1 1 1 1B
1 1 11 1 1 1 1B
XXXXXX0 0B
7DH
W
W
7EH
7FH
Not available
• Read/write notation
R/W : Reading and writing available
R
W
: Read-only
: Write-only
• Initial value notation
0
: Initial value of bit is “0”.
1
X
M
-
: Initial value of bit is “1”.
: Initial value of bit is undefined.
: Initial value of bit is specified by mask option.
: Bit is not used.
Note : Do not use the “unused areas”.
25
MB89960 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Rating
Parameter
Symbol
Unit
Remarks
Min.
Max.
VCC
AVCC
VSS − 0.3
VSS + 6.0
Power supply voltage
V
*
AVR
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS + 6.0
VCC + 0.3
VSS + 6.0
VCC + 0.3
VSS + 6.0
Pins other than P44 and P55
Pins P44 and P45
Input voltage
VI
V
V
Pins other than P44 and P55
Pins P44 and P45
Output voltage
VO
“L” level maximum
output current
IOL
IOLAV
ΣIOL
15
4
mA
mA
mA
mA
mA
mA
mA
mA
“L” level average
output current
Average value (operating cur-
rent × operating ratio)
“L” level total maximum
output current
100
40
“L” level total average
output current
Average value (operating cur-
rent × operating ratio)
ΣIOLAV
IOH
“H” level maximum
output current
−15
−4
“H” level average
output current
Average value (operating cur-
rent × operating ratio)
IOHAV
ΣIOH
ΣIOHAV
“H” level total maximum
output current
−50
−20
“H” level total average
output current
Average value (operating cur-
rent × operating ratio)
300
450
Power consumption
PD
mW
MB89F969A only
Operating temperature
Storage temperature
TA
−40
−55
+85
°C
°C
Tstg
+150
* : Set AVCC to the same potential as VCC.
Also ensure that AVCC does not exceed VCC at power on.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
26
MB89960 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Parameter
Symbol
Unit
Remarks
Min.
Max.
Normal operation guaranteed range
(MB89965/P965A/F969A)
3.5*
5.5*
V
V
V
V
To maintain RAM state in stop mode
(MB89965/P965A/F969A)
3.0
2.7*
1.5
5.5
5.5*
5.5
VCC
AVCC
Power supply voltage
Operating temperature
Normal operation guaranteed range
(MB89PV960)
To maintain RAM state in stop mode
(MB89PV960)
AVR
3.5
AVCC
V
TA
−40
+85
°C
* : Differs depending on the operating frequency and analog guaranteed range. See the figure below and
“5. Electrical Characteristics for the A/D Converter”.
Operating Voltage − Operating frequency
Analog accuracy guaranteed range : VCC = AVCC = 3.5 V to 5.5 V
6
5
Operation guaranteed range
4
3.5
3
2.7
: MB89PV960
2
: MB89965, MB89P965A, and MB89F969A
1
2
3
4
5
6
7
8
9
10
Operating Frequency (MHz)
The figure above shows the frequency of the external oscillator when the instruction cycle setting is 4/FC. As the
operating voltage depends on the instruction cycle, change to the new instruction cycle value if using the gear
function to change the operating speed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
27
MB89960 Series
3. DC Characteristics
Sym-
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Pin Name
Condition
Unit Remarks
bol
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P30 to P34
VIH
0.7 VCC
VCC + 0.3
V
RST, INT20 to
INT27, INT10 to
INT12, SI, SCK,
EC, TEST
VIHS
0.8 VCC
VCC + 0.3
V
“H” level input
voltage
MOD pin
input
VIHM MOD0/1/2
VCC − 0.3
VSS + 1.4
0.7 VCC
VCC + 0.3
VSS + 5.5
VSS + 5.5
V
WhenSMB
selected
VIHSMB
V
SCL, SDA
VIHI2C
When I2C
V
selected
P00 to P07,
VIL
P10 to P17,
P30 to P34
VSS − 0.3
VSS − 0.3
0.3 VCC
0.2 VCC
V
V
RST, INT20 to
INT27, INT10 to
INT12, SI, SCK,
EC, TEST
VILS
“L” level input
voltage
MOD pin
input
VILM MOD0/1/2
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS + 0.3
VSS + 0.6
0.3 VCC
V
WhenSMB
selected
VILSMB
V
SCL, SDA
VILI2C
When I2C
V
selected
Voltage applied to
open drain output
pins
VD
P40 to P45
VSS − 0.3
VCC + 0.3
V
V
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P34
“H” level output
voltage
VOH
IOH = −2.0 mA
IOL = 4.0 mA
4.0
P00 to P07,
P10 to P17,
“L” level output
voltage
VOL P20 to P27,
P30 to P34,
0.4
V
P40 to P45, RST
(Continued)
28
MB89960 Series
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym-
bol
Parameter
Pin Name
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P34,
P40 to P45
−5
+5
Without pull-
µA up resistor
Input leak
current
ILI
0 V < VI < VCC
option
MOD0/1/2,
TEST
−10
+10
+5
Open-drain
output leak
current
ILIOD P40 to P45
0 V < VI < VSS + 5.5 V
µA
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P34,
P40 to P45,
RST
With pull-up
resistor
option
Pull-up
resistance
RPULL
VI = 0.0 V
25
50
100
Ω
10
4
20
7
MB89PV960
FCH = 10.0 MHz
tINST*2 = 0.4 µs
main run mode
MB89965
MB89P965A
ICC1
mA
5
3
8
8
MB89F969A
MB89PV960
VCC
(when using
an external
clock)
FCH = 10.0 MHz
tINST*2 = 6.4 µs
main run mode
Power supply
current*1
MB89965
MB89P965A
MB89F969A
ICC2
mA
mA
1
3
2
3
8
4
MB89PV960
FCH = 10.0 MHz
tINST*2 = 0.4 µs
main sleep mode
MB89965
MB89P965A
MB89F969A
ICCS1
(Continued)
29
MB89960 Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym-
bol
Parameter
Pin Name
Condition
Unit
mA
µA
Remarks
Min.
Typ.
Max.
FCH = 10.0 MHz
tINST*2 = 6.4 µs
main sleep mode
ICCS2
1
3
70
20
150
100
MB89PV960
MB89965
FCH = 32.768 kHz
sub run mode
ICCL
MB89P965A
MB89F969A
0.3
10
1
mA
VCC
Power supply
current*1
(when using
an external
clock)
FCH = 32.768 kHz
sub sleep mode
ICCLS
ICCT
50
µA
FCH = 32.768 kHz
• clock mode, main stop
mode
5
1
5
15
10
10
µA
µA
pF
MB89PV960
TA = +25 °C
• sub stop mode
MB89965
MB89P965A
MB89F969A
ICCH
Except AVCC,
AVSS, VCC,
and AVSS
Input
capacitance
CIN
f = 1 MHz
10
*1 : The power supply current values are for an external clock.
*2 : See “ (4) Instruction Cycle” in “4. AC Characteristics”.
30
MB89960 Series
4. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min.
Max.
RST “L” pulse width
tZLZH
48 tHCYL*
ns
* : tHCYL is the period (1/FC) of the oscillation input to X0.
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-On Reset
Parameter
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Condition
Unit
Remarks
Min.
0.5
1
Max.
Power supply rising time
Power supply cutoff time
tR
50
ms
ns
tOFF
For repeated operation
Note : Ensure that the power supply rising time is less than the selected oscillation stabilization delay time.
For example, if the main clock frequency FC = 10 MHz and 214/FC is selected as the oscillation stabilization
delay time, the resulting oscillation stabilization delay time is 1.6 ms. As rapid changes in the power supply
voltage may cause a power-on reset, if you need to change the power supply voltage while the device is
operating, ensure that the power supply voltage changes smoothly.
tR
tOFF
2.0 V
0.2 V
0.2 V
0.2 V
VCC
31
MB89960 Series
(3) Clock Timings
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Typ.
Parameter
Symbol Pin Name
Unit
Remarks
Min.
Max.
FCH
FCL
X0, X1
X0A, X1A
X0, X1
1
10
MHz Main clock
kHz Sub clock
Clock frequency
32.768
30.5
tHCYL
tLCYL
100
20
1000
ns
Main clock
Sub clock
Clock cycle time
X0A, X1A
µs
PWH
PWL
X0
X0A
X0
ns
µs
ns
External clock
External clock
External clock
Input clock pulse width
PWHL
PWLL
15.2
tCR
tCF
Input clock rising/falling time
10
• X0 and X1 clock timing and input conditions
tHCYL
PWH
PWL
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Clock configurations
When using
a crystal oscillator
or ceramic oscillator
When using
an external clock
X0
X1
X0
X1
FCH
Open circuit
FCH
C2
C1
32
MB89960 Series
• X0A and X1A clock timing conditions
tLCYL
PWHL
PWLL
tCR
tCF
0.8 VCC 0.8 VCC
0.2 VCC
X0A
0.2 VCC
0.2 VCC
• Sub clock configuration
When using
a crystal oscillator
or ceramic oscillator
When using
an external clock
X0A
X1A
X0A
X1A
Open circuit
FCL
C2
FCL
C1
(4) Instruction Cycle
Parameter
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Value
Unit
Remarks
FCH = 10 MHz (4/FCH) operation
4/FCH, 8/FCH, 16/FCH, 64/FCH
2/FCL
time
tINST = 0.4 µs
Instruction cycle
(Minimum instruction
execution time)
tINST
µs
FCL = 32.768 kHz operation
time
tINST = 61.036 µs
33
MB89960 Series
(5) Serial I/O Timings
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym-
bol
Parameter
Pin Name Condition
Unit Remarks
Min.
2 tINST*
−200
200
Max.
Serial clock cycle time
SCK ↓ → SO delay time
Valid SI → SCK ↑
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
SCK
SCK, SO
SCK, SI
SCK, SI
SCK
µs
ns
ns
ns
µs
µs
ns
µs
µs
Internal
clock
operation
200
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO delay time
Valid SI → SCK
200
tINST*
tINST*
0
SCK
External
clock
operation
SCK, SO
SCK, SI
SCK, SI
200
200
SCK ↑ → valid SI hold time
200
* : See “ (4) Instruction cycle” for a definition of tINST.
• Internal shift clock mode
tSCYC
0.8 VCC
SCK
0.2 VCC
tSLOV
0.2 VCC
0.8 VCC
0.2 VCC
SO
SI
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
SCK
SO
SI
0.2 VCC
0.2 VCC
tSLOV
0.8 VCC
0.2 VCC
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
34
MB89960 Series
(6) Peripheral Input Timings
Parameter
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin Name
Unit Remarks
Min.
Max.
Peripheral input “H” pulse width
Peripheral input “L” pulse width
tILIH
tIHIL
2 tINST*
2 tINST*
µs
µs
INT10 to INT12,
INT20 to INT27, EC
* : See “ (4) Instruction cycle” for a definition of tINST.
tILIH
tIHIL
INT10 INT12,
INT20 INT27, EC
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
35
MB89960 Series
j
(7) I2C Timings
(VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym
bol
Parameter
Pin
Unit Remarks
Max.
Min.
1/4tINST*1 × m* × n*3 − 20
Start condition
output
SCL
SDA
tSTA
1/4tINST*1 × m*2 × n*3 + 20
ns Master mode
Stop condition
output
SCL 1/4tINST*1 × (m*2 × n*3 + 8) 1/4tINST*1 × (m*2 × n*3 + 8) +
tSTO
tSTA
ns Master mode
SDA
− 20
20
Start condition
detect
SCL
SDA
1/4tINST*1 × 6 + 40
ns
Stop condition
detect
SCL
SDA
tSTO
1/4tINST*1 × 6 + 40
ns
Restart condition out-
put
SCL 1/4tINST*1 × (m*2 × n*3 + 8) 1/4tINST*1 × (m*2 × n*3 + 8) +
tSTASU
ns Master mode
SDA
− 20
20
Restart condition de-
tect
SCL
SDA
tSTASU
1/4tINST*1 × 4+40
ns
SCL output “L” width tLOW SCL 1/4tINST*1 × m*2 × n*3 − 20
1/4tINST*1 × m*2 × n*3 + 20
ns Master mode
1/4tINST*1 × (m*2 × n*3 + 8) 1/4tINST*1 × (m*2 × n*3 + 8) +
SCL output “H” width tHIGH SCL
ns Master mode
− 20
20
SDA output delay
tDO SDA
tDOSU SDA
1/4tINST*1 × 4 − 20
1/4tINST*1 × 4 + 20
ns
ns
SDA output setup
time after interrupt
1/4tINST*1 × 4 − 20
1/4tINST*1 × 6 + 40
1/4tINST*1 × 2 + 40
SCL input “L” pulse
width
tLOW SCL
tHIGH SCL
ns
ns
SCL input “H” pulse
width
SDA input setup time tSU SDA
SDA hold time tHO SDA
40
0
ns
ns
*1: See “ (4) Instruction cycle” for a definition of tINST.
*2: m is the value set in the ICCR : CS4 and CS3 bits (bits 4 to 3) .
*3: n is the value set in the ICCR : CS2 to CS0 bits (bits 2 to 0) .
• Data transmit (master/slave)
tDO
tDO
tSU
tHO
tDOSU
SDA
ACK
tSTASU tSTA
tLOW
tHO
SCL
1
9
• Data receive (master/slave)
tDO
tDO
tDOSU
tSU
tHO
SDA
ACK
tHIGH
tLOW
tSTO
SCL
6
7
8
9
36
MB89960 Series
5. Electrical Characteristics for the A/D Converter
(AVcc = 3.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Sym
bol
Parameter
Resolution
Pin
Condition
Unit Remarks
Min.
Typ.
Max.
10
bit
Total error
−5.0
−2.5
+5.0
+2.5
LSB
LSB
Non-linearity error
Differential
linearity error
−1.9
+1.9
LSB
mV
AVR − 3.5 AVR + 0.5 AVR + 4.5
AVR = AVCC
Zero transition voltage VOT
LSB
LSB
LSB
Full-scale transition
VFST
VCC − 6.5
VCC − 1.5
VCC + 1.5
mV
voltage
LSB
LSB
LSB
Variation between
channels
4
LSB
MB89965
µs MB89P965A
MB89F969A
60 tINST*1
A/D mode conversion
time*2
38 tINST*1
16 tINST*1
µs MB89PV960
A/D sampling time
µs
Analog input current
IAIN
VAIN
IA
10
AVR
3
µA
AN0
to
AN3
Analog input voltage
range
AVSS
V
A/D operation
1.5
1
mA
µA
Power supply current
Reference voltage
AVCC
TA = + 25 °C
A/D stop
IAH
5
AVSS + 3.5
AVCC
V
IR AVR A/D operation
IRH A/D stop
400
µA
µA
Reference voltage
supply current
5
*1 : See “ (4) Instruction cycle” for a definition of tINST.
*2 : Includes sampling time.
37
MB89960 Series
6. A/D Converter Glossary
• Resolution
The change in analog voltage that can be recognized by the A/D converter.
• Linearity error (unit : LSB)
The deviation between the actual conversion characteristics and the line linking the zero transition point (“00
0000 0000B” ←→ “00 0000 0001B”) and the full scale transition point (“11 1111 1110B” ←→ “11 1111 1111B”) .
• Differential linearity error (unit : LSB)
The variation from the ideal input voltage required to change the output code by 1 LSB.
• Total error (unit : LSB)
The total error is the difference between the actual value and the theoretical value.
Total Error
Theoretical I/O Characteristics
3FFH
3FEH
3FDH
VFST
3FFH
3FEH
3FDH
Actual conversion
characteristic
1.5 LSB
{1 LSB × N + 0.5 LSB}
004H
003H
002H
001H
004H
003H
002H
001H
VNT
Actual conversion
characteristic
VOT
1 LSB
Theoretical characteristic
0.5 LSB
AVSS
AVR
AVSS
AVR
Analog input
Analog Input
VNT − {1 LSB × N + 0.5 LSB}
VFST − VOT
Total error for digital output N =
1 LSB =
(V)
1 LSB
1022
38
MB89960 Series
Full Scale Transition Error
Theoretical characteristic
Zero Transition Error
004H
003H
Actual conversion
characteristic
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristic
002H
001H
VFST
(Actual
measured value)
Actual conversion
characteristic
Actual conversion
characteristic
VOT
(Actual measured value)
AVR
AVSS
Analog Input
Analog Input
Linearity Error
Differential Linearity Error
Theoretical characteristic
Actual conversion
Actual conversion
3FFH
3FEH
3FDH
characteristic
N + 1
{1 LSB × N + VOT}
characteristic
V (N + 1) T
VFST
(Actual
measured
value)
N
N − 1
N − 2
VNT
Actual conversion
characteristic
004H
003H
002H
001H
VNT
Actual conversion
characteristic
Theoretical characteristic
VOT (Actual measured value)
AVSS
AVR
AVSS
AVR
Analog input
Analog Input
VNT − {1 LSB × N + VOT}
V (N + 1) T − VNT
Linearity error of digital output N =
Differential linearity error of digital output N =
− 1
1 LSB
1 LSB
39
MB89960 Series
7. Notes for A/D Conversion
• Analog input pins and input impedance
The A/D converter incorporates a sample & hold circuit as shown below. When an A/D conversion starts, the
voltage at the analog input pin is captured by the sample & hold capacitor for a period of 16 instruction cycles.
Accordingly, if the output impedance of the external circuit connected to the analog input is high, the analog
input voltage may not stabilize within the period of the analog input sampling time. Therefore, ensure that the
output impedance of the external circuit is sufficiently low (10 kΩ or less) . If it is not possible to reduce the output
impedance of the external circuit, connecting an external capacitor of approximately 0.1 µF is recommended.
Equivalent circuit of analog input
MB89960 series
Sample & hold circuit
R
AN0 to AN3
Comparator
controller
C
Closed for approximately 16 instruction cycles
after initiating A/D conversion.
MB89965
MB89P965A
MB89F969A
Analog channel selector
R = 3.2 kΩ, C = 30 pF approx
MB89PV960 R = 1.4 kΩ, C = 64 pF approx.
• Error
The relative error increases as |AVR − AVSS| becomes smaller.
40
MB89960 Series
8. Electrical Characteristics of Flash Memory
• Programming and erasing characteristics
Value
Sym
bol Name
Pin
Parameter
Condition
Unit Remarks
Min. Typ. Max.
Power supply current*1
IFWE
VCC
VCC = 5.0 V
40
mA
Successful
completion
time
1
15
s
Fixed time
Sector erasing per sector
time
regardless of
size
Unsuccess-
ful comple-
tion time
*2
Successful
completion
time
8
3600 µs
Programming
time
per byte
Unsuccess-
ful comple-
tion time
650 3600 µs
*1 : Automatic algorithm executing
*2 : If a fault occurs during sector erasing, detection via DQ5 may not be available (DQ5 = 1 may not occur) .
Accordingly, a fault must be assumed after 15 s, even if DQ5 does not go to “1”.
41
MB89960 Series
■ MASK OPTIONS
MB89P965A/
MB89F969A
Part No.
MB89965
MB89PV960
Not available
NO
Specify when
ordering mask
Specifying procedure
Not available
Initial value* selection for main
clock oscillation stabilization
delay time (FCH = 10 MHz)
218/FCH
(26.2 ms approx.)
218/FCH
(26.2 ms approx.)
1
Selectable
• 01 : 212/FCH (0.4 ms approx.)
• 10 : 216/FCH (6.6 ms approx.)
• 11 : 218/FCH (26.2 ms approx.)
FCH : Frequency of main clock oscillation
* : This specifies the initial value after a reset of the oscillation stabilization delay time setting bits in the system
clock control register (SYCC : WT1, WT0)
■ ORDERING INFOMATION
Part Number
MB89965PFV1
MB89P965APFV1
MB89965CPFV1
Package
Remarks
Plastic LQFP, 48-pin
(FPT-48P-M05)
The MB89965PFV1 does not have an I2C
function.
MB89965PFM
MB89P965APFM
MB89965CPFM
Plastic QFP, 48-pin
(FPT-48P-M13)
The MB89965PFM does not have an I2C
function.
MB89965PF
MB89P965APF
MB89965CPF
Plastic QFP, 48-pin
(FPT-48P-M16)
The MB89965PF does not have an I2C
function.
Plastic LQFP, 64-pin
(FPT-64P-M09)
MB89F969APFM
MB89PV960CF
Ceramic MQFP, 48-pin
(MQP-48C-P01)
42
MB89960 Series
■ PACKAGE DIMENSIONS
(These package dimensions are provisional. Please obtain the actual dimensions of the final product separately.)
Plastic LQFP, 48-pin
Note : The pin width and thickness includes plating.
(FPT-48P-M05)
9.00±0.20(.354±.008)SQ
7.00±0.10(.276±.004)SQ
0.145±0.055
(.006±.002)
36
25
37
24
Details of "A" part
0.08(.003)
1.50 –+00..1200
(Mounting height)
.059 –+..000048
INDEX
48
13
0.10±0.10
(.004±.004)
(Stand off)
"A"
0°~8°
1
12
LEAD No.
0.50(.020)
0.25(.010)
0.20±0.05
0.50±0.20
(.020±.008)
M
0.08(.003)
(.008±.002)
0.60±0.15
(.024±.006)
C
2000 FUJITSU LIMITED F48013S-c-4-8
Dimensions in mm (inches).
43
MB89960 Series
Plastic QFP, 48-pin
(FPT-48P-M13)
13.10±0.40 SQ
(.516±.016)
2.35(.093)MAX
(Mounting height)
10.00±0.20 SQ
(.394±.008)
0(0)MIN
(STAND OFF)
36
25
Details of "A" part
37
24
0.15(.006)
0.20(.008)
8.80
(.346)
REF
11.50±0.30
(.453±.012)
INDEX
"A"
0.18(.007)MAX
0.53(.021)MAX
48
13
Details of "B" part
1
12
LEAD No.
0.80(.0315)TYP
0.15±0.05
(.006±.002)
0.30±0.10
(.012±.004)
M
0.16(.006)
0~10°
"B"
0.80±0.30
(.031±.012)
0.10(.004)
C
2000 FUJITSU LIMITED F48023S-1C-2
Dimensions in mm (inches).
44
MB89960 Series
Plastic QFP, 48-pin
(FPT-48P-M16)
17.20±0.40 SQ
2.70(.106)MAX
(.677±.016)
12.00 +–00..1300 SQ
.472 –+..000142
(Mounting height)
0.05(.002)MIN
(STAND OFF)
36
25
Details of "A" part
0.15(.006)
37
24
8.80
(.346)
REF
13.60±0.40
(.535±.016)
0.20(.008)
0.15(.006)MAX
0.50(.020)MAX
INDEX
"A"
48
13
Details of "B" part
1
12
LEAD No.
0.15 –+00..0015
.006 +–..0000024
0.80(.0315)TYP
0.30±0.06
(.012±.002)
M
0.16(.006)
0~10°
"B"
1.80±0.30
(.071±.012)
0.15(.006)
C
2000 FUJITSU LIMITED F48026S-1C-2
Dimensions in mm (inches).
45
MB89960 Series
Ceramic MQFP, 48-pin
(MQP-48C-P01)
17.20(.677)TYP
15.00±0.25
(.591±.010)
1.50(.059)TYP
1.00(.040)TYP
8.80(.346)REF
PIN No.1 INDEX
14.82±0.35
(.583±.014)
0.80±0.22
(.0315±.0087)
PIN No.1 INDEX
1.02±0.13
(.040±.005)
10.92 +–00..013
.430 +–0.005
8.71(.343)
TYP
7.14(.281)
TYP
PAD No.1 INDEX
4.50(.177)TYP
1.10 +–00..2455
0.40±0.08
(.016±.003)
0.60(.024)TYP
0.30(.012)TYP
.043 –+..001108
8.50(.335)MAX
0.15±0.05
(.006±.002)
C
1994 FUJITSU LIMITED M48001SC-4-2
Dimensions in mm (inches).
46
MB89960 Series
Plastic LQFP, 64-pin
(FPT-64P-M09)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
1.50 –+00..1200
48
33
32
(Mounting height)
.059 +–..000048
49
9.75
(.384)
REF
13.00
(.512)
NOM
1 PIN INDEX
64
17
M
1
16
Details of "A" part
LEAD No.
"A"
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.127 +–00..0025
.005 +–..000012
0.10±0.10
(.004±.004)
0.13(.005)
(STAND OFF)
0.50±0.20
(.020±.008)
0.10(.004)
0
10°
C
2000 FUJITSU LIMITED F64018S-1C-3
Dimensions in mm (inches).
47
MB89960 Series
FUJITSU LIMITED
For further information please contact:
Japan
All Rights Reserved.
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
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North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
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The products described in this document are designed, and
manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use,
and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks
or dangers that, unless extremely high safety is secured, could have
a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
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third party for any claims or damages arising in connection with
above-mentioned uses of the products.
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Asia Pacific
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
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Korea
FUJITSU MICROELECTRONICS KOREA LTD.
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F0104
FUJITSU LIMITED Printed in Japan
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