MB89PV530 [FUJITSU]
8-bit Original Microcontroller; 8位微控制器的原始
| 型号： | MB89PV530 |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Original Microcontroller |
| 文件： | 总65页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12548-3E
8-bit Original Microcontroller
CMOS
F2MC-8L MB89530 Series
MB89537/537C/538/538C
MB89F538L/P538/PV530
■ DESCRIPTION
The MB89530 series is a one-chip microcontroller featuring the F2MC-8L core supporting low-voltage and high-
speed operation. Built-in peripheral functions include timers, serial interface, A/D converter, and external interrupt.
This product is an ideal general-purpose one-chip microcontroller for a wide variety of applications from household
to industrial equipment, as well as use in portable devices.
■ FEATURES
• Wide range of package options
• QFP package (1mm pitch)
• Two types of LQFP packages (0.5mm pitch, 0.65mm pitch)
• SH-DIP package
• BCC package (0.5mm pitch)
• Low voltage, high-speed operating capability
• Minimum instruction execution time 0.32 µs (at base oscillator 12.5MHz)
• F2MC-8L CPU Core
• Instruction set optimized for controller operation
• Multiplication/division instructions
• 16-bit calculation
• Branching instructions with bit testing
• Bit operation instructions, etc.
• Five timer systems
• 8-bit PWM timer with 2 channels (usable as either interval timer of PWM timer)
• Pulse width count timer (supports continuous measurement or remote control receiving applications)
• 16-bit timer counter
• 21-bit time base timer
• Watch prescaler (17-bit)
• UART
• Synchronous or asynchronous operation, switchable
• 2 serial interfaces (serial I/O)
• Selection of transfer direction (specify MSB first or LSB first) for communication with a variety of devices
(Continued)
MB89530 Series
(Continued)
• 10-bit A/D converter (8 channels)
• External clock input for startup support (except for MB89F538L)
• Time base timer output for startup support
• Pulse generators (PPG) with 2-program capability
• 6-bit PPG with selection of pulse width and pulse period
• 12-bit PPG (2 channels) with selection of pulse width and pulse period
• I2C interface circuits
• External interrupt 1 (single-clock : 4 channels, dual-clock : 3 channels)
• 4 or 3 independent inputs, release enabled from standby mode (includes edge detection function)
• External interrupt 2 (except for MB89F538L : 8 channels, MB89F538L : 7 channels)
• 8 or 7 independent inputs, release enabled form standby mode (includes level edge detection function)
• Standby modes (low power consumption modes)
• Stop mode (oscillator stops, virtually no power consumed)
• Sleep mode (CPU stops, power consumption reduced to one-third)
• Sub clock mode
• Watch mode
• Watchdog timer reset
• I/O ports
• Maximum port
single-clock : except for MB89F538L : 53
MB89F538L : 52
: except for MB89F538L : 51
MB89F538L : 50
dual-clock
• 38 general-purpose I/O ports (CMOS) (MB89F538L : 37)
• 2 general-purpose I/O ports (N-ch open drain)
• 8 general-purpose output ports (N-ch open drain)
• General-purpose input ports(CMOS)single-clock : except for MB89F538L : 5
dual-clock : except for MB89F538L : 3
2
MB89530 Series
■ PACKAGES
64-pin, Plastic SH-DIP
64-pin, Plastic LQFP
64-pin, Plastic QFP
(DIP-64P-M01)
(FPT-64P-M03)
(FPT-64P-M06)
64-pin, Plastic LQFP
64-pin, Ceramic MDIP
64-pin, Ceramic MQFP
(FPT-64P-M09)
(MDP-64C-P02)
(MQP-64C-P01)
64-pin, Plastic BCC
(LCC-64P-M19)
(LCC-64P-M16)
3
MB89530 Series
■ PRODUCT LINEUP
Part number
MB89537/
MB89538/
538C
MB89F538L
MB89P538
MB89PV530
537C
Parameter
One-time
programmable
Type
Mass produced (Mask ROM)
FLASH
Evaluation
48 K × 8-bit
(built-in FLASH
memory)
(write from
general purpose
EPROM writer)
48 K × 8-bit
(built-in ROM)
(write from
general purpose
EPROM writer)
48 K × 8-bit
(external
ROM) *2
32 K × 8-bit
(built-in ROM) (built-in ROM)
48 K × 8-bit
ROM capacity
RAM capacity
1 K × 8-bit
2 K × 8-bit
2.2 V to 3.6 V*1 (MB89537/538/
537C/538C)
Operating voltage
2.4 V to 3.6 V*1
2.7 V to 5.5 V
Basic instructions
Instruction bit length
Instruction length
Data bit length
: 136
: 8-bits
: 1 bit to 3 bits
: 1, 8, 16-bits
CPU functions
Minimum instruction execution time : 0.32 µs / 12.5 MHz
Minimum interrupt processing time : 2.88 µs / 12.5 MHz
Input ports
: single-clock 5 (4 also usable as external interrupts)
dual-clock 3 (3 also usable as external interrupts)
Output-only ports (N-ch open drain)
: 8 (8 also usable as ADC input)
I/O ports (N-ch open drain)
I/O ports (CMOS)
: 2 (2 also usable as SO2/SDA or SI2/SCL)
: 38 (21 have no other function)
Ports
(except for MB89F538L)
I/O ports (CMOS)
: 37 (21 have no other function)
(MB89F538L)
Total (except for MB89F538L) : single-clock 53, 2system clock 51
Total (MB89F538L)
: single-clock 52, 2system clock 50
21 bits
Time base timer Interrupt periods at main clock oscillation frequency of 12.5MHz
(approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms)
Reset period of approx. 167.8 ms to 335.6 ms at mail clock frequency of 12.5 MHz
Watchdog timer
Reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 kHz.
8-bit interval timer operation
(supports square wave output, operating clock period : 1, 8, 16, 64 tinst*3)
PWM timer
Pulse width measurement with 8-bit resolution (conversion period : 28 tinst*3 to 28 × 64 tinst*3)
2 channels (can also be used as interval timer, can also be used as ch1 output and ch2
count clock)
Interval times at 17-bit sub clock base frequency of 32.768 kHz
(approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s)
Watch prescaler
(Continued)
4
MB89530 Series
(Continued)
Part number
MB89537/537C MB89538/538C
MB89F538L
MB89P538
MB89PV530
Parameter
8-bit one-shot timer operation
(supports underflow output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit reload timer operation
(supports square wave output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit pulse width measurement operation
Pulse width
count timer
(continuous measurement, H width measurement, L width measurement, rise-to-rise, fall-
to-fall, H width measurement and rise-to-rise)
16-bit timer operation (operating clock period : 1 tinst*3, external)
16-bit event counter operation (select rising, falling, or both edges)
16-bit × 1 ch
16-bit timer/
counter
Serial I/O
8 bit length, Selection of LSB first or MSB first, Transfer clock (2, 8, 32 tinst*3, external)
CLK synchronous/CLK asynchronous data transfer capability (8, 9 bit with parity bit, or 7,8
bit without parity bit) .
UART/SIO
Built-in baud rate generator provides selection of 14 baud rate settings.
CLK synchronous/CLK asynchronous data transfer capability (4, 6, 7, 8 bit with parity bit,
or 5, 7, 8, 9 bit without parity bit) .
UART
Built-in baud rate generator provides selection of 14 baud rate settings.
External clock output, 2-channel 8-bit PWM timer output also available for baud rate set-
tings.
Single-clock : 4-channel independent, dual-clock : 3-channel independent
Selection of rising, falling, or both edge detection.
Can be used for recovery from standby mode (edge detection also available in stop mode) .
External
interrupt 1
Except for MB89F538L : 8-channel independent L level detection, MB89F538L : 7-channel
independent L level detection
Can be used for recovery from standby mode.
External
interrupt 2
6-bit PPG,
12-bit PPG
Can generate square wave signals with programmable period.
6-bit × 1 channel or 12-bit × 2 channels.
1-channel , compatible with Intel System Administrator bus version 1.0 and Philips I2C
I2C bus interface specifications.
2-line communications (on MB89PV530/P538/F538L/537C/538C)
10-bit resolution × 8 channels.
A/D conversion functions (conversion time : 60 tinst *3)
Supports repeated calls from external clock (except for MB89F538L)
Supports repeated calls from internal clock.
Standard voltage input provided (AVR)
A/D converter
Standby modes
(power saving
modes)
Sleep mode, stop mode, sub clock mode, watch mode.
CMOS
Process
*1 : Depends on operating frequency.
*2 : Using external ROM and MBM27C512.
*3 : tinst represents instruction execution time. This can be selected as 1/4, 1/8, 1/16, 1/64 of the main clock
cycle or 1/2 of the sub clock cycle.
Note : MB89537/538 have no built-in I2C functions.
To use I2C functions, choose the MB89PV530/P538/F538L/MB89537C/538C.
5
MB89530 Series
■ MODEL DIFFERENCES AND SELECTION CONSIDERATIONS
Part number
MB89537/537C MB89538/538C MB89F538L
Package
MB89P538
MB89PV530
DIP-64P-M01
FPT-64P-M03
FPT-64P-M06
FPT-64P-M09
LCC-64P-M19
LCC-64P-M16
MDP-64C-P02
MQP-64C-P01
O
O
O
O
X
X
X
X
O
O
O
O
X
X
X
X
O
X
O
O
O
X
X
X
O
X
X
X
X
X
X
X
O
O
O
O
X
O*
X
X
O : Model-package combination available
X : Model-package combination not available
* : Only for ES
Conversion sockets for pin pitch conversion (manufactured by Sunhayato Corp.) can be used.
Contact : Sunhayato Corp. : TEL : +81-3-3984-7791
FAX : +81-3-3971-0535
E-mail : adapter@sunhayato.co.jp
6
MB89530 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Capacity
When this product is used in a piggy-back or other evaluation configuration, it is necessary to carefully confirm
the differences between the model being used and the product it is evaluating. Particular attention should be
given to the following (see " CPU core 1. Memory Space") .
• The program ROM area starts from address 4000H on the MB89P538, MB89F538L and MB89PV530 models.
• Note upper limits on RAM, such as stack areas, etc.
2. Current Consumption
• On the MB89PV530, the additional current consumed by the EPROM is added at the connecting socket on
the back side.
• When operating at low speed, the current consumption in the one-time PROM or EPROM models is greater
than on the mask ROM models. However, current consumption in sleep or stop modes is identical.
For details, refer to “ ELECTRICAL CHARACTERISTICS”.
3. Mask Options
The options available for use, and the method of specifying options, differ according to the model. Before use,
check the “ MASK OPTIONS” specification section.
4. Wild Register Functions
The following table shows areas in which wild register functions can be used.
Wild Register Usage Areas
Part number
Address space
4000H to FFFFH
4000H to FFFFH
4000H to FFFFH
8000H to FFFFH
4000H to FFFFH
MB89PV530
MB89P538
MB89F538L
MB89537/537C
MB89538/538C
7
MB89530 Series
■ PIN ASSIGNMENTS
(TOP VIEW)
P36/WTO
P37/PTO1
P40/INT20/EC
P41/INT21/SCK2
P42/INT22/SO2/SDA
P43/INT23/SI2/SCL
P44/INT24/UCK2
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST/MOD2*2
P50/AN0
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1 (UO1)
P31/SCK1 (UCK1) /LMCO
P30/PPG03/MCO
C/NC *4
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20/PWCK
P21/PPG01
P22/PPG02
P23
P24
P25
1
*
65
66
67
68
69
70
71
72
73
74
75
76
77
78
92
VCC
A14
A13
A8
A15
A12
A7
A6
A5
A4
A3
A2
A1
91
90
89
88
87
86
85
84
83
82
81
80
79
A9
A11
OE
A10
CE
O8
O7
O6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
A0
O1
O2
O3
VSS
O5
O4
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P63/INT13/X0A*3
P64/X1A*3
RST
MOD0
MOD1
X0
X1
VSS
P26
P27
(DIP-64P-M01)
(MDP-64C-P02)
*1 : Package top pin assignments (MB89PV530 only)
Pin no.
65
Pin name
A15
A12
A7
Pin no.
73
Pin name
A1
Pin no.
81
Pin name
O6
Pin no.
89
Pin name
A8
A13
A14
VCC
66
74
A0
82
O7
90
67
75
O1
83
O8
91
68
A6
76
O2
84
CE
92
69
A5
77
O3
85
A10
OE
70
A4
78
VSS
86
71
A3
79
O4
87
A11
A9
72
A2
80
O5
88
N.C. : Internal connection only. Not for use.
*2 : Pin 10 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L.
*3 : Pin 25 and 26 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock.
*4 : The function of pin 57 depends on the model. For details, see “■PIN DESCRIPTIONS” and “■HANDLING
DEVICES”.
(Continued)
8
MB89530 Series
(TOP VIEW)
P46/INT26/UI2
P47/INT27/ADST/MOD2*1
P50/AN0
1
2
3
4
5
6
7
8
48
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
9
10
11
12
13
14
15
16
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
(FPT-64P-M03)
(FPT-64P-M09)
*1 : Pin 2 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L.
*2 : Pin 17 and 18 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock.
*3 : The function of pin 49 depends on the model. For details, see “■PIN DESCRIPTIONS” and “■HANDLING
DEVICES”.
(Continued)
9
MB89530 Series
(TOP VIEW)
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST/MOD2*2
P50/AN0
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P30/PPG03/MCO
C/NC*4
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
*1
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
85
77
76
75
74
73
72
71
70
69
86
87
88
89
90
91
92
93
9
10
11
12
13
14
15
16
17
18
19
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P63/INT13/X0A*3
P64/X1A*3
P17
P20/PWCK
(FPT-64P-M06)
(MQP-64C-P01)
*1 : Package top pin assignments (MB89PV530 only)
Pin no.
65
Pin name
N.C.
A15
A12
A7
Pin no.
73
Pin name
A2
Pin no.
81
Pin name
N.C.
O4
Pin no.
89
Pin name
OE
66
74
A1
82
90
N.C.
A11
A9
67
75
A0
83
O5
91
68
76
N.C.
O1
84
O6
92
69
A6
77
85
O7
93
A8
70
A5
78
O2
86
O8
94
A13
A14
VCC
71
A4
79
O3
87
CE
95
72
A3
80
VSS
88
A10
96
N.C. : Internal connection only. Not for use.
*2 : Pin 3 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L.
*3 : Pin 18 and 19 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock.
*4 : The function of pin 50 depends on the model. For details, see “■PIN DESCRIPTIONS” and “■HANDLING
DEVICES”.
(Continued)
10
MB89530 Series
(Continued)
(TOP VIEW)
P46/INT26/UI2
P47/INT27/ADST/MOD2
1
2
1
48
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(LCC-64P-M19)
(LCC-64P-M16) *4
*1 : Pin 2 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L.
*2 : Pin 17 and 18 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock.
*3 : The function of pin 49 depends on the model. For details, see “■PIN DESCRIPTIONS” and “■HANDLING
DEVICES”.
*4 : Only for ES
11
MB89530 Series
■ PIN DESCRIPTIONS
Pin no.
I/O
Pin name circuit
type
SH-DIP*1
MDIP*2
QFP*3
LQFP*5
BCC*6
Function
MQFP*4
30
31
23
24
22
23
X0
Connecting pins to crystal oscillator circuit or other os-
cillator circuit. The X0 pin can connect to an external
clock. In that case, X1 is left open.
A
X1
28
29
21
22
20
21
MOD0
B
Input pins for memory access mode setting. Connect di-
rectly to Vss.
MOD1
Reset I/O pin. This pin has pull-up resistance with
CMOS I/O or hysteresis input. At an internal reset re-
quest, an ’L’ signal is output. An ’L’ level input initializes
the internal circuits.
27
20
19
RST
C
56 to 49 49 to 42 48 to 41 P00 to P07
48 to 41 41 to 34 40 to 33 P10 to P17
D
D
General purpose I/O ports.
General purpose I/O ports.
General purpose I/O port.Resource I/O pin (hysteresis
input).Hysteresis input. This pin also functions as a
PWC input.
40
33
32
P20/PWCK
E
P21/
PPG01
General purpose I/O port.This pin also functions as the
PPG01 output.
39
38
32
31
31
30
D
D
P22/
PPG02
General purpose I/O port.This pin also functions as the
PPG02 output.
37
36
35
34
33
30
29
28
27
26
29
28
27
26
25
P23
P24
P25
P26
P27
D
D
D
D
D
General purpose I/O port.
General purpose I/O port.
General purpose I/O port.
General purpose I/O port.
General purpose I/O port.
P30/
PPG03/
MCO
General purpose I/O port.This pin also functions as the
PPG03 output.
58
51
50
D
P31/SCK1
(UCK1) /
LMCO
General purpose I/O port.Resource I/O pin (hysteresis
input).This pin also functions as the UART/SIO clock in-
put/output pin.
59
60
61
52
53
54
51
52
53
E
D
E
P32/SO1
(UO1)
General purpose I/O port.This pin also functions as the
UART/SIO clock input/output pin.
General purpose I/O port.Resource input/output pin
(hysteresis input).This pin also functions as the UART/
SIO serial data input pin.
P33/SI1
(UI1)
General purpose I/O port.This pin also functions as the
PWM time 2 output pin.
62
63
55
56
54
55
P34/PTO2
P35/PWC
D
E
General purpose I/O port.Resource I/O pin (hysteresis
input).This pin also functions as a PWC input.
(Continued)
12
MB89530 Series
Pin no.
I/O
Pin name circuit
type
SH-DIP*1
MDIP*2
QFP*3
LQFP*5
BCC*6
Function
MQFP*4
General purpose I/O port.Resource output.This pin also
functions as the PWC output pin.
1
2
58
59
57
58
P36/WTO
P37/PTO1
D
D
General purpose I/O port.Resource output.This pin also
functions as the PWM timer 1 output pin.
General purpose I/O port.Resource I/O pin (hysteresis
input)This pin also functions as an external interrupt
input or 16-bit timer/counter input.
P40/INT20/
EC
3
4
60
61
59
60
E
E
General purpose I/O port.Resource I/O pin (hysteresis
input)This pin also functions as an external interrupt
input or SIO clock I/O pin.
P41/INT21/
SCK2
N-ch open drain output.
P42/INT22/
SO2/SDA
Resource I/O pin (hysteresis only for INT22 input) .
This pin also functions as an external interrupt input,
SIO serial data output, or I2C data line.
5
6
7
8
9
62
63
64
1
61
62
63
64
1
G
G
E
E
E
E
N-ch open drain output.
P43/INT23/
SI2/SCL
Resource I/O pin (hysteresis only for INT23 input) .
This pin also functions as an external interrupt, SIO
serial data input, or I2C clock I/O pin.
General purpose I/O port.
P44/INT24/
UCK2
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
UART clock I/O pin.
General purpose I/O port.
P45/INT25/
UO2
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
UART data output pin.
General purpose I/O port.
P46/INT26/
UI2
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
UART data input pin.
2
except General purpose I/O port.
P47/INT27/
ADST
for
Resource I/O pin (hysteresis input) .
MB89F This pin also functions as an external interrupt
538L input or A/D converter clock input pin.
10
3
2
MB89F Input pin for memory access mode setting.
538L Connect to VSS directly.
MOD2
B
H
N-ch open drain output port.
This pin also functions as an A/D converter analog input
pin.
P50/AN0to
P57/AN7
11 to 18
4 to 11
3 to 10
P60/INT10
to
P62/INT12
General purpose input port.
Resource input pin (hysteresis input) .
This pin also functions as an external interrupt input pin.
22 to 24 15 to 17 14 to 16
I
(Continued)
13
MB89530 Series
(Continued)
Pin no.
I/O
Pin name circuit
type
SH-DIP*1
MDIP*2
QFP*3
LQFP*5
BCC*6
Function
MQFP*4
General purpose input port.
Resource input pin (hystere-
sis input) .
This pin also functions as an
external interrupt.
P63/INT13
I
Single-clock
25
18
17
X0A
P64
X1A
VCC
A
J
Dual-clock
Connected pin for sub clock.
General purpose input port.
Connected pin for sub clock.
Single-clock
26
19
18
A
Dual-clock
64
32
19
20
57
25
12
13
56
24
11
12
Power supply pin.
Ground pin (GND) .
VSS
AVCC
AVR
A/D converter power supply pin.
A/D converter reference voltage input pin.
A/D converter power supply pin.
Used at the same voltage level as the Vss supply.
21
14
13
AVSS
MB89P538
Fixed at Vss.
MB89PV530
MB89F538L
57
50
49
C
N.C. pin
MB89537/537C
MB89538/538C
*1 : DIP-64P-M01
*2 : MDP-64C-P02
*3 : FPT-64P-M06
*4 : MQP-64C-P01
*5 : FPT-64P-M03/M09
*6 : LCC-64P-M19/M16
14
MB89530 Series
External EPROM Socket Pin Function Descriptions (MB89PV530 only)
Pin no.
I/O Circuit
Pin name
Function
type
MDIP*1
MQFP*2
65
66
67
68
69
70
71
72
73
74
66
67
68
69
70
71
72
73
74
75
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins.
75
76
77
77
78
79
O1
O2
O3
I
Data input pins.
78
80
VSS
O
Power supply pin (GND) .
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
I
Data input pins.
ROM chip enable pin. Outputs an “H” level signal in standby
mode.
84
87
CE
O
85
86
88
89
A10
OE
O
O
Address output pin.
ROM output enable pin. Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8
O
Address output pins.
90
91
92
94
95
96
A13
A14
VCC
O
O
O
EPROM power supply pin.
65
76
81
90
Internally connected.
These pins always left open.
N.C.
O
*1 : MDP-64C-P02
*2 : MQP-64C-P01
15
MB89530 Series
■ I/O CIRCUIT TYPES
Type
Circuit
Remarks
Oscillator feedback resistance
• High speed side = approx. 1 MΩ
X1 (X1A)
Nch Pch
• Low speed side = approx. 10 MΩ
Pch
Nch
X0 (X0A)
A
• Hysteresis input
• Pull-down resistance built-in to
MB89537/537C
B
MB89538/538C
• Pull-up resistance approx. 50 kΩ
• Hysteresis input
R
Pch
C
Nch
• CMOS I/O
• Software pull-up resistance can be
used. Approx. 50 kΩ
R
Pull-up control
resistor
Pch
Pch
D
Nch
• CMOS I/O
• Software pull-up resistance can be
used. Approx. 50 kΩ
R
Pull-up control
resistors
Pch
Pch
E
Nch
Port input
Resource input
(Continued)
16
MB89530 Series
(Continued)
Type
Circuit
Remarks
• N-ch open drain output
• Hysteresis input
• CMOS input
Nch
G
Resource input
Port input
• N-ch open drain output
• Analog input (A/D converter)
Pch
H
Nch
Analog input
• Hysteresis input
• CMOS input
• Software pull-up resistance can be
used. Approx. 50 kΩ
R
Pch
Pull-up control resistors
I
Resource
Port
• CMOS input
• Software pull-up resistance can be
used. Approx. 50 kΩ
R
Pch
Pull-up control resistors
Port
J
17
MB89530 Series
■ HANDLING DEVICES
1. Preventing Latchup
Care must be taken to ensure that maximum voltage ratings are not exceeded (to prevent latchup) . When CMOS
integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins (other than
medium- and high-withstand voltage pins), or to voltages lower than Vss, as well as when voltages in excess of
rated levels are applied between Vcc and Vss, the phenomenon known as latchup can occur.
When a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor
elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also when switching power on or off to analog systems, care must be taken that analog power supplies (AVCC,
AVR) and analog input signals do not exceed the level of the digital power supply.
2. Power Supply Voltage Fluctuations
Keep supply voltage levels as stable as possible.
Even within the warranted operating range of the Vcc supply voltage, sudden changes in supply voltage can
cause abnormal operation. As a measure for stability, it is recommended that the Vcc ripple fluctuation (peak to
peak value) should be kept within 10% of the reference Vcc value on commercial power supply (50 Hz-60 Hz),
and instantaneous voltage fluctuations such as at power-on and shutdown should be kept within a transient
variability limit of 0.1V/ms.
3. Treatment of Unused Input Pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistance.
4. Treatment of N.C. Pins
Any pins marked ’NC’ (not connected) must be left open.
5. Treatment of Power Supply Pins on Models with Built-in A/D Converter
Even when A/D converters are not in use, pins should be connected so that AVCC = VCC, and
AVSS = AVR = VSS.
6. Precautions for Use of External Clock
Even when an external clock signal is used, an oscillator stabilization wait period is used after power-on reset,
or escape from sub clock mode or stop mode.
7. Execution of Programs on RAM
Debugging of programs executed on RAM cannot be performed even when using the MB89PV530.
8. Wild Register Functions
Wild registers cannot be debugged with the MB89PV530 and tools. To verify operations, actual in-device testing
on the MB89P538 or MB89F538L is advised.
18
MB89530 Series
9. Details on Handling C Terminal of MB89530 Series
The MB89530 series contains the following products. The regulator integrated model and the regulator-less
model have different performance characteristics.
Part No.
MB89PV530
Operation Voltage
integrated model
Not included
Included
Terminal type
Terminal treatments
Not required
N.C terminal
2.7 V to 5.5 V
Fixed to VCC
MB89P538
C terminal
Fixed to VSS
MB89537/537C
MB89538/538C
MB89F538L
2.2 V to 3.6 V
2.3 V to 3.6 V
Not included
N.C terminal
Not required
Although these product models have the same internal resources, the operation sequence after a power-on
reset is different between the regulator integrated model and regulator-less model.
The operation sequence after a power-on reset of each model is shown below.
Voltage step-down circuit stabilization time
+ oscillation stabilization time
Power supply (VCC)
(219/Fch)
CPU operation of regulator
integrated model
Oscillation stabiliza-
tion time (218/Fch)
CPU operation of regurator-less
model
CPU started on regulator
integrated model (Reset vector)
CPU started on regulator-less
model (Reset vector)
Fch : Crystal oscillator frequency
As above, the regulator integrated model starts the CPU behind the regulator-less model. This is because the
regulator requires a settling time for normal operation.
The MB89P538 offers a choice of regulator-integrated and regulator-less models selectable depending on the
C-terminal treatment. Use the right one for your mask board.
10. Note to Noise In the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunc-
tions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) .
19
MB89530 Series
■ PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F538L
1. Flash Memory
The flash memory is located between 4000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the
control of the CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
• 48 K byte×8-bit configuration : (16 K+8 K+8 K+16 K sectors)
• Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200)
• Includes an erase pause and restart function
• Data polling and toggle bit for detection of program/erase completion
• Detection of program/erase completion via CPU interrupt
• Compatible with JEDEC-standard commands
• Sector Erasing (sectors can be combined in any combination)
• No. of program/erase cycles : 10,000 (Min)
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flash memory, the program must first be copied from flash memory to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Control status register (FMCS)
Address
007AH
Initial value
000X00-0B
bit7
INTE RDYINT WE
R/W R/W R/W
bit6
bit5
bit4
RDY
R
bit3
Re-
bit2
Re-
bit1
bit0
Re-
served
served served
R/W
R/W
R/W
20
MB89530 Series
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector for both
during CPU access a flash memory programming.
• Sector configuration of flash memory
FLASH Memory
16 K bytes
8 K bytes
CPU Address
FFFFH to C000H
BFFFH to A000H
9FFFH to 8000H
7FFFH to 4000H
Programmer Address*
1FFFFH to 1C000H
1BFFFH to 1A000H
19FFFH to 18000H
17FFFH to 14000H
8 K bytes
16 K bytes
* : The programmer address is the address to be used instead of the CPU address when programming data from
a parallel flash memory programmer. Use the programmer address on programming or erasing using a general-
purpose parallel programmer.
6. ROM Programmer Adaptor and Recommended ROM Programmers
Recommended Programmer
Manufacturer and Model
Adaptor Part No.
Part number
Package
Sunhayato Corp.
Ando Electric Co., Ltd.
MB89F538L-101PF
MB89F538L-201PF
FPT-64P-M06
FPT-64P-M09
DIP-64P-M01
LCC-64P-M19
FLASH-64QF-32DP-8LF
MB89F538L-101PFM
MB89F538L-201PFM
FLASH-64QF2-32DP-8LF2
FLASH-64SD-32DP-8LF
FLASH-64BCC-32DP-8LF
AF9708*
AF9709*
MB89F538L-101P-SH
MB89F538L-201P-SH
MB89F538L-101PV4
MB89F538L-201PV4
* : For the version of the programmer, contact the Flash Support Group, Inc.
• Enquiries
Sunhayato Corp.
: TEL : +81-3-3984-7791
FAX : +81-3-3971-0535
E-mail : adapter@sunhayato.co.jp
Flash Support Group, Inc. : FAX : +81-53-428-8377
E-mail : support@j-fsg.co.jp
21
MB89530 Series
■ ONE-TIME WRITING SPECIFICATIONS WITH PROM AND EPROM MICROCONTROLLERS
The MB89P538 has a PROM mode with functions equivalent to the MBM27C1001, allowing writing with a general
purpose ROM writer using a proprietary adapter. Note, however, that the use of electronic signature mode is
not supported.
• ROM writer adapters
With some ROM writers, stability of writing performance is enhanced by placing an 0.1µF capacitor between
the Vcc and Vss pins. The following table lists adapters for use with ROM writers.
ROM Writer Adapters
Part number
Package
Compatible adapter
MB89P538-101PF
MB89P538-201PF
FPT-64P-M06
ROM-64QF-32DP-8LA2*1
MB89P538-101PFM
MB89P538-201PFM
FPT-64P-M09
DIP-64P-M01
LCC-64P-M16*2
ROM-64QF2-32DP-8LA
ROM-64SD-32DP-8LA2*1
ROM-64BCC-32DP-8LA-FJ
MB89P538-101P-SH
MB89P538-201P-SH
MB89P538-101P-PV
MB89P538-201P-PV
Inquiries should be addressed to
Sunhayato Corp. : TEL : +81-3-3984-7791
FAX : +81-3-3971-0535
E-mail : adapter@sunhayato.co.jp
*1 : Version 3 or later should be used.
*2 : Only for ES
• Memory map for EPROM mode
The following illustration shows a memory map for EPROM mode. There are no PROM options.
EPROM mode (corresponding
Normal operating mode
addresses on EPROM writer)
0000H
0080H
0000H
I/O
RAM
0100H
General
purpose
register
Prohibited
0200H
0880H
Prohibited
4000H
4000H
FFFFH
Program
(EPROM)
ROM
FFFFH
Prohibited
1FFFFH
22
MB89530 Series
• Recommended screening conditions
Before one-time writing of microcontroller programs to PROM, high temperature aging is recommended as a
screening process for chips before they are mounted.
The following diagram shows the flow of the screening process.
Program, verify
High temperature aging
+150 °C, 48 h
Read
Mount
• About writing yields
The nature of chips before one-time writing of microcontroller programs to PROM prevents the use of all-bit
writing tests. Therefore it is not possible to guarantee writing yields of 100% in some cases.
23
MB89530 Series
■ EPROM WRITING TO PIGGY-BACK/EVALUATION CHIPS
This section describes methods of writing to EPROM on piggy-back/evaluation chips.
• EPROM model
MBM27C512-20TV
• Writer adapter
For writing to EPROM using a ROM writer, use one of the writer adapters shown below (manufactured by
Sunhayato Corp.) .
Package
Adapter socket model
LCC-32 (rectangular)
ROM-32LC-28DP-YG
Inquiries should be addressed to
Sunhayato Corp. : TEL : +81-3-3984-7791
FAX : +81-3-3971-0535
E-mail : adapter@sunhayato.co.jp
• Memory Space
Piggy-back/Evaluation Memory Map
(Corresponding address on
ROM writer)
Normal operating mode
0000H
I/O
0000H
0080H
RAM
Prohibited
0880H
Prohibited
4000H
4000H
PROM
48 KB
EPROM
FFFFH
FFFFH
• Writing to EPROM
1) Set up the EPROM writer for the MBM27C512.
2) Load program data to the ERPOM writer, in the area 4000H - FFFFH.
3) Use the EPROM writer to write to the area 4000H - FFFFH.
24
MB89530 Series
■ BLOCK DIAGRAM
Sub clock
Low voltage
oscillator circuit
(32.786 kHz)
P63/INT13/X0A*2
CMOS I/O port
8
8
P00 P07
P10 P17
P64/X1A*2
Clock control
P60/INT10
P62/INT12
Watch prescaler
CMOS I/O port
4
External interrupt 1
(edge)
12-bit PPG01
12-bit PPG02
P20/PWCK
P21/PPG01
CMOS I/O port
Oscillator circuit
Clock controller
Main clock
P22/PPG02
P23 P27
X0
X1
CMOS I/O port
P40/INT20/EC
Reset circuit
(watchdog timer)
SIO
UART
I2C
RST
P41/INT21/SCK2
P42/INT22/
SO2/SDA
21-bit time
base timer
P43/INT23/
SI2/SCL
16-bit timer/
counter 1
P30/PPG03/MCO
6-bit PPF03
P44/INT24/UCK2
8-bit
PWM timer 2
P31/SCK1 (UCK1)
/LMCO
P45/INT25/UO2
P46/INT26/UI2
External interrupt 2
(level)
P32/SO1 (UO1)
P33/SI1 (UI1)
8-bit
PWM timer 1
P47/INT27/ADST*1
P34/PTO2
P35/PWC
P36/WTO
P37/PTO1
CMOS I/O port
UART/SIO
PWC
N-ch output
8
P50/AN0
P57/AN7
CMOS I/O port
8
1KB RAM/2KB RAM
10-bit
A/D converter
AVCC
AVR
F2MC-8L
CPU
AVSS
Wild register
32KB ROM/48KB ROM
Other pins
MOD0, MOD1, MOD2*1, C, VCC, VSS, C/NC
*1 : P47/INT27/ADST pins except for MB89F538L, MOD2 pin for MB89F538L
*2 : P63/INT13, P64 pins for single-clock, X0A, X1A pins for dual-clock
25
MB89530 Series
■ CPU CORE
1. Memory Space
The MBM89530 series has 64 KB of memory space, containing all I/O, data areas, and program areas. The I/
O area is located at the lowest addresses, with the data area placed immediately above. The data area can be
partitioned into register areas, stack areas, or direct access areas depending on the application. The program
area is located at the opposite end of memory, closest to the highest addresses, and the highest part of this
area is assigned to the tables of interrupt and reset vectors and vector call instructions. The following diagram
shows the structure of memory space in the MB89530 series.
• Memory Map
MB89PV530
MB89P538/F538L
MB89537/537C
MB89538/538C
0000H
0080H
0000H
0080H
I/O
I/O
RAM
RAM
0100H
0200H
0100H
0200H
General
purpose register
General
purpose register
0480H
0880H
0C80H
0C91H
Open
Open
0C80H
0C91H
Wild register
Wild register
Open
Open
4000H
8000H
ROM
External ROM*1
ROM
FFC0H
FFFFH
FFC0H
FFFFH
Vector tables*2
Vector tables*2
*1 : The external ROM area is on the MBM89PV530 only.
*2 : Vector tables (reset, interrupt, vector call instructions)
26
MB89530 Series
2. Registers
The F2MC-8L series has two types of registers, dedicated-use registers within the CPU, and general-purpose
registers in memory.
The dedicated-use registers are the following.
Program counter (PC)
: 16-bit length, shows the location where instructions are stored.
Accumulator (A)
: 16-bit length, a temporary memory register for calculation operations.
The lower byte is used for 8-bit data processing instructions.
Temporary accumulator (T) : 16-bit length, performs calculations with the accumulator.
The lower byte is used for 8-bit data processing instructions.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: 16-bit length, a register for index modification.
: 16-bit length, a pointer indicating memory addresses.
: 16-bit length, indicates stack areas.
: 16-bit length, contains register pointer and condition code.
16 bits
Initial value
PC
A
: Program counter
: Accumulator
FFFDH
Not fixed
: Temporary accumulator
: Index register
Not fixed
Not fixed
Not fixed
Not fixed
T
IX
: Extra pointer
EP
SP
PS
: Stack pointer
: Program status
I-flag = 0, IL1, 0 = 11
Other bits not fixed
In addition, the PS register can be divided so that the upper 8 bits are used as a register bank pointer (RP), and
the lower 8 bits as a condition code register (CCR). (See the following illustration.)
• Program status register configuration
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
Open
RP
H
IL1 IL0
N
PS
C
Open Open
V
RP
CCR
27
MB89530 Series
The RP register shows the address of the register bank currently being used, so that the RP value and the actual
address are related by the conversion rule shown in the following illustration.
• General purpose register area real address conversion principle
Operation code
RP upper
lower
"0" "0" "0" "0" "0" "0" "0" "1"
R4 R3 R2 R1 R0 b2
b1
b0
Address
generated
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR register has bits that show the content of results of calculations and transferred data, and bits that
control CPU operation during interrupts.
H-flag : Set to 1 if calculations result in carry or borrow operations from bit 3 to bit 4, otherwise set to 0.
This flag is used for decimal correction instructions.
I-flag
: This flag is set to 1 if interrupts are enabled, and 0 if interrupts are prohibited.
The default value at reset is 0.
IL1, 0 : Indicates the level of the currently permitted interrupts.
Only interrupt requests having a more powerful level than the value of these bits will be processed.
IL1
0
IL0
0
Interrupt level
Strength
Strong
1
0
1
1
0
2
3
Weak
1
1
N-flag : Set to 1 if the highest bit is 1 after a calculation, otherwise cleared to 0.
Z-flag : Set to 1 if a calculation result is 0, otherwise cleared to 0.
V-flag : Set to 1 if a two’s complement overflow results during a calculation, otherwise cleared to 0.
C-flag : Set to 1 if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to 0.
This is also the shift-out value in a shift instruction.
In addition, the following general purpose registers are available.
General purpose registers: 8-bit length, used to contain data.
The general purpose registers are 8-bit registers located in memory. There are eight such registers per bank,
and the MB89530 series have up to 32 banks for use. The bank currently in use is indicated by the register bank
pointer (RP).
28
MB89530 Series
•Register bank configuration
Address at this location
= 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
29
MB89530 Series
■ I/O MAP
Register
Address
Register description
Port 0 data register
Write/Read
Initial value
name
00H
01H
PDR0
DDR0
PDR1
DDR1
R/W
W
XXXXXXXXB
0 0 00 0 0 0 0B
XXXXXXXXB
0 0 00 0 0 0 0B
Port 0 direction register
Port 1 data register
02H
R/W
W
03H
Port 1 direction register
04H to 06H
07H
(Reserved area)
SYCC
STBC
WDTC
TBTC
WPCR
PDR2
DDR2
PDR3
DDR3
PDR4
DDR4
PDR5
PDR6
System clock control register
Standby control register
Watchdog control register
Time base timer control register
Watch prescaler control register
Port 2 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
X-1 MM10 0B
0 0 0 1 0 -- -B
0 -- -XXXXB
0 0 - -- 00 0B
0 0 - - 0 00 0B
XXXXXXXXB
0 0 00 0 0 0 0B
XXXXXXXXB
0 0 00 0 0 0 0B
XXXX 11 XXB
0 0 0 0 -- 00B
1 1 1 11 1 1 1 B
XXXXXXXXB
08H
09H
0AH
0BH
0CH
0DH
Port 2 direction register
Port 3 data register
0EH
0FH
Port 3 direction register
Port 4 data register
10H
11H
Port 4 direction register
Port 5 data register
12H
13H
Port 6 data register
14H to 21H
22H
(Reserved area)
SMC11
SRC1
SSD1
Serial mode control register 1 (UART)
Serial route control register (UART)
Serial status and data register (UART)
R/W
R/W
R/W
0 0 00 0 0 0 0B
- -0 1 1 0 00B
0 0 1 0 0 -1XB
23H
24H
SIDR1/
SODR1
25H
Serial input/output data register (UART)
R/W
XXXXXXXXB
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
SMC12
CNTR1
CNTR2
CNTR3
COMR1
COMR2
PCR1
Serial mode control register 2 (UART)
PWM control register 1
R/W
R/W
R/W
R/W
W
- -1 0 0 0 01B
00 00 0 0 0 0B
00 0 -0 0 0 0B
-0 0 0 -- --B
PWM control register 2
PWM control register 3
PWM compare register 1
XXXXXXXXB
XXXXXXXXB
00 0 -- 0 00B
00 00 0 0 0 0B
XXXXXXXXB
0 0 00 0 0 0 0B
0 0 00 0 0 0 0B
0 0 0 0 1 -- -B
PWM compare register 2
W
PWC pulse width control register 1
PWC pulse width control register 2
PWC reload buffer register
R/W
R/W
R/W
R/W
R/W
R/W
PCR2
RLBR
SMC21
SMC22
SSD2
Serial mode control register 1 (UART/SIO)
Serial mode control register 2 (UART/SIO)
Serial status and data register (UART/SIO)
SIDR2/
SODR2
32H
Serial data register (UART/SIO)
R/W
XXXXXXXXB
(Continued)
30
MB89530 Series
Register
name
Address
Register description
Write/Read
Initial value
33H
34H
SRC2
ADC1
ADC2
ADDL
ADDH
PPGC2
PRL22
PRL21
PRL23
TMCR
TCHR
TCLR
EIC1
Baud rate generator reload register
A/D control register 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
00 00 0 0 -0B
- 00 0 0 0 01B
XXXXXXXXB
-- -- -- 0 0B
35H
A/D control register 2
36H
A/D data register low
37H
A/D data register high
38H
PPG2 control register (12-bit PPG)
PPG2 reload register 2 (12-bit PPG)
PPG2 reload register 1 (12-bit PPG)
PPG2 reload register 3 (12-bit PPG)
16-bit timer control register
000 0 0 0 0 0B
0X00 0 0 00B
XX0 0 00 0 0B
XX0 0 00 0 0B
- -0 0 0 00 0B
000 0 0 0 0 0B
000 0 0 0 0 0B
0 00 0 0 0 0 0B
0 00 0 0 0 0 0B
39H
3AH
3BH
3CH
3DH
3EH
16-bit timer counter register high
16-bit timer counter register low
External interrupt 1 control register 1
External interrupt 1 control register 2
3FH
40H
EIC2
41H to 48H
49H
(Reserved area)
DDCR
DDC select register
R/W
-- -- -- - 0B
4AH to 4BH
4CH
4DH
4EH
(Reserved area)
PPGC1
PRL12
PRL11
PRL13
IACR
IBSR
PPG1 control register (12-bit PPG)
PPG1 reload register 2 (12-bit PPG)
PPG1 reload register 1 (12-bit PPG)
PPG1 reload register 3 (12-bit PPG)
I2C address control register
I2C bus status register
R/W
R/W
R/W
R/W
R/W
R
000 0 0 0 0 0B
0X00 0 0 00B
XX0 0 00 0 0B
XX0 0 00 0 0B
-- -- -0 0 0B
4FH
50H
51H
0 00 0 0 0 0 0B
0 00 0 0 0 0 0B
00 0 XXXXXB
- XXXXXXXB
XXXXXXXXB
000 0 0 0 0 0B
-- -- -- - 0B
52H
IBCR
ICCR
IADR
IDAR
EIE2
I2C bus control register
I2C clock control register
I2C address register
I2C data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
53H
54H
55H
56H
External interrupt 2 control register
External interrupt 2 flag register
6-bit PPG control register 1
6-bit PPG control register 2
Clock output control register
57H
EIF2
58H
RCR1
RCR2
CKR
000 0 0 0 0 0B
0X00 0 0 00B
-- -- -- 0 0B
59H
5AH
5BH to 6FH
70H
(Reserved area)
SMR
SDR
Serial mode register (SIO)
R/W
R/W
R/W
R/W
R/W
R/W
0 00 0 0 0 0 0B
XXXXXXXXB
1 1 1 11 1 1 1 B
1 1 1 11 1 1 1 B
1 1 1 11 1 1 1 B
1 1 1 11 1 1 1 B
(Continued)
71H
Serial data register (SIO)
72H
PURR0
PURR1
PURR2
PURR3
Port 0 pull-up resistance register
Port 1 pull-up resistance register
Port 2 pull-up resistance register
Port 3 pull-up resistance register
73H
74H
75H
31
MB89530 Series
(Continued)
Register
name
Address
Register description
Write/Read
Initial value
76H
77H
PURR4
WREN
Port 4 pull-up resistance register
Wild register enable register
Wild register data test register
Port 6 pull-up resistance register
FLASH control status register
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt test register
R/W
R/W
R/W
R/W
R/W
W
11 11 - -1 1B
- -0 0 00 0 0B
- -0 0 00 0 0B
- -- 1 1 11 1 B
000X00 - 0 B
1 11 1 1 1 11B
1 11 1 1 1 11B
1 11 1 1 1 11B
1 11 1 1 1 11B
78H
WROR
79H
PURR6
FMCS
7AH
7BH
ILR1
7CH
ILR2
W
7DH
ILR3
W
7EH
ILR4
W
7FH
ITR
Access prohibited XXXXXX0 0B
C80H
C81H
C82H
C83H
C84H
C85H
C86H
C87H
C88H
C89H
C8AH
C8BH
C8CH
C8DH
C8EH
C8FH
C90H
C91H
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
WRARH3
WRARL3
WRDR3
WRARH4
WRARL4
WRDR4
WRARH5
WRARL5
WRDR5
WRARH6
WRARL6
WRDR6
Upper address setting register 1
Lower address setting register 1
Data setting register 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Upper address setting register 2
Lower address setting register 2
Data setting register 2
Upper address setting register 3
Lower address setting register 3
Data setting register 3
Upper address setting register 4
Lower address setting register 4
Data setting register 4
Upper address setting register 5
Lower address setting register 5
Data setting register 5
Upper address setting register 6
Lower address setting register 6
Data setting register 6
• Description of write/read symbols :
R/W : read/write enabled
R
: Read only
: Write only
W
• Description of initial values :
0
: This bit initialized to “0”.
1
: This bit initialized to “1”.
X
M
-
: The initial value of this bit is not determined.
: The initial value of this bit is a mask option.
: This bit is not used.
Note : Do not use reserved spaces.
32
MB89530 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVss = Vss = 0 V)
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
MB89537/538
MB89537C/538C
MB89F538L
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS + 4.0
VSS + 4.0
VSS + 6.0
V
V
V
*1
*1
AVR
Supply voltage
VCC
AVCC
MB89P538
MB89PV530
AVR
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
− 2.0
VSS + 6.0
VCC + 0.3
VSS + 6.0
VCC + 0.3
VSS + 6.0
+ 2.0
V
V
V
V
V
Other than P42, P43
Only P42, P43
Input voltage
VI
Other than P42, P43
Only P42, P43
Output voltage
VO
Maximum clamp current
ICLAMP
mA *2
mA *2
Total maximum clamp current ∑| ICLAMP |
20
“L” level maximum output
current
IOL
15
4
mA
“L” level average output
current
Average value
(operating current × operating duty)
IOLAV
mA
mA
mA
mA
mA
mA
mA
“L” level maximum total
ΣIOL
100
40
output current
“L” level average total output
current
Average value
(operating current × operating duty)
ΣIOLAV
“H” level maximum output
current
IOH
−15
−4
“H” level average output
current
Average value
(operating current × operating duty)
IOHAV
“H” level maximum total
ΣIOH
−50
−20
output current
“H” level average total output
current
Average value
(operating current × operating duty)
ΣIOHAV
Current consumption
Operating temperature
Storage temperature
PD
TA
300
+85
mW
°C
−40
−55
Tstg
+150
°C
*1 : AVcc and Vcc are to be used at the same potential. AVR should not exceed AVcc + 0.3 V.
*2 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40, P41, P44 to P47, P50 to P57,
P60 to P64
• Use within recommended operating conditions.
• Use at DC voltage (current) .
(Continued)
33
MB89530 Series
(Continued)
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
VCC
Limiting
P-ch
resistance
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
34
MB89530 Series
2. Recommended Operating Conditions
(AVss = Vss = 0 V)
Value
Parameter
Symbol
Unit
Remarks
Min
Max
Range warranted for
normal operation
2.2*
3.6
V
V
V
V
V
V
MB89537/538
MB89537C/
538C
RAM status in stop
mode
1.5
2.4
1.5
2.7*
1.5
3.6
3.6
3.6
5.5
5.5
Range warranted for
normal operation
VCC,
MB89F538L
AVCC
Supply voltage
RAM status in stop
mode
Range warranted for
normal operation
MB89P538
MB89PV530
RAM status in stop
mode
AVR
TA
2.4
AVCC
V
Operating temperature
−40
+85
°C
* : Varies according to frequency used, and instruction cycle.
See “Operating voltage vs. operating frequency (MB89537/MB89538/MB89537C/MB89538C) and (MB89P538/
MB89PV530) ” and “5. A/D Converter Electrical Characteristics”.
Operating voltage vs. operating frequency (MB89537/MB89538/MB89537C/MB89538C)
Range of warranted analog precision : VCC = AVCC = 2.4 V to 3.6 V
4.0
3.6
3.0
2.4
2.2
2.0
1.0
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
(at instruction cycle = 4 / Fc)
4.0 2.0
0.8
0.4
0.32
Minimum instruction execution time (Instruction cycles) (µs)
35
MB89530 Series
Operating voltage vs. operating frequency (MB89F538L)
Range of warranted analog precision : VCC = AVCC = 2.4 V to 3.6 V
4.0
3.6
3.0
2.4
2.0
1.0
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
(at instruction cycle = 4 / Fc)
4.0 2.0
0.8
0.4
0.32
Minimum instruction execution time (Instruction cycles) (µs)
36
MB89530 Series
Operating voltage vs. operating frequency (MB89P538/MB89PV530)
Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V
5.5
5.0
4.0
3.5
3.0
2.7
2.2
2.0
1.0
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
12.5
Operating frequency (MHz)
(at instruction cycle = 4 / Fc)
4.0 2.0
0.8
0.4
0.32
Minimum instruction execution time (Instruction cycles) (µs)
indicates warranted operation at TA = −10 °C to +55 °C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
37
MB89530 Series
3. DC Characteristics
(AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Condition
Parameter
Pin name
Unit
Remarks
Min
Typ
Max
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
VIH
0.7 VCC
VCC + 0.3
V
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
“H” level
input voltage
VIHS
0.8 VCC
VCC + 0.3
V
With SMB input
buffer selected*
With I2C input
VIHSMB
VSS + 1.4
VSS + 5.5
VSS + 5.5
V
V
SCL, SDA
VIHI2C
0.7 VCC
buffer selected*
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
VIL
VSS − 0.3
0.3 VCC
0.2 VCC
V
V
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
“L” level
input voltage
VILS
VSS − 0.3
With SMB input
buffer selected*
With I2C input
VILSMB
VILI2C
VSS − 0.3
VSS − 0.3
VSS + 0.6
V
V
SCL, SDA
0.3 VCC
buffer selected*
Open drain
outputapplied
voltage
VD1
VD2
P50 to P57
P42, P43
VCC + 0.3
VSS + 5.5
V
V
VSS − 0.3
P00 to P07, P10 to P17,
P20 to P24, P30 to P37,
P40, P41, P44 to P47
IOH =
−2.0 mA
“H” level
output voltage
VOH
2.4
V
V
IOH =
−3.0 mA
P25 to P27
P00 to P07, P10 to P17,
“L” level
output
voltage
P20 to P27, P30 to P37, IOL =
P40 to P47, P50 to P57, 4.0 mA
RST
VOL
0.4
Input leak
current
(Hi-Z output
leak current)
P00 to P07, P10 to P17,
P20 to P27, P30 to P37, 0.0V<VI
P40 to P47, P50 to P57, < VCC
P60 to P64
With no pull-up
µA resistance
ILI
−5
+5
specified
(Continued)
38
MB89530 Series
(Continued)
(AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Condition
Parameter
Pin name
Unit
Remarks
Min
Typ
Max
Open drain
output leak
current
0.0 V < VI < VSS
+ 5.5 V
ILIOD
P42, P43
+5
µA
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37, P40,
P41, P44 to P47,
P60 to P64, RST
With pull-up resis-
tance is selected.
The RST signal is
excluded.
Pull-up
resistance
RPULL
VI = 0.0 V
25
50
6
100
kΩ
10
45
mA Normal operation
FCH = 10.0 MHz
tinst = 0.4 µs
FLASH memory
mA programming/erase
MB89F538L
ICC1
FCH = 10.0 MHz
tinst = 6.4 µs
ICC2
ICCS1
ICCS2
1.5
2
3
4
mA
FCH = 10.0 MHz
tinst = 0.4 µs
mA Sleep mode
mA Sleep mode
FCH = 10.0 MHz
tinst = 6.4 µs
1
2
Sub mode
mA
FCL = 32.768 kHz
1
3
MB89P538/PV530
FCL = 32.768 kHz
TA = +25 °C
Sub mode
µA
35
90
ICCL
MB89F538L
Sub mode
µA MB89537/538
MB89537C/538C
VCC
FCL = 32.768 kHz
FCL = 32.768 kHz
20
15
15
50
30
30
Supply
current
Sub, sleep modes
µA Except
MB89F538L
ICCLS
Watch mode, main
µA stop
FCL = 32.768 kHz
TA = +25 °C
MB89F538L
Watch mode, main
stop
Except
FCL = 32.768 kHz
5
15
µA
ICCT
MB89F538L
FCL = 32.768 kHz
TA = +25 °C
Sub, sleep modes
MB89F538L
5
1
1
1
5
15
5
µA
ICCH
IA
TA = +25 °C
FCH = 10.0 MHz
TA = +25 °C
f = 1 MHz
µA Sub, stop modes
A/D conversion
running
3
mA
AVCC
IAH
CIN
5
µA A/D stopped
Input
capacitance
Except VCC, VSS,
AVCC, AVSS
15
pF
* : The MB89PV530/P538/F538L/537C/538C have a built-in I2C function, and a choice of input buffers by software
setting. The MB89537/538 have no built-in I2C functions, and therefore this standard does not apply.
39
MB89530 Series
4. AC Characteristics
(1) Reset Timing
(VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min
Max
RST “L” pulse width
tZLZH
48 tHCYL
ns
Notes : • tHCYL is the main clock oscillator period.
• If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause
malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external
reset pin (RST) .
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
Parameter
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Condition
Unit
Remarks
Min
Max
50
Power on time
tR
0.5
ms
ms
For repeated
operation
Power shutoff time
tOFF
1
Note : Be sure that the power supply will come on within the selected oscillator stabilization period. Also, when
varyingthesupplyvoltageduringoperation, itisrecommendedthatthesupplyvoltagebeincreasedgradually.
tR
tOFF
2.2 V
VCC
0.2 V
0.2 V
0.2 V
40
MB89530 Series
(3) Clock Timing Standards
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Condition
Parameter
Clock frequency
Clock cycle time
Symbol Pin name
Unit
Remarks
Min
Typ
32.768
30.5
Max
FCH
FCL
X0, X1
X0A, X1A
X0, X1
1
12.5
MHz Main clock
kHz Sub clock
ns Main clock
µs Sub clock
tHCYL
tLCYL
80
20
1000
X0A, X1A
PWH
PWL
X0
X0A
X0
ns External clock
µs External clock
ns External clock
Input clock pulse width
Input clock rise, fall time
PWHH
PWLL
15.2
tCR
tCF
10
• X0, X1 timing and application conditions
tHCYL
PWH
PWL
tCR
tCF
0.8 VCC
0.2 VCC
0.8 VCC
X0
0.2 VCC
0.2 VCC
• Clock application conditions
Using a crystal oscillator
or
Using an external clock
signal
ceramic oscillator
X0
X1
X0
X1
Open
FCH
C2
FCH
C1
41
MB89530 Series
• X0A, X1A timing and application conditions
tLCYL
PWLH
PWLL
tCR
tCF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Clock application conditions
Using a crystal oscillator
or
Using an external clock
signal
ceramic oscillator
X0A
X1A
X0A
X1A
Open
FCL
C2
FCL
C1
(4) Instruction Cycle
Parameter
(AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Rated value
Unit
Remarks
Operating at FCH = 12.5 MHz
(4/FCH)
tinst = 0.32 µs
4/FCH, 8/FCH, 16/FCH, 64/FCH
2/FCL
µs
Instruction cycle (minimum
instruction execution time)
tinst
Operating at FCL = 32.768 kHz
tinst = 61.036 µs
µs
42
MB89530 Series
(5) Serial I/O Timing
Parameter
(VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min
2 tinst
−200
200
200
1 tinst
1 tinst
0
Max
Serial clock cycle time
SCK↓→SO
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
SCK, UCK
µs
ns
ns
ns
µs
µs
ns
ns
ns
Internal
clock
operation
SCK, SO, UCK, UO
SI, SCK, UI, UCK
SCK, SI, UCK, UI
+200
Valid SI→SCK↑
SCK↑→ valid SI hold time
Serial clock “H” pulse width
ÉSerial clock “L” pulse width
SCK↓→SO time
SCK, UCK
External
clock
operation
SCK, SO, UCK, UO
SI, SCK, UI, UCK
SCK, SI, UCK, UI
200
Valid SI→SCK↑
200
200
SCK↑→ valid SI hold time
Note : For tinst see “ (4) Instruction Cycle”.
Internal shift clock mode
tSCYC
SCK
UCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SO
UO
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
SI
UI
0.2 VCC
External shift clock mode
tSLSH
tSHSL
SCK
UCK
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
0.2 VCC
2.4 V
0.8 V
SO
UO
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SI
UI
43
MB89530 Series
(6) Peripheral Input Timing
(VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit
Remarks
Min
Max
Peripheral input “H”
level pulse width 1
tILIH1
tIHIL1
tILIH2
tIHIL2
2 tinst
µs
µs
µs
µs
INT10 to INT13,
INT20 to INT27,
EC, PWC, PWCK
Peripheral input “L”
level pulse width 1
2 tinst
28 tinst
28 tinst
Peripheral input “H”
level pulse width 2
ADST
Peripheral input “L”
level pulse width 2
Note : For tinst see “ (4) Instruction Cycle”.
tIHIL1
tILIH1
EC, INT, PWC, PWCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tIHIL2
tILIH2
ADST
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
44
MB89530 Series
(7) I2C Timing
(VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Value
Pin
name
Symbol
Condition
Parameter
Unit Remarks
Min
Max
SCL
SDA
1 / 4 tinst ×
m × n − 20
1 / 4 tinst ×
m × n + 20
Start condition output
Stop condition output
Start condition detection
Stop condition detection
Restart condition output
Restart condition detection
SCL output “L” width
tSTA
tSTO
ns Master only
ns Master only
ns
SCL
SDA
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
1 / 4 tinst ×
SCL
SDA
tSTA
1 / 4 tinst × 6 + 40
SCL
SDA
tSTO
1 / 4 tinst × 6 + 40
ns
SCL
SDA
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
1 / 4 tinst ×
tSTASU
tSTASU
tLOW
ns Master only
ns
SCL
SDA
1 / 4 tinst × 4 + 40
1 / 4 tinst ×
m × n − 20
1 / 4 tinst ×
m × n + 20
SCL
ns Master only
ns Master only
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
1 / 4 tinst ×
SCL output “H” width
SDA output delay time
tHIGH
tDO
SCL
SDA
SDA
1 / 4 tinst × 4 − 20 1 / 4 tinst × 4 + 20 ns
Setup after SDA output
interrupt interval
tDOSU
1 / 4 tinst × 4 − 20
ns
SCL input “L” width
SCL input “H” width
SDA input setup
tLOW
tHIGH
tSU
SCL
SCL
SDA
SDA
1 / 4 tinst × 6 + 40
ns
ns
ns
ns
1 / 4 tinst × 2 + 40
40
0
SDA input hold
tHO
Notes : • For tinst see “ (4) Instruction Cycle”.
• The value “m” in the above table is the value from the shift clock frequency setting bits (CS4-CS3) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• The value ’n’ in the above table is the value from the shift clock frequency setting bits (CS2-CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSU appears when the interrupt period is longer than the SCL “L” width.
• The rated values for SDA and SCL assume a start up time of 0 ns.
45
MB89530 Series
• I2C interface [Data sending (master/slave) ]
tDO
tSU
tSU
tDOSU
tDO
SDA
ACK
tSTASU
tSTA
tLOW
tHO
1
SCL
9
• I2C interface [Data sending (master/slave) ]
tSU
tHO
tDO
tDO
tDOSU
tSTO
SDA
SCL
ACK
tHIGH
tLOW
6
7
8
9
46
MB89530 Series
5. A/D Converter Electrical Characteristics
(1) MB89537/538/537C/538C
(VCC = 2.4 V to 3.6 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Parameter
Pin name Condition
Unit Remarks
Min
Typ
Max
10
Resolution capability
Total error
bit
±3.0
±2.5
±1.9
LSB
LSB
Linear error
Differential linear error
LSB
AVCC = VCC
AVSS −1.5 AVSS +0.5 AVSS +2.5
AVR = AVCC
Zero transition voltage
VOT
mV
LSB
LSB
LSB
Full scale transition
voltage
AVR − 3.5 AVR− 1.5 AVR+ 1.5
VFST
mV
LSB
LSB
LSB
4.0
Inter-channel variation
Conversion time
LSB
60 tinst
16 tinst
µs
µs
µA
V
*
Sampling time
Analog input current
Analog input voltage
Reference voltage
IAIN
10
AN0 to
AN7
VAIN
AVSS
AVR
AVCC
AVSS + 2.4
V
AVR
IR
A/D running
A/D off
200
µA
µA
Reference voltage
supply current
IRH
5
* : Includes sampling time
(2) MB89F538L
(VCC = 2.4 V to 3.6 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Parameter
Pin name Condition
Unit Remarks
Min
Typ
Max
10
Resolution capability
Total error
bit
±3.0
±2.5
±1.9
LSB
LSB
Linear error
Differential linear error
LSB
AVCC = VCC
AVSS −1.5 AVSS +0.5 AVSS +2.5
AVR = AVCC
Zero transition voltage
VOT
mV
LSB
LSB
LSB
Full scale transition
voltage
AVR − 3.5 AVR− 1.5 AVR+ 1.5
VFST
mV
LSB
LSB
LSB
4.0
Inter-channel variation
Conversion time
LSB
60 tinst
16 tinst
µs
µs
µA
V
*
Sampling time
Analog input current
Analog input voltage
Reference voltage
IAIN
10
AN0 to
AN7
VAIN
0
AVR
AVCC
AVSS + 2.4
V
AVR
IR
A/D running
A/D off
200
µA
µA
Reference voltage
supply current
IRH
5
* : Includes sampling time
47
MB89530 Series
(3) MB89P538/PV530
(VCC = 2.4 V to 3.6 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
Value
Symbol
Parameter
Pin name Condition
Unit Remarks
Min
Typ
Max
10
Resolution capability
Total error
bit
±3.0
±2.5
±1.9
LSB
LSB
Linear error
Differential linear error
LSB
AVCC = VCC
AVSS −1.5 AVSS +0.5 AVSS +2.5
AVR = AVCC
Zero transition voltage
VOT
mV
LSB
LSB
LSB
Full scale transition
voltage
AVR− 3.5 AVR− 1.5 AVR + 1.5
VFST
mV
LSB
LSB
LSB
4.0
Inter-channel variation
Conversion time
LSB
60 tinst
16 tinst
µs
µs
µA
V
*
Sampling time
Analog input current
Analog input voltage
Reference voltage
IAIN
10
AN0 to
AN7
VAIN
0
AVR
AVCC
AVSS + 3.5
V
AVR
IR
A/D running
A/D off
400
µA
µA
Reference voltage
supply current
IRH
5
* : Includes sampling time
48
MB89530 Series
(4) A/D Converter Terms and Definitions
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
• Linear error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000”←→“00
0000 0001”) of a device and the full-scale transition point (“11 1111 1110”←→“11 1111 1111”) , compared with
the actual conversion values obtained.
• Differential linear error (Unit : LSB)
The deviation from the theoretical input voltage required to produce a change of 1 LSB in output code.
• Total error (Unit : LSB)
The difference between theoretical conversion value and actual conversion value.
Theoretical input/output
Total error
characteristics
VFST
3FF
3FE
3FD
3FF
3FE
3FD
Actual conversion
characteristics
1.5 LSB
(1 LSB I N +
0.5 LSB)
004
003
002
001
004
003
002
001
VNT
Actual
VOT
conversion
characteristics
1 LSB
Theoretical
characteristics
0.5 LSB
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VNT − {1 LSB × N + 0.5 LSB}
VFST − VOT
Total error in digital output N =
1 LSB =
(V)
1 LSB
1022
(Continued)
49
MB89530 Series
(Continued)
Zero transition error
Full-scale transition error
Theoretical characteristics
004
003
002
001
Actual
conversion
characteristics
Actual
conversion
characteristics
3FF
3FE
3FD
3FC
VFST (actual
measurement
value)
Actual
conversion
characteristics
Actual conversion
characteristics
VOT (actual
measurement value)
AVSS
AVR
Analog input
Analog input
Linear error
Differential linear error
Actual conversion
characteristics
3FF
3FE
3FD
Theoretical characteristics
Actual
N + 1
(1 LSB × N + VOT)
conversion
V (N + 1) T
characteristics
VFST
(actual
measure-
ment
N
VNT
004
003
002
001
value)
N − 1
N − 2
Actual conversion
characteristics
VNT
Actual conversion
characteristics
Theoretical
characteristics
VOT (actual measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
VNT − {1 LSB × N + VOT}
1 LSB
V (N + 1) T − VNT
=
Analog input linear
error in digital out-
put N
=
Differential linear
error in digital
output N
−1
1 LSB
50
MB89530 Series
(5) Precautionary Information
• Input Impedance of Analog Input Pins
The A/D converter has a sample & hold circuit as shown below, which uses a sample-and-hold capacitor to
obtain the voltage at the analog input pin for 8 instruction cycles following the start of A/D conversion. For this
reason if the external circuits providing the analog input signal have high output impedance, the analog input
voltage may not stabilize within the analog input sampling time. It is therefore recommended that the output
impedance of external circuits be reduced to 10 kΩ or less.
• MB89537/537C/538/538C/F538L Analog Input Equivalent Circuit
Sample-and-hold circuit
C = 49 pF
Analog input pin
Compara-
tor
If analog input impedance is 10 kΩ
or more, the use of a capacitor of
approximately 0.1 µF is recom-
mended.
R = 7.1 kΩ
Closes 8 instruction cycles
after the start of A/D conversion
Analog channel selector
• MB89P538 and MB89PV530 Analog Input Equivalent Circuit
Analog input pin
Sample-and-hold circuit
C = 64 pF
Compar-
ator
R = 3 kΩ
If analog input impedance is 10 kΩ
or more, the use of a capacitor of
approximately 0.1 µF is recom-
mended.
Closes 8 instruction cycles after
the start of A/D conversion
Analog channel selector
• About error
The smaller the absolute value |AVR - AVss| is, the greater the relative error becomes.
51
MB89530 Series
6. Flash Memory
• Flash memory programming/erase characteristics
Value
Typ
Parameter
Conditions
Unit Remarks
Min
Max
Per 1 sector,
Sector erase Constant value inde-
1
15
s
*
*
time
pendent with sector ca-
pacitance
TA = +25 °C,
VCC = 3.3 V
Program-
ming time
Per 1 byte
8
5
3600
µs
Chip erase time
s
Program/Erase cycle
10,000
cycle
* : Excludes internal programming time before erase.
52
MB89530 Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current (External Clock)
MB89538 ICCS1 vs. VCC
MB89538 ICC1 vs. VCC
7
2.5
2
12.5 MHz
10 MHz
(T
A
= 25 ˚C)
(TA = 25 ˚C)
12.5 MHz
10 MHz
8 MHz
6
5
4
3
2
1
0
8 MHz
5 MHz
1.5
1
5 MHz
0.5
0
2 MHz
1 MHz
2 MHz
1 MHz
1
2
3
4
5
1
2
3
4
5
V
CC (V)
V
CC (V)
(2) “H” Level Input Voltage/ “L” Level Input Voltage (CMOS Input)
MB89538 VIN vs. VCC
4
(TA = 25 ˚C)
3
2
1
0
2
2.5
3
3.5
4
VCC (V)
(3) “H” Level Input Voltage / ”L” Level Input Voltage (Hysteresis Input)
MB89538 VIN vs. VCC
3
(TA = 25 ˚C)
VIH
2
VIL
1
0
2
2.5
3
3.5
4
VCC (V)
53
MB89530 Series
(4) AD Converter Characteristic Example
MB89538 Linearity Error
3
2.5
(VCC = AVR = 3 V, Fc = 10 MHz)
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
0
128
256
384
512
640
768
896
1024
Conversion characteristic
MB89538 Differential linearity error
2.5
2
1.5
1
(VCC = AVR = 3 V, Fc = 10 MHz)
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
128
256
384
512
640
768
896
1024
Conversion characteristic
MB89538 Total Error
4
3
(VCC = AVR = 3 V, Fc = 10 MHz)
2
1
0
-1
-2
-3
-4
0
128
256
384
512
640
768
896
1024
Conversion characteristic
54
MB89530 Series
■ MASK OPTIONS
MB89537
MB89537C
MB89538
MB89F538L-101 MB89P538-101 MB89PV530-101
MB89F538L-201 MB89P538-201 MB89PV530-201
Part number
No
MB89538C
Specify at time of
mask order
Setting not
possible
Setting not
possible
Setting not
possible
Method of specification
Main clock
Select oscillator
stabilization wait period
(FCH * = 10 MHz)
approx.214/FCH *
218/FCH *
218/FCH *
218/FCH *
1
Selection available
Selection available
(approx.1.6 ms)
(approx. 26.2ms) (approx. 26.2ms) (approx. 26.2ms)
approx.217/FCH *
(approx.13.1 ms)
approx.218/FCH *
(approx.26.2 ms)
Clock mode selection
• 2-system clock mode
• 1-system clock mode
• 101 : 1-system clock mode
• 201 : 2-system clock mode
2
* : FCH : Main clock frequency
55
MB89530 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89537P
MB89537CP
MB89538P
MB89538CP
MB89537P and MB89538P do not
have I2C functions.
DIP-64P-M01
MB89F538L-101P
MB89F538L-201P
MB89P538-101P
MB89P538-201P
MB89537PF
MB89537CPF
MB89538PF
MB89538CPF
MB89537PF and MB89538PF do not
have I2C functions.
FPT-64P-M06
MB89F538L-101PF
MB89F538L-201PF
MB89P538-101PF
MB89P538-201PF
MB89537PFM
MB89537CPFM
MB89538PFM
MB89538CPFM
MB89537PFM and MB89538PFM do
not have I2C functions.
FPT-64P-M09
FPT-64P-M03
MB89F538L-101PFM
MB89F538L-201PFM
MB89P538-101PFM
MB89P538-201PFM
MB89537PFV
MB89537CPFV
MB89538PFV
MB89538CPFV
MB89537PFV and MB89538PFV do
not have I2C functions.
MB89F538L-101PV4
MB89F538L-201PV4
LCC-64P-M19
LCC-64P-M16*
MDP-64C-P02
MQP-64C-P01
MB89F538-101PV*
MB89F538-201PV*
MB89PV530C-101
MB89PV530C-201
MB89PV530CF-101
MB89PV530CF-201
* : Only for ES
56
MB89530 Series
■ PACKAGE DIMENSIONS
64-pin, Plastic SH-DIP
(DIP-64P-M01)
Note: Pins width and pins thickness include plating thickness.
58.00 +–00..5252 2.283 –+..002029
INDEX-1
INDEX-2
17.00±0.25
(.669±.010)
4.95 –+00..2700
.195 +–..000288
0.70 –+00..1590
.028 +–..000270
0.27±0.10
(.011±.004)
3.30 +–00..3200
19.05(.750)
.130 –+..001028
1.378 +–00..2400
.0543 +–..000186
0.47±0.10
(.019±.004)
1.00 +–00.50
1.778(.0700)
0~15°
M
0.25(.010)
.039 –+..0020
C
2001 FUJITSU LIMITED D64001S-c-4-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
57
MB89530 Series
64-pin, Plastic LQFP
(FPT-64P-M03)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*
10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
48
33
49
32
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
64
17
"A"
0.25(.010)
0.50±0.20
(.020±.008)
1
16
LEAD No.
0.60±0.15
(.024±.006)
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
C
2003 FUJITSU LIMITED F64009S-c-5-8
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
58
MB89530 Series
64-pin, Plastic QFP
(FPT-64P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
24.70±0.40(.972±.016)
*20.00±0.20(.787±.008)
0.17±0.06
(.007±.002)
51
33
52
32
18.70±0.40
(.736±.016)
Details of "A" part
*14.00±0.20
(.551±.008)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
INDEX
64
20
0~8˚
1
19
1.00(.039)
0.42±0.08
(.017±.003)
0.25 +–00..2105
M
0.20(.008)
.010 +–..000086
1.20±0.20
(.047±.008)
(Stand off)
"A"
0.10(.004)
C
2003 FUJITSU LIMITED F64013S-c-5-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
59
MB89530 Series
64-pin, Plastic LQFP
(FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
0.145±0.055
(.0057±.0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 –+00..1200
(Mounting height)
.059 +–..000048
0.25(.010)
INDEX
0~8˚
64
17
0.50±0.20
(.020±.008)
0.10±0.10
(.004±.004)
(Stand off)
"A"
1
16
0.60±0.15
(.024±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
60
MB89530 Series
64-pin, Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
19.05±0.30
(.750±.012)
INDEX AREA
2.54±0.25
(.100±.010)
0.25±0.05
(.010±.002)
33.02(1.300)REF
1.27±0.25
(.050±.010)
10.16(.400)MAX
+0.13
3.43±0.38
(.135±.015)
1.778±0.25
(.070±.010)
0.46–0.08
0.90±0.13
(.035±.005)
.018+–..000035
55.12(2.170)REF
C
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
61
MB89530 Series
64-pin, Ceramic MQFP
(MQP-64C-P01)
18.70(.736)TYP
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
12.00(.472)TYP
INDEX AREA
1.00±0.25
(.039±.010)
1.20 –+00..2400
.047 –+..000186
1.00±0.25
(.039±.010)
1.27±0.13
(.050±.005)
18.12±0.20
(.713±.008)
22.30±0.33
(.878±.013)
12.02(.473)
TYP
18.00(.709)
TYP
10.16(.400)
14.22(.560)
TYP
0.30(.012)
TYP
24.70(.972)
TYP
TYP
0.40±0.10
(.016±.004)
1.27±0.13
(.050±.005)
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.20 –+00..2400
.047 –+..000186
10.82(.426)
MAX
0.15±0.05
0.50(.020)TYP
(.006±.002)
C
1994 FUJITSU LIMITED M64004SC-1-3
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
62
MB89530 Series
64-pin, Plastic BCC
(LCC-64P-M19)
8.20(.323)TYP
8.10(.319)TYP
0.50±0.10
(.020±.004)
(0.80(.031)MAX)
(Mount height)
9.00±0.10(.354±.004)
0.50(.020)
TYP
49
33
33
49
0.50(.020)
TYP
8.25(.325)
REF
8.20(.323)
TYP
9.00±0.10
(.354±.004)
7.00(.276)
REF
8.10(.319)
TYP
0.50±0.10
(.020±.004)
INDEX AREA
"A"
7.00(.276)REF
17
1
0.075±0.025
(.003±.001)
(Stand off)
"C"
1
17
"B"
8.25(.325)REF
Details of "A" part
Details of "B" part
Details of "C" part
0.14(.006)MIN.
0.55±0.06
(.022±.002)
C0.2(.008)
0.70±0.06
(.028±.002)
0.55±0.06
(.022±.002)
0.05(.002)
0.60±0.06
(.024±.002)
0.30±0.06
(.012±.002)
0.55±0.06
(.022±.002)
0.30±0.06
(.012±.002)
0.55±0.06
(.022±.002)
C
2002 FUJITSU LIMITED C64019S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
63
MB89530 Series
(Continued)
64-pin, Plastic BCC
(LCC-64P-M16)
8.20(.323)TYP
7.00(.276)REF
9.00±0.10(.354±.004)
49
(0.80(.031)MAX)
(Mount height)
0.50(.020)
TYP
0.50±0.10
(.020±.004)
33
33
49
0.50(.020)
TYP
8.15(.321)
REF
7.00(.276)
REF
8.20(.323)
TYP
9.00±0.10
(.354±.004)
INDEX AREA
0.50±0.10
(.020±.004)
"B"
17
"A"
8.15(.321)REF
1
"C"
1
17
0.075±0.025
(.003±.001)
(Stand off)
Details of "A" part
Details of "B" part
Details of "C" part
0.40±0.06
(.016±.002)
0.45±0.06
(.018±.002)
0.45±0.06
(.018±.002)
0.14(.006)
MIN
C0.2(.008)
0.05(.002)
0.30±0.06
(.012±.002)
0.45±0.06
(.018±.002)
0.45±0.06
(.018±.002)
C
2001 FUJITSU LIMITED C64016S-c-2-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
64
MB89530 Series
FUJITSU LIMITED
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FUJITSU LIMITED Printed in Japan
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