MB89PV680_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12525-2E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89680 Series

MB89689/P689/W689/PV680

■ OUTLINE

The MB89680 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the

microcontrollers contain a variety of peripheral functions such as dual-clock control system, four operating speed

control stages, timers, PWM timer, a serial interface, a UART, an A/D converter, and an external interrupt.

■ FEATURES

• F²MC-8L family CPU core

• Dual-clock control system

• Maximum memory space: 64 Kbytes

• Minimum execution time: 0.5 µs/8 MHz

• Interrupt processing time: 4.5 µs/8 MHz

• I/O ports: max. 85 channels

• 21-bit timebase counter

• 8-bit PWM timer

• 8/16-bit timer

• UART

• Serial I/O with 1-byte buffer

• 8-bit A/D converter

• Pulse width counter

• Modem signal output

• External interrupts: 16 channels

• Power-on reset function

• Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode)

• CMOS technology

■ PACKAGE

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Ceramic QFP

100-pin Ceramic MQFP

(FPT-100C-A02)

(MQP-100C-P01)

MB89680 Series

■ PRODUCT LINEUP

Part number

MB89689

MB89P689

MB89W689

MB89PV680

Piggyback/

evaluation product

(for development)

Item

Classification

Mass-produced

product

(mask ROM product)

One-time PROM

product

EPROM product

ROM size

60 K × 8 bits

(internal mask ROM) (internal PROM)

60 K × 8 bits

(internal EPROM)

60 K × 8 bits

(external ROM)

RAM size

2.0 K × 8 bits

Instruction bit length

Instruction length

Data bit length

8 bits

1 byte to 3 bytes

1, 8, 16 bits

136

Number of instructions

Clock generator

Built-in

Minimum execution time

Interrupt processing time

0.5 µs/8 MHz to 8 µs/8 MHz, 61 µs/32.768 kHz

4.5 µs/8 MHz to 72 µs/8 MHz, 562.5 µs/32.768 kHz

Ports

Output ports (N-ch open-drain):

Output ports (CMOS):

I/O ports (N-ch open-drain):

I/O ports (CMOS):

21 (8)

8 (0)

8 (6)

( ) indicate dual function

ports

48 (29)

Total:

85 (43)

8-bit PWM timer

8/16-bit timer/counter

8-bit serial I/O

8-bit A/D converter

UART

8 bits × 1 channel

8 bits × 2 channels, or 16 bits × 1 channel

With 1-byte buffer × 1 channel

8 bits × 8 channels

Full-duplex double buffer

Transfer data length: 6 bits to 8 bits

8 baud rates selectability, external clock available

Pulse width counter

5-bit noise reduction circuit

Pulse edge detectable and selectable (rising, falling, and both edges)

Software modem

transmission circuit

1200-bps/2400-bps modem output

External interrupt

Timebase timer

Watch prescaler

Standby mode

Process

16 channels

21 bits

15 bits

Watch mode, subclock mode, sleep mode, and stop mode

CMOS

Power supply voltage*

EPROM for use

2.2 V to 6.0 V

2.7 V to 6.0 V

MBM27C512-20TV

* : Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS.”)

2

MB89680 Series

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89689

MB89P689

Package

MB89W689

MB89PV680

FPT-100P-M06

FPT-100C-A02

MQP-100C-P01

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

2. Current Consumption

In the case of the MB89PV680, add the current consumed by the EPROM which is connected to the top socket.

When operated at low speed, the product with an OTPROM or an EPROM will consume more current than

the product with a mask ROM.

However, the current consumption in sleep/stop modes is the same.

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product. Before using

options check section “■ Mask Options.” Take particular care on the following points:

• Options are fixed on the MB89PV680.

3

MB89680 Series

■ PIN ASSIGNMENT

(Top view)

V^CC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P97/INL7

P96/INL6

P95/INL5

P94/INL4

P93/INL3

P92/INL2

P91/INL1

P90/INL0

P87

P86

P85

P84

P83

X1A

X0A

MOD0

MOD1

X0

X1

VSS

RST

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P82

P81

P80

P77

P76

P75/BSO2

P74/BSI2

P73/BSK2

V^SS

P72/UO2

P71/UI2

P70/UCK2

P67/BSO1

P66/BSI1

P65/BSK1

P64

P63/MSKO

(FPT-100P-M06)

(FPT-100C-A02)

4

MB89680 Series

(Top view)

VCC

P97/INL7

P96/INL6

P95/INL5

P94/INL4

P93/INL3

P92/INL2

P91/INL1

P90/INL0

P87

P86

P85

P84

P83

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

X1A

X0A

MOD0

MOD1

X0

X1

V^SS

O7

O8

01

N.C.

A0

RST

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CE

A10

OE

N.C.

A11

A9

A1

P82

P81

P80

P77

A2

A3

P76

P75/BSO2

P74/BSI2

P73/BSK2

V^SS

P72/UO2

P71/UI2

P70/UCK2

P67/BSO1

P66/BSI1

P65/BSK1

P64

A4

A5

A8

A6

P63/MSKO

(MQP-100C-P01)

• Pin assignment on package top (MB89PV680 only)

Pin no.

101

Pin name

N.C.

A15

A12

A7

Pin no.

109

Pin name

A2

Pin no.

117

Pin name

N.C.

O4

Pin no.

125

Pin name

OE

102

110

A1

118

126

N.C.

A11

A9

103

111

A0

119

O5

127

104

112

N.C.

O1

120

O6

128

105

A6

113

121

O7

129

A8

106

A5

114

O2

122

O8

130

A13

A14

V^CC

107

A4

115

O3

123

CE

131

108

A3

116

V^SS

124

A10

132

N.C.: Internally connected. Do not use.

5

MB89680 Series

■ PIN DESCRIPTION

Pin no.

Pin name

Circuit type

Function

QFP^*1, MQFP^*2

1

V^CC

—

A

Power supply pin

2

X1A

Subclock crystal oscillator pins (32.768 kHz)

3

X0A

4

MOD0

MOD1

X0

B

A

Operating mode selection pins

Connect to V^SS(GND) when using.

5

6

7

Main clock crystal oscillator pins (8 MHz)

X1

8

V^SS

—

C

D

F

Power supply (GND) pin

Reset input pin

9

RST

10 to 17

18 to 25

26 to 33

34 to 38

39

P00 to P07

P10 to P17

P20 to P27

P40 to P44

P30/PWM

General-purpose I/O ports

General-purpose output ports

I

E

General-purpose I/O port

Also serve as an 8-bit PWM.

40

41

P31/BUZR

P32/MSKI

E

General-purpose I/O port

Also serve as a buzzer output.

General-purpose I/O port

Also serve as a pulse width counter.

42,

43

P33,

P34

General-purpose I/O ports

44,

45,

46

P35/UCK1,

P36/UI1,

P37/UO1

General-purpose I/O ports

Also serve as a UART I/O 1.

47,

48,

49

P60/TMO1,

P61/TMO2,

P62/TCLK

E

General-purpose I/O ports

Also serve as an 8/16-bit timer.

50

51

V^CC

—

E

Power supply pin

P63/MSKO

General-purpose I/O port

Also serve as a modem output.

52

P64

E

General-purpose I/O port

53,

54,

55

P65/BSK1,

P66/BSI1,

P67/BSO1

General-purpose I/O ports

Also serve as a serial I/O 1 with 1-byte buffer.

(Continued)

*1: FPT-100P-M06, FPT-100C-A02

*2: MQP-100C-P01

6

MB89680 Series

(Continued)

Pin no.

Pin name

Circuit type

Function

QFP^*1, MQFP^*2

56,

57,

58

P70/UCK2,

P71/UI2,

P72/UO2

H

General-purpose I/O ports

Also serve as a UART I/O 2.

59

V^SS

—

H

Power supply (GND) pin

60,

61,

62

P73/BSK2,

P74/BSI2,

P75/BSO2

General-purpose I/O ports

Also serve as a serial I/O 2 with 1-byte buffer.

63,

64

P76,

P77

H

General-purpose I/O ports

65 to 72

73 to 80

P80 to P87

I

General-purpose output ports

P90/INL0 to

P97/INL7

E

General-purpose I/O ports

External interrupt input is hysteresis input.

81 to 83

PA0/INL8 to

PA2/INLA

E

General-purpose I/O ports

External interrupt input is hysteresis input.

84

V^SS(AV^SS)

—

G

(A/D converter) power supply (GND) pin

85 to 92

P50/AN00 to

P57/AN07

General-purpose I/O ports

Also serve as an analog input.

93

94

95

V^CC(AV^CC)

AVR

—

(A/D converter) power supply pin

A/D converter reference voltage input pin

N.C.

Internally connected pins

Be sure to leave them open.

96 to 100

PA3/INLB,

PA4/INT0 to

PA7/INT3

E

General-purpose I/O ports

External interrupt input is hysteresis input.

*1: FPT-100P-M06, FPT-100C-A02

*2: MQP-100C-P01

7

MB89680 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Main clock (A2)

(At an oscillation feedback resistor of approximately

1 MΩ/5.0 V)

• Subclock (A1)

(At an oscillation feedback resistor of approximately

4.5 MΩ/5.0 V

X1, X1A

X0, X0A

*

* The subclock circuit in the MB89PV680

contains no oscillation feedback resistor.

Standby control signal

B

C

• At an output pull-up resistor (P-ch) of approximately

50 kΩ/5.0 V

• Hysteresis input

R

P-ch

N-ch

D

• CMOS output

• CMOS input

R

P-ch

• Pull-up resistor optional

P-ch

N-ch

E

• CMOS output

• Hysteresis input

• Pull-up resistor optional

R

P-ch

N-ch

(Continued)

8

MB89680 Series

(Continued)

Type

Circuit

Remarks

F

• CMOS output

P-ch

N-ch

G

• N-ch open-drain output

• Analog input

P-ch

N-ch

Analog input

H

• N-ch open-drain output

• Hysteresis input

• Pull-up resistor optional

R

P-ch

N-ch

I

• N-ch open-drain output

• Pull-up resistor optional

R

P-ch

N-ch

9

MB89680 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than V^CCor lower than V^SSis applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between V^CCand V^SS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (V^CC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AV^CC= DAVC = V^CCand AV^SS= AVR = V^SSeven if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although V^CCpower supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could causemalfunctions, even if itoccurs within the rated range. Stabilizingvoltagesupplied totheIC is therefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 Hz to 60 Hz) and the

transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

6. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

wake-up from stop mode.

10

MB89680 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P689/W689

The MB89P689/W689 is an OTPROM version of the MP89680 series.

1. Features

• 60-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalent to the MBM27C1001 in EPROM mode (when programmed with the EPROM programmer) and

supporting the 4-byte programming mode

2. Memory Space

Memory space in each mode such as 60-Kbyte PROM, option area is diagrammed below.

Single chip

EPROM mode

(Corresponding addresses on the EPROM programmer)

Address

00000H

I/O

00080H

RAM

2 KB

Not available

00880H

00FE4H

Not available

Option area

00FE4H

Option area

00FFCH

01000^H

01000H

PROM

60 KB

PROM

60 KB

0FFFFH

0FFFF^H

Not available

1FFFF^H

3. Programming to the EPROM

In EPROM mode, the MB89P689 functions equivalent to the MBM27C1001. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter.

When the operating ROM area for a single chip is 60 Kbytes (1000^Hto FFFF^H) the PROM can be programmed

as follows:

• Programming procedure

(1) Set the EPROM programmer to MBM27C1001.

(2) Load program data into the EPROM programmer at 1000^Hto FFFF^H.

Load option data into addresses 0FE4^Hto 0FFC^Hof the EPROM programmer. (For information about each

corresponding option, see “8. Setting PROM Options.”)

(3) Program to 0FE4^Hto 0FFC^Hand 1000^Hto FFFF^Hwith the EPROM programmer.

11

MB89680 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. MB89W689 Erasure

In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an

ultraviolet light source. A dosage of 10 W-seconds/cm²is required to completely erase an internal EPROM. This

dosage can be obtained by exposure to an ultraviolent lamp (wavelength of 2537 Angstroms (Å)) with intensity

of 12000µW/cm²for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all

filters should be removed from the UV light source prior to erasure.

It is important to note that the internal EPROM and similar devices, will erase with light sources having wave-

lengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,

nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and

exposure to them should be prevented to realize maximum system reliability. If used in such an environment,

the package windows should be covered by an opaque label or substance.

12

MB89680 Series

7. EPROM Programmer Socket Adapter

Part no.

Package

MB89P689PF

QFP-100

Compatible

socket adapter

Sun Hayato Co.,

Ltd.

ROM-100QF-32DP-8LA

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

8. Setting PROM Options

The programming procedure is the same as that for the program data. Options can be set by programming

values at the addresses shown on the memory map. The relationship between bits and options is shown on the

following bit map:

• PROM option bit map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Reset

output

1: Yes

0: No

Bit 2

Bit 1

Bit 0

Oscillation stabilization time

Vacancy

Power-on

reset

1: Yes

0: No

Single/dual-

clock system

1: Dual clock

00FE4^H

11 2¹⁸/F^CH

01 2¹²/F^CH

10 2¹⁶/F^CH

Readable

3

and writable and writable and writable 2: Single clock

00 2 /F^CH

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

00FE8^H

00FEC^H

00FF0^H

00FF4^H

00FF8^H

00FFC^H

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P67

Pull-up

Readable

P66

Pull-up

Readable

P65

Pull-up

Readable

P64

P63

P62

P61

P60

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

and writable and writable and writable

P97

P96

P95

P94

P93

P92

P91

P90

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Notes: • Note that the option setting area addresses are at intervals of four addresses to support the 4-byte

programming mode.

• In three bytes between adjacent setup addresses, the value written to the preceding setup address is

mirrored. Be sure to set the same data in the programmer.

• Each bit is set to ‘1’ as the initialized value.

13

MB89680 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C512-20TV

2. Programming Socket Adapter

Package

Adapter socket part number

LCC-32 (Rectangle)

ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

3. Memory Space

Address

0000H

MB89PV680

I/O

MBM27C512

0080H

0100H

0200H

Register

RAM

2 KB

0880H

1000H

1000^H

FFFFH

External ROM

60 KB

EPROM

60 KB

FFFF^H

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C512.

(2) Load program data into the EPROM programmer at 1000^Hto FFFF^H.

(3) Program to 1000^Hto FFFF^Hwith the EPROM programmer.

14

MB89680 Series

■ BLOCK DIAGRAM

CMOS I/O

Timebase timer

P30/PWM

P31/BUZR

8-bit PWM timer

Reset circuit

(Watchdog)

RST

Buzzer output

Modem timer

P32/MSKI

P33

P34

X0

X1

Main clock oscillator

(max 8 MHz)

P35/UCK1

P36/UI1

P37/UO1

UART

Clock controller

X0A

X1A

Subclock oscillator

(32.768 kHz)

5

N-ch open-drain output port 4

N-ch open-drain output

P40 to P44

8

P00 to P07

P10 to P17

P20 to P27

CMOS I/O port 0

8

8-bit A/D

converter

P50/AN00

to P57/AN07

8

CMOS I/O port 1

CMOS I/O port 2

CMOS I/O

P60/TMO1

P61/TMO2

P62/TCLK

8/16-bit timer

Modem output

P63/MSKO

P64

P65/BSK1

P66/BSI1

P67/BSO1

8-bit serial I/O

with 1-byte buffer

RAM

P70/UCK2

P71/UI2

P72/UO2

P73/BSK2

P74/BSI2

P75/BSO2

P76

F²MC-8L

CPU

P77

N-ch open-drain I/O

ROM

8

N-ch open-drain output port 8

CMOS I/O

P80 to P87

8

4

P90/INL0

to P97/INL7

PA0/INL8

to PA3/INLB

PA4/INT0

12

External interrupt 2

Other pins

VCC × 2, VSS × 2

MOD0, MOD1, N.C.

AV^CC, AVR, AVSS

to PA7/INT3

4

External interrupt 1

15

MB89680 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89680 series offer 64 Kbytes of memory for storing all of I/O, data, and program

areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area.

The data area can be divided into register, stack, and direct areas according to the application. The program

area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89680 series is structured as illustrated below.

• Memory space

MB89689

I/O

MB89P689

MB89W689

MB89PV680

I/O

0 0 0 0 H

I/O

0 0 7 F H

0 0 8 0 H

0 0 7 F H

0 0 8 0 H

0 0 7 F H

0 0 8 0 H

00FFH

0 1 0 0 H

00FFH

0 1 0 0 H

00FFH

0 1 0 0 H

Register

01FFH

0 2 0 0 H

01FFH

0 2 0 0 H

01FFH

0 2 0 0 H

RAM

2.0 KB

0 8 7 F H

0 8 8 0 H

0 8 7 F H

0 8 8 0 H

0 8 7 F H

0 8 8 0 H

Vacancy

0FFFH

1 0 0 0 H

0FFFH

1 0 0 0 H

0FFFH

1 0 0 0 H

ROM

60 KB

ROM

60 KB

External ROM

60 KB

FFFFH

16

MB89680 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating the instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

Whenthe instructionisan8-bitdataprocessinginstruction, thelowerbyteisused.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

Initial value

FFFD^H

PC

A

: Program counter

: Accumulator

Indeterminate

T

: Temporary accumulator Indeterminate

IX

: Index register

: Extra pointer

: Stack pointer

: Program status

Indeterminate

EP

SP

PS

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

• Structure of the program status register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

17

MB89680 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

• Rule for conversion of actual addresses of the general-purpose register area

Lower OP codes

RP

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’.

Cleared to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

0

1

2

3

High

0

1

0

1

Low

N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is

cleared to ‘0’.

Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.

18

MB89680 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used. The bank currently in use is indicated by the register

bank pointer (RP).

• Register bank configuration

This address = 0100^H+ 2 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

19

MB89680 Series

■ I/O MAP

Address

00^H

01^H

02^H

03^H

04^H

05^H

06^H

07^H

08^H

09^H

0A^H

0B^H

0C^H

0D^H

0E^H

0F^H

10^H

11^H

12^H

13^H

14^H

15^H

16^H

17^H

18^H

19^H

1A^H

1B^H

1C^H

1D^H

1E^H

1F^H

20^H

21^H

22^H

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

(R/W)

(W)

PDR1

DDR1

Port 1 data direction register

Port 2 data register

(R/W)

PDR2

(Vacancy)

(R/W)

SYCC

SMC

System clock control register

Standby control register

Watchdog timer control register

Timebase timer control register

Watch prescaler control register

Port 3 data register

WDTC

TBTC

WPCR

PDR3

DDR3

PDR4

BZCR

PDR5

Port 3 data direction register

Port 4 data register

Buzzer register

Port 5 data register

(Vacancy)

(R/W)

PDR6

DDR6

PDR7

Port 6 data register

Port 6 data direction register

Port 7 data register

(Vacancy)

(R/W)

PDR8

Port 8 data register

(Vacancy)

(R/W)

PDR9

DDR9

PDRA

DDRA

Port 9 data register

Port 9 data direction register

Port A data register

Port A data direction register

(Vacancy)

(R/W)

(W)

CNTR

PWM control register

PWM compare register

COMR

(Vacancy)

(R/W)

SBMR

Serial mode register with 1 byte buffer

(Continued)

20

MB89680 Series

(Continued)

Address

Read/write

(R/W)

(W)

Register name

SBFR

Register description

23^H

Serial flag register with 1 byte buffer

SBUFW

SBUFR

SBDR

Serial buffer write register

24^H

(R)

Serial buffer read register

25^H

26^H

(R)

Serial data register with 1 byte buffer

Timer 2 control register

(R/W)

T2CR

27^H

T1CR

Timer 1 control register

28^H

T2DR

Timer 2 data register

29^H

T1DR

Timer 1 data register

2A^H

2B^H

2C^H

2D^H

2E^H

2F^H

MODC

MODA

Modem output control register

Modem output data register

(Vacancy)

(R/W)

(R)

ADC1

ADC2

ADCD

EIE1

A/D converter control 1 register

A/D converter control 2 register

A/D converter data register

External interrupt 1 enable register

External interrupt 1 flag register

External interrupt 2 enable register

External interrupt 2 flag register

Modem timer control 1 register

Modem timer control 2 register

Modem timer “H” level data register

Modem timer “L” level data register

UART serial mode control register

UART serial rate control register

UART serial status and data register

UART serial input data register

UART serial output data register

Serial I/O port switching register

(Vacancy)

30^H

31^H

EIF1

32^H

EIE2

33^H

EIF2

34^H

MDC1

MDC2

MLDH

MLDL

SMC

35^H

36^H

37^H

(R)

38^H

(R/W)

(R)

39^H

SRC

3A^H

3B^H

3C^H

3D^H

3E^Hto 7B^H

7C^H

7D^H

7E^H

7F^H

SSD

SIDR

SODR

SSEL

(W)

(R/W)

(W)

ILR1

ILR2

ILR3

Interrupt level 1 setting register

Interrupt level 2 setting register

Interrupt level 3 setting register

(Vacancy)

Note: Do not use (vacancies).

21

MB89680 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AV^SS= V^SS= 0.0 V)

Remarks

Value

Symbol

Unit

Parameter

Min.

Max.

V^CC

V^SS– 0.3

V^SS+ 7.0

V

AV^CC

Set V^CC= AV^CC*

Power supply voltage

AVR must not exceed “AV^CC+

0.3 V”.

AVR

V^SS– 0.3

V^SS+ 7.0

V

V^I

V^SS– 0.3

V^CC+ 0.3

V^SS+ 7.0

V^CC+ 0.3

V

Except P4, P7, P8

P4, P7, P8

Input voltage

V^I

Output voltage

V^O

“L” level maximum output

current

I^OL

20

10

mA Peak value

Average value (operating current

× operating rate)

“L” level average output current

I^OLAV

∑I^OL

∑I^OLAV

I^OH

mA

“L” level total maximum output

current

120

40

mA Peak value

“L” level total average output

current

Average value (operating current

× operating rate)

mA

“H” level maximum output

current

–20

–10

–60

–20

mA Peak value

Average value (operating current

× operating rate)

“H” level average output current

I^OHAV

∑I^OH

∑I^OHAV

mA

“H” level total maximum output

current

mA Peak value

“H” level total average output

current

Average value (operating current

× operating rate)

mA

Power consumption

Operating temperature

Storage temperature

P^D

200

+85

mW

°C

T^A

–40

–55

Tstg

+150

°C

* : Use AV^CCand V^CCset to the same voltage.

Take care so that AV^CCdoes not exceed V^CC, such as when power is turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

22

MB89680 Series

2. Recommended Operating Conditions

(AV^SS= V^SS= 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC,

AV^CC

Normal operation assurance range*

(MB89689)

2.2*

2.7*

1.5

6.0*

V

V^CC,

AV^CC

Normal operation assurance range*

(MB89P689/W689/PV680)

Power supply voltage

6.0*

6.0

V^CC,

AV^CC

Retains the RAM state in stop mode

A/D converter reference input

voltage

AVR

T^A

0.0

AV^CC

+85

V

Operating temperature

–40

°C

* : This values vary with the operating frequency. See Figure 1.

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

6

5

Analog accuracy assured in the

AV^CC= 3.5 V to 6.0 V range

Operation assurance range

4

3

2

1

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

Main clock operating frequency (MHz) (at an instruction cycle of 4/F^CH)

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F^CH.

Since the operating voltage range is dependent of the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

23

MB89680 Series

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

24

MB89680 Series

3. DC Characteristics

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Parameter

Symbol

Pin name

P0, P1

Condition

Unit Remarks

Min.

Typ.

Max.

V^CC+ 0.3

V^IH

0.7 V^CC

—

V

P3, P6, P9, PA,

RST, MOD0,

MOD1, X0, X0A

“H” level input

voltage

V^CC+ 0.3

V^IHS

0.8 V^CC

—

V

V^SS+ 7.0

0.3 V^CC

V^IHS2

V^IL

P7

0.8 V^CC

V

V^SS− 0.3

P0, P1

—

“L” level input

voltage

P3, P6, P7, P9, PA,

RST, MOD0,

V^SS− 0.3

V^ILS

0.2 V

CC

V

MOD1, X0, X0A

V^SS− 0.3

V^SS+ 7.0

V^CC+ 0.3

Open-drain

output pin applied V^D

voltage

P4, P7, P8

P5

—

V

“H” level output

voltage

P0 to P3, P6, P9,

PA

V^OH

I^OH= –2.0 mA

2.4

—

V

P0 to P4, P6 to P9,

PA

V^OL1

V^OL2

I^OL= 4.0 mA

—

0.4

V

“L” level output

voltage

RST

Input leakage

current (Hi-z

output leakage

current)

P0 to P9, PA,

MOD0, MOD1

0.45 V < V^I<

V^CC

I^LI

—

±5

µA

F^CH= 8 MHz

V^CC= 5.0 V

Main clock

opration

I^CC

V^CC

—

13

26

mA

Highest gear

speed

F^CH= 8 MHz

V^CC= 5.0 V

Main sleep

mode

Highest gear

speed

I^CCS1

V^CC

—

4

8

mA

Power supply

current

F^CH= 32.768 kHz

V^CC= 3.0 V

Subclock

I^CCS2

V^CC

—

25

—

50

1

µA

sleep mode

T^A= +25°C

Subclock stop

mode

I^CCH1

V^CC

µA

(Continued)

25

MB89680 Series

(Continued)

(AV^CC= V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Parameter

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

T^A= +85°C

Subclock stop

mode

I^CCH2

V^CC

—

1

10

µA

F^CL= 32.768 kHz

V^CC= 3.0 V

Subclock

I^CSB

V^CC

—

50

100

µA

operation

Power supply

current

V^CC= 3.0 V

Watch mode

I^CCT

V^CC

—

15

When A/D

mA conversion

is activated

I^A

AV^CC

1.5

3.5

F^CH= 8 MHz

f = 1 MHz

When A/D

µA conversion

is stopped

I^AH

AV^CC

—

1

5

Other than AV^CC,

AV^SS, V^CC,and V^SS

Input capacitance C^IN

10

—

pF

26

MB89680 Series

4. AC Characteristics

(1) Reset Timing

(V^CC= 5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

—

RST “L” pulse width

RST “H” pulse width

t^ZLZH

t^ZHZL

48 t^XCYL*

24 t^XCYL*

ns

—

* : t^XCYLis the oscillation cycle input to the X0.

tZLZH

tZHZL

RST

0.8 VCC

0.2 VCC

(2) Specifications for Power-on Reset

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Condition

Unit

Remarks

Parameter

Min.

Max.

50

Power supply rising time

Power supply cut-off time

t^R

—

1

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

—

Note: Make sure that power supply rises within the selected oscillation stabilization time selected.

For example, when the main clock is operating at F^CH= 8 MHz and the oscillation stabilization time is 2¹²/F^CH,

the oscillation stabilization time is 0.5 ms. Therefore, the maximum value of power supply rising time is about

0.5 ms.

When increasing the supply voltage during operation, voltage variation should be within twice the intended

increment so that the voltage rises as smoothly as possible.

tOFF

t^R

4.5 V

0.2 V

V

CC

27

MB89680 Series

(3) Clock Timing

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

name

Symbol

Condition

Unit

Remarks

Parameter

Min.

Typ.

Max.

F^CH

X0, X1

1

—

8

MHz Main clock

kHz Subclock

Input clock frequency

X0A,

X1A

32.768

—

F^CL

—

125

—

1000

—

t^HCYL

t^LCYL

X0, X1

ns

Main clock

Subclock

Clock cycle time

X0A,

X1A

30.5

µs

duty*¹

duty1*²

t^CR1

X0

30

—

70

%

—

Input clock duty rate

X1

X0

24

ns

External clock

t^CF1

X0

24

Input clock rising/falling

time

t^CR2

X0A

200

t^CF2

*1: duty = P^WH/t^HCYL

*2: duty1= P^WHL/t^HCYL

• Main clock timing conditions

tHCYL

0.8 VCC

X0

0.2 VCC

PWH

PWL

tCR

tCF

• Main clock configurations

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

FCH

C0

C¹

28

MB89680 Series

• Subclock timing conditions

tLCYL

0.8 VCC

X0A

0.2 VCC

PWHL

PWLL

tCR

tCF

• Subclock configurations

When a crystal

or

ceramic resonator is used

When an external clock is used

X0A

X1A

X0A

X1A

Open

FCL

C1

C0

FCL

(4) Instruction Cycle

Parameter

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Symbol

Value (typical)

Unit

Remarks

(4/F^CH) t^inst= 0.5 µs when operating at

F^CH= 8 MHz

t^inst

4/F^CH, 8/F^CH, 16/F^CH, 64/F^CH

µs

Minimum execution time

(instruction cycle)

t^inst= 61.036 µs when operating at

F^CL= 32.768 kHz

t^inst

2/F^CL

µs

29

MB89680 Series

(5) Serial I/O Timing

(AV^CC= V^CC= 5.0 V ±10%, V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

t^SCYC

t^SLOV

t^IVSH

t^SHIX

Pin name

Condition

Unit Remarks

Parameter

Min.

Max.

Serial clock cycle time

BSK/UCK

2 t^inst*

—

µs

BSK/UCK ↓ → BSO/UO

BSK/UCK,

BSO/UO

–200

200

—

ns

time

Internal shift

clock mode

BSI/UI,

BSK/UCK

Valid BSI/UI → BSK/UCK ↑

1/2 t^inst*

µs

BSK/UCK ↑ → valid BSI/UI

hold time

BSK/UCK,

BSI/UI

—

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

BSK/UCK

1 t^inst*

—

µs

BSK/UCK ↓ → BSO/UO

time

BSK/UCK,

BSO/UO

t^SLOV

t^IVSH

t^SHIX

0

200

—

ns

µs

External shift

clock mode

BSI/UI,

BSK/UCK

Valid BSI/UI → BSK/UCK ↑

1/2 t^inst*

BSK/UCK ↑ → valid BSI/UI

hold time

BSK/UCK,

BSI/UI

—

* : For information on t^inst, see “(4) Instruction Cycle.”

• Internal shift clock mode

tSCYC

2.4 V

BSK/UCK

0.8 V

tSLOV

2.4 V

BSO/UO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

BSI/UI

0.2 VCC

• External shift clock mode

tSLSH

tSHSL

0.8 VCC

BSK/UCK

0.2 VCC

tSLOV

2.4 V

0.8 V

BSO/UO

BSI/UI

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

30

MB89680 Series

(6) Peripheral Input Timing

Parameter

(AV^CC= V^CC= 5.0 V ±10%, V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Unit Remarks

Min.

Max.

Peripheral input “H” level pulse

width

INL0 to INLB,

INT0 to INT3

t^ILIH

t^IHIL

2 t^inst*

—

µs

Peripheral input “L” level pulse

width

INL20 to INLB,

INT0 to INT3

2 t^inst*

—

* : For information on t^inst,see “(4) Instruction Cycle.”

tILIH

tIHIL

INL0 to INLB

INT0 to INT3

0.8 VCC

0.2 V^CC

0.8 VCC

0.2 VCC

31

MB89680 Series

5. A/D Converter Electrical Characteristics

(AV^CC= V^CC= 3.5 V to 6.0 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Typ.

name

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

AVR = AV^CC

= 5.0 V

Resolution

—

8

bit

Total error

—

±1.5

±1.0

LSB

Linearity error

Differential linearity

error

—

V^0T

V^FST

—

±0.9

LSB

AVR = AV^CC

Zero transition

voltage

AVss

–1.0 LSB

AVss

+0.5 LSB

AVss

+2.0 LSB

mV

1 LSB =

AVR/256

AVR

–3.0 LSB

Full-scale transition

voltage

AVR

–1.5 LSB

AVR

0.5

—

mV

Interchannel

disparity

—

44

12

—

LSB

t^inst*

µA

A/D mode

conversion time

—

Sense mode

conversion time

—

Analog port input

current

AN00to

AN07

—

I^AIN

—

10

AN00to

AN07

Analog input voltage

Reference voltage

0.0

AVR

V

—

I^R

AVR

0.0

—

100

—

AV^CC

300

1

V

µA

Reference voltage

supply current

AVR = AV^CC

= 5.0 V

I^RH

—

* : For information on t^inst, see “(4) Instruction Cycle.”

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable by the A/D converter

When the number of bits is 8, analog voltage can be divided into 2⁸= 256.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

32

MB89680 Series

Digital output

Theoretical conversion value

Actual conversion value

1111 1111

1111 1110

•

(1 LSB × N + V^OT)

AVR

256

•

1 LSB =

•

V^NT– (1 LSB × N + VOT)

•

Linearity error =

•

1 LSB

•

V( N + 1 ) T – VNT

•

– 1

Differential linearity error =

Total error =

•

1 LSB

Linearity error

•

VNT – (1 LSB × N + 1 LSB)

•

1 LSB

•

0000 0010

0000 0001

0000 0000

VOT

VNT

V(N + 1)T

VFST

Analog input

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D converter used for the MB89890 series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx.

0.1 µF for the analog input pin.

• Analog Input Equivalent Circuit

Sample hold circuit

C

33 pF

Analog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

R

6 kΩ

Close for 8 instruction cycles after starting

A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

33

MB89680 Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

#vct

#d8

#d16

dir: b

rel

@

Register indirect (Example: @A, @IX, @EP)

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

T

TH

TL

IX

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

(Continued)

34

MB89680 Series

(Continued)

Symbol

Meaning

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

CCR

RP

Ri

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

The number of instructions

The number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

35

MB89680 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH N ZVC

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

(A) ← (Ri)

(dir) ← d8

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

–

AH

–

XCHW A,T

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

–

(A) ← (PC)

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

36

MB89680 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH

NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

INC Ri

INCW EP

INCW IX

INCW A

C8 to CF

C3

C2

C0

D8 to DF

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

ANDW A

ORW A

XORW A

CMP A

–

D3

D2

D0

01

11

63

73

53

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

(TL) − (AL)

(T) − (A)

12

13

03

CMPW A

RORC A

–

→

A

C

←

C ← A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

(A) − (Ri)

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

64

65

AND A,#d8

AND A,dir

(A) ← (AL) (dir)

(Continued)

37

MB89680 Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH

NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

C1

D1

DECW SP

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH

NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH

NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

CLRI

SETI

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

38

MB89680 Series

■ INSTRUCTION MAP

39

MB89680 Series

■ MASK OPTIONS

MB89P689

MB89W689

Part number

No.

MB89689

MB89PV680

Spcify when ordering

masking

Set with EPROM

programmer

Setting not

possible

Specifying procedure

Pull-up resistors

P00 to P07,

P10 to P17,

Fixed to without a

pull-up resistor

1

P30 to P37,

P60 to P67,

P90 to P97,

PA0 to PA7

Selectable by pin

Selectable

Selectable by pin

Selectable

Power-on reset (POR)

With power-on reset

Without power-on reset

Fixed to with power-on

reset

2

3

Oscillation stabilization time

selection (OSC)

The initial value of the main

clock oscillation stabilization

time can be set with WTM1

and WTM0 bit.

Selectable

WTM1 WTM0

Selectable

WTM1 WTM0

Fixed to oscillation

stabilization time of

2¹⁸/F^CH

0

1

0: 2³/F^CH

1: 2¹²/F^CH

0: 2¹⁶/F^CH

1: 2¹⁸/F^CH

0

1

0: 2³/F^CH

1: 2¹²/F^CH

0: 2¹⁶/F^CH

1: 2¹⁸/F^CH

Reset pin output (RST)

With reset output

Fixed to with reset

output

4

5

Selectable

Without reset output

Clock mode selection (CLK)

Dual-clock mode

Selectable

Fixed to dual clock

Single-clock mode

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89689PF

MB89P689PF

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Ceramic QFP

(FPT-100C-A02)

MB89W689CF

MB89PV680CF

100-pin Ceramic MQFP

(MQP-100C-P01)

40

MB89680 Series

■ PACKAGE DIMENSIONS

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

16.30±0.40

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

REF

(.642±.016)

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

"B"

0.10(.004)

0.30(.012)

0.18(.007)MAX

0

10°

18.85(.742)REF

0.80±0.20

(.031±.008)

0.53(.021)MAX

22.30±0.40(.878±.016)

C

1994 FUJITSU LIMITED F100008-3C-2

Dimensions in mm (inches)

100-pin Ceramic QFP

(FPT-100C-A02)

0.51(.020) TYP

17.91(.705)

TYP

12.34(.486)

REF

16.31(.642)

TYP

8.89(.350)DIA

TYP

16.00(.630)

14.00±0.25

(.551±.010)

TYP

INDEX AREA

0.65±0.15

(.0256±.0060)

0.30±0.05

(.012±.002)

0.65±0.15

(.0256±.0060)

0.15±0.05

(.006±.002)

18.85(.742)REF

1.60(.063) TYP

20.00±0.25

(.787±.010)

4.45(.175)MAX

23.90(.941) TYP

22.00(.866) TYP

22.30(.878) TYP

0.80(.0315) TYP

C

1994 FUJITSU LIMITED F100013SC-1-2

Dimensions in mm (inches)

41

MB89680 Series

100-pin Ceramic MQFP

(MQP-100C-P01)

18.70(.736)TYP

16.30±0.33

(.642±.013)

15.58±0.20

(.613±.008)

12.35(.486)TYP

INDEX AREA

0.65±0.15

(.0256±.0060)

1.20^–⁺⁰⁰^.^.²⁴⁰⁰

.047^–⁺^.^.⁰⁰⁰¹⁸⁶

0.65±0.15

(.0256±.0060)

1.27±0.13

(.050±.005)

18.12±0.20

(.713±.008)

22.30±0.33

(.878±.013)

12.02(.473)

TYP

18.85(.742)

TYP

10.16(.400)

14.22(.560)

TYP

0.30(.012)

TYP

24.70(.972)

TYP

0.30±0.08

(.012±.003)

1.27±0.13

(.050±.005)

0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.30±0.08

(.012±.003)

1.20^–⁺⁰⁰^.^.²⁴⁰⁰

.047^–⁺^.^.⁰⁰⁰¹⁸⁶

10.82(.426)

MAX

0.15±0.05

(.006±.002)

C

1994 FUJITSU LIMITED M100001SC-1-2

Dimensions in mm (inches)

42

MB89680 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: (044) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: (044) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document presented

as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the

use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9802

FUJITSU LIMITED Printed in Japan

44


型号：	MB89PV680
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总43页 (文件大小：657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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