MB89W867_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12504-5E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89860/850 Series

MB89865/867/P867/W867

MB89855/857/P857/W857/T855

■ DESCRIPTION

The MB89860/850 series has been developed as a general-purpose version of the F²MC*-8L family consisting

of proprietary 8-bit, single-chip, microcontrollers.

In addition to the F²MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers

contain a variety of peripheral functions such as a timer unit, PWM timers, a UART, a serial interface, a 10-bit

A/D converter, and an external interrupt.

The MB89860/850 series is applicable to a wide range of applications from welfare products to industrial

equipment, including portable devices.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• Various package options

QFP package (80 pins): MB89860

SDIP package (64 pins): MB89850

• High-speed processing at low voltage

Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V

(Continued)

■ PACKAGE

80-pin Ceramic QFP

64-pin Plastic SH-DIP

80-pin Plastic QFP

64-pin Plastic SH-DIP

(FPT-80P-M06)

(DIP-64P-M01)

(FPT-80C-A02)

(DIP-64C-A06)

MB89860/850 Series

(Continued)

• F²MC-8L family CPU core

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Instruction set optimized for controllers

Bit manipulation instructions, etc.

• 8-bit PWM timers: 2 channels

Also usable as a reload timer

• UART

Full-duplex double buffer

Synchronous and asynchronous data transfer

• 8-bit serial I/O

Switchable transfer direction allows communication with various equipment.

• 10-bit A/D converter

Conversion time: 13.2 µs

Activation by an external input or a timer unit capable

• External interrupt: 4 channels

Four channels are independent and capable of wake-up from low-power consumption modes (with an edge

detection function).

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

• Bus interface functions

Including hold and ready functions

• Timer unit

Outputs non-overlap three-phase waveforms to control an AC inverter motor.

Also usable as a PWM timer (4 channels)

2

MB89860/850 Series

■ PRODUCT LINEUP

Part number

MB89P857

MB89P867

MB89855

MB89T855

MB89865

MB89857

MB89867

MB89W857 MB89W867

Parameter

Classification

One-time PROM pruducts/

EPROM products, also

used for evaluation

Mass production products (mask ROM products)

ROM size

16 K × 8 bits

(internal mask ROM)

Note: In MB89T855, no

internal ROM can be used but

external ROM is used.

32 K × 8 bits

(internal mask ROM)

32 K × 8 bits

(internal PROM,

programming with general-

purpose EPROM

programmer)

RAM size

512 × 8 bits

1 K × 8 bits

CPU functions

Number of instructions:

Instruction bit length:

Instruction length:

Data bit length:

Minimum execution time:

Interrupt processing time:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

0.4 µs/10 MHz

3.6 µs/10 MHz

Ports

Input ports:

5 (All also serve as peripherals)

Output ports (N-ch open drain): 8 (All also serve as peripherals)

I/O ports (N-ch open drain):

Output ports (CMOS):

I/O ports (CMOS):

Total:

15 (MB89860 series only)

8 (All also serve as bus control pins)

32 (All also serve as bus pins or peripherals)

68 (53 pins for MB89850 series)

Timer unit

10-bit up/down count timer × 1

Compare registers with buffer × 4

Compare timer unit clear register with buffer × 1

Zero detection pin control

4 output channels

Non-overlap three-phase waveform output

Independent three-phase dead-time timer

8-bit PWM timer 1,

8-bit PWM timer 2

8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to

25.6 µs)

8-bit resolution PWM operation (conversion cycle: 102 µs to 6.528 ms)

UART

8 bits

Clock synchronous/asynchronous data transfer capable

8-bit serial I/O

8 bits

LSB first/MSB first selectability

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

10-bit A/D converter

External interrupt

10-bit resolution × 8 channels

A/D conversion time: 13.2 µs

Continous activation by a compare channel 0 in timer unit or an external activation capable

4 independent channels (edge selection, interrupt vector, source flag)

Rising edge/falling edge selectability.

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)

Standby modes

Process

Sleep mode, stop mode

CMOS

Operating voltage*

2.7 V to 6.0 V

2.7 V to 5.5 V

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

3

MB89860/850 Series

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89855

MB89865

MB89T855

Package

MB89W857

MB89867

MB89W867

MB89857

MB89P867

MB89P857

DIP-64P-M01

DIP-64C-A06

FPT-80P-M06

FPT-80C-A02

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the OTPROM (one-time PROM) products (also used for evaluation), verify its differences

from the product that will actually be used.

Take particular care on the following point:

• The stack area, etc., is set at the upper limit of the RAM.

2. Current Consumption

When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the

product with a mask ROM.

However, the current consumption in sleep/stop modes is the same.

3. Mask Options

In the MB89P857/W857/P867/W867/T855, no option can be set.

Before using options check section “■ Mask Options.”

Take particular care on the following point:

• A pull-up resistor can be set for P00 to P07, P10 to P17 and P20 to P27 only at single-chip mode.

4

MB89860/850 Series

■ PIN ASSIGNMENT

(Top view)

P31/SO1

P30/SCK1

P47/TRGI

P46/Z

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

V^CC

P32/SI1

P33/SCK2

P34/SO2

P35/SI2

P36/PTO1

P37/PTO2

V^SS

P45/Y

P44/X

P43/RTO3/W

P42/RTO2/V

P41/RTO1/U

P40/RTO0

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

9

P00/AD0

P01/AD1

P02/AD2

P03/AD3

P04/AD4

P05/AD5

P06/AD6

P07/AD7

P10/A08

P11/A09

P12/A10

P13/A11

P14/A12

P15/A13

P16/A14

P17/A15

P20/BUFC

P21/HAK

P22/HRQ

P23/RDY

P24/CLK

P25/WR

P26/RD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

AVR

AV^SS

P64/DTTI

P63/INT3/ADST

P62/INT2

P61/INT1

P60/INT0

RST

MOD0

MOD1

X0

X1

V^SS

P27/ALE

(DIP-64P-M01)

(DIP-64C-A06)

5

MB89860/850 Series

(Top view)

P82

P81

P80

P76

P75

P74

P73

P72

P71

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

N.C.

P40/RTO0

P41/RTO1/U

P42/RTO2/V

P43/RTO3/W

P44/X

V^SS

P45/Y

P46/Z

V^CC

P47/TRGI

P60/INT0

P61/INT1

P62/INT2

P63/INT3/ADST

P64/DTTI

P30/SCK1

P31/SO1

P32/SI1

P33/SCK2

P34/SO2

P35/SI2

P36/PTO1

P37/PTO2

9

P70

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MOD0

MOD1

X0

X1

V^SS

RST

P27/A L E

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

(FPT-80P-M06)

(FPT-80C-A02)

6

MB89860/850 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

X0

Function

SH-DIP^*1

QFP^*2

13

30

31

28

29

27

A

B

C

Crystal oscillator pins (10 MHz)

14

X1

11

MOD0

MOD1

RST

Operating mode selection pins

Connect directly to V^CCor VSS.

12

16

Reset I/O pin

This pin is an N-ch open-drain output type with a pull-up

resistor, and a hysteresis input type. “L” is output from this

pin by an internal reset source. The internal circuit is

initialized by the input of “L”.

56 to 49

48 to 41

40

40 to 33 P00 /AD0 to

P07/AD7

D

F

General-purpose I/O ports

When an external bus is used, these ports function as

multiplex pins of lower address output and data I/O.

32 to 25 P10 /A08 to

P17/A15

General-purpose I/O ports

When an external bus is used, these ports function as

upper address output.

24

23

P20/BUFC

P21/HAK

General-purpose output port

When an external bus is used, this port can also be used

as a buffer control output.

39

General-purpose output port

When an external bus is used, this port can also be used

as a hold acknowledge output.

38

37

36

35

34

33

2

22

21

20

19

18

17

48

P22/HRQ

P23/RDY

P24/CLK

P25/WR

P26/RD

D

F

E

General-purpose output port

When an external bus is used, this port can also be used

as a hold request input.

General-purpose output port

When an external bus is used, this port functions as a

ready input.

General-purpose output port

When an external bus is used, this port functions as a

clock output.

General-purpose output port

When an external bus is used, this port functions as a

write signal output.

General-purpose output port

When an external bus is used, this port functions as a

read signal output.

P27/ALE

P30/SCK1

General-purpose output port

When an external bus is used, this port functions as an

address latch signal output.

General-purpose I/O port

Also serves as the clock I/O for the UART.

This port is a hysteresis input type.

(Continued)

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-80P-M06, FPT-80C-A02

7

MB89860/850 Series

(Continued)

Pin no.

Circuit

Pin name

Function

General-purpose I/O port

type

SH-DIP^*1

QFP^*2

1

47

P31/SO1

E

Also serves as the data output for the UART.

This port is a hysteresis input type.

63

62

61

60

59

58

10

46

45

44

43

42

41

63

P32/SI1

E

General-purpose I/O port

Also serves as the data input for the UART.

This port is a hysteresis input type.

P33/SCK2

P34/SO2

P35/SI2

General-purpose I/O port

Also serves as the clock I/O for the 8-bit serial I/O.

This port is a hysteresis input type.

General-purpose I/O port

Also serves as the data output for the 8-bit serial I/O.

This port is a hysteresis input type.

General-purpose I/O port

Also serves as the data input for the 8-bit serial I/O.

This port is a hysteresis input type.

P36/PTO1

P37/PTO2

P40/RTO0

General-purpose I/O port

Also serves as the pulse output for the 8-bit PWM timer 1.

This port is a hysteresis input type.

General-purpose I/O port

Also serves as the pulse output for the 8-bit PWM timer 2.

This port is a hysteresis input type.

General-purpose I/O port

Also serves as the pulse output for the timer unit.

This port is a hystereisis input type.

9,

8,

7

62,

61,

60

P41/RTO1/U,

P42/RTO2/V,

P43/RTO3/W

General-purpose I/O ports

Also serve as the pulse output for the timer unit or a non-

overlap three-phase waveform output.

These ports are a hysteresis input type.

6,

5,

4

59,

57,

56

P44/X,

P45/Y,

P46/Z

E

General-purpose I/O ports

Also serve as a non-overlap three-phase output.

These ports are a hysteresis input type.

3

54

P47/TRGI

General-purpose I/O port

Also serves as the trigger input for the timer unit.

This port is a hysteresis input type.

11 to 18

26 to 24

69 to 76 P50/AN0 to

P57/AN7

H

I

N-ch open-drain output ports

Also serve as the analog input for the A/D converter.

53 to 51 P60/INT0 to

P62/INT2

General-purpose input ports

Also serve as an external interrupt input.

These ports are a hysteresis input type.

23

50

P63/INT3/

ADST

I

General-purpose input port

Also serves as an external interrupt input and as the

activation trigger input for the A/D converter.

This port is a hysteresis input type.

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-80P-M06, FPT-80C-A02

(Continued)

8

MB89860/850 Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

SH-DIP^*1

QFP^*2

22

49

P64/DTTI

I

General-purpose input port

Also serves as a dead-time timer disable input.

This port is a hysteresis input type.

DTTI input is with a noise canceller.

—

10 to 4

P70 to P76

G

N-ch open-drain I/O ports

These ports are a hysteresis input type.

3 to 1, 80, P80 to P87

68 to 65

N-ch open-drain I/O ports

These ports are a hysteresis input type.

64

32, 57

19

55

15, 58

77

V^CC

—

Power supply pin

V^SS

Power supply (GND) pins

AV^CC

AVR

AV^SS

A/D converter power supply pin

A/D converter reference voltage input pin

20

78

21

79

A/D converter power supply (GND) pin

Use this pin at the same voltage as V^SS.

—

64

N.C.

—

Internally connected pin

Be sure to leave it open.

*1: DIP-64P-M01, DIP-64C-A06

*2: FPT-80P-M06, FPT-80C-A02

9

MB89860/850 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• At an oscillation feedback resitor of approximately

1 MΩ/5.0 V

X1

X0

Standby control signal

B

C

• At an output pull-up resistor (P-ch) of approximately

50 kΩ/5.0 V

R

• Hysteresis input

P-ch

N-ch

D

• CMOS output

• CMOS input

R

P-ch

N-ch

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

E

• CMOS output

• Hysteresis input

R

P-ch

N-ch

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

(Continued)

10

MB89860/850 Series

(Continued)

Type

Circuit

Remarks

F

• CMOS output

R

P-ch

• Pull-up resistor optional (Mask ROM products)

N-ch

• At a pull-up resistor of approximately 50 kΩ/5.0 V

G

• N-ch open-drain output

• Hysteresis input

R

P-ch

N-ch

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

H

• N-ch open-drain output

• Analog input

P-ch

N-ch

Analog input

I

• Hysteresis input

• Pull-up resistor optional (Mask ROM products)

• At a pull-up resistor of approximately 50 kΩ/5.0 V

R

11

MB89860/850 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pin

Be sure to leave (internally connected) N.C. pin open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and

wake-up from stop mode.

12

MB89860/850 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P867/W867/P857/W857

The MB89P867/W867/P857/W857 are an OTPROM version of the MB89860/850 series.

1. Features

• 32-Kbyte PROM on chip

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in EPROM mode is diagrammed below.

Address

0000H

Single chip

I/O

EPROM mode

( Corresponding addresses on the EPROM programmer)

0080H

0480H

RAM

Not available

8000H

0000H

PROM

32 KB

EPROM

32 KB

FFFFH

7FFFH

3. Programming to the EPROM

In EPROM mode, the MB89P867/W867/P857/W857 functions equivalent to the MBM27C256A. This allows the

PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot

be used) by using the dedicated socket adapter.

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000^Hto 7FFFH (note that addresses 8000H to FFFFH

while operating as a single chip assign to addresses 0000H to 7FFFH in EPROM mode.)

(3) Program to 0000^Hto 7FFFH with the EPROM programmer.

13

MB89860/850 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. Erasure

In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an

ultraviolet light source. A dosage of 10 W-seconds/cm²is required to completely erase an internal EPROM. This

dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity

of 12000 µW/cm²for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all

filters should be removed from the UV light source prior to erasure.

It is important to note that the internal EPROM and similar devices, will erase with light sources having

wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,

nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and

exposure to them should be prevented to realize maximum system reliability. If used in such an environment,

the package windows should be covered by an opaque label or substance.

7. EPROM Programmer Socket Adapter

Package

DIP-64P-M01

FPT-80P-M01

Compatible socket adapter

ROM-64SD-28DP-8L*

ROM-80QF-28DP-8L2

* : Connect the adapter jumper pin to VSS when using.

Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760

14

MB89860/850 Series

■ BLOCK DIAGRAM

X0

X1

Time-base timer

Oscillator

Clock controller

P37/PTO2

P36/PTO1

8-bit PWM timer 2

8-bit PWM timer 1

Reset circuit

(WDT)

RST

P35/SI2

P34/SO2

P33/SCK2

8-bit serial I/O

UART

CMOS I/O port

8

P00/AD0

to P07/AD7

P32/SI1

P31/SO1

P30/SCK1

P10/A08

to P17/A15

MOD0

MOD1

External bus

interface

CMOS I/O port

P27/ALE

P26/RD

P47/TRGI

P46/Z

P45/Y

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

P44/X

P43/RTO3/W

P42/RTO2/V

P41/RTO1/U

P40/RTO0

6

Timer unit

CMOS output port

(Dead-time timer)

P64/DTTI

4

3

RAM

External interrupt

Input port

P60/INT0

to P62/INT2

F²MC-8L

CPU

P63/INT3/ADST

AVR

AV^CC

AVSS

ROM

8

Other pins

V^CC, VSS × 2

P50/AN0

to P57/AN7

10-bit A/D converter

N-ch open-drain output port

Part number

MB89865/855/T855*¹

MB89857/867

RAM size

512 bytes

1 Kbyte

ROM size

16 Kbytes

32 Kbytes

2

*

7

8

P70 to P76

P80 to P87

N-ch open-drain I/O port

Port 7 and port 8

32 Kbytes

(EPROM)

MB89W857/P867

1 Kbyte

*²: Not included in the MB89850 series.

*¹: In the MB89T855, an external ROM can be used.

15

MB89860/850 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89860/850 series offer a memory space of 64 Kbytes for storing all of I/O, data,

and program areas. The I/O area is located at the lowest address. The data area is provided immediately above

the I/O area. The data area can be divided into register, stack, and direct areas according to the application.

The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables

of interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89860/850 series is structured as illustrated below.

Memory Space

MB89867/857

MB89865

MB89855/T855*²

MB89W867/P867

MB89W857/P857

0000H

0080H

0000H

0080H

I/O

RAM

512 B

RAM

1 KB

0100^H

0100H

Register

0200H

0280H

0200H

0480H

External area

8000H

C000H

FFFF^H

1

*

ROM

1

*

32 KB

ROM

16 KB

FFFF H

*1: The ROM area is an external area depending on the mode.

*2: In the MB89T855, an external ROM can be used.

16

MB89860/850 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

Initial value

16 bits

PC

A

: Program counter

: Accumulator

FFFD^H

Undefined

T

: Temporary accumulator

: Index register

IX

EP

SP

PS

: Extra pointer

: Stack pointer

: Program status

I-flag = 0, IL1, 0 = 11

Other bits are undefined.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

17

MB89860/850 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared

otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0

when reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.

Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does

not occur.

C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.

Set to the shift-out value in the case of a shift instruction.

18

MB89860/850 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89860/850 series. The bank currently in use

is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

Register Bank Configuration

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

19

MB89860/850 Series

■ I/O MAP

Address

00^H

Read/write

(R/W)

(W)

Register name

PDR0

Register description

Port 0 data register

01^H

DDR0

Port 0 data direction register

Port 1 data register

02^H

(R/W)

(W)

PDR1

03H

DDR1

Port 1 data direction register

Port 2 data register

04^H

(R/W)

(W)

PDR2

05^H

BCTR

External bus pin control register

Vacancy

06H

07^H

Vacancy

08H

(R/W)

(W)

STBC

WDTC

TBTC

Standby control register

Watchdog timer control register

Time-base timer control register

Vacancy

09^H

0AH

0BH

0C^H

0DH

0EH

0F^H

10H

(R/W)

(W)

PDR3

DDR3

PDR4

DDR4

PDR5

Port 3 data register

Port 3 data direction register

Port 4 data register

(R/W)

(W)

Port 4 data direction register

Port 5 data register

(R/W)

11^H

Vacancy

12H

(R)

PDR6

PDR7

PDR8

Port 6 data register

13H

Vacancy

14^H

(R/W)

Port 7 data register

15H

Vacancy

16H

Port 8 data register

17^Hto 1BH

1C^H

1DH

1EH

1F^H

20H

Vacancy

(R/W)

(W)

CTR1

CMR1

CTR2

CMR2

SMC

PWM control register 1

PWM compare register 1

PWM control register 2

PWM compare register 2

UART serial mode control register

UART serial rate control register

UART serial status/data register

UART serial data register

Serial mode register

Serial data register

(R/W)

(W)

(R/W)

21H

SRC

22^H

SSD

23H

SIDR/SODR

SMR

24H

25^H

SDR

(Continued)

20

MB89860/850 Series

(Continued)

Address

Read/write

(R/W)

(R)

Register name

EIC1

Register description

External interrupt control register 1

External interrupt control register 2

A/D converter control register 1

A/D converter control register 2

A/D converter data register (H)

A/D converter data register (L)

Vacancy

26^H

27H

EIC2

28^H

ADC1

29^H

ADC2

2AH

2B^H

2C^H

2DH

2E^H

2FH

30^H

ADDH

(R)

ADDL

(W)

ZOCTR

CLRBRH

CLRBRL

TCSR

Zero detection output control register

Compare clear buffer register (H)

Compare clear buffer register (L)

Timer control status register

Compare interrupt control register

Timer mode control register

(W)

(R/W)

(W)

31H

CICR

32H

TMCR

33^H

COER

Compare/port selection register

Compare buffer mode control register

Dead-time timer control register

Dead-time setting register

34H

CMCR

35H

DTCR

36^H

DTSR

37H

(R/W)

(W)

OCTBR

OCPBR0H

OCPBR0L

OCPBR1H

OCPBR1L

OCPBR2H

OCPBR2L

OCPBR3H

OCPBR3L

Output control buffer register

Output compare buffer register 0 (H)

Output compare buffer register 0 (L)

Output compare buffer register 1 (H)

Output compare buffer register 1 (L)

Output compare buffer register 2 (H)

Output compare buffer register 2 (L)

Output compare buffer register 3 (H)

Output compare buffer register 3 (L)

Vacancy

38^H

39H

(W)

3AH

3B^H

3CH

3DH

3E^H

3F^H

40H to 7BH

7CH

7D^H

7EH

7FH

(W)

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

Notes: • Do not use vacancies.

• When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register

containing a write-only bit, a bit designated by the instruction will have a predetermined value. However,

a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access

to the register should be tried with any read-modefy-write instruction.

21

MB89860/850 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

Value

Parameter

Symbol

V^CC

Unit

Remarks

Min.

Max.

Power supply voltage

VSS – 0.3

V^SS– 0.3

VSS – 0.3

VSS + 7.0

V

*

AVCC

A/D converter reference input

voltage

AVR must not exceed AV^CC+

0.3 V.

AVR

VSS + 7.0

13.0

MOD1 pins of MB89P867/

W867 and MB89P857/W857

Program voltage

V^PP

Input voltage

V^I

VSS – 0.3

—

VCC + 0.3

VSS + 0.3

20

V

Output voltage

VO

“L” level maximum output current IOL

mA

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P50 to P57, P70 to P76,

P80 to P87

I^OLAV1

—

4

mA

“L” level average output current

I^OLAV2

15

30

mA P40 to P47

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P50 to P57, P70 to P76,

P80 to P87

ΣI^OLAV1

mA

“L” level total average output

current

ΣI^OLAV2

“H” level maximum output current IOH

—

50

–20

–4

mA P40 to P47

mA

“H” level average output current

I^OHAV

“H” level total maximum output

current

ΣI^OH

—

–20

mA

Power consumption

Operating temperature

Storage temperature

P^D

—

300

+85

mW

°C

T^A

–40

–55

Tstg

+150

°C

*: Use AV^CCand VCC set at the same voltage.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to the conditions as detailed in the operational sections of

this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

22

MB89860/850 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

Normal operation assurance

range*

2.7*

6.0*

V

MB89867/865, MB89857/855

Normal operation assurance

range*

MB89P867/W867,

MB89P857/W855/T855

V^CC

AVCC

Power supply voltage

2.7*

1.5

5.5*

6.0

V

Retains the RAM state in stop

mode

A/D converter reference input

voltage

AVR

T^A

0.0

AV^CC

+85

V

Operating temperature

–40

°C

*: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1

and “5. A/D Converter Electrical Characteristics.”

Note: Connect the MOD0 and MOD1 pins to V^CCor VSS.

6

5.5

Analog accuracy assured in the

VCC = AVCC = 3.5 V to 6.0 V range

5

Operation assurance range

4

3

2

1

2

3

4

5

6

7

8

9

10

Clock operating frequency (MHz)

(µs)

4.0 2.0

0.8

0.4

Minimum execution time (instruction cycle)

Note: The shaded area is assured only for the MB89865/867/855/857.

Figure 1 Operating Voltage vs. Clock Operating Frequency

23

MB89860/850 Series

3. DC Characteristics

(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

V^IH

Condition

Unit Remarks

Min.

Typ.

Max.

V^CC+

0.3

P00 to P07, P10 to P17,

P22, P23

—

0.7 VCC

—

V

“H” level input

voltage

RST, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87

V^CC+

0.3

V^IHS

V^IL

0.8 VCC

—

V^SS–

0.3

P00 to P07, P10 to P17,

P22, P23

0.3 V^CC

0.2 V^CC

—

“L” level input

voltage

RST, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87

V^SS–

0.3

V^ILS

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47

“H” level output

voltage

IOH = –2.0

mA

V^OH

2.4

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P50 to P57, P70 to P76,

P80 to P87

V^OL1

V^OL2

IOL = 1.8 mA

IOL = 15 mA

—

0.4

1.5

V

“L” level output

voltage

P40 to P47

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87,

MOD0, MOD1

Input leackage

current

0.0 V < VI <

VCC

I^LI1

—

±5

µA

With pull-

kΩ

Pull-up resistance R^PULL

RST

VI = 0.0 V

25

50

100

up resistor

FC = 10 MHz

Normal

operation

mode

I^CC

—

15

18

mA

(External

clock)

VCC

FC = 10 MHz

Sleep mode

(External

clock)

Power supply

current

I^CCS

I^CCH

I^A

—

6

—

6

8

mA

µA

mA

pF

Stop mode

TA = +25°C

10

—

FC = 10 MHz,

when A/D

conversion is

activated

AVCC

Other than AVCC,

AVSS, VCC, and VSS

Input capacitance C^IN

f = 1 MHz

10

24

MB89860/850 Series

4. AC Characteristics

(1) Reset Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min.

Max.

RST “L” pulse width

tZLZH

—

16 tXCYL*

—

ns

* : t^XCYLis the oscillation cycle (1/FC) to input to the X0 pin.

t ZLZH

RST

0.2 VCC

(2) Power-on Reset

(AV^SS= VSS = 0.0 V, TA = –40°C to +85°C)

Value

Max.

Parameter

Symbol

t^R

Condition

Unit

Remarks

Min.

—

Power supply rising time

Power supply cut-off time

50

—

ms Power-on reset function only

ms Due to repeated operations

—

tOFF

1

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

tOFF

t^R

2.0 V

0.2 V

V

CC

25

MB89860/850 Series

(3) Clock Timing

(AV^SS= VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Clock frequency

Symbol

F^C

Condition

Unit

Remarks

Min.

1

Max.

10

MHz

ns

X0, X1

Clock cycle time

t^XCYL

100

1000

P^WH

PWL

—

Input clock pulse width

20

—

ns External clock

X0

t^CR

tCF

Input clock rising/falling time

10

X0 and X1 Timing Conditions

tXCYL

PWH

PWL

tCR

tCF

0.8 VCC

X0

0.2 VCC

Clock Conditions

When a crystal

or

When an external clock is used

ceramic resonator is used

X0

X1

X0

X1

Open

(4) Instruction Cycle

Parameter

Symbol

Value (typical)

Unit

µs

Remarks

Instruction cycle

(minimum execution time)

t^inst= 0.4 µs when operating at

FC = 10 MHz

t^inst

4/FC

26

MB89860/850 Series

(5) Recommended Resonator Manufacturers

Sample Application of Piezoelectric Resonator (FAR Series)

X0

X1

*

FAR

C1

C2

*: Fujitsu Acoustic Resonator

C1 = C2 = 20 pF±8 pF (built-in FAR)

Temperature characteristics

FAR part number

(built-in capacitor type)

Initial deviation of

FAR frequency (T^A= +25°C)

Frequency

of FAR frequency

(T^A= –25°C to +60°C)

FAR-C4CB-08000-M02

FAR-C4CB-10000-M02

8.00 MHz

±0.5%

10.00 MHz

Inquiry: FUJITSU LIMITED

27

MB89860/850 Series

Sample Application of Ceramic Resonator

X0

X1

*

C1

C2

Resonator manufacturer*

Kyocera Corporation

Resonator

KBR-7.68MWS

KBR-8.0MWS

CSA8.00MTZ

Frequency

7.68 MHz

8.0 MHz

R (kΩ)

—

C1 (pF)

33

C2 (pF)

33

—

Murata Mfg. Co., Ltd.

8.0 MHz

30

—

Inquiry: Kyocera Corporation

• AVX Corporation

North American Sales Headquarters: TEL 1-803-448-9411

• AVX Limited

European Sales Headquarters: TEL 44-1252-770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters: TEL 852-363-3303

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL 1-404-436-1300

• Murata Europe Management GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

28

MB89860/850 Series

(6) Clock Output Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Cycle time

CLK ↑ → CLK ↓

Symbol

t^CYC

t^CHCL

Condition

Unit

Remarks

Min.

Max.

t^XCYL× 2 at 10 MHz

oscillation

200

—

ns

Load

condition:

50 pF

CLK

Approx. t^CYC/2 at

10 MHz oscillation

30

100

t CYC

t CHCL

2.4 V

CLK

0.8 V

29

MB89860/850 Series

(7) Bus Read Timing

(V^CC= +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value (10 MHz)

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

—

Valid address → RD ↓

RD, A15 to A08,

AD7 to AD0

1/4 t^inst* – 64 ns

1/2 t^inst* – 20 ns

—

t^AVRL

tRLRH

t^AVDV

ns

time

RD pulse width

RD

—

ns

Valid address → data

read time

AD7 to AD0,

A15 to A08

1/2 t^inst*

ns No wait

RD, AD7 to AD0

AD7 to AD0, RD

RD, ALE

1/2 t^inst* – 80 ns

RD ↓ → data read time tRLDV

RD ↑ → data hold time tRHDX

—

ns No wait

0

—

ns

Load

condition:

50 pF

1/4 t^inst* – 40 ns

1/4 t^inst* – 60 ns

0

RD ↑ → ALE ↑ time

RD ↑ → address invalid time

RD ↓ → CLK ↑ time

CLK ↓ → RD ↑ time

RD ↓ → BUFC ↓ time

tRHLH

tRHAX

tRLCH

tCLRH

tRLBL

RD, A15 to A08

RD, CLK

RD, BUFC

–5

A15 to A08,

AD7 to AD0,

BUFC

BUFC ↑ → valid

address time

t^BHAV

5

—

ns

* : For information on t^inst, see “(4) Instruction Cycle.”

2.4 V

CLK

0.8 V

tRHLH

ALE

0.8 V

0.7 V^CC

2.4 V

0.7 VCC

0.3 VCC

2.4 V

0.8 V

AD

0.8 V

0.3 VCC

tAVDV

t^RHDX

2.4 V

tCLRH

0.8 V

2.4 V

A

tRLCH

0.8 V

tAVRL

tRLDV

tRHAX

tRLRH

2.4 V

RD

0.8 V

tRLBL

tBHAV

2.4 V

BUFC

0.8 V

30

MB89860/850 Series

(8) Bus Write Timing

(V^CC= +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value (10 MHz)

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

Valid address → ALE ↓ time

tAVLL

tLLAX

1/4 t ^*1– 64 ns

inst

—

ns

AD7 to AD0,

ALE, A15 to

A08

ALE ↓ time → address

invalid time

5

—

Valid address → WR↓ time

1/4 t^inst*1– 60 ns

1/2 t^inst*1– 20 ns

inst

tAVWL

WR, ALE

—

ns

WR pulse width

tWLWH

WR

Write data → WR ↑ time tDVWH

1/2 t ^*1– 60 ns

AD7 to AD0, WR

WR, A15 to A08

AD7 to AD0, WR

WR, ALE

Load

condition:

50 pF

WR ↑ → address invalid time

tWHAX

1/4 t^inst*1– 40 ns

1/4 t^inst*1– 60 ns

0

WR ↑ → data hold time tWHDX

WR ↑ → ALE ↑ time

WR ↓ → CLK ↑ time

CLK ↓ → WR ↑ time

ALE pulse width

tWHLH

tWLCH

tCLWH

t^LHLL

WR, CLK

t^XCYL– 35 ns^*2

ALE

ALE ↓ → CLK ↑ time

t^LLCH

ALE, CLK

*1: For information on t^inst, see “(4) Instruction Cycle.”

*2: These characteristics are also applicable to the bus read timing.

2.4 V

CLK

0.8 V

tLHLL

tLLCH

t WHLH

2.4 V

ALE

AD

A

0.8 V

tAVLL

tLLAX

2.4 V

0.8 V

2.4 V 2.4 V

0.8 V 0.8 V

2.4 V

0.8 V

tDVWH

tWHDX

2.4 V

tCLWH

2.4 V

0.8 V

tWLCH

0.8 V

tAVWL

tWHAX

tWLWH

2.4 V

WR

0.8 V

31

MB89860/850 Series

(9) Ready Input Timing

(V^CC= +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

—

RDY valid → CLK ↑ time

CLK ↑ → RDY invalid time

t^YVCH

t^CHYX

60

0

ns

*

RDY,

CLK

Load condition:

50 pF

—

* : These characteristics are also applicable to the read cycle.

2.4 V

CLK

ALE

AD

A

Address

Data

WR

t ^YVCHt CHYX

0.7 VCC

RDY

0.3 V^CC

0.3 VCC

t YVCH t CHYX

Note: The bus cycle is also extended in the read cycle in the same manner.

32

MB89860/850 Series

(10) UART and Serial I/O Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

Serial clock cycle time

t^SCYC

t^SLOV

SCK1,SCK2

2 tinst*

—

µs

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

SCK1, SO1

SCK2, SO2

Internal shift

clock mode

Load

condition:

50 pF

–200

200

—

ns

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑

SI1, SCK1

SI2, SCK2

t^IVSH

1/2 t^inst*

µs

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

tSHIX

—

Serial clock “H” pulse width

Serial clock “L” pulse width

tSHSL

tSLSH

1 t^inst*

—

µs

SCK1, SCK2

1 tinst*

External shift

clock mode

Load

condition:

50 pF

SCK1 ↓ → SO1 time

SCK2 ↓ → SO2 time

SCK1, SO1

SCK2, SO2

t^SLOV

t^IVSH

tSHIX

0

200

—

ns

µs

Valid SI1 → SCK1 ↑

Valid SI2 → SCK2 ↑

SI1, SCK1

SI2, SCK2

1/2 t^inst*

SCK1, SI1

SCK2, SI2

SCK1 ↑ → valid SI1 hold time

SCK2 ↑ → valid SI2 hold time

—

* : For information on t^inst, see “(4) Instruction Cycle.”

33

MB89860/850 Series

Internal Shift Clock Mode

t^SCYC

SCK1

SCK2

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

External Shift Clock Mode

t SLSH

t SHSL

SCK1

SCK2

0.8 VCC

0.2 VCC

t SLOV

2.4 V

0.8 V

SO1

SO2

tIVSH

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

SI1

SI2

34

MB89860/850 Series

(11) Peripheral Input Timing

(V^CC= +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Condition

Unit Remarks

Min.

Max.

Peripheral input “H”

pulse width 1

t^ILIH1

t^IHIL1

2 t^inst*

—

µs

TRGI, DTTI,

ADST,

INT0 to INT3

Load

condition:

50 pF

Peripheral input “L”

pulse width 1

2 tinst*

—

* : For information on t^inst, see “(4) Instruction Cycle.”

TRGI

DTTI

tIHIL1

tILIH1

ADST

INT0 to INT3

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

5. A/D Converter Electrical Characteristics

(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Resolution

Symbol

Condition

Unit Remarks

Min.

—

Typ.

—

Max.

10

bit

Linearity error

—

±2.0

±1.5

±3.0

LSB

—

Differential linearity error

Total error

—

AV^CC= VCC

AVSS –

1.5

AVSS +

0.5

AVSS +

2.5

Zero transition voltage

V^OT

LSB

AN0 to

AN7

AVR –

3.5

AVR –

1.5

AVR +

0.5

Full-scale transition voltage V^FST

Interchannel disparity

—

0

—

33 t^inst*

—

4

LSB

µs

µA

V

—

A/D mode conversion time

Analog port input current

Analog input voltage

—

I^AIN

10

AN0 to

AN7

—

AVR

AV^CC

—

Reference voltage

0

—

V

AVR

Reference voltage supply

current

AVR = 5.0

V

I^R

—

200

—

µA

* : For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

35

MB89860/850 Series

(1) A/D Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

• Linearity error

The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1111” ↔´“11 1111 1110”) from actual conversion characteristics

• Differential linearity error

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error

The total error indicates the difference between the actual value and theoretical value. This error is caused by

the zero transition error, full-scale transition error, linearity error, quantization, and noise.

Theoretical I/O value

V^FST

Total error

3FF

3FE

3FD

3FF

3FE

3FD

Actual conversion

value

1.5 LSB

(1 LSB × N + 0.5 LSB)

004

003

002

001

004

003

002

001

VNT

VOT

Actual conversion

value

1 LSB

Theoretical value

0.5 LSB

AV^SS

AVR

AV^SS

AVR

Analog input

VFST – VOT

VNT – (1 LSB × N + 0.5 LSB)

1 LSB =

(V)

Total error of digital output “N” =

1022

1 LSB

(Continued)

36

MB89860/850 Series

(Continued)

Zero transition error

Full-scale transition error

Theoretical value

004

003

002

001

Actual conversion

value

3FF

3FE

3FD

3FC

Actual conversion

value

VFST

(Measured value)

Actual conversion

value

Actual conversion

value

VOT (Measured value)

Analog input

AV^SS

AVR

Analog input

Linearity error

Differential linearity error

Theoretical value

3FF

3FE

3FD

Actual conversion

value

N+1

N

(1 LSB

× N + VOT)

Actual conversion

value

V(N + 1)T

VFST

(Measured

value)

VNT

004

003

002

001

N – 1

N – 2

VNT

Actual conversion

value

Actual conversion

value

Theoretical value

VOT (Measured value)

Analog input

AV^SS

AVR

Analog input

V^NT– (1 LSB × N + VOT)

V(N + 1)T – VNT

Linearity error of digital output “N” =

Differential linearity error of digital output “N” =

– 1

1 LSB

37

MB89860/850 Series

(2) Precautions

• Input impedance of the analog input pins

The A/D converter used for the MB89860/850 series contains a sample hold circuit as illustrated below to

fetch analog input voltage into the sample hold capacitor for fifteen instruction cycles after activation A/D

conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance connot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

Analog Input Equivalent Circuit

Sample hold circuit

.

C = 64 pF

.

Anlog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

.

R = 3 kΩ

.

Close for 15 instruction cycles

after activating A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

38

MB89860/850 Series

■ EXAMPLE CHARACTERISTICS

(1) “L” Level Output Voltage (P00 to P07, P10 to

P17, P20 to P27, P30 to P37, P50 to P57, P70 to

P76, and P80 to P87)

(2) “L” Level Output Voltage (P40 to P47)

VOL vs. IOL

V^OL(V)

VOL (mV)

600

T^A= +25˚C

TA = +25˚C

0.5

500

V^CC= 3.0 V

0.4

400

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

300

0.3

V^CC= 5.0 V

V^CC= 6.0 V

200

0.2

100

0.1

0

0 1 2 3 4 5 6 7 8 9 1011121314151617181920

I^OL(mA)

0

1

2

3

4

5

6

7

8

9

10

I^OL(mA)

(4) Pull-up Resistance

(3) “H” Level Output Voltage (P00 to P07, P10 to

P17, P20 to P27, P30 to P37, and P40 to P47)

RPULL vs. VCC

VCC − VOH vs. IOH

R^PULL(kΩ)

1000

V^CC− VOH (V)

1.0

TA = +25˚C

0.9

0.8

0.7

V^CC= 3.0 V

0.6

0.5

100

V^CC= 4.0 V

V^CC= 5.0 V

0.4

0.3

0.2

0.1

0.0

V^CC= 6.0 V

10 to 1

0.0

−0.5

−1.0

−1.5

−2.0

−2.5

−3.0

I^OH(mA)

1

2

3

4

5

6

V^CC(V)

39

MB89860/850 Series

(5) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(6) “H” Level Input Voltage/“L” level Input

Voltage (Hysteresis Input)

VIN vs. VCC

V^IN(V)

5.0

V^IN(V)

5.0

TA = +25˚C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4.0

3.5

V^IHS

3.0

2.5

VILS

2.0

1.5

1.0

0.5

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

V^CC(V)

VIHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

V^ILS: Threshold when input voltage in hysteresis

characteristics is set to “L” level

(7) Operating Supply Current vs. Frequency

(8) Operating Supply Current vs. V^CC

ICC vs. F

C

ICC vs. VCC

I^CC(mA)

25

ICC (mA)

25

TA = +25˚C

F^C= 10 MHz

20

15

10

5

20

FC = 8 MHz

V^CC= 5.0 V

15

10

5

F^C= 6 MHz

F^C= 4 MHz

V^CC= 3.5 V

V^CC= 3.0 V

0

2

4

6

8

10

F^C(MHz)

3.0 3.5 4.0 4.5 5.0 5.5 6.0

V^CC(V)

40

MB89860/850 Series

(9) Sleep Power Supply Current vs. Frequency

(10) Sleep Power Supply Current vs. V^CC

ICCS vs. VCC

ICCS vs. FC

I^CCS(mA)

10

ICCS (mA)

10

TA = +25˚C

8

F^C= 10 MHz

FC = 8 MHz

6

V^CC= 5.0 V

FC = 6 MHz

4

2

0

F^C= 4 MHz

V^CC= 3.5 V

2

V^CC= 3.0 V

0

2

4

6

8

10

F^C(MHz)

3.0 3.5 4.0 4.5 5.0 5.5 6.0

V^CC(V)

41

MB89860/850 Series

■ INSTRUCTIONS

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

#vct

#d8

#d16

dir: b

rel

@

Register indirect (Example: @A, @IX, @EP)

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

T

TH

TL

IX

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

(Continued)

42

MB89860/850 Series

(Continued)

Symbol

Meaning

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

CCR

RP

Ri

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

Number of instructions

Number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH immediately before the instruction

is executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

43

MB89860/850 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

44

MB89860/850 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

+ + + +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

dH + + + +

–

+ + + +

22

38 to 3F

34

35

36

37

33

dH + + + +

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

32

C8 to CF

C3

C2

C0

D8 toDF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

dH + + R –

–

+ + + +

+ + – +

(TL) − (AL)

(T) − (A)

13

03

→

C

A

←

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

45

MB89860/850 Series

(Continued)

Mnemonic

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) +off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

46

MB89860/850 Series

■ INSTRUCTION MAP

47

MB89860/850 Series

■ MASK OPTIONS (MB89855/857/865/867)

Option type

Power-on reset

Option selection

Remarks

0: Without power-on reset

1: With power-on reset

—

Selects the initial value of the OSCS bit

in the STBC register during power-on

reset.

Initial value of oscillation

stabilization delay time

0: 2¹⁸/FC (s) (Crystal oscillator)

1: 2¹⁴/FC (s) (Ceramic oscillator)

0: Without reset output

1: With reset output

Reset pin output

—

• Can be set per pin.

• P70 to P76, and P80 to P87 are used

in the MB89860 series only.

• P00 to P07, P10 to P17, and P20 to

P27 with a pull-up resistor can be set

only for single-chip mode.

Pull-up resistor at port pin

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P47, P60 to P64,

P70 to P76, P80 to P87

1: Without pull-up resistor

0: With pull-up resistor

■ STANDARD OPTION LIST

Part number

Parameter

MB89P857/W857/

P867/W867/T855

Power-on reset

Available

2¹⁸/FC (s)

Initial value of oscillation

stabilization delay time

Output at reset pin

Available

Pull-up resistor at port pin

Not available

■ ORDERING INFORMATION

Part number

Package

Remarks

MB89865PF

MB89867PF

MB89P867PF

80-pin Plastic QFP

(FPT-80P-M06)

MB89855P-SH

MB89T855P-SH

MB89857P-SH

MB89P857P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

80-pin Ceramic QFP

(FPT-80C-A02)

MB89W867CF

ES level only

64-pin Ceramic SH-DIP

(DIP-64C-A06)

MB89W857C-SH

48

MB89860/850 Series

■ PACKAGE DIMENSIONS

80-pin Plastic QFP

(FPT-80P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

0.05(.002)MIN

(STAND OFF)

64

41

65

40

12.00(.472)

REF

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

16.30±0.40

(.642±.016)

INDEX

80

25

"A"

1

24

LEAD No.

0.80(.0315)TYP

0.35±0.10

(.014±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.16(.006)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.58(.023)MAX

18.40(.724)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

1994 FUJITSU LIMITED F80010S-3C-2

Dimensions in mm (inches)

64-pin Plastic SH-DIP

(DIP-64P-M01)

58.00⁺^–0⁰^.^.⁵²⁵²

+.008

2.283–.022

INDEX-1

17.00±0.25

(.669±.010)

INDEX-2

5.65(.222)MAX

3.00(.118)MIN

0.25±0.05

(.010±.002)

1.00⁺^–0^0.50

.039⁺^–0^.020

0.45±0.10

(.018±.004)

0.51(.020)MIN

19.05(.750)

TYP

15°MAX

1.778±0.18

(.070±.007)

1.778(.070)

MAX

55.118(2.170)REF

C

1994 FUJITSU LIMITED D64001S-3C-4

Dimensions in mm (inches)

49

MB89860/850 Series

80-pin Ceramic QFP

(FPT-80P-A02)

0.51(.020) TYP

17.91(.705)

TYP

12.00(.472)

REF

16.31(.642)

TYP

8.50(.335)TYP

16.00(.630)

14.00±0.25

(.551±.010)

TYP

INDEX AREA

0.80±0.10

0.35–⁺0⁰.^.0⁰7⁸

0.80±0.10

0.15±0.05

(.0315±.0040)

(.014±.003)

(.0315±.0040)

(.006±.002)

18.40(.725) REF

1.60(.063) TYP

20.00±0.25

(.787±.010)

4.45(.175)MAX

23.90(.941) TYP

22.00(.866) TYP

22.30(.878) TYP

0.80(.0315) TYP

C

1994 FUJITSU LIMITED F80014SC-1-2

Dimensions in mm (inches)

64-pin Ceramic SH-DIP

(DIP-64C-A06)

56.90±0.56

(2.240±.022)

8.89(.350) DIA

TYP

R1.27(.050)

REF

18.75±0.25

(.738±.010)

INDEX AREA

1.27±0.25

(.050±.010)

5.84(.230)MAX

0.25±0.05

(.010±.004)

3.40±0.36

(.134±.014)

+0.13

1.778±0.180

(.070±.007)

0.90±0.10

(.0355±.0040)

0.46^–0.08

19.05±0.25

.018⁺^–.^.⁰⁰⁰⁰³⁵

(.750±.010)

0°~9°

1.45(.057)

MAX

55.118(2.170)REF

C

1994 FUJITSU LIMITED D64006SC-1-2

Dimensions in mm (inches)

50

MB89860/850 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 1015, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211, Japan

Tel: (044) 754-3753

Fax: (044) 754-3329

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Circuit diagrams utilizing Fujitsu products are included as a

means of illustrating typical semiconductor applications. Com-

plete information sufficient for construction purposes is not nec-

essarily given.

Tel: (06103) 690-0

Fax: (06103) 690-122

The information contained in this document has been carefully

checked and is believed to be reliable. However, Fujitsu as-

sumes no responsibility for inaccuracies.

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED

No. 51 Bras Basah Road,

Plaza By The Park,

The information contained in this document does not convey

any license under the copyrights, patent rights or trademarks

claimed and owned by Fujitsu.

#06-04 to #06-07

Singapore 189554

Tel: 336-1600

Fujitsu reserves the right to change products or specifications

without notice.

Fax: 336-1609

No part of this publication may be copied or reproduced in any

form or by any means, or transferred to any third party without

prior written consent of Fujitsu.

The information contained in this document are not intended for

use with equipments which require extremely high reliability

such as aerospace equipments, undersea repeaters, nuclear con-

trol systems or medical equipments for life support.

F9606

FUJITSU LIMITED Printed in Japan

51


型号：	MB89W867
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总51页 (文件大小：689K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89W867 [FUJITSU]

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