MB90335_技术文档

FUJITSU MICROELECTRONICS

DATA SHEET

DS07-13735-2Ea

16-bit Microcontroller

CMOS

F²MC-16LX MB90335 Series

MB90337/F337/V330A

■ DESCRIPTION

The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral

devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but

also Mini-HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices

such as displays and audio devices, and control of mobile devices that support USB communications. While

inheriting the AT architecture of the F²MC* family, the instruction set supports the C language and extended

addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial

collection of improved bit manipulation instructions. In addition, long word processing is now available by intro-

ducing a 32-bit accumulator.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

• Clock

• Built-in oscillation circuit and PLL clock frequency multiplication circuit

• Oscillation clock

• The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)

• Clock for USB is 48 MHz

• Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable

• Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock

24 MHz and at operating V^CC= 3.3 V)

• The maximum memory space:16 Mbytes

• 24-bit addressing

• Bank addressing

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://edevice.fujitsu.com/micom/en-support/

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

2007.10

MB90335 Series

(Continued)

• Instruction system

• Data types: Bit, Byte, Word, Long word

• Addressing mode (23 types)

• Enhanced high-precision computing with 32-bit accumulator

• Enhanced Multiply/Divide instructions with sign and the RETI instruction

• Instruction system compatible with high-level language (C language) and multi-task

• Employing system stack pointer

• Instruction set symmetry and barrel shift instructions

• Program Patch Function (2 address pointer)

• 4-byte instruction queue

• Interrupt function

• Priority levels are programmable

• 20 interrupts function

• Data transfer function

• Extended intelligent I/O service function (EI²OS) : Maximum of 16 channels

• µDMAC : Maximum 16 channels

• Low Power Consumption Mode

• Sleep mode (with the CPU operating clock stopped)

• Time-base timer mode (with the oscillator clock and time-base timer operating)

• Stop mode (with the oscillator clock stopped)

• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)

• Package

• LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch)

• Process : CMOS technology

• Operation guaranteed temperature: −40 °C to +85 °C (0 °C to +70 °C when USB is in use)

2

MB90335 Series

■ INTERNAL PERIPHERAL FUNCTION (RESOURCE)

• I/O port : Max 45 ports

• Time-base timer : 1channel

• Watchdog timer : 1 channel

• 16-bit reload timer : 1 channel

• Multi-functional timer

• 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse can be

set by the program.

• 16-bit PWC timer : 1 channel

Timer function and pulse width measurement function

• UART : 2 channels

• Equipped with Full duplex double buffer with 8-bit length

• Asynchronous transfer or clock-synchronous serial (extended I/O serial) transfer can be set.

• Extended I/O serial interface : 1 channel

• DTP/External interrupt circuit (8 channels)

• Activate the extended intelligent I/O service by external interrupt input

• Interrupt output by external interrupt input

• Delayed interrupt output module

• Output an interrupt request for task switching

• USB : 1 channel

• USB function (conform to USB 2.0 Full Speed)

• Full Speed is supported/Endpoint are specifiable up to six.

• Dual port RAM (The FIFO mode is supported).

• Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible

• USB Mini-HOST function

• I²C* Interface : 1 channel

• Supports Intel SM bus standards and Phillips I²C bus standards

• Two-wire data transfer protocol specification

• Master and slave transmission/reception

* : I²C license :

Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use,

these components in an I²C system provided that the system conforms to the I²C Standard Specification as

defined by Phillips.

3

MB90335 Series

■ PRODUCT LINEUP

Part number

Type

MB90V330A

For evaluation

No

MB90F337

MB90337

Built-in Flash Memory

Built-in MASK ROM

ROM capacity

RAM capacity

64 Kbytes

28 Kbytes

4 Kbytes

Emulator-specific

power supply *

Used bit

⎯

Number of basic instructions : 351 instructions

Minimum instruction

execution time

Addressing type

: 41.6 ns / at oscillation of 6 MHz

(When 4 times are used : Machine clock of 24 MHz)

: 23 types

CPU functions

Program Patch Function

Maximum memory space

: For 2 address pointers

: 16 Mbytes

Ports

I/O Ports(CMOS) 45 ports

Equipped with full-duplex double buffer

Clock synchronous or asynchronous operation selectable.

It can also be used for I/O serial.

UART

Built-in special baud-rate generator

Built-in 2 channels

16-bit reload timer operation

Built-in 1 channel

16-bit reload timer

8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels)

16-bit PWC timer × 1 channel

Multi-functional timer

8 channels

DTP/External interrupt

I²C

Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable

1 channel

Extended I/O serial interface 1 channel

1 channel

USB

USB function (conform to USB 2.0 Full Speed)

USB Mini-HOST function

Withstand voltage of 5 V

8 ports (Excluding UTEST and I/O for I²C)

Low Power Consumption

Mode

Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode

Process

CMOS

Operating voltage V^CC

3.3 V 0.3 V (at maximum machine clock 24 MHz)

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to

the MB2147-01orMB2147-20hardwaremanual (3.3Emulator-dedicatedPowerSupplySwitching)aboutdetails.

■ PACKAGES AND PRODUCT MODELS

Package

FPT-64P-M09 (LQFP-0.65 mm)

PGA-299C-A01 (PGA)

MB90337

MB90F337

MB90V330A

: Yes

: No

4

MB90335 Series

■ PIN ASSIGNMENT

(TOP VIEW)

UTEST

Vss

1

2

3

4

5

6

7

8

9

48 Vss

47 X1

DVM

DVP

Vcc

46 X0

45 P24/PPG0

44 P23

43 P22

42 P21

41 P20

40 P17

39 P16

38 P15

37 P14

36 P13

35 P12

34 P11

33 P10

Vss

HVM

HVP

Vcc

HCON 10

P42/SIN0 11

P43/SOT0 12

P44/SCK0 13

P45/SIN1 14

P46/SOT1 15

P47/SCK1 16

(FPT-64P-M09)

5

MB90335 Series

■ PIN DESCRIPTION

I/O

Circuit

type*

Status at

reset/

function

Pin no.

Pin name

Function

It is a terminal which connects the oscillator.

When connecting an external clock, leave the X1 pin side

unconnected.

Oscillation

status

46 , 47

23

X0, X1

RST

A

F

Reset input External reset input pin.

General purpose input/output port.

The ports can be set to be added with a pull-up resistor

(RD00 to RD07 = 1) by the pull-up resistor setting register

(RDR0). (When the power output is set, it is invalid.)

25 to 32

33 to 40

P00 to P07

P10 to P17

I

General purpose input/output port.

The ports can be set to be added with a pull-up resistor

(RD10 to RD17 = 1) by the pull-up resistor setting register

(RDR1). (When the power output is set, it is invalid.)

41 to 44

45

P20 to P23

P24

D

General purpose input/output port.

PPG0

P25 to P27

PPG1 to PPG3

P40

Functions as output pins of PPG timers ch.0.

General purpose input/output port.

51 to 53

62

D

H

Functions as output pins of PPG timers ch.1 to ch.3.

General purpose input/output port.

TIN0

Function as event input pin of 16-bit reload timer.

General purpose input/output port.

P41

63

TOT0

P42

Function as output pin of 16-bit reload timer.

General purpose input/output port.

Port input

(Hi-Z)

11

SIN0

Functions as a data input pin for UART ch.0.

General purpose input/output port.

P43

12

SOT0

P44

Functions as a data output pin for UART ch.0.

General purpose input/output port.

13

SCK0

P45

Functions as a clock I/O pin for UART ch.0.

General purpose input/output port.

14

SIN1

Functions as a data input pin for UART ch.1.

General purpose input/output port.

P46

15

SOT1

P47

Functions as a data output pin for UART ch.1.

General purpose input/output port.

16

SCK1

P50

Functions as a clock I/O pin for UART ch.1.

General purpose input/output port.

50

64

K

P51

General purpose input/output port.

17, 18

24

P52, P53

P54

General purpose input/output port.

(Continued)

6

MB90335 Series

(Continued)

I/O

Pin name Circuit

type*

Status at

reset/

function

Pin no.

Function

P60, P61

C

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.0 and ch.1.

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.2.

Data input pin for extended I/O serial interface.

54, 55

56

INT0, INT1

P62

INT2

SIN

C

P63

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.3.

Data output pin for extended I/O serial interface.

57

58

59

INT3

SOT

P64

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.4.

Clock I/O pin for extended I/O serial interface.

INT4

SCK

P65

Port input

(Hi-Z)

General purpose input/output port (withstand voltage of 5 V) .

Functions as the input pin for external interrupt ch.5.

Functions as the PWC input pin.

INT5

PWC

P66

General purpose input/output port (withstand voltage of 5 V) .

INT6

Functions as the input pin for external interrupt ch.6.

60

C

Functions as the input/output pin for I²C interface clock. The port

output must be placed in Hi-Z state during I²C interface

operation.

SCL0

P67

General purpose input/output port (withstand voltage of 5 V) .

INT7

Functions as the input pin for external interrupt ch.7.

Functions as the I²C interface data input/output pin. The port out-

put must be placed in Hi-Z state during I²C interface operation.

61

1

C

SDA0

UTEST

input

USB test pin.

UTEST

Connect this to a pull-down resistor during normal usage.

3

4

DVM

DVP

HVM

HVP

HCON

MD1, MD0

MD2

Vcc

J

USB function D − pin.

USB function D + pin.

USB Mini-HOST D − pin.

USB Mini-HOST D + pin.

USB input

(SUSPEND)

7

J

8

J

10

21, 22

20

5

E

High output External pull-up resistor connection pin.

B

Mode input Input pin for selecting operation mode.

G

⎯

Power supply pin.

9

Vcc

49

2

Vcc

Power

supply

Vss

Power supply pin (GND).

6

Vss

Power supply pin (GND).

19

48

Vss

* : For circuit information, refer to “■ I/O CIRCUIT TYPE”.

7

MB90335 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistor of

approx. 1 MΩ

• With standby control

X1

X0

Clock input

A

Standby control signal

CMOS hysteresis input

B

C

CMOS hysteresis

input

• CMOS hysteresis input

• N-ch open drain output

N-ch

Nout

CMOS hysteresis input

Standby control signal

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

P-ch

N-ch

Pout

Nout

Notes : • Share one output buffer because

both output of I/O port and

internal resource are used.

• Share one input buffer because

both input of I/O port and internal

resource are used.

D

CMOS hysteresis input

Standby control signal

CMOS output

P-ch

N-ch

Pout

Nout

E

CMOS hysteresis input with pull-up

resistor

R

F

CMOS hysteresis

input

• CMOS hysteresis input with pull-down

resistor of approx. 50 kΩ

• Flash product is not provided with pull-

CMOS hysteresis

input

G

R

down resistor.

(Continued)

8

MB90335 Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Open drain control

signal

P-ch

N-ch

Pout

Nout

With open drain control signal

H

CMOS hysteresis input

Standby control signal

• CMOS output

• CMOS input

CTL

R

(With input interception function at

standby)

• Programmable input pull-up resistor

P-ch

N-ch

Pout

I

Nout

CMOS input

Standby control signal

D + input

USB I/O pin

D - input

+

D

Differential input

−

D

Full D + output

J

Full D - output

Low D + output

Low D - output

Direction

Speed

• CMOS output

• CMOS input

(With input interception function at

standby)

P-ch

N-ch

Pout

Nout

K

CMOS input

Standby control signal

9

MB90335 Series

■ HANDLING DEVICES

1. Preventing latch-up and turning on power supply

latch-up may occur on CMOS IC under the following conditions:

• If a voltage higher than V^CCor lower than VSS is applied to input and output pins.

• A voltage higher than the rated voltage is applied between V^CCand VSS.

When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When

using CMOS IC, take great care to prevent the occurrence of latch-up.

2. Treatment of unused pins

Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent dam-

age. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused

input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused

input pins. If there is unused output pin, make it to open.

3. About the attention when the external clock is used

Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or

when recovering from sub-clock or stop mode. When suing an external clock, 25 MHz should be the upper

frequency limit.

The following figure shows a sample use of external clock signals.

• Using external clock

X0

OPEN

X1

4. Treatment of power supply pins (VCC/VSS)

In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand VSS pins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between V^CCand VSS pins

near this device.

5. About crystal oscillator circuit

Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that

X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to

the device as possible.

It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane

because stable operation can be expected with such a layout.

Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.

6. Caution on Operations during PLL Clock Mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while

the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its

self-running frequency. However, Fujitsu Microelectronics will not guarantee results of operations if such failure

occurs.

10

MB90335 Series

7. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage

operating range. For stabilization reference, the supply voltage should be stabilized so that V^CCripple variations

(peak-to-peak value) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard V^CCsupply

voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply

switching.

8. Writing to flash memory

For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.

For normal writing to flash memory, always make sure that the operating voltage V^CCis between 3.0 V and 3.6 V.

11

MB90335 Series

■ BLOCK DIAGRAM

X0, X1

RST

MD0 to MD2

F²MC-16LX

CPU

Clock control

circuit

Interrupt

controller

8/16-bit PPG

timer

ch.0 to ch.3*

PPG0 to PPG3

PWC

RAM

ROM

16-bit PWC

SIN0, SIN1

SOT0, SOT1

SCK0, SCK1

UART/SIO

ch.0, ch.1

SIN

SOT

SCK

SIO

SCL0

SDA0

I²C

µDMAC

16-bit reload

timer

TOT0

TIN0

DVP

DVM

HVP

HVM

HCON

UTEST

USB

(Function)

(Mini-HOST)

External interrupt

INT0 to INT7

I/O port (port 0, 1, 2, 4, 5, 6)

P00

P07

P10

P17

P20

P27

P40

P47

P50

P54

P60

P67

* : Channel for use in 8-bit mode. 2 channels (ch.1, ch.3) are used in 16-bit mode.

Note : I/O ports share pins with peripheral function (resources) .

For details, refer to “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.

Note also that pins used for peripheral function (resources) cannot serve as I/O ports.

12

MB90335 Series

■ MEMORY MAP

Single chip mode (with ROM mirror function)

MB90V330A

MB90F337

MB90337

FFFFFFH

FF0000H

FFFFFFH

FF0000H

FFFFFFH

ROM (FF bank)

FF0000H

00FFFFH

ROM area

(image of FF bank)

ROM area

(image of FF bank)

ROM area

(image of FF bank)

008000H

007FFFH

008000H

007FFFH

008000H

007FFFH

Peripheral area

007900H

007100H

RAM area

(28 Kbytes)

001100H

RAM area

(4 Kbytes)

RAM area

(4 Kbytes)

Register

000100H

0000FBH

000100H

0000FBH

000100H

0000FBH

Peripheral area

000000H

Notes : • When the ROM mirror function register has been set, the mirror image data at upper addresses (“FF8000H

to FFFFFF^H” ) of bank FF is visible from the upper addresses (“008000H to 00FFFFH”) of bank 00.

• The ROM mirror function is effective for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in

bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be

reproduced in bank 00.

• When the C compiler small model is used, the data table mirror image can be shown at “008000^Hto

00FFFF^H” by storing the data table at “FF8000H to FFFFFFH”.

Therefore, data tables in the ROM area can be referred without declaring the far addressing with

the pointer.

13

MB90335 Series

■ F²MC-16L CPU PROGRAMMING MODEL

• Dedicated register

AH

AL

Accumulator

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

DPR

Direct page register

PCB

DTB

USB

SSB

ADB

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

8-bit

16-bit

32-bit

• General purpose registers

MSB

LSB

16-bit

000180^H+ RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

R1

R0

R2

R4

R6

RW4

RW5

RW6

RW7

RL2

RL3

R3

R5

R7

• Processor status

Bit 15

PS

13 12

ILM

8 7

0

RP

CCR

14

MB90335 Series

■ I/O MAP

Register

abbreviation

Read/

Write

Address

Register

Port 0 Data Register

Resource name

Initial Value

000000^H

000001H

000002H

000003H

000004^H

000005H

000006H

PDR0

R/W

Port 0

Port 1

Port 2

XXXXXXXXB

PDR1

Port 1 Data Register

Port 2 Data Register

PDR2

Prohibited

PDR4

PDR5

PDR6

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

R/W

Port 4

Port 5

Port 6

XXXXXXXXB

- - - XXXXXB

XXXXXXXXB

000007H

to

00000F^H

000010^H

000011H

000012H

000013H

000014^H

000015H

000016H

DDR0

DDR1

DDR2

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

R/W

Port 0

Port 1

Port 2

0 0 0 0 0 0 0 0B

DDR4

DDR5

DDR6

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

R/W

Port 4

Port 5

Port 6

0 0 0 0 0 0 0 0B

- - - 0 0 0 0 0B

0 0 0 0 0 0 0 0B

000017H

to

00001A^H

Port 4 (Open-drain

control)

00001B^H

ODR4

Port 4 Output Pin Register

R/W

0 0 0 0 0 0 0 0B

00001CH

00001DH

00001EH

00001F^H

000020H

000021H

RDR0

RDR1

Port 0 Pull-up Resistance Register

Port 1 Pull-up Resistance Register

R/W

Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B

Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B

Prohibited

SMR0

SCR0

Serial Mode Register 0

R/W

R

0 0 1 0 0 0 0 0B

0 0 0 0 0 1 0 0B

Serial Control Register 0

SIDR0

SODR0

SSR0

Serial Input Data Register 0

Serial Output Data Register 0

Serial Status Register 0

UART0

000022H

XXXXXXXX^B

W

000023^H

000024H

000025H

000026H

000027H

R/W

R

0 0 0 0 1 0 0 0B

UTRLR0

UTCR0

SMR1

SCR1

UART Prescaler Reload Register 0

UART Prescaler Control Register 0

Serial Mode Register 1

0 0 0 0 0 0 0 0B

0 0 0 0 - 0 0 0B

0 0 1 0 0 0 0 0B

0 0 0 0 0 1 0 0B

Communication

Prescaler(UART0)

Serial Control Register 1

SIDR1

SODR1

SSR1

Serial Input Data Register 1

Serial Output Data Register 1

Serial Status Register 1

UART1

000028H

000029^H

XXXXXXXX^B

W

R/W

0 0 0 0 1 0 0 0B

(Continued)

15

MB90335 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

00002A^H

00002BH

UTRLR1

UTCR1

UART Prescaler Reload Register 1

UART Prescaler Control Register 1

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 - 0 0 0B

Communication

Prescaler(UART1)

00002CH

to

Prohibited

00003B^H

00003C^H

00003DH

00003EH

00003FH

ENIR

EIRR

DTP/Interrupt Enable Register

R/W

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

DTP/Interrupt source Register

DTP/External

interrupt

Request Level Setting Register Lower

Request Level Setting Register Upper

ELVR

000040H

to

Prohibited

000045^H

000046^H

000047H

000048H

000049H

00004AH

00004B^H

00004CH

00004DH

00004E^H

PPGC0

PPGC1

PPGC2

PPGC3

PPG0 Operation Mode Control Register R/W

PPG1 Operation Mode Control Register R/W

PPG2 Operation Mode Control Register R/W

PPG3 Operation Mode Control Register R/W

PPG ch.0

PPG ch.1

PPG ch.2

PPG ch.3

0X0 0 0XX1B

0X0 0 0 0 0 1B

0X0 0 0XX1B

0X0 0 0 0 0 1B

Prohibited

PPG01

PPG23

PPG0 and PPG1 Output Control Register R/W

Prohibited

PPG ch.0/ch.1

0 0 0 0 0 0XXB

PPG2 and PPG3 Output Control Register R/W

PPG ch.2/ch.3 0 0 0 0 0 0 XXB

00004FH

to

Prohibited

000057^H

000058^H

000059H

00005AH

XXXX0 0 0 0^B

SMCS

Serial Mode Control Status Register

Serial Data Register

R/W

Extended Serial

0 0 0 0 0 0 1 0B

I/O

SDR

R/W

XXXXXXXXB

Communication Prescaler Control

Register

Communication

0XXX0 0 0 0B

Prescaler

00005BH

SDCR

00005CH

00005DH

00005EH

00005FH

000060H

000061H

000062^H

000063H

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 XB

PWCSR

PWC Control Status Register

R/W

16-bit

PWC Timer

0 0 0 0 0 0 0 0^B

PWCR

DIVR

PWC Data Buffer Register

R/W

0 0 0 0 0 0 0 0B

- - - - - - 0 0B

PWC Dividing Ratio Control Register

Prohibited

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0B

TMCSR0

Timer Control Status Register

R/W

TMR0

TMRLR0

TMR0

16-bit Timer Register Lower

16-bit Reload Register Lower

16-bit Timer Register Upper

16-bit Reload Register Upper

R

W

R

XXXXXXXXB

(Continued)

16-bit Reload

Timer

000064H

000065H

TMRLR0

W

16

MB90335 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name Initial Value

000066^H

to

Prohibited

00006E^H

ROM Mirror

Function

Selection Module

ROM Mirroring Function Selection

Register

00006F^H

ROMM

W

- - - - - - 1 1^B

000070H

000071H

000072H

000073H

000074H

IBSR0

IBCR0

ICCR0

IADR0

IDAR0

I²C Bus Status Register

I²C Bus Control Register

I²C Bus Clock Control Register

I²C Bus Address Register

I²C Bus Data Register

R

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

R/W

R/W I²C Bus Interface XX 0 XXXXXB

R/W

XXXXXXXXB

000075H

to

Prohibited

00009A^H

DMA Descriptor Channel Specification

Register

00009B^H

DCSR

R/W

0 0 0 0 0 0 0 0B

µDMAC

00009CH

00009DH

DSRL

DSRH

DMA Status Register Lower

DMA Status Register Upper

R/W

0 0 0 0 0 0 0 0B

Program Address Detection Control

Status Register

Address Match

Detection

00009EH

00009FH

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0B

Delayed Interrupt Source generate/

release Register

R/W Delayed Interrupt - - - - - - - 0B

Low Power

Low Power Consumption Mode Control

Register

0000A0H

LPMCR

CKSCR

R/W

Consumption

control circuit

0 0 0 1 1 0 0 0^B

1 1 1 1 1 1 0 0B

0000A1H

0000A2H

0000A3^H

0000A4H

Clock Selection Register

Prohibited

Clock

DSSR

DMA Stop Status Register

R/W

µDMAC

0 0 0 0 0 0 0 0B

0000A5H

to

Prohibited

0000A7^H

0000A8^H

0000A9H

0000AAH

0000AB^H

0000ACH

0000ADH

0000AEH

0000AFH

WDTC

TBTC

Watchdog Timer Control Register

Time-base Timer Control Register

R/W Watchdog Timer X - XXX 1 1 1B

R/W Time-base Timer 1 - - 0 0 1 0 0B

Prohibited

DERL

DERH

FMCS

DMA Enable Register Lower

DMA Enable Register Upper

Flash Memory Control Status Register

Prohibited

R/W

0 0 0 0 0 0 0 0B

µDMAC

R/W Flash Memory I/F 0 0 0 X 0 0 0 0B

(Continued)

17

MB90335 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

0000C0H

0000C1H

0000C2H

0000C3H

0000C4H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

HCNT0

HCNT1

HIRQ

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

Host Control Register 0

R/W

0 0 0 0 0 1 1 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 1 1B

XX 0 1 0 0 1 0B

Interrupt

Controller

Host Control Register 1

Host Interruption Register

Host Error Status Register

Host State Status Register

HERR

HSTATE

SOF Interrupt FRAME Compare Reg-

ister

0000C5H

HFCOMP

R/W

0 0 0 0 0 0 0 0B

0000C6H

0000C7H

0000C8H

0000C9H

0000CAH

0000CBH

0000CCH

0000CDH

0000CEH

0000CFH

0000D0^H

0000D1H

R/W

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

XXXXXX 0 0B

X 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

XX 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

XXXXX 0 0 0B

0 0 0 0 0 0 0 0B

USB Mini-HOST

HRTIMER

Retry Timer Setting Register

HADR

HEOF

Host Address Register

EOF Setting Register

HFRAME

HTOKEN

FRAME Setting Register

Host Token End Point Register

Prohibited

R/W

1 0 1 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

(Continued)

UDCC

UDC Control Register

USB Function

18

MB90335 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

0000D2^H

0000D3H

0000D4H

0000D5H

0000D6H

0000D7H

0000D8H

0000D9H

0000DAH

0000DBH

0000DCH

0000DDH

0000DEH

0000DFH

0000E0H

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

0000E6H

0000E7H

0000E8H

0000E9H

0000EAH

0000EBH

0000ECH

0000EDH

0000EEH

0000EFH

0000F0H

0000F1H

0000F2H

0000F3H

0000F4H

0000F5H

0000F6H

0000F7H

0000F8H

0000F9H

R/W

R

0 1 0 0 0 0 0 0^B

XXXX 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 1 1 0 0 0 0 1B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

XXXXX0 0 0B

XX0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 XXX 1 XXB

0 XXXXXXX^B

1 0 0 XX 0 0 0B

XXXXXXXX^B

1 0 0 0 0 0 0 XB

XXXXXXXX^B

1 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 0 0 0 0 0 0B

XXXXXXXXB

1 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 0 0 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

(Continued)

EP0C

EP1C

EP2C

EP3C

EP4C

EP5C

TMSP

EP0 Control Register

EP1 Control Register

EP2 Control Register

EP3 Control Register

EP4 Control Register

EP5 Control Register

Time Stamp Register

R

UDCS

UDCIE

UDC Status Register

R/W

R/W, R

R/W

R

UDC Interrupt Enable Register

EP0IS

EP0OS

EP1S

EP0I Status Register

EP0O Status Register

EP1 Status Register

EP2 Status Register

EP3 Status Register

EP4 Status Register

EP5 Status Register

EP0 Data Register

EP1 Data Register

EP2 Data Register

EP3 Data Register

EP4 Data Register

USB Function

R/W

R

EP2S

R/W

R

EP3S

R/W

R

EP4S

R/W

R

EP5S

R/W

EP0DT

EP1DT

EP2DT

EP3DT

EP4DT

19

MB90335 Series

Register

Address

Read/

Write

Register

EP5 Data Register

Resource name

Initial Value

abbreviation

0000FA^H

R/W

XXXXXXXX^B

XXXXXXXXB

EP5DT

USB Function

0000FBH

0000FCH

to

0000FF^H

Prohibited

RAM Area

000100^H

to

001100^H

Program Address Detection Register

ch.0 Lower

001FF0^H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

R/W

XXXXXXXX^B

Program Address Detection Register

ch.0 Middle

PADR0

PADR1

Program Address Detection Register

ch.0 Upper

Address Match

Detection

Program Address Detection Register

ch.1 Lower

Program Address Detection Register

ch.1 Middle

Program Address Detection Register

ch.1 Upper

007900H

007901H

007902H

007903H

007904H

007905H

007906H

007907H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PPG Reload Register Lower ch.0

PPG Reload Register Upper ch.0

PPG Reload Register Lower ch.1

PPG Reload Register Upper ch.1

PPG Reload Register Lower ch.2

PPG Reload Register Upper ch.2

PPG Reload Register Lower ch.3

PPG Reload Register Upper ch.3

R/W

XXXXXXXXB

PPG ch.0

PPG ch.1

PPG ch.2

PPG ch.3

007908H

to

Prohibited

00790B^H

Flash Memory Program Control

Register 0

00790C^H

FWR0

R/W

Flash

0 0 0 0 0 0 0 0B

Flash Memory Program Control

Register 1

00790DH

00790EH

FWR1

SSR0

R/W

Flash

0 0 0 0 0 0 0 0B

0 0 XXXXX0B

Sector Conversion Setting Register

00790FH

to

Prohibited

00791F^H

(Continued)

20

MB90335 Series

(Continued)

Register

abbreviation

Read/

Write

Address

Register

Resource name Initial Value

007920^H

007921H

007922H

007923H

DBAPL

DBAPM

DBAPH

DMACS

DMA Buffer Address Pointer Lower 8-bit R/W

DMA Buffer Address Pointer Middle 8-bit R/W

DMA Buffer Address Pointer Upper 8-bit R/W

XXXXXXXXB

DMA Control Register

R/W

DMA I/O Register Address Pointer Lower

8-bit

µDMAC

007924H

007925H

DIOAL

DIOAH

R/W

XXXXXXXX^B

DMA I/O Register Address Pointer

Upper 8-bit

R/W

007926H

007927H

DDCTL

DDCTH

DMA Data Counter Lower 8-bit

DMA Data Counter Upper 8-bit

R/W

XXXXXXXXB

007928H

to

Prohibited

007FFF^H

• Explanation on read/write

R/W : Readable and Writable

R

: Read only

: Write only

W

• Explanation of initial values

0

1

X

-

: Initial value is “0”.

: Initial value is “1”.

: Initial value is undefined.

: Initial value is undefined (None).

Note : No I/O instruction can be used for registers located between 007900^Hand 007FFFH.

21

MB90335 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt control

EI²OS

support

Interrupt vector

register

Interrupt source

µDMAC

Priority

Number*¹

Address

08H FFFFDCH

ICR Address

Reset

×

#08

#09

#10

#11

⎯

High

INT 9 instruction

09^HFFFFD8H

0A^HFFFFD4H

0B^HFFFFD0H

0CH FFFFCCH

0DH FFFFC8H

0EH FFFFC4H

0FH FFFFC0H

10H FFFFBCH

Exceptional treatment

×

USB Function1

0, 1

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

ICR06 0000B6H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

ICR13 0000BDH

USB Function2

2 to 6*²#12

USB Function3

×

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

USB Function4

USB Mini-HOST1

×

USB Mini-HOST2

I²C ch.0

×

11H

12H

13H

FFFFB8H

FFFFB4H

FFFFB0H

DTP/External interrupt ch.0/ch.1

×

No

⎯

×

DTP/External interrupt ch.2/ch.3

14H FFFFACH

No

⎯

×

15H

16H

17H

FFFFA8H

FFFFA4H

FFFFA0H

DTP/External interrupt ch.4/ch.5

PWC/Reload timer ch.0

14

×

DTP/External interrupt ch.6/ch.7

18H FFFF9CH

No

⎯

×

⎯

×

19H

1AH

1BH

FFFF98H

FFFF94H

FFFF90H

No

1CH FFFF8CH

1DH FFFF88H

No

PPG ch.0/ch.1

1EH

1FH

FFFF84H

FFFF80H

No

⎯

×

⎯

×

PPG ch.2/ch.3

20H FFFF7CH

No

⎯

13

9

21H

22H

23H

FFFF78H

FFFF74H

FFFF70H

No

24H FFFF6CH

UART (Send completed) ch.0/ch.1

Extended serial I/O

25H

26H

FFFF68H

FFFF64H

×

UART(Reception completed)

ch.0/ch.1

12

#39

27^H

FFFF60H

ICR14 0000BEH

ICR15 0000BFH

Time-base timer

×

#40

#41

#42

28H FFFF5CH

Flash memory status

Delay interrupt output module

29H

2AH

FFFF58H

FFFF54H

Low

(Continued)

22

MB90335 Series

(Continued)

: Available. EI²OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.

With a stop request).

: Available (The interrupt request flag is cleared by the interrupt clear signal).

: Available when any interrupt source sharing ICR is not used.

× : Unavailable

*1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has

priority.

*2 : Ch.2 and ch.3 can be used in Mini-HOST operation.

Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI²OS is permitted,

the EI²OS is activated when either of the factors is detected. As any interrupt other than the activation

factor is masked while the EI²OS is running, it is recommended that you should mask either of the interrupt

requests when using the EI²OS.

• The interrupt flag is cleared by the EI²OS interrupt clear signal for the resource that has two interrupt

factors in the same interrupt control register (ICR).

• Ifaresourcehastwointerruptsourcesforthesameinterruptnumber, bothoftheinterruptrequestflags are

cleared by the µDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the

DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “ 0 ” in the

appropriate resource, and take measures by software polling.

■ Content of USB Interruption Factor

USB interrupt factor

USB function 1

Details

End Point0-IN, EndPoint 0-OUT

USB function 2

End Point 1-5 *

USB function 3

SUSP, SOF, BRST, WKOP, COHF

SPIT

USB function 4

USB Mini-HOST1

USB Mini-HOST2

DIRQ, CHHIRQ, URIRQ, RWKIRQ

SOFIRQ, CMPIRQ

* : End Point 1and 2 can be used in Mini-HOST operation.

23

MB90335 Series

■ PERIPHERAL RESOURCES

1. I/O port

The I/O ports are used as general-purpose input/output ports (parallel I/O ports). MB90335 series model is

provided with 6 ports (45 inputs) . The ports function as input/output pins for peripheral functions also.

An I/O port, using port data register (PDR) , outputs the output data to I/O pin and input a signal input to I/O

port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.

The following table lists the I/O ports and the peripheral functions with which they share pins.

Port pin name Pin Name (Peripheral)

Peripheral Function that Shares Pin

Port 0

Port 1

P00 to P07

P10 to P17

P20 to P23

P24 to P27

P40, P41

⎯

Port 2

PPG0 to PPG3

TIN0, TOT0

8/16-bit PPG timer 0, 1

16-bit reload timer

Port 4

Port 5

SIN0, SOT0, SCK0,

SIN1, SOT1, SCK1

P42 to P47

UART0, 1

P50 to P54

P60, P61

⎯

INT0, INT1

External interrupt

INT2 to INT4,

SIN, SOT, SCK

P62 to P64

External interrupt, serial I/O

External interrupt, PWC

Port 6

P65

INT5, PWC

P66, P67

INT6, INT7, SCL0, SDA0 External interrupt, I²C

24

MB90335 Series

• Register list (port data register)

PDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 000000^H

XXXXXXXXB R/W*

P07

P06

P05

P04

P03

P02

P01

P00

PDR1

15

14

13

12

11

10

9

8

Address : 000001^H

P17

P16

P15

P14

P13

P12

P11

P10

PDR2

7

6

5

4

3

2

1

0

Address : 000002^H

P27

P26

P25

P24

P23

P22

P21

P20

PDR4

7

6

5

4

3

2

1

0

Address : 000004^H

P47

P46

P45

P44

P43

P42

P41

P40

PDR5

15

14

13

12

11

10

9

8

Address : 000005^H

- - - XXXXXB

R/W*

⎯

P54

P53

P52

P51

P50

PDR6

7

6

5

4

3

2

1

0

Address : 000006^H

XXXXXXXXB R/W*

P67

P66

P65

P64

P63

P62

P61

P60

* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows:

• Input mode

Read : The level at the relevant pin is read.

Write : Data is written to the output latch.

• Output mode

Read : The data register latch value is read.

Write : Data is output to the relevant pin.

25

MB90335 Series

• Register list (port direction register)

DDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 000010^H

00000000B

- - - 00000B

00000000B

R/W

D07

D06

D05

D04

D03

D02

D01

D 00

DDR1

15

14

13

12

11

10

9

8

Address : 000011^H

D17

D16

D15

D14

D13

D12

D11

D10

DDR2

7

6

5

4

3

2

1

0

Address : 000012^H

D27

D26

D25

D24

D23

D22

D21

D20

DDR4

7

6

5

4

3

2

1

0

Address : 000014^H

D47

D46

D45

D44

D43

D42

D41

D40

DDR5

15

14

13

12

11

10

9

8

Address : 000015^H

⎯

D54

D53

D52

D51

D50

DDR6

7

6

5

4

3

2

1

0

Address : 000016^H

D67

D66

D65

D64

D63

D62

D61

D60

•

When each pin is serving as a port, the corresponding pin is controlled as follows:

0 : Input mode

1 : Output mode

This bit becomes 0 after a reset.

Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits

manipulated by the instruction are set to prescribed values but those other bits in output registers which

have been set for input are rewritten to current input values of the pins. When switching a pin from input port

to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output.

• Register list (Port pull-up register)

RDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001CH

00000000B

R/W

RD07

RD06

RD05

RD04

RD03

RD02

RD01

RD00

RDR1

15

14

13

12

11

10

9

8

Address : 00001D^H

00000000B

R/W

RD17

RD16

RD15

RD14

RD13

RD12

RD11

RD10

Controls the pull-up resistor in input mode.

0 : Without pull-up resistor in input mode.

1 : With Pull-up resistor in input mode.

Meaningless in output mode (without pull-up resistor) ./ The input/output register is decided by the setting of the

direction register (DDR) .

No pull-up resistor is used in stop mode (SPL = 1).

26

MB90335 Series

• Register list (output pin register)

ODR4

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001B^H

00000000B

R/W

OD47

OD46

OD45

OD44

OD43

OD42

OD41

OD40

Controls open-drain output in output mode.

0 : Serves as a standard output port in output mode.

1 : Serves as an open-drain output port in output mode.

Meaningless in input mode. (output Hi-Z) / The input/output register is decided by the setting of the direction

register (DDR) .

• Block diagram of port 0 pin and port1 pin

Pull-up resistor

setting register

(RDRx)

Built-in pull-up

resistor

PDRx read

Input

buffer

Port data

register

(PDRx)

I/O

decision circuit

Port

Output

buffer

PDRx

Write

Port direction

register

Standby control (LPMCR : SPL = “1”)

(DDRx)

• Block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin

Resource input

PDRx read

Input

buffer

Port data

I/O

register

decision circuit

(PDRx)

Port

Output

buffer

PDRx

write

Port direction

register

(DDRx)

Standby control (LPMCR : SPL = “1”)

Resource output control signal

Resource output

27

MB90335 Series

2. Time-base timer

The time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization

with the main clock (2 cycles of the oscillation clock HCLK). Four different time intervals can be selected, for

each of which an interrupt request can be generated. Operating clock signals are supplied to peripheral resources

such as the oscillation stabilization wait timer and watchdog timer.

• Interval time of time-base timer

Internal count clock cycle

Interval time

2¹²/HCLK (Approx. 0.68 ms)

2¹⁴/HCLK (Approx. 2.7 ms)

2¹⁶/HCLK (Approx. 10.9 ms)

2¹⁹/HCLK (Approx. 87.4 ms)

2/HCLK (0.33 µs)

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

• Clock cycles supplied from time-base timer

Where to supply clock

Clock cycle

2¹³/HCLK (Approx. 1.36 ms)

2¹⁵/HCLK (Approx. 5.46 ms)

2¹⁷/HCLK (Approx. 21.84 ms)

2¹²/HCLK (Approx. 0.68 ms)

2¹⁴/HCLK (Approx. 2.7 ms)

2¹⁶/HCLK (Approx. 10.9 ms)

2¹⁹/HCLK (Approx. 87.4 ms)

Main clock oscillation

stabilization wait

Watch dog timer

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

• Register list

Time-base timer control register (TBTC)

Initial Value

1--00100B

15

14

13

12

11

10

9

8

Address : 0000A9^H

RESV

⎯

TBIE

TBOF

TBR

TBC1

TBC0

( R/W )

( ⎯ )

( R/W ) ( R/W )

( W )

( R/W ) ( R/W )

28

MB90335 Series

• Block Diagram

To

watchdog

timer

To PPG timer

Time-base timer counter

Dividing HCLK by 2

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

OF

Power-on reset

To clock controller

oscillation stabilizing

wait time selector

Stop mode start

Counter

clear control

circuit

Interval timer selector

CKSCR : MCS = 1→0*

TBOF

set

TBOF clear

Time-base timer control register (TBTC)

Time-base timer interrupt signal

RESV

⎯

TBIE TBOF TBR TBC1 TBC0

⎯

: Unused

OF : Overflow

HCLK : Oscillation clock

*

: Switching the machine clock from main clock to PLL clock

Actual interrupt request number of time-base timer is as follows:

Interrupt request number:#40 (28^H)

29

MB90335 Series

3. Watchdog timer

The watchdog timer is timer counter provided for measure of program runaway. It is a 2-bit counter operating

with an output of the timebase timer or watch timer as the count clock and resets the CPU when the counter is

not cleared for a preset period of time after start.

• Interval time of watchdog timer

HCLK: Oscillation clock (6 MHz)

Min

Max

Clock cycle

Approx. 2.39 ms

Approx. 9.56 ms

Approx. 38.23 ms

Approx. 305.83 ms

Approx. 3.07 ms

Approx. 12.29 ms

Approx. 49.15 ms

Approx. 393.22 ms

2¹⁴2¹¹/ HCLK

2¹⁶2¹³/ HCLK

2¹⁸2¹⁵/ HCLK

2²¹2¹⁸/ HCLK

Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.

• The watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer.

• Interval time of watchdog timer is longer than the set time during the following conditions.

- When clearing the timebase timer during operation on oscillation (HCLK)

• Event that stop the watchdog timer

• Stop due to a power-on reset

• Watchdog reset

• Clear factor of watchdog timer

• External reset input by RST pin

• Writing “0” to the software reset bit

• Writing “0” to the watchdog control bit (second and subsequent times)

• Transition to sleep mode (clearing the watchdog timer to suspend counting)

• Transition to time-base timer mode (clearing the watchdog timer to suspend counting)

• Transition to stop mode (clearing the watchdog timer to suspend counting)

• Register list

Watchdog timer control register (WDTC)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000A8^H

X-XXX111B

⎯

PONR

WRST

ERST

SRST

WTE

WT1

WT0

( R )

( ⎯ )

( R )

( W )

30

MB90335 Series

• Block Diagram

Watchdog timer control register (WDTC)

PONR

⎯

WRST ERST SRST WTE WT1 WT0

2

Time-base timer mode start

Sleep mode start

Watchdog timer

CLR and

start

CLR

To

internal

reset

generation

circuit

Watchdog timer

reset

Counter

clear control

circuit

2-bit

counter

Count clock

selector

generation

circuit

Stop mode start

CLR

4

Clear

Time-base timer counter

× 2¹× 2²× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

Dividing HCLK by 2

HCLK: Oscillation clock

31

MB90335 Series

4. 16-bit reload timer

The 16-bit reload timer has the internal clock mode to be decrement in synchronization with 3 different internal

clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the

external pin. Either can be selected. This timer defines when the count value changes from 0000^Hto FFFFH as

an underflow. The timer therefore causes an underflow when the count reaches [reload register setting +1].

Either mode can be selected for the count operation from the reload mode which repeats the count by reloading

the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow

occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC.

• Register list

• Timer control status register

Timer control status register (Upper) (TMCSR0)

Initial Value

15

14

13

12

11

10

9

8

Address : 000063^H

XXXX0000B

⎯

CSL1

CSL0

MOD2 MOD1

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

Timer control status register (Lower) (TMCSR0)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 000062^H

MOD0 OUTE OUTL

RELD

INTE

UF

CNTE

TRG

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

• 16-bit timer register/16-bit reload register

TMR0/TMRLR0 (Upper)

Initial Value

15

14

13

12

11

10

9

8

Address : 000065^H

XXXXXXXXB

D15

D14

D13

D12

D11

D10

D09

D08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

TMR0/TMRLR0 (Lower)

Address : 000064^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

D07

D06

D05

D04

D03

D02

D01

D00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

32

MB90335 Series

• Block Diagram

Internal data bus

TMRLR0

16-bit reload register

Reload

Reload signal

control circuit

TMR0

*2

UF

16-bit timer register

CLK

Count clock generation circuit

Gate

input

Valid

clock

decision

circuit

3

Wait signal

Machine

clock φ

Prescaler

Clear

Trigger

Internal

clock

Output control circuit

CLK

Output signal

generation

circuit

Input

control

circuit

Clock

selector

EN

TOT0

TIN0

External clock

2

3

Select

signal

Operating

Control

circuit

Select

function

⎯

CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR0)

Interrupt

requestoutput

#23 (17^H)*¹

*1 : Interrupt number

*2 : Underflow

33

MB90335 Series

5. Multifunction timer

The multifunction timer can be used for waveform output, input pulse width measurement, and external clock

cycle measurement.

• Configuration of a multi-functional timer

8/16-bit PPG timer

16-bit PWC timer

8-bit × 4 channels

(16-bit × 2 channels)

1 channel

• 8/16-bit PPG timer (8-bit : 4 channels, 16-bit : 2 channels)

8/16-bit PPG timer consists of a 8-bit down counter (PCNT) , PPG operation mode control register (PPGC0 to

PPGC3) , PPG output control register (PPG01, PPG23) and PPG reload register (PRLL0 to PRLL3, PRLH0 to

PRLH3) .

When used as an 8/16-bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an

arbitrary duty ratio at an arbitrary frequency.

• 8-bit PPG mode

Each channel operates as an independent 8-bit PPG.

• 8-bit prescaler + 8-bit PPG mode

Operates as an arbitrary-cycle 8-bit PPG with ch.0 (ch.2) operating as an 8-bit prescaler and ch.2 (ch.3)

counted by the borrow output of ch.0 (ch.2).

• 16-bit PPG mode

Operates as a 16-bit PPG with ch.0 (ch.2) and ch.1 (ch.3) connected.

• PPG Operation

The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of

pulse waveform) at an arbitrary frequency. Can also be used as a D/A converter by an external circuit.

34

MB90335 Series

• Register list

PPG operation mode control register

(PPGC1/PPGC3)

Initial Value

15

14

⎯

13

12

11

10

9

8

000047^H

000049H

0X000001^B

Reserved

Address :

PEN1

( R/W )

PE10

PIE1

PUF1

MD1

MD0

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(PPGC0/PPGC2)

000046^H

Initial Value

0X000XX1^B

7

6

⎯

5

4

3

2

⎯

1

0

Address :

Reserved

PEN0

( R/W )

PE0O

PIE0

PUF0

⎯

000048H

( ⎯ )

( R/W ) ( R/W ) ( R/W )

( ⎯ )

( R/W )

PPG output control register (PPG01/PPG23)

Initial Value

000000XX^B

7

6

5

4

3

2

1

0

00004C^H

00004EH

Reserved

Address :

Reserved

PCM1 PCM0

PCS2

PCS1

PCS0

PCM2

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PPG reload register

(PRLH0 to PRLH3)

007901^H

Initial Value

15

14

13

12

11

10

9

8

007903H

007905H

007907H

XXXXXXXX^B

D15

D14

D13

D12

D11

D10

D09

D08

Address :

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(PRLL0 to PRLL3)

007900^H

Initial Value

7

6

5

4

3

2

1

0

007902H

007904H

007906H

XXXXXXXX^B

Address :

D07

D06

D05

D04

D03

D02

D01

D00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

35

MB90335 Series

• 8/16-bit PPG ch.0/ch.2 block diagram

PPG0/PPG2

output enable

Peripheral clock × 16

Peripheral clock × 8

Peripheral clock × 4

Peripheral clock × 2

Peripheral clock

PPG0/PPG2

A/D converter

PPG0/PPG2

output latch

PEN0

S

R

PCNT

(down counter)

To interrupt

#30 (1E^H)*

#32 (20H)*

Q

IRQ

Count clock

selector

ch.1/ch.3 borrow

L/H selector

Timebase counter

output main clock × 512

PUF0

PIE0

L/H selector

PRLL

PRLHB

PPGC0

(operation mode control)

PRLL

L data bus

H data bus

* : Interrupt number

36

MB90335 Series

• 8/16-bit PPG ch.1/ch.3 block diagram

PPG1/PPG3

output enable

Peripheral clock × 16

Peripheral clock × 8

Peripheral clock × 4

Peripheral clock × 2

Peripheral clock

PPG1/PPG3

output latch

PEN1

S

R

PCNT

(down counter)

To interrupt

#30 (1E^H)*

#32 (20^H)*

Q

IRQ

Count clock

selector

L/H selector

Timebase counter

output main clock × 512

PUF1

PIE1

L/H selector

PRLL

PRLHB

PPGC1

(operation mode control)

PRLL

L data bus

H data bus

* : Interrupt number

37

MB90335 Series

• PWC timer

The PWC timer is a 16-bit multi-function up-count timer capable of measuring the input signal pulse width.

• Register list

PWC control status register (PWCSR)

Initial Value

15

14

13

12

11

10

9

8

Address : 00005D^H

0000000XB

Reserved

STRT

STOP

EDIR

EDIE

OVIR

OVIE

ERR

( R/W ) ( R/W )

( R )

( R/W ) ( R/W ) ( R/W )

( R )

( R/W )

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00005C^H

CKS1

CKS0

PIS1

PIS0

S/C

MOD2 MOD1 MOD0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PWC data buffer register (PWCR)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00005F^H

D15

D14

D13

D12

D11

D10

D9

D8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00005E^H

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PWC ratio of dividing frequency control register (DIVR)

Initial Value

7

6

5

4

3

2

1

0

Address : 000060^H

------00B

⎯

DIV1

DIV0

( ⎯ )

( R/W ) ( R/W )

38

MB90335 Series

• Block Diagram

PWCR read

Error

detection

ERR

PWCR

16

Internal clock

(machine clock/4)

Reload

Data transfer

Over-

16

2²

flow

Clock

divider

16-bit up-count timer

2³

CKS1/CKS0

Timer

clear

Divider

clear

Control circuit

Count enable

Start edge

selection

End edge

selection

Measurement

starting edge

Input

waveform

comparator

Divider ON/OFF

Edge

detection

Pin PWC

Measurement

termination edge

Measurement

termination interrupt

request

8-bit

divider

PIS0/PIS1

Overflow interrupt

request

CKS0/CKS1

ERR

15

Divide ratio

select

PWCSR

2

DIVR

39

MB90335 Series

6. UART

UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop syn-

chronization) communications with external devices.

It supports bi-directional communication (normal mode) and master/slave communication (multi-processor

mode: supported on master side only).

An interrupt can be generated upon completion of reception, detection of a reception error, or upon completion

of transmission. EI²OS is supported.

• UART functions

UART, or a generic serial data communication interface that sends and receives serial data to and from other

CPU and peripherals, has the functions listed in following.

Function

Data buffer

Full-duplex double-buffered

• Clock synchronous (without start/stop bit)

• Clock asynchronous (start-stop synchronous)

Transmission mode

• Special-purpose baud-rate generator

Baud rate

It is optional from 8 kinds.

• Baud rate by external clock (clock of SCK0/SCK1 terminal input)

• 8-bit or 7-bit (in the asynchronous normal mode only)

• 1 to 8 bits (in the synchronous mode only)

Data length

Signaling system

Non Return to Zero (NRZ) system

• Framing error

Reception error detection

• Overrun error

• Parity error (Not supported in operation mode 1)

• Receive interrupt (reception completed, reception error detected)

• Transmission interrupt (transmission completed)

• Both the transmission and reception support EI²OS.

Interrupt request

Master/slave type

communication function Capable of 1 (master) to n (slaves) communication (available just as master)

(multi processor mode)

Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.

• UART operation modes

Data length

Operation mode

Synchronization

Stop bit length

Without parity

With parity

0

1

2

Normal mode

7-bit or 8-bit

Asynchronous

Synchronous

1-bit or 2-bit *²

No

Multi processor mode

Normal mode

8-bit + 1 *¹

⎯

1 to 8-bit

⎯ : Setting disabled

*1 : + 1 is an address/data setting bit (A/D) which is used for communication control.

*2 : Only one bit can be detected as a stop bit at reception.

40

MB90335 Series

• Register list

Serial mode register (SMR0, SMR1)

Initial Value

7

6

5

4

3

2

1

0

000020^H

000026H

Address :

00100000^B

M2L0

MD1

MD0

SCKL

M2L2

M2L1

SCKE

SOE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Serial control register (SCR0, SCR1)

Initial Value

00000100^B

15

14

P

13

12

11

10

9

8

000021H

Address :

PEN

SBL

CL

A/D

REC

RXE

TXE

000027H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( W )

( R/W ) ( R/W )

Serial input/output data register (SIDR0, SIDR1 / SODR0, SODR1)

Initial Value

7

6

5

4

3

2

1

0

000022H

000028H

Address :

XXXXXXXX^B

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Serial status register (SSR0, SSR1)

Initial Value

00001000^B

15

14

13

12

11

10

9

8

000023H

Address :

PE

ORE

FRE

RDRF TDRE

BDS

RIE

TIE

000029H

( R )

( R/W ) ( R/W ) ( R/W )

UART prescaler reload register (UTRLR0, UTRLR1)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

000024H

00002AH

Address :

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

UART prescaler control register (UTCR0, UTCR1)

Initial Value

15

14

13

12

11

10

9

8

000025H

00002BH

Address :

0000-000^B

Reserved

MD

SRST

CKS

⎯

D10

D9

D8

( R/W ) ( R/W ) ( R/W ) ( R/W )

( ⎯ )

( R/W ) ( R/W ) ( R/W )

41

MB90335 Series

• Block Diagram

Control bus

Special-purpose

baud-rate generator

(UART prescaler

control register

Reception interrupt

signal

*

#39 (27^H)

Transmission

clock

UTCR0, UTCR1)

Send interrupt signal

#37 (25^H)

*

(UART prescaler

Clock

Reception

clock

Reception

control

circuit

reload resister

selector

UTRLR0, UTRLR1)

Transmission

control circuit

SCK0, SCK1

Start bit

Transmission

detection circuit

start circuit

Reception bit

counter

Transmission bit

counter

Transmission

parity counter

Reception parity

counter

SOT0, SOT1

Shift register for

reception

Shift register for

transmission

SIN0, SIN1

Reception

complete

SIDR0, SIDR1

SODR0, SODR1

Start

transmission

Receive status

decision circuit

Reception error

occurrence signal for

EI²OS (to CPU)

Internal data bus

MD1

MD0

PEN

P

SBL

PE

ORE

FRE

RDRF

TDRE

BDS

RIE

SCKL

M2L2

M2L1

M2L0

SCKE

SOE

SMR0,

SMR1

SCR0,

SCR1

SSR0,

SSR1

CL

A/D

REC

RXE

TXE

TIE

* : Interrupt number

42

MB90335 Series

7. Extended I/O serial interface

The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit ×

1 channel configured clock synchronization scheme. LSB-first or MSB-first transfer mode can be selected for

data transfer.

There are 2 serial I/O operation modes available:

• Internal shift clock mode : Transfer data in synchronization with the internal clock.

• External shift clock mode : Transfer data in synchronization with the clock supplied via the external pin (SCK).

By manipulating the general-purpose port sharing the external pin (SCK) in this

mode, data can also be transferred by a CPU instruction.

• Register list

Serial mode control status register (SMCS)

Initial Value

00000010 B

15

14

13

12

11

10

9

8

Address : 000059^H

Address : 000058^H

SMD2 SMD1 SMD0

( R/W ) ( R/W ) ( R/W )

SIE

SIR

BUSY

STOP

STRT

( R/W ) ( R/W )

( R )

( R/W ) ( R/W )

Initial Value

XXXX0000 B

7

6

5

4

3

2

1

0

⎯

MODE

BDS

SOE

SCOE

( ⎯ )

( R/W )

( ⎯ )

( R/W )

Serial data register (SDR)

Address : 00005A^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Communication prescaler control register (SDCR)

Initial Value

0XXX0000B

15

14

13

12

11

10

9

8

Address : 00005B^H

MD

⎯

DIV3

DIV2

DIV1

DIV0

( R/W )

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

43

MB90335 Series

• Block Diagram

Internal data bus

D7 to D0 (LSB first)

Transfer direction selection

Initial Value

(MSB first) D0 to D7

SIN

Read

Write

SDR (serial data register)

SOT

SCK

Shift clock counter

Control circuit

Internal clock

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

44

MB90335 Series

2

8. I C Interface

The I²C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I²C

bus and has the following features.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Detecting transmitting direction function

• Start condition repeated generation and detection function

• Bus error detection function

• Register list

I²C bus status register (IBSR0)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 000070^H

BB

RSC

AL

LRB

TRX

AAS

GCA

FBT

( R )

I²C bus control register (IBCR0)

15

14

13

12

11

10

9

8

Initial Value

00000000B

Address : 000071^H

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus clock control register (ICCR0)

7

6

5

4

3

2

1

0

Initial Value

Address : 000072^H

XX0XXXXXB

⎯

EN

CS4

CS3

CS2

CS1

CS0

( ⎯ ) ( ⎯ ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus address register (IADR0)

15

14

A6

13

A5

12

A4

11

A3

10

A2

9

8

Initial Value

XXXXXXXXB

Address : 000073H

⎯

A1

A0

( ⎯ ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus data register (IDAR0)

7

6

5

4

3

2

1

0

Initial Value

Address : 000074^H

XXXXXXXXB

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

45

MB90335 Series

• Block Diagram

ICCR

EN

2

I C enable

Peripheral clock

Clock divide 1

5

6

7

8

ICCR

CS4

CS3

Clock selector 1

Clock divide 2

CS2

CS1

CS0

Sync

2

4

8 16 32 64 128 256

Generating shift clock

Clock selector 2

Shift clock edge

change timing

IBSR

Bus busy

BB

Repeat start

Start stop condition

detection

RSC

LRB

TRX

Last Bit

Error

Send/receive

First Byte

FBT

AL

Arbitration lost detection

IBCR

BER

SCL0

SDA0

BEIE

INTE

INT

IRQ

Interrupt request

End

IBCR

Start

SCC

Master

MSS

ACK

Start stop condition

generation

ACK enable

GC-ACK enable

GCAA

IDAR

IBSR

AAS

Slave

Slave address

compare

Global call

GCA

IADR

46

MB90335 Series

9. USB Function

The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.

Feature of USB function

• Conform to USB 2.0 Full Speed

• Full speed (12 Mbps) is supported.

• The device status is auto-answer.

• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16.

• Toggle check by data synchronization bit.

• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these

three commands can be processed the same way as the class vendor commands).

• The class vendor commands can be received as data and responded via firmware.

• Supports up to maximum six EndPoints (EndPoint0 is fixed to control transfer).

• Two transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for end point 0).

• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0).

• Register list

UDC control register (UDCC)

7

6

5

4

3

2

1

0

Initial Value

10100000B

Address : 0000D0^H

Address : 0000D1^H

Reserved

RST RESUM HCON USTP

RFBK

PWC

( R/W ) ( R/W ) ( R/W ) ( R/W )

(

)

(

)

( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

00000000B

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

( ⎯ )

EP0 control register (EP0C)

Address : 0000D2^H

7

6

5

4

3

2

1

0

Initial Value

01000000B

Reserved

PKS0

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XXXX0000B

Address : 0000D3^H

⎯

Reserved Reserved STAL Reserved

( ⎯ )

( R/W )

( ⎯ )

EP1 control register (EP1C)

Address : 0000D4^H

7

6

5

4

3

2

1

0

Initial Value

00000000B

PKS1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

01100001B

Address : 0000D5^H

EPEN

TYPE

DIR

DMAE NULE

STAL

PKS1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(Continued)

47

MB90335 Series

EP2/3/4/5 control register (EP2C to EP5C)

Initial Value

01000000B

7

6

5

4

3

2

1

0

0000D6^H

0000D8H

0000DAH

0000DCH

Reserved

Address :

PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5 PKS2∼5

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

01100000B

15

14

13

12

11

10

9

8

0000D7^H

0000D9H

0000DBH

0000DDH

Reserved

EPEN

TYPE

DIR

DMAE NULE

STAL

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Time stamp register (TMSP)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000DE^H

TMSP

TMSP TMSP TMSP

TMSP

( R )

15

14

13

12

11

10

9

8

Initial Value

XXXXX000B

Address : 0000DF^H

⎯

TMSP TMSP

( R ) ( R )

TMSP

( ⎯ )

( R )

UDC status register (UDCS)

Address : 0000E0^H

7

6

5

4

3

2

1

0

Initial Value

XX000000B

⎯

SUSP

SOF

BRST WKUP SETP

CONF

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

UDC Interrupt enable register (UDCIE)

15

14

13

12

11

10

9

8

Initial Value

00000000B

Address : 0000E1^H

Reserved Reserved SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

( R )

( R/W )

EP0I status register (EP0IS)

Address : 0000E2^H

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXXB

⎯

( ⎯ )

15

14

13

12

11

10

9

8

Initial Value

10XXX1XXB

Address : 0000E3^H

BFINI DRQIIE

( R/W ) ( R/W )

⎯

DRQI

⎯

( ⎯ )

( R/W )

( ⎯ )

(Continued)

48

MB90335 Series

(Continued)

EP0O status register (EP0OS)

Initial Value

0XXXXXXXB

7

6

5

4

3

2

1

0

Address : 0000E4^H

Reserved SIZE

SIZE

( ⎯ )

( R )

15

14

13

12

11

10

9

8

Initial Value

100XX000B

Address : 0000E5^H

BFINI DRQOIE SPKIE

( R/W ) ( R/W ) ( R/W )

⎯

DRQO

SPK

Reserved

( ⎯ )

( R/W ) ( R/W )

( ⎯ )

EP1 status register (EP1S)

Address : 0000E6^H

Initial Value

XXXXXXXXB

7

6

5

4

3

2

1

0

SIZE

( R )

15

14

13

12

11

10

9

8

Initial Value

1000000XB

Address : 0000E7^H

BFINI DRQIE SPKIE Reserved BUSY

DRQ

SPK

SIZE

( R/W ) ( R/W ) ( R/W )

( ⎯ )

( R )

( R/W ) ( R/W )

( R )

EP2/3/4/5 status register (EP2S to EP5S)

Initial Value

0XXXXXXXB

7

6

5

4

3

2

1

0

0000E8^H

0000EAH

0000ECH

0000EEH

Address :

Reserved

SIZE

( ⎯ )

( R )

Initial Value

10000000B

15

14

13

12

11

10

9

8

0000E9^H

0000EBH

0000EDH

0000EFH

Reserved

BFINI DRQIE SPKIE

( R/W ) ( R/W ) ( R/W )

BUSY

DRQ

SPK

( ⎯ )

( R )

( R/W ) ( R/W )

( ⎯ )

EP0/1/2/3/4/5 data register (EP0DT to EP5DT)

0000F0H

0000F2H

0000F4^H

0000F6H

0000F8H

0000FAH

Initial Value

7

6

5

4

3

2

1

0

Address :

XXXXXXXXB

BFDT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

0000F1H

0000F3H

0000F5^H

0000F7H

0000F9H

0000FBH

Initial Value

15

14

13

12

11

10

9

8

Address :

XXXXXXXXB

BFDT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

49

MB90335 Series

10. USB Mini-HOST

USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred

to and from Device without PC intervention.

• Feature of USB Mini-HOST

• Automatic detection of Low Speed/Full Speed transfer

• Low Speed/Full Speed transfer support

• Automatic detection of connection and cutting device

• Reset sending function support to USB-bus

• Support of IN/OUT/SETUP/SOF token

• In-token handshake packet automatic transmission (excluding STALL)

• Handshake packet automatic detection at out-token

• Supports a maximum packet length of 256 bytes

• Error (CRC error/toggle error/time-out) various supports

• Wake-Up function support

• Differences between the USB HOST and USB Mini-HOST

HOST

Mini-HOST

Hub support

Transfer

×

Bulk transfer

Control transfer

Interrupt transfer

ISO transfer

Low Speed

×

Transfer speed

Full Speed

PRE packet support

SOF packet support

CRC error

Toggle error

Error

Time-out

Maximum packet < receive data

Detection of connection and cutting of device

Transfer speed detection

: Supported

×

: Not supported

50

MB90335 Series

• Register list

Host control register 0 (HCNT0)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000C0^H

RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST

HOST

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Host control register 1 (HCNT1)

15

14

13

12

11

10

SOFSTEP CANCEL RETRY

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

9

8

Initial Value

00000001B

Address : 0000C1^H

Reserved Reserved Reserved Reserved Reserved

Host interruption register (HIRQ)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000C2^H

Reserved

TCAN

RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Host error status register (HERR)

15

14

13

12

11

10

9

8

Initial Value

00000011B

Address : 0000C3^H

LSTSOF RERR TOUT

CRC TGERR STUFF

HS

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Host state status register (HSTATE)

7

6

5

4

3

2

1

0

Initial Value

XX010010B

Address : 0000C4^H

⎯

ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

( R )

SOF interruption FRAME comparison register (HFCOMP)

15

14

13

12

11

10

9

8

Initial Value

00000000B

FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME

COMP COMP COMP COMP COMP COMP COMP COMP

Address : 0000C5^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Retry timer setting register (HRTIMER)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000C6^H

Address : 0000C7^H

Address : 0000C8^H

RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

00000000B

RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

7

6

5

4

3

2

1

0

Initial Value

XXXXXX00B

⎯

RTIMER2 RTIMER2

( R/W ) ( R/W )

( ⎯ )

(Continued)

51

MB90335 Series

(Continued)

Host address register (HADR)

15

14

13

12

11

10

9

8

Initial Value

X0000000B

Address : 0000C9^H

⎯

ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( ⎯ )

EOF setting register (HEOF)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000CA^H

EOF0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XX000000B

Address : 0000CB^H

⎯

EOF1

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

FRAME setting register (HFRAME)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000CC^H

FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XXXXX000B

Address : 0000CD^H

⎯

FRAME1 FRAME1 FRAME1

( R/W ) ( R/W ) ( R/W )

( ⎯ )

Host token end point register (HTOKEN)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000CE^H

TGGL TKNEN TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

52

MB90335 Series

11. DTP/external interrupt circuit

DTP (Data Transfer Peripheral)/external interrupt circuit detects the interrupt request input from the external

interrupt input terminal INT7 to INT0, and outputs the interrupt request.

• DTP/external interrupt circuit function

The DTP/external interrupt function outputs an interrupt request upon detection of the edge or level signal input

to the external interrupt input pins (INT7 to INT0).

If CPU accept the interrupt request, and if the extended intelligent I/O service (EI²OS) is enabled, branches to

the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI²OS.

And if EI²OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer

(DTP function) performed by EI²OS.

• Feature of DTP/external interrupt circuit

External interrupt

DTP function

8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK,

P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0)

Input pin

The detection level or the type of the edge for each terminals can be set in the

request level setting register (ELVR)

Interrupt source

Input of “H” level/ “L” level/rising edge/falling edge.

#18 (12^H) , #20 (14H) , #22 (16H) , #24 (18H)

Interrupt number

Interrupt control

Enabling/Prohibit the interrupt request output using the DTP/interrupt enable

register (ENIR)

Interrupt flag

Holding the interrupt source using the DTP/interrupt cause register (EIRR)

Process setting

Prohibit EI²OS (ICR: ISE=“0”)

Enable EI²OS (ICR: ISE=“1”)

Branched to the interrupt handling

routine

After an automatic data transfer by EI²OS,

Branched to the interrupt handling routine

Process

• Register list

DTP/Interrupt enable register (ENIR)

Initial Value

7

6

5

4

3

2

1

0

Address : 00003C^H

00000000B

EN7

EN6

EN5

(R/W)

EN4

(R/W)

EN3

(R/W)

EN2

(R/W)

EN1

(R/W)

EN0

(R/W)

DTP/Interrupt source register (EIRR)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00003D^H

ER7

(R/W)

ER6

ER5

(R/W)

ER4

(R/W)

ER3

(R/W)

ER2

(R/W)

ER1

(R/W)

ER0

(R/W)

Request level setting register (ELVR)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00003E^H

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

(R/W)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00003F^H

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

(R/W)

53

MB90335 Series

• Block Diagram

Request level setting register (ELVR)

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2

DTP/external interrupt input detection circuit

Selector

P60/INT0

P67/INT7/

SDA0

Selector

P66/INT6/

SCL0

P61/INT1

Selector

P62/INT2/

P65/INT5/

PWC

SIN

Selector

P64/INT4/

SCK

P63/INT3/

SOT

DTP/interrupt

source register

(EIRR)

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

Interrupt request signal

#18(12H)^*

#20(14H)^*

#22(16H)^*

#24(18H)^*

DTP/interrupt

enable register

(ENIR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

* : Interrupt number

54

MB90335 Series

12. Interrupt controller

The interrupt control register is located inside the interrupt controller, it exists for every I/O having an interrupt

function. This register has the following functions.

• Setting of the interrupt levels of relevant peripheral

• Register list

Interrupt control register (ICR01, ICR03, ICR05, ICR07, ICR09, ICR11, ICR13, ICR15)

Initial Value

Address : ICR01 : 0000B1^H

ICR03 : 0000B3H

ICR05 : 0000B5H

ICR07 : 0000B7H

ICR09 : 0000B9H

ICR11 : 0000BBH

ICR13 : 0000BDH

ICR15 : 0000BFH

00000111B

15

14

13

12

11

10

9

8

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

( W )

( R/W ) ( R/W ) ( R/W ) ( R/W )

Interrupt control register (ICR00, ICR02, ICR04, ICR06, ICR08, ICR10, ICR12, ICR14)

Address : ICR00 : 0000B0^H

Initial Value

00000111B

7

6

5

4

3

2

1

0

ICR02 : 0000B2H

ICR04 : 0000B4H

ICR06 : 0000B6H

ICR08 : 0000B8H

ICR10 : 0000BAH

ICR12 : 0000BCH

ICR14 : 0000BEH

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

( W )

( R/W ) ( R/W ) ( R/W ) ( R/W )

Note : Do not access interrupt control registers using any read modify write instruction because it causes a

malfunction.

• Block Diagram

3

32

Interrupt request

(peripheral resource)

IL2

IL1

IL0

3

Determine

priority

of

interrupt

3

(CPU)

Interrupt level

55

MB90335 Series

13. µDMAC

µDMAC is simple DMA with the function equal with EI²OS. It has 16 channels DMA transfer channels with the

following features.

• Performs automatic data transfer between the peripheral resource (I/O) and memory

• The program execution of CPU stops in the DMA startup

• Capable of selecting whether to increment the transfer source and destination addresses

• DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register and

descriptor

• A STOP request is available for stopping DMA transfer from the resource

• Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA

status register is set and a termination interrupt is output to the transfer controller.

• Register list

DMA enable register upper (DERH)

Initial Value

15

14

13

12

11

10

9

8

Address : 0000AD^H

00000000B

EN15

EN14

EN13

EN12

EN11

EN10

EN9

EN8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA enable register lower (DERL)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 0000AC^H

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA stop status register (DSSR)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 0000A4^H

STP7

STP6

STP5

STP4

STP3

STP2

STP1

STP0

STP8

STP15 STP14 STP13 STP12 STP11 STP10 STP9

*

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA status register upper (DSRH)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00009D^H

DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9

DTE8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA status register lower (DSRL)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00009C^H

DTE7

DTE6

DTE5

DTE4

DTE3

DTE2

DTE1

DTE0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA descriptor channel specification register (DCSR)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00009B^H

Reserved Reserved Reserved

STP

DCSR3 DCSR2 DCSR1 DCSR0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

* : The DSSR is lower when the STP bit of DCSR in the DSSR is “0”.

The DSSR is upper when the STP bit of DCSR in the DSSR is “1”.

(Continued)

56

MB90335 Series

(Continued)

DMA buffer address pointer lower 8 bit (DBAPL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007920H

XXXXXXXXB

DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA buffer address pointer middle 8 bit (DBAPM)

Initial Value

15

14

13

12

11

10

9

8

Address : 007921^H

XXXXXXXXB

DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA Buffer address pointer upper 8 bit (DBAPH)

Initial Value

7

6

5

4

3

2

1

0

Address : 007922^H

XXXXXXXXB

DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA control register (DMACS)

Initial Value

15

14

13

12

IF

11

10

9

8

Address : 007923^H

XXXXXXXXB

RDY2

RDY1 BYTEL

BW

BF

DIR

SE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA I/O register address pointer lower 8 bit (DIOAL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007924^H

XXXXXXXXB

A07

A06

A05

A04

A03

A02

A01

A00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA I/O register address pointer upper 8 bit (DIOAH)

Initial Value

15

14

13

12

11

10

9

8

Address : 007925^H

XXXXXXXXB

A15

A14

A13

A12

A11

A10

A09

A08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA data counter lower 8 bit (DDCTL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007926^H

XXXXXXXXB

B07

B06

B05

B04

B03

B02

B01

B00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA data counter upper 8 bit (DDCTH)

Initial Value

15

14

13

12

11

10

9

8

Address : 007927^H

XXXXXXXXB

B15

B14

B13

B12

B11

B10

B09

B08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Note : The above register is switched for each channel depending on the DCSR.

57

MB90335 Series

14. Address matching detection function

When the address is equal to the value set in the address detection register, the instruction code to be read into

the CPU is forcibly replaced with the INT9 instruction code (01^H). As a result, the CPU executes the INT9

instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the

program patch function is enabled.

2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address

matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code

to be read into the CPU is forcibly replaced with the INT9 instruction code.

• Register list

• Program address detect register 0 (PADR0)

PADR0 (lower)

Initial Value

7

6

5

4

3

2

1

0

Address : 001FF0^H

XXXXXXXXB

(R/W)

PADR0 (middle)

Address : 001FF1^H

Initial Value

15

14

13

12

11

10

9

8

XXXXXXXXB

(R/W)

PADR0 (upper)

Address : 001FF2^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

(R/W)

• Program address detect register 1 (PADR1)

PADR1 (lower)

Initial Value

15

14

13

12

11

10

9

8

Address : 001FF3^H

XXXXXXXXB

(R/W)

PADR1 (middle)

Address : 001FF4^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

(R/W)

PADR1 (upper)

Address : 001FF5^H

Initial Value

15

14

13

12

11

10

9

8

XXXXXXXXB

(R/W)

• Program address detect control status register (PACSR)

PACSR

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00009E^H

Reserved

Reserved Reserved Reserved

Reserved

AD1E

AD0E

(R/W)

R/W : Readable and Writable

X

: Undefined

58

MB90335 Series

15. Delay interrupt generator module

The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware

interrupt can be generated by software.

• Delay interrupt generator module function

Function and control

• Setting the R0 bit in the delayed interrupt request generation/release register to

1 (DIRR: R0 = 1) generates a delayed interrupt request.

• Setting the R0 bit in the delayed interrupt request generation/release register to

0 (DIRR: R0 = 0) cancels the delayed interrupt request.

Interrupt source

Interrupt control

Interrupt flag

No setting of permission register is provided.

Set in bit R0 of the delayed interrupt request generation /clear register (DIRR : R0)

Not ready for extended intelligent I/O service (EI²OS).

EI²OS support

• Block Diagram

Internal data bus

⎯

R0

S Interrupt request

R Latch

Interrupt

request

signal

Delayed Interrupt source/release register (DIRR)

⎯ : Undefined bit

59

MB90335 Series

16. ROM mirroring function selection module

The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read

by accessing bank 00.

• ROM mirroring function selection module function

Description

FFFFFFH to FF8000H in the FF bank can be read through 00FFFFH to 008000H in

Mirror setting address

the 00 bank.

Interrupt source

EI²OS support

None

Not ready for extended intelligent I/O service (EI²OS).

• Block Diagram

ROM mirror function selection register (ROMM)

Re-

served

MI

Address

Address area

FF bank

00 bank

Data

ROM

60

MB90335 Series

17. Low power consumption (standby) mode

The F²MC-16LX can be set to save power consumption by selecting and setting the low power consumption

mode.

• CPU operation mode and functional description

CPU

operating clock

Operation

mode

Description

The CPU and peripheral resources operate at the clock frequency obtained by

PLL multiplication of oscillator clock (HCLK) frequency.

Normal run

Sleep

Only peripheral resources operate at the clock frequency obtained by PLL

multiplication of the oscillator clock (HCLK) frequency.

PLL clock

Time-base Only the time-base timer operates at the clock frequency obtained by PLL

timer

multiplication of the oscillator clock (HCLK) frequency.

The CPU and peripheral resources are suspended with the oscillator clock

stopped.

Stop

The CPU and peripheral resources operate at the clock frequency obtained by

dividing the oscillator clock (HCLK) frequency by two.

Normal run

Sleep

Only peripheral resources operate at the clock frequency obtained by dividing the

oscillator clock (HCLK) frequency by two.

Main clock

Time-base Only the time-base timer operates at the clock frequency obtained by dividing the

timer

oscillator clock (HCLK) frequency by two.

The CPU and peripheral resources are suspended with the oscillator clock

stopped.

Stop

CPU intermittent

operation mode

The halved or PLL-multiplied oscillator clock (HCLK) frequency is used for

operation while being decimated in a certain period.

Normal run

• Register list

Low power consumption mode control register (LPMCR)

Initial Value

00011000B

7

6

5

4

3

2

1

0

Address : 0000A0^H

Reserved

STP

SLP

SPL

RST

TMD

CG1

CG0

( W )

( R/W )

( W )

( R/W ) ( R/W ) ( R/W ) ( R/W )

61

MB90335 Series

18. Clock

The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The

internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on

source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation as PLL clock.

• Register list

Clock selection register (CKSCR)

Initial Value

11111100B

15

14

13

12

11

10

9

8

Address : 0000A1^H

SCM

MCM

WS1

WS0

SCS

MCS

CS1

CS0

( R )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

62

MB90335 Series

19. 512 Kbits flash memory

The description that follows applies to the flash memory built in the MB90F337; it is not applicable to evaluation

ROM or masked ROM.

The method of data write/erase to flash memory is following three types.

• Parallel writer

• Serial dedicated writer

• Write/erase by executing program

• Description of 512 Kbits flash memory

512 Kbits flash memory is located in FF^Hbank in the CPU memory map. Function of flash memory interface

circuit enables read and program access from CPU.

Write/erase to flash interface is executed by instruction from CPU via flash memory interface, so rewrite of

program and data is carried on in the mounting state effectively.

Data can be reprogrammed not only by program execution in existing RAM but by program execution in flash

memory by dual operation. Also, erase/write and read in the different bank (Upper Bank/Lower Bank) is executed

simultaneously.

• Features of 512 Kbits flash memory

• Sector configuration : 64 Kwords × 8 bits/32 words × 16 bits (4 K × 4 + 16 K × 2 + 4 K × 4)

• Simultaneous execution of erase/write and read by 2-bank configuration

• Automatic program algorithm (Embedded Algorithm^TM*)

• Built-in deletion pause/deletion resume function

• Detection of programming/erasure completion using data polling and the toggle bit

• At least 10000 times guaranteed

• Minimum flash read cycle time : 2 machine cycles

* : Embedded Algorithm^TMis a trade mark of Advanced Micro Devices Inc.

Note : The read function of manufacture code and device code is not including.

Also, these code is not accessed by the command.

• Flash write/erase

• Flash memory can not execute write/erase and read by the same bank simultaneously.

• Data can be programmed/deleted into and erased from flash memory by executing either the program

residing in the flash memory or the one copied to RAM from the flash memory.

63

MB90335 Series

• Sector configuration of flash memory

Flash Memory CPU address Writer address *

FF0000^H

FF0FFFH

FF1000H

FF1FFFH

FF2000H

FF2FFFH

FF3000^H

FF3FFFH

FF4000H

FF7FFFH

FF8000H

FFBFFFH

FFC000H

FFCFFFH

FFD000^H

FFDFFFH

FFE000H

FFEFFFH

FFF000H

FFFFFFH

70000H

70FFFH

71000H

71FFFH

72000H

72FFFH

73000H

73FFFH

74000H

77FFFH

78000H

7BFFFH

7C000H

7CFFFH

7D000H

7DFFFH

7E000H

7EFFFH

7F000H

7FFFFH

SA0 (4 Kbytes)

SA1 (4 Kbytes)

SA2 (4 Kbytes)

SA3 (4 Kbytes)

SA4 (16 Kbytes)

SA5 (16 Kbytes)

SA6 (4 Kbytes)

SA7 (4 Kbytes)

SA8 (4 Kbytes)

SA9 (4Kbytes)

* : Flash memory writer address indicates the address equivalent to the CPU address when data is written

to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel

programmer are executed based on writer addresses.

64

MB90335 Series

• Register list

Flash memory control status register (FMCS)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000AE^H

000X0000B

Reserved

INTE RDYINT

WE

RDY

LPM1

LPM0

( R/W ) ( R/W ) ( R/W )

( R )

( W )

( R/W )

( W )

( R/W )

Flash memory program control register (FWR0)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00790C^H

SA7E

SA6E

SA5E

SA4E

SA3E

SA2E

SA1E

SA0E

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Flash memory program control register (FWR1)

Initial Value

00000000B

15

14

13

12

11

10

9

0

Address : 00790D^H

SA9E

SA8E

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Sector conversion setting register (SSR0)

Initial Value

00XXXXX0B

7

6

5

4

3

2

1

0

Address : 00790E^H

SEN0

( R/W ) ( R/W )

(

)

(

)

(

)

(

)

(

)

( R/W )

Note : When writing to SSR0 register, write “0” except for SEN0.

65

MB90335 Series

• Standard configuration for Fujitsu standard serial on-board writing

The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corp.

is used for Fujitsu standard serial on-board writing.

Host interface cable (AZ201)

General-purpose common cable (AZ210)

Flash

CLK synchronous

microcontroller

RS232C

serial

MB90F337

user system

programmer

+

Memory card

Can operate stand-alone

Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the

flash microcontroller programmer (AF220, AF210, AF120 and AF110) , general-purpose common cable for

connection (AZ210) and connectors.

• Pins Used for Fujitsu Standard Serial On-board Programming

Function

Description

MD2,

The device enters the serial program mode by setting MD2 = 1,

MD1 = 1 and MD0 = 0.

Mode input pin

MD1, MD0

X0, X1

Because the internal CPU operation clock is set to be the 1 multiplication

PLL clock in the serial write mode, the internal operation clock frequency

is the same as the oscillation clock frequency.

Oscillation pin

P60, P61 Write program start pins

Input a Low level to P60 and a High level to P61.

RST

Reset input pin

⎯

SIN0

SOT0

SCK0

Serial data input pin

Serial data output pin

Serial clock input pin

UART0 is used as CLK synchronous mode.

In write mode, the pins used for the UART0 CLK synchronous mode are

SIN0, SOT0, and SCK0.

When supplying the write voltage (MB90F337 : 3.3 V 0.3 V) from the

user system, connection with the flash microcontroller programmer is

not necessary.

V^CC

V^SS

Power source input pin

GND Pin

When connecting, do not short-circuit with the user power supply.

Share GND with the flash microcontroller programmer.

66

MB90335 Series

The control circuit shown in the figure is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the

user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash

microcontroller programmer.

AF220/AF210/AF120/AF110

Write control pin

MB90F337 write control pin

10 kΩ

AF220/AF210/AF120/AF110

/TICS pin

User

Control circuit

The MB90F337 serial clock frequency that can be input is determined by the following expression. Use the flash

microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock

frequency to be used.

Inputable serial clock frequency = 0.125 × oscillation clock frequency.

• Maximum serial clock frequency

Maximum serial clock

Oscillation

clock

frequency

Maximum serial clock

frequency acceptable to the

flash microcontroller

Maximum serial clock

frequency that can be set

with the AF200

frequency that can be set

with the AF220/AF210/

AF120/AF110

At 6 MHz

750 kHz

500 kHz

• System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110)

(made by Yokogawa Digital Computer Corp.)

Part number

Function

AF220/AC4P Model with internal Ethernet interface

AF210/AC4P Standard model

/100 V to 220 V power adapter

Unit

AF120/AC4P Single key internal Ethernet interface mode

AF110/AC4P Single key model

AZ221

AZ210

PC/AT RS232C cable for writer

Standard target probe (a) length : 1 m

Control module for Fujitsu Microelectronics F²MC-16LX flash microcontroller control mod-

ule

FF201

AZ290

/P2

Remote controller

2 MB PC Card (option) Flash memory capacity to respond to 128 KB

4 MB PC Card (option) Flash memory capacity to respond to 512 KB

/P4

Contact to : Yokogawa Digital Computer Corporation TEL : 81-423-33-6224

Note : The AF200 flash microcontroller programmer is a retired product, but it can be supported using control module

FF201.

67

MB90335 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

Power supply voltage*¹

VCC

VSS − 0.3

VSS + 4.0

V

*2

N-ch open-drain

(Withstand voltage I/O of 5 V)*³

Input voltage*¹

VI

V^SS− 0.3

VSS + 6.0

V

− 0.5

VSS − 0.3

− 0.5

VSS + 4.5

VSS + 4.0

V^SS+ 4.5

+2.0

V

USB I/O

*2

Output voltage*¹

VO

V

USB I/O

*4

Maximum clamp current

I^CLAMP

− 2.0

mA

Total maximum clamp

current

Σ⏐I^CLAMP⏐

⎯

20

mA

*4

I^OL1

IOL2

⎯

10

43

4

mA

Other than USB I/O*⁵

“L” level maximum output

current

USB I/O*⁵

I^OLAV1

*6

“L” level average output

current

USB-IO

(Full speed/Low speed) *⁶

I^OLAV2

ΣI^OL

⎯

15/4.5

100

mA

“L” level maximum total

output current

“L” level average total

output current

ΣI^OLAV

50

*7

I^OH1

IOH2

⎯

− 10

− 43

− 4

mA

Other than USB I/O*⁵

“H” level maximum output

current

USB I/O*⁵

I^OHAV1

*6

“H” level average output

current

USB-IO

(Full speed/Low speed) *⁶

I^OHAV2

ΣI^OH

⎯

−15/−4.5

− 100

mA

“H” level maximum total

output current

“H” level average total

output current

ΣI^OHAV

− 50

*7

Power consumption

Pd

T^A

⎯

270

+ 85

mW

°C

Operating temperature

− 40

− 55

+ 150

+ 125

°C

Storage temperature

Tstg

°C

USB I/O

*1 : The parameter is based on VSS = 0.0 V.

*2 : V^Iand VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some

means with external components, the I^CLAMPrating supersedes the VI rating.

*3 : Applicable to pins : P60 to P67, UTEST

(Continued)

68

MB90335 Series

(Continued)

*4 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P54

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply

is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than P60 to P67, DVP, DVM, HVP, HVM, UTEST, HCON

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

V^CC

Limiting

resistance

P-ch

N-ch

+B input (0 V to 16 V)

R

*5 : A peak value of an applicable one pin is specified as a maximum output current.

*6 : The average output current specifies the mean value of the current flowing in the relevant single pin during a

period of 100 ms.

*7 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins

during a period of 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

69

MB90335 Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

3.6

V

At normal operation (When using USB)

At normal operation (When not using USB)

Hold state of stop operation

CMOS input pin

Power supply voltage

V^CC

2.7

1.8

V^IH

0.7 VCC

0.8 VCC

VCC + 0.3

V^IHS1

CMOS hysteresis input pin

N-ch open-drain

(Withstand voltage I/O of 5 V)*

Input “H” voltage

Input “L” voltage

V^IHS2

0.8 VCC

VSS + 5.3

V

V^IHM

V^IHUSB

V^IL

VCC − 0.3

2.0

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

0.8

V

MD pin input

USB pin input

VSS − 0.3

VSS

CMOS input pin

CMOS hysteresis input pin

MD pin input

V^ILS

V^ILM

V^ILUSB

USB pin input

Differential input

sensitivity

V^DI

0.2

0.8

⎯

V

USB pin input

Differential common

mode input voltage

range

V^CM

2.5

V

USB pin input

− 40

+ 85

+ 70

°C

When not using USB

When using USB

Operating

temperature

T^A

0

* : Applicable to pins : P60 to P67, UTEST

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

representatives beforehand.

70

MB90335 Series

3. DC Characteristics

(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = − 40 °C to +85 °C)

Value

Sym-

Parameter

bol

Pin name

Conditions

Unit Remarks

Min

Typ

Max

Output pins other

than P60 to P67,

HVP, HVM, DVP,

DVM

VCC − 0.5

I^OH= −4.0 mA

⎯

Vcc

V

Output “H”

voltage

V^OH

HVP, HVM, DVP,

DVM

R^L= 15 kΩ 5%

2.8

Vss

0

⎯

3.6

Vss + 0.4

0.3

V

Output pins other

than HVP, HVM, DVP, I^OL= 4.0 mA

DVM

Output “L”

voltage

V^OL

HVP, HVM, DVP,

DVM

R^L= 1.5 kΩ 5%

Output pins other

than P60 to P67,

HVP, HVM, DVP,

DVM

V^CC= 3.3 V,

Vss < V^I< VCC

− 10

⎯

+ 10

µA

Input leak

current

I^IL

HVP, HVM, DVP,

DVM

⎯

− 5

⎯

+ 5

µA

kΩ

Pull-up

resistance

P00 to P07,

P10 to P17

VCC = 3.3 V,

T^A= + 25 °C

R^PULL

25

50

100

Open drain

output

current

I^LIODP60 to P67

⎯

0.1

10

µA

VCC = 3.3 V,

⎯

55

50

45

65

60

55

mA MB90F337

mA MB90337

mA MB90F337

mA MB90337

Internal frequency 24 MHz,

At normal operating

At USB operating

(USTP = 0)

I^CC

V^CC= 3.3 V,

Internal frequency 24 MHz,

At normal operating

At non-operating USB

(USTP = 1)

Power

supply

current

VCC

VCC = 3.3 V,

Internal frequency 24 MHz,

At sleep mode

I^CCS

⎯

25

40

10

mA

VCC = 3.3 V,

Internal frequency 24 MHz,

At timer mode

3.5

I^CTS

V^CC= 3.3 V,

Internal frequency 3 MHz,

At timer mode

⎯

1.0

1

2.0

40

TA = +25 °C,

At stop mode

I^CCH

µA

(Continued)

71

MB90335 Series

(Continued)

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = − 40 °C to +85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Typ

Max

Input

capacitance

Other than Vcc and

Vss

C^IN

⎯

5

15

pF

Pull-up

resistor

R^upRST

25

50

100

kΩ

Pull-down

resistor

V^CC= 3.0 V

R^downMD2

kΩ MB90337

At T^A= +25 °C

USB I/O

output

impedance

DVP, DVM

HVP, HVM

Z^USB

⎯

3

⎯

14

Ω

Note : P60 to P67 are N-ch open-drain pins usually used as CMOS.

72

MB90335 Series

4. AC Characteristics

(1) Clock input timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = − 40 °C to +85 °C)

Value

Sym-

bol

name

Parameter

Unit

Remarks

Min

⎯

Typ

6

Max

⎯

MHz When oscillator is used

MHz External clock input

ns When oscillator is used

ns External clock input

Clock frequency

f^CH

X0, X1

6

⎯

24

⎯

166.7

⎯

Clock cycle time

t^HCYL

166.7

41.7

P^WH

PWL

A reference duty ratio is

30% to 70%.

Input clock pulse width

X0

⎯

10

⎯

3

⎯

5

ns

Input clock rise time and fall

time

tcr

tcf

ns At external clock

Internal operating clock

frequency

f^CP

t^CP

24

333

MHz When main clock is used

ns When main clock is used

Internal operating clock

cycle time

⎯

42

• Clock Timing

tHCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcr

tcf

73

MB90335 Series

• PLL operation guarantee range

Relation between power supply voltage and internal operation clock frequency

PLL operation guarantee range

3.6

3.0

2.7

Normal operation

assurance range

3

6

12

24

Internal clock fCP (MHz)

Note : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V.

Relation between internal operation clock frequency and external clock frequency

24

4 x

External clock

2 x

1 x

12

6

3

24

6

External clock FC (MHz)

The AC standards provide that the following measurement reference voltages.

• Output signal waveform

• Input signal waveform

Hysteresis input pin

Output pin

0.8 VCC

0.2 VCC

2.4 V

0.8 V

Hysteresis input/other than MD input pin

0.7 V^CC

0.3 VCC

74

MB90335 Series

(2) Reset

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Sym-

bol

name

Parameter

Conditions

Unit

Remarks

Min

Max

At normal operating,

At time base timer mode,

At main sleep mode,

At PLL sleep mode

500

⎯

ns

Reset input

time

t^RSTL

RST

⎯

Oscillation time of

oscillator* + 500 ns

⎯

µs At stop mode

* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several

dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a

ceramic oscillator, and 0 milliseconds on an external clock.

• During normal operation, time-base timer mode, main sleep mode and PLL sleep mode

t

RSTL

RST

0.2 VCC

• During stop mode

RST

t

RSTL

0.2 VCC

90% of

amplitude

X0

Internal

operation

clock

Oscillation time

of oscillator

500 ns

Oscillation stabilization wait time

Execute instruction

Internal reset

75

MB90335 Series

(3) Power-on reset

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min

Max

Power supply rising time

t^R

VCC

0.05

30

ms

⎯

Waiting time

until power-on

Power supply shutdown time

tOFF

1

⎯

Notes : • V^CCmust be lower than 0.2 V before the power supply is turned on.

• The above standard is a value for performing a power-on reset.

• In the device, there are internal registers which is initialized only by a power-on reset. When the initial

ization of these items is expected, turn on the power supply according to the standards.

tR

2.7 V

0.2 V

VCC

0.2 V

t^OFF

Note : Sudden change of power supply voltage may activate the power-on reset function.

When changing the power supply voltage during operation as illustrated below, voltage fluctuation should

be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL

clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.

VCC

The rising edge should be 50 mV/ms

or less.

3.0 V

RAM data hold

VSS

76

MB90335 Series

(4) UART0, UART1 I/O extended serial timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

SCKx

8 t^CP

⎯

ns

SCKx

SOTx

SCK ↓ → SOT delay time

− 80

100

60

+ 80

⎯

Internal shift clock

Mode output pin is

C^L= 80 pF + 1 TTL

SCKx

SINx

Valid SIN → SCK ↑

ns

SCK ↑ → valid

SIN hold time

SCKx

SINx

⎯

Serial clock H pulse width

Serial clock L pulse width

t^SHSL

t^SLSH

SCKx, SINx

4 t^CP

⎯

ns

4 tCP

SCKx

SOTx

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

External shift clock

Mode output pin is

C^L= 80 pF + 1 TTL

⎯

60

150

⎯

ns

SCKx

SINx

SCK ↑ → valid

SIN hold time

SCKx

SINx

⎯

Notes : • Above rating is the case of CLK synchronous mode.

• C^Lis a load capacitance value on pins for testing.

• t^CPis the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

77

MB90335 Series

(5) I²C timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Conditions

Unit

Min

Max

SCL clock frequency

f^SCL

0

100

kHz

(Repeat) [start] condition hold

time

SDA ↓ → SCL ↓

t^HDSTA

4.0

⎯

µs

Power-supply of external pull-up resistor

at 5.0 V

R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

SCL clock “L” width

SCL clock “H” width

t^LOW

t^HIGH

4.7

4.0

⎯

µs

Repeat [start] condition setup time

SCL ↑ → SDA ↓

t^SUSTA

t^HDDAT

R = 1.0 kΩ, C = 50 pF*²

4.7

0

⎯

µs

Data hold time

SCL ↓ → SDA ↓ ↑

3.45*³

Power-supply of external pull-up resistor

at 5.0 V

f^CP*¹≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

250*⁴

200*⁴

⎯

f^CP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

Data setup time

SDA ↓ ↑ → SCL ↑

t^SUDAT

ns

Power-supply of external pull-up resistor

at 5.0 V

f^CP*¹> 20 MHz, R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

f^CP*¹> 20 MHz, R = 1.0 kΩ, C = 50 pF*²

[Stop] condition setup time

SCL ↑ → SDA ↑

Power-supply of external pull-up resistor

at 5.0 V

t^SUSTO

4.0

4.7

⎯

µs

R = 1.2 kΩ, C = 50 pF*²

Power-supply of external pull-up resistor

at 3.6 V

Bus free time between [stop]

condition and [start] condition

t^BUS

R = 1.0 kΩ, C = 50 pF*²

*1 : f^CPis internal operating clock frequency. Refer to “ (1) Clock input timing”.

*2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance.

*3 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

*4 : Refer to “• Note of SDA, SCL set-up time”.

78

MB90335 Series

•Note of SDA, SCL set-up time

SDA

Input data set-up time

SCL

6 tcp

Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on

the load capacitance or pull-up resistor.

Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be

satisfied.

•Timing definition

SDA

tBUS

tHDSTA

tLOW

tSUDAT

SCL

tHDSTA

tHDDAT

tHIGH

tSUSTA

tSUSTO

79

MB90335 Series

(6) Timer Input Timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Min

Max

tTIWH

tTIWL

Input pulse width

PWC

⎯

4 tCP

⎯

ns

Note : t^CPis the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.

0.8 VCC

0.2 VCC

PWC

tTIWH

tTIWL

(7) Timer output timing

Parameter

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Pin name

Conditions

Unit

Min

Max

CLK ↑ → T^OUTchange time

PPG0 to PPG3 change time

t^TO

PPGx

⎯

30

⎯

ns

2.4 V

CLK

t

TO

2.4 V

0.8 V

PPGx

(8) Trigger Input Timing

(V^CC= 3.3 V 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min

5 t^CP

1

Max

⎯

ns

At normal operating

At Stop mode

t^TRGH

Input pulse width

INTx

⎯

tTRGL

⎯

µs

Note : t^CPis the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.

0.8 VCC

0.2 VCC

INTx

tTRGH

tTRGL

80

MB90335 Series

5. USB characteristics

Parameter

(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = 0 °C to +70 °C)

Value

Sym-

bol

Symbol

Unit

Remarks

Min

2.0

⎯

Max

⎯

Input High level voltage

Input Low level voltage

Differential input sensitivity

V^IH

V^IL

V^DI

V

0.8

⎯

Input

characteristics

0.2

0.8

2.8

0.0

1.3

4

V

Differential common mode range V^CM

2.5

3.6

0.3

2.0

20

V

Output High level voltage

Output Low level voltage

Cross over voltage

V^OH

V^OL

V^CRS

t^FR

V

IOH = −200 µA

IOL = 2 mA

V

ns

%

Ω

Full Speed

Low Speed

Full Speed

Low Speed

(TFR/TFF)

Rise time

Fall time

t^LR

75

4

300

20

Output

characteristics

t^FF

t^LF

75

90

80

28

300

111.11

125

44

t^RFM

t^RLM

Z^DRV

Rising/falling time matching

Output impedance

(TLR/TLF)

Including Rs = 27 Ω

Recommended value

= 27 Ω at using USB*

Series resistance

R^S

25

30

Ω

* : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV.

• Data signal timing (Full Speed)

Fall time

Rise time

DVP/HVP

DVM/HVM

90%

Vcrs

10%

tFF

tFR

• Data signal timing (Low Speed)

Rise time

Fall time

HVP

90%

Vcrs

10%

HVM

tLF

tLR

81

MB90335 Series

• Load condition (Full Speed)

Testing point

Z^USB

RS = 27 Ω

DVP/HVP

DVM/HVM

C^L= 50 pF

ZUSB

Testing point

CL = 50 pF

• Load condition (Low Speed)

Testing point

ZUSB

RS = 27 Ω

HVP

C^L= 50 pF ∼ 150 pF

Testing point

ZUSB

RS = 27 Ω

HVM

C^L= 50 pF ∼ 150 pF

82

MB90335 Series

6. Flash memory write/erase characteristics

Value

Typ

Parameter

Condition

Unit

Remarks

Min

Max

Sector erase time

(4 Kbytes sector)

Excludes 00^Hprogramming

prior to erasure.

⎯

0.2

0.5

2.6

0.5

s

Sector erase time

(16 Kbytes sector)

Excludes 00^Hprogramming

prior to erasure.

⎯

7.5

TA = + 25 °C

V^CC= 3.0 V

Excludes 00^Hprogramming

prior to erasure.

Chip erase time

⎯

Word (8 bits width)

programming time

Except for over head time of

system

⎯

10000

20

16

⎯

3600

⎯

µs

Program/erase cycle

⎯

cycle

year

Average

T^A= + 85 °C

Flash data retention time

⎯

*

* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C)

83

MB90335 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F337PFM

MB90337PFM

64-pin plastic LQFP

(FPT-64P-M09)

299-pin ceramic PGA

(PGA-299C-A01)

MB90V330A

For evaluation

84

MB90335 Series

■ PACKAGE DIMENSION

64-pin plastic LQFP

Lead pitch

0.65 mm

Package width ×

package length

12 × 12 mm

Gullwing

Lead shape

Sealing method

Mounting height

Plastic mold

1.70 mm MAX

P-LQFP64-12×12-0.65

Code

(Reference)

(FPT-64P-M09)

64-pin plastic LQFP

(FPT-64P-M09)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

14.00±0.20(.551±.008)SQ

*12.00±0.10(.472±.004)SQ

0.145±0.055

(.0057±.0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.25(.010)

INDEX

0~8˚

64

17

0.50±0.20

(.020±.008)

0.10±0.10

(.004±.004)

(Stand off)

"A"

1

16

0.60±0.15

(.024±.006)

0.65(.026)

0.32±0.05

(.013±.002)

M

0.13(.005)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F64018S-c-3-5

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

85

MB90335 Series

■ MAIN CHANGES IN THIS EDITION

Page

Section

■ PRODUCT LINEUP

Change Results

Changed VBUS to UTEST.

4

5

7

■ PIN ASSIGNMENT

■ PIN DESCRIPTION

Changed the description;

Pin no. 56, 57, 58

Data input pin for simple serial I/O

→ Data input pin for extended I/O serial interface

Pin no. 1

For pin name, VBUS → UTEST

For status at reset/ function, VBUS → UTEST input

For function, “ Status detection pin of USB

cable (withstand voltage of 5 V)” → “USB test pin.

Connect this to a pull-down resistor during normal

usage.”

10

■ HANDLING DEVICES

5. About crystal oscillator circuit

Added at the end of the section;

Please ask the crystal maker to evaluate the

oscillational characteristics of the crystal and this

device.

12

16

■ BLOCK DIAGRAM

Changed VBUS to UTEST.

■ I/O MAP

Address 000060^H

For the register, PWC Dividing Ratio Register →

PWC Dividing Ratio Control Register

17

Address 000072^H

For the register, I²C Bus Clock Selection Register →

I²C Bus Clock Control Register

Address 0000A0^H

For the register, Low Power Consumption Mode

Register → Low Power Consumption Mode Control

Register

Address 0000A8^H

Address 0000AE^H

For the register, Watchdog Control Register →

Watchdog Timer Control Register

For the register abbreviation,

FMCR → FMCS

18

19

Address 0000D1^H

Address 0000D2^H

Address 0000D3H

Address 0000DFH

Address 0000E0H

Address 0000E4H

Address 0000E5H

Prohibited → UDC Control Register

For the initial value, X1000000B → 01000000B

For the initial value, XXXX000XB → XXXX0000B

For the initial value, 00000000B → XXXXX000B

For the initial value, 00000000B → XX000000B

For the initial value, XXXXXXXXB → 0XXXXXXXB

For the initial value, 100XX00XB → 100XX000B

Address 0000E9H, 0000EBH, 0000EDH, For the initial value, 1000000XB → 10000000B

0000EF^H

20

Address 00790CH

Address 00790D^H

For the register, Flash Program Control Register 0 →

Flash Memory Program Control Register 0

For the register, Flash Program Control Register 1 →

Flash Memory Program Control Register 1

(Continued)

86

MB90335 Series

Page

22

Section

Change Results

■ INTERRUPT SOURCES,

INTERRUPT VECTORS, AND

INTERRUPT CONTROL REGISTERS.

USB function 2

For the µDMAC, “2 to 6” → “2 to 6*²”.

23

Added the footnote of *2.

■ Content of USB Interruption Factor

USB function 2

Added the “ * ” and its footnote.

Deleted the VOFF, VON.

USB function 3

34

■ PERIPHERAL RESOURCES

5. Multifunction timer

• 8/16-bit PPG timer

PPG control register (PPGC0 to PPGC3) →

PPG operation mode control register (PPGC0 to

PPGC3)

PPG clock control register (PCS01, PCS23) →

PPG output control register (PPG01, PPG23)

38

41

• PWC timer

Ratio of dividing frequency control register (DIVR) →

PWC ratio of dividing frequency control register

(DIVR)

6. UART

Serial input/output register (SIDR0, SIDR1/SODR0,

SODR1) → Serial input/output data register (SIDR0,

SIDR1/SODR0, SODR1)

Serial data register (SSR0, SSR1) → Serial status

register (SSR0, SSR1)

45

47

8. I²C Interface

I²C bus clock selection register (ICCR0) → I²C bus

clock control register (ICCR0)

9. USB Function

Deleted the following list;

• Capable of detection of connection and

disconnection by monitoring the USB bus power line.

Changed the register list in UDC control register

(UDCC) and EP0 control register (EP0C).

48

49

Changed the register list in Time stamp register

(TMSP), UDC status register (UDCS), and UDC

Interrupt enable register (UDCIE).

For EP0O status register (EP0OS), changed to

“Reserved” for the bit8 and bit7 and changed the

initial value.

For EP1 status register (EP1S), changed to

“Reserved” for the bit12 and changed (R/W) to (R) in

the bit8 to bit0.

For EP2/3/4/5 status register (EP2S to EP5S),

changed to “Reserved” for bit12, bit8, bit7, (R/W) to

(R) for the bit6 to bit0, and changed the initial values.

51

10. USB Mini-HOST

Deleted all of the “USB” from the register names.

Changed the “USB retry timer setting register 0/1/2

(HRTIMER)” to “Retry timer setting register

(HRTIMER)”.

(Continued)

87

MB90335 Series

(Continued)

Page

Section

Change Results

52

■ PERIPHERAL RESOURCES

10. USB Mini-HOST

Deleted all of the “USB” from the register names.

Changed the “USB EOF setting register 0/1 (HEOF)”

to “EOF setting register (HEOF)”.

Changed the “USB token end point register

(HTOKEN)” to “Host token end point register

(HTOKEN)”.

65

68

19. 512 Kbits flash memory

Flash memory control register (FMCS) → Flash

memory control status register (FMCS)

■ ELECTRICAL CHARACTERISTICS

For “L” level average output current,

1. Absolute Maximum Ratings

I^OLAV“3” → IOLAV1 “4”, IOLAV2 “15/4.5”

For “L" level maximum total output current,

ΣI^OL“60” → ΣIOL “100”

For “L” level average total output current,

ΣI^OLAV“30” → ΣIOLAV “50”

For “H” level average output current,

I^OHAV“ − 3” → IOHAV1 “ − 4”, IOHAV2 “ − 15/ − 4.5”

For “H” level maximum total output current,

ΣI^OH“ − 60” → ΣIOH “ − 100”

For “H” level average total output current,

ΣI^OHAV“ − 30” → ΣIOHAV “ − 50”

Changed the footnote *3 “Applicable to pins :

P60 to P67, VBUS” to “Applicable to pins : P60 to

P67, UTEST”

69

70

Changed the “VBUS” to “UTEST” in the footnote

*4 “ • Note that analog system input/output pins other

than P60 to P67, DVP,DVM, HVP, HVM, UTEST,

HCON”.

2. Recommended Operating Conditions Deleted the “Series resistance”.

Changed the “VBUS” to “UTEST” in the footnote.

72

76

3. DC Characteristics

Added the “USB I/O output impedance”.

4. AC Characteristics

(3) Power-on reset

Changed the minimum value of the “Power supply

rising time” : “⎯” → “0.05”

78

81

(5) I²C timing

Added “*4” to the minimum value in the “Data setup

time SDA ↓↑→ SCL↑ ” Added the footnote :

*4 : Refer to “ • Note of SDA, SCL set-up time”.

5. USB characteristics

For the symbol of parameter, Output resistance of

Output characteristics → Output impedance of Out-

put characteristics.

Added the “Series resistance”.

82

84

Changed the figures of “ • Load condition

(Full Speed)” and “ • Load condition (Low Speed)”

■ ORDERING INFORMATION

Added the MB90V330A.

The vertical lines marked in the left side of the page show the changes.

88

MB90335 Series

MEMO

89

MB90335 Series

MEMO

90

MB90335 Series

MEMO

91

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0722, Japan

Tel: +81-3-5322-3347 Fax: +81-3-5322-3387

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

FUJITSU MICROELECTRONICS ASIA PTE LTD.

151 Lorong Chuan, #05-08 New Tech Park,

Singapore 556741

Tel: +65-6281-0770 Fax: +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

Europe

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm.3102, Bund Center, No.222 Yan An Road(E),

Shanghai 200002, China

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen,

Germany

Tel: +86-21-6335-1560 Fax: +86-21-6335-1605

http://cn.fujitsu.com/fmc/

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road

Tsimshatsui, Kowloon

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Hong Kong

Tel: +852-2377-0226 Fax: +852-2376-3269

http://cn.fujitsu.com/fmc/tw

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-

ing the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited Strategic Business Development Dept.


型号：	MB90335
厂家：	FUJITSU
描述：	16-bit Microcontroller 16位微控制器微控制器
文件：	总92页 (文件大小：876K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90335 [FUJITSU]

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MB90337PMC

MB90340

MB90340E

MB90340E

MB90340E_10

MB90341ASPFV

MB90341CE

MB90341CEPF