MB90428GPF_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13711-1E

16-Bit Original Microcontroller

CMOS

F²MC-16LX MB90420G/5G (A) Series

MB90423G/423GA/F423G/F423GA/V420G

MB90427G/427GA/428G/428GA/F428G/F428GA

■ DESCRIPTIONS

The FUJITSU MB90420G/5G (A) Series is a 16-bit general purpose high-capacity microcontroller designed for

vehicle meter control applications etc.

The instruction set retains the same AT architecture as the FUJITSU original F²MC-8L and F²MC-16L series, with

further refinements including high-level language instructions, expanded addressing mode, enhanced (signed)

multipler-divider computation and bit processing.

In addition, A 32-bit accumulator is built in to enable long word processing.

■ FEATURES

• 16-bit input capture (4 channels)

Detects rising, falling, or both edges.

16-bit capture register × 4

Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.

• 16-bit reload timer (2 channels)

16-bit reload timer operation (select toggle output or one-shot output)

Event count function selection provided

(Continued)

■ PACKAGES

Plastic QFP, 100-pin

Plastic LQFP, 100-pin

(FPT-100P-M06)

(FPT-100P-M05)

MB90420G/5G (A) Series

• Clock timer (main clock)

Operates directly from oscillator clock.

Compensates for oscillator deviation

Read/write enabled second/minute/hour register

Signal interrupt

• 16-bit PPG (3 channels)

Output pins (3) , external trigger input pin (1)

Output clock frequencies : f^CP, fCP/2², fCP/2⁴, fCP/2⁶

• Delay interrupt

Generates interrupt for task switching.

Interruptions to CPU can be generated/deleted by software setting.

• External interrupts (8 channels)

8-channel independent operation

Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.

• A/D converter

10-bit or 8-bit resolution × 8 channels (input multiplexed)

Conversion time : 6.13 µs or less (at f^CP= 16 MHz)

External trigger startup available (P50/INT0/ADTG)

Internal timer startup available (16-bit reload timer 1)

• UART (2 channels)

Full duplex double buffer type

Supports asynchronous/synchronous transfer (with start/stop bits)

Internal timer can be selected as clock (16-bit reload timer 0)

Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps

Synchronous : 500 Kbps, 1Mbps, 2Mbps (at f^CP= 16 MHz)

• CAN interface *¹

Conforms to CAN specifications version 2.0 Part A and B.

Automatic resend in case of error.

Automatic transfer in response to remote frame.

16 prioritized message buffers for data and messages for data and ID

Multiple message support

Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks

Supports up to 1 Mbps

CAN WAKEUP function (connects RX internally to INT0)

• LCD controller/driver (1 channel)

Segment driver and command driver with direct LCD panel (display) drive capability

• Low voltage/Program Looping detect reset *²

Automatic reset when low voltage is detected

Program Looping detection function

• Stepping motor controller (4 channels)

High current output for all channels × 4

Synchronized 8/10-bit PWM for all channels × 2

• Sound generator

8-bit PWM signal mixed with tone frequency from 8-bit reload counter.

PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at f^CP= 16MHz)

Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)

(Continued)

2

MB90420G/5G (A) Series

(Continued)

• Input/output ports

Push-pull output and Schmitt trigger input

Programmable in bit units for input/output or peripheral signals.

• Flash memory

Supports automatic programming, Embeded Algorithm^TM, write/erase/erase pause/erase resume instructions

Flag indicates algorithm completion

Minato Electronics flash writer

Boot block configuration

Erasable by blocks

Block protection by external programming voltage

*1 : MB90420G (A) series has 2 channels built-in, MB90425G (A) series has 1 channel built-in

*2 : Built-in to MB90420GA/5GA series only. Not built-in to MB90420G/5G series.

Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc.

3

MB90420G/5G (A) Series

■ PRODUCT LINEUP

• MB90420G (A) Series

Part number

MB90F423G *¹MB90F423GA *¹

MB90423G *²

MB90423GA *²

MB90V420G

Parameter

Configuration

CPU

Evaluation model

Flash ROM model

F²MC-16LX CPU

Mask ROM model

On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)

System clock

ROM

External

6 KB

Flash ROM 128 KB

6 KB

Mask ROM 128 KB

6 KB

RAM

CAN interface

2 channels

Yes

QFP100, LQFP100

Low voltage/

CPU operation

detection reset

No

Yes

Packages

PGA-256

No

Emulator dedicat-

ed power supply*

• MB90425G (A) Series

Part number

MB90F428G MB90F428GA MB90427G*²MB90427GA*²MB90428G*¹MB90428GA*¹

Parameter

Configuration

CPU

Flash ROM model

Mask ROM model

MC-16LX CPU

F²

On-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)

Minimum instruction execution time 62.5 ns (with 4 MHz oscillator × 4)

System clock

ROM

Flash ROM 128 KB

6 KB

Mask ROM 64 KB

4 KB

Mask ROM 128 KB

6 KB

RAM

CAN interface

1 channel

Low voltage/

CPU operation

detection reset

No

Yes

No

Yes

No

Yes

Packages

QFP100, LQFP100

Emulator dedicat-

ed power supply*

* : When used with evaluation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-507

Hardware Manual (2.7 “Emulator Dedicated Power Supply Pin”) .

*1 : Under development

*2 : Planned

4

MB90420G/5G (A) Series

■ PIN ASSIGNMENTS

(TOP VIEW)

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

VSS

SEG8

SEG9

SEG10

SEG11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

X0A

X1A

P57/SGA

RST

P56/SGO/FRCK

P55/RX0

P54/TX0

DVSS

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

DVCC

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DVSS

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

DVCC

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

DVSS

P36/SEG12

P37/SEG13

P40/SEG14

P41/SEG15

P42/SEG16

P43/SEG17

P44/SEG18

VCC

P45/SEG19

P46/SEG20

P47/SEG21

C

P90/SEG22

P91/SEG23

V0

P53/INT3

MD2

(FPT-100P-M06)

(Continued)

5

MB90420G/5G (A) Series

(Continued)

(TOP VIEW)

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RST

P56/SGO/FRCK

P55/RX0

P54/TX0

DVSS

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

VSS

SEG8

SEG9

SEG10

SEG11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

DVCC

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DVSS

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

DVCC

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

DVSS

P36/SEG12

P37/SEG13

P40/SEG14

P41/SEG15

P42/SEG16

P43/SEG17

P44/SEG18

VCC

P45/SEG19

P46/SEG20

P47/SEG21

C

(FPT-100P-M05)

6

MB90420G/5G (A) Series

■ PIN DESCRIPTIONS

Pin no.

Circuit

type

Symbol

Description

LQFP

80

QFP

82

X0

X1

High speed oscillator input pin.

A

High speed oscillator output pin.

81

83

Low speed oscillator input pin. If no oscillator is connected, apply

pull-down processing.

78

80

X0A

X1A

A

Low speed oscillator output pin. If no oscillator is connected, leave

open.

77

75

79

77

RST

P00

B

Reset input pin.

General purpose input/output port.

UART ch.0 serial data input pin.

INT4 external interrupt input pin.

General purpose input/output port.

UART ch.0 serial data output pin.

INT5 external interrupt input pin.

General purpose input/output port.

UART ch.0 serial clock input/output pin.

INT6 external interrupt input pin.

General purpose input/output port.

UART ch.1 serial data input pin.

INT7 external interrupt input pin.

General purpose input/output port.

UART ch.1 serial data output pin.

General purpose input/output port.

UART ch.1 serial clock input/output pin.

16-bit PPG ch.0-2 external trigger input pin.

General purpose input/output port.

16-bit PPG ch.0 output pin.

83

84

85

86

87

SIN0

INT4

P01

G

SOT0

INT5

P02

G

SCK0

INT6

P03

86

87

88

89

90

SIN1

INT7

P04

G

SOT1

P05

SCK1

TRG

P06

89

91

PPG0

TOT1

P07

G

16-bit reload timer ch.1 TOT output pin.

General purpose input/output port.

16-bit PPG ch.1 output pin.

90

91

92

93

PPG1

TIN1

P10

G

16-bit reload timer ch.1 TIN output pin.

General purpose input/output port.

16-bit PPG ch.2 output pin.

PPG2

(Continued)

7

MB90420G/5G (A) Series

Pin no.

Circuit

Symbol

type

Description

General purpose input/output port.

LQFP

QFP

P11

TOT0

92

94

G

16-bit reload timer ch.0 TOT output pin.

Real-time clock timer WOT output pin.

General purpose input/output port.

16-bit reload timer ch.0 TIN output pin.

Input capture ch.3 trigger input pin.

General purpose input/output ports.

Input capture ch.0-2 trigger input pins.

WOT

P12

93

95

TIN0

G

IN3

P13 to P15

IN2 to IN0

94 to 96 96 to 98

99 to 100, COM0 to

97 to 100

1 to 8,

I

LCD controller/driver common output pins.

1 to 2

COM3

3 to 10,

10 to 13 12 to 15

SEG0 to

SEG11

LCD controller/driver segment output pins.

General purpose output ports.

P36 to P37

14 to 15 16 to 17

E

SEG12 to

SEG13

LCD controller/driver segment output pins.

General purpose input output ports.

LCD controller/driver segment output pins.

General purpose input output ports.

LCD controller/driver segment output pins.

P40 to P47

16 to 20, 18 to 22,

22 to 24 24 to 26

SEG14 to

SEG21

P90 to P91

26 to 27 28 to 29

SEG22 to

SEG23

P50

INT0

General purpose input output ports.

INT0 external interrupt input pin.

34

36

G

F

ADTG

A/D converter external trigger input pin.

General purpose input output ports.

P60 to P67

36 to 39, 38 to 41,

41 to 44 43 to 46

AN0 to

AN7

A/D converter input pins.

P51

INT1

(RX1 *)

P52

General purpose input output port.

INT1 external interrupt input pin.

CAN interface 1 RX intput pin.

General purpose input output port.

INT2 external interrupt input pin.

CAN interface 1 TX output pin.

General purpose input output port.

INT3 external interrupt input pin.

45

47

G

46

50

48

52

INT2

(TX1 *)

P53

G

INT3

* : MB90420G (A) series only.

(Continued)

8

MB90420G/5G (A) Series

Pin no.

LQFP QFP

Circuit

type

Symbol

Description

P70 to P73

General purpose input output ports.

PWM1P0

PWM1M0

PWM2P0

PWM2M0

52 to 55 54 to 57

57 to 60 59 to 62

62 to 65 64 to 67

67 to 70 69 to 72

H

Stepping motor controller ch.0 output pins.

General purpose input output ports.

P74 to P77

PWM1P1

PWM1M1

PWM2P1

PWM2M1

Stepping motor controller ch.1 output pins.

General purpose input output ports.

P80 to P83

PWM1P2

PWM1M2

PWM2P2

PWM2M2

Stepping motor controller ch.2 output pins.

General purpose input output ports.

P84 to P87

PWM1P3

PWM1M3

PWM2P3

PWM2M3

Stepping motor controller ch.3 output pins.

P54

TX0

General purpose input output port.

CAN interface 0 TX output pin.

72

73

74

75

G

P55

General purpose output port.

RX0

CAN interface 0 RX input pin.

P56

General purpose input output port.

Sound generator SG0 output pin.

Free-run timer clock input pin.

74

76

78

SGO

FRCK

P57

G

General purpose input output port.

Sound generator SGA output pin.

LCD controller /driver reference power supply pins.

SGA

V0 to V3

28 to 31 30 to 33

56, 66 58, 68

51, 61, 71 53, 63, 73

High current output buffer with dedicated power supply input pins

(pin numbers 54-57, 59-62, 64-67, 69-72) .

DV^CC

DV^SS

High current output buffer with dedicated power supply GND pins

(pin numbers 54-57, 59-62, 64-67, 69-72) .

32

35

33

34

37

35

AVCC

AVSS

A/D converter dedicated power supply input pin.

A/D converter dedicated GND supply pin.

A/D converter Vref + input pin. Vref − AVss.

(Continued)

AVRH

9

MB90420G/5G (A) Series

(Continued)

Pin no.

Circuit

Symbol

type

Description

LQFP

QFP

47

48

49

50

MD0

MD1

B *

D *

Test mode input pins. Connect to V^CC.

Text mode input pin. Connect to V^SS.

49

51

MD2

External capacitor pin. Connect an 0.1 µF capacitor between this

pin and VSS.

25

27

C

21, 82

23, 84

V^CC

V^SS

Power supply input pins.

GND power supply pins.

9, 40, 79 11, 42, 81

* : Type C in the flash ROM models.

10

MB90420G/5G (A) Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistance :

approx. 1 MΩ

X1

X0

A

Standby control signal

• Pull-up resistance attached :

approx. 50 kΩ, hysteresis input

B

C

Hysteresis input

• Hysteresis input

• Pull-down resistance attached :

approx. 50 kΩ, hysteresis input

• No pull-down resistance on flash

models.

Hyteresis input

D

• CMOS output

• LCDC output

• Hysteresis input

E

LCDC output

Hysteresis input

(Continued)

11

MB90420G/5G (A) Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• Hysteresis input

• Analog input

F

Analog input

Hysteresis input

• CMOS output

• Hysteresis input

G

Hysteresis input

• CMOS high current output

• Hysteresis input

High current

H

Hysteresis input

• LCDC output

I

LCDC output

12

MB90420G/5G (A) Series

■ HANDLING DEVICES

When handling semiconductor devices, care must be taken with regard to the following ten matters.

• Strictly observe maximum rated voltages (prevent latchup)

• Stable supply voltage

• Power-on procedures

• Treatment of unused input pins

• Treatment of A/D converter power supply pins

• Use of external clock signals

• Power supply pins

• Proper sequence of A/D converter power supply analog input

• Handling the power supply for high-current output buffer pins (DV^CC, DVSS)

• Pull-up/pull-down resistance

• Precautions when not using a sub clock signal.

Precautions for Handling Semiconductor Devices

• Strictly observe maximum rated voltages (prevent latchup)

When CMOS integrated circuit devices are subjected to applied voltages higher than V^CCat input and output

pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in

excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup

condition, supply current can increase dramatically and may destroy semiconductor elements. In using semi-

conductor devices, always take sufficient care to avoid exceeding maximum ratings.

Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power

supply (AV^CC, AVRH, DVCC) and analog input do not exceed the digital power supply (VCC) .

Once the digital power supply (VCC) is switched on, the analog power (AVCC,AVRH,DVCC) may be turned on in

any sequence.

• Stable supply voltage

Even within the warranted operating range of V^CCsupply voltage, sudden fluctuations in supply voltage can

cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial fre-

quencies (50 to 60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur during

switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.

• Power-on procedures

In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during power-

on should be attained within 50 µs (0.2 V to 2.7 V) .

• Treatment of unused input pins

If unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanent

damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least

2 kΩ.

Also any unused input/output pins should be left open in output status, or if found set to input status, they should

be treated in the same way as input pins.

• Treatment of A/D converter power supply pins

Even if the A/D converter is not used, pins should be connected so that AV^CC= VCC, and AVSS = AVRH = VSS.

13

MB90420G/5G (A) Series

• Use of external clock signals

Even when an external clock is used, a stabilization period is required following a power-on reset or release

from sub clock mode or stop mode. Also, when an external clock is used it should drive only the X0 pin and the

X1 pin should be left open, as shown in Figure 3.

X0

OPEN

X1

MB90420G/425G (A) Series

Sample external clock connection

• Power supply pins

Devices are designed to prevent problems such as latchup when multiple V^CCand VSS supply pins are used, by

providing internal connections between pins having the same potential. However, in order to reduce unwanted

radiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total

output current ratings, all such pins should always be connected externally to power supplies and ground.

As shown in Figure 4, all V^CCpower supply pins must have the same potential. All VSS power supply pins should

be handled in the same way. If there are multiple VCC or VSS systems, the device will not operate properly even

within the warranted operating range.

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power supply input pins (VCC/VSS)

In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as little

impedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC and

VSS as close to the pins as possible.

• Proper sequence of A/D converter power supply analog input

A/D converter power (AVCC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply

(VCC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut off

before the digital power supply is switched on (VCC) . In both power-on and shut-off, care should be taken that

AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input ports, be

sure that the input voltage does not exceed AVCC. (There is no problem if analog power supplies and digital

power supplies are turned off and on at the same time.)

14

MB90420G/5G (A) Series

• Handling the power supply for high-current output buffer pins (DV^CC, DV^SS)

Always apply power to high-current output buffer pins (DV^CC, DVSS) after the digital power supply (VCC) is turned

on. Also when switching power off, always shut off the power supply to the high-current output buffer pins (DVCC,

DVSS) before switching off the digital power supply (VCC) . (There will be no problem if high-current output buffer

pins and digital power supplies are turned off and on at the same time.)

Even when high-current output buffer pins are used as general purpose ports, the power for high current output

buffer pins (DV^CC, DVSS) should be applied to these pins.

• Pull-up/pull-down resistance

The MB90420G/5G series does not support internal pull-up/pull-down resistance. If necessary, use external

components.

• Precautions for when not using a sub clock signal.

If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave

the X1A pin open.

15

MB90420G/5G (A) Series

■ BLOCK DIAGRAM

X0, X1

Clock control

X0A, X1A

CPU

F²MC-16LX core

circuit

RST

Interrupt

controller

RAM

Low voltage

detector reset

ROM

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

Sound generator

P57/SGA

P56/SGO/FRCK

P55/RX0

P54/TX0

P53/INT3

P52/INT2 (/TX1)

P51/INT1 (/RX1)

P50/INT0/ADTG

Port 8

CAN controller

Port 5

Stepping

motor

Controller

0/1/2/3

External interrupt

(8 ch)

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

P73/PWM2M0

P72/PWM2P0

P71/PWM1M0

P70/PWM1P0

P00/SIN0/INT4

P01/SOT0/INT5

P02/SCK0/INT6

P03/SIN1/INT7

P04/SOT1

P05/SCK1/TRG

P06/PPG0/TOT1

P07/PPG1/TIN1

UART0/1

Prescaler

0/1

Port 7

Port 6

Port 0

P67 - P60/

AN7 - AN0

AVCC/AVSS

AVRH

A/D converter

(8 ch)

PPG0/1/2

Port 1

P10/PPG2

P11/TOT0/WOT

P12/TIN0/IN3

P13/IN2

P14/IN1

P15/IN0

P91 - P90/

SEG23 - SEG22

Port 9

Port 4

Port 3

Reload timer

0/1

P47 - P40/

SEG21 - SEG14

Real-time

Clock timer

P37 - P36/

SEG13 - SEG12

ICU0/1/2/3

SEG11 - SEG0

COM3 - COM0

V3 - V0

Free-run timer

LCD controller/

driver

Evaluation device (MB90V420G)

No built-in ROM

Built-in RAM is 6 KB.

16

MB90420G/5G (A) Series

■ MEMORY MAP

Single chip mode

(with ROM mirror function)

000000H

0000C0H

Peripheral area

000100H

Register

RAM area

Address #2

003900H

004000H

Peripheral area

010000H

ROM area

(FF bank image)

FF0000H

Address #1

: Internal access memory

: Access prohibited

ROM area

FFFFFFH

Parts No.

Address #1

FE0000^H

FF0000H

FE0000H

FE0000H *

Address #2

001900H

001100H

001900H

MB90423G (A)

MB90427G (A)

MB90428G (A)

MB90F423G (A)

MB90F428G (A)

MB90V420G

* : MB90V420G has no built-in ROM. On the tool side this area may be considered a ROM

decoder.

Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The

image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of

small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address,

so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example

when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank

ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore

because the ROM data from FF4000H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is

recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH.

17

MB90420G/5G (A) Series

■ I/O MAP

• Other than CAN Interface

Address

00^H

Register name

Port 0 data register

Symbol Read/write Peripheral function Initial value

PDR0

PDR1

R/W

Port 0

Port 1

XXXXXXXX

- - XXXXXX

01^H

Port 1 data register

02^H

(Disabled)

03H

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

R/W

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

XX - - - - - -

XXXXXXXX

- - - - - -XX

04^H

05^H

06H

07^H

08H

09^H

0AH to

0FH

(Disabled)

10^H

11^H

12H

13H

14^H

15H

16^H

17H

18H

19^H

1AH

Port 0 direction register

Port 1 direction register

DDR0

DDR1

R/W

Port 0

Port 1

0 0 0 0 0 0 0 0

- - 0 0 0 0 0 0

(Disabled)

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Analog input enable

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

ADER

R/W

Port 3

Port 4

0 0 - - - - - -

0 0 0 0 0 0 0 0

- - - - - - 0 0

1 1 1 1 1 1 1 1

Port 5

Port 6

Port 7

Port 8

Port 9

Port 6, A/D

1BH to

1FH

(Disabled)

20^H

21^H

22H

23H

24^H

25^H

26H

27^H

28H

29H

A/D control status register lower

A/D control status register higher

A/D data register lower

ADCSL

ADCSH

ADCRL

ADCRH

R/W

R

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 1 0 1 XXX

XXXXXXXX

0 0 0 0 0 0 0 0

0 - - 0 0 0 0 0

(Continued)

A/D converter

A/D data register higher

R/W

Compare clear register

Timer data register

CPCLR

TCDT

16-bit free-run timer

Timer control status register lower

Timer control status register higher

TCCSL

TCCSH

18

MB90420G/5G (A) Series

Address

2A^H

2B^H

2C^H

2DH

2E^H

2F^H

Register name

Symbol Read/write Peripheral function Initial value

PPG0 control status register lower

PCNTL0

R/W

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 -

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 0 0 0 0 0 0

0 0 0 0 0 - 0 0

0 0 0 0 0 1 0 0

16-bit PPG0

16-bit PPG1

16-bit PPG2

PPG0 control status register higher PCNTH0

PPG1 control status register lower PCNTL1

PPG1 control status register higher PCNTH1

PPG2 control status register lower PCNTL2

PPG2 control status register higher PCNTH2

30H

External interrupt enable

External interrupt request

External interrupt level lower

External interrupt level higher

Serial mode register 0

ENIR

EIRR

31^H

External interrupt

32^H

ELVRL

ELVRH

SMR0

SCR0

33H

34H

35H

Serial control register 0

UART 0

Input data register 0/

Output data register 0

SIDR0/

SODR0

36^H

R/W

XXXXXXXX

37H

38H

39^H

Serial status register 0

Serial mode register 1

Serial control register 1

SSR0

SMR1

SCR1

R/W

0 0 0 0 1 0 0 0

0 0 0 0 0 − 0 0

0 0 0 0 0 1 0 0

UART1

Input data register 1/

Output data register 1

SIDR1/

SODR1

3AH

R/W

XXXXXXXX

0 0 0 0 1 0 0 0

3B^H

3CH

Serial status register 1

SSR1

(Disabled)

3DH

Clock division control register 0

CAN wake-up control register

Clock division control register 1

CDCR0

CWUCR

CDCR1

R/W

Prescaler

CAN

0 - - - 0 0 0 0

- - - - - - - 0

0 - - - 0 0 0 0

3E^H

3FH

Prescaler

40H to 4FH

50^H

Area reserved for CAN interface 0

Timer control status register 0 lower TMCSR0L

R/W

0 0 0 0 0 0 0 0

- - - 0 0 0 0 0

Timer control status register 0 high-

51H

TMCSR0H

R/W

er

16-bit reload timer 0

16-bit reload timer 1

52^H

53^H

54^H

XXXXXXXX

0 0 0 0 0 0 0 0

Timer register 0/

Reload register 0

TMR0/

TMRLR0

R/W

Timer control status register 1 lower TMCSR1L

R/W

Timer control status register 1 high-

55^H

TMCSR1H

- - - 0 0 0 0 0

er

56^H

57^H

58H

59H

XXXXXXXX

0 0 0 - - 0 0 0

0 0 0 0 0 0 0 0

(Continued)

Timer register 1/

Reload register 1

TMR1/

TMRLR1

R/W

Clock timer control register lower

Clock timer control register higher

WTCRL

WTCRH

R/W

Real-time

clock timer

19

MB90420G/5G (A) Series

Address

5A^H

5B^H

5C^H

5DH

5E^H

5F^H

60H

Register name

Sound control register lower

Sound control register higher

Frequency data register

Amplitude data register

Decrement grade register

Tone count register

Symbol Read/write Peripheral function Initial value

SGCRL

SGCRH

SGFR

R/W

0 0 0 0 0 0 0 0

0 - - - - - 0 0

XXXXXXXX

0 0 0 0 0 0 0 0

XXXXXXXX

0 0 0 0 0 0 0 0

Sound generator

SGAR

SGDR

SGTR

Input capture register 0

Input capture register 1

Input capture register 2

IPCP0

IPCP1

IPCP2

R

61^H

Input capture 0/1

Input capture 2/3

62^H

63^H

64H

65^H

66^H

Input capture register 3

IPCP3

ICS01

R

67^H

68H

Input capture control status 0/1

R/W

Input capture 0/1

Input capture 2/3

69^H

(Disabled)

6AH

6B^H

6CH

6DH

Input capture control status 2/3

ICS23

R/W

0 0 0 0 0 0 0 0

(Disabled)

LCDC control register lower

LCDC control register higher

LCRL

LCRH

R/W

0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0

LCD controller/

driver

Low voltage detect reset control

register

Low voltage

detect reset

6E^H

LVRC

R/W

W

1 0 1 1 1 0 0 0

X X X X X X X 1

6F^H

ROM mirror

ROMM

ROM mirror

70H to 7FH

Area reserved for CAN interface 1

Stepping motor

controller0

80^H

81H

82^H

83^H

84H

85^H

86^H

PWM control register 0

PWC0

PWC1

PWC2

PWC3

R/W

(Disabled)

R/W

(Disabled)

R/W

(Disabled)

R/W

(Disabled)

0 0 0 0 0 - - 0

Stepping motor

controller1

PWM control register 1

PWM control register 2

PWM control register 3

Stepping motor

controller2

Stepping motor

controller3

87^Hto

9DH

(Continued)

20

MB90420G/5G (A) Series

(Continued)

Address

Register name

Symbol Read/write Peripheral function Initial value

Address match

detection function

9E^H

ROM correction control register

PACSR

R/W

- - - - - 0 - 0

9F^H

A0^H

A1H

Delay interrupt/release

Power saving mode

Clock select

DIRR

R/W

Delayed interrupt

- - - - - - - 0

0 0 0 1 1 0 0 0

1 1 1 1 1 1 0 0

LPMCR

CKSCR

Power saving

control circuit

A2^Hto

A7H

(Disabled)

A8^H

A9H

Watchdog control

WDTC

TBTC

R/W

Watchdog timer

Time base timer

XXXXX 1 1 1

1 - - 0 0 1 0 0

Time base timer control register

Clock timer

(sub clock)

AA^H

Clock timer control register

WTC

R/W

1 X 0 0 0 0 0 0

AB^Hto

ADH

(Disabled)

AE^H

AFH

B0H

B1^H

B2H

B3^H

B4H

B5H

B6^H

B7H

B8H

B9^H

BA^H

BBH

BCH

BD^H

BEH

BFH

Flash control register

FMCS

R/W

Flash interface

0 0 0 X 0 XX 0

(Disabled)

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

R/W

0 0 0 0 0 1 1 1

Interrupt controller

C0^Hto

FFH

(Disabled)

21

MB90420G/5G (A) Series

Address

1FF0^H

1FF1^H

1FF2^H

1FF3H

1FF4^H

1FF5^H

Register name

ROM correction address 0

ROM correction address 1

ROM correction address 2

ROM correction address 3

ROM correction address 4

ROM correction address 5

Symbol Read/write Peripheral function Initial value

PADR0

PADR1

R/W

XXXXXXXX

Address match

detection function

3900H to

391FH

(Disabled)

3920^H

3921^H

3922^H

3923^H

3924H

3925^H

1 1 1 1 1 1 1 1

XXXXXXXX

PPG0 down counter register

PPG0 cycle setting register

PPG0 duty setting register

PDCR0

PCSR0

PDUT0

R

W

16-bit PPG 0

16-bit PPG 1

16 bit PPG 2

3926H to

3927H

(Disabled)

3928^H

3929^H

392AH

392B^H

392CH

392D^H

1 1 1 1 1 1 1 1

XXXXXXXX

PPG1 down counter register

PPG1 cycle setting register

PPG1 duty setting register

PDCR1

PCSR1

PDUT1

R

W

392E^Hto

392FH

(Disabled)

3930^H

3931^H

3932H

3933^H

3934H

3935^H

1 1 1 1 1 1 1 1

XXXXXXXX

PPG2 down counter register

PPG2 cycle setting register

PPG2 duty setting register

PDCR2

PCSR2

PDUT2

R

W

3936^Hto

3959H

(Disabled)

(Continued)

22

MB90420G/5G (A) Series

Address

395A^H

395B^H

395C^H

395DH

395E^H

395F^H

Register name

Symbol Read/write Peripheral function Initial value

XXXXXXXX

Sub second data register

WTBR

R/W

XXXXXXXX

- - - XXXXX

- - XXXXXX

- - - XXXXX

Real time

clock timer

Second data register

Minute data register

Hour data register

WTSR

WTMR

WTHR

R/W

3960H to

396FH

LCD controller/

driver

LCD display RAM

VRAM

R/W

XXXXXXXX

3970^Hto

397FH

(Disabled)

3980^H

3981^H

3982H

3983^H

3984^H

3985H

XXXXXXXX

- - - - - - XX

XXXXXXXX

- - - - - - XX

- - 0 0 0 0 0 0

- 0 0 0 0 0 0 0

PWM1 compare register 0

PWM2 compare register 0

PWC10

PWC20

R/W

Stepping motor

controller 0

PWM1 select register 0

PWM2 select register 0

PWS10

PWS20

R/W

3986H to

3987H

(Disabled)

3988^H

3989^H

398A^H

398B^H

398CH

398D^H

XXXXXXXX

- - - - - - XX

XXXXXXXX

- - - - - - XX

- - 0 0 0 0 0 0

- 0 0 0 0 0 0 0

PWM1 compare register 1

PWM2 compare register 1

PWC11

PWC21

R/W

Stepping motor

controller 1

PWM1 select register 1

PWM2 select register 1

PWS11

PWS21

R/W

398EH to

398FH

(Disabled)

3990H

3991^H

3992^H

3993^H

3994H

3995^H

XXXXXXXX

- - - - - - XX

XXXXXXXX

- - - - - - XX

- - 0 0 0 0 0 0

- 0 0 0 0 0 0 0

PWM1 compare register 2

PWM2 compare register 2

PWC12

PWC22

R/W

Stepping motor

controller 2

PWM1 select register 2

PWM2 select register 2

PWS12

PWS22

R/W

3996H to

3997H

(Disabled)

(Continued)

23

MB90420G/5G (A) Series

(Continued)

Address

3998H

Register name

Symbol Read/write Peripheral function Initial value

XXXXXXXX

PWM1 compare register 3

PWC13

PWC23

R/W

3999^H

- - - - - - XX

XXXXXXXX

- - - - - - XX

- - 0 0 0 0 0 0

- 0 0 0 0 0 0 0

399A^H

399B^H

399C^H

399D^H

Stepping motor

controller 3

PWM2 compare register 3

PWM1 select register 3

PWM2 select register 3

PWS13

PWS23

R/W

399EH to

39FFH

(Disabled)

3A00^Hto

3AFFH

Area reserved for CAN interface 0

Area reserved for CAN interface 1

Area reserved for CAN interface 0

Area reserved for CAN interface 1

(Disabled)

3B00^Hto

3BFFH

3C00^Hto

3CFFH

3D00H to

3DFFH

3E00^Hto

3EFFH

• Initial value symbols :

“0” initial value 0.

“1” initial value 1.

“X” initial value undetermined

“-” initial value undetermined (none)

• Write/read symbols :

“R/W” read/write enabled

“R” read only

“W” write only

• Addresses in the area 0000^Hto 00FFH are reserved for the principal functions of the MCU. Read access

attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.

24

MB90420G/5G (A) Series

• I/O Map for CAN Interface

Address

Read/

write

Register name

Message buffer valid area

Transmission request register

Transmission cancel register

Transmission completed register

Receiving completed register

Remote request receiving register

Receiving overrun register

Receiving interrupt enable register

Control status register

Symbol

BVALR

TREQR

TCANR

TCR

Initial value

CAN0

CAN1

000040^H000070H

000041^H000071H

000042H 000072H

000043^H000073H

000044H 000074H

000045^H000075H

000046H 000076H

000047^H000077H

000048H 000078H

000049^H000079H

00004AH 00007AH

00004B^H00007BH

00004CH 00007CH

00004D^H00007DH

00004EH 00007EH

00004F^H00007FH

003C00H 003D00H

003C01^H003D01H

003C02H 003D02H

003C03^H003D03H

003C04H 003D04H

003C05^H003D05H

003C06H 003D06H

003C07^H003D07H

003C08H 003D08H

003C09^H003D09H

003C0AH 003D0AH

003C0B^H003D0BH

003C0CH 003D0CH

003C0D^H003D0DH

003C0EH 003D0EH

003C0F^H003D0FH

(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(W)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(R/W,R) 0 0 - - - 0 0 0 0 - - - - 0 - 1

RCR

RRTRR

ROVRR

RIER

CSR

Last event indicator register

RX/TX error counter

LEIR

(R/W)

(R)

- - - - - - - - 0 0 0 - 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTEC

BTR

Bit timing register

(R/W) - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IDE register

IDER

(R/W)

XXXXXXXX XXXXXXXX

Transmission RTR register

TRTRR

(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Remote frame receiving wait register RFWTR

Transmission interrupt enable register TIER

(R/W)

XXXXXXXX XXXXXXXX

(R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(Continued)

25

MB90420G/5G (A) Series

Address

Read/

write

Register name

Symbol

Initial value

CAN0

CAN1

003C10^H003D10H

003C11^H003D11H

003C12H 003D12H

003C13^H003D13H

003C14H 003D14H

003C15^H003D15H

003C16H 003D16H

003C17^H003D17H

003C18H 003D18H

003C19^H003D19H

003C1AH 003D1AH

003C1B^H003D1BH

003A00H 003B00H

XXXXXXXX XXXXXXXX

Acceptance mask select register

Acceptance mask register 0

AMSR

(R/W)

AMR0

AMR1

XXXXX- - -

XXXXXXXX

XXXXXXXX XXXXXXXX

Acceptance mask register 1

General purpose RAM

ID register 0

(R/W)

XXXXX- - -

XXXXXXXX

to

XXXXXXXX to XXXXXXXX

XXXXXXXX XXXXXXXX

003A1FH 003B1FH

003A20^H003B20H

003A21^H003B21H

003A22H 003B22H

003A23^H003B23H

003A24H 003B24H

003A25^H003B25H

003A26H 003B26H

003A27^H003B27H

003A28H 003B28H

003A29^H003B29H

003A2AH 003B2AH

003A2B^H003B2BH

003A2CH 003B2CH

003A2D^H003B2DH

003A2EH 003B2EH

003A2F^H003B2FH

003A30H 003B30H

003A31^H003B31H

003A32H 003B32H

003A33^H003B33H

IDR0

IDR1

IDR2

IDR3

IDR4

XXXXX- - -

XXXXXXXX

XXXXXXXX XXXXXXXX

ID register 1

ID register 2

ID register 3

ID register 4

(R/W)

XXXXX- - -

XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXXXXX XXXXXXXX

XXXXX- - -

XXXXXXXX

(Continued)

26

MB90420G/5G (A) Series

Address

CAN0 CAN1

Read/

write

Register name

Symbol

Initial value

003A34^H003B34H

003A35^H003B35H

003A36H 003B36H

003A37^H003B37H

003A38H 003B38H

003A39^H003B39H

003A3AH 003B3AH

003A3B^H003B3BH

003A3CH 003B3CH

003A3D^H003B3DH

003A3EH 003B3EH

003A3F^H003B3FH

003A40H 003B40H

003A41^H003B41H

003A42H 003B42H

003A43^H003B43H

003A44H 003B44H

003A45^H003B45H

003A46H 003B46H

003A47^H003B47H

003A48H 003B48H

003A49^H003B49H

003A4AH 003B4AH

003A4B^H003B4BH

003A4CH 003B4CH

003A4D^H003B4DH

003A4EH 003B4EH

003A4F^H003B4FH

003A50H 003B50H

003A51^H003B51H

003A52H 003B52H

003A53^H003B53H

XXXXXXXX

ID register 5

IDR5

(R/W)

XXXXX- - -

XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXX- - -

ID register 6

ID register 7

ID register 8

ID register 9

ID register 10

ID register 11

ID register 12

IDR6

IDR7

(R/W)

IDR8

IDR9

IDR10

IDR11

IDR12

XXXXXXXX

(Continued)

27

MB90420G/5G (A) Series

Address

Read/

write

Register name

Symbol

Initial value

CAN0

CAN1

003A54^H003B54H

003A55^H003B55H

003A56H 003B56H

003A57^H003B57H

003A58H 003B58H

003A59^H003B59H

003A5AH 003B5AH

003A5B^H003B5BH

003A5CH 003B5CH

003A5D^H003B5DH

003A5EH 003B5EH

003A5F^H003B5FH

003A60H 003B60H

003A61^H003B61H

003A62H 003B62H

003A63^H003B63H

003A64H 003B64H

003A65^H003B65H

003A66H 003B66H

003A67^H003B67H

003A68H 003B68H

003A69^H003B69H

003A6AH 003B6AH

003A6B^H003B6BH

003A6CH 003B6CH

003A6D^H003B6DH

003A6EH 003B6EH

003A6F^H003B6FH

003A70H 003B70H

003A71^H003B71H

003A72H 003B72H

003A73^H003B73H

003A74H 003B74H

003A75^H003B75H

XXXXXXXX

- - - -XXXX

ID register 13

ID register 14

ID register 15

IDR13

(R/W)

XXXXX- - -

XXXXXXXX

XXXXX- - -

XXXXXXXX

XXXXX- - -

- - - -XXXX

IDR14

IDR15

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLCR0

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

(R/W)

DLCR10 (R/W)

- - - -XXXX

(Continued)

28

MB90420G/5G (A) Series

Address

CAN0 CAN1

Read/

write

Register name

Symbol

Initial value

003A76^H003B76H

003A77^H003B77H

003A78H 003B78H

003A79^H003B79H

003A7AH 003B7AH

003A7B^H003B7BH

003A7CH 003B7CH

003A7D^H003B7DH

003A7EH 003B7EH

003A7F^H003B7FH

003A80H 003B80H

DLC register 11

DLCR11 (R/W)

DLCR12 (R/W)

DLCR13 (R/W)

DLCR14 (R/W)

DLCR15 (R/W)

- - - -XXXX

DLC register 12

DLC register 13

DLC register 14

DLC register 15

- - - -XXXX

to

Data register 0 (8 bytes)

Data register 1 (8 bytes)

Data register 2 (8 bytes)

Data register 3 (8 bytes)

Data register 4 (8 bytes)

Data register 5 (8 bytes)

Data register 6 (8 bytes)

Data register 7 (8 bytes)

Data register 8 (8 bytes)

Data register 9 (8 bytes)

DTR0

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

(R/W)

XXXXXXXX to XXXXXXXX

003A87H 003B87H

003A88^H003B88H

to

003A8FH 003B8FH

003A90^H003B90H

to

003A87H 003B97H

003A98^H003B98H

to

003A9FH 003B9FH

003AA0^H003BA0H

to

003AA7H 003BA7H

003AA8^H003BA8H

to

003AAF^H003BAF^H

003AB0^H003BB0H

to

003AB7^H003BB7^H

003AB8H 003BB8H

to

003ABFH 003BBFH

003AC0^H003BC0H

to

003AC7H 003BC7H

003AC8^H003BC8H

to

XXXXXXXX to XXXXXXXX

(Continued)

003ACF^H003BCF^H

29

MB90420G/5G (A) Series

(Continued)

Address

Read/

write

Register name

Symbol

Initial value

CAN0

003AD0^H003BD0H

to to

CAN1

Data register 10 (8 bytes)

Data register 11 (8 bytes)

Data register 12 (8 bytes)

Data register 13 (8 bytes)

Data register 14 (8 bytes)

Data register 15 (8 bytes)

DTR10

(R/W)

XXXXXXXX to XXXXXXXX

003AD7H 003BD7H

003AD8H 003BD8H

to

DTR11

DTR12

DTR13

DTR14

DTR15

XXXXXXXX to XXXXXXXX

003ADFH 003BDFH

003AE0^H003BE0H

to

003AE7H 003BE7H

003AE8^H003BE8H

to

003AEF^H003BEF^H

003AF0^H003BF0H

to

003AF7H 003BF7H

003AF8^H003BF8H

to

003AFFH 003BFFH

30

MB90420G/5G (A) Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt control register

Interrupt vector

EI²OS

compatible

Priority

Interrupt source

2

*

Number Address

#08 08^HFFFFDCH

#09 09H FFFFD8H

#10 0A^HFFFFD4H

#11 0B^HFFFFD0H

#12 0CH FFFFCCH

#13 0DH FFFFC8H

#14 0EH FFFFC4H

#15 0FH FFFFC0H

#16 10H FFFFBCH

#17 11H FFFFB8H

#18 12H FFFFB4H

#19 13H FFFFB0H

#20 14H FFFFACH

#21 15H FFFFA8H

#22 16H FFFFA4H

#23 17H FFFFA0H

#24 18H FFFF9CH

#25 19H FFFF98H

#26 1AH FFFF94H

#27 1BH FFFF90H

#28 1CH FFFF8CH

#29 1DH FFFF88H

#30 1EH FFFF84H

#31 1FH FFFF80H

#32 20H FFFF7CH

#33 21H FFFF78H

#34 22H FFFF74H

#35 23H FFFF70H

#36 24H FFFF6CH

#37 25H FFFF68H

#38 26H FFFF64H

#39 27H FFFF60H

#40 28H FFFF5CH

#41 29H FFFF58H

#42 2AH FFFF54H

ICR

Address

Reset

×

High

INT9 instruction

Exception processing

CAN0 RX

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

0000B0H *¹

0000B1H *¹

0000B2H *¹

0000B3H *¹

0000B4H *¹

0000B5H *¹

0000B6H *¹

0000B7H *¹

0000B8H *¹

0000B9H *¹

0000BAH *¹

0000BBH *¹

0000BCH *¹

0000BDH *¹

0000BEH *¹

0000BFH *¹

CAN0 TX/NS

CAN1 RX

CAN1 TX/NS

Input capture 0

DTP/external interrupt - ch 0 detected

Reload timer 0

DTP/external interrupt - ch 1 detected

Input capture 1

DTP/external interrupt - ch 2 detected

Input capture 2

DTP/external interrupt - ch 3 detected

Input capture 3

DTP/external interrupt - ch 4/5 detected

PPG timer 0

DTP/external interrupt - ch 6/7 detected

PPG timer 1

Reload timer 1

PPG timer 2

Real time clock timer

Free-run timer over flow

A/D converter conversion end

Free-run timer clear

Sound generator

×

Time base timer

Clock timer (sub clock)

UART 1 RX

UART 1 TX

UART 0 RX

UART 0 TX

Flash memory status

Delayed interrupt generator module

×

Low

31

MB90420G/5G (A) Series

: Compatible, with EI²OS stop function

: Compatible

: Compatible when interrupt sources sharing ICR are not in use

× : Not compatible

*1 : • Peripheral functions sharing the ICR register have the same interrupt level.

• If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other

cannot be used.

• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services,

the interrupt from the other function cannot be used.

*2 : Priority applies when interrupts of the same level are generated.

32

MB90420G/5G (A) Series

■ PERIPHERAL FUNCTIONS

1. I/O Ports

The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/O

pins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled in

bit units by the port direction register (DDR) as required. The following list shows each of the functions as well

as the shared peripheral function for each port.

• Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG)

• Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/clock timer/ICU)

• Port 3 : General purpose I/O port, shared with peripheral functions (LCD)

• Port 4 : General purpose I/O port, shared with peripheral functions (LCD)

• Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG)

• Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter)

• Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)

• Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller)

• Port 9 : General purpose I/O port, shared with peripheral functions (LCD)

(1) List of Functions

Input

format

Output

format

Port

Pin name

Function

bit15 bit14 bit13 bit12

General purpose I/O port

P00/SIN0/INT4

to P07/PPG1

Port 0

Peripheral function

General purpose I/O port

Peripheral function

P15

IN0

P14

IN1

P10/PPG2 to

P15/IN0

Port 1

CMOS

(hysteresis)

General purpose I/O port

Peripheral function

P37

P36

P36/SEG12 to

P37/SEG13

Port 3

Port 4

SEG13 SEG12

General purpose I/O port

Peripheral function

P40/SEG14 to

P47/SEG21

General purpose I/O port

P57

P56

SGO

FRCK

P55

RX0

P54

TX0

CMOS

P50/INT0 to

P57/SGA

Port 5

Port 6

SGA

Peripheral function

Analog

CMOS

(hysteresis)

General purpose I/O port

Peripheral function

P60/AN0 to

P67/AN7

General purpose I/O port

Peripheral function

P77

P76

P75

P74

P70/PWM1P0to

P77/PWM2M1

Port 7

Port 8

Port 9

PWM2M1 PWM2P1 PWM1M1 PWM1P1

General purpose I/O port

Peripheral function

P80/PWM1P2to

P87/PWM2M3

CMOS

(hysteresis)

General purpose I/O port

Peripheral function

P90/SEG22 to

P91/SEG23

33

MB90420G/5G (A) Series

(Continued)

Port bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

P07

P06

P05

P04

P03

P02

P01

P00

Port 0

PPG1 PPG0 SCK1 SOT1 SIN1 SCK0 SOT0 SIN0

TIN1 TOT1 INT7 INT6 INT5 INT4

P13

P12

IN3

P11

P10

Port 1 IN2

WOT PPG2

TOT0

TIN0

Port 3

Port 4

P47

P46

P45

P44

P43

P42

P41

P40

SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14

P53

P52

INT2

TX1

P51

INT1

RX1

P50

Port 5 INT3

INT0

P67

AN7

P66

AN6

P65

AN5

P64

AN4

P63

AN3

P62

AN2

P61

AN1

P60

AN0

Port 6

P73

P72

P71

P70

Port 7

PWM2M0 PWM2P0 PWM1M0 PWM1P0

P87

P86

P85

P84

P83

P82

P81

P80

Port 8

Port 9

PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 PWM1P2

P91

P90

SEG23 SEG22

Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write

“0” to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to “1” at reset.

34

MB90420G/5G (A) Series

(2) Block Diagrams

Ports 0, 1, 3, 4, 5, 7, 8, 9

Peripheral function output

Peripheral function input

Peripheral function output enabled

PDR (Port data register)

PDR read

PDR write

Output latch

DDR (Port direction register)

Direction

latch

DDR write

DDR read

Standby control (SPL = 1)

or LCD output enabled

Port 6

ADER

Analog input

PDR (Port data register)

RDR read

Output latch

PDR write

DDR (Port direction register)

Direction

latch

DDR write

DDR read

Standby control (SPL = 1)

35

MB90420G/5G (A) Series

2. Watchdog Timer/Time Base Timer/Clock Timer

The watchdog timer, timer base timer, and clock timer have the following circuit configuration.

• Watchdog timer : Watchdog counter, control register, watchdog reset circuit

• Time base timer : 18-bit timer, interval interrupt control circuit

• Clock timer

: 15-bit timer, interval interrupt control circuit

(1) Watchdog timer function

The watchdog timer is composed of a 2-bit watchdog counter that uses the carry signal from the 18-bit time

base timer or 15-bit clock timer as a clock source, plus a control register and watchdog reset control circuit.

After startup, this function will reset the CPU if not cleared within a given time.

(2) Time base timer function

The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count clock

(base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Other

functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or

other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS

bit or SCS bit in the CKSCR register.

(3) Clock timer function

The clock timer provides functions including a clock source for the watchdog timer, a sub clock base oscillator

stabilization wait timer, and an interval timer to generate an interrupt at fixed intervals. Note that the clock timer

uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.

36

MB90420G/5G (A) Series

• Block Diagram

Main base oscillator

divided by 2

TBTC

2¹¹

2¹³

Clock input

TBC1

TBC0

Selector

2¹⁶

2¹⁸

Time base timer

TBR

TBIE

TBOF

2¹¹2¹³2¹⁶2¹⁸

TBTRES

S

R

AND

Q

Time base

interrupt

WDTC

WT1

2-bit

counter

CLR

Watchdog reset

generator circuit

CLR

Selector

OF

To WDGRST

internal reset

generator circuit

WT0

WTE

WTC

AND

WDCS

SGW

Power-on reset,

sub-clock stop

S

R

SCE

Q

2¹⁰2¹³2¹⁴2¹⁶

2⁸

2⁹

2¹⁰

2¹¹

2¹²

2¹³

2¹⁴

2¹⁶

WTC2

WTC0

WTR

Selector

Clock timer

S

R

WTIE

AND

Q

WTOF

Clock input

WTRES

Clock interrupt

Sub base oscillator divided by 4

From power-on generator

WDTC

PONR

WRST

ERST

SRST

RST pin

From RST bit in STBYC

register

37

MB90420G/5G (A) Series

3. Input Capture

This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits.

(1) Input capture ( × 4)

The input capture circuits consist of four independent external input pins and corresponding capture registers

and control registers. When the specified edge of the external signal input (at the input pin) is detected, the value

of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be

generated.

• The valid edge (rising edge, falling edge, both edges) of the external signal can be selected.

• The four input capture circuits can operate independently.

• The interrupt can be generated from the valid edge of the external input signal.

(2) 16-bit free-run timer ( × 1)

The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and

prescaler. The output values from this counter are used as the base time for the input capture circuits.

• The counter clock operation can be selected from 8 options. The eight internal clock settings are φ, φ/2, φ/4,

φ/8, φ/16, φ/32, φ/64, φ/128 where φ represents the machine clock cycle.

• Interrupts can be generated from overflow events, or from compare match events with the compare register.

(Compare match operation requires a mode setting.)

• The counter value can be initialized to “0000^H” by a reset, soft clear, or a compare match with the compare

register.

(3) Block diagram

φ

interrupt

#31 (1FH)

Divider

Clock

IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0

16-bit free-run timer

Interrupt

#33 (21H)

16-bit compare clear register

Compare circuit

MSI3

0

ICLR ICRE

A/D startup

IN0/2

Edge detection

Capture data register 0/2

Capture data register 1/3

EG11

ICP1

EG10

EG01

EG00

Edge detection

IN1/3

ICP0

ICE0

ICE1

Interrupt

#19, #23

Interrupt

#15, #21

38

MB90420G/5G (A) Series

4. 16-bit Reload Timer

The 16-bit reload timer can either count down in synchronization with three types of internal clock signals in

internal clock mode, or count down at the detection of the designated edge of an external signal. The user may

select either function. This timer defines a transition from 0000H to FFFFH as an underflow event. Thus an

underflow occurs when counting from the value [Reload register setting + 1].

A selection of two counter operating modes are available. In reload mode, the counter is reset to the count value

and continues counting after an underflow, and in one-shot mode the count stops after an underflow. The counter

can generate an interrupt when an underflow occurs, and is compatible with the expanded intelligent I/O services

(EI²OS) .

(1) 16-bit Reload timer operating modes

Clock mode

Counter mode

16-bit reload timer operation

Reload mode

Soft trigger operation

External trigger operation

External gate input operation

Internal clock mode

One-shot mode

Reload mode

Event count mode

(external clock mode)

Soft trigger operation

One-shot mode

(2) Internal clock mode

One of three input clocks is selected as the count clock, and can be used in one of the following operations.

• Soft trigger operation

When “1” is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operation

starts.Trigger input at the TRG bit is normally valid with an external trigger input, as well as an external gate

input.

• External trigger operation

Count operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin.

• External gate input operation

Counting continues as long as the selected signal level (“L” or “H”) is input at the TIN0/1 pin.

(3) Event count mode (External clock mode)

In this mode a down count event occurs when a selected valid edge (rising, falling, both edges) is input at the

TIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used.

(4) Counter operation

• Reload mode

In down count operation, when an underflow event (transition from “0000^H” to “FFFFH”) occurs, the set count

value is reloaded and count operation continues. The function can be used as an interval timer by generating

an interrupt request at each underflow event. Also, a toggle waveform that inverts at each underflow can be

output from the TOT0/1 pin.

Counter clock

Internal clock

External clock

Counter clock period

2¹/φ (0.125 µs)

Interval time

0.125 µs to 8.192 ms

0.5 µs to 32.768 ms

2.0 µs to 131.1 ms

0.5 µs or greater

2³/φ (0.5 µs)

2⁵/φ (2.0 µs)

2³/φ or greater (0.5 µs)

φ : Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz.

39

MB90420G/5G (A) Series

(5) One-shot mode

In down count operation, the count stops when an underflow event (transition from “0000^H” to “FFFFH”) occurs.

This function can generate an interrupt at each underflow. While the counter is operating, a rectangular wave

form indicating that the count is in progress can be output form the TOT0 and TOT1 pins.

(6) Block diagram

Internal data bus

TMRLR0 *¹

16-bit reload register

Reload signal

Reload

control circuit

TMR0 *¹

<TMR1>

16-bit timer register (down counter)

UF

CLK

Count clock generator circuit

Gate input

Wait signal

Valid clock

decision circuit

Machine

clock φ

3

Prescaler

To UART 0, 1 *¹

CLK

Clear

Internal clock

External clock

Output signal

generator

Inverted

circuit

Input

control

circuit

Clock

selector

Pins

P11/TOT0 *¹

P12/TIN0 *¹

EN

Select

signal

3

2

Operation

control

Function selection

circuit

CSL1 CSL0 WOD2 WOD1 WOD0 OUTEOUTL RELD INTE UF CNTE TRG

1

Timer control status register (TNGSR0)

Interrupt

*

request signal

2

#17 (11h)

*

<#28 (10h)>

*1 : Channel 0 and channel 1. Figures in < > are for channel 1.

*2 : Interrupt number

40

MB90420G/5G (A) Series

5. Real Time Clock Timer

The real time clock timer is composed of a real time clock timer control register, sub second data register, second/

minute/hour data registers, 1/2 clock divider, 21-bit prescaler and second/minute/hour counters. Because the

MCU oscillation frequency operates on a given real time clock timer operation, a 4 MHz frequency is assumed.

The real time clock timer operates as a real world timer and provides real world time information.

• Block diagram

OE

Main oscillator clock

1/2 clock

21-bit

prescaler

WOT

divider

CO

EN

Sub second

register

UPDT

ST

Second

counter

LOAD

CI

EN

Hour

counter

Minute

counter

CO

6-bit

5-bit

Second/minute/hour register

INTE0 INT0

INTE1 INT1

INTE2 INT2

INT3 INT3

IRQ

41

MB90420G/5G (A) Series

6. PPG Timer

The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting,

and 16-bit compare register with buffer for duty setting, plus pin control circuits.

The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the output

pulse can be adjusted by rewriting the values in the two 16-bit registers.

(1) PWM function

Programmable to output a pulse, synchronized with a trigger.

Can also be used as a D/A converter with an external circuit.

(2) One-shot function

Detects the edge of a trigger input, and outputs a single pulse.

(3) Pin control

• Set to “1” at a duty match (priority) .

• Reset to “0” at a counter borrow event

• Has a fixed output mode to output a simple all “L” ( or “H”) signal.

• Polarity can be specified

(4) 16-bit down counter

• Select from four types of counter operation clocks. Four internal clocks (φ, φ/4, φ/16, φ/64) φ : Machine clock

cycles.

• The counter value can be initialized to “FFFF^H” at a reset or counter borrow event.

(5) Interrupt requests

• Timer startup

• Counter borrow event (period match)

• Duty match event

• Counter borrow event (period match) or duty match event

(6) Multiple channels can be set to start up at an external trigger, or to restart during operation.

42

MB90420G/5G (A) Series

(7) Block diagram

PCSR

PSCT

PDUT

Prescaler

1/1

1/4

Load

CK

1/16

1/32

CMP

16-bit down counter

Borrow

Start

PPG mask

Machine clock

PPG

output

S

R

Q

Inversion bit

Enable

Interrupt

selection

Interrupt

Trigger input

P05/TRG

Edge detection

Soft trigger

43

MB90420G/5G (A) Series

7. Delayed Interrupt Generator Module

The delayed interrupt generator module is a module that generates interrupts for task switching. This module

makes it possible to use software to generate/cancel interrupt requests to the F²MC-16LX CPU.

• Block diagram

F²MC-16LX bus

Delayed interrupt source generate/delete decoder

Source latch

44

MB90420G/5G (A) Series

8. DTP/External Interrupt Circuit

The DTP (Data transfer peripheral) /external interrupt circuit is located between an externally connected periph-

eral device and the F²MC-16LX CPU and sends interrupt requests or data transfer requests generated from the

peripheral device to the CPU, thereby generating external interrupt requests or starting the expanded intelligent

I/O services (EI²OS) .

(1) DTP/external interrupt function

The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source.

And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate an

external interrupt or start the expanded intelligent I/O service (EI²OS) .

When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI²OS) is

prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If the

EI²OS is permitted the interrupt functions as a DTP function, using EI²OS for automatic data transfer, then

branching to an interrupt routine after the completion of the specified number of data transfers.

External interrupt

DTP function

Input pins

8 pins (P50/INT0 to P53/INT3, P00/INT4 to P03 INT7)

Request level setting register (ELVR) sets the detection level, or selected edge for

each pin

Interrupt sources

“H” level/ “L” level/ rising edge/falling

“H” level/ “L” level input

edge input

Interrupt numbers

Interrupt control

Interrupt flags

#16 (10^H) , #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) , #26 (1AH)

DTP/interrupt enable register (ENIR) permits/prohibits interrupt request output

DTP/interrupt enable register (EIRR) stores interrupt sources

Process selection

When EI²OS prohibited (ICR : ISE = 0) When EI²OS is enabled (ICR : ISE = 1)

EI²OS performs automatic data transfer,

Branch to external interrupt processing

then after a specified number of cycles,

routine

Processing

branches to an interrupt routine

ICR : Interrupt control register

45

MB90420G/5G (A) Series

(2) Block diagram

Request level setting register (ELVR)

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

Selector

P03/INT7

P50/INT0

Selector

P02/INT6

P51/INT1

Selector

P01/INT5

P52/INT2

Selector Selector

P00/INT4

P53/INT3

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

Interrupt request number

#16 (10H)

#18 (12H)

#20 (14H)

#22 (16H)

#24 (18H)

#26 (1AH)

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

46

MB90420G/5G (A) Series

9. 8/10-bit A/D Converter

The 8/10-bit A/D converter has functions for using RC sequential comparator conversion format to convert analog

input voltage into 10-bit or 8-bit digital values. The input signal is selected from 8-channel analog input pins, and

the conversion start can be selected from three types : by software, 16-bit reload timer 1 or a trigger input from

an external signal pin.

(1) 8/10-bit A/D converter functions

The A/D converter takes analog voltage signals (input voltage) input at analog input pins, and converts these to

digital values, providing the following features.

• Minimum conversion time is 6.13 µs (at machine clock frequency of 16 MHz, including sampling time) .

• Minimum sampling time is 3.75 µs (at machine clock 16 MHz)

• The conversion method is an RC sequential conversion in comparison with a sample hold circuit.

• Either 10-bit or 8-bit resolution can be selected.

• The analog input pin can select from 8 channels by a program setting.

• At completion of A/D conversion, an interrupt request can be generated, or EI²OS can be started.

• Because the conversion data protection function operates in an interrupt enabled state, no data is lost even

in continuous conversion.

• The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external

trigger input (falling edge) .

Three conversion modes are available

Conversion mode

Single conversion operation

Scan conversion operation

Converts multiple consecutive channels (up

to 8 channels may be specified) one time,

then stops.

Converts the specified channel (1 channel

only) one time, then stops.

Single conversion mode

Continuous conversion Converts the specified channel (1 channel Converts multiple consecutive channels (up

mode

only) repeatedly.

to 8 channels may be specified) repeatedly.

Converts multiple consecutive channels (up

to 8 channels may be specified) , however

pauses after conversion of each channel,

waits until the next start is applied.

Converts the specified channel (1 channel

Stop conversion mode only) one time, then pauses, waits until

the next start is applied.

47

MB90420G/5G (A) Series

(2) Block diagram

AVCC

AVRH

AVSS

D/A converter

MPX

AN0

AN1

AN2

AN3

AN4

AN5

AN6

Sequential comparator

register

Comparator

AN7

Sample & hold circuit

A/D data register

ADCRH, L

A/D control status register, high

A/D control status register, low

Timer start

ADCSH, L

Operating clock

16-bit reload timer 1

Trigger start

P50/ADTG

φ

Prescaler

48

MB90420G/5G (A) Series

10. UART

The UART is a general purpose serial data communication interface for synchronous communication, or asyn-

chronous (start-stop synchronized) communication with external devices. Functions include normal bi-directional

functions, as well as master/slave type communication functions (multi-processor mode : master side only

supported) .

(1) UART Functions

The UART is a general purpose serial data communication interface for sending and receiving of serial data with

other CPU’s or peripheral devices, and provides the following functions.

Functions

Data buffer

Full duplex double buffer

• Clock synchronous (no start/stop bits)

• Clock asynchronous (start-stop synchronized)

Transfer modes

• Exclusive baud rate generator provides a selection of 8 rates

• External clock input enabled

Baud rate

• Internal clock (can use internal clock feed from 16-bit reload timer)

• 7-bit (asynchronous normal mode only)

• 8-bit

Data length

Signal type

NRZ (Non return to zero)

• Framing errors

Receiving error detection

• Overrun errors

• Parity errors (not enabled in multiprocessor mode)

• Receiving interrupt (receiving completed, receiving error detection)

• Sending interrupt (sending completed)

• Sending/receiving both compatible with expanded intelligent I/O services

(EI²OS)

Interrupt request

Master/slave type

communication function 1 (master) -to-n (slave) communication enabled (only master side supported) .

(multi-processor mode)

Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only.

Data length

Operating mode

Synchronization

Stop bit length

No parity

Parity

0

1

2

Normal mode

7-bit or 8-bit

Asynchronous

Synchronous

1-bit or 2-bit *²

None

Multi-processor mode

Normal mode

8 + 1 *¹

8

: Setting not available

*1 : “+” indicates an address/data selection bit (A/D) for communication control.

*2 : In receiving only one stop bit is detected.

49

MB90420G/5G (A) Series

(2) Block diagram

Control bus

Receiving

interrupt signals

#39 (27H) *

<#37 (25H) *>

Exclusive baud

rate generator

Sending clock

Sending

interrupt signals

#40 (28H) *

<#38 (26H) *>

Clock

selector

16-bit

reload timer

Receiving

clock

Receiving

control

circuit

Sending

control

circuit

Pins

P02/SCK0

Start bit

detection circuit

Sending start

circuit

Receiving bit

counter

Sending bit

counter

Receiving parity

counter

Sending parity

counter

P01/SOT0

Receiving

shift register

Sending

shift register

Pins

P00/SIN0

Rece-

iving

end

Sending start

SIDR0/1

SODR0/1

Receiving status

judging circuit

EI²OS receiving error

generator circuit (to CPU)

Internal data bus

MD1

MD0

CS2

CS1

CS0

PEN

P

PE

ORE

FRE

RDRF

TDRE

BOS

RIE

SBL

CL

A/D

REC

RXE

TXE

SMR0/1

register

SCR0/1

register

SSR0/1

register

SCKE

SOE

TIE

: Interrupt number

50

MB90420G/5G (A) Series

11. CAN Controller

The CAN controller is a self-contained module within a 16-bit microcomputer (F²MC-16LX) . The CAN (controller

area network) controller is the standard protocol for serial transmissions among automotive controllers and is

widely used in the industry.

(1) CAN controller features

The CAN controller has the following features.

• Conforms to CAN specifications version 2.0 A and B.

Supports sending and receiving in standard frame and expanded frame format.

• Supports data frame sending by means of remote frame receiving.

• 16 sending/receiving message buffers

29-bit ID and 8-byte data

Multi-level message buffer configuration

• Supports full bit compare, full bit mask as well as partial bet mask filtering.

Provides two receiving mask registers for either standard frame or expanded frame format.

• Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16 MHz)

• CAN WAKE UP function

• The MB90420G (A) series has a two-channel built-in CAN controller. The MB90425G (A) series has a 1-

channel built-in CAN controller.

51

MB90420G/5G (A) Series

(2) Block diagram

F²MC-16LX bus

TQ (operating clock)

Machine

clock

Prescaler 1-to-64

frequency divider

Bit timing generator

SYNC, TSEG1, TSEG2

PSC

PR

PH

BTR

RSJ

TOE

TS

RS

HALT

NIE

NT

IDLE, SUSPND,

TX, RX, ERR,

OVRLD

CSR

Bus

state

machine

Node status change

interrupt generator

Node status

change interrupt

NS1,0

Error

control

RTEC

Send/receive

sequencer

BVALR

TREQR

TBFx

clear

Error

frame

generator

Send buffer

decision

TBFX

Receiving

Data

counter

filter

Overload

frame

control

generator

TDLC RDLC IDSEL

TBFX

BITER, STFER,

CRCER, FRMER,

ACKER

Output

driver

TCANR

TRTRR

RFWTR

TCR

TX

ARBLOST

Send shift

register

Stuffing

TBFx, set, clear

ACK

generator

CRC

generator

Sending

completed

interrupt

TDLC

Sending completed

interrupt generator

TIER

CRCER

RBFx, set

RCR

RDLC

STFER

CRC generator

error check

Receiving

completed

interrupt

Receiving completed

interrupt generator

RIER

Receiving

shift register

Destuffing/

stuffing

error check

RBFx, TBFx, set clear

RRTRR

ROVRR

AMSR

AMR0

AMR1

RBFx

IDSEL

set

Arbitration

check

ARBLOST

BITER

Bit error

check

Acknowledge error

check

0

1

Receiving

Receiving bufferx

decision

PH1

filter

ACKER

FRMER

IDR0 ~ 15,

DLCR0 ~ 15,

DTR0 ~ 15,

RAM

RBFX

Form error

check

Input

latch

RX

RAM address

generator

RBFX, TBFX, RDLC, TDLC, IDSEL

LEIR

52

MB90420G/5G (A) Series

12. LCD Controller/Driver

The LCD controller/driver has a built-in 16 × 8-bit display data memory, and controls the LCD display by means

of four common outputs and 24 segment outputs. A selection of three duty outputs are available. This block can

drive an LCD (liquid crystal display) panel directly.

(1) LCD controller/driver functions

The LCD controller/driver provides functions for directly displaying the contents of display data memory (display

RAM) on the LCD panel by means of segment output and common output.

• LCD drive voltage divider resistance is built-in. External divider resistance can also be connected.

• Up to 4 common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to SEG23) can be used.

• 16-byte display data memory (display RAM) is built-in.

• The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) .

• Drives the LCD directly.

Bias

1/2 duty

1/3 duty

1/4 duty

×

1/2 bias

1/3 bias

×

: Recommended mode

× : Use prohibited

Note : When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting, they

cannot be used for segment output.

53

MB90420G/5G (A) Series

(2) Block diagram

V0 V1 V2 V3

LCDC control register L

(LCRL)

Divider resistance

4

COM0

COM1

COM2

COM3

Time base

timer output

Timing

controller

Prescaler

Common

driver

SEG0

SEG1

SEG2

SEG3

SEG4

24

Segment

driver

Display RAM,

16 × 8 bits

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

LCDC control register H

(LCRH)

Driver

Controller

54

MB90420G/5G (A) Series

13. Low voltage/Program Looping Detection Reset Circuit

The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when

a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal

is generated.

The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal

reset signal if not cleared within a given time after startup.

(1) Low voltage detection reset circuit

Detection voltage

4.0 V ± 0.3 V

When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an

internal reset signal is output.

Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage

condition generates an internal reset and releases stop mode.

During an internal RAM write cycle, an internal reset is generated after the completion of writing. During the

output of this internal reset, the reset output from the low voltage detection circuit is suppressed.

(2) Program Looping detection reset circuit

The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts

automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval

elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an

internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has

a width of 5 machine cycles.

Interval duration

Number of oscillation clock cycles

Approx. 262 ms *

2²⁰cycles

* : This value assumes an oscillation clock speed of 4 MHz.

During recovery from standby mode the detection period is the maximum interval plus 20 µs.

This circuit does not operate in modes where CPU operation is stopped.

The Program Looping detection reset circuit counter is cleared under any of the following conditions.

1. Writing “0” to the LVRC register CL bit

2. Internal reset

3. Main oscillation clock stop

4. Transition to sleep mode

5. Transition to time base timer mode or clock mode

6. Start of hold

55

MB90420G/5G (A) Series

(3) Block diagram

Voltage comparator

circuit

VCC

−

+

VSS

Constant

voltage

source

Program Looping detection circuit

Oscillation clock

Counter

OF

Internal reset

Noise canceller

Clear

RESV0 RESV0 RESV1 RESV1

CL

LVRF RESV0 CPUF

Low voltage detection reset control register (LVRC)

Internal data bus

56

MB90420G/5G (A) Series

14. Stepping Motor Controller

The stepping motor controller is composed of two PWM pulse generators, four motor drivers and selector logic

circuits.

The four motor drivers have a high output drive capacity and can be directly connected to the four ends of two

motor coils. They are designed to operate together with the PWM pulse generators and selector logic circuits

to control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse gener-

ators.

• Block diagram

Machine clock

OE1

Output enable

CK

EN

PWM1Pn

PWM1Mn

Prescaler

PWM1 pulse generator

PWM

Selector

P1

P0

PWM1 compare register

PWM2 pulse generator

PWM1 selector register

OE2

Output enable

CK

EN

SC

CE

PWM2Pn

PWM2Mn

Selector

PWM

Load

PWM2 compare register

BS

n : 0 ~ 3

PWM2 select register

57

MB90420G/5G (A) Series

15. Sound Generator

The sound generator is composed of a sound control register, frequency data register, amplitude data register,

decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter,

and tone pulse counter.

• Block diagram

Clock input

Prescaler

Frequency

counter

Toggle

flip-flop

8-bit PWM

pulse generator

CO

EN

PWM

CI

CO

EN

D

Q

EN

S1

S0

Reload

1/d

Frequency data

register

Amplitude data

register

DEC

Decrement

counter

CI

CO

EN

SGA

OE1

Decrement grade

register

Blend

SGO

OE2

Tone pulse

counter

TONE OE2

CI

CO

EN

INTE INT

ST

Tone count

register

IRQ

58

MB90420G/5G (A) Series

16. Address Match Detect Function

If the address setting is the same as the ROM correction address register, an INT9 instruction is executed. The

ROM correction function can be implemented by processing the INT9 interrupt service routine.

Two address registers are used, each with its own compare enable bit. When there is a match between the

address register and program counter, and the compare enable bit is set to “1” , the INT9 instruction is forcibly

executed by the CPU.

• Block diagram

Address latch

ROM correction

address register

Enable bit

F²MC-16LX

CPU core

F²MC-16LX bus

59

MB90420G/5G (A) Series

17. ROM Mirror Function Select Module

The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated

to the FF bank to be viewed in the 00 bank.

• Block diagram

F²MC-16LX bus

ROM mirror function select register

Address area

FF bank

00 bank

ROM

60

MB90420G/5G (A) Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(V^SS= AV^SS= DV^SS= 0 V)

Rating

Parameter

Symbol

Unit

Remarks

Min.

Max.

VSS + 6.0

VCC + 0.3

2.0

V^CC

AV^CC

VAVRH

DVCC

VI

VSS − 0.3

−2.0

V

AVCC = VCC*¹

AVCC ≥ VAVRH

DVCC = VCC*¹

Power supply voltage

V

Input voltage

Output voltage

Clamp current

V

V^O

V

ICLAMP

IOL1

mA

mW

°C

15

Other than P70-P77, P80-P87

P70-77, P80-87

“L”level maximum

output current*²

IOL2

40

IOLAV1

IOLAV2

ΣI^OL1

ΣI^OL2

ΣI^OLAV1

ΣIOLAV2

I^OH1*²

IOH2*²

I^OHAV1*³

IOHAV2*³

ΣI^OH1

ΣI^OH2

ΣI^OHAV1*⁴

ΣIOHAV2*⁴

PD

4

Other than P70-P77, P80-P87

P70-77, P80-87

“L”level average output

current*³

30

100

Other than P70-P77, P80-P87

P70-77, P80-87

“L”level maximum

total output current

330

50

Other than P70-P77, P80-P87

P70-77, P80-87

“L”level average total

output current

250

−15

Other than P70-P77, P80-P87

P70-77, P80-87

“H”level maximum

output current

−40

−4

Other than P70-P77, P80-P87

P70-77, P80-87

“H”level average

output current

−30

−100

−330

−50

Other than P70-P77, P80-P87

P70-77, P80-87

“H”level maximum

total output current

Other than P70-P77, P80-P87

P70-77, P80-87

“H”level average total

output current

−250

500

Power consumption

Operating temperature

Storage temperature

T^A

−40

−55

+105

+150

TSTG

°C

*1 : Care must be taken to ensure that AV^CCand DVCC do not exceed VCC at power-on etc.

*2 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.

*3 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times

“operating factor”.

*4 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins. The “average value” can be calculated from the formula of “operating current” times

“ operating factor”.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

61

MB90420G/5G (A) Series

2. Recommended Operating Conditions

Value

(VSS = DVSS = AVSS = 0.0 V)

Parameter

Symbol

Unit

Remarks

Min.

Max.

In normal operation:

4.5

5.5

V

(MB90F428G/F428GA, MB90428G/428GA,

MB90427G/427GA)

V^CC

AVCC

DVCC

Power supply

voltage

Holding stop operation status

(MB90F428G, MB90428G, MB90427G)

3.0

4.5

5.5

V

Holding stop operation status

(MB90F428GA, MB90428GA, MB90427GA)

Use a ceramic capacitor or other capacitor of

equivalent frequency characteristics. A

smoothing capacitor on the V^CCpin should

have a capacitance greater than Cs.

Smoothing

capacitor*

C^S

T^A

0.1

1.0

µF

Operating

temperature

−40

+105

°C

* : For smoothing capacitor Cs connections, see the illustration below.

• C pin connection

C

AVSS

VSS

DVSS

C^S

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

62

MB90420G/5G (A) Series

3. DC Characteristics

(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

name

Symbol

Parameter

Conditions

Unit

Remarks

Min.

Typ.

Max.

VCC + 0.3

0.6 VCC

VSS + 0.3

72

CMOS hysteresis

input pin*¹

V^IHS

VIHM

V^ILS

VILM

0.8 VCC

VCC − 0.3

VSS − 0.3

V

“H”level

input voltage

MD pin*²

CMOS hysteresis

input pin*¹

V

“L”level

input voltage

V

MD pin*²

MB90F428G/GA

MB90F423G/GA

45

38

15

13

mA

Operating frequency

F^CP= 16 MHz,

normal operation

ICC

MB90428G/GA

61

24

21

mA MB90427G/GA

MB90423G/GA

MB90F428G/GA

mA

MB90F423G/GA

Operating frequency

FCP = 16 MHz,

sleep mode

I^CCS

MB90428G/GA,

mA MB90427G/GA

MB90423G/GA

Power supply

current*³

Operating frequency

FCP = 2 MHz,

time base timer mode

VCC

I^CTS

0.75

0.35

40

1.0

0.7

mA

µA

Operating frequency

FCP = 8 kHz, TA = 25 °C,

subclock operation

I^CCL

Operating frequency

FCP = 8 kHz, TA = 25 °C,

sub sleep operation

I^CCLS

100

Operating frequency

FCP = 8 kHz, TA = 25 °C,

clock mode

I^CCT

40

µA

*1 : All input pins except X0, X0A, MD0, MD1, MD2 pins.

*2 : MD0, MD1, MD2 pins.

*3 : Current values are provisional, and may be changed without prior notice for purposes of characteristic improve

ment, etc. Supply current values assume external clock feed from the 1 pin and X1A pin. Users must be aware

that supply current levels differ depending on whether an external clock or oscillator is useed.

(Continued)

63

MB90420G/5G (A) Series

(Continued)

(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Typ.

Sym

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min.

Max.

MB90F428G

MB90F423G

5

20

µA MB90428G

MB90427G

MB90423G

Power supply

current *³

TA = 25 °C,

stop mode

ICCH

VCC

MB90F428GA

MB90F423GA

µA MB90428GA

MB90427GA

40

100

5

MB90423GA

Input leakage

current

VCC = DVCC = AVCC = 5.5 V

VSS < VI < VCC

I^IL

All input pins

−5

µA

Other than

Vcc, Vss,

Input

capacitance 1

DVcc, DVss,

Avcc,Avss,C,

P70 to P77,

P80 to P87

C^IN1

5

15

pF

Input

capacitance 2

P70 to P77,

P80 to P87

CIN2

15

50

45

pF

kΩ

Pull-up

resistance

RST, MD0,

MD1

R^UP

25

100

Pull-down

resistance

R^DOWNMD2

Other than

V^OH1P70 to P77,

P80 to P87

Output H

voltage 1

V^CC= 4.5 V

IOH = −4.0 mA

VCC −

0.5

V

Output H

voltage 2

P70 to P77,

V^OH2

VCC = 4.5 V

IOH = −30.0 mA

VCC −

0.5

P80 to P87

Other than

VOL1 P70 to P77,

P80 to P87

Output L

voltage 1

VCC = 4.5 V

IOL = 4.0 mA

0.4

0.5

Output L

voltage 2

P70 to P77,

V^OL2

VCC = 4.5 V

IOL = 30.0 mA

P80 to P87

*3: Current values are provisional, and may be changed without prior notice for purposes of characteristic improve

ment, etc. Supply current values assume external clock feed from the 1 pin and X1A pin. Users must be aware

that supply current levels differ depending on whether an external clock or oscillator is useed.

(Continued)

64

MB90420G/5G (A) Series

(Continued)

Value

Symbol

Parameter

Pin name

Conditions

Unit Remarks

Min.

Typ.

Max.

PWM1Pn,

PWM1Mn,

∆V^OH2PWM2Pn,

PWM2Mn,

Large current

output drive

capacity

V^CC= 4.5 V

IOH = 30.0 mA

VOH2 maximum variation

0

90

mV *4

variation 1

n = 0 to 3

PWM1Pn,

PWM1Mn,

∆VOL2 PWM2Pn,

PWM2Mn,

Large current

output drive

capacity

V^CC= 4.5 V

IOH = 30.0 mA

VOL2 maximum variation

0

90

mV *4

variation 2

n = 0 to 3

V0 to V1,

V1 to V2,

V2 to V3

LCD divider

resistance

R^LCD

50

100

200

2.5

kΩ

COM0 to

COM3

output imped-

ance

COMn

(n = 0 to 3)

RVCOM

SEG0 to

SEG3

output imped-

ance

SEGn

(n = 00 to 23)

R^VSEG

15

kΩ

V0 to V3

COMm

(m = 00 to 23)

SEGn

LCD leakage

current

I^LCDC

−5.0

+5.0

(n = 00 to 23)

*4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simul-

taneously ON. Similarly for other channels.

65

MB90420G/5G (A) Series

4. AC Characteristics

(1) Clock timing

(V^CC= 5.0 V±10%, V^SS= DV^SS= AV^SS= 0.0 V, T^A= −40 °C to +105 °C)

Value

Typ.

4

Condi-

tions

Parameter

Symbol Pinname

Unit

Remarks

Min.

Max.

F^C

F^LC

tCYL

tLCYL

X0, X1

X0A, X1A

X0, X1

MHz

kHz

ns

Base oscillation

clock frequency

32.768

250

Base oscillation

clock cycle time

X0A, X1A

30.5

µs

Use duty ratio of

40 to 60% as a guideline

PWH, PWL

P^WLH, PWLL

tcr, tcf

X0

X0A

10

ns

µs

ns

Input clock pulse

width

15.2

Input clock

rise, fall time

With external

clock signal

X0, X0A

5

Using main clock,

PLL clock

F^CP

FLCP

t^CP

2

16

MHz

Input operating

clock frequency

8.192

—

kHz Using sub clock

Using main clock,

PLL clock

62.5

500

ns

Input operating

clock cycle time

tLCP

∆f

122.1

µs Using sub clock

Frequency variability

ratio* (locked)

5

%

*: The frequency variability ratio is the maximum proportion of variation from the set central frequency using a

multiplier in locked operation.

+

+α

α

Central

frequency

∆f =

× 100 (%)

fo

−α

−

• X0, X1 clock timing

t

0.8 VCC

0.2 VCC

X0

P

PLCYL

tcf

tcr

• X0A, X1A clock timing

tHCYL

0.8 VCC

0.2 VCC

X0A

PWH

PWL

tcf

tcr

66

MB90420G/5G (A) Series

• Range of warranted operation

Relation between internal operating clock frequency and supply voltage

MB90F428GA, MB90428GA, MB90427GA

range of warranted operation

5.5

3.7

3.3

3.0

PLL range of

warranted operation

MB90F428G, MB90428G, MB90427G

range of warranted operation

2

8

12

16

Internal clock frequency fCP (MHz)

The MB90F428GA, MB90F423GA, MB90428GA, MB90427GA, and MB90423GA enter reset mode at

supply voltage below 4 V ± 0.3 V.

Relation between oscillator clock frequency and internal operating clock frequency

Internal operating clock frequency

PLL clock

Main clock

Multiplier Multiplier Multiplier Multiplier

× 1

× 2

× 3

× 4

Oscillation clock

frequency

4 MHz

2 MHz

8 MHz

12 MHz

16 MHz

• Sample oscillator circuit

Oscillator

element

manufacturer

Oscillator Frequency

C1

TBD

C2

TBD

R

TBD

4 MHz

TBD

X0

X1

R

C1

C2

67

MB90420G/5G (A) Series

AC ratings are defined for the following measurement reference voltage values:

• Input signal waveform

• Output signal waveform

Hysteresis input pin

Output pin

0.8 VCC

0.6 VCC

2.4 V

0.8 V

68

MB90420G/5G (A) Series

(2) Reset input

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter

Symbol

Pin name Conditions

Unit

Remarks

Min.

Max.

Reset input time

t^RSTL

RST

16 tCP

ns

tRSTL

RST

0.6 VCC

(3) Power-on reset, power on conditions

(V^SS= 0.0 V, TA = −40 °C to +105 °C)

Value

name

Symbol

Parameter

Conditions

Unit

Remarks

Min.

Max.

30

Power supply rise time

t^R

0.05

ms

V

Power supply start voltage

Power supply attained voltage

Power supply cutoff time

V^OFF

V^ON

tOFF

0.2

VCC

2.7

50

V

ms For repeat operation

tR

2.7 V

VCC

0.2 V

tOFF

Extreme variations in voltage supply may activate a power-on reset.

As the illustration below shows, when varying supply voltage during operation the use of a smooth

voltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on the

device should not be used, however it is permissible to use the PLL clock during a voltage drop of

1mV/s or less.

VCC

5.0 V

4.5 (V) 420G/425G series

A rise slope of 50 mV or

less is recommended

3.0 (V) 420GA/425GA series

RAM data hold

VSS

0 V

69

MB90420G/5G (A) Series

(4) UART0, UART1 timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Min. Max.

8 tCP

Symbol

Conditions

Parameter

Pin name

Unit

Remarks

Serial clock cycle time

t^SCYC

t^SLOV

SCK0, SCK1

ns

Internal shift

clock mode

output pin C^L=

80 pF + 1•TTL

SCK0, SCK1

SOT0, SOT1

SCK fall to SOT delay time

−80

80

Valid SIN to SCK rise

t^IVSH

t^SHIX

t^SHSL

tSLSH

100

60

ns

SCK0, SCK1

SIN0, SIN1

SCK rise to valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

4 t^CP

4 tCP

SCK0, SCK1

External shift

clock mode

output pin C^L=

80 pF + 1•TTL

SCK0, SCK1

SOT0, SOT1

SCK fall to SOT delay time

tSLOV

150

ns

Valid SIN to SCK rise

tIVSH

60

ns

SCK0, SCK1

SIN0, SIN1

SCK rise to valid SIN hold time

t^SHIX

Notes : • AC ratings are for CLK synchronous mode.

• C^Lis load capacitance connected to pin during testing.

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

SOT

0.8 V

tIVSH

tSHIX

0.8 VCC

0.6 VCC

SIN

0.6 VCC

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.6 VCC

tSLOV

0.6 VCC

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.6 VCC

0.8 VCC

0.6 VCC

70

MB90420G/5G (A) Series

(5) Timer input timing

Parameter

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Symbol

Pin name

Conditions

Unit

Remarks

Min.

Max.

TIN0, TIN1,

IN0, IN1,

IN2, IN3,

t^TIWH

tTIWL

Input pulse width

4 tCP

ns

• Timer input timing

tTIWH

tTIWL

0.8 VCC

TIN0 TIN1

IN0 IN3

0.6 VCC

(6) Trigger input timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit Remarks

Min.

Max.

Input pulse width

t^TRGL

IRQ0 to IRQ7

5 tCP

ns

• Trigger input timing

tTRGH

tTRGL

0.8 VCC

IRQ0 IRQ7

0.6 VCC

71

MB90420G/5G (A) Series

(7) Low voltage detection

(V^SS= AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Symbol

Conditions

Parameter

Pin name

Unit

Remarks

Min.

Typ.

Max.

Duringvoltage

drop

Detection voltage

Hysteresis width

V^DL

VCC

V^CC

3.7

4.0

4.3

V

Duringvoltage

rise

V^HYS

0.1

Powersupplyvoltage

fluctuation ratio

dV/dt

td

−0.1

0.02

35

V/µs

µs

Detection delay time

Internal reset

VCC

dV

dt

VHYS

Vni

td

72

MB90420G/5G (A) Series

5. A/D Conversion Block

(1) Electrical Characteristics

(V^CC= AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)

Value

Parameter

Resolution

Symbol Pin name

Unit

Remarks

Min.

Typ.

Max.

10

bit

Total error

±5.0

±2.5

±1.9

AVSS

LSB

Non-linear error

Differential linear error

AVSS

Zero transition voltage

V^OT

AN0 to AN7

V

1 LSB =

(AVRH − AV^SS)

/ 1024

− 3.5 LSB + 0.5 LSB + 4.5 LSB

Full scale transition

voltage

AVRH AVRH AVRH

− 6.5 LSB − 1.5 LSB + 1.5 LSB

V^FST

Sampling time

t^SMP

tCMP

tCNV

2.000

4.125

6.125

µs

*1

Compare time

*2

*3

A/D conversion time

Analog port

input current

I^AIN

AN0 to AN7

10

µA

VAVSS = VAIN = VAVCC

Analog input current

Reference voltage

VAIN

AVR+

I^A

AN0 to AN7

AVRH

0

AVRH

AVCC

6.0

5

V

3.0

2.3

mA

Power supply current

AVCC

IAH

µA *4

I^R

AVRH

200

400

600

5

µA

VAVRH = 5.0 V

Reference voltage feed

current

IRH

µA *4

LSB

Inter-channel variation

—

AN0 to AN7

4

*1 : At F^CP= 16 MHz, tSMP = 32 × tCP = 2.000 (µs) .

*2 : At F^CP= 16 MHz, tCMP = 66 × tCP = 4.125 (µs) .

*3 : Equivalent to conversion time per channel at F^CP= 16 MHz, and selection of tSMP = 32 × tCP and tCMP = 32 × tCP.

*4 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in

stop mode.

Notes : •The relative error increases as AVRH is reduced.

•The output impedance (rs) on the external analog input circuit should be used as follows.

External circuit output impedance rs = 5 kΩ max.

•If the output impedance on the external circuit is too great, the analog voltage sampling time may be

insufficient.

•If DC inhibitor capacitance is placed between the external circuit and input pin, then a capacitance value

several thousand times the value of the chip internal sampling capacitance (CSH) should be selected in

order to suppress the effects of voltage division with CSH.

73

MB90420G/5G (A) Series

• Analog input equivalent circuit

Microcontroller internal circuits

Input pin AN0

Input pin AN7

CSH

rS

RSH

Comparator

VS

S/H circuit

External circuits

Analog channel selector

rs = 5 kΩ or less

RSH = approx. 3 kΩ

CSH = approx. 25 pF

Note : These element parameters are intended as guidelines for reference, and are not warranted for

actual use.

74

MB90420G/5G (A) Series

(2) Definition of terms

• Resolution

Indicates the ability of the A/D converter to discriminate in analog conversion.

10-bit resolution indicates that analog voltage can be resolved into 2¹⁰= 1024 levels.

• Total error

Expresses the difference between actual and logical values. It is the total value of errors that can come from

offset error, gain error, non-linearity error and noise.

• Linearity error

Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s

zero transition point (00 0000 0000 ←→ 00 0000 0001) and full scale transition point (11 1111 1110 ←→ 11

1111 1111) .

• Differential linearity error

Expresses the deviation of the logical value of input voltage required to create a variation of 1 SLB in output

code.

• 10-bit A/D converter conversion characteristics

11 1111 1111

11 1111 1110

11 1111 1101

11 1111 1100

.

1 LSB × N + VOT

Linearity error

00 0000 0011

00 0000 0010

00 0000 0001

00 0000 0000

VOT

VNT V(N + 1)T

VFST

Analog input

VFST − VOT

1 LSB =

Linearity error =

1022

VNT − (1 LSB × N + VOT)

[LSB]

1 LSB

V (N + 1) T − VNT

Differential linearity error =

− 1 [LSB]

1 LSB

75

MB90420G/5G (A) Series

■ EXAMPLE CHARACTERISTICS

ICC − VCC (TA = +25 °C)

40

35

30

25

20

15

10

5

FC = 16 MHz

FC = 11 MHz

FC = 8 MHz

FC = 5 MHz

FC = 4 MHz

FC = 2 MHz

0

3.5

4.5

5.5

6.5

VCC (V)

I^CCS− VCC (TA = +25 °C)

3.5

3

2.5

2

FC = 16 MHz

FC = 11 MHz

FC = 8 MHz

1.5

1

FC = 5 MHz

FC = 4 MHz

FC = 2 MHz

0.5

0

3.5

4.5

5.5

6.5

VCC (V)

I^CTS− VCC (TA = +25 °C)

900

800

700

600

500

400

300

200

100

0

FC = 16 MHz

FC = 11 MHz

FC = 8 MHz

FC = 5 MHz

FC = 4 MHz

FC = 2 MHz

3.5

4.5

5.5

6.5

VCC (V)

(Continued)

76

MB90420G/5G (A) Series

(Continued)

ICCL − VCC (FC = 8 kHz)

500

400

300

200

100

0

Ta = 25 °C

Ta = 125 °C

Ta = −40 °C

3.5

4.5

5.5

6.5

VCC (V)

I^CCLS− VCC (FC = 8 kHz)

70

60

50

40

30

20

10

0

Ta = 125 °C

Ta = 25 °C

Ta = −40 °C

3.5

4.5

5.5

6.5

VCC (V)

I^CCT− VCC (FC = 8 kHz)

70

60

50

40

30

20

10

0

Ta = 125 °C

Ta = 25 °C

Ta = −40 °C

3.5

4.5

5.5

6.5

VCC (V)

77

MB90420G/5G (A) Series

■ INSTRUCTIONS (351 INSTRUCTIONS)

Table 1 Explanation of Items in Tables of Instructions

Meaning

Mnemonic Upper-case letters and symbols: Represented as they appear in assembler.

Item

Lower-case letters: Replaced when described in assembler.

Numbers after lower-case letters:Indicate the bit width within the instruction code.

#

~

Indicates the number of bytes.

Indicates the number of cycles.

m: When branching

n : When not branching

See Table 4 for details about meanings of other letters in items.

RG

B

Indicates the number of accesses to the register during execution of the instruction.

It is used calculate a correction value for intermittent operation of CPU.

Indicates the correction value for calculating the number of actual cycles during execution of the

instruction. (Table 5)

The number of actual cycles during execution of the instruction is the correction value summed

with the value in the “~” column.

Operation

LH

Indicates the operation of instruction.

Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.

Z : Transfers “0”.

X : Extends with a sign before transferring.

– : Transfers nothing.

AH

Indicates special operations involving the upper 16 bits in the accumulator.

* : Transfers from AL to AH.

– : No transfer.

Z : Transfers 00^Hto AH.

X : Transfers 00H or FFH to AH by signing and extending AL.

I

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),

N (negative), Z (zero), V (overflow), and C (carry).

* : Changes due to execution of instruction.

– : No change.

S

T

N

Z

S : Set by execution of instruction.

R : Reset by execution of instruction.

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction. (a single instruction that

reads data from memory, etc., processes the data, and then writes the result to memory.)

* : Instruction is a read-modify-write instruction.

– : Instruction is not a read-modify-write instruction.

Note: A read-modify-write instruction cannot be used on addresses that have different

meanings depending on whether they are read or written.

• Number of execution cycles

The number of cycles required for instruction execution is acquired by adding the number of cycles for each

instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.

Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal

ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution

cycles is increased.

For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data

bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.

When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external

bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles

specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number

of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the

number of times access is done × the number of cycles suspended as the corrective value to the number of

ordinary execution cycles.

78

MB90420G/5G (A) Series

Table 2 Explanation of Symbols in Tables of Instructions

Meaning

Symbol

A

32-bit accumulator

The bit length varies according to the instruction.

Byte : Lower 8 bits of AL

Word : 16 bits of AL

Long : 32 bits of AL and AH

AH

AL

Upper 16 bits of A

Lower 16 bits of A

SP

PC

Stack pointer (USP or SSP)

Program counter

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB, SPB

DTB, ADB, SSB, USB, DPR, SPB

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

Compact direct addressing

addr16

addr24

ad24 0 to 15

ad24 16 to 23

Direct addressing

Physical direct addressing

Bit 0 to bit 15 of addr24

Bit 16 to bit 23 of addr24

io

I/O area (000000^Hto 0000FFH)

imm4

imm8

4-bit immediate data

8-bit immediate data

imm16

imm32

ext (imm8)

16-bit immediate data

32-bit immediate data

16-bit data signed and extended from 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

bp

Bit offset

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

( )b

rel

Bit address

PC relative addressing

ear

eam

Effective addressing (codes 00 to 07)

Effective addressing (codes 08 to 1F)

rlst

Register list

79

MB90420G/5G (A) Series

Table 3 Effective Address Fields

Address format

RL0 Register direct

Number of bytes in address

extension *

Code

Notation

00

01

02

03

04

05

06

07

R0

R1

R2

R3

R4

R5

R6

R7

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

(RL0)

RL1 “ea” corresponds to byte, word, and

(RL1) long-word types, starting from the left

RL2

(RL2)

RL3

—

(RL3)

08

09

0A

0B

@RW0

Register indirect

@RW1

@RW2

@RW3

0

0C

0D

0E

0F

@RW0 +

@RW1 +

@RW2 +

@RW3 +

Register indirect with post-increment

10

11

12

13

14

15

16

17

@RW0 + disp8

@RW1 + disp8

@RW2 + disp8

@RW3 + disp8

@RW4 + disp8

@RW5 + disp8

@RW6 + disp8

@RW7 + disp8

Register indirect with 8-bit

displacement

1

2

18

19

1A

1B

@RW0 + disp16

@RW1 + disp16

@RW2 + disp16

@RW3 + disp16

Register indirect with 16-bit

displacement

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)

column in the tables of instructions.

80

MB90420G/5G (A) Series

Table 4 Number of Execution Cycles for Each Type of Addressing

(a)

Number of register accesses

for each type of addressing

Code

Operand

Number of execution cycles

for each type of addressing

Ri

RWi

RLi

00 to 07

Listed in tables of instructions Listed in tables of instructions

08 to 0B

0C to 0F

10 to 17

18 to 1B

@RWj

2

4

2

1

2

1

@RWj +

@RWi + disp8

@RWj + disp16

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

4

2

1

2

0

Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.

Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles

(b) byte

(c) word

(d) long

Operand

Cycles

Access

Cycles

Access

Cycles

Access

Internal register

+0

1

+0

1

+0

2

Internal memory even address

Internal memory odd address

+0

1

+0

+2

1

2

+0

+4

2

4

Even address on external data bus (16 bits)

Odd address on external data bus (16 bits)

+1

1

+1

+4

1

2

+2

+8

2

4

External data bus (8 bits)

+1

1

+4

2

+8

4

Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)

in the tables of instructions.

• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction

Internal memory

Byte boundary

Word boundary

—

+3

+2

+3

—

External data bus (16 bits)

External data bus (8 bits)

Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

• Because instruction execution is not slowed down by all program fetches in actuality, these correction

values should be used for “worst case” calculations.

81

MB90420G/5G (A) Series

Table 7 Transfer Instructions (Byte) [41 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

MOV

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RLi+disp8

2

3

1

2

3

4

2

0

1

0

2

0

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

Z

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a)

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

1

3

2

3

10

1

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ← ((RLi)+disp8) Z

MOVN A, #imm4

0

byte (A) ← imm4

Z

– R

MOVX A, dir

MOVX A, addr16

MOVX A, Ri

MOVX A, ear

MOVX A, eam

MOVX A, io

MOVX A, #imm8

MOVX A, @A

MOVX A,@RWi+disp8

MOVX A, @RLi+disp8

2

3

2

3

4

2

0

1

0

1

2

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

X

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a)

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

2

3

5

10

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ← ((RWi)+disp8) X

(b) byte (A) ← ((RLi)+disp8) X

MOV

dir, A

addr16, A

Ri, A

ear, A

eam, A

io, A

@RLi+disp8, A

Ri, ear

Ri, eam

ear, Ri

eam, Ri

Ri, #imm8

io, #imm8

dir, #imm8

ear, #imm8

eam, #imm8

@AL, AH

2

3

1

2

3

4

2

0

1

0

2

1

2

1

0

1

0

(b) byte (dir) ← (A)

(b) byte (addr16) ← (A)

–

*

–

*

–

*

–

*

–

0

byte (Ri) ← (A)

byte (ear) ← (A)

2+ 3+ (a)

(b) byte (eam) ← (A)

(b) byte (io) ← (A)

(b) byte ((RLi) +disp8) ← (A) –

2

3

2

3

10

3

0

byte (Ri) ← (ear)

(b) byte (Ri) ← (eam)

byte (ear) ← (Ri)

(b) byte (eam) ← (Ri)

byte (Ri) ← imm8

–

2+ 4+ (a)

2

2+ 5+ (a)

2

3

4

0

2

5

2

0

(b) byte (io) ← imm8

(b) byte (dir) ← imm8

0

byte (ear) ← imm8

3+ 4+ (a)

(b) byte (eam) ← imm8

/MOV @A, T

2

3

0

(b) byte ((A)) ← (AH)

–

*

–

XCH

A, ear

4

2

0

4

2

0

byte (A) ↔ (ear)

2× (b) byte (A) ↔ (eam)

byte (Ri) ↔ (ear)

2× (b) byte (Ri) ↔ (eam)

Z

–

A, eam

Ri, ear

Ri, eam

2+ 5+ (a)

2

2+ 9+ (a)

7

0

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

82

MB90420G/5G (A) Series

Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

MOVW A, dir

MOVW A, addr16

MOVW A, SP

MOVW A, RWi

MOVW A, ear

MOVW A, eam

MOVW A, io

MOVW A, @A

#

~

B

Operation

2

3

1

2

3

4

1

2

0

1

0

1

2

(c) word (A) ← (dir)

(c) word (A) ← (addr16)

0

(c) word (A) ← (eam)

(c) word (A) ← (io)

(c) word (A) ← ((A))

0

(c)

–

*

–

*

–

*

–

word (A) ← (SP)

word (A) ← (RWi)

word (A) ← (ear)

2+ 3+ (a)

2

3

2

3

2

5

10

MOVW A, #imm16

MOVW A,@RWi+disp8

MOVW A, @RLi+disp8

word (A) ← imm16

word (A) ← ((RWi) +disp8)

word (A) ← ((RLi) +disp8)

MOVW dir, A

MOVW addr16, A

MOVW SP, A

MOVW RWi, A

MOVW ear, A

MOVW eam, A

MOVW io, A

MOVW @RWi+disp8,A

MOVW @RLi+disp8, A

MOVW RWi, ear

MOVW RWi, eam

MOVW ear, RWi

MOVW eam, RWi

MOVW RWi, #imm16

MOVW io, #imm16

MOVW ear, #imm16

MOVW eam, #imm16

MOVW @AL, AH

/MOVW@A, T

2

3

1

2

3

4

1

2

0

1

0

1

2

1

2

1

0

1

0

(c) word (dir) ← (A)

(c) word (addr16) ← (A)

–

*

–

*

–

*

–

*

–

0

word (SP) ← (A)

word (RWi) ← (A)

word (ear) ← (A)

2+ 3+ (a)

(c) word (eam) ← (A)

(c) word (io) ← (A)

2

3

2

3

5

10

3

word ((RWi) +disp8) ← (A)

word ((RLi) +disp8) ← (A)

(c)

(0) word (RWi) ← (ear)

(c) word (RWi) ← (eam)

2+ 4+ (a)

2

2+ 5+ (a)

3

4

0

word (ear) ← (RWi)

(c) word (eam) ← (RWi)

word (RWi) ← imm16

(c) word (io) ← imm16

word (ear) ← imm16

2

5

2

0

4+ 4+ (a)

(c) word (eam) ← imm16

2

3

4

0

(c) word ((A)) ← (AH)

–

*

–

XCHW A, ear

2

0

4

2

0

word (A) ↔ (ear)

2× (c) word (A) ↔ (eam)

word (RWi) ↔ (ear)

2× (c) word (RWi) ↔ (eam)

–

XCHW A, eam

XCHW RWi, ear

XCHW RWi, eam

2+ 5+ (a)

2

2+ 9+ (a)

7

0

MOVL A, ear

MOVL A, eam

MOVL A, #imm32

2

4

2

0

long (A) ← (ear)

–

*

–

2+ 5+ (a)

5

(d) long (A) ← (eam)

0

3

long (A) ← imm32

long (ear) ← (A)

MOVL ear, A

MOVL eam, A

2

4

2

0

–

*

–

2+ 5+ (a)

(d) long (eam) ← (A)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

83

MB90420G/5G (A) Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

ADD A,#imm8

#

~

B

Operation

2

5

3

0

1

0

2

0

1

0

1

0

2

0

1

0

byte (A) ← (A) +imm8

Z

–

Z

–

*

–

*

–

*

ADD

ADDC

A, dir

A, ear

A, eam

ear, A

eam, A

A

(b) byte (A) ← (A) +(dir)

byte (A) ← (A) +(ear)

(b) byte (A) ← (A) +(eam)

byte (ear) ← (ear) + (A)

2× (b) byte (eam) ← (eam) + (A)

0

2+ 4+ (a)

2

2+ 5+ (a)

1

2

3

0

2

3

0

byte (A) ← (AH) + (AL) + (C) Z

byte (A) ← (A) + (ear) + (C)

ADDC A, ear

ADDC A, eam

ADDDC A

Z

2+ 4+ (a)

(b) byte (A) ← (A) + (eam) + (C) Z

byte (A) ← (AH) + (AL) + (C) (decimal)

1

2

3

2

5

3

0

Z

–

SUB

SUBC

A, #imm8

A, dir

A, ear

A, eam

ear, A

eam, A

A

byte (A) ← (A) –imm8

(b) byte (A) ← (A) – (dir)

byte (A) ← (A) – (ear)

(b) byte (A) ← (A) – (eam)

byte (ear) ← (ear) – (A)

2× (b) byte (eam) ← (eam) – (A)

0

2+ 4+ (a)

2

2+ 5+ (a)

1

2

2+ 4+ (a)

1

3

0

2

3

0

byte (A) ← (AH) – (AL) – (C) Z

byte (A) ← (A) – (ear) – (C)

–

SUBC A, ear

SUBC A, eam

SUBDC A

Z

(b) byte (A) ← (A) – (eam) – (C) Z

byte (A) ← (AH) – (AL) – (C) (decimal)

3

0

Z

ADDW A

1

2

3

0

1

0

2

0

1

0

1

0

2

0

1

0

word (A) ← (AH) + (AL)

word (A) ← (A) +(ear)

–

*

–

*

–

*

ADDW A, ear

ADDW A, eam

ADDW A, #imm16

ADDW ear, A

ADDW eam, A

ADDCWA, ear

ADDCWA, eam

SUBW A

SUBW A, ear

SUBW A, eam

SUBW A, #imm16

SUBW ear, A

SUBW eam, A

SUBCW A, ear

SUBCW A, eam

2+ 4+ (a)

3

2

2+ 5+ (a)

2

2+ 4+ (a)

1

2

2+ 4+ (a)

3

2

(c) word (A) ← (A) +(eam)

0

2

3

word (A) ← (A) +imm16

word (ear) ← (ear) + (A)

2× (c) word (eam) ← (eam) + (A)

word (A) ← (A) + (ear) + (C)

3

0

(c) word (A) ← (A) + (eam) + (C) –

0

(c) word (A) ← (A) – (eam)

0

2

3

word (A) ← (AH) – (AL)

word (A) ← (A) – (ear)

–

2

3

word (A) ← (A) –imm16

word (ear) ← (ear) – (A)

2+ 5+ (a)

2

2+ 4+ (a)

2× (c) word (eam) ← (eam) – (A)

word (A) ← (A) – (ear) – (C)

3

0

–

(c) word (A) ← (A) – (eam) – (C) –

ADDL A, ear

2

6

2

0

2

0

long (A) ← (A) + (ear)

–

*

–

ADDL A, eam

ADDL A, #imm32

SUBL A, ear

SUBL A, eam

SUBL A, #imm32

2+ 7+ (a)

5

2

2+ 7+ (a)

5

(d) long (A) ← (A) + (eam)

0

4

6

long (A) ← (A) +imm32

long (A) ← (A) – (ear)

(d) long (A) ← (A) – (eam)

long (A) ← (A) –imm32

4

0

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

84

MB90420G/5G (A) Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

INC

ear

eam

2

0

byte (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a)

2× (b) byte (eam) ← (eam) +1

DEC

ear

eam

2

3

2

0

byte (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a)

2× (b) byte (eam) ← (eam) –1

INCW ear

INCW eam

2

3

2

0

word (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a)

2× (c) word (eam) ← (eam) +1

DECW ear

DECW eam

2

3

2

0

word (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a)

2× (c) word (eam) ← (eam) –1

INCL ear

INCL eam

2

7

4

0

long (ear) ← (ear) +1

–

*

–

*

2+ 9+ (a)

2× (d) long (eam) ← (eam) +1

DECL ear

DECL eam

2

7

4

0

long (ear) ← (ear) –1

–

*

–

*

2+ 9+ (a)

2× (d) long (eam) ← (eam) –1

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

CMP

A

1

2

1

2

0

1

0

byte (AH) – (AL)

byte (A) ← (ear)

–

*

–

CMP

A, ear

A, eam

A, #imm8

2+ 3+ (a)

2

(b) byte (A) ← (eam)

0

2

byte (A) ← imm8

CMPW A

1

2

1

2

0

1

0

word (AH) – (AL)

word (A) ← (ear)

–

*

–

CMPW A, ear

CMPW A, eam

CMPW A, #imm16

2+ 3+ (a)

3

(c) word (A) ← (eam)

0

2

word (A) ← imm16

CMPL A, ear

CMPL A, eam

CMPL A, #imm32

2

6

2

0

word (A) ← (ear)

–

*

–

2+ 7+ (a)

5

(d) word (A) ← (eam)

word (A) ← imm32

3

0

Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

85

MB90420G/5G (A) Series

Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

LH AH

I

S

T

N

Z

V

C

RMW

RG

Mnemonic

#

~

B

Operation

1

DIVU

A

1

0

0 word (AH) /byte (AL)

–

*

–

*

Quotient → byte (AL) Remainder → byte (AH)

2

DIVU

A, ear

2

1

0

1

0

0 word (A)/byte (ear)

–

*

–

*

Quotient → byte (A) Remainder → byte (ear)

6

3

A, eam 2+

word (A)/byte (eam)

Quotient → byte (A) Remainder → byte (eam)

*

4

DIVUW A, ear

2

long (A)/word (ear)

Quotient → word (A) Remainder → word (ear)

0

*

7

5

DIVUW A, eam 2+

long (A)/word (eam)

Quotient → word (A) Remainder → word (eam)

*

8

MULU

MULU A, ear

MULU A, eam 2+

A

1

2

0

1

0

byte (AH) *byte (AL) → word (A)

byte (A) *byte (ear) → word (A)

byte (A) *byte (eam) → word (A)

–

0

(b)

*

9

*

10

*

MULUW A

MULUW A, ear

MULUW A, eam 2+

1

2

11

12

13

0

1

0

word (AH) *word (AL) → long (A)

word (A) *word (ear) → long (A)

word (A) *word (eam) → long (A)

–

0

(c)

*

*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.

*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.

*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.

*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.

*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.

*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.

*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.

*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

86

MB90420G/5G (A) Series

Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

DIV

A

2

*1

0

word (AH) /byte (AL)

Quotient → byte (AL)

Remainder → byte (AH)

word (A)/byte (ear)

Z

–

*

–

DIV

A, ear

2

*2

1

0

1

0

–

*

–

Quotient → byte (A)

Remainder → byte (ear)

DIV

A, eam 2 + *3

*6 word (A)/byte (eam)

Quotient → byte (A)

Remainder → byte (eam)

long (A)/word (ear)

DIVW

A, ear

2

*4

0

Quotient → word (A)

Remainder → word (ear)

A, eam 2+ *5

*7 long (A)/word (eam)

Quotient → word (A)

Remainder → word (eam)

MULU

MULUW A

MULUW A, ear

A

A, ear

A, eam 2 + *10

2

*8

*9

0

1

0

1

0

byte (AH) *byte (AL) → word (A)

byte (A) *byte (ear) → word (A)

–

(b) byte (A) *byte (eam) → word (A)

0

2

*11

*12

word (AH) *word (AL) → long (A)

word (A) *word (ear) → long (A)

MULUW A, eam 2 + *13

(c) word (A) *word (eam) → long (A)

*1: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.

*2: Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.

*3: Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.

*4: Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.

Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.

*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for

normal operation.

Negative dividend:Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for

normal operation.

*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.

*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.

*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.

*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.

*10: Setto4+(a)whenbyte(eam)iszero, 13+(a)whentheresultispositive, and14+(a)whentheresultisnegative.

*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.

*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.

*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is

negative.

Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes

two values because of detection before and after an operation.

• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.

• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”

and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”

87

MB90420G/5G (A) Series

Table 14 Logical 1 Instructions (Byte/Word) [39 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

AND A, #imm8

#

~

B

Operation

2

3

0

1

0

2

0

byte (A) ← (A) and imm8

byte (A) ← (A) and (ear)

–

*

R

–

*

AND

A, ear

A, eam

ear, A

2+ 4+ (a)

2

2+ 5+ (a)

(b) byte (A) ← (A) and (eam)

byte (ear) ← (ear) and (A)

3

0

eam, A

2× (b) byte (eam) ← (eam) and (A) –

OR

A, #imm8

A, ear

A, eam

ear, A

2

3

0

1

0

2

0

byte (A) ← (A) or imm8

byte (A) ← (A) or (ear)

–

*

R

–

*

2+ 4+ (a)

2

2+ 5+ (a)

(b) byte (A) ← (A) or (eam)

byte (ear) ← (ear) or (A)

2× (b) byte (eam) ← (eam) or (A)

3

0

eam, A

XOR A, #imm8

XOR A, ear

XOR A, eam

XOR ear, A

XOR eam, A

2

3

0

1

0

2

0

byte (A) ← (A) xor imm8

byte (A) ← (A) xor (ear)

–

*

R

–

*

2+ 4+ (a)

2

2+ 5+ (a)

(b) byte (A) ← (A) xor (eam)

byte (ear) ← (ear) xor (A)

3

0

2× (b) byte (eam) ← (eam) xor (A) –

NOT

A

ear

eam

1

2

3

0

2

0

byte (A) ← not (A)

byte (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a)

2× (b) byte (eam) ← not (eam)

ANDW A

1

3

2

3

0

1

0

2

0

word (A) ← (AH) and (A)

word (A) ← (A) and imm16

word (A) ← (A) and (ear)

–

*

R

–

*

ANDW A, #imm16

ANDW A, ear

ANDW A, eam

ANDW ear, A

ANDW eam, A

2+ 4+ (a)

2

2+ 5+ (a)

(c) word (A) ← (A) and (eam)

word (ear) ← (ear) and (A)

2× (c) word (eam) ← (eam) and (A)

3

0

ORW

A

1

3

2

3

0

1

0

2

0

word (A) ← (AH) or (A)

word (A) ← (A) or imm16

word (A) ← (A) or (ear)

–

*

R

–

*

ORW A, #imm16

ORW A, ear

ORW A, eam

ORW ear, A

2+ 4+ (a)

2

2+ 5+ (a)

(c) word (A) ← (A) or (eam)

word (ear) ← (ear) or (A)

2× (c) word (eam) ← (eam) or (A)

3

0

ORW eam, A

XORW A

1

3

2

3

0

1

0

2

0

word (A) ← (AH) xor (A)

word (A) ← (A) xor imm16

word (A) ← (A) xor (ear)

–

*

R

–

*

XORW A, #imm16

XORW A, ear

XORW A, eam

XORW ear, A

XORW eam, A

2+ 4+ (a)

2

2+ 5+ (a)

(c) word (A) ← (A) xor (eam)

word (ear) ← (ear) xor (A)

2× (c) word (eam) ← (eam) xor (A)

3

0

NOTW A

NOTW ear

NOTW eam

1

2

3

0

2

0

word (A) ← not (A)

word (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a)

2× (c) word (eam) ← not (eam)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

88

MB90420G/5G (A) Series

Table 15 Logical 2 Instructions (Long Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

ANDL A, ear

ANDL A, eam

2

6

2

0

long (A) ← (A) and (ear)

–

*

R

–

2+ 7+ (a)

(d) long (A) ← (A) and (eam)

ORL

A, ear

A, eam

2

6

2

0

long (A) ← (A) or (ear)

–

*

R

–

2+ 7+ (a)

(d) long (A) ← (A) or (eam)

XORL A, ea

XORL A, eam

2

6

2

0

long (A) ← (A) xor (ear)

–

*

R

–

2+ 7+ (a)

(d) long (A) ← (A) xor (eam)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

NEG

A

1

2

0

byte (A) ← 0 – (A)

X

–

*

–

NEG ear

NEG eam

2

3

2

0

byte (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a)

2× (b) byte (eam) ← 0 – (eam)

NEGW A

1

2

0

word (A) ← 0 – (A)

–

*

–

NEGW ear

NEGW eam

2

3

2

0

word (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a)

2× (c) word (eam) ← 0 – (eam)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 17 Normalize Instruction (Long Word) [1 Instruction]

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

RG

B

Operation

1

NRML A, R0

2

1

0

long (A) ← Shift until first digit is “1” –

byte (R0) ← Current shift count

–

*

–

*

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

89

MB90420G/5G (A) Series

Table 18 Shift Instructions (Byte/Word/Long Word) [18 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

RORC A

#

~

B

Operation

byte (A) ← Right rotation with carry

byte (A) ← Left rotation with carry

2

0

–

*

–

*

–

ROLC A

RORC ear

RORC eam

ROLC ear

ROLC eam

byte (ear) ← Right rotation with carry

byte (eam) ← Right rotation with carry

byte (ear) ← Left rotation with carry

byte (eam) ← Left rotation with carry

2

2+

2

3

2

0

–

*

–

*

–

*

–

*

5+ (a)

0 2× (b)

2

0 2× (b)

0

3

2+

5+ (a)

byte (A) ← Arithmetic right barrel shift (A, R0)

byte (A) ← Logical right barrel shift (A, R0)

byte (A) ← Logical left barrel shift (A, R0)

ASR A, R0

LSR A, R0

LSL A, R0

1

2

1

0

–

*

–

*

–

*

–

*

1

*

1

*

word (A) ← Arithmetic right shift (A, 1 bit)

word (A) ← Logical right shift (A, 1 bit)

word (A) ← Logical left shift (A, 1 bit)

ASRW A

LSRW A/SHRW A

LSLW A/SHLW A

1

2

0

–

*

–

*

R

*

–

*

–

1

word (A) ← Arithmetic right barrel shift (A,

R0)

ASRW A, R0

LSRW A, R0

LSLW A, R0

2

1

0

–

*

–

*

–

*

–

*

1

*

1

word (A) ← Logical right barrel shift (A, R0)

word (A) ← Logical left barrel shift (A, R0)

*

2

ASRL A, R0

LSRL A, R0

LSLL A, R0

long (A) ← Arithmetic right shift (A, R0)

long (A) ← Logical right barrel shift (A, R0)

long (A) ← Logical left barrel shift (A, R0)

2

1

0

–

*

–

*

–

*

–

*

2

*

2

*

*1: 6 when R0 is 0, 5 + (R0) in all other cases.

*2: 6 when R0 is 0, 6 + (R0) in all other cases.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

90

MB90420G/5G (A) Series

Table 19 Branch 1 Instructions [31 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

1

BZ/BEQ

BNZ/BNE rel

BC/BLO

BNC/BHS rel

rel

2

*

0

Branch when (Z) = 1

Branch when (Z) = 0

Branch when (C) = 1

Branch when (C) = 0

Branch when (N) = 1

Branch when (N) = 0

Branch when (V) = 1

Branch when (V) = 0

Branch when (T) = 1

Branch when (T) = 0

Branch when (V) xor (N) = 1

Branch when (V) xor (N) = 0

Branch when ((V) xor (N)) or (Z) = 1

Branch when ((V) xor (N)) or (Z) = 0

Branch when (C) or (Z) = 1

Branch when (C) or (Z) = 0

Branch unconditionally

–

1

rel

1

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

1

*

JMP

@A

1

3

2

3

0

1

0

2

0

word (PC) ← (A)

word (PC) ← addr16

word (PC) ← (ear)

–

addr16

@ear

@eam

2+ 4+ (a)

2

2+ 6+ (a)

4

(c) word (PC) ← (eam)

0

(d)

0

JMPP @ear *³

JMPP @eam *³

JMPP addr24

word (PC) ← (ear), (PCB) ← (ear +2)

5

word (PC) ← (eam), (PCB) ← (eam +2)

4

word (PC) ← ad24 0 to 15,

(PCB) ← ad24 16 to 23

CALL @ear *⁴

CALL @eam *⁴

CALL addr16 *⁵

CALLV #vct4 *⁵

CALLP @ear *⁶

2

6

1

0

2

(c) word (PC) ← (ear)

–

2+ 7+ (a)

2× (c) word (PC) ← (eam)

(c) word (PC) ← addr16

2× (c) Vector call instruction

2× (c) word (PC) ← (ear) 0 to 15,

3

1

2

6

7

10

(PCB) ← (ear) 16 to 23

2

CALLP @eam *⁶

CALLP addr24 *⁷

2+ 11+ (a)

10

0

word (PC) ← (eam) 0 to 15,

(PCB) ← (eam) 16 to 23

word (PC) ← addr0 to 15,

(PCB) ← addr16 to 23

–

*

4

2× (c)

*1: 4 when branching, 3 when not branching.

*2: (b) + 3 × (c)

*3: Read (word) branch address.

*4: W: Save (word) to stack; R: read (word) branch address.

*5: Save (word) to stack.

*6: W: Save (long word) to W stack; R: read (long word) R branch address.

*7: Save (long word) to stack.

Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

91

MB90420G/5G (A) Series

Table 20 Branch 2 Instructions [19 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

1

Branch when byte (A) ≠ imm8

Branch when word (A) ≠ imm16

CBNE A, #imm8, rel

CWBNE A, #imm16, rel

3

4

0

–

– – – – *

*

–

*

1

2

Branch when byte (ear) ≠ imm8

Branch when byte (eam) ≠ imm8

Branch when word (ear) ≠ imm16

Branch when word (eam) ≠ imm16

CBNE ear, #imm8, rel

4

4+

5

*

1

0

1

0

(b)

0

–

– – – – *

*

–

CBNE

eam, #imm8, rel*¹⁰

3

4

CWBNE ear, #imm16, rel

CWBNE eam, #imm16, rel*¹⁰

3

5+

(c)

5

DBNZ ear, rel

DBNZ eam, rel

3

2

0

Branch when byte (ear) =

(ear) – 1, and (ear) ≠ 0

–

– – – – *

*

* –

–

*

6

*

3+

2× (b) Branch when byte (eam) =

(eam) – 1, and (eam) ≠ 0

5

DWBNZ ear, rel

DWBNZ eam, rel

3

*

2

0

Branch when word (ear) =

(ear) – 1, and (ear) ≠ 0

–

– – – – *

*

* –

–

*

6

3+

2× (c) Branch when word (eam) =

(eam) – 1, and (eam) ≠ 0

*

INT

INTP

INT9

RETI

#vct8

addr16

addr24

8× (c)

6× (c)

8× (c)

2

3

4

1

0

Software interrupt

Return from interrupt

–

– R S – – – – –

–

20

16

17

20

15

7

*

–

*

LINK

#imm8

(c)

2

0

At constant entry, save old

frame pointer to stack, set

new frame pointer, and

allocate local pointer area

At constant entry, retrieve old

frame pointer from stack.

–

– – – – – – – –

–

6

UNLINK

1

0

–

– – – – – – – –

–

5

RET *⁸

(c)

(d)

1

0

Return from subroutine

–

– – – – – – – –

–

4

6

RETP *⁹

*1: 5 when branching, 4 when not branching

*2: 13 when branching, 12 when not branching

*3: 7 + (a) when branching, 6 + (a) when not branching

*4: 8 when branching, 7 when not branching

*5: 7 when branching, 6 when not branching

*6: 8 + (a) when branching, 7 + (a) when not branching

*7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return.

*8: Retrieve (word) from stack

*9: Retrieve (long word) from stack

*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

92

MB90420G/5G (A) Series

Table 21 Other Control Instructions (Byte/Word/Long Word) [28 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

PUSHW A

PUSHW AH

PUSHW PS

PUSHW rlst

#

~

B

Operation

word (SP) ← (SP) –2, ((SP)) ← (A)

word (SP) ← (SP) –2, ((SP)) ← (AH)

word (SP) ← (SP) –2, ((SP)) ← (PS)

(SP) ← (SP) –2n, ((SP)) ← (rlst)

1

2

4

0

(c)

–

– – – – – – –

–

3

5

4

*

word (A) ← ((SP)), (SP) ← (SP) +2

word (AH) ← ((SP)), (SP) ← (SP) +2

word (PS) ← ((SP)), (SP) ← (SP) +2

(rlst) ← ((SP)), (SP) ← (SP) +2n

POPW A

1

2

–

*

– – – – – – –

–

3

4

0

(c)

POPW AH

POPW PS

POPW rlst

–

*

2

5

4

– – – – – – –

*

JCTX @A

1

Context switch instruction

–

*

–

14

0

6× (c)

AND CCR, #imm8

OR CCR, #imm8

2

byte (CCR) ← (CCR) and imm8 –

–

*

–

3

0

byte (CCR) ← (CCR) or imm8

–

MOV RP, #imm8

MOV ILM, #imm8

2

byte (RP) ←imm8

byte (ILM) ←imm8

–

– – – – – – –

–

2

0

MOVEA RWi, ear

MOVEA RWi, eam 2+

MOVEA A, ear

MOVEA A, eam

2

word (RWi) ←ear

word (RWi) ←eam

word(A) ←ear

–

*

– – – – – – –

–

3

1

0

2+ (a)

1

1+ (a)

2

2+

word (A) ←eam

*

ADDSP #imm8

ADDSP #imm16

2

3

word (SP) ← (SP) +ext (imm8)

word (SP) ← (SP) +imm16

–

– – – – – – –

–

3

0

1

MOV

A, brgl

brg2, A

2

byte (A) ← (brgl)

byte (brg2) ← (A)

Z

–

*

–

– – –

*

– –

–

0

*

1

NOP

ADB

DTB

PCB

SPB

NCC

CMR

1

No operation

–

– – – – – – –

–

0

1

Prefix code for accessing AD space

Prefix code for accessing DT space

Prefix code for accessing PC space

Prefix code for accessing SP space

Prefix code for no flag change

Prefix code for common register bank

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB, DPR : 2 states

*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)

*3: 29 +3 × (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)

*4: Pop count × (c), or push count × (c)

*5: Pop count or push count.

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

93

MB90420G/5G (A) Series

Table 22 Bit Manipulation Instructions [21 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

MOVB A, dir:bp

MOVB A, addr16:bp

MOVB A, io:bp

3

4

3

5

4

0

(b) byte (A) ← (dir:bp) b

(b) byte (A) ← (addr16:bp) b

(b) byte (A) ← (io:bp) b

Z

*

–

*

–

MOVB dir:bp, A

MOVB addr16:bp, A

MOVB io:bp, A

3

4

3

7

6

0

2× (b) bit (dir:bp) b ← (A)

2× (b) bit (addr16:bp) b ← (A)

2× (b) bit (io:bp) b ← (A)

–

*

–

*

SETB dir:bp

SETB addr16:bp

SETB io:bp

3

4

3

7

0

2× (b) bit (dir:bp) b ← 1

2× (b) bit (addr16:bp) b ← 1

2× (b) bit (io:bp) b ← 1

–

*

CLRB dir:bp

CLRB addr16:bp

CLRB io:bp

3

4

3

7

0

2× (b) bit (dir:bp) b ← 0

2× (b) bit (addr16:bp) b ← 0

2× (b) bit (io:bp) b ← 0

–

*

1

BBC dir:bp, rel

BBC addr16:bp, rel

BBC io:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 0

(b) Branch when (addr16:bp) b = 0

(b) Branch when (io:bp) b = 0

–

*

–

*

1

2

1

BBS dir:bp, rel

BBS addr16:bp, rel

BBS io:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 1

(b) Branch when (addr16:bp) b = 1

(b) Branch when (io:bp) b = 1

–

*

–

*

1

2

3

Branch when (addr16:bp) b = 1, bit = 1

SBBS addr16:bp, rel

WBTS io:bp

5

3

0

2× (b)

–

*

–

*

5

4

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

–

*

4

5

WBTC io:bp

*

*1: 8 when branching, 7 when not branching

*2: 7 when branching, 6 when not branching

*3: 10 when condition is satisfied, 9 when not satisfied

*4: Undefined count

*5: Until condition is satisfied

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 23 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

SWAP

SWAPW/XCHW A,T

EXT

EXTW

ZEXT

#

~

B

Operation

1

3

2

1

2

1

0

0 byte (A) 0 to 7 ↔ (A) 8 to 15

0 word (AH) ↔ (AL)

0 byte sign extension

0 word sign extension

0 byte zero extension

0 word zero extension

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

ZEXTW

*

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

94

MB90420G/5G (A) Series

Table 24 String Instructions [10 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

2

5

3

Byte transfer @AH+ ← @AL+, counter = RW0

Byte transfer @AH– ← @AL–, counter = RW0

MOVS/MOVSI

MOVSD

2

–

*

2

5

3

*

1

5

4

Byte retrieval (@AH+) – AL, counter = RW0

Byte retrieval (@AH–) – AL, counter = RW0

SCEQ/SCEQI

SCEQD

2

–

*

–

*

1

5

4

*

5

3

Byte filling @AH+ ← AL, counter = RW0

FISL/FILSI

2

–

*

–

6m +6

*

2

8

6

Word transfer @AH+ ← @AL+, counter = RW0

Word transfer @AH– ← @AL–, counter = RW0

MOVSW/MOVSWI 2

–

*

2

8

6

MOVSWD

2

*

1

8

7

Word retrieval (@AH+) – AL, counter = RW0

Word retrieval (@AH–) – AL, counter = RW0

SCWEQ/SCWEQI

SCWEQD

2

–

*

–

*

1

8

7

*

8

6

Word filling @AH+ ← AL, counter = RW0

FILSW/FILSWI

2

–

*

–

6m +6

*

m: RW0 value (counter value)

n: Loop count

*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs

*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case

*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) sepa-

rately for each.

*4: (b) × n

*5: 2 × (RW0)

*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)

separately for each.

*7: (c) × n

*8: 2 × (RW0)

Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

95

MB90420G/5G (A) Series

■ ORDERING INFORMATION

Part number

MB90F428GAPF

Package

Remarks

MB90F423GAPF

MB90428GAPF

MB90427GAPF

MB90423GAPF

MB90F428GPF

MB90F423GPF

MB90428GPF

MB90427GPF

MB90423GPF

Plastic QFP, 100-pin

(FPT-100P-M06)

MB90F428GAPFV

MB90F423GAPFV

MB90428GAPFV

MB90427GAPFV

MB90423GAPFV

MB90F428GPFV

MB90F423GPFV

MB90428GPFV

MB90427GPFV

MB90423GPFV

Plastic LQFP, 100-pin

(FPT-100P-M05)

96

MB90420G/5G (A) Series

■ PACKAGE DIMENSIONS

Plastic QFP, 100-pin

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

REF

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

16.30±0.40

(.642±.016)

INDEX

31

100

"A"

1

30

M

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

0.13(.005)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.53(.021)MAX

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

1994 FUJITSU LIMITED F100008-3C-2

Dimensions in mm (inches)

(Continued)

97

MB90420G/5G (A) Series

(Continued)

Plastic LQFP, 100-pin

(FPT-100P-M05)

1.50 –⁺0⁰.^.1²0⁰

.059 –⁺.^.0⁰0⁰4⁸

16.00±0.20(.630±.008)SQ

(Mouting height)

75

51

14.00±0.10(.551±.004)SQ

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

0.15(.006)

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

0.50(.0197)TYP

0.18 –⁺0⁰.^.0⁰3⁸

0.127 ⁺–0⁰.^.0⁰2⁵

.005 ⁺^–.^.⁰⁰⁰⁰¹²

M

Details of "B" part

0.08(.003)

.007 –⁺.^.0⁰0⁰1³

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0~10°

C

1995 FUJITSU LIMITED F100007S-2C-3

Dimensions in mm (inches)

98

MB90420G/5G (A) Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

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F0012

FUJITSU LIMITED Printed in Japan


型号：	MB90428GPF
厂家：	FUJITSU
描述：	16-Bit Original Microcontroller 16位微控制器原创微控制器
文件：	总99页 (文件大小：1706K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90428GPF [FUJITSU]

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