MB90523PFV [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB90523PFV |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总106页 (文件大小：1431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13702-4E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90520 Series
MB90522/523/F523/V520
■ DESCRIPTION
The MB90520 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process
control applications in consumer products that require high-speed real-time processing.
The instruction set of the F2MC-16LX CPU core inherits AT architecture of the F2MC* family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division
instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for
processing long word data.
The MB90520 series has peripheral resources of 8/10-bit A/D converter, 8-bit D/A converter, UART (SCI),
extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1,
I/O timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (ICU), output compares 0 and 1 (OCU)), and
an LCD controller/driver.
*:F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
The system can be operated by a sub-clock (rated at 32.768 kHz).
Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, four times the oscillation clock, operation
at VCC of 5.0 V)
(Continued)
■ PACKAGES
120-pin Plastic LQFP
120-pin Plastic QFP
(FPT-120P-M05)
(FPT-120P-M13)
MB90520 Series
(Continued)
• Maximum memory space
16 Mbytes
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed
4-byte instruction queue
• Enhanced interrupt function
8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 16 channels
• Embedded ROM size and types
Mask ROM: 64 kbytes/128 kbytes
Flash ROM: 128 kbytes
• Embedded RAM size
Mask ROM: 4 kbytes
Flash ROM: 4 kbytes
Evaluation product: 6 kbytes
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware stand-by mode
Clock mode (mode in which other than sub-clock and timebase timer are stopped)
• Process
CMOS technology
• I/O port
General-purpose I/O ports (CMOS): 53 ports
General-purpose I/O ports (via pull-up resistors): 24 ports
General-purpose I/O ports (open-drain): 8 ports
Total: 85 ports
• Timer
Timebase timer/watchdog timer: 1 channel
8/16-bit PPG timers 0, 1: 8-bit × 2 channels or 16-bit × 1 channel
• 16-bit re-load timers 0, 1: 2 channels
(Continued)
2
MB90520 Series
(Continued)
• 16-bit I/O timer
16-bit free-run timers 1, 2: 2 channels
Input captures 0, 1 (ICU): Generatesaninterruptrequestbylatchinga16-bitfree-runtimercountervalueupon
detection of an edge input to the pin.
Output compares 0, 1 (OCU): Generates an interrupt request and reverses the output level upon detection of a
match between the 16-bit free-run timer counter value and the compare setting
value.
8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit × 2 channels)
• Extended I/O serial interfaces 0, 1: 1 channel
• UART (SCI)
With full-duplex double buffer
Clock asynchronized or clock synchronized transmission can be selectively used.
• DTP/external interrupt circuit (8 channels)
A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered
by an external input.
• Wake-up interrupt
Receives external interrupt requests and generates an interrupt request upon an “L” level input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
Conversion time: minimum 15.0 µs (at machine clock frequency of 16 MHz, including sampling time)
• 8-bit D/A converter (based on the R-2R system)
8-bit resolution: 2 channels (independent)
Setup time: 12.5 µs
• Clock timer: 1 channel
• LCD controller/driver
A common driver and a segment driver that can directly drive the LCD (liquid crystal display) panel
• Clock output function
Note: Do not set external bus mode for the MB90520 series because it cannot be operated in this mode.
3
MB90520 Series
■ PRODUCT LINEUP
Part number
MB90522
MB90523
MB90F523
MB90V520
Item
Classification
ROM size
Mask ROM product
64 kbytes
Flash ROM product Evaluation product
128 kbytes
None
RAM size
4 kbytes
6 kbytes
Number of instructions: 351
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
CPU functions
Minimum execution time: 62.5 ns
(at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs
(at machine clock frequency of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output): 53
General-purpose I/O ports (via pull-up resistor): 24
General-purpose I/O ports (N-ch open-drain output): 8
Total: 85
Ports
Clock synchronized transmission (62.5 kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by
master/slave connection.
UART (SCI)
Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode (converts two or more successive channels and can
program up to 8 channels.)
8/10-bit A/D converter
8/16-bit PPG timers 0, 1
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
Number of channels: 1 (8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
Pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 µs (at machine clock frequency of 16 MHz)
Number of channels: 1 (8-bit × 2 channels)
Event input: 6 channels
8-bit up/down counter/timer used: 2 channels
8-bit re-load/compare function supported: 1 channel
8/16-bit up/down counter/
timers 0, 1
16-bit
I/O timer
16-bit free-run
timers 1, 2
Number of channels: 2
Overflow interrupts
(Continued)
4
MB90520 Series
(Continued)
Part number
MB90523
MB90523
MB90F523
MB90V520
Item
Output
compares 0, 1
(OCU)
Number of channels: 8
Pin input factor: Match signal of compare register
16-bit
I/O timer
Inputcaptures
0, 1 (ICU)
Number of channels: 2
Rewriting register value upon pin input (rising, falling, or both edges)
Number of inputs: 8
Started by rising edge, falling edge, “H” level input, or “L” level input.
DTP/external interrupt circuit
Wake-up intrrupt
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
Number of inputs: 8
Started by “L” level input.
Delayed interrupt generation
module
Interrupt generation module for switching tasks
Used in real-time operating systems.
Clock synchronized transmission (3125 bps to 1 Mbps)
LSB first/MSB first
Extended I/O serial
interfaces 0, 1
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(at oscillation of 4 MHz)
Timebase timer
8-bit resolution
Number of channels: 2 channels
Based on R-2R system
8-bit D/A converter
Number of common output pins: 4
Number of segment output pins: 32
Number of power supply pins for LCD drive: 4
RAM for LCD indication: 16 bytes
Booster for LCD drive: Internal
LCD controller/driver
Watchdog timer
Split resistor for LCD drive: Internal
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Low-power consumption
(stand-by) mode
Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by
CMOS
Process
Power supply voltage for
operation*
3.0 V to 5.5 V
4.0 V to 5.5 V
3.0 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3.0 V to 5.5 V, an
operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 MHz to 16 MHz.
5
MB90520 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
FPT-120P-M05
MB90522
MB90523
MB90F523
FPT-120P-M13
: Available × : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation chip, note the difference between the evaluation chip and the chip actually used.
The following items must be taken into consideration.
• The MB90V520 does not have an internal ROM. However, operations equivalent to those performed by a chip
with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM
size by setting the development tool.
• In the MB90V520, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90522, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank
FF only.
• In the MB90523/F523, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH
to bank FE and bank FF.
6
MB90520 Series
■ PIN ASSIGNMENT
(Top view)
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P31/CKOT
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
P36/PG00
P37/PG01
VCC
P40/PG10
P41/PG11
P42/SIN0
P43/SOT0
P44/SCK0
P45/SIN1
P46/SOT1
P47/SCK1
SEG00
SEG01
SEG02
SEG03
SEG04
SEG05
SEG06
SEG07
RST
MD0
MD1
MD2
HST
V3
V2
V1
9
V0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P97/SEG31
P96/SEG30
P95/SEG29
P94/SEG28
P93/SEG27
P92/SEG26
P91/SEG25
X0A
X1A
P90/SEG24
P87/SEG23
P86/SEG22
P85/SEG21
P84/SEG20
P83/SEG19
P82/SEG18
P81/SEG17
P80/SEG16
VSS
PA0/SEG08
PA1/SEG09
PA2/SEG10
PA3/SEG11
PA4/SEG12
PA5/SEG13
P77/COM3
P76/COM2
(FPT-120P-M05)
(FPT-120P-M13)
7
MB90520 Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
X0,
Function
LQFP-120*1
QFP-120*2
92,
93
A
B
C
This is a high-speed crystal oscillator pin.
This is a low-speed crystal oscillator pin.
X1
74,
73
X0A,
X1A
89 to 87
MD0 to MD2
This is an input pin for selecting operation modes.
Connect directly to VCC or VSS.
90
86
RST
C
C
D
This is an external reset request signal input pin.
This is a hardware stand-by input pin.
HST
95 to 101
P00 to P06
This is a general-purpose I/O port.
This function can be set by the port 0 input pull-up resistor setup
register (RDR0) for input. For output, however, this function is
invalid.
INT0 to INT6
P07
This is a request input pin of the DTP/external interrupt circuit ch.0
to ch.6.
102
D
D
This is a general-purpose I/O port.
This function can be set by the port 0 input pull-up resistor setup
register (RDR0) for input. For output, however, this function is
invalid.
103 to 110 P10 to 17
This is a general-purpose I/O port.
This function can be set by the port 1 input pull-up resistor setup
register (RDR1) for input. For output, however, this function is
invalid.
WI0 to WI7
This is an I/O pin for wake-up interrupts.
This is a general-purpose I/O port.
111,
112,
113,
114
P20,
P21,
P22,
P23
E
IC00,
IC01,
IC10,
IC11
This is a trigger input pin for input capture (ICU) 0 and 1.
Since this input is used as required for input capture 0 and 1 (ICU)
ch.0, ch.01, ch.10 and ch.11 input operation, output by other
functions must be suspended except for intentional operation.
115
116
P24
E
E
This is a general-purpose I/O port.
AIN0
This port can be used as count clock A input for 8/16-bit up/down
counter/timer 0.
P25
This is a general-purpose I/O port.
BIN0
This port can be used as count clock B input for 8/16-bit up/down
counter/timer 0.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
8
MB90520 Series
Pin no.
Circuit
type
Pin name
P26
Function
This is a general-purpose I/O port.
LQFP-120*1
QFP-120*2
117
118
E
ZIN0
This port can be used as count clock Z input for 8/16-bit up/down
counter/timer 0.
INT7
This is a request input pin of the DTP/external interrupt circuit
ch.7.
P27
E
This is a general-purpose I/O port.
ADTG
This is an external trigger input pin of the 8/10-bit A/D converter.
Since this input is used as required for 8/10-bit A/D converter input
operation, output by other functions must be suspended except for
intentional operation.
120
1
P30
E
E
This is a general-purpose I/O port.
This is a general-purpose I/O port.
P31
CKOT
This is a clock monitor function output pin.
This function is valid when clock monitor output is enabled.
2
3
4
5
6
P32
E
E
E
E
E
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT0 is disabled.
OUT0
P33
This is an event output pin for output compare 0 (OCU) ch.0.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT1 is disabled.
OUT1
P34
This is an event output pin for output compare 0 (OCU) ch.1.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT2 is disabled.
OUT2
P35
This is an event output pin for output compare 0 (OCU) ch.2.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT3 is disabled.
OUT3
P36
This is an event output pin for output compare 0 (OCU) ch.3.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the PG00
is disabled.
PG00
This is an output pin of 8/16-bit PPG timer 0.
This function becomes valid when waveform output from PG00 is
enabled.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
9
MB90520 Series
Pin no.
Circuit
type
Pin name
P37
Function
This is a general-purpose I/O port.
This function becomes valid when waveform output from the PG01
is disabled.
LQFP-120*1
QFP-120*2
7
E
PG01
This is an output pin of 8/16-bit PPG timer 0.
This function becomes valid when waveform output from PG01 is
enabled.
9,
10
P40,
P41
D
This is a general-purpose I/O port.
This function becomes valid when waveform output from the PG10
and PG11 are disabled.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
PG10,
PG11
This is an output pin of 8/16-bit PPG timer 1.
This function becomes valid when waveform outputs from PG10
and PG11 are enabled.
11
P42
D
This is a general-purpose I/O port.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
SIN0
This is a serial data input pin of UART (SCI).
Because this input is used as required when UART (SCI) is
performing input operations, it is necessary to stop outputs by
other functions unless such outputs are made intentionally.
When using other output functions as well, disable output during
SIN operation.
12
13
14
P43
D
D
D
This is a general-purpose I/O port.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
SOT0
P44
This is a serial data output pin of UART (SCI).
This function becomes valid when serial data output from UART
(SCI) is enabled.
This is a general-purpose I/O port.
This function can be set by the pull-up resistor setup register
(RDR4) for input. For output, however, this function is invalid.
SCK0
P45
This is a serial clock I/O pin of UART (SCI).
This function becomes valid when serial clock output from UART
(SCI) is enabled.
This is a general-purpose I/O port.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
SIN1
This is a data input pin for extended I/O serial interface 0.
Since this input is used as required for serial data input operation,
output by other functions must be suspended except for intentional
operation. When using other output functions as well, disable
output during SIN operation.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
10
MB90520 Series
Pin no.
Circuit
type
Pin name
P46
Function
This is a general-purpose I/O port.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
LQFP-120*1
QFP-120*2
15
16
35
D
D
D
SOT1
P47
This is a data output pin for extended I/O serial interface 0.
This function becomes valid when serial data output from SOT1 is
enabled.
This is a general-purpose I/O port.
This function can be set by the port 4 input pull-up resistor setup
register (RDR4) for input. For output, however, this function is
invalid.
SCK1
This is a serial clock I/O pin for extended I/O serial interface 0.
This function becomes valid when serial clock output from SCK1 is
enabled.
P50
This is a general-purpose I/O port.
SIN2
This is a data input pin for extended I/O serial interface 1.
Since this input is used as required for serial data input operation,
output by other functions must be suspended except for intentional
operation.
AIN1
This port can be used as count clock A input for 8/16-bit up/down
counter/timer 1.
36
37
P51
D
D
This is a general-purpose I/O port.
SOT2
This is a data output pin for extended I/O serial interface 1.
This function becomes valid when serial data output from SOT2 is
enabled.
BIN1
This port can be used as count clock B input for 8/16-bit up/down
counter/timer 1.
P52
This is a general-purpose I/O port.
SCK2
This is a serial clock I/O pin for extended I/O serial interface 1.
This function becomes valid when serial clock output from serial
SCK2 is enabled.
ZIN1
This port can be used as control clock Z input for 8/16-bit up/down
counter/timer 1.
40,
41
P53,
P54
I
This is a general-purpose I/O port.
DA0,
DA1
These are analog signal output pins for 8-bit D/A converter ch.0
and ch.1.
46 to 53
P60 to P67
K
This is a general-purpose I/O port.
The input function become valid when the analog input enable
register (ADER) is set to select a port.
AN0 to AN7
These are analog input pins of the 8/10-bit A/D converter.
This function is valid when the analog input enable register
(ADER) is enabled.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
11
MB90520 Series
Pin no.
Circuit
type
Pin name
P70,
Function
This is a general-purpose I/O port.
LQFP-120*1
QFP-120*2
55,
57
E
P72
TI0,
TI1
These are event input pins for 16-bit re-load timers 0 and 1.
Since this input is used as required for 16-bit re-load timers 0 and
1 operation, output by other functions must be suspended except
for intentional operation.
OUT4,
OUT6
These are event output pins for output compare 1 (OCU) ch.4 and
ch.6.
This function is valid when output for each channel is enabled.
56,
58
P71,
P73
E
This is a general-purpose I/O port.
This function is valid when TO0 and TO1 output are disabled.
TO0,
TO1
These are output pins for 16-bit re-load timers 0 and 1.
This function is valid when TO0 and TO1 output are enabled.
OUT5,
OUT7
These are event output pins for output compare 1 (OCU) ch.5 and
ch.7.
This function is valid when output for each channel is enabled.
59 to 62
64 to 71
P74 to P77
L
L
This is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
COM0 to
COM3
These are common pins for the LCD controller/driver.
This function is valid with common output specified for the LCD
controller/driver control register.
P80 to P87
This is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
SEG16 to
SEG23
These are segment outputs for the LCD controller/driver.
This function is valid with segment output specified for the LCD
controller/driver control register.
72,
75 to 81
P90,
P91 to P97
M
This is a general-purpose I/O port.
The maximum IOL can be 10mA.
This function is valid with port output specified for the LCD
controller/driver control register.
SEG24,
SEG25 to
SEG31
These are segment outputs for the LCD controller/driver.
This function is valid with port output specified for the LCD
controller/driver control register.
17 to 24
25 to 32
SEG00 to
SEG07
F
L
These are pins dedicated to LCD segments 00 to 07 for the LCD
controller/driver.
PA0 to PA7
This is a general-purpose I/O port.
This function is valid with port output specified for the LCD
controller/driver control register.
SEG08 to
SEG15
These are pins for LCD segments 08 to 15 for the LCD controller/
driver.
Units of four ports or segments can be selected by the internal
register in the LCD controller.
*1: FPT-120P-M05
*2: FPT-120P-M13
(Continued)
12
MB90520 Series
(Continued)
Pin no.
Circuit
type
LQFP-120*1
Pin name
Function
QFP-120*2
34
C
G
This is a capacitance pin for power supply stabilization.
Connect an external ceramic capacitor rated at about 0.1 µF. This
capacitor is not, however, required for the M90F523 (flash
product).
82 to 85
V0 to V3
VCC
N
This is a pin for the reference power supply for the LCD controller/
driver.
8,
54,
94
Power
supply
This is a power supply (5.0 V) input pin to the digital circuit.
33,
63,
91,
119
VSS
Power
supply
This provides the GND level (0.0 V) input pin for the digital circuit.
42
AVCC
H
J
This is a power supply for the analog circuit.
Make sure to turn on/turn off this power supply with a voltage
exceeding AVCC applied to VCC.
43
AVRH
This is a reference voltage input to the analog circuit.
Make sure to turn on/turn off this power supply with a voltage
exceeding AVRH applied to AVCC.
44
45
38
AVRL
AVSS
DVCC
H
H
H
This is a reference voltage input to the analog circuit.
This is a GND level of the analog circuit.
This is the Vref input pin for the D/A converter.
The voltage to be applied must not exceed VCC.
39
DVSS
H
This is the GND level pin for the D/A converter.
The potential must be the same as VSS.
*1: FPT-120P-M05
*2: FPT-120P-M13
13
MB90520 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• High-speed oscillation feedback resistor
X1
approx. 1MΩ
Nch
Pch
X0
Pch
Nch
Standby control signal
B
• Low-speed oscillation feedback resistor
X1A
X0A
approx. 1MΩ
Pch
Nch
Pch
Nch
Standby control signal
C
D
• Hysteresis input
R
Hysteresis input
• Hysteresis input (can be set with the input
pull-up resistor)
CMOS level output
• Pull-up resistor approx. 50 kΩ
• Provided with a standby control function
for input interruption
Selecting signal
with or without a
input pull-up resistor
Pch
Pch
Nch
R
Hysteresis input
IOL = 4 mA
Standby control for
input interruption
(Continued)
14
MB90520 Series
Type
Circuit
Remarks
E
• CMOS hysteresis input/output
• CMOS level output
VCC
• Provided with a standby control function
for input interruption
Pch
Nch
R
Hysteresis input
IOL = 4 mA
Standby control for input interruption
F
• Pins dedicated to segment output
Pch
Nch
R
G
• C pin output
(Pin for capacitor connection)
N.C. pin for the MB90F523
Pch
Nch
H
• Analog power input protector
Pch
Nch
AVP
I
• CMOS hysteresis input/output
• Pin for analog output/CMOS output
(During analog output, CMOS output is
not produced.)
VCC
Pch
(Analog output has priority over CMOS
output: DAE = 1)
Nch
• Provided with a standby control function
for input interruption
R
Hysteresis input
Standby control for input interruption
DAO
IOL = 4 mA
(Continued)
15
MB90520 Series
Type
Circuit
Remarks
J
• Input pin for ref+ power for the A/D
converter
Provided with power protection
ANE
AVR
ANE
Pch
Pch
Nch
Nch
K
• Hysteresis input/analog input
• CMOS output
• Provided with a standby control for input
interruption
Pch
Nch
R
Hysteresis input
Standby control for input interruption
Analog input
IOL = 4 mA
L
• CMOS hysteresis input/output
• Segment input
• Standby control to cut off the input is
available in segment input operation
Pch
Nch
R
Hysteresis input
Standby control for input interruption
SEG
IOL = 4 mA
M
• Hysteresis input
• Nch open-drain output
Nch
(High current for LCD drive)
• Standby control to cut off the input is
available in segment input operation
Nch
R
Hysteresis input
Standby control for input interruption
IOL = 10 mA
N
• Reference power supply pin for the LCD
controller
Pch
R
Nch
IOL = 10 mA
16
MB90520 Series
■ HANDLING DEVICES
1. Ensuring that the Voltage does not exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when a voltage exceeding VCC or below VSS is applied to
input or output pins or if a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased, resulting in thermal
breakdown of devices. To avoid the latch-up, make sure that the voltage does not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog power voltages (AVCC, AVRH, DVCC)
and analog input voltages do not exceed the digital voltage (VCC).
And also make sure the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power
supply voltage (VCC).
2. Handling Unused Pins
• Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled-up or pull-down through at least 2 kΩ resistance.
• Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
• Using external clock
X0
MB90520 series
Open
X1
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X0A pin and X1A pin.
5. Power Supply Pins
In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to
avoid abnormal operations including latch-ups. However, the pins should be connected to external powers and
groundlinestolowertheelectro-magneticemissionlevel, topreventabnormaloperationofstrobesignalscaused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect Vcc and Vss pins via lowest impedance to power lines.
It is recommended that a bypass capacitor of around 0.1 µF be placed between the Vcc and Vss pins near the
device.
17
MB90520 Series
V
CC
SS
• Usingpowersupplypins
V
VCC
VSS
V
SS
CC
MB90520 series
V
CC
SS
V
V
VCC
VSS
6. Crystal Oscillator Circuit
Noise around the X0 and X1 pins may cause abnormal operation in this device. In designing printed circuit
boards, the X0 and X1 pins and crystal oscillator (or ceramic oscillator), as well as the bypass capacitor to the
ground, should be placed as close as possible, and the related wiring should have as few crossings with other
wiring as possible.
Circuit board artwork in which the area of the X0 and X1 pins is surrounded by grounding is recommended for
stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC,
DVSS) and analog inputs (AN0 to AN7) after turning on the digital power supply (VCC).
Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that AVRH and DVCC do not exceed AVCC (turning on/off the analog and digital supplies simultaneously is
acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter and those of D/A converter to AVCC = DVCC = VCC, AVSS = AVRH = AVRL
= VSS.
9. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
10.Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V).
11.Use of SEG/COM Pins for the LCD Controller/Driver as Ports
In MB90520 series, pins SEG08 to SEG31, and COM0 to COM3 can also be used as general-purpose ports.
The electrical standard is such that pins SEG08 to SEG23, and COM0 to COM3 have the same ratings as the
CMOS output port, while pins SEG24 to SEG31 have the same ratings as the open-drain type.
18
MB90520 Series
12.Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during
a power-on reset) after the power is turned on.
Pay attention to the port output timing shown as follow
• Timming chart of indeterminate outputs from ports o and 1
Oscillation setting time 2
Step-down circuit
1
setting time
Vcc(power-supply pin)
PONR(power-on reset) signal
RST(external asynchronous reset) signal
RST(internal reset) signal
Oscillation clock signal
KA(internal operation clock A) signal
KB(internal operation clock B) signal
PORT(port output)signal
indereterminate period
* : 1:Step-down circuit setting time : 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)
* : 2:Oscillation setting time: 218/oscillation clock frequency (oscillation cllock frequency of 16 MHz: 16.38 ms)
13.Initialization
The device contains internal registers that can be initialized only by a power-on reset. To initialize the internal
registers, restart the power supply.
14. Interrupt Recovery from Standby
If an external interrupt is used for recovery from standby, use an “H” level input request. An “L” level request
causes abnormal operation.
15.Precautions for Use of “DIV A, Ri”, and “DIVW A, Ri” Instructions
The signed multiplication-division instructions “DIV A, Ri”, and “DIVW A, RWi” should be used when the
corresponding bank registers (DTB, ADB, USB, SSB) are set to value “00h”. If the corresponding bank registers
(DTB, ADB, USB, SSB) are set to a value other than “00h,” then the remainder obtained after the execution of
the instruction will not be placed in the instruction operand register.
16. Precautions for Use of REALOS
Extended intelligent I/O service(EI2OS) cannot be used, when REALOS is used.
19
MB90520 Series
■ BLOCK DIAGRAM
8
8
8
Port 8*5, 9*5, A*5
24
P80/SEG16 to P87/SEG23
P90/SEG24 to P97/SEG31
PA0/SEG08 to PA7/SEG15
SEG00 to SEG07
F2MC-16LX
CPU
LCD
controller/
driver
4
Oscillation clock
8
4
4
X0, X1
X0A, X1A
Clock control
block*1
Sub clock
V0 to V3
P74/COM0 to P77/COM3
(including
RST
HST
timebase timer)
Port 7*4
Port 0*2
16-bit
re-load
timer 0
P07
7
7
P00/INT0 to P06/INT6
DTP/
16-bit
re-load
timer 1
external
interrupt
circuit
P70/TI0/OUT4
P71/TO0/OUT5
P72/TI1/OUT6
P73/TO1/OUT7
16-bit
I/O timer 2
Port 2*4
Output
4
compare
(OCU)
P24/AIN0
P25/BIN0
P26/ZIN0/INT7
8/16-bit
3
up/down
counter/timer
0, 1
16-bit
free-run
timer 2
16-bit
Input
2
P22/IC10
P23/IC11
I/O timer 1
capture 1
(ICU)
Input
2
P20/IC00
P21/IC01
capture 0
(ICU)
Port 2*4
16-bit
free-run
timer 1
Port 6*4
8
8
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
P60/AN0 to P67/AN7
Output
4
compare 0
(OCU)
AVCC
AVSS
AVRH
AVRL
P27/ADTG
8/10-bit
A/D
converter
P31/CKOT
Clock output
Port 3*4
P30
P36/PG00
P37/PG01
2
8/16-bit
PPG
timer 0, 1
2
P40/PG10
P41/PG11
Port 2*4
Interrupt controller
Port 5*5
P42/SIN0
P43/SOT0
P44/SCK0
UART
(SCI)
P45/SIN1
P46/SOT1
P47/SCK1
P50/SIN2/AIN1
P51/SOT2/BIN1
P52/SCK2/ZIN1
SIO ch.0
Port 4*2
SIO ch.1
Port 1*2
P53/DA0
P54/DA1
2
8-bit D/A
converter
× 2 ch.
8
8
Wake-up
interrupt
P10/WI0 to P17/WI7
DVCC
DVSS
RAM
ROM
Other pins
MD0 to MD2,
C, VCC, VSS
Notes: Actually 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported.
*1: The clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller.
*2: A register for setting a pull-up resistor is supported.
*3: This is a high-current port for an LCD drive.
*4: A register for setting a pull-up resistor is supported. Signals in the CMOS level are input and output.
*5: Also used for LCD output. With this port used as is, Nch open-drain output develops. A register for setting a pull-up resistor
is supported.
20
MB90520 Series
■ MEMORY MAP
Single chip mode
A mirroring function
is supported.
FFFFFFH
ROM area
Address #1
FE0000H
010000H
ROM area
(image of
bank FF)
Address #2
004000H
002000H
Address #3
Register
RAM
000100H
0000C0H
000000H
Peripheral
Part number
MB90522
Address #1*
FF0000H
Address #2*
004000H
Address #3*
001100H
MB90523
FE0000H
004000H
001100H
MB90F523
FE0000H
004000H
001100H
: Internal access memory
: Access prohibited
*: Addresses #1, #2 and #3 vary with product type.
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the
same address, enabling reference of the table on the ROM without stating “far.”
For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are
actually accessed. Since the ROM area of the FF bank exceeds 48k bytes, the whole area cannot be
reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it
were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in
the area of FF4000H to FFFFFFH.
21
MB90520 Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
: Accumlator (A)
AH
AL
Dual 16-bit register used for storing results of calculation, etc. The two 16-bit
registers can be combined to be used as a 32-bit register.
: User stack pointer (USP)
16-bit pointer for containing a user stack address.
USP
SSP
PS
: System stack pointer (SSP)
16-bit pointer for displaying the status of the system stack address.
: Processor status (PS)
16-bit register for displaying the system status.
: Program counter (PC)
16-bit register for displaying the storing location of the current instruction code.
PC
: Direct page register (DPR)
DPR
8-bit register for specifying bit 8 through 15 of the operand address in the short
direct addressing mode.
: Program bank register (PCB)
8-bit register for displaying the program space.
PCB
DTB
USB
SSB
: Data bank register (DTB)
8-bit register for displaying the data space.
: User stack bank register (USB)
8-bit register for displaying the user stack space.
: System stack bank register (SSB)
8-bit register for displaying the system stack space.
: Additional data bank register (ADB)
8-bit register for displaying the additional data space.
ADB
8-bit
16-bit
32-bit
22
MB90520 Series
• General-purpose registers
Maximum of 32 banks
RW7
R7
R6
RL3
RL2
RL1
RL0
RW6
RW5
RW4
R5
R3
R4
R2
R1
R0
RW3
RW2
RW1
RW0
000180H + (RP × 10H )
16-bit
• Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
ILM2 ILM1 ILM0 B4
B3
0
B2
0
B1
0
B0
0
—
—
I
S
1
T
X
N
X
Z
X
V
X
C
Initial value
0
0
0
0
0
X
— : Unused
X : Indeterminate
23
MB90520 Series
■ I/O MAP
Abbreviated
Read/
write
Address
register
name
Register name
Port 0 data register
Resource name
Initial value
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port A data register
Port 7,
00000BH
LCDCMR Port 7/COM pin selection register
R/W
R/W
X X X X 0 0 0 0 B
LCD controller/driver
00000CH
00000DH
00000EH
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
000019H
00001AH
16-bit I/O timer
(output compare 1
(OCU) section)
X X X X X X X X B
X X X X X X X X B
OCP4
OCU compare register ch.4
(Disabled)
EIFR
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
Wake-up interrupt flag register
Port 0 direction register
Port 1 direction register
Port 2 direction register
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Port A direction register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Wake-up interrupt X X X X X X X 0 B
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X X X 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
Port 6,
00001BH
ADER
OCP5
Analog input enable register
OCU compare register ch.5
R/W
R/W
1 1 1 1 1 1 1 1 B
A/Dconverter
00001CH
00001DH
00001EH
00001FH
16-bit I/O timer
(output compare 1
(OCU) section)
X X X X X X X X B
X X X X X X X X B
(Disabled)
Wake-up interrupt enable register
Wake-up interrupt
EICR
W
0 0 0 0 0 0 0 0 B
(Continued)
24
MB90520 Series
Abbreviated
register
name
Read/
write
Resource
Initial value
name
Address
Register name
Serial mode register
000020H
000021H
SMR
R/W
0 0 0 0 0 0 0 0 B
R/Wor
W
SCR
Serial control register
0 0 0 0 0 1 0 0 B
UART
SIDR/
SODR
Serial input data register/
serial output data register
R
W
(SCI)
000022H
000023H
X X X X X X X X B
R/Wor
R
SSR
Serial status register
0 0 0 0 1 X 0 0 B
000024H
000025H
000026H
SMCSL0
SMCSH0
SDR0
Serial mode control lower status register 0 R/W
Serial mode control upper status register 0 R/W
X X X X 0 0 0 0 B
Extended I/O
serial
0 0 0 0 0 0 1 0 B
interface 0
Serial data register 0
R/W
X X X X X X X X B
Communica-
000027H
CDCR
Communications prescaler control register R/W tions prescaler 0 X X X 1 1 1 1 B
control register
000028H
000029H
00002AH
00002BH
00002CH
00002DH
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
SMCSL1
SMCSH1
SDR1
Serial mode control lower status register 1 R/W
Serial mode control upper status register 1 R/W
X X X X 0 0 0 0 B
0 0 0 0 0 0 1 0 B
X X X X X X X X B
Extended I/O
serial
interface 1
Serial data register 1
R/W
(Disabled)
0 0 0 0 X X 0 0 B
X X X 0 0 0 0 0 B
0 0 0 0 X X 0 0 B
X X X 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
OCS45
OCS67
OCU control status register ch.45
OCU control status register ch.67
R/W
R/W
16-bit I/O timer
(output com-
pare 1 (OCU)
section)
ENIR
EIRR
DTP/interrupt enable register
DTP/interrupt factor register
R/W
R/W
DTP/external
interrupt circuit
ELVR
Request level setting register
R/W
16-bit I/O timer X X X X X X X X B
(output com-
OCP6
OCU compare register ch.6
R/W
pare 1 (OCU)
000035H
X X X X X X X X B
section)
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
ADCS1
ADCS2
ADCR1
ADCR2
DADR0
DADR1
DACR0
DACR1
A/D control status register lower digits
A/D control status register upper digits
A/D data register lower digits
A/D data register upper digits
D/A converter data register ch.0
D/A converter data register ch.1
D/A control register 0
R/W
R/W
R
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
8/10-bit A/D
converter
X X X X X X X X B
R or W
R/W
R/W
R/W
R/W
0 0 0 0 1 X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X 0 B
X X X X X X X 0 B
8-bit D/A
converter
D/A control register 1
Clock monitor
function
00003EH
CLKR
Clock output enable register
R/W
X X X X 0 0 0 0 B
(Continued)
25
MB90520 Series
Abbreviated
Read/
write
Address
register
name
Register name
Resource name
Initial value
00003FH
000040H
000041H
000042H
000043H
000044H
000045H
(Disabled)
PRLL0
PRLH0
PRLL1
PRLH1
PPGC0
PPGC1
PPG0 re-load register L
PPG0 re-load register H
PPG1 re-load register L
PPG1 re-load register H
R/W
R/W
R/W
R/W
R/W
R/W
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
0 X 0 0 0 X X 1 B
0 X 0 0 0 0 0 1 B
8/16-bit PPG
timer 0, 1
PPG0 operating mode control register
PPG1 operating mode control register
PPGOE0/
PPGOE1
000046H
PPG0 and 1 output control registers
R/W
0 0 0 0 0 0 0 0 B
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
000059H
00005AH
00005BH
00005CH
00005DH
00005EH
00005FH
000060H
000061H
(Disabled)
Timer control status register lower ch.0
Timer control status register upper ch.0
0 0 0 0 0 0 0 0 B
X X X X 0 0 0 0 B
X X X X X X X X B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
X X X X 0 0 0 0 B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
0 0 0 0 0 0 0 0 B
TMCSR0
R/W
R/W
R/W
R/W
R
16-bit re-load
timer 0
TMR0/
TMRLR0
16-bit timer register upper, lower ch.0/
16-bit re-load register upper, lower ch.0
Timer control status register lower ch.1
Timer control status register upper ch.1
TMCSR1
16-bit re-load
timer 1
TMR1/
TMRLR1
16-bit timer register upper, lower ch.1/
16-bit re-load register upper, lower ch.1
IPCP0
ICU data register ch.0
ICU data register ch.1
16-bit I/O timer
(input compare 0,
1 (ICU) section)
IPCP1
ICS01
R
ICU control status register
(Disabled)
R/W
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
16-bit I/O timer
(16-bit free-run
timer 1 section)
TCDT1
TCCS1
Free-run timer data register 1
R/W
R/W
Free-run timer control status register 1
(Disabled)
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
(Continued)
OCP0
OCP1
OCP2
OCP3
OCU compare register ch.0
OCU compare register ch.1
OCU compare register ch.2
OCU compare register ch.3
R/W
R/W
R/W
R/W
16-bit I/O timer
(output compare 0
(OCU) section)
26
MB90520 Series
Abbreviated
register
name
Read/
write
Address
Register name
Resource name
Initial value
000062H
000063H
000064H
000065H
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
0 0 0 0 X X 0 0 B
X X X 0 0 0 0 0 B
0 0 0 0 X X 0 0 B
X X X 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
OCS01
OCS23
OCU control status register ch.01
OCU control status register ch.23
R/W
R/W
16-bit I/O timer
(output compare 0
(OCU) section)
16-bit I/O timer
(16-bit free-run
timer 2 section)
TCDT2
TCCS2
Free-run timer data register 2
R/W
R/W
Free-run timer control status register 2
(Disabled)
LCR0
LCR1
R/W
R/W
0 0 0 1 0 0 0 0 B
0 0 0 0 0 0 0 0 B
X X X X X X X X B
LCD controller/
driver
LCDC control registers 0 and 1
OCU compare register ch.7
16-bit I/O timer
(output compare 1
(OCU) section)
OCP7
R/W
00006DH
00006EH
X X X X X X X X B
(Disabled)
ROM mirroring
function
selection module
ROM mirroring function selection
register
00006FH
ROMM
VRAM
W
X X X X X X X 1 B
X X X X X X X X B
000070H
to
00007FH
LCD controller/
driver
RAM for LCD indication
R/W
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
UDCR0
UDCR1
RCR0
Up/down count register 0
Up/down count register 1
Re-load compare register 0
Re-load compare register 1
Counter status register 0
R
R
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
8/16-bit up/down
counter/timer
0, 1
W
RCR1
W
CSR0
R/W
(Reserved area)*3
CCRL0
CCRH0
CSR1
X 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 B
8/16-bit up/down
counter/timer
0, 1
Counter control register 0
Counter status register 1
R/W
R/W
(Reserved area)*3
CCRL1
CCRH1
8/16-bit up/down X 0 0 0 0 0 0 0 B
counter/timer
Counter control register 1
R/W
00008BH
00008CH
X 0 0 0 0 0 0 0 B
0, 1
Port 0 input pull-up resistor setup
register
RDR0
RDR1
RDR4
R/W
R/W
R/W
Port 0
0 0 0 0 0 0 0 0 B
Port 1 input pull-up resistor setup
register
00008DH
00008EH
Port 1
Port 4
0 0 0 0 0 0 0 0 B
Port 4 input pull-up resistor setup
register
0 0 0 0 0 0 0 0 B
(Continued)
27
MB90520 Series
Abbreviated
Read/
write
Address
register
name
Register name
Resource name
Initial value
00008FH
to
(Area used by the system)*3
00009DH
Address match
detection
Program address detection control
status register
00009EH
00009FH
PACSR
DIRR
R/W
R/W
0 0 0 0 0 0 0 0 B
X X X X X X X 0 B
function
Delayed inter-
rupt generation
module
Delayed interrupt factor generation/
cancellation register
Low-power consumption mode
control register
R/W or
W
0000A0H
0000A1H
LPMCR
CKSCR
0 0 0 1 1 0 0 0 B
1 1 1 1 1 1 0 0 B
Low-power
consumption
(stand-by) mode
R/W or
R
Clock select register
0000A2H
to
(Disabled)
0000A7H
0000A8H
0000A9H
WDTC
TBTC
Watchdog timer control register
Timebase timer control register
R or W Watchdog timer X X X X X X X X B
R/W
Timebase timer 1 X X 0 0 0 0 0 B
R/W or
R
0000AAH
WTC
Clock timer control register
Clock timer
1 X 0 0 1 0 0 0 B
0000ABH
to
(Disabled)
0000ADH
0000AEH
0000AFH
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
FMCS
Flash control register
R/W
Flash interface
1 X X 0 0 1 0 0 B
(Disabled)
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
Interrupt
controller
0 0 0 0 0 1 1 1 B
(Continued)
28
MB90520 Series
(Continued)
Abbreviated
register
name
Read/
write
Address
Register name
Resource name
Initial value
0000BEH
0000BFH
ICR14
ICR15
Interrupt control register 14
Interrupt control register 15
R/W
R/W
0 0 0 0 0 1 1 1 B
0 0 0 0 0 1 1 1 B
Interrupt
controller
0000C0H
to
(External area)*1
0000FFH
000100H
to
(RAM area)*2
00####H
00####H
to
(Reserved area)*3
001FEFH
001FF0H
001FF1H
001FF2H
001FF3H
001FF4H
001FF5H
Program address detection register 0
Program address detection register 1
Program address detection register 2
Program address detection register 3
Program address detection register 4
Program address detection register 5
R/W
R/W
R/W
R/W
R/W
R/W
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
X X X X X X X X B
PADR0
PADR1
Address match
detection
function
001FF6H
to
(Reserved area)*3
001FFFH
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
Descriptions for initial value
0 : The initial value is “0.”
1 : The initial value is “1.”
X : The initial value is indeterminate.
*1: This area is the only external access area having an address of 0000FFH or lower. An access operation to this
area is handled as that to external I/O area.
*2: For details of the “RAM area”, see the memory map.
*3: The “reserved area” is basically disabled because it is used in the system.
*4: “Area used by the system” is the area set by the resistor for evaluating tool.
Notes: • For bits initialized by reset operations, the initial value set by the reset operation is listed as an initial value.
Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases in which initialization is performed or not performed,
depending on the types of the reset. The value listed is the initial value in cases where initialization is per
formed.
• The addresses following 0000FFH are reserved. No external bus access signal is generated.
• Boundary ####H between the “RAM area” and the“ reserved area” varies with the product models.
• Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU
compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU)
0 and 1.
29
MB90520 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS
Interrupt vector
Number Address
Interrupt control register
EI2OS
Interrupt source
Priority
support
ICR
—
Address
Reset
×
×
×
# 08
# 09
# 10
# 11
# 12
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
—
—
—
High
INT9 instruction
Exception
—
—
8/10-bit A/D converter
Timebase timer
ICR00
ICR01
ICR02
ICR03
0000B0H
0000B1H
0000B2H
0000B3H
×
DTP0/DTP1 (external interrupt 0/
external interrupt 1)
# 13
FFFFC8H
16-bit free-run timer 1 overflow
Extended I/O serial interface 0
Wake-up interrupt
×
×
# 14
# 15
# 16
# 17
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
Extended I/O serial interface 1
DTP2/DTP3 (external interrupt 2/
external interrupt 3)
# 18
# 19
# 20
# 21
# 22
# 23
# 24
FFFFB4H
FFFFB0H
FFFFACH
FFFFA0H
FFFFA4H
FFFFA0H
FFFF9CH
8/16-bit PPG timer 0 counter
borrow
×
ICR04
ICR05
ICR06
0000B4H
0000B5H
0000B6H
DTP4/DTP5 (external interrupt 4/
external interrupt 5)
8/16-bit up/down counter/timer 0
compare match
8/16-bit up/down counter/timer 0
overflow up/down inversion
8/16-bit PPG timer 1 counter
borrow
×
DTP6/DTP7 (external interrupt 6/
external interrupt 7)
Output compare 1 (OCU) ch.4/ch.5
match
# 25
# 26
# 27
# 28
# 29
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
ICR07
ICR08
0000B7H
0000B8H
Clock prescaler
×
×
Output compare 1 (OCU) ch.6/ch.7
match
16-bit free-run timer 2 overflow
8/16-bit up/down counter/timer 1
compare match
ICR09
ICR10
0000B9H
0000BAH
8/16-bit up/down counter/timer 1
overflow, up/down inversion
# 30
FFFF84H
Input capture 0 (ICU) include
Input capture 1 (ICU) include
# 31
# 32
FFFF80H
FFFF7CH
Low
(Continued)
30
MB90520 Series
(Continued)
Interrupt source
Interrupt vector
Number Address
Interrupt control register
Priority
EI2OS
support
ICR
Address
Output compare 0 (OCU) ch.0
match
# 33
# 34
# 35
# 36
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
High
ICR11
0000BBH
Output compare 0 (OCU) ch.1
match
Output compare 0 (OCU) ch.2
match
ICR12
0000BCH
Output compare 0 (OCU) ch.3
match
UART (SCI) reception complete
16-bit re-load timer 0
# 37
# 38
# 39
# 40
# 41
FFFF68H
FFFF64H
FFFF60H
FFFF5CH
FFFF58H
ICR13
ICR14
0000BDH
0000BEH
UART (SCI) transmission complete
16-bit re-load timer 1
Reserved
×
×
ICR15
0000BFH
Delayed interrupt generation
module
# 42
FFFF54H
Low
: Can be used
×
: Can not be used
: Can be used with EI2OS stop function
31
MB90520 Series
■ PERIPHERALS
1. I/O Port
(1) Input/Output Port
Port 0 through A are general-purpose I/O ports having a combined function as a resource input. The I/O ports
can be used as general-purpose I/O ports only in the single-chip mode.
• Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register,
the destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register for output. However, values of bits configured as inputs by the DDR register are changed
because input values to the pins are written into the output latch. To avoid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when switching the bit
used as input to output.
• Operation as input port
The pin is configured as input by setting the corresponding bit of the DDR register to “0.”
When the pin is configured as an input, the output buffer is turned off and the pin is put into a high-impedance
status.
When data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
32
MB90520 Series
(2) Register Configuration
• Port 0 data register (PDR0)
bit 7
P07
R/W
bit 6
P06
R/W
bit 5
P05
R/W
bit 4
P04
R/W
bit 3
P03
R/W
bit 2
P02
R/W
bit 1
P01
R/W
bit 0
P00
R/W
Initial value
XXXXXXXX
Address
000000H
B
• Port 1 data register (PDR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
P11
bit 8
P10
Initial value
Address
B
XXXXXXXX
P17
P16
R/W
P15
R/W
P14
R/W
P13
R/W
P12
R/W
000001H
R/W
R/W
R/W
• Port 2 data register (PDR2)
bit 7
P27
R/W
bit 6
P26
R/W
bit 5
P25
R/W
bit 4
P24
R/W
bit 3
P23
R/W
bit 2
P22
R/W
bit 1
P21
R/W
bit 0
P20
R/W
Initial value
XXXXXXXX
Address
000002H
B
• Port 3 data register (PDR3)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Address
B
XXXXXXXX
P34
R/W
P37
R/W
P36
R/W
P35
R/W
P33
R/W
P32
R/W
P31
R/W
P30
R/W
000003H
• Port 4 data register (PDR4)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
Address
000004H
B
P47
R/W
P46
R/W
P45
R/W
P44
R/W
P43
R/W
P42
R/W
P41
R/W
P40
R/W
• Port 5 data register (PDR5)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Address
B
XXXXXXXX
—
—
—
—
—
—
P54
R/W
P53
R/W
P52
R/W
P51
R/W
P50
R/W
000005H
• Port 6 data register (PDR6)
bit 7
P67
R/W
bit 6
P66
R/W
bit 5
P65
R/W
bit 4
P64
R/W
bit 3
P63
R/W
bit 2
P62
R/W
bit 1
P61
R/W
bit 0
P60
R/W
Initial value
XXXXXXXX
Address
000006H
B
• Port 7 data register (PDR7)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
P71
R/W
bit 8
P70
R/W
Address
B
XXXXXXXX
P77
R/W
P76
R/W
P75
R/W
P74
R/W
P73
R/W
P72
R/W
000007H
• Port 8 data register (PDR8)
bit 7
P87
R/W
bit 6
P86
R/W
bit 5
P85
R/W
bit 4
P84
R/W
bit 3
P83
R/W
bit 2
P82
R/W
bit 1
P81
R/W
bit 0
P80
R/W
Initial value
XXXXXXXX
Address
000008H
B
• Port 9 data register (PDR9)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Initial value
Address
B
XXXXXXXX
P95
R/W
P97
R/W
P96
R/W
P94
R/W
P93
R/W
P92
R/W
P91
R/W
P90
R/W
000009H
(Continued)
33
MB90520 Series
• Port A data register (PDRA)
bit 7
bit 6
PA6
R/W
bit 5
PA5
R/W
bit 4
PA4
R/W
bit 2
PA2
R/W
bit 1
PA1
R/W
bit 0
PA0
R/W
bit 3
PA3
R/W
Initial value
XXXXXXXX
Address
PA7
B
00000AH
R/W
• Port 0 direction register (DDR0)
bit 7
bit 6
D06
R/W
bit 5
D05
R/W
bit 4
D04
R/W
bit 3
D03
R/W
bit 2
D02
R/W
bit 1
D01
R/W
bit 0
D00
R/W
Initial value
Address
D07
B
00000000
000010H
R/W
• Port 1 direction register (DDR1)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
D11
bit 8
D10
Address
B
D17
R/W
D16
D15
D14
D13
D12
00000000
000011H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 2 direction register (DDR2)
bit 7
bit 6
D26
bit 5
D25
bit 4
D24
bit 3
D23
bit 2
D22
bit 1
D21
bit 0
D20
Initial value
00000000
Address
D27
B
000012H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 3 direction register (DDR3)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
D31
bit 8
D30
Address
B
D37
D36
D35
D34
R/W
D33
R/W
D32
R/W
00000000
000013H
R/W
R/W
• Port 4 direction register (DDR4)
bit 7
bit 6
D46
bit 5
D45
bit 4
D44
bit 3
D43
bit 2
D42
bit 1
D41
bit 0
D40
Initial value
00000000
Address
D47
B
000014H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 5 direction register (DDR5)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
D51
bit 8
D50
Initial value
Address
000015H
—
—
—
D54
R/W
D53
R/W
D52
R/W
B
XXX00000
R/W
R/W
R/W
R/W
R/W
• Port 6 direction register (DDR6)
bit 7
bit 6
D66
bit 5
D65
bit 4
D64
bit 3
D63
bit 2
D62
bit 1
D61
bit 0
D60
Initial value
00000000
Address
D67
B
000016H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 7 direction register (DDR7)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
D71
bit 8
D70
Initial value
Address
D77
R/W
D76
R/W
D75
R/W
D74
R/W
D73
R/W
D72
R/W
B
00000000
000017H
R/W
R/W
• Port 8 direction register (DDR8)
bit 7
bit 6
D86
R/W
bit 5
D85
R/W
bit 4
D84
R/W
bit 3
D83
R/W
bit 2
D82
R/W
bit 1
D81
R/W
bit 0
D80
R/W
Initial value
00000000
Address
D87
B
000018H
R/W
(Continued)
34
MB90520 Series
(Continued)
• Port 9 direction register (DDR9)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
D91
R/W
bit 8
Address
000019H
Initial value
D97
R/W
D96
R/W
D95
R/W
D94
R/W
D93
R/W
D92
R/W
D90
R/W
B
00000000
• Port A direction register (DDRA)
bit 7
DA7
R/W
bit 6
DA6
R/W
bit 5
DA5
R/W
bit 4
DA4
R/W
bit 3
DA3
R/W
bit 2
DA2
R/W
bit 1
DA1
R/W
bit 0
DA0
R/W
Address
Initial value
00000000
00001AH
B
• Port 0 input pull-up resistor setup register (RDR0)
Address
Initial value
00000000
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
00008CH
B
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 1 input pull-up resistor setup register (RDR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Address
Initial value
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
B
00000000
00008DH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 4 input pull-up resistor setup register (RDR4)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
RD47 RD46 RD45 RD44 RD43 RD42 RD41 RD40
00008EH
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Analog input enable register (ADER)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Address
Initial value
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
B
11111111
00001BH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Port 7/COM pin selection register (LCDCMR)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Initial value
—
—
—
—
—
—
—
—
COM3 COM2 COM1 COM0
R/W R/W R/W R/W
B
XXXX0000
00000BH
R/W : Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
35
MB90520 Series
(3) Block Diagram
• Input/output port
PDR (port data register)
PDR read
PDR write
Output latch
Pch
Nch
Pin
DDR (port direction register)
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
• Input pull-up resistor setup register (RDR)
To resource input
PDR (port data register)
Pull-up resistor
About 50 kΩ
(5.0 V)
PDR read
Output latch
PDR write
Pch
Nch
Pch
Pin
DDR (port direction register)
Direction latch
DDR write
Standby control
(SPL=1)
DDR read
RDR latch
RDR write
RDR read
RDR (input pull-up resistor setup register)
Standby control: Stop, timebase timer mode and SPL=1
36
MB90520 Series
• Analog input enable register (ADER)
ADER (analog input enable register)
ADER read
ADER latch
To analog input
ADER write
PDR (port data register)
RMW
(read-modify-write
type instruction)
PDR read
Output latch
PDR write
Pch
Nch
Pin
DDR (port direction register)
Direction latch
DDR write
Standby control
(SPL=1)
DDR read
Standby control: Stop, timebase timer mode and SPL=1
37
MB90520 Series
2. Timebase Timer
The timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the
internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from
four types : 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK.
The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation
stabilization time or the watchdog timer, etc.
(1) Register Configuration
• Timebase timer control register (TBTC)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
1XX00000
Address
0000A9H
Reserved
TBC1
TBOF
R/W
—
TBIE
R/W
TBR
R/W
TBC0
—
B
R/W
R/W
R/W
—
—
R/W: Readable and writable
— : Undefined bits (read value undefined)
(2) Block Diagram
To watchdog timer
To 8/16-bit PPG timer
Timebase timer counter
× 21 × 22 × 23
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
. . . . . .
Divided-by-2
of HCLK
OF
OF
OF
OF
To oscillation stabilization
time selector of clock control block
Power-on reset
Counter
clear circuit
Interval
timer selector
Start stop-mode
CKSCR : MCS = 1→0*1
Set TBOF
Clear TBOF
Timebase timer control register
(TBTC)
Reserved
TBIE TBOF TBR TBC1 TBC0
—
—
Timebase timer
interrupt signal
#12*2
*1: Switch machine clock from oscillation clock to PLL clock
*2: Interrupt number
OF : Overflow
HCLK : Oscillation clock frequency
38
MB90520 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
• Watchdog timer control register (WDTC)
Address
0000A8H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
WT1
W
bit 0
WT0
W
Initial value
B
XXXXXXXX
PONR STBR WRST ERST SRST WTE
R
R
R
R
R
W
R : Read only
W: Write only
X : Indeterminate
(2) Block Diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1 WT0
2
Watchdog timer
CLR and start
Overflow
CLR
Start sleep-mode
Watchdog timer
reset generation
circuit
Counter clear
control circuit
Count clock
selector
2-bit
counter
To internal reset
generation circuit
Start hold status
Start stop-mode
CLR
4
Clear
(Timebase timer counter)
Divided-by-2
of HCLK
× 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
× 28
× 21 × 22
. . .
HCLK : Oscillation clock frequency
39
MB90520 Series
4. 8/16-bit PPG Timer 0, 1
The 8/16-bit PPG timer is a 2-CH re-load timer module for outputting pulse having given frequencies/duty ratios.
The two modules perform the following operation by combining functions.
• 8-bit PPG timer output 2-CH independent output mode
This is a mode for operating independent 2-CH 8-bit PPG timers, in which PG00 and PG10 pins correspond
to outputs from PPG0 and PPG1 respectively.
• 16-bit PPG timer output operation mode
In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer 0 and 1 operating
asa16-bittimer. Becauseoutputsduring16-bitPPGtimeroutput operationmodearereversedbyanunderflow
from PPG1, the same output pulses are output from PG10 and PG11 pins.
• 8 + 8-bit PPG timer output operation mode
In this mode, PPG0 is operated as an 8-bit prescaler register, in which an underflow output of PPG0 is used
as a clock source for PPG1.
A prescaler output of PPG0 is output from PG00 and PG01 pins. PPG output of PPG1 is output from PG10 and
PG11 pins.
• PPG output operation
A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an
external add-on circuit.
40
MB90520 Series
(1) Register Configuration
• PPG0 operating mode control register (PPGC0)
bit 7
bit 6
bit 5
PE00 PIE0 PUF0
R/W R/W R/W
bit 4
bit 3
bit 2
—
bit 1
—
bit 0
Address
000044H
Initial value
Reserved
PEN0
—
B
0X000XX1
R/W
—
—
—
—
• PPG1 operating mode control register (PPGC1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
MD0
R/W
bit 8
Address
000045H
Initial value
PEN1
R/W
—
—
PE10 PIE1 PUF1 MD1
B
Reserved
R/W
0X000001
R/W
R/W
R/W
R/W
• PPG0 output control register (PPGOE0)
Address
Initial value
00000000
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
B
000046H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• PPG1 output control register (PPGOE1)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
B
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
000046H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• PPG0 re-load register H (PRLH0)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Address
Initial value
B
XXXXXXXX
000041H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 9
R/W
bit 8
• PPG1 re-load register H (PRLH1)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
Initial value
B
XXXXXXXX
000043H
R/W
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
• PPG0 re-load register L (PRLL0)
Address
bit 7
Initial value
B
XXXXXXXX
000040H
R/W
R/W
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
• PPG1 re-load register L (PRLL1)
Address
Initial value
bit 7
bit 6
B
XXXXXXXX
000042H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W:Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
41
MB90520 Series
(2) Block Diagram
• Block diagram of 8/16-bit PPG timer 0
Data bus for “H” digits
Data bus for “L” digits
PPG0 re-load
register
PPG0 operating mode
control register (PPGC0)
Reserved
PEN0
—
PE00 PIE0 PUF0
—
—
PRLH0
PRLL0
R
Temporary buffer
(PRLBH0)
Interrupt
request
#19*
S
Q
2
Oprating mode
control signal
Select signal
Re-load selector
L/H selector
PPG1 underflow
PPG0 underflow
(to PPG1)
Count value
Re-load
Clear
Pulse selector
Underflow
Down counter
(PCNT0)
CLK
PPG0
output latch
Pin
Reverse
P36/PG00
PPG output
control circuit
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Count
clock
selector
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
Pin
P37/PG01
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
PPG0, 1 output control register (PPGOE0,1)
*
: Interrupt number
HCLK: Oscillation clock frequency
: Machine clock frequency
φ
42
MB90520 Series
• Block diagram of 8/16-bit PPG timer 1
Data bus for “H” digits
Data bus for “L” digits
PPG1 operating mode
control register (PPGC1)
PPG1 re-load
register
Reserved
PEN1
—
PEI0 PIE1 PUF1 MD1 MD0
PRLH0
PRLL0
Operating
mode
control signal
2
R
Temporary buffer
(PRLBH1)
Interrupt
request
#23*
S
Q
Re-load selector
(L/H selector)
Select signal
Clear
Count value
Re-load
Underflow
PPG1
output latch
Down counter
(PCNT1)
Pin
Reverse
P40/PG10
PPG output control circuit
MD0
CLK
PPG1 underflow
(to PPG0)
Pin
PPG0 underflow
P41/PG11
Timebase timer output (512/HCLK)
Peripheral clock (16/φ)
Peripheral clock (8/φ)
Peripheral clock (4/φ)
Peripheral clock (2/φ)
Peripheral clock (1/φ)
Count clock selector
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
PPG0, 1 Output control register (PPGOE0, 1)
*
: Interrupt number
HCLK: Oscillation clock frequency
: Machine clock frequency
φ
43
MB90520 Series
5. 16-bit Re-load Timer 0, 1 (With an Event Count Function)
The 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal
clocks and an event count mode for counting down by detecting a given edge of the pulse input to the external
bus pin. Either of the two functions can be selectively used.
For this timer, an “underflow” is defined as the timing of transition from the counter value of “0000H” to “FFFFH.”
According to this definition, an underflow occurs after a counter value of [re-load register setting value + 1] .
In operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after
anunderflowortheone-shotmodeforstoppingthecountingoperationafteranunderflowcanbeselectivelyused.
Because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent
I/O service (EI2OS).
The MB90520 series has 2 channels of 16-bit re-load timers.
(1) Register Configuration
• Timer control status register upper digits ch.0, ch.1 (TMCSR0, TMCSR1 : H)
Initial value
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
CSL1 CSL0 MOD2 MOD1
R/W R/W R/W R/W
bit 8
Address
TMCSR0 : 000049H
TMCSR1 : 00004DH
B
XXXX0000
—
—
—
—
—
—
—
—
• Timer control status register lower digits ch.0, ch.1 (TMCSR0, TMCSR1 : L)
Initial value
00000000
bit 7
MOD0 OUTE OUTL RELD INTE
R/W R/W R/W R/W R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
CNTE TRG
R/W R/W
bit 0
Address
TMCSR0 : 000048H
TMCSR1 : 00004CH
B
UF
R/W
• 16-bit timer register upper and lower digits ch.0, ch.1 (TMR0, TMR1)
Address
TMR0 : 00004BH
00004AH
TMR1 : 00004EH
00004FH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
B
B
B
B
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
• 16-bit re-load register upper and lower digits ch.0, ch.1 (TMRLR0, TMRLR1)
Address
TMRLR0 : 00004BH
00004AH
TMRLR1 : 00004EH
00004FH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W : Readable and writable
R
: Read only
W : Write only
X : Indeterminate
— : Undefined bits (read value undefined)
44
MB90520 Series
(2) Block Diagram
Internal data bus
TMRLR0*1
<TMRLR1>
16-bit re-load register
Re-load signal
Re-load
control
circuit
TMR0*1
<TMR1>
16-bit timer register (down counter) UF
CLK
Count clock generation circuit
Gate input
Valid clock
decision
circuit
3
Wait signal
φ
Prescaler
To UART*1
<To 8/10-bit
A/D converter>
Clear
CLK
Output control circuit
Internal
clock
Output signal
generation
circuit
Input
control
circuit
Pin
Clock
selecter
Pin
P71/TO0/OUT5*1
<P73/TO1/OUT7>
EN
Reverse
External
clock
P70/TI0/OUT4*1
Select
signal
3
2
<P72/TI1/OUT6>
Operation
control
circuit
Function select
—
—
—
—
CSL1 CSL0 MOD2MOD1MOD0OUTE OUTLRELD INTE UF CNTE TRG
Timer control status register (TMCSR0)*1
<TMCSR1>
Clear
EI2CS
Interrupt request signal
#38*1, *2
<#40>
*1: The timer has ch.0 and ch.1, and figures bracketed by < > are for ch.1
*2: Interrupt number
φ: Machine clock frequency
45
MB90520 Series
6. 16-bit I/O Timer
The 16-bit I/O timer module consists of two 16-bit free-run timers, two input capture circuits (ICU), and eight
output comparators (OCU). This module allows two independent waveforms to be output on the basis of the
16-bit free-run timer. Input pulse width and external clock periods can, therefore, be measured.
• Block diagram
Internal data bus
16-bit
free-run timer 1, 2
Output compare 0, 1
(OCU)
Input capture 0, 1 Dedicated
Dedicated
bus
(ICU)
bus
46
MB90520 Series
(1) 16-bit Free-run Timer 1, 2
The 16-bit free-run timer consists of a 16-bit up counter, a control register and a communications prescaler
register. The value output from the timer counter is used as basic time (base timer) for input capture (ICU) and
output compare (OCU).
• A counter operation clock can be selected from four internal clocks (φ/4, φ/16, φ/64 and φ/256).
• An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0
and 4. (Compare match requires mode settings.)
• The counter value can be initialized to “0000H” by a reset, software clear or compare match with OCU compare
register 0 and 4.
• Register configuration
• Free-run timer data register 1, 2 (TCDT1, TCDT2)
Address
bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Initial value
TCDT1 : 000057H
000056H
TCDT2 : 000067H
000066H
B
B
B
B
00000000
00000000
00000000
00000000
T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
• Free-run timer control status register 1, 2 (TCCS1, TCCS2)
Address
TCCS1 : 000058H
TCCS2 : 000068H
Initial value
bit 7
Reserved
R/W
bit 6
bit 5
IVFE STOP MODE CLR CLK1 CLK0
R/W R/W R/W R/W R/W R/W
bit 4
bit 3
bit 2
bit 1
bit 0
B
B
00000000
00000000
IVF
R/W
R/W: Readable and writable
• Block diagram
Count value output
to ICO and OCU
Free-run timer data register (TCDT1)*1 <TCDT2>
OF
16-bit counter
CLK
STOP
CLR
Communications
prescaler register
φ
OCU compare register 0
match signal
2
Free-run timer
control status register
(TCCS1) *1 <TCCS2>
Reserved
IVF IVFE STOP MODE CLR CLK1 CLK0
16-bit free-run timer
interrupt request
2
#14*1,
<#28>
*
*1: The timer has ch.1 and ch.2, and figures bracketed by < > are for ch.2.
*2: Interrupt number
φ : Machine clock frequency
OF: Overflow
47
MB90520 Series
(2) Input Capture 0, 1 (ICU)
The input capture (ICU) generates an interrupt request to the CPU while storing the current counter value of
the 16-bit free-run timer to the ICU data register (IPCP) upon input of a trigger edge from the external pin.
There are two sets (two channels) of input capture external pins and ICU data registers, enabling measurements
of a maximum of four events.
• The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling
measurements of a maximum of four events.
• Trigger edge direction can be selected from rising/falling/both edges.
• The input capture can be set to generate an interrupt request at the storage timing of the counter value of the
16-bit free-run timer to the ICU data register (IPCP).
• The input compare conforms to the extended intelligent I/O service (EI2OS).
• The input capture ( ICU) function is suited for measurements of intervals (frequencies) and pulse-widths.
• Register configuration
• ICU data register ch.0 ch.1 (IPCP0, IPCP1)
bit 13
CP13
R
bit 12
CP12
R
bit 11
CP11
R
bit 10
CP10
R
bit 9
CP09
R
bit 8
CP08
R
bit 15
CP15
R
bit 14
CP14
R
Address
IPCP0(upper) : 000051H
IPCP1(upper) : 000053H
Initial value
XXXXXXXXB
bit 6
bit 4
CP04
R
bit 3
CP03
R
bit 7
CP07
R
bit 5
CP05
R
bit 2
bit 1
CP01
R
bit 0
Address
IPCP0(lower) : 000050H
IPCP1(lower) : 000052H
Initial value
CP06
R
CP02
R
CP00
R
XXXXXXXXB
Note: This register holds a 16-bit free-run timer value when the valid edge of the corresponding external pin input waveform
is detected. (This register can be word-accessed, but not programmed.)
• ICU control status register (ICS01)
bit 6
ICP0
R/W
bit 5
ICE1
R/W
bit 7
bit 4
bit 2
EG10
R/W
bit 1
EG01
R/W
bit 3
EG11
R/W
Address
bit 0
EG00
R/W
Initial value
00000000B
ICE0
000054H
ICP1
R/W
R/W
R/W : Readable and writable
R
X
: Read only
: Indeterminate
48
MB90520 Series
• Block diagram
Internal data bus
Latch
signal
P20/IC00
Output latch
Pin
ICU data register (IPCP)
16
Edge detection circuit
Data latch signal
P21/IC01
Pin
IPCP0(lower)
IPCP0(upper)
IPCP1(upper)
2
16-bit free-run
timer 1, 2
P22/IC10
Pin
16
IPCP1(lower)
P23/IC11
Pin
2
ICU control status register (ICS01)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Interrupt request
#31*
Interrupt request
#32*
* : Interrupt number
49
MB90520 Series
(3) Output Compare 0, 1 (OCU)
The output compare (OCU) is two sets of compare units each consisting of an eight-channel OCU compare
register, a comparator and a control register.
An interrupt request can be generated for each channel upon a match detection by performing time-division
comparison between the OCU compare data register setting value and the counter value of the 16-bit free-run
timer.
The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a general-
purpose output port for directly outputting the setting value of the CMOD bit.
• Register Configuration
• OCU control status register ch.01, ch.23, ch.45, ch.67 (OCS01, OCS23, OCS45, OCS67)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address
Initial value
XXX00000
ch.01 : OCS01 (upper) : 0000063H
ch.23 : OCS23 (upper) : 0000065H
ch.45 : OCS45 (upper) : 000002DH
ch.67 : OCS67 (upper) : 000002FH
—
—
—
—
—
—
CMOD OTE1 OTE0 OTD1 OTD0
B
R/W
R/W
R/W
R/W
bit 1
R/W
bit 0
bit 7
ICP1
R/W
bit 6
bit 5
bit 4
ICE0
R/W
bit 3
—
bit 2
—
Address
Initial value
ch.01 : OCS01 (lower) : 000062H
ch.23 : OCS23 (lower) : 000064H
ch.45 : OCS45 (lower) : 00002CH
ch.67 : OCS67 (lower) : 00002EH
ICP0 ICE1
R/W R/W
CST1 CST0
B
0000XX00
—
—
R/W
R/W
• OCU control status register ch.0 to ch.7 (OCS0 to OCS7)
Address
ch.0 : OCP0 (upper) : 00005BH
ch.1 : OCP1 (upper) : 00005DH
ch.2 : OCP2 (upper) : 00005FH
ch.3 : OCP3 (upper) : 000061H
ch.4 : OCP4 (upper) : 00000DH
ch.5 : OCP5 (upper) : 00001DH
ch.6 : OCP6 (upper) : 000035H
ch.7 : OCP7 (upper) : 00006DH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
C08
R/W
Initial value
XXXXXXXX
C15
R/W
C14
R/W
C13
R/W
C12
R/W
C11
R/W
C10
R/W
C09
R/W
B
Address
ch.0 : OCP0 (lower) : 00005AH
ch.1 : OCP1 (lower) : 00005CH
ch.2 : OCP2 (lower) : 00005EH
ch.3 : OCP3 (lower) : 000060H
ch.4 : OCP4 (lower) : 00000CH
ch.5 : OCP5 (lower) : 00001CH
ch.6 : OCP6 (lower) : 000034H
ch.7 : OCP7 (lower) : 00006CH
bit 7
C07
R/W
bit 6
C06
R/W
bit 5
C05
R/W
bit 4
C04
R/W
bit 3
C03
R/W
bit 2
C02
R/W
bit 1
C01
R/W
bit 0
C00
R/W
Initial value
B
XXXXXXXX
R/W : Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
50
MB90520 Series
• Block diagram
• Output compare 0 (OCU)
#36*
Output compare
interrupt request
#35*
OCU control status register ch. 23 (OCS23)
CMOD
OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
CST1 CST0
—
—
—
—
—
2
2
16-bit free-run timer 1
Compare control circuit 3
OCU compare register ch. 3
Compare control circuit 2
OCP3
OCP2
P35/OUT3
Output
control
circuit 3
Pin
OCU compare register ch. 2
Compare control circuit 1
P34/OUT2
Pin
Output
control
circuit 2
P33/OUT1
Pin
Output
control
circuit 1
OCP1
OCP0
OCU compare register ch.1
Compare control circuit 0
P32/OUT0
Pin
Output
control
circuit 0
OCU compare register ch. 0
2
2
CMOD
OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0
CST1 CST0
—
—
—
—
—
OCU control status register ch. 01
(OCS01)
#34*
#33*
Output compare
interrupt request
* : Interrupt number
51
MB90520 Series
• Output compare 1(OCU)
Output compare
interrupt request
#27*
OCU control status register ch. 67 (OCS67)
—
—
—
—
—
CST1 CST0
CMOD OTE1 OTE0 OTD1OTD0 ICP1 ICP0 ICE1 ICE0
2
2
16-bit free-run timer 2
Compare control circuit 7
OCU compare register ch. 7
Compare control circuit 6
OCU compare register ch. 6
Compare control circuit 5
OCU compare register ch. 5
Compare control circuit 4
OCU compare register ch. 4
OCP7
OCP6
OCP5
OCP4
P73/TO1/OUT7
Pin
Output control
circuit 7
P72/TI1/OUT6
Pin
Output control
circuit 6
P71/TO0/OUT5
Pin
Output control
circuit 5
P70/TI0/OUT4
Pin
Output control
circuit 4
2
2
—
—
—
—
—
CST1 CST0
CMOD OTE1 OTE0 OTD1OTD0 ICP1 ICP0 ICE1 ICE0
OCU control status register ch. 45 (OCS45)
Output compare
interrupt request
#25*
* : Interrupt number
52
MB90520 Series
7. 8/16-bit Up/Down Counter/Timer 0, 1
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit
re-load compare registers, and their controllers.
(1) Register Configuration
• Up/down count register 0 (UDCR0)
Address
Initial value
00000000
bit 7
D07
R
bit 6
D06
R
bit 5
D05
R
bit 4
D04
R
bit 3
D03
R
bit 2
D02
R
bit 1
D01
R
bit 0
D00
R
000080H
B
• Up/down count register 1 (UDCR1)
Address
Initial value
00000000
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
D10
R
000081H
D17
R
D16
R
D15
R
D14
R
D13
R
D12
R
D11
R
B
• Re-load compare register 0 (RCR0)
Address
Initial value
00000000
bit 7
bit 6
bit 5
D05
bit 4
D04
bit 3
D03
bit 2
D02
bit 1
D01
bit 0
D00
000082H
D07
D06
B
W
W
W
W
W
W
W
W
• Re-load compare register 1 (RCR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
D10
W
Address
Initial value
00000000
D17
W
D16
W
D15
W
D14
W
D13
W
D12
W
D11
W
000083H
B
B
B
• Counter status register 0, 1 (CSR0, CSR1)
Address
Initial value
00000000
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CSR0 : 000084H
CSR1 : 000088H
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
R/W
R/W
R/W
R/W
R/W
bit 3
R/W
bit 2
R
R
• Counter control register 0, 1 (CCRL0, CCRL1)
Address
Initial value
X0000000
bit 7
bit 6
bit 5
bit 4
bit 1
bit 0
CCRL0 : 000086H
CCRL1 : 00008AH
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Counter control register 0 (CCRH0)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Initial value
00000000
000087H
B
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Counter control register 1 (CCRH1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address
Initial value
X0000000
00008BH
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
R/W R/W R/W R/W R/W R/W R/W
—
—
B
R/W : Readable and writable
: Read only
W : Write only
— : Undefined bits (read value undefined)
R
53
MB90520 Series
(2) Block Diagram
• Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Re-load compare register 0
Re-load
control
circuit
UDCR0
CARRY/
Up/down count register 0
BORROW
(to channel 1)
Counter control
register 0 (CCRL0)
UDCC CGSC
CTUT UCRE RLDE
CGE1 CGE0
—
Compare
control circuit
Counter clear
circuit
P26/ZIN0/INT7
Edge/level
detection
circuit
Pin
Count clock
Counter status
register 0 (CSR0)
φ
Prescaler
UP/down count
clock selector
P24/AIN0
Pin
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
P25/BIN0
Interrupt request
#21*
Interrupt request
#22*
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
Counter control register 0 (CCRH0)
M16E
(to channel 1)
* : Interrupt number
φ: Machine clock frequency
54
MB90520 Series
• Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Re-load compare register 1
Re-load
control
circuit
UDCR1
Up/down count register 1
Counter control
register 1 (CCRL1)
—
CTUT UCRE RLDE UDCC
CGSC
CGE1 CGE0
Compare
control circuit
P52/SCK2/ZIN1
Pin
Counter clear
circuit
Edge/level
detection
circuit
CARRY/BORRW
(from channel 0)
Count clock
Counter status
φ
(CSR1)
register 1
Prescaler
P50/SIN2/AIN1
UP/down count
clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Pin
Pin
P51/SOT2/BIN1
Interrupt request
#29*
M16E
(from channel 1)
Interrupt request
#30*
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
—
Counter control register 1 (CCRH1)
* : Interrupt number
φ: Machine clock frequency
55
MB90520 Series
8. Extended I/O Serial Interface 0, 1
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel
configuration.
For data transfer, you can select LSB first/MSB first.
(1) Register Configuration
• Serial mode control upper status register 0, 1 (SMCSH0, SMCSH1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address
SMCSH0 : 000025H
SMCSH1 : 000029H
Initial value
00000010
SMD2 SMD1 SMD0 SIE
R/W R/W R/W R/W
SIR
BUSY STOP STRT
B
R/W
R
R/W
R/W
bit 0
• Serial mode control lower status register 0, 1 (SMCSL0, SMCSL1)
Address
SMCSL0 : 000024H
SMCSL1 : 000028H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Initial value
XXXX0000
MODE BDS
SOE SCOE
—
—
—
—
B
R/W
R/W
R/W
R/W
—
—
—
—
• Serial data register 0, 1 (SDR0, SDR1)
Address
SDR0 : 000026H
SDR1 : 00002AH
bit 7
D7
bit 6
D6
bit 5
D5
bit 4
D4
bit 3
D3
bit 2
D2
bit 1
D1
bit 0
D0
Initial value
XXXXXXXX
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
R
X
: Read only
: Indeterminate
— : Undefined bits (read value undefined)
56
MB90520 Series
(2) Block Diagram
Internal data bus
D7 to D0 (LSB first)
(MSB first) D0 to D7
Transfer direction selection
Pin
Read
Write
Serial data register
(SDR)
P45/SIN1
Pin
Pin
P50/SIN2/AIN1
P46/SOT1
Pin
P51/SOT2/BIN1
Pin
P47/SCK1
Control circuit
Shift clock counter
Pin
P52/SCK2/ZIN1
Internal clock
3
2
1
0
MODE
SCOE
BDS SOE
SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT
—
—
—
—
Serial mode control
status register
(SMCSH,L)
Interrupt request
#15 (SMCS0)*
#17 (SMCS1)*
*: Interrupt number
57
MB90520 Series
9. UART (SCI)
UART (SCI) is a general-purpose serial data communication interface for performing synchronous or
asynchronous communication (start-stop synchronization system).
• Data buffer: Full-duplex double buffer
• Transfer mode:Clock synchronized (with start and stop bit)
Clock asynchronized (start-stop synchronization system)
• Baud rate:Embedded dedicated baud rate generator
External clock input possible
Internal clock (a clock supplied from 16-bit re-load timer 0 can be used.)
Internal machine clock
For 6 MHz, 8 MHz, 10 MHz,
12 MHz and 16 MHz
• Data length:8 bit (without a parity bit)
Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps
CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps
}
7 bit (with a parity bit)
• Signal format: NRZ (Non Return to Zero) system
• Reception error detection: Framing error
Overrun error
Parity error (multi-processor mode is supported, enabling setup of any baud rate
by an external clock.)
• Interrupt request: Receive interrupt (reception complete, receive error detection)
Transmit interrupt (transmisson complete)
Transmit/receive conforms to extended intelligent I/O service (EI2OS)
58
MB90520 Series
(1) Register Configuration
• Serial control register (SCR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address
Initial value
TXE
PEN
P
SBL
R/W
CL
A/D
REC
W
RXE
R/W
B
000021H
00000100
R/W
R/W
R/W
R/W
R/W
• Serial mode register (SMR)
bit 7
bit 6
MD0
R/W
bit 5
CS2
R/W
bit 4
CS1
R/W
bit 3
CS0
R/W
bit 2
Reserved
R/W
bit 1
bit 0
Address
Initial value
MD1
R/W
SCKE SOE
B
000020H
00000000
R/W
R/W
• Serial status register (SSR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
TIE
Address
000023H
Initial value
PE
R
ORE
R
FRE RDRF TRDE
—
—
RIE
B
00001X00
R
R
R
R/W
R/W
• Serial input data register (SIDR)
bit 7
bit 6
D6
bit 5
D5
bit 4
D4
bit 3
D3
bit 2
D2
bit 1
D1
bit 0
D0
Address
Initial value
D7
B
XXXXXXXX
000022H
R
R
R
R
R
R
R
R
• Serial output data register (SODR)
bit 7
bit 6
bit 5
D5
bit 4
D4
bit 3
D3
bit 2
D2
bit 1
D1
bit 0
D0
Address
Initial value
D7
D6
W
B
000022H
XXXXXXXX
W
W
W
W
W
W
W
• Communications prescaler control register (CDCR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8
Address
Initial value
MD
—
—
—
DIV3 DIV2 DIV1 DIV0
B
0XXX1111
000027H
R/W
—
—
—
R/W R/W R/W R/W
R/W:Readable and writable
R : Read only
W : Write only
X : Indeterminate
— : Undefined bits (read value undefined)
59
MB90520 Series
(2) Block Diagram
Control bus
Receive
interrupt signal
#37*
Dedicated baud
rate generator
Transmit
clock
Transmit
interrupt signal
#39*
Clock
16-bit re-load timer 0
selector
Receive
clock
Receive
control circuit
External clock
Transmit
control circuit
Pin
P42/SCK0
Start bit
detection circuit
Transmit start
circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
P43/SOT0
Shift register for
transmission
Shift register for
reception
Pin
P42/SIN0
Start transmission
SIDR
SODR
Reception
complete
Receive condition
decision circuit
To EI2OS reception
error generation
signal (to CPU)
Internal data bus
PE
ORE
FRE
RDRF
TDRE
PEN
P
SBL
CL
A/D
REC
RXE
TXE
MD1
MD0
CS2
CS1
CS0
SMR
register
SCR
register
SSR
register
RIE
TIE
SCKE
SOE
* : Interrupt number
60
MB90520 Series
10. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*
for transmission to the F2MC-16LX CPU. It is used to activate the intelligent I/O service or interrupt processing.
As with request levels, two types of “H” and “L” can be selected for the intelligent I/O service. Rising and falling
edges as well as “H” and “L” can be selected for an external interrupt request.
* : The external peripheral circuit is connected outside the MB90520 series device.
(1) Register Configuration
• DTP/interrupt factor register (EIRR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
ER1
bit 8
ER0
Address
000031H
Initial value
ER7
R/W
ER6
R/W
ER5
R/W
ER4
R/W
ER3
R/W
ER2
R/W
B
XXXXXXXX
R/W
R/W
• DTP/interrupt enable register (ENIR)
bit 7
bit 6
bit 5
EN5
bit 4
EN4
bit 3
EN3
bit 2
EN2
bit 1
EN1
bit 0
EN0
Address
000030H
Initial value
EN7
EN6
B
00000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Request level setting register (ELVR)
bit 7
LB3
R/W
bit 6
LA3
R/W
bit 5
LB2
R/W
bit 4
LA2
R/W
bit 3
LB1
R/W
bit 2
LA1
R/W
bit 1
LB0
R/W
bit 0
LA0
R/W
Address
Initial value
ELVR (lower) : 000032H
B
00000000
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
LB4
bit 8
LA4
Address
Initial value
LB7
R/W
LA7
R/W
LB6
R/W
LA6
R/W
LB5
R/W
LA5
R/W
B
00000000
ELVR (upper) : 000033H
R/W
R/W
R/W: Readable and writable
X : Indeterminate
61
MB90520 Series
(2) Block Diagram
Internal data bus
62
MB90520 Series
11. Wake-up Interrupt
Wake-up interrupts transmit interrupt request (“L” level) generated by peripheral equipment located between
external peripheral devices and the F2MC-16LX CPU to the CPU and invoke interrupt processing.
The interrupt does not conform to the exterded intelligent I/O service (EI2OS).
(1) Register Configuration
• Wake-up interrupt flag register (EIFR)
Address
00000FH
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
—
bit 8
WIF
Initial value
—
—
—
—
—
—
—
—
—
B
XXXXXXX0
—
—
—
—
R/W
• Wake-up interrupt enable register (EICR)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
EN1
bit 8
EN0
Initial value
00001FH
EN7
W
EN6
W
EN5
W
EN4
W
EN3
W
EN2
W
B
00000000
W
W
R/W: Readable and writable
W : Write only
— : Undefined bits (read value undefined)
(2) Block Diagram
Internal data bus
Wake-up interrupt
enable register (EICR)
Wake-up interrupt flag
register (EIFR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
—
—
—
—
—
—
—
WIF
Interrupt request detection circuit
P10/WI0 Pin
P11/WI1 Pin
P12/WI2 Pin
Wake-up interrupt
request
#16*
P13/WI3 Pin
P14/WI4 Pin
P15/WI5 Pin
P16/WI6 Pin
P17/WI7 Pin
*: Interrupt number
63
MB90520 Series
12. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks. By using this module,
hardware interrupt requests to the CPU can be generated and cancelled using software.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
• Delayed interrupt factor generation/cancellation register (DIRR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
—
bit 8
R0
Address
Initial value
—
—
—
—
—
—
—
—
—
—
—
—
B
00009FH
XXXXXXX0
—
R/W
Note: Upon a reset, an interrupt is cancelled.
R/W: Readable and writable
— : Undefined bits (read value undefined)
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The undefined bit area can be programmed with either “0” or
“1.” For future extension, however, it is recommended that bit set and clear instructions be used to access this
register.
(2) Block Diagram
Internal data bus
—
—
—
—
—
—
—
R0
S factor
R latch
Interrupt request signal
#42*
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt number
64
MB90520 Series
13. 8/10-bit A/D Converter
The 8/10-bit A/D converter converts analog voltage input to the analog input pins (input voltage) to digital values
(A/D conversion) and has the following features:
• Minimum conversion time: minimum 15.0 µs (at machine clock frequency of 16 MHz, including sampling time)
• Minimum sampling period: 4 µs/8 µs (at machine clock frequency of 16 MHz)
• Compare time: 99/176 machine cycles per channel
(99 machine cycles are used for a machine clock frequency below 10 MHz.)
• Conversion method: RC successive approximation method with a sample and hold circuit
• 8/10-bit resolution
• Analog input pins: Selectable from eight channels by software
Single conversion mode: Selects and converts one channel.
Scan conversion mode: Converts two or more successive channels. Up to eight channels can be programmed.
Continuous conversion mode: Repeatedly converts specified channels.
Stop conversion mode: Stops conversion after completing a conversion for one channel and wait for the
next activation (conversion can be started synchronously).
• Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the
end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling
efficient continuous processing.
• When interrupts are enabled, there is no loss of data even in continuous operations because the conversion
data protection function is in effect.
• Starting factors for conversion: Selectable from software activation, external trigger (falling edge) and timer
(rising edge).
65
MB90520 Series
(1) Register Configuration
• A/D control status register upper digits (ADCS2)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Reserved
R/W
Initial value
B
000037H
BUSY INT
R/W R/W
INTE PAUS STS1 STS0 STRT
00000000
R/W
R/W
R/W
R/W
W
• A/D control status register lower digits (ADCS1)
Address
bit 7
MD1
R/W
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
000036H
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
B
00000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• A/D data register upper digits (ADCR2)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
(D9)
R
bit 8
(D8)
R
Address
000039H
Initial value
B
00001XXX
SELB ST1
ST0
W
CT1
W
CT0
W
—
—
W
W
• A/D data register lower digits (ADCR1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
Initial value
B
XXXXXXXX
000038H
D7
R
D6
R
D5
R
D4
R
D3
R
D2
R
D1
R
D0
R
R/W: Readable and writable
R : Read only
W : Write only
X : Indeterminate
— : Undefined bits (read value undefined)
66
MB90520 Series
(2) Block Diagram
A/D control status
register (ADCS)
Interrupt request #11*
Reserved
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
STRT
BUSY INT INTE
STS1 STS0
PAUS
6
2
P27/ADTG
P73/TO1/OUT7
Clock selector
Decoder
φ
Comparator
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
Sample hold
circuit
Control circuit
Analog
channel
selector
AVRH, AVRL
AVCC
8-bit D/A converter
AVSS
A/D data register
SELB
ST1 ST0 CT1 CT0
—
(D9) (D8) D7 D6 D5 D4 D3 D2 D1 D0
(ADCR)
TO : 16-bit re-load timer channel 1 output
: Interrupt number
φ : Machine clock frequency
*
67
MB90520 Series
14. 8-bit D/A Converter
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two
channels, each of which can be controlled in terms of output by the D/A control register.
(1) Register Configuration
• D/A converter data register ch.0 (DADR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
Initial value
00003AH
B
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
XXXXXXXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 9
R/W
bit 8
• D/A converter data register ch.1 (DADR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
Address
Initial value
00003BH
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
B
XXXXXXXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• D/A control register 0 (DACR0)
Address
00003CH
bit 7
—
bit 6
—
bit 5
—
bit 4
—
bit 3
—
bit 2
—
bit 1
—
bit 0
Initial value
B
XXXXXXX0
DAE0
—
—
—
—
—
—
—
R/W
• D/A control register 1 (DACR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Address
Initial value
B
XXXXXXX0
00003DH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DAE1
R/W
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
68
MB90520 Series
• Block Diagram
Internal data bus
D/A converter data register ch.1 (DADR1)
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
D/A converter data register ch.0 (DADR0)
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
D/A converter 1
D/A converter 0
DVRH
DVRL
DA17
DA07
Pin
P54/DA1
Pin
2R
2R
P53/DA0
R
R
R
R
R
R
DA16
DA06
DA05
DA04
DA03
DA02
DA01
DA00
2R
2R
2R
2R
2R
R
DA15
2R
R
DA14
2R
R
DA13
2R
R
DA12
2R
2R
2R
2R
R
R
R
DA11
2R
R
DA10
2R
2R
2R
DVSS
DVSS
Standby control
Standby control
D/A control register 1 (DACR1)
D/A control register 0 (DACR0)
DAE1
DAE0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Internal data bus
69
MB90520 Series
15. Clock Timer
The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt.
(1) Register Configuration
• Clock timer control register (WTC)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
0000AAH
Initial value
B
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
R/W R/W R/W R/W R/W R/W R/W
1X001000
R
R/W: Readable and writable
R : Read only
X : Indeterminate
(2) Block Diagram
To watchdog timer
Timer counter
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
LCLK
OF
OF
OF
OF
OF
OF
OF
Power-on reset
Counter
Shift to a hardware stand-by
To sub-clock
stabilization time controller
clear circuit
Shift to stop mode
Interval
timer selector
Clock timer interrupt request
#22*
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clock timer control register (WTC)
*
: Interrupt number
OF : Overflow
LCLK : Sub-clock frequency
70
MB90520 Series
16.LCD Controller/Driver
The LCD (liquid crystal display) controller/driver, which contains a 16-byte display data memory, controls LCD
indication using four common output pins and 32 segment output pins. It can select three types of duty output
and directly drive the LCD panel.
(1) Register Configuration
• LCDC control register 0 (LCR0)
bit 7
CSS LCEN VSEL
R/W R/W R/W
bit 6
bit 5
bit 4
BK
bit 3
MS1
R/W
bit 2
MS0
R/W
bit 1
FP1
R/W
bit 0
FP0
R/W
Address
Initial value
00006AH
B
00010000
R/W
• LCDC control register 1 (LCR1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
bit 8
Address
Initial value
Reserve
d
SEG5 SEG4 Reserved SEG3 SEG2 SEG1 SEG0
00006BH
B
00000000
R/W
R/W R/W R/W
R/W
R/W
R/W
bit 9
R/W
bit 8
• Port 7/COM pin selection register (LCDCMR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
Address
00000BH
Initial value
B
XXXX0000
—
—
—
—
—
—
—
—
COM3 COM2 COM1 COM0
R/W
R/W
R/W
R/W
• RAM for LCD indication (VRAM)
Address
bit 7
b7
bit 6
b6
bit 5
b5
bit 4
b4
bit 3
b3
bit 2
b2
bit 1
b1
bit 0
b0
Initial value
000070H
to
00007FH
B
XXXXXXXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
71
MB90520 Series
(2) Block Diagram
Pin
Pin
Pin
Pin
V0
V1
V2
V3
LCDC control
register 0
(LCR0)
Split resistor
LCEN VSEL
CSS
BK MS1 MS0 FP1 FP0
2
Pin
Pin
Pin
Pin
Pin
P74/COM0
P75/COM1
P76/COM2
P77/COM3
SEG00
Timing
controller
HCLK
LCLK
Prescaler
Indication RAM
(16 bytes)
32
Pin
Pin
SEG01
SEG02
6
SEG3
Reserved
SEG2
SEG5 SEG4 Reserved
SEG1 SEG0
LCDC control register 1
(LCR1)
Pin
P95/SEG29
Controller section
Pin
Pin
P96/SEG30
P97/SEG31
HCLK: Oscillation frequency
LCLK : Sub-clock frequency
72
MB90520 Series
17. Communications Prescaler Register
This register controls machine clock division.
Output from the communications prescaler register is used for UART (SCI) and extended I/O serial interface.
The communications prescaler register is so designed that a constant baud rate may be acquired for various
machine clocks.
(1) Register Configuration
• Communications prescaler control register (CDCR)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
DIV3 DIV2 DIV1 DIV0
R/W R/W R/W R/W
bit 8
Address
000027H
Initial value
MD
—
—
—
—
—
—
B
0XXX1111
R/W
R/W: Readable and writable
— : Undefined bits (read value undefined)
73
MB90520 Series
18. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1,” the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
• Program address detection register 0 to 2 (PADR0)
Address bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
B
XXXXXXXX
PADR0 (High order address) : 001FF2H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 9
R/W
bit 8
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
Initial value
B
XXXXXXXX
PADR0 (Middle order address) : 001FF1H
R/W
bit 7
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
Address
Initial value
B
XXXXXXXX
PADR0 (Low order address) : 001FF0H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Program address detection register 3 to 5 (PADR1)
Address bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
B
XXXXXXXX
PADR1 (High order address) : 001FF5H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 9
R/W
bit 8
Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
Initial value
B
XXXXXXXX
PADR1 (Middle order address) : 001FF4H
R/W
bit 7
R/W
bit 6
R/W
bit 5
R/W
bit 4
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
Address
Initial value
B
XXXXXXXX
PADR1 (Low order address) : 001FF3H
R/W
R/W
R/W
R/W
R/W
bit 3
R/W
bit 2
R/W
bit 1
R/W
bit 0
• Program address detection control status register (PACSR)
Address
bit 7
Reserved
R/W
bit 6
bit 5
bit 4
Initial value
B
00000000
Reserved Reserved
Reserved AD1E Reserved AD0E Reserved
00009EH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable and writable
X : Indeterminate
— : Undefined bits (read value undefined)
74
MB90520 Series
(2) Block Diagram
Address latch
INT9
instruction
Address detection register
F2MC-16LX
CPU core
Enable bit
75
MB90520 Series
19. ROM Mirroring Function Selection Module
The ROM mirror function select module enables the ROM data from the FF bank to be read also from the 00 bank.
(1) Register Configuration
• ROM mirroring function selection register (ROMM)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
—
bit 8
MI
Address
00006FH
Initial value
—
—
—
—
—
—
—
—
—
—
—
—
B
XXXXXXX1
—
W
W : Write only
— : Undefined bits (read value undefined)
Note: Do not access this register during operation at addresses 004000H to 00FFFFH.
(2) Block Diagram
ROM mirroring function selection
register (ROMM)
Address area
Address
FF bank
00 bank
Data
ROM
76
MB90520 Series
20. Low-power Consumption (Stand-by) Mode
The F2MC-16LX has the following CPU operating modes configured by selection of an operating clock and clock
operation control.
• Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock.
Main clock mode: A mode in which the CPU and peripheral equipment are driven by drivided-by-2 of the
oscillation clock. The PLL multiplication circuits stops in the main clock mode.
• Sub-clock mode
The sub-clock mode causes the CPU to operate only with the sub-clock. This mode uses the sub-clock
frequency divided by four as the operating clock frequency while stopping the main clock and PLL clock.
• CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high speed.
• Hardware stand-by mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU
by the low-power consumption control circuit (sleep mode), stopping clock supplies to the CPU and peripheral
functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware stand-by mode). Of
these modes, modes other than the PLL clock mode are low power consumption modes.
(1) Register Configuration
• Clock select register (CKSCR)
Address
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10
bit 9
CS1
R/W
bit 8
CS0
R/W
Initial value
0000A1H
SCM MCM WS1 WS0
R/W R/W
SCS
R/W
MCS
R/W
B
11111100
R
R
• Low-power consumption mode control register (LPMCR)
Address
bit 7
STP
W
bit 6
bit 5
SPL
R/W
bit 4
RST
W
bit 3
TMD
W
bit 2
CG1
R/W
bit 1
CG0
R/W
bit 0
SSR
R/W
Initial value
0000A0H
SLP
B
00011000
W
R/W: Readable and writable
R : Read only
W : Write only
77
MB90520 Series
(2) Block Diagram
Standby control circuit
Low-power consumption mode control register (LPMCR)
CPU intermittent
operation cycle
selector
CPU clock
control circuit
CPU operation
clock
STP SLP SPL RST TMD CG1 CG0 SSR
2
Clock mode
Sleep signal
Stop signal
Peripheral function
operation clock
Peripheral clock
control circuit
Hardware
standby
S
R
Q
Q
S
R
Q
Q
Machine clock
S
R
S
R
Reset
Interrupt
Clock selector
Oscillation
stabilization
time selector
2
2
PLL multiplication
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0 Pin
X1 Pin
Divided-
by-2
Divided-
by-2048
Divided-
by-4
Divided-
by-4
Divided-
by-8
Oscillation
clock
Main
clock
Clock oscillator
Timebase timer
To watchdog timer
X0A Pin
X1A Pin
Divided-
by-1024
Divided-
by-8
Divided-
by-2
Divided-
by-2
Sub-clock
Sub-clock oscillator
Clock timer
S : Set
R : Reset
Q : Output
78
MB90520 Series
21.Clock Monitor Function
The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from
the CKOT pin.
(1) Register configuration
• Clock output enable register
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Address
00003EH
Initial value
XXXXXXX1B
CKEN FRQ2 FRQ1 FRQ0
R/W
R/W
R/W
R/W
R/W:Readable and writable
—:Undefined bits (read value undefined)
(2) Block Diagram
CKEN
FQR2
FQR1
FQR0
φ
Divider
circuit
P31/CKOT
φ : Machine clock frequency
79
MB90520 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Rating
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
VSS – 0.3
VSS – 0.3
VSS + 6.0
VSS + 6.0
V
V
AVCC
*1
*1
Power supply voltage
AVRH,
AVRL
VSS – 0.3
VSS + 6.0
V
DVCC
VI
VSS – 0.3
VSS – 0.3
VSS – 0.3
VSS + 6.0
VCC + 6.0
VCC + 6.0
15
V
V
*2
*3
*3
*4
*5
Input voltage
Output voltage
VO
V
“L” level maximum output current
“L” level average output current
IOL
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
IOLAV
4
“L” level total maximum output current ΣIOL
100
“L” level total average output current
“H” level maximum output current
“H” level average output current
ΣIOLAV
50
*6
*4
*5
IOH
–15
IOHAV
–4
“H” level total maximum output current ΣIOH
–100
–50
“H” level total average output current
Power consumption
ΣIOHAV
*6
PD
300
Operating temperature
TA
–40
–55
+85
Storage temperature
Tstg
+150
°C
*1: AVCC, AVRH, AVRL, and DVCC shall never exceed VCC. AVRL shall never exceed AVRH.
*2: VCC ≥ AVCC ≥ DVCC ≥ 3.0V
*3: VI and VO shall never exceed VCC + 0.3 V.
*4: The maximum output current is a peak value for a corresponding pin.
*5: Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*6: Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
80
MB90520 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
VCC
3.0
5.5
V
Normal operation (MB90522, MB90523)
Normal operation (MB90F523)
Guaranteed frequency = 10 MHz
at 4.0 V to 4.5V
VCC
4.0
3.0
5.5
5.5
V
V
Power supply voltage
Smoothing capacitor
Retains status at the time operation
stops
VCC
CS
0.1
1.0
µF
°C
*
Operating temperature TA
–40
+85
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be
connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
• C pin diagram
C
CS
81
MB90520 Series
3. DC Characteristics
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol
Pin name
Condition
Unit Remarks
Min.
Typ.
Max.
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7,
“H” level
VIHS
0.8 VCC
—
VCC + 0.3
VCC + 0.3
0.2 VCC
V
V
V
input
voltage
VCC = 3.0 V to 5.5 V
(MB90523)
VIHM
MD0 to MD2
VCC – 0.3
VSS – 0.3
—
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7,
VCC = 4.0 V to 5.5 V
(MB90F523)
“L” level
VILS
—
input
voltage
VILM
MD0 to MD2
VSS – 0.3
VCC – 0.5
—
—
VSS + 0.3
—
V
V
“H” level
output
voltage
Other than P90 VCC = 4.5 V,
to P97
VOH
IOH = –2.0 mA
“L” level
output
voltage
VCC = 4.5 V,
IOL = 2.0 mA
VOL
All output pins
—
—
–5
—
0.1
—
0.4
5
V
Open-drain
output
leakage
current
Output pin
P90 to P97
Ileak
—
µA
µA
kΩ
Input
leakage
current
Other than P90 VCC = 5.5 V,
IIL
5
to P97
VSS < VI < VCC
P00 to P07, P10
to P17, P40 to
P47, RST, MD0,
MD1
Pull-up
resistance
RUP
—
—
15
15
30
30
100
100
Pull-down
resistance
RDOWN
MD2
kΩ
(Continued)
82
MB90520 Series
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol
Pin name
Condition
Unit Remarks
Min.
Typ.
Max.
Internal operation
at 16 MHz
VCC at 5.0 V
MB90522,
mA
ICC
ICC
ICC
VCC
VCC
VCC
—
30
40
MB90523
—
—
85
35
130
45
mA MB90F523
Normal operation
Internal operation
at 16 MHz
MB90522,
mA
MB90523
VCC at 5.0 V
A/D converter
operation
ICC
ICC
ICC
VCC
VCC
VCC
—
—
—
90
40
95
140
50
mA MB90F523
Internal operation
at 16 MHz
VCC at 5.0 V
D/A converter
operation
MB90522,
mA
MB90523
145
mA MB90F523
mA MB90F523
When data is
written or erased
in flash mode
ICC
VCC
—
95
140
Internal operation
at 16 MHz
VCC at 5.0 V
MB90522,
mA
ICCS
VCC
VCC
VCC
—
—
—
7
12
30
MB90523
Power
supply
current*
ICCS
ICCL
25
0.1
mA MB90F523
In sleep mode
Internal operation
at 8 kHz
MB90522,
mA
1.0
MB90523
VCC at 5.0 V
TA = +25°C
Subsystem
operation
ICCL
VCC
—
4
7
mA MB90F523
Internal operation
at 8 kHz
VCC at 5.0 V
TA = +25°C
In subsleep mode
MB90522,
µA
ICCLS
ICCLS
ICCT
VCC
VCC
VCC
VCC
—
—
—
—
30
0.1
15
30
50
1
MB90523
mA MB90F523
Internal operation
at 8 kHz
VCC at 5.0 V
TA = +25°C
MB90522,
µA
30
50
MB90523
ICCT
µA MB90F523
In clock mode
MB90522,
µA
ICCH
ICCH
CIN
VCC
VCC
—
—
—
5
20
10
80
TA = +25°C
In stop mode
MB90523
0.1
10
µA MB90F523
pF
Input
capacitance
Other than AVCC,
AVSS, C, VCC, VSS
—
(Continued)
83
MB90520 Series
(Continued)
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter Symbol
Pin name
V0 to V1,
V1 to V2,
V2 to V3
Condition
Unit Remarks
Min.
Typ.
Max.
LCD split
RLCD
—
50
100
200
kΩ
resistor
Output
impedance
for COM0
to COM3
RVCOM
COM0 to COM3
SEG00 to SEG31
—
—
2.5
kΩ
V1 to V3 = 5.0 V
Output
impedance
RVSEG
—
—
—
—
15
kΩ
µA
for SEG00
to SEG31
V0 to V3,
COM1 to COM3,
SEG00 to SEG31
LCDC leak
ILCDC
—
±5
current
* : The current value is preliminary and may be subject to change for enhanced characteristics without previous
notice.The power supply current is measured with an external clock.
84
MB90520 Series
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
4 tCP*
4 tCP*
Max.
—
Reset input time
tRSTL
RST
HST
ns
ns
—
Hardware standby input time tHSTL
—
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
• Measurement conditions for AC ratings
Pin
CL
CL is a load capacitance connected to a pin under test.
CL of 80 pF must be connected to address data bus (AD15 to AD00).
85
MB90520 Series
(2) Specification for Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
ms
Remarks
Parameter
Min.
Max.
Power supply rising time
Power supply cut-off time
tR
VCC
VCC
0.05
30
*
—
Due to repeated
operations
tOFF
4
—
ms
* : VCC must be kept lower than 0.2 V before power-on.
Notes: • The above ratings are values for causing a power-on reset.
• There are internal registers which can be initialized only by a power-on reset.
Apply power according to this rating to ensure initialization of the registers.
tR
2.7 V
0.2 V
VCC
0.2 V
tOFF
0.2 V
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to raise the voltage
smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage when the PLL clock is not in use. If the voltage drops 1 V or less per
second, however, the PLL clock may be used.
VCC
It is recommended to keep the rising
speed of the supply voltage at 50 mV/ms
or slower.
0.2 V
VSS
86
MB90520 Series
(3) Clock Timings
Parameter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name Condition
Unit
Remarks
Min.
Typ. Max.
FC
X0, X1
X0, X1
—
3
—
16
MHz
4.0 V to
4.5 V
Clock frequency
Clock cycle time
FC
3
—
10
MHz MB90F523
FCL
X0A, X1A
X0, X1
—
32.768
—
—
kHz
ns
—
tHCYL
62.5
333
4.0 V to
4.5 V
tHCYL
tLCYL
X0, X1
100
—
—
333
—
ns MB90F523
X0A, X1A
—
30.5
µs
Recommended
ns duty ratio of
30% to 70%
PWH,
PWL
X0
—
10
—
—
Input clock pulse width
PWLH,
PWLL
X0A
X0, X0A
—
—
—
—
—
—
15.2
—
—
5
µs
tCR,
tCF
External clock
operation
Input clock rising/falling time
ns
When the main
MHz
fCP
fCP
fLCP
tCP
1.5
1.5
—
16
10
clock is used
4.0 V to
4.5 V
When the main
MHz
Internal operating clock
frequency
—
—
clock is used
When the
kHz subclock is
used
—
—
—
8.192
—
When the main
ns
—
—
—
62.5
100
—
—
333
333
clock is used
4.0 V to
4.5 V
When the main
ns
Internal operating clock cycle tCP
time
clock is used
When the
µs subclock is
used
tLCP
—
—
—
—
—
—
122.1
—
—
5
Frequency fluctuation rate
locked
∆f
%
*
* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+ α
| α |
fO
∆f =
× 100 (%)
Center frequency fO
– α
–
The PLL frequency deviation changes periodically from the preset frequency “(about CLK × (1CYC to 50 CYC),”
thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with
long intervals).
87
MB90520 Series
• X0, X1 clock timing
tHCYL
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
X0
PWH
PWL
tCF
tCR
• X0A, X1A clock timing
tLCYL
0.8 VCC
0.2 VCC
0.8 VCC
0.8 VCC
0.2 VCC
X0A
PWLH
PWLL
tCF
tCR
• PLL operation guarantee range
Relationship between internal operating clock
frequency and power supply voltage
(V)
MB90F523 operation guarantee range
5.5
4.5
4.0
PLL operation
MB90V520 operation guarantee range
guarantee range
3.3
3.0
MB90522,MB90523 operation guarantee range
1
3
8
10
12
16
(MHz)
Internal clock fCP
Relationship between oscillating frequency and internal
operating clock frequency
(MHz)
16
Multiplied Multiplied Multiplied
Multiplied
-by-1
-by-4
-by-3
-by-2
12
8
Not multiplied
4
3
2
1
2
3
4
6
8
12
16 (MHz)
Oscillation clock FC
88
MB90520 Series
The AC ratings are measured for the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hystheresis input pin
0.8 VCC
Hystheresis input pin
2.4 VCC
0.2 VCC
0.8 VCC
Pins other than hystheresis input/MD input
0.7 VCC
0.3 VCC
89
MB90520 Series
(4) Recommended Resonator Manufacturers
• Sample application of ceramic resonator
X0
X1
R
*
XTAL
C1
C2
• Mask ROM product (MB90522, MB90523)
Frequency
Resonator
manufacturer
Resonator
C1 (pF)
C2 (pF)
R
(MHz)
CSA2.00MG040
CSA4.00MG040
CSA8.00MTZ
2.00
100
100
30
100
100
30
Not required
Not required
Not required
Not required
Not required
4.00
Murata
Mfg. Co., Ltd.
8.00
CSA16.00MXZ040
CSA32.00MXZ040
16.00
32.00
15
5
15
5
3.52
to
6.96
CCR3.52MC3 to
CCR6.96MC3
Built-in
Built-in
Built-in
Built-in
Built-in
Built-in
Not required
Not required
Not required
7.00
to
12.00
CCR7.0MC5 to
CCR12.0MC5
TDK Corporation
20.00
to
32.00
CCR20.0MSC6 to
CCR32.0MSC6
(Continued)
90
MB90520 Series
(Continued)
• Flash ROM product (MB90F523)
Resonator
manufacturer
Frequency
(MHz)
Resonator
C1 (pF)
C2 (pF)
R
CSA2.00MG040
CSA4.00MG040
CSA8.00MTZ
2.00
4.00
100
100
30
15
100
100
30
15
Not required
Not required
Not required
Not required
Not required
Murata
Mfg. Co., Ltd.
8.00
CSA16.00MXZ040
CSA32.00MXZ040
16.00
32.00
5
5
3.52
to
6.96
CCR3.52MC3 to
CCR6.96MC3
Built-in
Built-in
Built-in
Built-in
Built-in
Built-in
Not required
Not required
Not required
7.0
to
12.0
CCR7.0MC5 to
CCR12.0MC5
TDK Corporation
20.0
to
32.0
CCR20.0MSC6 to
CCR32.0MSC6
Inquiry:Murata Mfg. Co., Ltd..
• Murata Electronics North America, Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.): TEL 65-758-4233
TDK Corporation
• TDK Corporation of America
Chicago Regional Office: TEL 1-708-803-6100
• TDK Electronics Europe GmbH
Components Division: TEL 49-2102-9450
• TDK Singapore (PTE) Ltd.: TEL 65-273-5022
• TDK Hong Kong Co., Ltd.: TEL 852-736-2238
• Korea Branch, TDK Corporation: TEL 82-2-554-6636
91
MB90520 Series
(5) UART (SCI) Timing
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
tSCYC
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
Serial clock cycle time
SCK0 to SCK2
8 tCP*
—
ns
ns
SCK ↓ → SOT delay
SCK0 to SCK2,
SOT0 to SOT2
Internal shift clock
mode
CL = 80 pF
+ 1 TTL for an
output pin
tSLOV
– 80
100
60
80
—
time
SCK0 to SCK2,
SIN0 to SIN2
Valid SIN → SCK ↑
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
ns
ns
ns
ns
ns
ns
ns
SCK ↑ → valid SIN
hold time
SCK0 to SCK2,
SIN0 to SIN2
—
Serial clock “H” pulse
width
SCK0 to SCK2
SCK0 to SCK2
4 tCP*
4 tCP*
—
—
Serial clock “L” pulse
width
—
External shift
clock mode
CL = 80 pF
+ 1 TTL for an
output pin
SCK ↓ → SOT delay
SCK0 to SCK2
SOT0 to SOT2
150
—
time
SCK0 to SCK2,
SIN0 to SIN2
Valid SIN → SCK ↑
60
SCK ↑ → valid SIN
hold time
SCK0 to SCK2,
SIN0 to SIN2
60
—
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Notes: • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitor value connected to pins while testing.
92
MB90520 Series
• Internal shift clock mode
tSCYC
SCK
2.4 V
0.8 V
tSLOV
0.8 V
2.4 V
0.2 V
SOT
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SIN
• External shift clock mode
SCK
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
0.2 VCC
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
93
MB90520 Series
(6) Timer Input Timing
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
tTIWH,
tTIWL
IC00,IC01,IC10,
IC11,TI0, TI1
Input pulse width
—
4 tCP*
—
ns
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
IN
tTIWH
tTIWL
(7) Timer Output Timing
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
OUT0 to OUT3,
PG00,
PG01,PG10, PG11
CLK ↑ → TOUT
transition time
tTO
—
30
—
ns
2.4 V
CLK
TOUT
tTO
2.4 V
0.8 V
94
MB90520 Series
5. A/D Converter
Parameter
≤
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, 3.0 V AVRH – AVRL, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit
Min.
—
Typ.
8/10
—
Max.
—
Resolution
—
—
—
—
—
—
bit
Total error
—
±5.0
±2.5
LSB
LSB
Non-linear error
—
—
Differential
linearity error
—
—
—
—
±1.9
LSB
mV
—
Zero transition
voltage
AN0 to
AN7
AVSS
–3.5 LSB
AVSS
+4.5 LSB
VOT
VFST
+0.5 LSB
AVRH
Full-scale
transition
voltage
AN0 to
AN7
AVRH
AVRH
mV
–6.5LSB –1.5 LSB +1.5 LSB
VCC = 5.0 V ±10%
at machine clock of 16 MHz
Conversion time
Sampling time
—
—
—
—
240 tCP*
64 tCP*
—
—
—
—
—
—
—
—
ns
ns
µA
V
VCC = 5.0 V ±10%
at machine clock of 16 MHz
Analog port
input current
AN0 to
AN7
IAIN
10
Analog input
voltage
AN0 to
AN7
VAIN
AVRL
AVRH
AVCC
—
AVRL
+ 2.7
—
—
AVRH
V
Reference
voltage
AVRH
–2.7
AVRL
0
—
5
V
IA
AVCC
—
—
mA
Supply current when CPU
stopped and 8/10-bit A/D
converter not in operation
(VCC = AVCC = AVRH = 5.0 V)
Power supply
current
IAH
IR
AVCC
—
—
—
—
400
—
5
µA
µA
µA
AVRH
AVRH
—
—
5
Reference
voltage supply
current
Supply current when CPU
stopped and 8/10-bit A/D
converter not in operation
(VCC = AVCC = AVRH = 5.0 V)
IRH
Offset between
channels
AN0 to
AN7
—
—
—
—
4
LSB
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
95
MB90520 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000
0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error: The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error, full-scale transition error and linearity error.
Total error
3FF
0.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N – 1) + 0.5 LSB}
004
003
002
001
VNT
(measured value)
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
Analog input
AVRL
AVRH
AVRH – AVRL
1024
VNT – {1 LSB × (N – 1) + 0.5 LSB}
1 LSB = (Theoretical value)
[V]
Total error for digital output N
[LSB]
=
1 LSB
VNT: Voltage at a transition of digital output from (N – 1) to N
VOT (Theoretical value) = AVRL + 0.5 LSB [V]
VFST (Theoretical value) = AVRH – 1.5 LSB [V]
(Continued)
96
MB90520 Series
(Continued)
Linearity error
Differential linearity error
Theoretical
characteristics
3FF
3FE
3FD
Actual conversion
characteristics
N + 1
N
Actual conversion
characteristics
{1 LSB × (N – 1)
+ VOT}
VFST
(measured value)
VNT
N – 1
N – 2
004
003
002
001
(measured value)
V(N + 1)T
(measured value)
Actual conversion
characteristics
VNT (measured value)
Theoretical
Actual conversion
characteristics
characteristics
VOT (mesured value)
Analog input
AVRL
AVRH
AVRL
Analog input
AVRH
Linearity error of
digital output N
VNT – {1 LSB × (N – 1) + VOT}
[LSB]
=
1 LSB
V(N + 1)T – VNT
1 LSB
Differential linearity error
of digital N
– 1 LSB [LSB]
=
VFST – VOT
1 LSB
[V]
=
1022
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
7. Notes for A/D Conversion
Analog inputs should have external circuit impedance of approximately 5 kΩ or less.
External capacitance, if used, should be several thousand times the level of the chip’s internal capacitance in
consideration of the effects of partial potential between the external and internal capacitance.
If the impedance of the external circuit is too high, the analog voltage sampling interval may be insufficient (using
a sampling interval of 4.00 µs and a machine clock frequency of 16 MHz).
• Block diagram of analog input circuit model
RON
C
Analog input
Comparator
MB90522, MB90523
RON: Approx. 1.5 kΩ
C: Approx. 30 pF
MB90F523
RON: Approx. 3.0 kΩ
C: Approx. 65 pF
Note: Listed values must be considered standards.
• Error
The smaller | AVRH – AVRL | is, the greater the error is.
97
MB90520 Series
8. D/A Converter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Symbol
Pin name
Remarks
Parameter
Resolution
Min.
Typ.
Max.
—
—
—
—
—
8
—
bit
Differential linearity
error
—
—
±0.9
LSB
Absolute accuracy
Linearity error
—
—
—
—
—
—
—
—
—
—
—
10
±1.2
±1.5
20
%
LSB
Conversion time
µs Load capacitance: 20 pF
Analog reference
voltage
—
DVCC
VSS + 3.0
—
AVCC
V
IDVR
DVCC
DVCC
—
—
—
—
300
10
µA
Reference voltage
supply current
IDVRS
µA In sleep mode
Analog output
impedance
—
—
—
20
—
kΩ
98
MB90520 Series
■ EXAMPLE CHARACTERISTICS
(1) Power Supply Current (MB90523)
ICC – VCC
ICCS – VCC
ICC (mA)
35
ICCS (mA)
10
TA = +25°C
TA = +25°C
9
8
7
6
5
4
3
2
1
30
Fc = 16 MHz
25
Fc = 16 MHz
Fc = 12.5 MHz
20
15
10
5
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 2 MHz
3.0
4.0
5.0
6.0
3.0
4.0
ICCS – TA
5.0
6.0
VCC (V)
VCC (V)
ICC – TA
ICC (mA)
35
ICCS (mA)
10
VCC = 5.0 V
VCC = 5.0 V
9
8
7
6
5
4
3
2
1
30
25
20
15
10
5
Fc = 16 MHz
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
+100
TA (°C)
+70
+40
+100
TA (°C)
+10
+70
–20
+40
+10
–20
ICCLS – VCC
TA = +25°C
ICCL – VCC
ICCLS (mA)
70
ICCL (µA)
160
TA = +25°C
60
50
40
30
20
10
140
120
100
80
Fc = 8 kHz
Fc = 8 kHz
60
40
20
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
99
MB90520 Series
ICCS – Fc
ICC – Fc
ICC (mA)
35
ICCS (mA)
10
TA = +25°C
TA = +25°C
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
9
8
7
6
5
4
3
2
1
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
30
25
20
15
10
5
VCC = 3.0 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 2.5 V
4.0
6.0
8.0
12.0
16.0
4.0
6.0
8.0
12.0
16.0
Fc (MHz)
Fc (MHz)
ICCT – VCC
ICCH – VCC
ICCT (µA)
ICCH (µA)
20
10
TA = +25°C
TA = +25°C
18
16
14
12
10
8
9
8
7
6
5
4
3
2
1
Fc = 8 kHz
6
4
2
3.0
4.0
ICCT – TA
5.0
6.0
3.0
4.0
ICCH – TA
5.0
6.0
VCC (V)
VCC (V)
ICCT (µA)
ICCL (µA)
10
10
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
VCC = 6.0 V
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 2.5 V
+100
TA (°C)
+70
+40
+100
TA (°C)
+10
+70
–20
+40
+10
–20
100
MB90520 Series
ICCL – TA
ICCLS – TA
ICCL (µA)
ICCLS (µA)
20
14
VCC = 6.0 V
VCC = 5.5 V
18
16
14
12
10
8
VCC = 6.0 V
12
10
8
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
6
6
4
4
2
2
+100
+100
TA (°C)
+70
+70
+40
+40
+10
+10
–20
–20
TA (°C)
(2) Power Supply Current (MB90F523)
ICCS – VCC
ICC – VCC
ICC (mA)
140
ICCS (mA)
40
TA = +25°C
TA = +25°C
35
30
25
20
15
10
5
120
100
80
Fc = 16 MHz
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 12.5 MHz
Fc = 10 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 8 MHz
60
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
40
20
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
ICC – TA
ICCS – TA
ICC (mA)
ICCS (mA)
120
100
80
40
35
30
25
20
15
10
5
VCC = 5.0 V
VCC = 5.0 V
Fc = 16 MHz
Fc = 12.5 MHz
Fc = 16 MHz
60
Fc = 10 MHz
Fc = 8 MHz
Fc = 12.5 MHz
Fc = 10 MHz
40
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
Fc = 8 MHz
Fc = 5 MHz
Fc = 4 MHz
Fc = 2 MHz
20
+100
TA (°C)
+70
+40
+10
+100
TA (°C)
+70
–20
+40
+10
–20
101
MB90520 Series
ICCS – VCC
ICCLS (µA)
200
180
160
140
120
100
80
TA = +25°C
Fc = 8 MHz
60
40
20
3.0
4.0
5.0
6.0
VCC (V)
ICC – Fc
ICCS – Fc
ICCS (mA)
ICC (mA)
120
40
35
30
25
20
15
10
5
TA = +25°C
TA = +25°C
VCC = 6.0 V
100
80
60
40
20
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.5 V
4.0
8.0
12.0
16.0
Fc (MHz)
4.0
8.0
12.0
16.0
Fc (MHz)
ICCT – VCC
ICCH – VCC
ICCT (µA)
ICCH (µA)
50
10
TA = +25°C
TA = +25°C
9
40
30
20
10
8
7
Fc = 8 kHz
6
5
4
3
2
1
3.0
4.0
5.0
6.0
VCC (V)
3.0
4.0
5.0
6.0
VCC (V)
102
MB90520 Series
ICCH – TA
ICCT – TA
ICCH (µA)
ICCT (µA)
10
10
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
+100
+70
+100
TA (°C)
+40
+70
+10
+40
–20
+10
–20
TA (°C)
ICCLS – TA
ICCLS (µA)
20
18
16
14
12
10
8
VCC = 6.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 4.0 V
VCC = 3.5 V
VCC = 3.0 V
VCC = 2.5 V
6
4
2
+100
TA (°C)
+70
+40
+10
–20
103
MB90520 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90523PFF
MB90522PFF
MB90F523PFF
120-pin Plastic LQFP
(FPT-120P-M05)
MB90523PFV
MB90522PFV
MB90F523PFV
120-pin Plastic QFP
(FPT-120P-M13)
104
MB90520 Series
■ PACKAGE DIMENSIONS
120-pin Plastic LQFP
(FPT-120P-M05)
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
.059 +–..000048
(Mounting height)
INDEX
120
31
"A"
0~8°
1
30
LEAD No.
0.10±0.10
(.004±.004)
(Stand off)
0.16±0.03
(.006±.001)
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
M
0.07(.003)
0.40(.016)
0.45/0.75
(.018/.030)
0.25(.010)
Dimensions in mm (inches)
C
1998 FUJITSU LIMITED F120006S-3C-4
120-pin Plastic QFP
(FPT-120P-M13)
22.60±0.20(.890±.008)SQ
20.00±0.10(.787±.004)SQ
3.85(.152)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
90
61
91
60
Details of "A" part
0.15(.006)
14.50
(.571)
REF
21.60
(.850)
NOM
0.15(.006)
INDEX
0.15(.006)MAX
0.40(.016)MAX
"A"
120
31
M
Details of "B" part
1
30
LEAD No.
0.50(.0197)
0.20±0.10
(.008±.004)
0.125±0.05
(.005±.002)
0.08(.003)
0
10°
0.50±0.20(.020±.008)
"B"
0.10(.004)
Dimensions in mm (inches)
C
1995 FUJITSU LIMITED F120013S-2C-3
105
MB90520 Series
FUJITSU LIMITED
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Electronic Devices
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F0012
FUJITSU LIMITED Printed in Japan
相关型号：
MB90523PFV-G
Microcontroller, 16-Bit, MROM, F2MC-16LX CPU, 16MHz, CMOS, PQFP120, PLASTIC, QFP-120
FUJITSU
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