MB90565_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13715-3E

16-bit Proprietary Microcontrollers

CMOS

F²MC-16LX MB90560/565 Series

MB90561/561A/562/562A/F562/F562B/V560

MB90567/568/F568

■ DESCRIPTION

The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and process

control applications that require high-speed real-time processing. The device features a multi-function timer able

to output a programmable waveform.

The microcontroller instruction set is based on the same AT architecture as the F²MC-8L and F²MC-16L families

with additional instructions for high-level languages, extended addressing modes, enhanced signed multiplication

and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a

32-bit accumulator for processing long word (32-bit) data.

■ FEATURES

• Clock

• Internal oscillator circuit and PLL clock multiplication circuit

• Oscillation clock

Clockspeedselectablefromeitherthemachineclock, mainclock, orPLLclock. Themainclockistheoscillation

clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation

clock multiplied by one to four (4 MHz to 16 MHz for a 4 MHz base oscillation) .

• Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, V^CC= 5.0 V)

• Maximum CPU memory space : 16 MB

• 24-bit addressing

• Bank addressing

(Continued)

■ PACKAGES

64-pin plastic QFP

64-pin plastic LQFP

64-pin plastic SH-DIP

(FPT-64P-M06)

(FPT-64P-M09)

(DIP-64P-M01)

MB90560/565 Series

(Continued)

• Instruction set

• Bit, byte, word, and long word data types

• 23 different addressing modes

• Enhanced calculation precision using a 32-bit accumulator

• Enhanced signed multiplication and division instructions and RETI instruction

• Instruction set designed for high level language (C) and multi-tasking

• Uses a system stack pointer

• Symmetric instruction set and barrel shift instructions

• Program patch function (2 address pointers) .

• 4-byte instruction queue

• Interrupt function

• Priority levels are programmable

• 32 interrupts

• Data transfer function

• Extended intelligent I/O service function : Up to 16 channels

• Low-power consumption modes

• Sleep mode (CPU operating clock stops.)

• Timebase timer mode (Only oscillation clock and timebase timer continue to operate.)

• Stop mode (Oscillation clock stops.)

• CPU intermittent operation mode (The CPU operates intermittently at the specified interval.)

• Package

• LQFP-64P (FTP-64P-M09 : 0.65 mm pin pitch)

• QFP-64P (FTP-64P-M06 : 1.00 mm pin pitch)

• SH-DIP (DIP-64P-M01 : 1.778 mm pin pitch)

• Process : CMOS technology

■ PERIPHERAL FUNCTIONS (RESOURCES)

• I/O ports : 51 ports (max.)

• Timebase timer : 1 channel

• Watchdog timer : 1 channel

• 16-bit reload timer : 2 channel 5

• Multi-function timer

• 16-bit free-run timer : 1 channel

• Output compare : 6 channels

Can output an interrupt request when a match occurs between the count in the 16-bit freerun timer and the

value set in the compare register.

• Input capture : 4 channels

On detecting an active edge on the input signal from an external input pin, copies the count value of the 16-

bit freerun timer to the input capture data register and generates an interrupt request.

• 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) The period and duty of the output pulse can

be set by the program.

• Waveform generator (8-bit timer : 3 channels)

• UART : 2 channels

• Full-duplex, double-buffered (8-bit)

• Can be set to asynchronous or clock synchronous serial transfer (I/O expansion serial) operation

• DTP/external interrupt circuit (8 channels)

• External interrupts can activate the extended intelligent I/O service.

• Generates interrupts in response to external interrupt inputs.

2

MB90560/565 Series

• Delayed interrupt generation module

• Generates an interrupt request for task switching.

• 8/10-bit A/D converter : 8 channels

• 8-bit or 10-bit resolution selectable

3

MB90560/565 Series

■ PRODUCT LINEUP

1. MB90560 Series

Part Number

MB90F562/B

MB90562/A

MB90561/A

MB90V560

Internal flash memory

product

Classification

Internal mask ROM product

Evaluation product

ROM size

RAM size

64 Kbytes

32 Kbytes

1 Kbytes

No ROM

4 Kbytes

2 Kbytes

Dedicated emula-

tor power supply^*

No

Number of instructions : 351

Minimum instruction execution time : 62.5 ns for a 4 MHz oscillation (with ×4 multiplier)

Addressing modes : 23 modes

Program patch function : 2 address pointers

CPU functions

Ports

Maximum memory space : 16 Mbytes

I/O ports (CMOS) : 51

Full-duplex, double-buffered

Clock synchronous or asynchronous operation selectable

Can be used as I/O serial

UART

Internal dedicated baud rate generator

2 channels

16-bit reload timer operation

2 channels

16-bit reload timer

16-bit free-run timer × 1 channel

Output compare × 6 channels

Input capture × 4 channels

8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels)

Waveform generator (8-bit timer × 3 channels) 3-phase waveform output, deadtime output

Multi-function

timer

8 channels (multiplexed input)

8-bit or 10-bit resolution selectable

Conversion time : 6.13 µs (min.) (for maximum machine clock speed 16 MHz)

8/10-bit

A/D converter

8 channels (8 channels available, shared with A/D input)

Interrupt triggers :

“L” → “H” edge, “H” → “L” edge, “L” level, “H” level (selectable)

DTP/external

interrupts

Low power

consumption

modes

Sleep mode, timebase timer mode, stop mode, and CPU intermittent operation mode

CMOS

Process

Operating voltage 5 V ± 10%

* : DIP switch setting (S2) when using the emulation pod (MB2145-507) .

Refer to “2.7 Dedicated Emulator Power Supply” in the “MB2145-507 Hardware Manual” for details.

4

MB90560/565 Series

2. MB90565 Series

Part Number

MB90F568

MB90568

MB90567

Classification

ROM size

Internal flash memory product

128 Kbytes

4 Kbytes

Internal mask ROM product

96 Kbytes

4 Kbytes

RAM size

Dedicated emula-

tor power supply^*

Number of instructions : 351

Minimum instruction execution time : 62.5 ns for a 4 MHz oscillation (with ×4 multiplier)

Addressing modes : 23 modes

Program patch function : 2 address pointers

CPU functions

Ports

Maximum memory space : 16 Mbytes

I/O ports (CMOS) : 51

Full-duplex, double-buffered

Clock synchronous or asynchronous operation selectable

Can be used as I/O serial

UART

Internal dedicated baud rate generator

2 channels

16-bit reload timer operation

2 channels

16-bit reload timer

16-bit free-run timer × 1 channel

Output compare × 6 channels

Input capture × 4 channels

8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels)

Waveform generator (8-bit timer × 3 channels) 3-phase waveform output, deadtime output

Multi-function

timer

8 channels (multiplexed input)

8-bit or 10-bit resolution selectable

Conversion time : 6.13 µs (min.) (for maximum machine clock speed 16 MHz)

8/10-bit A/D

converter

8 channels (8 channels available, shared with A/D input)

Interrupt triggers :

“L” → “H” edge, “H” → “L” edge, “L” level, “H” level (selectable)

DTP/external

interrupts

Low power con-

sumption modes

Sleep mode, timebase timer mode, stop mode, and CPU intermittent operation mode

CMOS

Process

Operating voltage 3.3 V ± 0.3 V

* : DIP switch setting (S2) when using the emulation pod (MB2145-507) .

Refer to “2.7 Dedicated Emulator Power Supply” in the “MB2145-507 Hardware Manual” for details.

5

MB90560/565 Series

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

MB90561/A MB90562/A MB90F562/B MB90567 MB90568 MB90F568 MB90V560

FPT-64P-M09

(LQFP-0.65 mm)

×

FPT-64P-M06

(QFP-1.00 mm)

DIP-64P-M01

(SH-DIP)

×

PGA-256C-A01

(PGA)

×

: Available

: Not available

Note : See the “Package Dimensions” section for details of each package.

6

MB90560/565 Series

■ PIN ASSIGNMENTS

(TOP VIEW)

P44/PPG3

P45/PPG4

P46/PPG5

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

1

2

3

4

5

6

7

8

9

51 P30/RTO0

50 VSS

49 P27/IN3

48 P26/IN2

47 P25/IN1

46 P24/IN0

45 P23/TO1

44 P22/TIN1

43 P21/TO0

42 P20/TIN0

41 P17/FRCK

40 P16/INT6

39 P15/INT5

38 P14/INT4

37 P13/INT3

36 P12/INT2

35 P11/INT1

34 P10/INT0

33 P07

P56/AN6 10

P57/AN7 11

AVCC 12

AVR 13

AVSS 14

P60/SIN1 15

P61/SOT1 16

P62/SCK1 17

P63/INT7/DTTI 18

MD0 19

(FPT-64P-M06)

* : N.C. on the MB90F568, MB90567, and MB90568.

(Continued)

7

MB90560/565 Series

(TOP VIEW)

P45/PPG4

P46/PPG5

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

1

2

3

4

5

6

7

8

9

48 P27/IN3

47 P26/IN2

46 P25/IN1

45 P24/IN0

44 P23/TO1

43 P22/TIN1

42 P21/TO0

41 P20/TIN0

40 P17/FRCK

39 P16/INT6

38 P15/INT5

37 P14/INT4

36 P13/INT3

35 P12/INT2

34 P11/INT1

33 P10/INT0

P57/AN7 10

AVCC 11

AVR 12

AVSS 13

P60/SIN1 14

P61/SOT1 15

P62/SCK1 16

(FPT-64P-M09)

* : N.C. on the MB90F568, MB90567, and MB90568.

(Continued)

8

MB90560/565 Series

(Continued)

(TOP VIEW)

C^*

P36/SIN0

P37/SOT0

P40/SCK0

P41/PPG0

P42/PPG1

P43/PPG2

P44/PPG3

P45/PPG4

P46/PPG5

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AVCC

VCC

1

2

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P35/RTO5

P34/RTO4

P33/RTO3

P32/RTO2

P31/RTO1

P30/RTO0

VSS

3

4

5

6

7

8

9

P27/IN3

P26/IN2

P25/IN1

P24/IN0

P23/TO1

P22/TIN1

P21/TO0

P20/TIN0

P17/FRCK

P16/INT6

P15/INT5

P14/INT4

P13/INT3

P12/INT2

P11/INT1

P10/INT0

P07

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

AVR

AVSS

P60/SIN1

P61/SOT1

P62/SCK1

P63/INT7/DTTI

MD0

P06

RST

P05

MD1

P04

MD2

P03

X0

P02

X1

P01

VSS

P00

(DIP-64P-M01)

(Only support MB90F562/B, MB90561/A, and MB90562/A.)

* : Not support on the MB90F568, MB90567, and MB90568.

9

MB90560/565 Series

■ PIN DESCRIOTIONS

Pin No.

State/

Function

at Reset

Circuit

Description

Name Type^*

QFPM06 LQFPM09 SDIP

Connect oscillator to these pins.

If using an external clock, leave X1 open.

23, 24

20

22, 23

19

30, 31 X0, X1

A

B

C

Oscillator

Reset

input

27

RST

External reset input pin

I/O ports

P00 to

P07

26 to 33

25 to 32 33 to 40

P10 to

P16

I/O ports

Can be used as interrupt request inputs ch0 to ch6.

In standby mode, these pins can operate as inputs

by setting the bits corresponding to EN0 to EN6 to

“1” and setting as input ports. When used as a port,

set the corresponding bits in the analog input

enable register (ADER) to “port”.

34 to 40

33 to 39 41 to 47

C

INT0to

INT6

P17

I/O port

External clock input pin for the freerun timer.

This pin can be used as an input when set as the

clock input for the freerun timer and set as an input

port. When used as a port, set the corresponding

bit in the analog input enable register (ADER) to

“port”.

41

40

48

FRCK

Port

inputs

(Hi-Z

P20

I/O port

External clock input pin for reload timer ch0. This

pin can be used as an input when set as the exter-

nal clock input and set as an input port.

42

43

44

45

41

42

43

44

49

50

51

52

D

TIN0

outputs)

P21

TO0

P22

I/O port

Event output pin for reload timer ch0. Output oper-

ates when event output is enabled.

I/O port

External clock input pin for reload timer ch1. This

pin can be used as an input when set as the exter-

nal clock input and set as an input port.

TIN1

P23

TO1

I/O port

Event output pin for reload timer ch1. Output oper-

ates when event output is enabled.

P24 to

P27

I/O ports

46 to 49

45 to 48 53 to 56

D

Trigger input pins for input capture ch0 to ch3.

These pins can be used as an input when set as an

input capture trigger input and set as an input port.

IN0 to

IN3

* : See “■ I/O CIRCUITS” for details of the circuit types.

(Continued)

10

MB90560/565 Series

Pin No.

Cir-

cuit

State/

Name

Function

Description

Type^*at Reset

QFPM06 LQFPM09 SDIP

P30 to

P35

I/O ports

Event output pins for the output compare and wave-

form generator output pins. The pins output the

specified waveform generated by the waveform

generator. If not using waveform generation, these

terminals enable output compare event output to

use as output compare outputs. When used as a

port, set the corresponding bits in the analog input

enable register (ADER) to “port”.

51 to 56 50 to 55 58 to 63

E

RTO0

to

RTO5

P36

I/O port

Serial data input pin for UART ch0.

59

58

2

D

This pin is used continuously when input operation

is enabled for UART ch0. In this case, do not use as

a general input pin.

SIN0

Port

inputs

(Hi-Z)

P37

SOT0

P40

I/O port

60

61

59

60

3

4

D

Serial data output pin for UART ch0.

Output operates when UART ch0 output is enabled.

I/O port

Serial clock I/O pin for UART ch0.

Output operates when UART ch0 clock output is

enabled.

SCK0

P41 to

P46

I/O ports

62 to 64, 61 to 64,

5 to 10

D

PPG0

to

PPG5

Output pins for PPG ch0 to ch5.

The outputs operate when output is enabled for

PPG ch0 to ch5.

1 to 3

1, 2

P50 to

P57

I/O ports

Analog

inputs

4 to 11

3 to 10 11 to 18

F

Analog input pins for the A/D converter. Input is

available when the corresponding analog input en-

able register bits are set. (ADER : bit0 to bit7)

AN0 to

AN7

Power

12

13

14

11

12

13

19

20

21

AV^CC

AVR

AV^SS

supply VCC power supply input pin for A/D converter.

input

Refer-

Reference voltage input pin for A/D converter.

G

ence volt-

Ensure that the voltage does not exceed V^CC.

age input

Power

supply VSS power supply input pin for A/D converter.

input

* : See “■ I/O CIRCUITS” for details of the circuit types.

(Continued)

11

MB90560/565 Series

(Continued)

Pin No.

State/

Function

at Reset

Name

Circuit

Description

Type^*1

QFPM06 LQFPM09 SDIP

P60

I/O port

Serial data input pin for UART ch1.

15

14

22

D

This pin is used continuously when input opera-

tion is enabled for UART ch1. In this case, do not

use as a general input pin.

SIN1

P61

SOT1

P62

I/O port

Serial data output pin for UART ch1.

Output operates when UART ch1 output is en-

abled.

16

17

15

16

23

24

D

I/O port

Port input

(Hi-Z)

Serial clock I/O pin for UART ch1.

Output operates when UART ch1 clock output is

enabled.

SCK1

P63

I/O port

This pin can be used as interrupt request input

ch7. In standby mode, this pin can operate as an

input by setting the bit corresponding to EN7 to

“1” and setting as an input port.

INT7

DTTI

C^*2

18

58

17

57

25

D

Fixed pin level input pin when RTO0 to RTO5

pins are used. Input is enabled when “input en-

abled” set in the waveform generator.

Capacitor

pin, pow-

er supply

input

Capacitor pin for stabilizing the power supply.

Connect an external ceramic capacitor of approx-

imately 0.1 µF.

1

Input pin for setting the operation mode.

Connect directly to VCC or VSS.

19

21

18

20

26

28

MD0

MD1

B

Mode

Input pin for setting the operation mode.

input pins Connect directly to V^CCor VSS.

Input pin for setting the operation mode.

Connect directly to V^SS.

22

25, 50

57

21

24, 49

56

29

32, 57

64

MD2

V^SS

Power supply (GND) input pin

Power

supply

inputs

MB90560 series is power supply (5 V) input pin

MB90565 series is power supply (3.3 V) input pin

V^CC

*1 : See “■ I/O CIRCUITS” for details of the circuit types.

*2 : N.C. on the MB90F568, MB90567, and MB90568

12

MB90560/565 Series

■ I/O CIRCUITS

Type

Circuit

Remarks

• Oscillation circuit

Internal oscillation feedback

resistor (R^f)

X1

Xout

Rf

Nch

X0

A

B

Pch

Nch

Standby control signal

Reset input

• CMOS hysteresis reset input pin

• CMOS hysteresis I/O pin with pull-up

control

CMOS output

Pull-up control

Pout

Rp

CMOS hysteresis input (with input cut-

off function in standby mode)

Internal pull-up resistor (R^p)

< Note >

Pch

Nch

Nout

C

• The pull-up resistor is active when the

Input signal

port is set as an input.

Standby control signal

• CMOS hysteresis I/O pin

CMOS output

CMOS hysteresis input (with input cut-

off function in standby mode)

< Notes >

Pch

Pout

Nout

Nch

• The I/O port output and internal

resource output share the same out-

put buffer.

D

Input signal

• The I/O port input and internal

resource input share the same input

buffer.

Standby control signal

(Continued)

13

MB90560/565 Series

(Continued)

Type

Circuit

Remarks

• CMOS I/O pin

CMOS output

CMOS hysteresis input (with input cut-

off function in standby mode)

Pch

Nch

Pout

Nout

E

< I^OL= 12 mA >

Hysteresis input

Standby control signal

• Analog/CMOS hysteresis I/O pin

CMOS output

Pch

Nch

Pout

Nout

CMOS hysteresis input (with input cut-

off function in standby mode)

Analog input (Analog input to A/D con-

verter is enabled when “1” is set in the

corresponding bit in the analog input

enable register (ADER) .)

Input signal

F

• The I/O port output and internal

resource output share the same out-

put buffer.

Standby control signal

A/D converter analog input

• The I/O port input and internal

resource input share the same input

buffer.

• A/D converter (AVR) voltage input pin

Pch

Nch

Pch

Nch

AVR input

G

Analog input

enable signal

from A/D converter

14

MB90560/565 Series

■ HANDLING DEVICES

Take note of the following nine points when handling devices :

• Do not exceed maximum rated voltage (to prevent latch-up)

• Supply voltage stability

• Power-on precautions

• Treatment of unused pins

• Treatment of A/D converter power supply pins

• Notes on using an external clock

• Power supply pins

• Sequence for connecting and disconnecting the A/D converter power supply and analog input pins

• Notes on using the DIV A, Ri and DIVW A, RWi instructions

• Device Handling Precautions

(1) Do not exceed maximum rated voltage (to prevent latch-up)

Do not apply a voltage grater than V^CCor less than VSS to the MB90560/565 series input or output pins. Also

ensure that the voltage between VCC and VSS does not exceed the rating. Applying a voltage in excess of the

ratings may result in latch-up causing thermal damage to circuit elements.

Similarly, when connecting or disconnecting the power to the analog power supply (AVCC, AVR) and analog

inputs (AN0 to AN7) , ensure that the analog power supply voltages do not exceed the digital voltage (VCC) .

(2) Supply voltage stability

Rapid changes in the V^CCsupply voltage may cause the device to misoperate. Accordingly, ensure that the VCC

power supply is stable. The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at

the supply frequency (50 to 60 Hz) of 10% or less of VCC and a transient fluctuation in the voltage of 0.1 V/ms

or less when turning the power supply on or off.

(3) Power-on precautions

To prevent misoperation of the internal regulator circuit, ensure that the voltage rise time at power-on is at least

50 µs (between 0.2 V to 2.7 V) .

(4) Treatment of unused pins

Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to

latchup. Always pull-up or pull-down unused pins using a 2 kΩ or larger resistor.

If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same

way as input pins.

(5) Treatment of A/D converter power supply pins

If not using the A/D converter, connect the analog power supply pins so that AV^CC= AVR = VCC and AVSS = VSS.

(6) Notes on using an external clock

Even if using an external clock, an oscillation stabilization delay time occurs after a power-on reset and when

recovering from stop mode in the same way as when an oscillator is connected. When using an external clock,

drive the X0 pin only and leave the X1 pin open.

15

MB90560/565 Series

X0

X1

OPEN

MB90560/565 series

Example of using an external clock

(7) Power supply pins

The multiple V^CCand VSS pins are connected together in the internal device design so as to prevent misoperation

such as latch-up. However, always connect all VCC and VSS pins to the same potential externally to minimize

spurious radiation, prevent misoperation of strobe signals due to increases in the ground level, and maintain the

overall output current rating.

Also, ensure that the impedance of the V^CCand VSS connections to the power supply is as low as possible.

To minimize these problems, connect a bypass capacitor of approximately 0.1 µF between VCC and VSS. Connect

the capacitor close to the VCC and VSS pins.

(8) Sequence for connecting and disconnecting power supply

Do not apply voltage to the A/D converter power supply pins (AV^CC, AVR, AVSS) or analog inputs (AN0 to AN7)

until the digital power supply (V^CC) is turned on. When turning the device off, turn off the digital power supply

after disconnecting the A/D converter power supply and analog inputs. When turning the power on or off, ensure

that AVR does not exceed AVCC.

When using the I/O ports that share pins with the analog inputs, ensure that the input voltage does not exceed

AV^CC(turning the analog and digital power supplies on and off simultaneously is OK) .

(9) Conditions when output from ports 0 and 1 is undefined

After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabilization

delay time controlled by the regulator circuit (during the power-on reset) if the RST pin level is “H”. When the

RST pin level is “L”, ports 0 and 1 go to high impedance.

Figures 1 and 2 show the timing (for the MB90F562/B and MB90V560) .

Note that this undefined output period does not occur on products without an internal regulator circuit as these

products do not have an oscillation stabilization delay time.

(MB90561/A, MB90562/A, MB90F568, and MB90567/8)

16

MB90560/565 Series

• Figure 1 Timing chart for undefined output from ports 0 and 1 (When RST pin level is “H”)

Oscillation stabilization delay time^*2

Regulator circuit

stabilization delay time^*1

VCC (Power supply pin)

PONR (Power-on reset) signal

RST (External asynchronous reset) signal

RST (Internal reset) signal

Oscillation clock signal

KA (Internal operating clock A) signal

KB (Internal operating clock B) signal

PORT (port output) signal

Undefined output time

*1 : Regulator circuit oscillation stabilization delay time :

2¹⁷/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency)

*2 : Oscillation stabilization delay time :

2¹⁸/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency)

17

MB90560/565 Series

• Figure 2 Timing chart for ports 0 and 1 going to high impedance state (When RST pin level is “L”)

Oscillation stabilization delay time^*2

Regulator circuit

stabilization delay time^*1

VCC (Power supply pin)

PONR (Power-on reset) signal

RST (External asynchronous reset) signal

RST (Internal reset) signal

Oscillation clock signal

KA (Internal operating clock A) signal

KB (Internal operating clock B) signal

PORT (port output) signal

High impedance

*1 : Regulator circuit oscillation stabilization delay time :

2¹⁷/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency)

*2 : Oscillation stabilization delay time :

2¹⁸/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency)

(10) Notes on using the DIV A, Ri and DIVW A, RWi instructions

The location in which the remainder value produced by the signed division instructions “DIV A, Ri” and “DIVW

A, RWi” is stored depends on the bank register. The remainder is stored in an address in the memory bank

specified in the bank register.

Set the bank register to “00^H” when using the “DIV A, Ri” and “DIVW A, RWi” instructions.

(11) Notes on using REALOS

The extended intelligent I/O service (EI²OS) cannot be used when using REALOS.

(12) Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free-

running frequency of the self oscillation circuit in the PLL circuitry even if the oscillator is out of place or the clock

input is stopped. Performance of this operation, however, cannot be guaranteed.

18

MB90560/565 Series

■ BLOCK DIAGRAM

X0, X1

RST

MD0 to MD2

Clock

control circuit

F²MC-16LX

CPU

Interrupt controller

8/16-bit

PPG timer

PPG0 to PPG5

IN0 to IN3

RAM

ROM

ch0 to ch5^*

Input

capture

SIN0

SOT0

SCK0

ch0 to ch3

UART

ch0

SIN1

SOT1

SCK1

16-bit

freerun

timer

UART

ch1

FRCK

AVCC

AVR

8/10-bit

RTO0

RTO1

RTO2

RTO3

RTO4

RTO5

DTTI

AVSS

AN0 to AN7

A/D converter

Output

compare

ch0 to ch5

16-bit

reload timer

ch0

TO0

TIN0

Waveform generator circuit

16-bit

reload timer

ch1

TO1

TIN1

DTP/

external interrupts

INT0 to INT7

I/O ports (Ports 0, 1, 2, 3, 4, 5, and 6)

P00

P07

P10

P17

P20

P27

P30

P37

P40

P46

P50

P57

P60

P63

* : Channel numbers when used as 8-bit timers. Three channels (ch1, ch3, and ch5) are available when used

as 16-bit timers.

Note: The I/O ports share pins with the various peripheral functions (resources) .

See the Pin Assignment and Pin Description sections for details.

Note that, if a pin is used by a peripheral function (resource) , it may not be used as an I/O port.

19

MB90560/565 Series

■ MEMORY MAP

Single chip mode

(with ROM mirror function)

FFFFFFH

ROM area

Address #1

FF0000H

010000H

ROM area

(image of FF bank)

Address #2

004000H

Address #3

RAM

Registers

area

000100H

0000C0H

Peripherals

000000H

Access prohibited

Part No.

MB90561/A

MB90562/A

MB90F562/B

MB90567

Address#1

FF8000^H

FF0000H

FE8000H

FE0000H

Address#2

Address#3

000500H

000900H

001100H

008000H

004000H

MB90568

MB90F568

MB90V560

*

FE0000H

004000H

* : “V” products do not contain internal ROM. Treat this address as the ROM decode area

used by the tools.

Memory map of MB90560/565 series

Notes : • When specified in the ROM mirror function register, the upper part of 00 bank (“004000H to 00FFFFH”)

contains a mirror of the data in the upper part of FF bank (“FF4000H to FFFFFFH”) .

• See “10. ROM Mirror Function Selection Module” in the Peripheral Functions section for details of the

ROM mirror function settings.

Remarks : • The ROM mirror function is provided so the C compiler’s small memory model can be used.

• The lower 16 bits of the FF bank and 00 bank addresses are the same. However, as the FF bank ROM

area exceeds 48 KBytes, the entire ROM data area cannot be mirrored in 00 bank.

• When using the C compiler’s small memory model, locating data tables in the area “FF4000^Hto

FFFFFFH” makes the image of the data visible in the “004000H to 00FFFFH” area. This means that

data tables located in ROM can be referenced without needing to declare far pointers.

20

MB90560/565 Series

■ I/O MAP

Abbreviat-

Address ed Register

Name

Read/

Register name

Port 0 data register

Resource Name Initial Value

Write

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

XXXXXXXXB

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

000007H

to

Access prohibited

00000FH

000010^H

000011H

000012H

000013H

000014H

000015H

000016H

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

0 0 0 0 0 0 0 0B

X 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

XXXX 0 0 0 0B

Port 5,

A/D converter

000017H

ADER

Analog input enable register

R/W

1 1 1 1 1 1 1 1B

000018H

to

Access prohibited

00001FH

000020^H

000021H

SMR0

SCR0

SIDR0

SODR0

SSR0

Mode register ch0

R/W

W, R/W

R

0 0 0 0 0 X 0 0B

0 0 0 0 0 1 0 0B

Control register ch0

Input data register ch0

Output data register ch0

Status register ch0

Mode register ch1

UART0

UART1

000022H

XXXXXXXX^B

W

000023^H

000024H

000025H

R, R/W

R/W

W, R/W

R

0 0 0 0 1 0 0 0B

0 0 0 0 0 X 0 0B

0 0 0 0 0 1 0 0B

SMR1

SCR1

SIDR1

SODR1

SSR1

Control register ch1

Input data register ch1

Output data register ch1

Status register ch1

000026H

XXXXXXXX^B

W

000027H

000028H

R, R/W

0 0 0 0 1 0 0 0B

Access prohibited

Communication prescaler

control register ch0

Communication

prescaler

000029H

CDCR0

R/W

0 XXX 0 0 0 0B

(Continued)

21

MB90560/565 Series

Abbreviat-

Address ed Register

Name

Read/

Write

Register name

Resource Name Initial Value

00002A^H

Access prohibited

Communication prescaler

control register ch1

Communication

0 XXX 0 0 0 0B

prescaler

00002B^H

CDCR1

R/W

00002CH

to

Access prohibited

00002FH

000030H

000031H

000032H

000033H

000034H

000035H

000036H

000037H

000038H

000039H

00003AH

00003BH

00003CH

00003DH

00003EH

00003FH

000040H

000041H

000042H

000043H

000044H

000045H

000046H

000047H

000048^H

000049H

00004AH

00004BH

00004CH

ENIR

EIRR

DTP/external interrupt enable register

DTP/external interrupt request register

Request level setting register (lower)

Request level setting register (upper)

A/D control status register (lower)

A/D control status register (upper)

A/D data register (lower)

R/W

W, R/W

R

0 0 0 0 0 0 0 0B

XXXXXXXXB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

XXXXXXXXB

0 0 0 0 0 XXXB

XXXXXXXXB

DTP/external

interrupts

ELVR

ADCS0

ADCS1

ADCR0

ADCR1

PRLL0

PRLH0

PRLL1

PRLH1

PPGC0

PPGC1

PCS01

8/10-bit

A/D converter

A/D data register (upper)

R, W

R/W

PPG reload register ch0 (lower)

PPG reload register ch0 (upper)

PPG reload register ch1 (lower)

PPG reload register ch1 (upper)

PPG control register ch0 (lower)

PPG control register ch1 (upper)

PPG clock control register ch0, ch1

8/16-bit PPG timer XXXXXXXXB

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 XXB

Access prohibited

PRLL2

PRLH2

PRLL3

PRLH3

PPGC2

PPGC3

PCS23

PPG reload register ch2 (lower)

PPG reload register ch2 (upper)

PPG reload register ch3 (lower)

PPG reload register ch3 (upper)

PPG control register ch2 (lower)

PPG control register ch3 (upper)

PPG clock control register ch2, ch3

R/W

XXXXXXXXB

8/16-bit PPG timer XXXXXXXXB

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 XXB

Access prohibited

PRLL4

PRLH4

PRLL5

PRLH5

PPGC4

PPG reload register ch4 (lower)

PPG reload register ch4 (upper)

PPG reload register ch5 (lower)

PPG reload register ch5 (upper)

PPG control register ch4 (lower)

R/W

XXXXXXXXB

8/16-bit PPG timer XXXXXXXXB

XXXXXXXXB

0 0 0 0 0 0 0 1B

(Continued)

22

MB90560/565 Series

Abbreviat-

Address ed Register

Name

Read/

Register name

Resource Name Initial Value

Write

00004D^H

00004EH

00004FH

000050H

000051H

000052H

000053H

000054H

000055H

000056H

000057H

000058H

000059H

00005AH

00005BH

00005CH

00005DH

00005EH

00005F^H

000060H

000061H

000062H

000063H

000064H

000065H

000066H

000067H

000068H

000069H

00006AH

PPGC5

PCS45

PPG control register ch5 (upper)

PPG clock control register ch4, ch5

R/W

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 XXB

8/16-bit PPG timer

Access prohibited

TMRR0

DTCR0

TMRR1

DTCR1

TMRR2

DTCR2

SIGCR

8-bit reload register ch0

R/W

XXXXXXXXB

0 0 0 0 0 0 0 0B

XXXXXXXXB

0 0 0 0 0 0 0 0B

XXXXXXXXB

0 0 0 0 0 0 0 0B

8-bit timer control register ch0

8-bit reload register ch1

Waveform

generator

8-bit timer control register ch1

8-bit reload register ch2

8-bit timer control register ch2

Waveform control register

Access prohibited

Compare clear register (lower)

Compare clear register (upper)

Timer data register (lower)

R/W

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 XX 0 0 0 0 0B

CPCLR

TCDT

TCCS

16-bit freerun

timer

Timer data register (upper)

Timer control/status register (lower)

Timer control/status register (upper)

Access prohibited

Input capture data register ch0 (lower)

Input capture data register ch0 (upper)

Input capture data register ch1 (lower)

Input capture data register ch1 (upper)

Input capture data register ch2 (lower)

Input capture data register ch2 (upper)

Input capture data register ch3 (lower)

Input capture data register ch3 (upper)

Input capture control register 01

R

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

IPCP0

IPCP1

IPCP2

R

Input capture

R

IPCP3

ICS01

R

R/W

Access prohibited

ICS23

Input capture control register 23

R/W

Input capture

0 0 0 0 0 0 0 0B

(Continued)

00006BH

to

00006EH

Access prohibited

23

MB90560/565 Series

Abbreviat-

Address ed Register

Name

Read/

Write

Register name

Resource Name Initial Value

ROM mirror

00006F^H

ROMM

ROM mirror function selection register

W

function selection XXXXXXX 1B

module

000070H

000071H

000072H

000073H

000074H

000075H

000076H

000077H

000078H

000079H

00007AH

00007BH

00007CH

00007DH

00007EH

00007FH

000080H

000081H

Compare register ch0 (lower)

Compare register ch0 (upper)

Compare register ch1 (lower)

Compare register ch1 (upper)

Compare register ch2 (lower)

Compare register ch2 (upper)

Compare register ch3 (lower)

Compare register ch3 (upper)

Compare register ch4 (lower)

Compare register ch4 (upper)

Compare register ch5 (lower)

Compare register ch5 (upper)

Compare control register ch0 (lower)

Compare control register ch1 (upper)

Compare control register ch2 (lower)

Compare control register ch3 (upper)

Compare control register ch4 (lower)

Compare control register ch5 (upper)

R/W

R

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

OCCP0

OCCP1

OCCP2

OCCP3

OCCP4

OCCP5

XXXXXXXX^B

Output compare

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 XX 0 0B

XXX 0 0 0 0 0B

0 0 0 0 XX 0 0B

XXX 0 0 0 0 0B

0 0 0 0 XX 0 0B

XXX 0 0 0 0 0B

0 0 0 0 0 0 0 0B

XXXX 0 0 0 0B

XXXXXXXXB

OCS0

OCS1

OCS2

OCS3

OCS4

OCS5

000082H TMCSR0 : L Timer control status register ch0 (lower)

000083H TMCSR0 : H Timer control status register ch0 (upper)

TMR0

TMRLR0 16-bit reload register ch0 (lower)

TMR0 16-bit timer register ch0 (upper)

TMRHR0 16-bit reload register ch0 (upper)

16-bit timer register ch0 (lower)

000084H

000085H

W

R

W

XXXXXXXXB

16-bit reload timer

000086H TMCSR1 : L Timer control status register ch1 (lower)

000087H TMCSR1 : H Timer control status register ch1 (upper)

R/W

R

0 0 0 0 0 0 0 0B

XXXX 0 0 0 0B

XXXXXXXXB

TMR1

TMRLR1 16-bit reload register ch1 (lower)

TMR1 16-bit timer register ch1 (upper)

TMRHR1 16-bit reload register ch1 (upper)

16-bit timer register ch1 (lower)

000088H

000089H

W

R

W

XXXXXXXXB

(Continued)

24

MB90560/565 Series

Abbreviat-

Address ed Register

Name

Read/

Register name

Resource Name Initial Value

Write

00008A^H

to

Access prohibited

00008BH

00008C^H

00008DH

RDR0

RDR1

Port 0 pull-up resistor setting register

Port 1 pull-up resistor setting register

R/W

Port 0

Port 1

0 0 0 0 0 0 0 0B

00008EH

to

Access prohibited

00009DH

Program address detection

control status register

Address match

detection

00009E^H

00009FH

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0B

Delayed interrupt request/clear register

Delayed interrupt XXXXXXX 0B

Low power

0000A0H

LPMCR

CKSCR

Low power consumption mode register W, R/W

consumption

control circuit

0 0 0 1 1 0 0 0B

1 1 1 1 1 1 0 0B

0000A1H

Clock selection register

R, R/W

Access prohibited

Clock

0000A2H

to

0000A7H

0000A8^H

0000A9H

WDTC

TBTC

Watchdog control register

R/W

Watchdog timer 1 XXXX 1 1 1B

Timebase timer 1 XX 0 0 1 0 0B

Timebase timer control register

W, R/W

0000AAH

to

Access prohibited

0000ADH

R, W,

R/W

0000AE^H

0000AFH

FMCS

Flash memory control status register

Flash memory

0 0 0 0 0 0 0 0B

Access prohibited

Interrupt control register 00 (for writing) W, R/W

Interrupt control register 00 (for reading) R, R/W

Interrupt control register 01 (for writing) W, R/W

Interrupt control register 01 (for reading) R, R/W

Interrupt control register 02 (for writing) W, R/W

Interrupt control register 02 (for reading) R, R/W

Interrupt control register 03 (for writing) W, R/W

Interrupt control register 03 (for reading) R, R/W

Interrupt control register 04 (for writing) W, R/W

Interrupt control register 04 (for reading) R, R/W

Interrupt control register 05 (for writing) W, R/W

Interrupt control register 05 (for reading) R, R/W

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

0000B0^H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

Interrupts

XX 0 0 0 1 1 1B

(Continued)

25

MB90560/565 Series

Abbreviat-

Address ed Register

Name

Read/

Write

Register name

Resource Name Initial Value

Interrupt control register 06 (for writing) W, R/W

Interrupt control register 06 (for reading) R, R/W

Interrupt control register 07 (for writing) W, R/W

Interrupt control register 07 (for reading) R, R/W

Interrupt control register 08 (for writing) W, R/W

Interrupt control register 08 (for reading) R, R/W

Interrupt control register 09 (for writing) W, R/W

Interrupt control register 09 (for reading) R, R/W

Interrupt control register 10 (for writing) W, R/W

Interrupt control register 10 (for reading) R, R/W

Interrupt control register 11 (for writing) W, R/W

Interrupt control register 11 (for reading) R, R/W

Interrupt control register 12 (for writing) W, R/W

Interrupt control register 12 (for reading) R, R/W

Interrupt control register 13 (for writing) W, R/W

Interrupt control register 13 (for reading) R, R/W

Interrupt control register 14 (for writing) W, R/W

Interrupt control register 14 (for reading) R, R/W

Interrupt control register 15 (for writing) W, R/W

Interrupt control register 15 (for reading) R, R/W

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

0000B6^H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

XX 0 0 0 1 1 1B

Interrupts

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

XXXX 0 1 1 1^B

XX 0 0 0 1 1 1B

0000C0H

to

0000FFH

Unused area

RAM area

000100H

to

#H

#^H

to

Reserved area

001FEFH

Program address detection register ch0

(lower)

001FF0^H

001FF1H

001FF2H

R/W

XXXXXXXXB

Program address detection register ch0

(middle)

Address match

XXXXXXXXB

detection

PADR0

R/W

Program address detection register ch0

(lower)

R/W

XXXXXXXXB

(Continued)

26

MB90560/565 Series

(Continued)

Abbreviat-

Address ed Register

Name

Read/

Register name

Resource Name Initial Value

Write

Program address detection register ch1

(lower)

001FF3^H

R/W

XXXXXXXXB

Program address detection register ch1

(middle)

Address match

detection

001FF4H

001FF5H

PADR1

Program address detection register ch1

(lower)

001FF6H

to

Unused area

001FFFH

• Read/write notation

R/W : Reading and writing permitted

R

: Read-only

: Write-only

W

• Initial value notation

0

: Initial value is “0”.

1

: Initial value is “1”.

X

: Initial value is undefined.

27

MB90560/565 Series

■ INTERRUPTS, INTERRUT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt Control

Register

EI²OS

Sup-

port

Interrupt Vector

Priori-

ty

Interrupt

No.^*

Address

08^HFFFFDCH

09^HFFFFD8H

0AH FFFFD4H

ICR

Address

×

Reset

#08

#09

#10

#11

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

#39

#40

#41

#42

High

INT 9 instruction

Exception

A/D converter conversion complete

Output compare channel 0 match

8/16-bit PPG timer 0 counter borrow

Output compare channel 1 match

8/16-bit PPG timer 1 counter borrow

Output compare channel 2 match

8/16-bit PPG timer 2 counter borrow

Output compare channel 3 match

8/16-bit PPG timer 3 counter borrow

Output compare channel 4 match

8/16-bit PPG timer 4 counter borrow

Output compare channel 5 match

8/16-bit PPG timer 5 counter borrow

DTP/external interrupt channel 0/1 detection

DTP/external interrupt channel 2/3 detection

DTP/external interrupt channel 4/5 detection

DTP/external interrupt channel 6/7 detection

8-bit timer 0/1/2 counter borrow

16-bit reload timer 0 underflow

16-bit freerun timer overflow

16-bit reload timer 1 underflow

Input capture channel 0/1

0B^HFFFFD0H ICR00

0000B0H

0000B1H

0DH FFFFC8H

ICR01

0EH FFFFC4H

0FH

FFFFC0H

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

10H FFFFBCH

11H

12H

13H

FFFFB8H

FFFFB4H

FFFFB0H

14H FFFFACH

15H

16H

17H

18H

19H

1AH

1BH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

1CH FFFF8CH

×

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

FFFF60H

FFFF5CH

FFFF58H

FFFF54H

×

16-bit freerun timer clear

Input capture channel 2/3

Timebase timer

UART1 receive

UART1 send

UART0 receive

UART0 send

×

Flash memory status

Delay interrupt output module

Low

28

MB90560/565 Series

: Supported

×

: Not supported

: Supported, includes EI²OS stop function

: Available if the interrupt that shares the same ICR is not used.

* : If two or more interrupts with the same level occur simultaneously, the interrupt with the lower interrupt vector

number has priority

29

MB90560/565 Series

■ PERIPHERAL FUNCTIONS

1. I/O Ports

• The I/O ports can be used as general-purpose I/O ports (parallel I/O ports) . The MB90560/565 series have

7 ports (51 pins) . The ports share pins with the inputs and outputs of the peripheral functions.

• The port data registers (PDR) are used to output data to the I/O pins and read the data input from the I/O

ports. Similarly, the port direction registers (DDR) set the I/O direction (input or output) for each individual port

bit.

• The following table lists the I/O ports and the peripheral functions with which they share pins.

Pin Name (Port) Pin Name (Peripheral)

Peripheral Function that Shares Pin

Not shared

Port 0

Port 1

P00-P07

P10-P16

P17

INT0-INT6

FRCK

External interrupts

Freerun timer external input

P20-P23

P24-P27

P30-P35

P36, P37

P40

TIN0, TO0, TIN1, TO1 16-bit reload timer 0 and 1

Port 2

Port 3

IN0-IN3

RTO0-RTO5

SIN0, SOT0

SCK0

Input capture 0 to 3

Output compare

UART0

Port 4

Port 5

P41-P46

P50-P57

P60-P62

PPG0-PPG5

AN0-AN7

8/16-bit PPG timer

8/10-bit A/D converter

UART1

SIN1, SOT1, SCK1

INT7

Port 6

External interrupts

Waveform generator

P63

DTTI

Notes : • Pins P30 to P35 of port 3 can drive a maximum of I^OL= 12 mA.

• Port 5 shares pins with the analog inputs. When using port 5 pins as a general-purpose ports, ensure that

the corresponding analog input enable register (ADER) bits are set to “0B”. ADER is initialized to “FFH”

after a reset.

• Block diagram for port 0 and 1 pins

Pull-up resistor

setting register

(PDRx)

Internal

pull-up resistor

PDRx read

Input

Port data

register

(PDRx)

buffer

Input/output

selection circuit

Output

buffer

Port pin

PDRx

write

Port direction

register

Standby control (LPMCR : SPL = "1")

(DDRx)

30

MB90560/565 Series

• Block diagram for port 2, 3, 4, and 6 pins

Resource input

PDRx read

Input

Port data

register

(PDRx)

buffer

Input/output

selection circuit

Output

buffer

Port

PDRx

write

Port direction

register

Standby control (LPMCR : SPL = "1")

(DDRx)

Resource output control signal

Resource output

• Block diagram for port 5 pins

Analog input

enable register

(ADER)

Analog converter

analog input signal

PDR5 read

Input

Port data

register

(PDR5)

buffer

Input/output

selection circuit

Output

buffer

Port 5

PDR5

write

Port direction

register

(DDR5)

Standby control (LPMCR : SPL = "1")

Notes : • When using as an input port, set the corresponding bit in the port 5 direction register (DDR5) to “0” and

set the corresponding bit in the analog input enable register (ADER) to “0”.

• When using as an analog input pin, set the corresponding bit in the port 5 direction register (DDR5) to “0”

and set the corresponding bit in the analog input enable register (ADER) to “1”.

31

MB90560/565 Series

2. Timebase Timer

• The timebase timer is an 18-bit freerun timer (timebase timer/counter) that counts up synchronized with the

main clock (oscillation clock : HCLK divided into 2) .

• The timer can generate interrupt requests at a specified interval, with four different interval time settings

available.

• The timer supplies the operating clock for peripheral functions including the oscillation stabilization delay timer

and watchdog timer.

• Timebase timer interval settings

Internal Count Clock Period

Interval Time

2¹²/HCLK (approx. 1.024 ms)

2¹⁴/HCLK (approx. 4.096 ms)

2¹⁶/HCLK (approx. 16.384 ms)

2/HCLK (0.5 µs)

2¹⁹/HCLK (approx. 131.072 ms)

Notes : • HCLK : Oscillation clock frequency

• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.

• Period of clocks supplied from timebase timer

Peripheral Function

Clock Period

2¹⁰/HCLK (approx. 0.256 ms)

2¹³/HCLK (approx. 2.048 ms)

2¹⁵/HCLK (approx. 8.192 ms)

2¹⁷/HCLK (approx. 32.768 ms)

2¹²/HCLK (approx. 1.024 ms)

2¹⁴/HCLK (approx. 4.096 ms)

2¹⁶/HCLK (approx. 16.384 ms)

Oscillation stabilization delay for

the main clock

Watchdog timer

2¹⁹/HCLK (approx. 131.072 ms)

Notes : • HCLK : Oscillation clock frequency

• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.

32

MB90560/565 Series

• Block diagram

To watchdog timer

To PPG timer

Timebase timer/counter

HCLK

divided into 2

× 2¹× 2²× 2³

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

OF

To oscillation stabilization

delay time selector

in clock controller

Reset^*1

Clear stop mode, etc.^*2

Switch clock mode^*3

Counter

clear circuit

Interval

timer selector

TBOF clear

TBOF set

Timebase timer control register

(TBTC)

TBIE TBOF TBR TBC1 TBC0

Timebase timer interrupt signal

OF : Overflow

HCLK : Oscillation clock frequency

*1

*2

*3

: Power-on reset, watchdog reset

: Recovery from stop mode and timebase timer mode

: Main → PLL clock

The actual interrupt request number for the timebase timer is :

Interrupt request number : #36 (24^H)

33

MB90560/565 Series

3. Watchdog Timer

• The watchdog timer is a timer/counter used to detect faults such as program runaway.

• The watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer.

• Once started, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs,

the CPU is reset.

• Interval time for the watchdog timer

HCLK : Oscillation Clock (4 MHz)

Min.

Max.

Clock Period

Approx. 3.58 ms

Approx. 14.33 ms

Approx. 57.23 ms

Approx. 458.75 ms

Approx. 4.61 ms

Approx. 18.30 ms

Approx. 73.73 ms

Approx. 589.82 ms

2

¹⁴± 2¹¹/ HCLK

¹⁶± 2¹³/ HCLK

¹⁸± 2¹⁵/ HCLK

2

Notes: • Thedifferencebetweenthemaximumandminimumwatchdogtimerintervaltimesisduetothetimingwhen

the counter is cleared.

• As the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock

timer, clearing the timebase timer (when operating on HCLK) or the clock timer (when operating on SCLK)

lengthens the time until the watchdog timer reset is generated.

• Watchdog timer count clock

HCLK : Oscillation clock

WTC : WDCS

PCLK : PLL clock

“0”

“1”

Prohibited setting

Count the timebase timer output.

• Events that stop the watchdog timer

1 : Stop due to a power-on reset

2 : Watchdog reset

• Events that clear the watchdog timer

1 : External reset input from the RST pin.

2 : Writing “0” to the software reset bit.

3 : Writing “0” to the watchdog control bit (second and subsequent times) .

4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) .

5 : Changing to timebase timer mode (clears the watchdog timer and temporarily halts the count) .

6 : Changing to stop mode (clears the watchdog timer and temporarily halts the count) .

34

MB90560/565 Series

• Block diagram

Watchdog timer control register (WDTC)

PONR STBR WRST ERST SRST WTE WT1 WT0

2

Watchdog timer

Start

Reset

Watchdog timer

reset generation

circuit

Change to sleep mode

Counter clear

control circuit

Counter clock

selector

To internal

reset circuit

2-bit counter

Clear

Change to timebase

timer mode

Change to stop mode

4

(Timebase timer/counter)

× 2¹× 2²× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

Main clock

(HCLK divided into 2)

HCLK : Oscillation clock frequency

35

MB90560/565 Series

4. 16-Bit Reload Timers 0 and 1 (With Event Count Function)

• The 16-bit reload timers have the following functions.

• The count clock can be selected from three internal clocks or the external event clock.

• An interrupt to the CPU can be generated when an underflow occurs on 16-bit reload timer 0 or 1. This interrupt

allows the timers to be used as interval timers.

• Two different operation modes can be selected when an underflow occurs on 16-bit reload timer 0 or 1: one-

shot mode in which timer operation halts when an underflow occurs or reload mode in which the value in the

reload register is loaded into the timer and counting continues.

• Extended intelligent I/O service (EI²OS) is supported.

• The MB90560/565 series contains two 16-bit reload timer channels.

• 16-bit reload timer operation modes

Operation When an

Count Clock

Start Trigger

Underflow Occurs

One-shot mode

Reload mode

Software trigger

Internal clock

One-shot mode

Reload mode

External trigger

Software trigger

One-shot mode

Reload mode

Event count mode

(external clock mode)

• Interval times for the 16-bit reload timers

Count Clock

Count Clock Period

Example of Interval Times

0.125 µs to 8.192 ms

0.5 µs to 32.768 ms

2.0 µs to 131.1 ms

2¹/φ (0.125 µs)

2³/φ (0.5 µs)

2⁵/φ (2.0 µs)

2³/φ or longer

Internal clock

Event count mode

0.5 µs or longer

Note : The values enclosed in ( ) and the example of interval times is for a machine clock frequency of 16 MHz.

φ is the machine clock frequency value for the calculation.

Remarks : 16-bit reload timer 0 can be used to generate the baud rate for UART0.

16-bit reload timer 1 can be used to generate the baud rate for UART1 and activation trigger for the

A/D converter.

36

MB90560/565 Series

• Block diagram

Internal data bus

TMRLR0^*1

TMRLR1^*2

16-bit reload register

Reload signal

Reload

control circuit

TMR0^*1

TMR1^*2

*4

UF

16-bit timer register

CLK

Count clock generation circuit

Clock

pulse

detection

circuit

Gate input

Machine

clock φ

3

Wait signal

Prescaler

To UART0^*1

To UART1 and

A/D converter trigger^*2

Clear

trigger

Internal

clock

Output control circuit

CLK

Output signal

generation circuit

Input

control

circuit

Clock

selector

EN

TO0^*1

TO1^*2

TIN0^*1

TIN1^*2

External clock

Select

signal

3

2

Operation

control circuit

Function selection

CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR)

Interrupt

request output

#30 (1EH) ^{*1, *3}

#32 (20H) ^{*2, *3}

*1 : Channel 0

*2 : Channel 1

*3 : Interrupt number

*4 : Underflow

37

MB90560/565 Series

5. Multi-Function Timer

• Based on the 16-bit freerun timer, the multi-function timer can be used to generate 12 independent waveform

outputs and to measure input pulse widths and external clock periods.

• Structure of multi-function timer

16-bit

freerun timer

16-bit

output compare

16-bit

input capture

8/16-bit

PPG timer

Waveform

generator

8 bit × 6 ch

16 bit × 3 ch

1 ch

6 ch

4 ch

8-bit timer × 3 ch

• 16-bit freerun timer (1 channel)

The 16-bit freerun timer consists of a 16-bit up-counter (timer data register (TCDT) ) , compare clear register

(CPCLR) , timer control status register (TCCS) , and prescaler.

The count output value from the 16-bit freerun timer provides the base time for the input capture and output

compare functions.

• The count clock can be selected from the following eight clocks :

1/φ, 2/φ, 4/φ, 8/φ, 16/φ, 32/φ, 64/φ, 128/φ

φ : Machine clock frequency

• An interrupt can be generated when the 16-bit freerun timer overflows or when the 16-bit freerun timer count

is cleared to “0000^H” due to a match occurring between the value in the compare clear register (CPCLR) and

the count in the 16-bit freerun timer (TCCS : ICRE = “1”, MODE = “1”) .

• The 16-bit freerun timer is cleared to “0000^H” when a reset occurs, on setting the timer clear bit (SCLR) in the

timer control status register (TCCS) , when a compare match occurs between the 16-bit freerun timer count

and the value in the compare clear register (CPCLR) (TCCS : MODE = “1”) , or by writing “0000^H” to the timer

data register (TCDT) .

• Output compare (6 channels)

The output compare unit consists of compare registers (OCCP0 to OCCP5) , compare control registers (OCS0

to OCS5) , and compare output latches.

When a match occurs between a compare register (OCCP0 to OCCP5) value and the count from the 16-bit

freerun timer, the output compare can invert the level of the corresponding output compare pin and generate

an interrupt.

• The compare registers (OCCP0 to OCCP5) operate independently for each channel. Each of the compare

registers (OCCP0 to OCCP5) has a corresponding output pin and an interrupt request flag in the channel’s

compare control register (lower) (OCS0, OCS2, OCS4) .

• Two channels of the compare registers (OCCP0 to OCCP5) can be used to invert the output pins.

• An interrupt can be output when a match occurs between a compare register (OCCP0 to OCCP5) and the

count from the 16-bit freerun timer (OCS0, OCS2, OCS4 : IOP0 = “1”, IOP1 = “1”) . (OCS0, OCS2, OCS4 :

IOE0 = “1”, IOE1 = “1”)

• The initial output levels for the output compare pins can be set.

• Input capture (4 channels)

The input capture consists of external input pins (IN0 to IN3) , corresponding input capture data registers (IPCP0

to IPCP3) , and input capture control status registers (ICS01, ICS23) .

The input capture can transfer the count value from the 16-bit freerun timer to the input capture data register

(IPCP0 to IPCP3) and output an interrupt on detecting an active edge on the signal input from the external input

pin.

• Each channel of the input capture operates independently.

• The active edge (rising edge, falling edge, or either edge) on the external signal can be specified.

38

MB90560/565 Series

• An interrupt can be generated when an active edge is detected on the external signal (ICS01, ICS23 : ICE0

= “1”, ICE1 = “1”, ICE2 = “1”, ICE3 = “1”) .

• 8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels)

The 8/16-bit PPG timer consists of an 8-bit down counter (PCNT) , PPG control registers (PPGC0 to PPGC

5) , PPG clock control registers (PCS01, PCS23, PCS45) , and PPG reload registers (PRLL0 to PRLL5, PRLH0

to PRLH5) .

When used as an 8/16-bit reload timer, the PPG operates as an event timer. The PPG can also be used to output

pulses with specified frequency and duty ratio.

• 8-bit PPG mode

Each channel operates as an independent 8-bit PPG.

• 8-bit prescaler + 8-bit PPG mode

ch0 (ch2, ch4) operates as an 8-bit prescaler and ch1 (ch3, ch5) operates as a variable frequency PPG by

counting up on the borrow output from ch0 (ch2, ch4) .

• 16-bit PPG mode

ch0 (ch2, ch4) and ch1 (ch3, ch5) operate together as a 16-bit PPG.

• PPG operation

Outputs pulses with the specified frequency and duty ratio (ratio of “H” level period and “L” level period), and

can also be used as a D/A converter when combined with an external circuit.

• Waveform generator

The waveform generator consists of an 8-bit timer, 8-bit timer control registers (DTCR0 to DTCR2) , 8-bit reload

registers (TMRR0 to TMRR2) , and waveform control register (SIGCR) .

The waveform generator can generate a DC chopper output or non-overlapping three-phase waveform output

for inverter control using the realtime outputs (RT0 to RT5) and 8/16-bit PPG timer.

• A non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a non-

overlap time delay to the PPG timer pulse output. (Deadtime timer function)

• A non-overlapping waveform can be generated by using the 8-bit timer as a deadtime timer and adding a non-

overlap time delay to the realtime outputs (RT1, RT3, RT5) . (Deadtime timer function)

• A GATE signal can be generated when a match occurs between the count from the 16-bit freerun timer and

compare register in the output compare (OCCP0 to OCCP5) (rising edge on realtime output (RT) ) to control

the PPG timer operation. (GATE function)

• Can control the RTO0 to RTO5 pin outputs using the DTTI pin input.

By making the DTTI pin input clockless, the pins can be controlled externally even when the oscillation clock

is halted. (The level for each pin can be set by the program.) However, the I/O ports (P30 to P35) must have

been set beforehand as outputs and the output values set in the port 3 data register (PDR3) .

39

MB90560/565 Series

• Block diagram

• 16-bit freerun timer, input capture, and output compare

To interrupt

#31 (1FH)

φ

*

3

8

IVF

IVFE STOP MODE SCLR CLK2

16-bit freerun timer

CLK1 CLK0

Divider

Clock

16

To interrupt

#34 (22H)

16-bit compare clear register

Compare registers 0, 2, 4

Compare circuit

*

MS13 to 0

ICLR

ICRE

To A/D trigger

T

Q

Compare circuit

To RT0, 2, 4

waveform generator

16

4

Compare registers 1, 3, 5

CMOD

To RT1, 3, 5

waveform generator

T

Compare circuit

IOP1

IOP0

IOE1

IOE0

To interrupts

#13 (0DH) *, #17 (11H) *,

#21 (15H) *

#15 (0FH) *, #19 (13H) *,

#23 (17H) *

Capture registers 0, 2

Edge detection

IN0/2

4

EG11 EG10

EG01 EG00

IN1/3

Capture registers 1, 3

Edge detection

ICP0

ICP1

ICE0

ICE1

To interrupts

#33 (21H) *, #35 (23H) *

* : Interrupt number

φ : Machine clock frequency

40

MB90560/565 Series

• Block diagram of 8/16-bit PPG timer

PC02 PC01 PC00 POS0 OEN0 SST0 POE0

PIE0

PUF0

To interrupt

#14 (0EH) *

φ

Operation

control

Selector

Divider

GATE0/1

PCNT0

(Down counter)

To PPG0, 2, 4

Selector

Reload

Selector

ch1, 3, 5 borrow

L/H selector

PRLL0/2/4

PRLH0/2/4

PRLBH0/2/4

PC12 PC11 PC10 POS1 OEN1 SST1 POE1 PUF1 PIE1

To interrupt

#16 (10H) *

ch0, 2, 4 borrow

Selector

φ

Operation

control

Divider

GATE1

PCNT1

To PPG1, 3, 5

Selector

Reload

Selector

(Down counter)

L/H selector

PRLL1/3/5

PRLH1/3/5

PRLBH1/3/5

* : Interrupt number

φ : Machine clock frequency

41

MB90560/565 Series

• Block diagram of waveform generator

DCK2 DCK1

DCK0

TMD1 TMD0 NRSL

DTIL

DTIE

φ

DTTI control circuit

DTTI

Divider

Clock

To GATE0, 1 (To PPG timer)

TO0

RT0

Waveform

generator

TO1

RT1

RTO0/U

Selector

RTO1/X

Compare circuit

Selector

U

8-bit timer

Deadtime generation

X

8-bit timer register 0

To GATE2, 3 (To PPG timer)

TO2

Waveform

generator

RT2

TO3

RT3

RTO2/V

Selector

8-bit timer

Compare circuit

RTO3/Y

Selector

V

Deadtime generation

Y

8-bit timer register 1

To GATE4, 5 (To PPG timer)

TO4

Waveform

generator

RT4

TO5

RT5

RTO4/W

RTO5/Z

Selector

8-bit timer

Compare circuit

Selector

W

8-bit timer register 2

Deadtime generation

φ : Machine clock frequency

42

MB90560/565 Series

6. UART

(1) Overview

• The UART is a general-purpose serial communications interface for performing synchronous or asynchronous

(start-stop synchronization) communications with external devices.

• The interface provides both a bi-directional communication function (normal mode) and a master-slave com-

munication function (multi-processor mode) .

• The UART can generate interrupt requests at receive complete, receive error detected, and transmit complete

timings. Also the UART supports EI²OS.

• UART functions

The UART is a general-purpose serial communications interface for sending serial data to and from other CPUs

and peripheral devices.

Function

Data buffer

Full-duplex double-buffered

• Clock synchronous (no start and stop bits)

• Clock asynchronous (start-stop synchronization)

Transmission modes

• Max. 2 MHz (for a 16 MHz machine clock)

• Baud rate generated by dedicated baud rate generator

• Baud rate generated by external clock (clock input from SCK0 and SCK1 pins)

• Baud rate generated by internal clock (clock supplied from 16-bit reload timer)

• Eight different baud rate settings are available.

Baud rate

• 7 bits (asynchronous normal mode only)

• 8 bits

Number of data bits

Signal format

Non return to zero (NRZ) format

• Framing errors

Receive error detection

Interrupt requests

• Overrun errors

• Parity errors (not available in multi-processor mode)

• Receive interrupt (Receive complete or receive error detected)

• Transmit interrupt (Transmission complete)

• Both transmit and receive support the extended intelligent I/O service (EI²OS) .

Master/slave

communication function

(multi-processor mode)

Used for 1 (master) to n (slave) communications.

(Can only be used as master)

Note : The UART does not add the start and stop bits in clock synchronous mode. In this case, only data is

transmitted.

43

MB90560/565 Series

• UART operation modes

No. of Data Bits

No Parity With Parity

7 or 8 bits

Operation Mode

Synchronization

No. of Stop Bits

0

1

2

Normal mode

Asynchronous

Synchronous

1 or 2 bits^*2

None

Multi-processor mode

Clock synchronous mode

8 + 1^*1

8

: Not available

*1 : The “+1” represents the address/data (A/D) bit used for communication control.

*2 : Only 1 stop bit supported for receiving.

• UART interrupts and EI²OS

Interrupt Control

Vector Table Address

Register

Interrupt

No.

2

Interrupt

EI OS

Register

Name

Address

0000BDH

0000BEH

Lower

Upper

Bank

UART1

receive interrupt

#37 (25^H)

#38 (26H)

#39 (27H)

#40 (28H)

ICR13

FFFF68H

FFFF64H

FFFF60H

FFFF5CH

FFFF69H

FFFF65H

FFFF61H

FFFF5DH

FFFF6AH

FFFF66H

FFFF62H

FFFF5EH

UART1

send interrupt

ICR13

ICR14

UART0

receive interrupt

UART0

send interrupt

: The UART has a function to halt EI²OS if a receive error is detected.

: Available when the interrupt shared with ICR13 or ICR14 is not used.

44

MB90560/565 Series

(2) UART structure

The UART consists of the following 11 blocks:

• Clock selector

• Mode registers (SMR0, SMR1)

• Control registers (SCR0, SCR1)

• Status registers (SSR0, SSR1)

• Input data registers (SIDR0, SIDR1)

• Output data registers (SODR0, SODR1)

• Receive control circuit

• Transmission control circuit

• Receive status evaluation circuit

• Receive shift register

• Transmission shift register

• Block diagram

Control bus

Receive

interrupt signal

#39 (27H)*

<#37 (25H)*>

Dedicated baud

rate generator

Transmit clock

Clock

Transmit

16-bit reload timer

selector

interrupt signal

#40 (28H)*

<#38 (26H)*>

Receive

clock

Transmission

control circuit

Receive

control circuit

Start bit

detection circuit

Transmission

start circuit

P40/SCK0

Receive bit

counter

Transmit bit

counter

Receive parity

counter

Transmit parity

counter

P37/SOT0

Receive

shift register

Transmission

shift register

P36/SIN0

Receive

Transmission start

complete

SIDR0/SIDR1

SODR0/SODR1

Receive status

evaluation circuit

Receive error detection

signal for EI²OS

(to CPU)

Internal data bus

MD1

MD0

CS2

CS1

CS0

PEN

P

PE

ORE

FRE

RDRF

TDRE

BDS

RIE

SBL

CL

A/D

REC

RXE

TXE

SMR0/SMR1

SCR0/SCR1

SSR0/SSR1

SCKE

SOE

TIE

* : Interrupt number

45

MB90560/565 Series

• Clock selector

Selects the send/receive clock from either the dedicated baud rate generator, external input clock (clock input

to SCK0 or SCK1 pin) , or internal clock (clock supplied by 16-bit reload timer) .

• Receive control circuit

The receive control circuit consists of a receive bit counter, start bit detection circuit, and receive parity counter.

The receive bit counter counts the received data bits and outputs a receive interrupt request when the required

number of data bits have been received. The start bit detection circuit detects the start bit on the serial input

signal. On detecting a start bit, the receive data is shifted to the input data register (SIDR0 or SIDR1) in

accordance with the specified transfer speed. The receive parity counter calculates the parity of the received

data if parity is selected.

• Transmission control circuit

The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission

parity counter. The transmission bit counter counts the transmitted data bits and outputs a transmit interrupt

request when the required number of data bits have been sent. The transmission start circuit starts transmission

when data is written to the output data register (SODR0 or SODR1) . The transmission parity counter generates

the parity bit for the transmitted data when parity is selected.

• Receive shift register

The receive shift register captures the data input from the SIN0 or SIN1 pin by shifting one bit at a time then

transfers the received data to the input data register (SIDR0 or SIDR1) when reception completes.

• Transmission shift register

The transmission data is transferred from the output data register (SODR0 or SODR1) to the transmission shift

register and output from the SOT0 or SOT1 pin by shifting one bit at a time.

• Mode register (SMR0, SMR1)

Set the operation mode, baud rate clock and serial clock input/output control, and enables output for the

serial data pin.

• Control register (SCR0, SCR1)

Specifies whether to use parity, the type of parity, number of stop bits and data bits and the frame data format

for operation mode 1, to clear the receive error flag bit, and to enable or disable send and receive operation.

• Status register (SSR0, SSR1)

Stores the send/receive and error status information, set the serial data transfer direction, and enables or disables

the send and receive interrupt requests.

• Input data register (SIDR0, SIDR1)

Stores the received data.

• Output data register (SODR0, SODR1)

Set the transmission data. The data set in the output data register is converted to serial format and output.

46

MB90560/565 Series

7. DTP/External Interrupt Circuit

(1) Overview of the DTP/external interrupt circuit

The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input to the external

interrupt input pins (INT7 to INT0) and outputs interrupt requests.

• DTP/external interrupt circuit functions

The DTP/external interrupt function detects edge or level signals input to the external interrupt input pins (INT7

to INT0) and outputs interrupt requests.

The interrupt request is received by the CPU and, if the extended intelligent I/O service (EI²OS) is enabled,

EI²OS performs automatic data transfer (DTP function) then passes control to the interrupt handler routine on

completion. If EI²OS is disabled, control passes directly to the interrupt handler routine without performing

automatic data transfer (DTP function) .

• Overview of the DTP/external interrupt circuit

External Interrupt

DTP Function

Input pins

8 channels (P10/INT0 to P16/INT6, P63/INT7)

The level or edge to detect can be set independently for each pin in the detection lev-

el setup register (ELVR) .

Interrupt conditions

“L” level, “H” level, rising edge, or falling edge input

#25 (19^H) to #28 (1CH)

Interrupt number

Interrupt control

Interrupts can be enabled or disabled in the DTP/external interrupt enable register

(ENIR) .

Interrupt flag

The DTP/external interrupt request register (ENRR) stores interrupt requests.

Processing selection

Set EI²OS to disabled (ICR : ISE = 0)

Set EI²OS to enabled (ICR : ISE = 1)

Jumps to interrupt handler routine after

automatic data transfer by EI²OS com-

pletes.

Operation

Jumps to interrupt handler routine

ICR : Interrupt control register

• DTP/external interrupt circuit interrupts and EI²OS

Interrupt Control Register

Interrupt

Vector Table Address

2

Channel

No.

EI OS

RegisterName

Address

Lower

Upper

Bank

INT0/INT1

INT2/INT3

INT4/INT5

INT6/INT7

#25 (19^H)

#26 (1AH)

#27 (1BH)

#28 (1CH)

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF99H

FFFF95H

FFFF91H

FFFF8DH

FFFF9AH

FFFF96H

FFFF92H

FFFF8EH

ICR07

0000B7^H

ICR08

0000B8^H

: Available when the interrupt shared with ICR07 or ICR08 is not used.

47

MB90560/565 Series

(2) Structure of the DTP/external interrupt circuit

The DTP/external interrupt circuit consists of the following four blocks :

• DTP/interrupt detection circuit

• DTP/interrupt request register (EIRR)

• DTP/interrupt enable register (ENIR)

• Request level setting register (ELVR)

• Block diagram

Request level setting register (ELVR)

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2

DTP/external interrupt input detection circuit

Selector

P63/INT7

P10/INT0

Selector

P16/INT6

P11/INT1

Selector

P15/INT5

P12/INT2

Selector

P14/INT4

P13/INT3

DTP/interrupt

request register

(EIRR)

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

Interrupt request signal

#25 (19H)*

#26 (1AH)*

#27 (1BH)*

#28 (1CH)*

DTP/interrupt

enable register

(ENIR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

* : Interrupt number

48

MB90560/565 Series

8. Delayed Interrupt Generation Module

• The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this

hardware interrupt can be specified by software.

• Delayed interrupt generation module functions

Function and Control

• Writing “1” to bit R0 of the delayed interrupt request generation/clear register

(DIRR : R0 = 1) generates an interrupt request.

• Writing “0” to bit R0 of the delayed interrupt request generation/clear register

Interrupt trigger

(DIRR : R0 = 1) clears the interrupt request.

Interrupt control

Interrupt flag

• No enable/disable register is provided for this interrupt.

• Set in bit R0 of the delayed interrupt request generation/clear register

(DIRR : R0) .

EI²OS support

• Not supported by the extended intelligent I/O service (EI²OS) .

• Block diagram

Internal data bus

R0

S

R

Interrupt

request signal

Interrupt request

latch

Delayed interrupt request generation/

clear register (DIRR)

: Undefined

49

MB90560/565 Series

9. 8/10-Bit A/D Converter

• Overview of the 8/10-bit A/D converter

• The 8/10-bit A/D converter uses RC successive approximation to convert analog input voltages to an 8-bit or

10-bit digital value.

• The input signals can be selected from the eight analog input pin channels.

• 8/10-bit A/D converter functions

The minimum conversion time is 6.13 µs (for a 16 MHz machine clock, including sampling

A/D conversion time time) .

The minimum sampling time is 2.0 µs (for a 16 MHz machine clock)

Conversion method RC successive approximation with sample & hold circuit

Resolution

8-bit or 10-bit, selectable

Analog input pins Eight analog input pin channels are available. The input pin can be selected by the program.

An interrupt request can be generated and EI²OS invoked when A/D conversion completes.

Interrupts

The conversion data protection function operates when A/D conversion is performed with

the interrupt enabled.

A/D conversion

start trigger

The conversion start trigger can be set from the following options : software, output of 16-

bit reload timer 1 (rising edge) , or zero detection edge from 16-bit freerun timer.

EI²OS support

Supported by the extended intelligent I/O service (EI²OS) .

• 8/10-bit A/D converter conversion modes

Conversion Mode

Single Conversion Mode Operation Scan Conversion Mode Operation

Sequentially performs one conversion

for multiple channels (up to 8 channels

can be set) , then halts.

Single-shot conversion mode 1 Performs one conversion for the spec-

Single-shot conversion mode 2 ified channel (1 channel) then halts.

Performs repeated conversions for the

specified channels (up to 8 channels

can be set) .

Performs repeated conversions for the

Continuous conversion mode

specified channel (1 channel) .

Sequentially performs one conversion

for multiple channels (up to 8 channels

can be set) , then halts and waits for

the next activation.

Performs one conversion for the spec-

Incremental conversion mode ified channel (1 channel) then halts

and waits for the next activation.

• 8/10-bit A/D converter interrupts and EI²OS

Interrupt Control Register

Vector Table Address

2

Interrupt No.

EI OS

Register Name

Address

Lower

Upper

Bank

#11 (0B^H)

: Available

ICR00

0000B0H

FFFFD0H

FFFFD1H

FFFFD2H

50

MB90560/565 Series

• Block diagram

Interrupt request signal #11 (0BH) *

Rese-

A/D control status register

(ADCS0, ADCS1)

BUSY INT INTE PAUS STS1 STS0 STRT

MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

rved

6

2

16-bit reload timer 1 output

Decoder

Clock selector

16-bit freerun timer zero-detect

φ

Comparator

Sample &

P57/AN7

P56/AN6

P55/AN5

P54/AN4

P53/AN3

P52/AN2

P51/AN1

P50/AN0

Control circuit

hold circuit

Analog

channel

selector

2

AVR

AVCC

AVSS

D/A converter

A/D data register

(ADCR0, ADCS1)

S10 ST1 ST0 CT1 CT0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

φ : Machine clock

* : Interrupt number

51

MB90560/565 Series

10. ROM Mirror Function Selection Module

• The ROM mirror function selection module enables ROM data in FF bank to be read by accessing 00 bank.

• ROM mirror function selection module functions

Function

• Data in FFFFFF^Hto FF4000H in FF bank can be read from 00FFFFH to 004000H

Mirror setting address

in 00 bank.

Interrupts

• None

EI²OS support

• Not supported by the extended intelligent I/O service (EI²OS) .

• Relationship between addresses in the ROM mirror function

FE0000H

FE8000H

FEFFFFH

ROM area in MB90568 and MB90F568

ROM area in MB90567

FF0000H

FF4000H

ROM area in MB90562/A and MB90F562/B

FF bank

FF8000H

FFFFFFH

Mirrored ROM

data area

ROM area in MB90561/A

• Block diagram

ROM mirror function selection register (ROMM)

MI

Address

Address space

FF bank

00 bank

Data

ROM

52

MB90560/565 Series

11. Low Power Consumption (Standby) Modes

• The power consumption of F²MC-16LX devices can be reduced by various settings that control the operating

clock selection.

• Functions of each CPU operation mode

CPU Operation

Clock

Operation

Mode

Function

The CPU and peripheral functions operate using the oscillation clock (HCLK)

multiplied by the PLL circuit.

Normal Run

Sleep

The peripheral functions only operate using the oscillation clock (HCLK) mul-

tiplied by the PLL circuit.

PLL clock

The timebase timer only operates using the oscillation clock (HCLK) multi-

plied by the PLL circuit.

Pseudo-clock

Stop

The oscillation clock is stopped and the CPU and peripherals halt operation.

The CPU and peripheral functions operate using the oscillation clock (HCLK)

divided into 2.

Normal Run

Main clock

The peripheral functions only operate using the oscillation clock (HCLK) di-

vided into 2.

Sleep

Stop

The oscillation clock is stopped and the CPU and peripherals halt operation.

CPU intermittent

operation

The oscillation clock (HCLK) divided into 2 operates intermittently for fixed

time intervals.

Normal Run

53

MB90560/565 Series

12. 512 Kbit Flash Memory

• This section describes the flash memory on the MB90F562/B and does not apply to evaluation and mask ROM

versions.

• The flash memory is located in bank FF in the CPU memory map.

• Flash memory functions

Function

Memory size

• 512 Kbit (64 KBytes)

Memory configuration

Sector configuration

Sector protect function

• 64 KWords × 8 bits or 32 KWords × 16 bits

• 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes

• Selectable for each sector

• Automatic programming algorithm (Embedded Algorithm^*: Equivalent to

MBM29F400TA)

Programming algorithm

• Compatible with JEDEC standard commands

• Includes an erase pause and restart function

• Write/erase completion detection by data polling or toggle bit

• Erasing by sector available (sectors can be combined in any combination)

Operation commands

No. of write/erase cycles

• Min. 10,000 guaranteed

• Can be written and erased using a parallel writer

(Ando Denki AF9704, AF9705, AF9706, AF9708, and AF9709)

• Can be written and erased using a dedicated serial writer

(Yokogawa Digital Computer Corporation AF200, AF210, AF120, and AF110)

• Can be written and erased by the program

Memory write/erase method

Interrupts

• Write and erase completion interrupts

EI²OS support

• Not supported by the extended intelligent I/O service (EI²OS) .

* : Embedded Algorithm is a trademark of Advanced Micro Devices.

• Sector configuration of flash memory

Flash memory

SA1 (32 Kbyte)

CPU address

Writer address*

FF0000H

FF7FFFH

FF8000H

FF9FFFH

FFA000H

FFBFFFH

FFC000H

FEFFFFH

70000H

77FFFH

78000H

79FFFH

7A000H

7BFFFH

7C000H

7FFFFH

SA2 (8 Kbyte)

SA3 (8 Kbyte)

SA4 (16 Kbyte)

* : The writer address is the address to be used instead of the CPU address when writing data from a parallel

flash memory writer. Use the writer address when programming or erasing with a general-purpose parallel

writer.

54

MB90560/565 Series

13. 1 Mbit Flash Memory

• This section describes the flash memory on the MB90F568 and does not apply to evaluation and mask ROM

versions.

• The flash memory is located in banks FE to FF in the CPU memory map.

• Flash memory functions

Function

Memory size

• 1 Mbit (128 KBytes)

Memory configuration

Sector configuration

Sector protect function

• 128 KWords × 8 bits or 64 KWords × 16 bits

• 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes + 64 KBytes

• Selectable for each sector

• Automatic programming algorithm (Embedded Algorithm* : Equivalent to

MBM29F400TA)

Programming algorithm

• Compatible with JEDEC standard commands

• Includes an erase pause and restart function

• Write/erase completion detection by data polling or toggle bit

• Erasing by sector available (sectors can be combined in any combination)

Operation commands

No. of write/erase cycles

• Min. 10,000 guaranteed

• Can be written and erased using a parallel writer

(Ando Denki AF9704, AF9705, AF9706, AF9708, and AF9709)

• Can be written and erased using a dedicated serial writer

(Yokogawa Digital Computer Corporation AF200, AF210, AF120, and AF110)

• Can be written and erased by the program

Memory write/erase method

Interrupts

• Write and erase completion interrupts

EI²OS support

• Not supported by the extended intelligent I/O service (EI²OS) .

* : Embedded Algorithm is a trademark of Advanced Micro Devices.

• Sector configuration of flash memory

Flash memory

SA0 (64 Kbyte)

CPU address

Writer address*

FE0000H

FEFFFH

60000H

6FFFFH

70000H

77FFFH

78000H

79FFFH

7A000H

7BFFFH

7C000H

7FFFFH

FF0000H

FF7FFFH

FF8000H

FF9FFFH

FFA000H

FFBFFFH

FFC000H

FEFFFFH

SA1 (32 Kbyte)

SA2 (8 Kbyte)

SA3 (8 Kbyte)

SA4 (16 Kbyte)

* : The writer address is the address to be used instead of the CPU address when writing data from a parallel

flash memory writer. Use the writer address when programming or erasing with a general-purpose parallel

writer.

55

MB90560/565 Series

• Standard configuration for Fujitsu standard serial on-board programming

Fujitsu standard serial on-board programming uses a flash microcontroller writer from Yokogawa Digital Com-

puter Corporation (AF220, AF210, AF120, or AF210) .

Host interface cable (AZ201)

General-purpose cable (AZ221)

Flash

microcontroller

Clock synchronous

serial

RS232C

MB90F562/F562B/F568

user system

writer

+

memory card

Can operate standalone

Note : Contact Yokogawa Digital Computer Corporation for details of the functions and operation of the flash

microcontroller writer (AF220, AF210, AF120, or AF110) , standard connection cable (AZ221) , and connec-

tors.

• Pins used for Fujitsu standard serial on-board programming

Symbol

Pin name

Function

MD2,

Setting MD2 = 1, MD1 = 1, and MD0 = 0 selects serial programming

mode.

Mode input pins

MD1, MD0

X0, X1

As flash memory serial programming mode uses the PLL clock with the

multiplier set to 1 as the internal CPU operation clock, the internal op-

eration clock frequency is the same as the oscillation clock frequency.

Accordingly, the frequency that can be input to the high speed oscilla-

tion input pin when performing serial programming is between 1 MHz

and 16 MHz.

Oscillation input pin

Write program activation

pins

P00, P01

Input P00 = “L” level and P01 = “H” level.

RST

Reset input pin

SIN1

SOT1

SCK0

Serial data input pin

Serial data output pin

Serial clock input pin

Uses UART0 and UART1 in clock synchronous mode. In programming

mode, the pins used by UART0 in clock synchronous mode are SIN1,

SOT1, and SCK0.

Capacitor/power supply in- Capacitor pin for power supply stabilization. Connect an external ce-

C

put pin

ramic capacitor of approx. 0.1 µF.

If the user system provides the programming voltage (MB90F562 :

5 V ± 10%, MB90F568 : 3 V ± 10%) , these do not need to be connected

to the flash microcontroller writer.

V^CC

V^SS

Power supply input pins

GND pin

Connect to common GND with the flash microcontroller writer.

56

MB90560/565 Series

The control circuit shown in the figure is required when the P00, P01, SIN1, SOT1, and SCK0 pins are used on

the user system. Use the /TICS signal from the flash microcontroller writer to disconnect the user circuit during

serial on-board programming.

AF220/AF210/AF120/AF110

write control pin

MB90F562/F562B/F568

write control pin

10 kΩ

AF220/AF210/AF120/AF110

/TICS pin

User

Control circuit

Use the formula below to calculate the serial clock frequency able to be input to the MB90F562/F562B/F568.

Set up the flash microcontroller writer to use a serial clock input frequency that is permitted for the oscillation

clock frequency you are using.

Permitted input serial clock frequency = 0.125 × oscillation clock frequency

• Maximum serial clock frequency

Oscillation

Clock

Frequency

Maximum Serial Clock

Frequency that can be Input Frequency that can be Set on FrequencythatcanbeSeton

to Microcontroller

500 kHz

the AF220/AF210/AF120/AF110

the AF200

500 kHz

4 MHz

8 MHz

16 MHz

500 kHz

850 kHz

1.25 MHz

1 MHz

2 MHz

• System configuration of flash microcontroller writer (AF220/AF210/AF120/AF110) (Supplier : Yokoga-

wa Digital Computer Corporation)

Model

Function

AF200/AC4P

AF210/AC4P

AF120/AC4P

AF110/AC4P

Internal Ethernet interface model

Standard model

/100 V to 220 V power adapter

Unit

Single key, Internal Ethernet interface model

Single key model

AZ221

AZ210

FF201

AZ290

Special RS232C cable for connecting writer to PC/AT

Standard target probe (a) Length : 1 m

Control module for Fujitsu F²MC-16LX flash microcontrollers

Remote controller

Power supply regulator (MB90F568 : Required to supply 3 V versions from the flash

microcontroller writer.)

AZ264

/P2

/P4

2 MB PC card (option) Supports FLASH memory sizes up to 128 KB

4 MB PC card (option) Supports FLASH memory sizes up to 512 KB

Contact : Yokogawa Digital Computer Corporation Tel : 042-333-6224

Note : The AF200 flash microcontroller writer is an obsolete model but can still be used with the FF201 control

module.

57

MB90560/565 Series

■ ELECTRICAL CHARACTERISTICS (MB90560 SERIES)

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Rating

Parameter

Symbol

Unit

Remarks

Min.

Max.

VSS + 6.0

15

V^CC

AV^CC

AVR

VI

VSS − 0.3

V

*1

Power supply voltage

VCC ≥ AVCC

AVCC ≥ AVR ≥ 0 V ^*1

Input voltage

*2

Output voltage

V^O

I^OL1

mA *3, *4

mA *3, *5

“L” level maximum output

current

I^OL2

20

Average value

IOLAV1

IOLAV2

ΣIOL

4

12

mA

(operating current × operating ratio) ^*4

“L” level average output

current

Average value

(operating current × operating ratio) ^*5

“L” level total maximum

output current

100

50

“L” level total average

output current

Average value

(operating current × operating ratio)

ΣI^OLAV

I^OH

“H”levelmaximumoutput

current

−15

−4

mA *3

“H” level average output

current

Average value

(operating current × operating ratio)

IOHAV

ΣI^OH

mA

“H” level total maximum

output current

−100

−50

“H” level total average

output current

Average value

(operating current × operating ratio)

ΣI^OHAV

Power consumption

Operating temperature

Storage temperature

Pd

T^A

300

+85

mW

°C

−40

−55

Tstg

+150

°C

*1 : AV^CCand AVR must not exceed VCC. Also, AVR must not exceed AVCC.

*2 : VI and VO must not exceed VCC + 0.3 V.

*3 : The maximum output current is the peak value for a single pin.

*4 : Pins other than P30/RTO0 to P35/RTO5

*5 : P30/RTO0 to P35/RTO5 pins

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

58

MB90560/565 Series

2. Recommended Operating Conditions

Value

(VSS = AVSS = 0.0 V)

Parameter

Symbol

Unit

Remarks

Min.

Max.

Normal operation (MB90562, 562A, 561,

561A, and V560)

3.0

5.5

V

V^CC

Power supply voltage

4.5

5.5

V

Normal operation (MB90F562 and F562B)

Maintaining state in stop mode

CMOS input pin

V^CC

VIH

3.0

5.5

0.7 VCC

0.8 VCC

VCC − 0.3

VSS − 0.3

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

Input “H” voltage

Input “L” voltage

VIHS

V^IHM

VIL

CMOS hysteresis input pin

MD input pin

CMOS input pin

V^ILS

VILM

CMOS hysteresis input pin

MD input pin

Use a ceramic capacitor or other capacitor

with equivalent frequency characteristics.

The capacitance of the smoothing capacitor

connected to the V^CCpin must be greater

than CS.

Smoothing capacitor

C^S

T^A

0.1

1.0

µF

°C

Operating

temperature

−40

+85

• C pin diagram

C

C^S

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

59

MB90560/565 Series

3. DC Characteristics

Sym-

(TA = −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Parameter

Pin Name

Condition

Unit

Remarks

bol

Min.

Typ. Max.

Output “H”

voltage

All output

pins

VCC = 4.5 V

IOH = −2.0 mA

V^OH

VCC − 0.5

V

Pins other

than P30/ VCC = 4.5 V

V^OL1

0.4

V

RTO0 to

IOL1 = 2.0 mA

Output “L”

voltage

P35/RTO5

P30/RTO0

V^OL2to P35/

RTO5

VCC = 4.5 V

IOL2 = 12.0 mA

0.8

5

Input leak

current

All output

VCC = 5.5 V

I^IL

−5

µA

pins

VSS < VI < VCC

MB90562/A,

MB90561/A

For VCC = 5 V,

internalfrequency= 16MHz,

normal operation

50

40

55

80

50

85

mA

mA MB90F562/B

ICC

MB90562/A,

mA

For V^CC= 5 V,

internal frequency = 16 MHz,

A/D operation in progress

MB90561/A

Powersupply

current^*

VCC

45

55

60

mA MB90F562/B

Flash write or erase

For VCC = 5 V,

internalfrequency= 16MHz,

sleep mode

MB90562/A,

mA MB90561/A

MB90F562/B^*

I^CCS

15

5

20

ICCH

Stop mode, TA = 25 °C

µA

Other than

AVCC,

Input

capacitance

C^IN

AVSS, C,

VCC, and

VSS

10

80

pF

P00 to P07

P10 to P17

RST, MD0,

MD1

Pull-up

resistor

R^UP

15

30

100

kΩ

Pull-down

resistor

RDOWN MD2

* : Value when low power mode bits (LPM0, 1) is set to “01” with an internal operating frequency of 4 MHz.

Note : Current values are provisional and are subject to change without notice to allow for improvements to the

characteristics. The power supply current is measured with an external clock.

60

MB90560/565 Series

4. AC Characteristics

(1) Clock Timings

(T^A= −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Sym

bol

Condi-

tion

Parameter

Clock frequency

Clock cycle time

Pin Name

X0, X1

Unit

MHz

ns

Remarks

Min.

3

Typ.

Max.

16

With a PLL circuit

Without a PLL circuit

With a PLL circuit

Without a PLL circuit

fC

1

16

62.5

333

1000

tHCYL

X0, X1

P^WH

PWL

Recommended duty

ratio = 30% to 70%

Input clock pulse width

Input clock rise/fall time

X0

10

ns

tcr

tcf

When using an

external clock

5

Internal operating clock

frequency

When using a main

clock

f^CP

1.5

16

MHz

ns

Internal operating clock

cycle time

When using a main

clock

tCP

62.5

333

• X0 and X1 clock timing

tHCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcr

tcf

61

MB90560/565 Series

• PLL guaranteed operation range

Relationship between internal operating clock frequency and power supply voltage

Guaranteed operation range

for MB90F562/B

PLL guaranteed operation range

5.5

4.5

PLL guaranteed

operation range

A/D converter guaranteed

operation range

3.3

3.0

Guaranteed operation range

for MB90561/A and MB90562/A

Guaranteed operation range for MB90V560

1

3

8

12

16

Internal Clock fCP (MHz)

Relationship between oscillation frequency and internal operating clock frequency

×4 ×3

×2

×1

16

12

8

No multiplier

4

3

2

0.5

1

2

3

4

6

8

12

16

Source Oscillation Clock fC (MHz)

The AC ratings are specified for the following measurement reference voltages.

• Input signal waveform

• Output signal waveform

Hysteresis input pin

Output pin

0.8 VCC

2.4 V

0.2 VCC

0.8 V

Pins other than hysteresis input or MD input pins

0.7 VCC

0.3 VCC

62

MB90560/565 Series

(2)Reset

(T^A= −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol Pin Name Condition

Unit

Remarks

Min.

Max.

In normal

operation

16 t^CP

ns

Reset input time

t^RSTH

RST

Oscillator oscillation

ms In stop mode

time* + 16 t^CP

*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several

dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms.

• In normal operation

tRSTL

RST

0.2 VCC

• In stop mode

t

RSTL

RST

0.2Vcc

90 % of

amplitude

X0

Internal

operation

clock

Oscillator

oscillation time

16 tcp

Oscillator stabilization wait time

Execution of the instruction

Internal

reset

63

MB90560/565 Series

(3) Power-On Reset

(T^A= −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Condi-

tion

Parameter

Symbol Pin Name

Unit

Remarks

Min.

0.05

4

Max.

Power supply rise time

Power supply cutoff time

t^R

VCC

30

ms

t^OFF

ms For repeated operation

* : V^CCmust be less than 0.2 V before power-on.

Notes : • The above rating values are for generating a power-on reset.

• Some internal registers are only initialized by a power-on reset. Always apply the power supply in

accordance with the above ratings if you wish to initialize these registers.

tR

2.7 V

0.2 V

VCC

0.2 V

tOFF

Sudden changes in the power supply voltage may cause a power-on reset.

The recommended practice if you wish to change the power supply voltage while the device is

operating is to raise the voltage smoothly as shown below. Also, changes to the supply voltage

should be performed when the PLL clock is not in use. The PLL clock may be used, however, if

the rate of voltage change is 1 V/s or less.

VCC

Recommended rate of voltage

rise is 50 mV/ms or less.

3.0 V

Maintain RAM data

VSS

64

MB90560/565 Series

(4) UART0, UART1, and I/O Expansion Serial Timings

(T^A= −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol Pin Name

Condition

Unit Remarks

Min.

Max.

Serial clock cycle time

t^SCYC

t^SLOV

SCK0, SCK1

8 t^CP

ns

SCK ↓ → SOT delay

time

SCK0, SCK1

SOT0, SOT1

−80

100

60

80

Internal shift clock

mode, output pin load is

CL = 80 pF + 1 TTL

SCK0, SCK1

SIN0, SIN1

Valid SIN → SCK ↑

t^IVSH

tSHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

ns

SCK ↑ → valid

SIN hold time

SCK0, SCK1

SIN0, SIN1

Serial clock “H” pulse

width

SCK0, SCK1

4 t^CP

4 tCP

Serial clock “L” pulse

width

External shift clock

mode, output pin load is

CL = 80 pF + 1 TTL

SCK ↓ → SOT delay

time

SCK0, SCK1

SOT0, SOT1

150

SCK0, SCK1

SIN0, SIN1

Valid SIN → SCK ↑

60

SCK ↑ → valid

SIN hold time

SCK0, SCK1

SIN0, SIN1

Notes : • These are the AC ratings for CLK synchronous mode.

• C^Lis the load capacitor connected to the pin for testing.

• tCP is the machine cycle period (unit = ns)

65

MB90560/565 Series

• Internal shift clock mode

tSCYC

SCK

0.8 V

tSLOV

2.4 V

0.8 V

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SIN

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SIN

66

MB90560/565 Series

(5) Timer Input Timings

(T^A= −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Condi-

tion

Parameter

Symbol

Pin Name

Unit

Remarks

Min.

Max.

Input pulse width t^TIWH, tTIWL FRCK, IN0, IN1, TIN0, TIN1

4 tCP

ns

0.8 VCC

0.2 VCC

tTIWH

tTIWL

(6) Timer Output Timings

(T^A= −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Condi-

tion

Parameter

Symbol

Pin Name

Unit Remarks

Min. Max.

RTO0 to RTO5,

PPG0 to PPG5, TO0 to TO1

CLK ↑ → T^OUTchange time

tTO

30

ns

2.4 V

CLK

tTO

2.4 V

0.8 V

TOUT

(7) Trigger Input Timings

(T^A= −40 °C to +85 °C, VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Pin Name

Condition

Unit

Remarks

Min.

5 t^CP

1

Max.

In normal

operation

ns

Input pulse width

t^TRGL

INT0 to INT7, IN0 to IN3

µs In stop mode

0.8 VCC

0.2 VCC

tTRGH

tTRGL

67

MB90560/565 Series

5. Electrical Characteristics for the A/D Converter

(TA = −40 °C to +85 °C, 3.0 V ≤ AVR, VCC = AVCC = 5.0 V ±10%, VSS = AVSS = 0.0 V)

Value

Typ.

10

Parameter

Resolution

Symbol Pin Name

Unit

Remarks

Min.

Max.

bit

Total error

±5.0

±2.5

±1.9

LSB

Non-linearity error

Differential linearity error

AVSS

−3.5 LSB

AVSS

+4.5 LSB

Zero transition voltage

V^OT

AN0 to AN7

+0.5

mV

1 LSB = AVRH/1024

Full-scale transition

voltage

AVR

V^FST

−6.5 LSB −1.5 LSB +1.5 LSB

Conversion time

Sampling time

176 t^CP

64 t^CP

ns

Analog port input

current

IAIN

AN0 to AN7

10

µA

Analog input voltage

Reference voltage

V^AIN

AN0 to AN7

AVR

0

AVR

AV^CC

V

2.7

I^A

IAH

I^R

AVCC

5

mA

µA

Power supply current

AVCC

5

*

AVR

400

Reference voltage

supply current

IRH

AVR

5

4

Variation between

channels

AN0 to AN7

LSB

* : Current when A/D converter is not used and CPU is in stop mode (V^CC= AVCC = AVR = 5.0 V)

Notes : • The L reference voltage is fixed to AVSS. The relative error increases as AVR becomes smaller.

• Ensure that the output impedance of the external circuit connected to the analog input meets the following

condition :

Output impedance of external circuit ≤ 10 kΩ (Sampling Time = 4.0 µs)

• If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short.

• Equivalent circuit of analog input circuit

RON

C

Comparator

Analog input

MB90561/A, MB90562/A

RON = 2.2 kΩ approx.

C = 45 pF approx.

MB90F562

RON = 3.2 kΩ approx.

C = 30 pF approx.

MB90F562/B

RON = 2.6 kΩ approx.

C = 28 pF approx.

Note : The values listed are an indication only.

68

MB90560/565 Series

6. Flash Memory Erase and Programming Performance

Value

Parameter

Condition

Units

Remarks

Min

Typ

Max

Excludes 00H programming prior

erasure

Sector erase time

Chip erase time

1

15

s

T^A= + 25 °C

Vcc = 5.0 V

Excludes 00H programming prior

erasure

5

Word (16 bit width)

programming time

16

3,600

µs Excludes system-level overhead

Erase/Program cycle

Data holding time

10,000

cycle

100,000

h

69

MB90560/565 Series

■ ELECTRICAL CHARACTERISTICS (MB90565 SERIES)

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Rating

Parameter

Symbol

Unit

Remarks

Min.

Max.

V^CC

AV^CC

AVR

VI

VSS − 0.3

VSS + 4.0

V

*1

Power supply voltage

VCC ≥ AVCC

AVCC ≥ AVR ≥ 0 V ^*1

Input voltage

*2

Output voltage

V^O

“L” level maximum output

current

IOL

I^OLAV

ΣIOL

15

4

mA *3

“L” level average output

current

Average value

mA

(operating current × operating ratio)

“L” level total maximum

output current

100

50

“L” level total average

output current

Average value

ΣI^OLAV

(operating current × operating ratio)

“H” level maximum output

current

IOH

−15

−4

mA *3

“H” level average output

current

Average value

I^OHAV

ΣIOH

ΣIOHAV

mA

(operating current × operating ratio)

“H” level total maximum

output current

−100

−50

“H” level total average

output current

Average value

(operating current × operating ratio)

Power consumption

Operating temperature

Storage temperature

Pd

T^A

300

+85

mW

°C

−40

−55

Tstg

+150

°C

*1 : AV^CCand AVR must not exceed VCC. Also, AVR must not exceed AVCC.

*2 : VI and VO must not exceed VCC + 0.3 V.

*3 : The maximum output current is the peak value for a single pin.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

70

MB90560/565 Series

2. Recommended Operating Conditions

(VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

3.0

3.6

V

Normal operation (MB90V560)

Normaloperation(MB90F568, MB90567

and MB90568)

Power supply voltage

V^CC

2.7

3.6

2.5

V

Maintaining state in stop mode

CMOS input pin

V^IH

VIHS

V^IHM

VIL

0.7 VCC

0.8 VCC

VCC − 0.3

VSS − 0.3

−40

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

+85

Input “H” voltage

V

CMOS hysteresis input pin

MD input pin

V

CMOS input pin

Input “L” voltage

V^ILS

VILM

TA

V

CMOS hysteresis input pin

MD input pin

V

Operating temperature

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

71

MB90560/565 Series

3. DC Characteristics

Sym

(TA = −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Parameter

Pin Name

Condition

Unit

Remarks

bol

Min.

Typ.

Max.

Output “H”

voltage

All output VCC = 3.0 V

pins IOH = −2.0 mA

V^OH

VCC − 0.5 VCC − 0.3

V

Output “L”

voltage

All output VCC = 3.0 V

pins IOL = 2.0 mA

VOL

0.2

0.4

5

Input leak

current

All output VCC = 3.0 V

I^IL

−5

−1

µA

pins

VSS < VI < VCC

For VCC = 3.3 V,

internal frequency = 8 MHz,

normal operation

14

22

40

27

45

28

45

33

mA MB90567/568

mA MB90F568

For V^CC= 3.3 V,

internal frequency = 16 MHz,

normal operation

27

18

32

18

36

23

For V^CC= 3.3 V,

internal frequency = 8 MHz,

A/D operation in progress

For V^CC= 3.3 V,

internal frequency = 16 MHz,

A/D operation in progress

I^CC

For V^CC= 3.3 V,

internal frequency = 8 MHz,

normal operation

Power

supply

current*

For V^CC= 3.3 V,

internal frequency = 16 MHz,

normal operation

VCC

mA MB90F568

For V^CC= 3.3 V,

internal frequency = 8 MHz,

A/D operation in progress

mA MB90F568

For VCC = 3.3 V,

internal frequency = 16 MHz,

A/D operation in progress

41

40

6

50

10

mA MB90F568

Flash write or erase

For VCC = 3.3 V,

internal frequency = 8 MHz,

sleep mode

MB90567/568

mA

MB90F568^*

I^CCS

For VCC = 3.3 V,

MB90567/568

mA

internal frequency = 16 MHz,

sleep mode

14

5

20

MB90F568^*

ICCH

Stop mode, TA = 25 °C

µA

* : Value when low power mode bits (LPM0, 1) are set to “01” with an internal operating frequency of 8 MHz.

(Continued)

72

MB90560/565 Series

(Continued)

Value

Sym-

bol

Parameter

Pin Name

Condition

Unit Remarks

Min.

Typ.

Max.

P00 to P07

P10 to P17

RST, MD0,

MD1

Pull-up

resistor

R^UP

20

65

200

kΩ

Pull-down

resistor

R^DOWNMD2

20

65

200

Note : Current values are provisional and are subject to change without notice to allow for improvements to the

characteristics. The power supply current is measured with an external clock.

73

MB90560/565 Series

4. AC Characteristics

(1) Clock Timings

(MB90567/568/F568 : T^A= −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

(MB90V560 : T^A= +25 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Sym

bol

Condi-

tion

Parameter

Pin Name

Unit

Remarks

Min.

Typ.

Max.

3

12

MHz MB90V560

Clock frequency

f^C

X0, X1

MB90567/568

MHz

3

16

MB90F568

83.3

62.5

333

ns MB90V560

Clock cycle time

t^HCYL

X0, X1

MB90567/568

ns

MB90F568

P^WH

PWL

Recommended duty

ratio = 30% to 70%

Input clock pulse width

Input clock rise/fall time

X0

10

ns

tcr

tcf

When using an

external clock

5

1.5

12

MHz MB90V560

Internal operating clock

frequency

f^CP

MB90567/568

MHz

16

MB90F568

83.3

62.5

666

ns MB90V560

Internal operating clock

cycle time

t^CP

MB90567/568

ns

MB90F568

• X0 and X1 clock timing

tHCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcr

tcf

74

MB90560/565 Series

• PLL guaranteed operation range

Relationship between internal operating clock frequency and power supply voltage

PLL guaranteed operation range

(MB90567/568/F568 : 3.0 V to 3.6 V, fCP = 3 MHz to 16 MHz)

(MB90V560 : 3.0 V to 3.6 V, fCP = 3 MHz to 12 MHz)

3.6

PLL guaranteed

operation range

A/D converter

guaranteed

operation range

3.0

2.7

Guaranteed operation range

for MB90V560

(3.0 V to 3.6 V,

Guaranteed operation range for MB90567/568/F568

(3.0 V to 3.6 V, fCP = 1.5 MHz to 16 MHz)

(2.7 V to 3.6 V, fCP = 1.5 MHz to 8 MHz)

fCP = 1.5 MHz to 12 MHz)

1.5

3

8

12

16

Internal Clock fCP (MHz)

Relationship between oscillation frequency and internal operating clock frequency

×4 ×3

×2

×1

16

12

9

8

No multiplier

6

4

3

2

1.5

3

4

6

8

12

16

Source Oscillation Clock fC (MHz)

The AC ratings are specified for the following measurement reference voltages.

• Input signal waveform

• Output signal waveform

Hysteresis input pin

Output pin

0.8 VCC

2.4 V

0.2 VCC

0.8 V

Pins other than hysteresis input or MD input pins

0.7 VCC

0.3 VCC

75

MB90560/565 Series

(2) Reset

(T^A= −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol Pin Name Condition

Unit Remarks

Min.

Max.

In normal

operation

16 t^CP

ns

Reset input time

t^RSTL

RST

Oscillatoroscillation

In stop

mode

ms

time* + 16 t^CP

*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several

dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms.

• In normal operation

tRSTL

RST

0.2 VCC

• In stop mode

t

RSTL

RST

0.2Vcc

90 % of

amplitude

X0

Internal

operation

clock

Oscillator

oscillation time

16 tcp

Oscillator stabilization wait time

Execution of the instruction

Internal

reset

76

MB90560/565 Series

(3) Power-On Reset

Parameter

(T^A= −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Condi-

tion

Symbol Pin Name

Unit

Remarks

Min.

0.05

4

Max.

*

Power supply rise time

Power supply cutoff time

t^R

VCC

30

ms

t^OFF

ms For repeated operation

* : V^CCmust be less than 0.2 V before power-on.

Notes : • The above rating values are for generating a power-on reset.

• Some internal registers are only initialized by a power-on reset. Always apply the power supply in

accordance with the above ratings if you wish to initialize these registers.

tR

2.7 V

0.2 V

VCC

0.2 V

tOFF

Sudden changes in the power supply voltage may cause a power-on reset.

The recommended practice if you wish to change the power supply voltage while the device is

operating is to raise the voltage smoothly as shown below. Also, changes to the supply voltage

should be performed when the PLL clock is not in use. The PLL clock may be used, however, if

the rate of voltage change is 1 V/s or less.

VCC

Recommended rate of voltage

rise is 50 mV/ms or less.

2.5 V

Maintain RAM data

VSS

77

MB90560/565 Series

(4) UART0 and UART1

(T^A= −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol Pin Name

Condition

Unit Remarks

Min. Max.

Serial clock cycle time

t^SCYC

t^SLOV

SCK0, SCK1

8 t^CP

ns

SCK0, SCK1

SOT0, SOT1

SCK ↓ → SOT delay time

−80

100

60

80

Internal shift clock

mode, output pin

load is

SCK0, SCK1

SIN0, SIN1

Valid SIN → SCK ↑

t^IVSH

ns

C^L= 80 pF + 1 TTL

SCK0, SCK1

SIN0, SIN1

SCK ↑ → valid SIN hold time

tSHIX

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

SCK0, SCK1

4 t^CP

ns

tSLSH

4 tCP

SCK0, SCK1 External shift clock

SOT0, SOT1 mode, output pin

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

150

ns

load is

C^L= 80 pF + 1 TTL

SCK0, SCK1

SIN0, SIN1

60

SCK0, SCK1

SIN0, SIN1

SCK ↑ → valid SIN hold time

Notes : • These are the AC ratings for CLK synchronous mode.

• CV is the load capacitor connected to the pin for testing.

• t^CPis the machine cycle period (unit = ns)

78

MB90560/565 Series

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

79

MB90560/565 Series

(5) Timer Input Timings

(T^A= −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Condi-

tion

Parameter

Symbol

Pin Name

Unit

Remarks

Min.

Max.

Input pulse width

t^TIWH, tTIWL FRCK, TIN0, TIN1

4 tCP

ns

0.8 VCC

0.2 VCC

FRCK

TIN0 to 1

tTIWH

tTIWL

(6) Timer Output Timings

(T^A= −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Pin Name

Condition

Unit Remarks

Min. Max.

CLK ↑ → T^OUTchange

time

RTO0 to RTO5, PPG0 to PPG5

TO0, TO1

tTO

30

ns

2.4 V

tTO

CLK

TOUT

2.4 V

0.8 V

(7) Trigger Input Timings

(T^A= −40 °C to +85 °C, VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Pin Name

Condition

Unit

Remarks

Min.

5 t^CP

1

Max.

In normal

operation

ns

Input pulse width

t^TRGL

INT0 to INT7, IN0 to IN3

µs

In stop mode

0.8 VCC

0.2 VCC

INT0 to INT7

IN0 to IN3

tTRGH

tTRGL

80

MB90560/565 Series

5. Electrical Characteristics for the A/D Converter

(MB90567/568/F568 : TA = −40 °C to +85 °C, 2.7 V ≤ AVR, VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V)

(MB90V560 : T^A= +25 °C, 3.0 V ≤ AVR, VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V)

Value

Parameter

Resolution

Symbol

Pin Name

Unit

Remarks

Min.

Typ.

Max.

10

bit

Total error

±3.0

±2.5

LSB

Non-linearity error

Differential linearity

error

±1.9

LSB

mV

Zero transition

voltage

AVSS

−1.5 LSB

AVSS

+0.5

AVSS

+2.5 LSB

V^OT

AN0 to AN7

1 LSB = AVRH/1024

Full-scale transition

voltage

AVR

V^FST

−3.5 LSB −1.5 LSB +0.5 LSB

Conversion time

Sampling time

66 t^CP

ns

32 tCP

Analog port input

current

IAIN

AN0 to AN7

10

µA

Analog input voltage

Reference voltage

V^AIN

AN0 to AN7

AVR

0

AVR

AVCC

5

V

2.7

I^A

IAH

I^R

AVCC

1

mA

µA

Power supply current

AVCC

5

*

AVR

100

200

5

Reference voltage

supply current

I^RH

AVR

Variation between

channels

AN0 to AN7

4

LSB

* : Current when A/D converter is not used and CPU is in stop mode (V^CC= AVCC = AVR = 3.3 V)

Notes : • The L reference voltage is fixed to AVSS. The relative error increases as AVR becomes smaller.

• Ensure that the output impedance of the external circuit connected to the analog input meets the following

condition :

Output impedance of MB90F568 external circuit ≤ 14 kΩ (Sampling Time = 4 µs)

Output impedance of MB90567/568 external circuit ≤ 7 kΩ (Sampling Time = 4 µs)

• If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short.

81

MB90560/565 Series

• Equivalent circuit of analog input circuit

RON

C

Comparator

MB90567/568/F568

RON = 7.1 kΩ approx.

C = 48.3 pF approx.

Analog input

Note : The values listed are an indication only.

82

MB90560/565 Series

6. Flash Memory Erase and Programming Performance

Value

Parameter

Condition

Units

Remarks

Min

Typ

Max

Excludes 00H programming prior

erasure

Sector erase time

Chip erase time

1

15

s

T^A= + 25 °C

Vcc = 3.3 V

Excludes 00H programming prior

erasure

5

Word (16 bit width)

programming time

16

3,600

µs Excludes system-level overhead

Erase/Program cycle

Data holding time

10,000

cycle

100,000

h

• Points to note regarding the MB90F568, 567, and 568 specifications

This section describes the specification differences between the MB90F568/567/568 and the MB90F562/F562B/

562/562A/561/561A.

(1) Functional differences

1) The 5 V to 3 V regulator has been removed in the MB96565 series.

The C pin has been changed to an N.C. pin.

2) The A/D converter unit in the MB96565 series has changed from a 5 V version to a 3 V version.

However, the conversion time and sampling time remain the same.

3) The maximum voltage that can be applied to I/O pins has changed from 5 V to 3 V in the MB96565 series.

4) Added transfer counter clear function to UART in the MB96565 series.

This function restores the UART to its initial state when “0” is written to the UART reset bit.

(2) Points to note when using the devices

The MB90F562, F562B, and F568 use P60 (14) as SIN1, P61 (15) as SOT1, and P40 (60) as SCK0 when

performing on-board programming.

Use the following pin settings when performing on-board programming.

Pin Name

MD2

Pin I/O Level*

“H” level

Remarks

MD1

“H” level

Serial write mode settings

MD0

“L” level

SIN1

SOT1

SCK0

P00

Serial data input

Serial data output

Serial clock

“L” level

Normally shared with P60

Normally shared with P61

Normally shared with P40

P01

“H” level

Input “L” level for PC writing

* : These settings are for using a Yokogawa Digital Computer Corporation writer for on-board programming. Alter-

natively, writing can be performed from a PC, but a special write program is required.

83

MB90560/565 Series

■ EXAMPLE CHARACTERISTICS

MB90F568 ICC − VCC

60

TA = +25 °C

50

16 MHz

12 MHz

40

30

20

10

0

8 MHz

4 MHz

2 MHz

2

2.5

3

3.5

4

4.5

VCC (V)

MB90568 ICC − VCC

40

35

30

25

20

15

10

5

TA = +25 °C

16 MHz

12 MHz

8 MHz

4 MHz

2 MHz

0

3

3.5

4

VCC (V)

MB90F568 ICCS − VCC

20

18

16

14

12

10

8

TA = +25 °C

16 MHz

12 MHz

8 MHz

6

4 MHz

2 MHz

4

2

0

3

3.5

4

VCC (V)

(Continued)

84

MB90560/565 Series

MB90568 ICCS − VCC

18

16

14

12

10

8

TA = +25 °C

16 MHz

12 MHz

8 MHz

6

4 MHz

2 MHz

4

2

0

2

2.5

3

3.5

4

4.5

VCC (V)

MB90F562 ICC − VCC

40

35

30

25

20

15

10

5

TA = +25 °C

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

0

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

MB90562 ICC − VCC

70

60

50

40

30

20

10

0

TA = +25 °C

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

(Continued)

85

MB90560/565 Series

(Continued)

MB90F562 ICCS − VCC

16

TA = +25 °C

14

f = 16 MHz

f = 12 MHz

12

10

8

f = 10 MHz

f = 8 MHz

6

4

f = 4 MHz

f = 2 MHz

2

0

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

MB90562 ICCS − VCC

30

TA = +25 °C

25

20

15

10

5

f = 16 MHz

f = 12 MHz

f = 10 MHz

f = 8 MHz

f = 4 MHz

f = 2 MHz

0

2.5

3

3.5

4

4.5

5

5.5

6

6.5

VCC (V)

86

MB90560/565 Series

■ ORDERING INFORMATION

• MB90560 series

Part No.

Package

Remarks

MB90561P

MB90562P

MB90561AP

MB90562AP

MB90F562P

MB90F562BP

64-pin plastic SH-DIP

(DIP-64P-M01)

MB90561PF

MB90562PF

MB90561APF

MB90562APF

MB90F562PF

MB90F562BPF

64-pin plastic QFP

(FPT-64P-M06)

MB90561PFM

MB90562PFM

MB90561APFM

MB90562APFM

MB90F562PFM

MB90F562BPFM

64-pin plastic LQFP

(FPT-64P-M09)

• MB90565 series

Part No.

Package

Remarks

MB90567PF

MB90568PF

MB90F568PF

64-pin plastic QFP

(FPT-64P-M06)

MB90567PFM

MB90568PFM

MB90F568PFM

64-pin plastic LQFP

(FPT-64P-M09)

87

MB90560/565 Series

■ PACKAGE DIMENSIONS

64-pin plastic QFP

(FPT-64P-M06)

Note : Pins width and pins thickness include plating thickness.

24.70±0.40(.972±.016)

20.00±0.20(.787±.008)

0.17±0.06

(.007±.002)

51

33

52

32

18.70±0.40

(.736±.016)

Details of "A" part

3.00 ⁺^–0⁰^.^.²³⁰⁵

14.00±0.20

(.551±.008)

(Mounting height)

INDEX

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

64

20

0~8°

1

19

1.00(.039)

0.42±0.08

(.017±.003)

0.25 ⁺^–0⁰^.^.²¹⁰⁵

M

0.20(.008)

.010 ⁺^–.^.⁰⁰⁰⁰⁸⁶

1.20±0.20

(.047±.008)

(Stand off)

"A"

0.10(.004)

C

2001 FUJITSU LIMITED F64013S-c-4-4

Dimensions in mm (inches)

(Continued)

88

MB90560/565 Series

64-pin plastic LQFP

(FPT-64P-M09)

Note : Pins width and pins thickness include plating thickness.

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

0.145±0.055

(.0057±.0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.25(.010)

INDEX

0~8°

64

17

0.50±0.20

(.020±.008)

0.10±0.10

(.004±.004)

(Stand off)

"A"

1

16

0.60±0.15

(.024±.006)

0.65(.026)

0.32±0.05

(.013±.002)

M

0.13(.005)

C

2001 FUJITSU LIMITED F64018S-c-2-4

Dimensions in mm (inches)

(Continued)

89

MB90560/565 Series

(Continued)

64-pin plastic SH-DIP

Note : Pins width and pins thickness include plating thickness.

(DIP-64P-M01)

58.00 ⁺^–0⁰^.^.⁵²⁵²2.283 ^–⁺^.^.⁰⁰²⁰²⁹

INDEX-1

INDEX-2

17.00±0.25

(.669±.010)

4.95 –⁺0⁰.^.2⁷0⁰

.195 ⁺^–.^.⁰⁰⁰²⁸⁸

0.70 –⁺0⁰.^.1⁵9⁰

.028 ⁺^–.^.⁰⁰⁰²⁷⁰

0.27±0.10

(.011±.004)

3.30 ⁺^–0⁰^.^.³²⁰⁰

19.05(.750)

.130 –⁺.^.0⁰1⁰2⁸

1.378 ⁺–0⁰.^.2⁴0⁰

.0543 ⁺^–.^.⁰⁰⁰¹⁸⁶

0.47±0.10

(.019±.004)

1.00 ⁺^–0^0.50

1.778(.0700)

0~15°

M

0.25(.010)

.039 –⁺.^.0⁰²⁰

C

2001 FUJITSU LIMITED D64001S-c-4-5

Dimensions in mm (inches)

90

MB90560/565 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0204

FUJITSU LIMITED Printed in Japan


型号：	MB90565
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontrollers 16位微控制器专用微控制器
文件：	总91页 (文件大小：879K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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