MB90660A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13604-2E

16-bit Proprietary Microcontroller

CMOS

F²MC-16L MB90660A Series

MB90662A/663A/P663A

■ DESCRIPTION

MB90660A series microcontrollers are 16-bit microcontrollers optimized for high speed realtime processing of

consumer equipment and system control of air conditioner video cameras, VCRs, and copiers. Based on the

F²MC*-16 CPU core, an F²MC-16L is used as the CPU. This CPU includes high-level language-support

instructions and robust task switching instructions, and additional addressing modes.

Microcontrollers in this series have built-in peripheral resources including multi-function timers, 16-bit reload

timer four channels, 8-bit PWM one channel, UART one channel, 10-bit A/D eight converter channels, and

external interrupt eight channels.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

• F²MC-16L CPU

• Minimum execution time: 62.5 ns/4 MHz oscillation (uses PLL multiplier): fastest speed at quadruple operation

• Instruction set optimized for controller applications

Upward compatibility at object level with the F²MC-16(H)

Various data types (bit, byte, word, long-word)

Higher speed due to review of instruction cycle

Expanded addressing modes: 23 types

High coding efﬁciency

Two access methods (bank system or linear pointer)

Improved multiply-and-divide instructions (additional signed instructions)

Improved high-precision operation with 32-bit accumulator

Extended intelligent I/O services (access area extended by 64 Kbytes)

Large memory space: 16 Mbytes

(Continued)

■ PACKAGE

64-pin Plastic SH-DIP

64-pin Plastic LQFP

(FPT-64P-M09)

(DIP-64P-M01)

MB90660A Series

(Continued)

• Improved instruction set applicable to high-level language (C) and multitasking

System stack pointer

Improved indirect instructions using various pointers

Barrel shift instruction

Stack check function

• Improved execution speed: 4-byte instruction queue

• Improved interrupt functions

• Automatic data transfer function independent of CPU

Peripheral Resources

• ROM: 16 Kbytes (MB90661A)

32 Kbytes (MB90662A)

48 Kbytes (MB90663A)

One-time PROM: 48 Kbytes (MB90P663A)

• RAM: 512 bytes (MB90661A)

1.64 Kbytes (MB90662A)

2 Kbytes (MB90663A/MB90P663A)

• General-purpose ports: Max. 51

• UART: 1 channel

Can be used for both asynchronous transfer and clocked serial (I/O extended serial) communications

• A/D converter: 10-bit, 8 channels

Includes 8-bit conversion mode

• 16-bit reload timer: 4 channels

• 8-bit PWM: 1 channel

• External interrupts: 8 channels

• 18-bit timebase timer with watchdog timer function

• PLL clock multiplier function

• CPU intermittent operation function

• Various standby modes

• Package: SH-DIP-64/LQFP-64 (0.65-mm pitch)

• CMOS technology

2

MB90660A Series

■ PRODUCT LINEUP

Part number

Parameter

MB90P663A

MB90662A

MB90663A

Classiﬁcation

ROM size

OTPROM

48 Kbytes

2 Kbytes

MASK ROM

32 Kbytes

MASK ROM

48 Kbytes

2 Kbytes

RAM size

1.64 Kbytes

CPU functions

Number of basic instructions

Instruction bit length

Instruction length

: 340

: 8/16 bits

: 1 to 7 bytes

Data bit length

Minimum execution time

Interrupt processing time

: 1, 4, 8, 16, or 32 bits

: 62.5 ns/4 MHz (PLL 4 multiply)

: 1000 ns/16 MHz (minimum)

Ports

Input Ports

I/O ports (CMOS)

: 4

: 39

I/O ports (N channel open-drain) : 8

Total : 51

Packages

DIP-64P-M01

FPT-64P-M09

DIP-64P-M01

FPT-64P-M09

DIP-64P-M01

FPT-64P-M09

Multi-Function

Timer

14-bit up/down count timer × 1, buffered compare register × 4, buffered compare clear

register, zero detect terminal control, 4 output channels, non-overlapped 3-phase waveform

output, 3-phase independent dead time timer, 4-bit carrier counter

UART

Full duplex double buffer

Selectable clock synchronous/asynchronous operation

Built-in dedicated baud rate generator (During asynchronous operation: 62500, 31250,

19230, 9615, 4808, 2404, 1202 bps)

A/D Converter

10-bit precision × 8 channels

A/D conversion time

Startup trigger

Activiation

: 6.13 µs (98 machine cycles at 16 MHz machine clock,

includes sample hold time)

: Startup by software, external source, or multi-function

timer output (RT0) can be selected

: Single, scan (multiple channel continuous), continuous

(1 channel continuous), stop (synchronized with

conversion start in scan mode)

16-Bit Reload

Timer

16-bit reload timer operation (toggle output, one-shot output selectable)

(Count clock can be selected from 0.125 µs, 0.5 µs, or 2.0 µs at 16 MHz machine cycle)

Event count function selectable

4 channels built-in

8-Bit PWM

8-bit resolution PWM operation (arbitrary cycle: duty ratio pulse output)

(Count clock can be selected from 0.125 µs or 64.0 µs at 16 MHz machine cycle)

External Interrupts Number of inputs: 8

External interrupt mode (Interrupts can be generated by four types of request detect

sources)

PLL Function

1/2/3/4-time multiplier can be selected (Please set so as not to exceed guaranteed

operation frequency)

Miscellaneous

Items

V^PPis shared with MD2

terminal (when writing the

EPROM)

—

3

MB90660A Series

■ PIN ASSIGNMENT

(TOP VIEW)

P66/RT0

DTTI

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

V

P65/Z

P64/Y

P63/X

P62/RT3/W

P61/RT2/V

P60/RT1/U

CC

P40/SIN

P41/SOT

P42/SCK

P43/PWM

P44/INT0

P45/INT1

P46/INT2/TRG

P47/INT3/ATG

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

V

SS

9

P27/TIM3/INT7

P26/TIM2/INT6

P25/TIM1/INT5

P24/TIM0/INT4

P23

P22

P21

P20

P17

P16

P15

P14

P13

P12

P11

P10

P07

P06

P05

P04

P03

P02

P01

P00

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

AVR

AV^SS

P30

P31

P32

P33

MD0

RST

MD1

MD2

X0

X1

V

SS

(DIP-64P-M01)

4

MB90660A Series

(TOP VIEW)

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P27/TIM3/INT7

P26/TIM2/INT6

P25/TIM1/INT5

P24/TIM0/INT4

P23

P22

P21

P20

P17

P16

P15

P14

P13

P12

P11

P10

P46/INT2/TRG

P47/INT3/ATG

P50/AN0

P51/AN1

P52/AN2

P53/AN3

P54/AN4

P55/AN5

P56/AN6

P57/AN7

AV^CC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

AVR

AVSS

P30

P31

P32

(FPT-64P-M09)

5

MB90660A Series

■ PIN DESCRIPTION

Pin no.

Pin name

Circuit

type

Function

Crystal oscillator pin (32 MHz).

SH-DIP*¹LQFP*²

30

31

22

23

X0

X1

A

(Oscillator)

33 to 40 25 to 32 P00 to P07

41 to 48 33 to 40 P10 to P17

49 to 52 41 to 44 P20 to P23

53 to 56 45 to 48 P24 to P27

B

General-purpose I/O ports.

(CMOS)

B

(CMOS)

B

(CMOS)

G

(CMOS) This function is activated when the output speciﬁcation of the

reload timer is “disabled”.

TIM0 to TIM3

I/O pins for reload timers 0 to 4.

Input is used only as necessary while serving as input for the

reload timer. It is therefore necessary to stop output

beforehand using other functions unless intentionally used

otherwise.

Their function as output terminals for the reload timer is

activated when the output speciﬁcation is “enabled”.

INT4 to INT7

External interrupt request input pins.

Input is used only as necessary while external interrupts are

enabled. It is therefore necessary to stop output beforehand

using other functions unless intentionally used otherwise.

22 to 25 14 to 17 P30 to P33

B

General-purpose I/O ports.

(CMOS)

3

59

P40

SIN

E

General-purpose I/O port.

(CMOS/H) This function is always enabled.

UART serial data input pin.

Input is used only as necessary while serving as UART input.

It is therefore necessary to stop output beforehand using other

functions unless intentionally used otherwise.

4

60

P41

E

General-purpose I/O port.

(CMOS/H) This function is activated when the serial data output

speciﬁcation of the UART is “disabled”.

SOT

UART serial data output pin.

This function is activated when the serial data output

speciﬁcation of the UART is “enabled”.

(Continued)

*1: DIP-64P-M01

*2: FPT-64P-M09

6

MB90660A Series

Pin no.

Circuit

type

Pin name

P42

Function

SH-DIP*¹LQFP*²

5

61

E

General-purpose I/O port.

(CMOS/H) This function is activated when the clock output speciﬁcation

of the UART is “disabled”.

SCK

UART clock I/O pin.

This function is activated when the clock output speciﬁcation

of the UART is “enabled”.

Input is used only as necessary while serving as UART input.

It is therefore necessary to stop output beforehand using other

functions unless intentionally used otherwise.

6

62

P43

E

General-purpose I/O port.

(CMOS/H) This function is activated when the output speciﬁcation of the

PWM is “disabled”.

PWM

PWM timer output pin.

This function is activated when the waveform output speciﬁca-

tion of the PWM timer is “enabled”.

7

8

63

64

P44 to P45

D

General-purpose I/O ports.

(CMOS/H) This function is always active.

INT0 to INT1

External interrupt request input pins.

Input is used only as necessary while external interrupts are

enabled.

9

1

P46

D

General-purpose input port.

(CMOS/H) This function is always active.

INT2

External interrupt request input pin.

Input is used only as necessary while external interrupts are

enabled.

TRG

Timer clear trigger input pin for multi-function timer.

Input is used only as necessary while multi-function timer

input is enabled.

10

2

P47

D

General-purpose input port.

(CMOS/H) This function is always active.

INT3

External interrupt request input pin.

Input is used only as necessary while external interrupts are

enabled.

ATG

Trigger input pin for the A/D converter.

Input is used only as necessary while the A/D converter is

performing input.

11 to 18 3 to 10 P50 to P57

AN0 to AN7

C

(AD)

Open-drain type I/O ports.

This function is enabled when the analog input enable register

speciﬁcation is “port”.

Analog input pins for the A/D converter.

This function is enabled when the analog input enable register

speciﬁcation is “AD”.

(Continued)

*1: DIP-64P-M01

*2: FPT-64P-M09

7

MB90660A Series

Pin no.

Pin name

Circuit

type

Function

SH-DIP*¹LQFP*²

58

59

60

50

51

52

P60

E

General-purpose I/O port.

(CMOS/H) This function is enabled when the multi-function timer

waveform output speciﬁcation is “disabled” and the 3-phase

waveform output speciﬁcation is “disabled”.

RT1

U

Multi-function timer waveform output pin.

This function is enabled when the multi-function timer output

speciﬁcation is “enabled”.

3-phase waveform output pin.

This function is enabled when the 3-phase waveform output

speciﬁcation is “enabled”.

P61

E

General-purpose I/O port.

(CMOS/H) This function is enabled when the multi-function timer

waveform output speciﬁcation is “disabled” and the 3-phase

waveform output speciﬁcation is “disabled”.

RT2

V

Multi-function timer waveform output pin.

This function is enabled when the multi-function timer output

speciﬁcation is “enabled”.

3-phase waveform output pin.

This function is enabled when the 3-phase waveform output

speciﬁcation is “enabled”.

P62

E

General-purpose I/O port.

(CMOS/H) This function is enabled when the multi-function timer

waveform output speciﬁcation is “disabled” and the 3-phase

waveform output speciﬁcation is “disabled”.

RT3

W

Multi-function timer waveform output pin.

This function is enabled when the multi-function timer output

speciﬁcation is “enabled”.

3-phase waveform output pin.

This function is enabled when the 3-phase waveform output

speciﬁcation is “enabled”.

61

62

53

54

P63

X

E

General-purpose I/O port.

(CMOS/H) This function is enabled when the 3-phase waveform output

speciﬁcation is “disabled”.

3-phase waveform output pin.

This function is enabled when the 3-phase waveform output

speciﬁcation is “enabled”.

P64

Y

E

General-purpose I/O port.

(CMOS/H) This function is enabled when the 3-phase waveform output

speciﬁcation is “disabled”.

3-phase waveform output pin.

This function is enabled when the 3-phase waveform output

speciﬁcation is “enabled”.

(Continued)

*1: DIP-64P-M01

*2: FPT-64P-M09

8

MB90660A Series

(Continued)

Pin no.

SH-DIP*¹LQFP*²

Circuit

type

Pin name

P65

Function

63

55

E

General-purpose I/O port.

(CMOS/H) This function is enabled when the 3-phase waveform output

speciﬁcation is “disabled”.

Z

3-phase waveform output pin.

This function is enabled when the 3-phase waveform output

speciﬁcation is “enabled”.

1

57

P66

RT0

E

General-purpose I/O port.

(CMOS/H) This function is enabled when the multi-function timer

waveform output speciﬁcation is “disabled”.

Multi-function timer waveform output pin.

This function is enabled when the multi-function timer output

speciﬁcation is “enabled”.

2

58

11

DTTI

AV^CC

D

3-phase waveform output disable input (DTTI) pin.

(CMOS/H)

19

Power Power supply for analog circuits.

supply Turn this power supply on/off by applying a voltage level

greater than AV^CCto VCC.

20

21

12

13

AVR

Reference power supply for analog circuits.

Power

Turn this pin on/off by applying a voltage level greater than

supply

AVR to AVCC.

AV^SS

Power

Ground level for analog circuits.

supply

26

28

29

18

20

21

MD0 to MD2

F

Input pins for specifying operation mode.

(CMOS/H)

Use these pins by directly connecting to V^CCor V^SS.

27

19

RST

V^CC

D

External reset request input pin.

(CMOS/H)

64

56

Power

Power supply for digital circuits.

supply

32

57

24

49

V^SS

Power

Ground level for digital circuits.

supply

*1: DIP-64P-M01

*2: FPT-64P-M09

9

MB90660A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• 3 MHz to 32 MHz operation

• Oscillation feedback resistor: Approx. 1 MΩ

X1

X0

Clock input

Standby control signal

B

• CMOS level input and output

With standby control

• Pull-up option can be selected

With standby control

Digital output

Standby control

signal

Digital input

C

• N-channel open-drain output

CMOS level hysteresis input

With A/D control

Digital output

A/D input

Digital input

A/D disable

D

• CMOS level hysteresis input

Without standby control

• Pull-up option can be selected

Without standby control

Digital input

(Continued)

10

MB90660A Series

(Continued)

Type

Circuit

Remarks

E

• CMOS level output

• CMOS level hysteresis input

With standby control

Digital output

• Pull-up option can be selected

With standby control

Digital input

Standby control

signal

F

• CMOS level input

(Mask ROM version uses CMOS hysteresis

input)

Without standby control

*2

*3

• Pull-up option can be selected for MD2 (*1)

Pull-up option can be selected for MD1/0 (*2)

Both without standby option

*1

• The MB90P663A does not include a noise filter.

It also does not have a P channel protect Tr (*3)

for the MD2 pin or pull-down.

Noise filter

Typ. 40 ns

Digital input

G

• CMOS level input and output

Without standby control

• Pull-up option can be selected

With standby control

Digital output

Digital input

11

MB90660A Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur with CMOS ICs if voltage higher than V^CCor lower than V^SSis applied to input and output

pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between V^CCand VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

To prevent the similar aftereffects, use also the utmost care not to allow the analog supply voltage to exceed

the digital supply voltage.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be pins should be connected to a pull-

up or pull-down resistor.

3. External Reset Input

When resetting by inputting “L” level to the RST pin, the “L” level must be input for at least 5 machine cycles to

ensure that internal reset has occurred. Be aware of this point when using external clock input.

4. VCC, VSS Pin

Be sure that both VCC and VSS are at the same voltage.

5. Notes on Using an External Clock

Drive X0 when using an external clock.

• Using an External Clock

MB90660A

X0

X1

6. Order of Power-on to A/D Converter and Analog Inputs

Power-off (AVCC, AVR) to the digital power supply (VCC) must be performed only after the A/D converter and the

analog inputs (AN0 to AN7) has been turned on.

Turning on or off should always be performed keeping AVR below AV^CC.

Use caution for the input voltage not to exceed AVCC when the pin sharing the analog input for its function is

used as an input port.

7. Programming Mode

When the MB90P663A is shipped from Fujitsu, all bits (48 K × 8 bits) are set to “1”. Program by setting selected

bits to “0” when you wish to set the data. Note that “1” cannot be programming electrically.

12

MB90660A Series

8. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program and verify

Aging

150°C, 48 H

Data verification

Assembly

9. ProgrammingYields

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

10.Fluctuations in Supply Voltage

Although the assured VCC supply voltage operating range is as speciﬁed, sudden ﬂuctuations even within this

range may cause a malfunction. Therefore, the voltage supply to the IC should be kept as constant as possible.

The VCC ripple (P-P value) at the supply frequency (50 to 60 Hz) should be less than 10% of the typical VCC

value, or the coefﬁcient of excessive variation should not be more than 0.1 V/ms instantaneous change when

power is supplied.

13

MB90660A Series

■ PROGRAMMING THE MB90P663A EPROM

Since the MB90P663A is functionally equivalent to the MBM27C1000 when it is in EPROM mode, it is possible

to program them with a general-purpose EPROM programmer by using a special adaptor socket.

However, the MB90660A does not support the electronic signature (device ID code) mode.

1. Pin Assignment in EPROM Mode

• MBM27C1000-compatible pins

MBM27C1000

Pin no. Pin name

MB90P663A

MBM27C1000

MB90P663A

Pin no.

SH-DIP LQFP

Pin no.

SH-DIP LQFP

Pin name

Pin no.

Pin name

1

2

VPP

OE

29

24

48

45

56

55

54

53

52

51

50

49

33

34

35

—

21

16

40

37

48

47

46

45

44

43

42

41

25

26

27

—

MD2 (VPP)

P32

P17

P14

P27

P26

P25

P24

P23

P22

P21

P20

P00

P01

P02

—

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCC

PGM

NC

64

25

—

56

17

—

VCC

P33

—

3

A15

A12

A07

A06

A05

A04

A03

A02

A01

A00

D00

D01

D02

GND

4

A14

A13

A08

A09

A11

A16

A10

CE

47

46

41

42

44

22

43

23

40

39

38

37

36

39

38

33

34

36

14

35

15

32

31

30

29

28

P16

P15

P10

P11

P13

P30

P12

P31

P07

P06

P05

P04

P03

5

6

7

8

9

10

11

12

13

14

15

16

D07

D06

D05

D04

D03

• Power supply, GND connection pins

Pin no.

Type

Power

GND

Pin name

SH-DIP

LQFP

2

64

58

56

DTTI

V^CC

57

21

27

32

26

3

49

13

19

24

18

59

60

61

VSS

AVSS

RST

VSS

MD0

P40

P41

P42

4

5

14

MB90660A Series

• Pins other than MBM27C1000-compatible pins

Pin no.

Pin name

Processing

SH-DIP

LQFP

30

28

22

20

X0

MD1

X1

Pull-up by

4.7 KΩ

31

23

OPEN

9

10

1

2

P46

P47

11 to 18 3 to 10 P50 to P57

1 MΩ-level

19

20

11

12

AV^CC

AVR

pull-up resistor

connected to

each pin

58 to 63 50 to 55 P60 to P65

1

57

P66

6 to 8

62 to 64 P43 to P45

2. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Recommended programmer manufacturer

Compatible socket

adapter

Sun Hayato Co., Ltd.

and programmer name

Part no.

Package

Minato

Electronics Inc.

Data I/O Co., Ltd. Advantest Corp.

MB90P663AP

SH-DIP-64 ROM-64SD-32DP-16L Recommended

ROM-64SF-32DP-16L Recommended

Recommended

MB90P663APF LQFP-64

Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

Minato Electronics Inc.: TEL: USA (1)-916-348-6066

JAPAN (81)-45-591-5611

Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444

EUROPE (49)-8-985-8580

Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111

15

MB90660A Series

3. Programming Data

(1) Adjust the EPROM programmer to settings for the MBM27C1000.

(2) Load program data from addresses 10000H to 1FFFFH in the EPROM programmer.

OTPROM addresses FF4000H to FFFFFFH of the MB90P663A in operation mode correspond to addresses

14000H to 1FFFFH in EPROM mode.

Operation mode

EPROM mode

FFFFFFH

1FFFFH

OTPROM

FF4000H

FF0000H

14000^H

10000H

(3) Set the MB90P663A into the adaptor socket and install the adaptor socket into the EPROM programmer.

Pay attention to the orientation of the device and the adaptor socket at this time.

(4) Programming data to the EPROM.

(5) If data cannot be programmed, try again with a 0.1 µF capacitor connected between V^CCand GND and VPP

and GND.

Note: Since Mask ROM products (MB90662A/663A) do not include an EPROM mode, data cannot be read-out

using an EPROM programmer.

16

MB90660A Series

4. PROM Option Bitmap

The programming method is the same as a PROM, and can be set by programming values to addresses indicated

in the memory map.

The following bit map shows the relation between bits and options.

• PROM Option Bitmap

Bit

7

6

5

4

3

2

1

0

Address

00004^HP07

P06

Pull-up

1: No

P05

Pull-up

1: No

P04

Pull-up

1: No

P03

Pull-up

1: No

P02

Pull-up

1: No

P01

Pull-up

1: No

P00

Pull-up

1: No

Pull-up

1: No

0:Yes

00008H P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

0000CH P27

P26

P25

P24

P23

P22

P21

P20

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

00010H P43

P42

P41

P40

P33

P32

P31

P30

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

MD1/MD0^*2

Pull-up

1: No

Accept asyn-

chronous reset

1:Yes

00014H

*1

P47

P46

P45

P44

RST

DTTI

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

0: No

0:Yes

00018H

P66

P65

P64

P63

P62

P61

P60

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Pull-up

1: No

0:Yes

Open

Initially (value when blank), all bits are “1”.

*1: Under this release, the pull-up resistor is cut-off during stop mode for pins for which the pull-up option was

selected. (Pins for which the circuit type shown in the “■ Pin Description” is B or E.)

However, the pull-up resistor is not cut-off even in stop mode for P44 to 47, RST, DTTI (pins for which the circuit

type shown in the “■ Pin Description” is D or G), and MD1 and MD0.

*2: Whether or not a pull-up/pull-down resistor is present for MD2, MD1 and MD0 is determined as follows. If pull-

up/pull-down resistor is selected, it is included with all 2 (or 3) pins. Presence or absence of the pull-up or pull-

down resistors for the mode terminal cannot be selected for each pin.

MB90P663A

MB90663A/2A

Pull-down can be selected

With pull-up resistor

MD2

MD1

MD0

No

With pull-up resistor

Notes: • “FFH” must be set to addresses no deﬁned in the table above.

• Since the option setting for the MB90P663A takes 8 machine cycles, the option setting is not made until

a clock is provided after power-on. (This results in no pull-up for all pins, and asynchronous reset input is

accepted.)

17

MB90660A Series

■ BLOCK DIAGRAM

X0, X1

RST

MD0 to MD2

CPU

Clock

controller

F²MC-16L family core

INT0 to INT7

RAM

External interrupts

Interrupt controller

ROM

TRG

DTTI

RT0 to RT3

U, V, W

X, Y, Z

SIN

SOT

SCK

Multi-function timer

(Dead time timer)

UART

AVcc

AVR

AVss

AN0 to AN7

ATG

10-bit

A/D converter

TIM0 to TIM3

PWM

16-bit timer

8-bit PWM

I/O ports

8

4

8

7

P00 P10 P20 P30 P40 P50 P60

to to to to to to to

P07 P17 P27 P33 P47 P57 P66

Note: In the diagram above, I/O ports share pins with all internal function blocks. These

cannot be used as I/O ports when used as internal module pins.

18

MB90660A Series

■ F²MC-16L CPU PROGRAMMING MODEL

• Dedicated Registers

Accumulator

AH

AL

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

Direct page register

DPR

Program bank register

Data bank register

PCB

DTB

USB

SSB

ADB

User stack bank register

System stack bank register

Additional data bank register

8 bits

16 bits

32 bits

• General-purpose Registers

32 banks max.

R7

R5

R3

R1

R6

RW7

RW6

RW5

RW4

RL3

RL2

RL1

RL0

R4

R2

R0

RW3

RW2

RW1

RW0

000180^H+ RP 10H→

16 bits

• Processor States (PS)

ILM

RP

—

I

S

T

N

Z

V

C

CCR

19

MB90660A Series

■ MEMORY MAP

FFFFFF H

Single chip

ROM area

Address1#

FF0000 H

010000 H

ROM area

(FF bank image)

Address2#

004000 H

002000 H

Address3#

000380 H

RAM

Registers

000180 H

000100 H

0000C0 H

: Internal

Peripheral resources

: Access disabled

000000 H

Product Model

MB90662A

Address #1

FF8000H

FF4000H

Address #2

Address #3

000780H

008000H

004000H

MB90663A

000900H

MB90P663A

000900H

20

MB90660A Series

■ I/O MAP

Access^*2

R/W*

R/W!

Address

Register

Name

PDR0

Resource name

Port 0

Initial value

X X X X X X X X

– – – – X X X X

X X X X X X X X

1 1 1 1 1 1 1 1

000000^HPort 0 data register

000001H Port 1 data register

000002H Port 2 data register

000003H Port 3 data register

000004H Port 4 data register

000005H Port 5 data register

PDR1

PDR2

PDR3

PDR4

PDR5

Port 1

Port 2

Port 3

Port 4

R/W*

Port 5

Port 6 data register/

000006H

PDR6/

PDBR

R/W*

*1

Port 6

– X X X X X X X

Port data buffer register

000007H

Vacancy

to 0FH

—

000010H Port 0 direction register

000011H Port 1 direction register

000012^HPort 2 direction register

000013H Port 3 direction register

000014H Port 4 direction register

000015H Analog input enable register

000016H Port 6 direction register

DDR0

DDR1

DDR2

DDR3

DDR4

ADER

DDR6

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

0 0 0 0 0 0 0 0

– – – – 0 0 0 0

1 1 1 1 1 1 1 1

– 0 0 0 0 0 0 0

000017H

Vacancy

to 1BH

—

*1

—

00001CH

System reserved area

to 1FH

PWM operation mode control

000020H

register

PWMC

R/W

0 0 0 0 0 – – 1

000021H Vacancy

—

PRLL

PRLH

SMR

*1

—

PWM

UART

000022H

R/W

R/W!

X X X X X X X X

0 0 0 0 0 – 0 0

0 0 0 0 0 1 0 0

PWM reload register

000023H

000024H Serial mode register

000025H Serial control register

SCR

Serial input data register/

000026H

SIDR/

SODR

R/W

X X X X X X X X

0 0 0 0 1 – 0 0

Serial output data register

000027H Serial status register

000028H Interrupt enable register

000029H Interrupt source register

SSR

R/W!

R/W

ENIR

EIRR

External interrupt 0 0 0 0 0 0 0 0

X X X X X X X X

00002AH

External interrupt 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

Request level setting register

00002BH

ELVR

R/W

00002CH

0 0 0 0 0 0 0 0

A/D converter

A/D control status register

00002DH

ADCS

R/W!

0 0 0 0 0 0 0 0

(Continued)

21

MB90660A Series

(Continued)

Access^*2

Address

00002E^H

00002FH

000030H

000031H

000032H

000033H

000034H

000035H

000036H

000037H

000038H

000039H

00003AH

00003BH

00003CH

00003DH

00003EH

00003FH

Register

A/D data register

Name

ADCR

Resource name

Initial value

X X X X X X X X

0 0 0 0 0 0 X X

0 0 0 0 0 0 0 0

– – – – 0 0 0 0

X X X X X X X X

0 0 0 0 0 0 0 0

– – – – 0 0 0 0

X X X X X X X X

0 0 0 0 0 0 0 0

– – – – 0 0 0 0

X X X X X X X X

0 0 0 0 0 0 0 0

– – – – 0 0 0 0

X X X X X X X X

1 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 1 – 0 0 0 0

– – – – 0 0 0 0

R/W!

A/D converter

Control status register

TMCSR0

R/W

16-bit

reload timer 0

16-bit timer register/

16-bit reload register

TMR0/

TMRLR0

Control status register

TMCSR1

16-bit

reload timer 1

16-bit timer register/

16-bit reload register

TMR1/

TMRLR1

Control status register

TMCSR2

16-bit

reload timer 2

16-bit timer register/

16-bit reload register

TMR2/

TMRLR2

Control status register

TMCSR3

16-bit

reload timer 3

16-bit timer register/

16-bit reload register

TMR3/

TMRLR3

000040H Timer control status register

000041H Compare interrupt control register

000042H Timer mode control register

000043H Compare/data select register

TCSR

CICR

R/W!

R/W

R/W!

R/W

TMCR

COER

Compare buffer mode control

000044H

register

CMCR

R/W

– – – – 0 0 0 0

000045H Zero detect output control register

000046H Output control buffer register

ZOCTR

OCTBR

W

– – – X 0 0 0 0

1 1 1 1 1 1 1 1

0 – – – X X X X

X X X X X X X X

– – X X X X X X

X X X X X X X X

– – X X X X X X

X X X X X X X X

– – X X X X X X

(Continued)

Multi-function

timer

R/W

R/W!

000047H Zero detect interrupt control register ZICR

000048H

Output compare buffer register 0

Output compare buffer register 1

Output compare buffer register 2

OCPBR0

W

000049H

00004AH

00004BH

00004CH

00004DH

OCPBR1

OCPBR2

22

MB90660A Series

(Continued)

Access^*2

Address

Register

Name

Resource name

Initial value

X X X X X X X X

– – X X X X X X

0 0 0 0 0 0 0 0

– – 0 0 0 0 0 0

0 0 0 0 0 0 0 0

X X X 0 X X X X

X X X X X X X X

—

00004E^H

00004FH

000050H

000051H

Output compare buffer register 3

OCPBR3

W

Compare clear buffer register

CLRBR

W

Multi-function

timer

000052H Dead time control register

000053H Dead time setting register

000054H Dead time compare register

000055H Vacancy

DTCR

DTSR

DTCMR

—

R/W!

W

*1

—

000056H

– 0 0 1 – 0 0 0

– 0 1 1 – 0 1 0

16-bit reload

timer

Timer pin control register

000057H

TPCR

R/W

000058H

Vacancy

to 5EH

—

CDCR

—

*1

W

—

UART

—

Machine clock division control

00005FH

register

– – – – 1 1 1 1

000060H

Vacancy

to 8FH

*1

—

000090H

System reserved area

to 9EH

—

*1

—

Delayed interrupt source generate/

cancel register

Delayed interrupt

generator module

00009FH

DIRR

R/W

– – – – – – – 0

0000A0H Low power mode control register

0000A1H Clock select register

LPMCR

CKSCR

R/W!

0 0 0 1 1 0 0 0

1 1 1 1 1 1 0 0

Low power

0000A2H

System reserved area

to A7H

—

*1

—

0000A8H Watchdog timer control register

0000A9H Timebase timer control register

WDTC

TBTC

R/W!

Watchdog timer

Timebased timer

X – X X X 1 1 1

1 – – 0 0 1 0 0

0000AAH

System reserved area

to AFH

—

*1

—

0000B0H Interrupt control register 00

0000B1H Interrupt control register 01

0000B2H Interrupt control register 02

0000B3H Interrupt control register 03

0000B4H Interrupt control register 04

0000B5H Interrupt control register 05

0000B6H Interrupt control register 06

0000B7H Interrupt control register 07

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

R/W!

0 0 0 0 0 1 1 1

(Continued)

Interrupt

controller

23

MB90660A Series

(Continued)

Access^*2

R/W!

Address

Register

Name

ICR08

Resource name

Initial value

0 0 0 0 0 1 1 1

0000B8^HInterrupt control register 08

0000B9H Interrupt control register 09

0000BAH Interrupt control register 10

0000BBH Interrupt control register 11

0000BCH Interrupt control register 12

0000BDH Interrupt control register 13

0000BEH Interrupt control register 14

0000BFH Interrupt control register 15

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt

controller

0000C0H

System reserved area

to FFH

—

*1

—

*1: Access prohibited

*2: Registers marked “R/W!” in the access column include some bits that can only be read or only be written. For

details, see the register list for each resource.

* : When a register marked “R/W!”, “R/W*” or “W” in the access column is accessed by a read-modify-write instruc-

tion (such as a bit set instruction), the bit operated on by the instruction will be set to the speciﬁed value, but a

malfunction will occur if there are any other bits which can only be written. Therefore, do not access these

locations using these instructions.

Description of Initial Values

0: The initial value of this bit is “0”.

1: The initial value of this bit is “1”.

*: The initial value of this bit is “1” or “0”. (This is determined depending on the level of the MD0 to MD2 pins.)

X: The initial value of this bit is undeﬁned.

–: This bit is not used. The initial value is undeﬁned.

Note: The initial value results for bits which can only be written when initialized by a reset. Note that this is not the

value when read.

Also, sometimes LPMCR, CKSCR and WDTC are initialized and sometimes they are not depending on the

type of reset. If they are initialized, the initial value is used.

24

MB90660A Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS

AND INTERRUPT CONTROL REGISTERS

Interrupt vector

Interrupt control register

I²OS

Interrupt source

support

Number

Address

FFFFDCH

FFFFD8H

FFFFD4H

FFFFCCH

FFFFC8H

ICR

—

Address

Reset

×

#08

#09

#10

#12

#13

08^H

09H

0AH

0CH

0DH

—

INT9 instruction

Exception

—

Multi-function timer DTTI input

External interrupt #0

ICR00

0000B0H

ICR01

0000B1H

External interrupt #4

#14

#15

#17

#19

0EH

0F^H

11H

13H

FFFFC4H

FFFFC0H

FFFFB8H

FFFFB0H

Multi-function timer trigger input or

zero detect

ICR02

ICR03

ICR04

0000B2H

0000B3H

0000B4H

Multi-function timer zero detect

Multi-function timer overﬂow, compare

clear or zero detect

External interrupt #1

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#34

#35

#37

#39

#40

#42

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

22H

23H

25H

27H

28H

2AH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF74H

FFFF70H

FFFF68H

FFFF60H

FFFF5CH

FFFF54H

ICR05

ICR06

ICR07

0000B5H

0000B6H

0000B7H

Multi-function timer compare match

External interrupt #5

×

PWM underﬂow

External interrupt #2

External interrupt #6

16-bit reload timer #0

ICR08

ICR09

0000B8H

0000B9H

16-bit reload timer #1

16-bit reload timer #2

16-bit reload timer #3

End of A/D converter conversion

Timebase timer interval interrupt

UART send complete

ICR10

ICR11

ICR12

ICR13

0000BAH

0000BBH

0000BCH

0000BDH

×

UART receive complete

External interrupt #3

ICR14

ICR15

0000BEH

0000BFH

External interrupt #7

Delayed interrupt generator module

: indicates that the interrupt request flag is cleared by the I²OS interrupt clear signal (no stop request).

: indicates that the interrupt request flag is cleared by the I²OS interrupt clear signal (with stop request).

: indicates that the interrupt request flag is not cleared by the I²OS interrupt clear signal.

Note: Do not specify I²OS activation in interrupt control registers that do not support I²OS.

25

MB90660A Series

■ PERIPHERAL RESOURCES

1. Parallel Port

The MB90660A includes 39 I/O pins, 4 input pins, and 8 open-drain output pins.

Port 0, 1, 2, 3 and 6 are I/O ports. They are used for input when the corresponding direction register value is

“0”, and for output when the value is “1”.

Port 5 is an open-drain port. It is used as a port when the analog input enable register is “0”.

Ports 40 to 43 are I/O ports. They are used for input when the corresponding direction register value is “0”, and

for output when the value is “1”. Ports 44 to 47 are input ports which can only be used for reading data.

(1) Register Conﬁguration

bit

15

14

13

12

11

10

9

8

Port Data Register

: PDR1 000001^H

Address

: PDR3 000003H

PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0

PDR1, 3

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(X)

bit

7

6

5

4

3

2

1

0

Port Data Register

: PDR0 000000^H

Address

PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0

PDR0, 2, 6

: PDR2 000002H

: PDR6 000006H

(PDBR)

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(X)

bit

15

14

13

12

11

10

9

8

Port Data Register

Address: 000005^H

PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

PDR5

PDR4

Read/Write

Initial value

(1)

bit

7

6

5

4

3

2

1

0

Port Data Register

Address: 000004H

PD47 PD46 PD45 PD44 PD43 PD42 PD41 PD40

(R)

(X)

(R)

(X)

(R)

(X)

(R) (R/W) (R/W) (R/W) (R/W)

(X) (X) (X) (X) (X)

Read/Write

Initial value

Notes: There are no register bits for bits 15 to 12 of Port 3.

There is no register bit for bit 7 of Port 6.

Bits 7 to 4 of Port 4 can only be used to read data.

26

MB90660A Series

bit

15

14

13

12

11

10

9

8

Port Direction Register

: DDR1 000011^H

: DDR3 000013H

Address

DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0

DDR1, 3

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

bit

7

6

5

4

3

2

1

0

Port Direction Register

: DDR0 000010^H

: DDR2 000012H

: DDR4 000014H

: DDR6 000016H

Address

DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0

DDR0, 2, 4, 6

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

Notes: There are no register bits for bits 15 to 12 of Port 3.

There are not register bits for bits 7 to 4 of Port 4

There is no DDR for Port 5.

There is no register bit for bit 7 of Port 6.

bit

15

14

13

12

11

10

9

8

Analog Input Enable Register

Address: 000015^H

ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0

ADER

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(1)

27

MB90660A Series

(2) Block Diagrams

• I/O Ports

Data register read

Data register

Data register write

Direction register

Direction register write

Direction register read

• Open-drain Ports (Also Used for Analog Input)

RMW

(Read-modify-

write instruction)

Data register read

Data register

Data register write

ADER

ADER register write

ADER register read

• Input Ports

Data register read

28

MB90660A Series

2. Multi-function Timer

The multi-function timer controls up to 7 realtime output pins, and includes the following functions.

• Interval timer function

It can output pulses or generate an interrupt at a ﬁxed interval.

• PWM output function

Can perform output for a ﬁxed cycle pulse while changing the duty ratio (ratio between “L” output width and

“H” output width) in realtime.

• 3-phase AC sine wave output (inverter control output) function

Can perform 3-phase AC sine wave output using AC motor inverter control, etc. (using any setting for the non-

overlap interval)

This timer also has the following characteristics.

• Pulse cycle control using 14-bit timer

A machine cycle of 1, 2, 8 or 16 can be selected based on pre-scalars as the clock source (Minimum resolution

of 62.5 ns at 16 MHz operation).

Can use a carrier frequency up to 30 KHz at 8-bit stop when used for AC motor control.

Up count only or up/down count can be selected using the count mode selection.

Possessing a buffer, cycle can be changed in realtime by transferring data from buffer upon zero detect.

• Duty control using compare registers

Possessing four compare registers, output pulse duty can be set for four separate channels.

Each possessing a separate buffer, duty can be changed in realtime by transferring data from buffer upon zero

detect or comparison.

• Non-overlap control using dead time timer

Dead time timer can be used to generate PWM output for three channels or even reversed signals with non-

overlap, thus allowing an AC motor control wave (U, V, W, X, Y, Z) to be generated.

A machine cycle of 1, 4, 8 or 32 can be selected based on pre-scalars as the clock source for the dead timer

(Minimum resolution of 62.5 ns at 16 MHz operation)

• Forced stop control using DTTI pin input

The forced pin output level can be ﬁxed by DTTI pin input or software.

Inactive control can be performed during AC motor control using DTTI pin input.

External pin control even during vibration stop can be performed through clockless DTTI pin input.

• Event detection and interrupt generation using various ﬂags

Flagscanbesetand/orinterruptsgenerateduponzerodetect, overﬂow, detectofmatchwithcompareregisters,

or clear by TRG pin input, or any match of the compare registers for the four channels for the 14-bit timer (also

possible to disable interrupt output).

29

MB90660A Series

(1) Register Conﬁguration

8 bits

TCSR

CICR

Address : 000040H

Address : 000041H

Address : 000042H

Address : 000043H

Address : 000044H

(R/W) Timer control status register

(R/W) Compare interrupt control register

(R/W) Timer mode control register

TMCR

COER

CMCR

(R/W) Compare/data select register

(R/W) Compare buffer mode control register

ZOCTR

OCTR

Address : 000045H

(W)

Zero detect output control register

Output control register

Address : 000046H

Address : 000047H

OCTBR

ZICR

(R/W) Output control buffer register

(R/W) Zero detect interrupt control register

14 bits

Output compare registers 0 to 3

OCPR0 to 3

Address : 000048H

OCPBR0 to 3

(W)

Output compare buffer registers 0 to 3

to

: 00004FH

14 bits

CLRR

(W)

Compare clear register

Address : 000050^H

: 000051H

CLRBR

Compare clear buffer register

Address : 000052H

Address : 000053H

Address : 000054H

DTCR

DTSR

(R/W) Dead time timer control register

(W)

Dead time setting register

Dead time compare register

DTCMR

Address : 000006H

PDBR

(W)

Port data buffer register

30

MB90660A Series

(2) Block Diagrams

• Timer/wave generator block diagram

CLRR, CLRBR

Reverse

Interrupt Control

IIOS

or Clear

Comparator

TCIE, TCIR

TZIE, TZIR

TMIE, TMIR

CIE3 to 0, CIR3 to 0

Count Clock

Pre-scalar

(1, 2, 8 or 16 machine cycles)

14-bit Timer

STCR, TMST, MODE

CES1, 0

Timer Clear

TCS1, 0

TRG

(External Input)

Zero detect interrupt

Timer interrupt

Zero detect

Zero detect interrupt mask

Compare interrupt

ZOSC, IME, CYC3 to 0

Zero detect pin control

ZSB0

Zero detect

Set, Reset

14

Set, Reset,

Transfer

Comparator, pin control

RO01, 0

PDR6

PD66

RT0

(External Output)

OCPR0, OCPBR0

Zero detect pin control

ZSB1

Set, Reset

Set, Reset,

Transfer

Comparator, pin control

RO11, 0

PDR6

PD60

RT1

(to Output Selector)

OCPR1, OCPBR1

Zero detect pin control

ZSB2

Set, Reset

Set, Reset,

Transfer

Comparator, pin control

RO21, 0

PDR6

PD61

RT2

(to Output Selector)

OCPR2, OCPBR2

Zero detect pin control

ZSB3

Set, Reset

Set, Reset,

Transfer

Transfer request

Comparator, pin control

RO31, 0

PDR6

PD62

RT3

(to Output Selector)

Buffer transfer control

TREN, TMSK, BFS1, 0

OCPR3, OCPBR3

31

MB90660A Series

• Output selector/dead time generator block diagram

DTTI interrupt

DTTI Interrupt

DTIE, DTIF

Flag set

DTTI control

Inactive

TOCE, TOC1, 0

DTTI

(External input)

NRSL

RT1

(from wave

generator)

P60/RT1/U

Compare

Selector

U

X

Dead time

Comparator

8-bit timer

P63/X

wave

(External output)

generator

Count clock

Pre-scalar

Active level

Mode select

Inactive

Division select

RT2

(from wave

generator)

P61/RT2/V

Selector

Compare

P64/Y

V

Y

Dead time

wave

generator

Comparator

8-bit timer

(External output)

Active level

Mode select

Inactive

Count clock

Pre-scalar

Division select

RT3

(from wave

generator)

P62/RT3/W

P65/Z

Selector

Compare

W

Z

Dead time

wave

generator

Comparator

8-bit timer

(External output)

Active level

Mode select

Count clock

Pre-scalar

Division select

Wave control

8

DMOD, DT1, 0

DCS1, 0

DTCMR

32

MB90660A Series

3. UART

The UART is a serial I/O port for asynchronous (start/stop) or CLK synchronous communications with external

resources. It has the following characteristics:

• Full duplex double buffering

• Asynchronous (start/stop) or CLK synchronous communications

• Multiprocessor mode support

• Internal dedicated baud-rate generator

Asynchronous

: 19230/9615/31250/4808/2404/1202 bps

CLK synchronous

: 2 M/1 M/500 K/250 K bps

• Free baud-rate setting based on external clock

• Error detection functions (parity, framing and overrun)

• Use of NRZ coded transfer signal

• Supports intelligent I/O services

(1) Register Conﬁguration

15

8

7

0

SCR

SSR

SMR

(R/W)

SIDR (R)/SODR (W)

CDCR

8 bits

(W)

8 bits

bit

7

6

5

4

3

2

–

1

0

Serial mode register

(SMR)

MD1 MD0 CS2 CS1 CS0

SCKE SOE

Address : 000024^H

bit

15

14

P

13

12

11

10

9

8

Serial control register

(SCR)

PEN

SBL

CL

A/D REC RXE TXE

Address : 000025^H

bit

7

6

5

4

3

2

1

0

Serial input register

Serial output register

(SIDR/SODR)

D7

D6

D5

D4

D3

D2

D1

D0

Address : 000026^H

bit

15

14

13

12

11

10

–

9

8

Serial status register

(SSR)

PE ORE FRE RDRF TDRE

RIE

TIE

Address : 000027^H

bit

15

–

14

–

13

–

12

–

11

10

9

8

Machine clock

division control register

(CDCR)

DIV3 DIV2 DIV1 DIV0

Address : 00005F^H

33

MB90660A Series

(2) Block Diagram

Control signal

Receive interrupt

(to CPU)

Dedicated baud

rate generator

SCK

Send interrupt

(to CPU)

Transfer clock

16-bit timer0

(connected internally)

Clock selector

Receive clock

External clock

Receive controller

Send controller

Start bit

SIN

Send start circuit

Send bit counter

detect circuit

Receive bit

counter

Receive parity

counter

Send parity

counter

SOT

Receive shifter

Send shifter

Receive status

determination circuit

Receive end

Send start

SODR

SIDR

Receive error

generator signal for EI²OS

(to CPU)

F²MC-16 bus

MD1

MD0

PEN

PE

P

ORE

CS2

CS1

CS0

SBL

CL

FRE

SMR

register

SCR

register

SSR

register

RDRF

TDRE

A/D

REC

RXE

TXE

SCKE

SOE

RIE

TIE

Control signal

34

MB90660A Series

4. 10-bit, 8-channel A/D Converter (with 8-bit Resolution Mode)

This 10-bit, 8-channel A/D converter is used to convert analog input voltage to corresponding digital values. It

has the following features.

• Conversion time: 6.13 µs per channel (includes sample and hold time at 98 machine cycles/machine clock

of 16 MHz)

• Sample hold time: 3.75 µs per channel (60 machine cycles per machine clock of 16 MHz)

• RC-type sequential approximation conversion with sample and hold circuits

• 10-bit or 8-bit resolution

• Analog input can be selected from 8 channels

Single conversion mode

: One channel selected for conversion

Scan conversion mode

: Consecutive multiple channels converted (programmable with max. eight

channels)

Repetitive conversion mode : Data on the speciﬁed channel is converted repeatedly

Stop conversion mode : Once one channel is converted, operations stop and the device waits until

started again (conversion start can be synchronized)

• At the end of each A/D conversion, an interrupt request to the CPU can be generated. This interrupt can be

used to activate I²OS or transfer A/D conversion results to memory, making it useful when continuous

processing is desired.

• Conversion can be triggered by software, an external trigger (falling edge), and/or a timer (rising edge).

(1) Register Conﬁguration

bit

15

14

13

12

11

10

9

8

A/DControl status register (upper)

Address: 00002D^H

BUSY INT INTE PAUS STS1 STS0 STRT Reserved

ADCS

ADCR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W)

(–)

(0)

Read/Write

Initial value

(0)

bit

7

6

5

4

3

2

1

0

A/D Control status register (lower)

Address: 00002CH

MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

bit

15

14

–

13

–

12

–

11

–

10

–

9

8

A/D Data register (upper)

Address: 00002FH

S10

D9

D8

(R/W) (R)

(R)

(0)

(R)

(0)

(R)

(0)

(R)

(0)

(R)

(X)

(R)

(X)

Read/Write

Initial value

(0)

bit

7

6

5

4

3

2

1

0

A/D Data register (lower)

Address: 00002E^H

D7

D6

D5

D4

D3

D2

D1

D0

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

Read/Write

Initial value

35

MB90660A Series

(2) Block Diagram

AVCC

AVR

AV^SS

D/A converter

MPX

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Sequential

comparison register

Comparator

Sample and

hold circuits

Data register

ADCR0, 1

A/D control register 1

A/D control register 2

ADCS0, 1

Trigger start

Timer start

ATG

Operation clock

Multi-function timer

(RT0 output)

Pre-scalar

Peripheral clock

36

MB90660A Series

5. PWM Timer

This block, which is an 8-bit reload timer module, outputs the pulse width modulation (PWM) using pulse output

control corresponding to the timer operation.

In terms of hardware, this block possesses an 8-bit down counter, two 8-bit reload registers for setting “L” width

and “H” width, a control register, external pulse output pin, and interrupt output circuit to achieve the following

functions.

• PWM output operation : Pulse waves of any period and duty factor are output.

This block can also be used as a D/A converter with an external circuit.

Interrupt requests can be output based on counter underﬂow.

(1) Register Conﬁguration

PWM operation mode

(Functions)

8 bits

control register

Address: 000020^H

PWMC (R/W) Operation mode control

PWM reload register

000022H

PRLL (R/W) Hold “L” pulse width reload value

000023H

PRLH (R/W) Hold “H” pulse width reload value

(2) Block Diagram

PWM

Output enabled

(Port)

TBT output main clock divided by 4

TBT output main clock divided by 512

TBT: Timebase timer

PWMO

Output latch

Clear

Reverse

PEN

PCNT

(down counter)

IRQ

Count clock

selection

Reload

L/H selector

L/H select

PRLL

PRLH

PRLBH

Operation mode

control

PWMC

F²MC-16 bus

37

MB90660A Series

6. 16-bit Reload Timer (with Event Count Function)

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, control register, and 4 timer

pins (I/O set by timer pin select register). Three internal clocks and an external clock can be selected as input

clocks.A toggle output waveform is output at the output pin (TOT) in reload mode, while a square wave indicating

that the timer is counting is output at the output pin in single-shot mode. The input pin (TIN) can be used for

event input in even count mode, and for trigger input or gate input in internal clock mode.

This product has this timer built into four channels.

(1) Register Conﬁguration

Control status register (upper)

bit

15

14

13

12

11

10

9

8

: channel 0 000031^H

: channel 1 000035H

: channels 2 000039H

: channels 3 00003DH

Address

–

CSL1 CSL0 MOD2 MOD1

(–)

(–) (R/W) (R/W) (R/W) (R/W)

(–) (0) (0) (0) (0)

Read/Write

Initial value

Control status register (lower)

Address: channel 0 000030^H

: channel 1 000034H

: channels 2 000038H

: channels 3 00003CH

Read/Write

7

6

5

4

3

2

1

0

MOD0 Reserved OUTL RELD INTE UF CNTE TRG

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

TMCSR

0 to 3

(0)

Initial value

16-bit timer register (upper)

16-bit reload register (upper)

15

14

13

12

11

10

9

8

Address

: channel 0 000033^H

: channel 1 000037H

: channels 2 00003BH

: channels 3 00003FH

Read/Write

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(X) (X) (X) (X) (X) (X) (X) (X)

Initial value

16-bit timer register (lower)

16-bit reload register (lower)

Address: channel 0 000032H

: channel 1 000036H

bit

7

6

5

4

3

2

1

0

TMR/

TMRLR

0 to 3

: channels 2 00003AH

: channels 3 00003EH

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(X)

15

–

(X)

11

–

(X)

bit

14

13

12

10

9

8

Timer pin control register (upper)

Address: 000057^H

OTE3 CSB3 CSA3

OTE2 CSB2 CSA2

(–) (R/W) (R/W) (R/W) (–) (R/W) (R/W) (R/W)

Read/Write

Initial value

(–)

(0)

(1)

(–)

(0)

(1)

(0)

7

6

5

4

3

2

1

0

Timer pin control register (lower)

Address: 000056H

–

OTE1 CSB1 CSA1

–

OTE0 CSB0 CSA0

TPCR

(–) (R/W) (R/W) (R/W) (–) (R/W) (R/W) (R/W)

(–) (0) (0) (1) (–) (0) (0) (0)

Read/Write

Initial value

38

MB90660A Series

(2) Block Diagram

16

16-bit reload register

8

Reload

RELD

UF

16-bit down counter

16

OUTL

INTE

2

OUT

CTL

GATE

UF

IRQ

CSL1

Clock selector

CNTE

TRG

CSL0

Clear

I²OSCLR

Trigger

2

IN CTL

TIN

EXCK

3

TOT

φ

Prescaler

clear

–

2¹2³2⁵

MOD2

Serial baud rate

(channel 0 only)

MOD1

MOD0

Peripheral clock

3

I/O pins for timer*

TIM0

16-bit reload timer

Channel 0

TIN0

TOT0

16-bit reload timer

Channel 1

TIN1

TOT1

TIM1

TIM2

TIM3

16-bit reload timer

Channel 2

TIN2

TOT2

16-bit reload timer

Channel 3

TIN3

TOT3

* : Timer channel and direction (I/O) can be selected for each pin.

39

MB90660A Series

7. External Interrupts

In addition to “H” and “L”, rising and falling edge can be selected as the external interrupt level for a total of four

interrupt level types.

(1) Register Conﬁguration

bit

7

6

5

4

3

2

1

0

Interrupt enable register

Address: 000028H

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

ENIR

EIRR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

15

(0)

14

(0)

13

(0)

12

(0)

11

(0)

10

(0)

9

(0)

8

Interrupt source register

Address: 000029H

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

15

(0)

14

(0)

13

(0)

12

(0)

11

(0)

10

(0)

9

(0)

8

Request level setting register (upper)

Address: 00002BH

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

7

(0)

6

(0)

5

(0)

4

(0)

3

(0)

2

(0)

1

(0)

0

bit

Request level setting register (lower)

Address: 00002AH

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

ELVR

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

(2) Block Diagram

8

Gate

IRQ

Interrupt enable register

Source F/F

Edge detector

Request input

8

Interrupt source register

Request level setting register

16

40

MB90660A Series

8. Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate an interrupt for task switching. If this module is

used, an interrupt request to the F²MC-16L CPU can be generated or cancelled by software.

(1) Register Conﬁguration

Delayed interrupt request

generation/cancel register

bit

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

R0

DIRR

Address

: 000009^H

Read/Write

Initial value

(–)

(–) (R/W)

(–) (0)

The DIRR register controls the generation and cancellation of delayed interrupt requests. A delayed interrupt

request is generated when “1” is written to this register, while a delayed interrupt request is cancelled when “0”

is written here. Request cancel status results upon reset. Although either “0” or “1” may be written into reserved

bits, we recommend using the set bit and clear bit instructions when accessing this register in consideration of

possible future extensions.

(2) Block Diagram

Delayed interrupt source generation/

cancel decoder

Source latch

41

MB90660A Series

9. Watchdog Timer and Timebase Timer Functions

The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit timebase timer as

the clock source, a control register, and a watchdog reset controller.

In addition to an 18-bit timer, the timebase timer consists of a circuit for controlling interval interrupts. Note that

the timebase timer uses the main clock regardless of the status of the MCS bit within the CKSCR register.

(1) Register Conﬁguration

bit

7

6

–

5

4

3

2

1

0

Watchdog timer

control register

PONR

WRST ERST SRST WTE WT1 WT0

WDTC

TBTC

Address

: 0000A8^H

(R)

(X)

(–)

(R)

(X)

(R)

(X)

(R)

(X)

(W)

(1)

(W)

(1)

(W)

(1)

Read/Write

Initial value

bit

15

14

–

13

–

12

11

10

9

8

Timebase timer

control register

: 0000A9^H

Reserved

TBIE TBOF TBR TBC1 TBC0

Address

Read/Write

Initial value

(–)

(1)

(–)

(–) (R/W) (R/W) (W) (R/W) (R/W)

(–)

(0)

(1)

(0)

(2) Block Diagram

Main clock

(OSC oscillation)

TBTC

2¹²

Clock input

2¹⁴

2²

2⁹

TBC1

TBC0

TBR

Selector

2¹⁶

2¹⁹

to PWM timer

Timebase timer

2¹²2¹⁴2¹⁶2¹⁹

TBTRES

S

Q R

TBIE

TBOF

AND

Timebase

interrupt

WDTC

WT1

2-bit counter

OF

Watchdog reset

generator

to WDGRST

internal reset

generator

Selector

WT0

WTE

CLR

PONR

WRST

ERST

SRST

from power-on generator

RST pin

from RST bit of

STBYC register

42

MB90660A Series

10. Low Power Consumption Controller (CPU intermittent operation function, stable oscillation

wait time, and clock multiplier function)

The following operation modes are available: PLL clock mode, PLL sleep mode, clock mode, main clock mode,

main sleep mode and stop mode. Operation modes other than PLL clock mode are classiﬁed as low power

consumption modes.

Main clock mode and main sleep mode are modes where the microcontroller operates using the main clock

(OSC oscillation clock) only. In these modes, the main clock divided by two is used as the operation clock and

the PLL clock (VCO oscillation clock) is stopped.

In PLL sleep mode and main sleep mode, only the operation clock of the CPU is stopped, while operations

besides the CPU clock continue.

In clock mode, only the timebase timer is allowed to operate.

In stop mode, oscillation is stopped, allowing data to be held at the lowest power consumption possible.

The CPU intermittent operation function causes the clock provided to the CPU to function intermittently when

accessing registers, internal memory, internal resources and the external bus. This allows processing to be

performed at lower power consumption by reducing the CPU execution speed while continuing to provide a high

speed clock to internal resources.

The PLL clock multiplier can be selected as 1, 2, 3 or 4 using the CS1 and CS0 bits.

The stable oscillation wait time for the main clock when stop mode is cancelled can be set using the WS1 and

WS0 bits.

(1) Register Conﬁguration

bit

7

6

5

4

3

2

1

0

Low power consumption mode

control register

STP SLP SPL RST Reserved CG1 CG0 Reserved

LPMCR

CKSCR

: 0000A0^H

Address

(W)

(0)

(W) (R/W) (W)

(0)

(–) (R/W) (R/W) (–)

(1)

Read/Write

Initial value

(0)

(1)

(0)

15

14

13

12

11

10

9

8

Clock selection register

Address: 0000A1H

Reserved MCM WS1 WS0 Reserved MCS CS1 CS0

(–)

(1)

(R) (R/W) (R/W) (–) (R/W) (R/W) (R/W)

(1) (1) (1) (1) (1) (0) (0)

Read/Write

Initial value

43

MB90660A Series

(2) Block Diagram

CKSCR

Main clock

(OSC oscillation)

PLL multiplier

circuit

MCM

MCS

1

2

3

4

2

CPU clock

Clock generator

for CPU

CKSCR

CS1

CPU

Clock selector

CS0

0, 9, 17 or 33

intermittent cycle select

LPMCR

CG1

CPU intermittent

operation function

CG0

Cycle count selector

Peripheral resource

clock

Clock generator

for peripheral

resources

LPMCR

SLP

Standby controller

RST cancel

STP

Interrupt request

or RST

CKSCR

2⁴

2²

2⁹

Clock input

2¹³

2¹⁵

2¹⁸

WS1

WS0

Stable

oscillation

wait time

selector

to PWM timer

Timebase timer

2¹²2¹⁴2¹⁶2¹⁹

LPMCR

SPL

Pin high-impedance controller

Internal reset generator

Pin HI-Z

LPMCR

RST

RST pin

Internal RST

to watchdog timer

WDGRST

44

MB90660A Series

11. Interrupt Controller

The interrupt control register is located within the interrupt controller. Its status conforms to all I/O possessed

by the interrupt function. This register includes the following three functions.

• Sets the interrupt level of the corresponding peripheral resource

• Selects whether to use conventional interrupts or extended intelligent I/O services for the interrupt of the

corresponding peripheral resource

• Selects the channel for the extended intelligent I/O services

(1) Register Conﬁguration

Interrupt control register

bit

15

14

13

12

11

10

9

8

: ICR01 0000B1H

: ICR03 0000B3H

: ICR05 0000B5H

: ICR07 0000B7H

: ICR09 0000B9H

: ICR11 0000BBH

: ICR13 0000BDH

: ICR15 0000BFH

Address

ICS1 ICS0

ICS2

S1

ICR01, 03, 05, 07,

09, 11, 13, 15

ICS3

or

ISE

IL2

IL1

IL0

or

S0

(W)

(0)

(W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/Write

Initial value

(0)

(1)

Interrupt control register

Address: ICR00 0000B0H

: ICR02 0000B2H

bit

7

6

5

4

3

2

1

0

: ICR04 0000B4H

: ICR06 0000B6H

: ICR08 0000B8H

: ICR10 0000BAH

: ICR12 0000BCH

: ICR14 0000BEH

ICS1 ICS0

ICR00, 02, 04, 06,

08, 10, 12, 14

ICS3

or

ISE

IL2

IL1

IL0

ICS2

S1

or

S0

(W)

(0)

(W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (1) (1) (1)

Read/Write

Initial value

Note: Since read-modify-write type instructions can cause a malfunction, do not access using these instructions.

45

MB90660A Series

(2) Block Diagram

4

32 Interrupt request/

I²OS request

Determines interrupt/I²OS

priority level

ISE

IL2

IL1

IL0

(peripheral resource)

(CPU)

Interrupt level

I²OS select

4

3

4

I²OS vector

(CPU)

Selects I²OS vector

ICS3 ICS2 ICS1 ICS0

2

I²OS end condition

Detects I²OS end condition

S1

S0

46

MB90660A Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Rating

(VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

VSS + 7.0

13.0

V^CC

VSS – 0.3

V

Power supply voltage

AV^CC*¹

VAVR*¹

V^PP

VSS – 0.3

V

Programming voltage

Input voltage*²

VSS – 0.3

V

*6

VI

VSS – 0.3

VCC + 0.3

10

V

Output voltage*²

VO

VSS – 0.3

—

V

IOL1

mA

mW

°C

*7

*8

*7

*8

*7

*8

“L” level maximum current*³

IOL2

—

30

IOLAV1

IOLAV2

∑IOLAV1

∑IOLAV2

IOH

—

4

“L” level average output current*⁴

“L” level total average output current*⁵

—

20

—

30

—

60

“H” level maximum output current*³

“H” level average output current*⁴

“H” level total average output current*⁵

Power consumption

—

–10

IOHAV

∑IOHAV

Pd

—

–4

—

–40

—

400

Operating temperature

T^A

–40

–55

+85

Storage temperature

Tstg

+150

*1: AVCC and VAVR must not exceed VCC.

*2: VI and VO must not exceed VCC + 0.3 V.

*3: Maximum output current speciﬁes the peak value of one corresponding pin.

*4: Average output current speciﬁes the average current within a 100 ms interval ﬂowing through one corresponding

pin.

*5: Average total output current speciﬁes the average current within a 100 ms interval ﬂowing through all

corresponding pins.

*6: MD2 pin of MB90P663A

*7: Pins excluding P60/RT1/U, P61/RT2/V, P62/RT3/W, P63/X, P64/Y and P65/Z pins

*8: P60/RT1/U, P61/RT2/V, P62/RT3/W, P63/X, P64/Y and P65/Z pins

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

47

MB90660A Series

2. Recommended Operating Conditions

(VSS = AVSS = 0.0 V)

Ratings

Parameter

Symbol

Unit

Remarks

Min.

2.7

Max.

5.5

VCC

During normal operation

Power supply voltage

V

2.0

5.5

Stop operation status is held

Operating temperature TA

–40

+85

°C

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

48

MB90660A Series

3. DC Characteristics

(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min.

Typ.

Max.

VCC = 4.5 V

IOH = –4.0 mA

VCC – 0.5

—

V

“H” level

output voltage

V^OH

Except P50 to P57

V^CC= 2.7 V

IOH = –1.6 mA

VCC – 0.3

—

0.4

VCC = 4.5 V

IOL = 4.0 mA

V^OL1

Except P60 to P65

VCC = 2.7 V

IOL = 2.0 mA

—

0.4

“L” level

output voltage

VCC = 4.5 V

I^OL= 15.0 mA

—

1.0

V^OL2

P60 to P65

V^CC= 2.7 V

IOL = 2.0 mA

—

0.4

Pins except VIHS,

VIHM

VIH

—

0.7 VCC

VCC + 0.3

“H” level

input voltage

VIHS

VIHM

Hysteresis input pins

—

0.8 VCC

—

VCC + 0.3

V

*

MD pin

VCC – 0.3

Pins except VILS,

VILM

V^IL

—

VSS – 0.3

—

0.3 VCC

V

“L” level

input voltage

VILS

VILM

Hysteresis input pins

—

VSS – 0.3

—

0.2 VCC

V

MD pin

VSS + 0.3

Input leakage

current

VCC = 5.5 V

VSS < VI < VCC

IIL

Except P50 to P57

–10

—

10

µA

Pins for which

pull-up option is

selected

When VCC = 5.0 V

When VCC = 3.0 V

When VCC = 5.0 V

When VCC = 3.0 V

25

40

25

40

—

100

200

400

kΩ

Pull-up

resistor

RPUP

Pins for which

pull-down options

selected

80

Pull-down

resister

RPDN

160

Internal 16 MHz

operation

During normal

operation

ICC

—

50

25

10

70

30

20

mA

When VCC = 5.0 V

Internal 16 MHz

operation

ICCS

ICC

mA During sleep

Supply current

Internal 8 MHz

operation

During normal

mA

operation

When VCC = 3.0 V

Internal 8 MHz

operation

ICCS

I^CCH

CIN

—

5

10

—

mA During sleep

µA During stop

pF

—

TA = 25°C

0.1

10

Input

capacitance

Except AVCC,

AVSS, VCC and VSS

—

Open-drain

output leakage

current

Ileak

P50 to P57

—

0.1

10

µA N channel Tr off

* : Applies to pins P40 to P47, P50 to P57, P60 to P66, DTTI and RST.

49

MB90660A Series

4. AC Characteristics

(1) Clock Timing Values

• Used at VCC = 5.0 V ±10%

(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min.

3

Max.

32

Oscillation frequency

Oscillation cycle time

FC

tC

X0, X1

—

MHz

ns

31.25

333

Frequency ﬂuctuation ratio*

(when locked)

∆f

—

X0

—

10

3

—

5

%

ns

PWH

PWL

Use duty ratio of 30%

to 70% as guideline

Input clock pulse width

Input clock rising and

falling times

tcr

tcf

X0

—

ns

Internal operating clock

frequency

fCP

tCP

—

1.5

62.5

16

666

MHz

ns

Internal operating clock

cycle time

—

* : The frequency ﬂuctuation ratio represents the maximum ﬂuctuation from the central frequency as a percentage

when a multiplier is locked.

+

+α

α

Central frequency f 0

∆ f =

× 100 (%)

f ⁰

–α

–

• Used at V^CC= 2.7 V (minimum)

(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min.

3

Max.

16

Oscillation frequency

Oscillation cycle time

F^C

X0, X1

—

MHz

ns

tC

62.5

333

PWH

PWL

Use duty ratio of 30%

to 70% as guideline

Input clock pulse width

X0

—

20

—

5

ns

Input clock rising and

falling times

tcr

tcf

Internal operating clock

frequency

fCP

tCP

1.5

125

8

MHz

ns

Internal operating clock

cycle time

—

666

50

MB90660A Series

(2) Recommended Resonator Manufacturers

• Sample Application of Piezoelectric Resonator (FAR Family)

X 0

X 1

R

*1

FAR

*1

*2

C 1

C 2

*1: Fujitsu Acoustic Resonator

Temperature

characteristics of

FAR frequency

Initial deviation of

FAR frequency

(T^A= +25°C)

Loading*²

capacitors

FAR part number

Frequency Dumping

(built-in capacitor type)

(MHz)

resistor

(TA = –20°C to +60°C)

FAR-C4CC-02000-L20

FAR-C4SA-04000-M01

FAR-C4CB-04000-M00

FAR-C4CB-08000-M02

FAR-C4CB-12000-M02

FAR-C4CB-16000-M02

FAR-C4CB-20000-L14B

FAR-C4CB-24000-L14A

2.00

4.00

510 Ω

—

±0.5%

—

8.00

—

Built-in

12.00

16.00

19.80

23.76

—

Inquiry: FUJITSU LIMITED

51

MB90660A Series

• Sample Application of Ceramic Resonator

X 0

X 1

R

*

C 1

C 2

• Mask Products

Resonator

Frequency (MHz)

C1 (pF)

C2 (pF)

R

manufacturer*

KBR-2.0MS

PBRC2.00A

KBR-4.0MSA

KBR-4.0MKS

PBRC4.00A

PBRC4.00B

KBR-6.0MSA

KBR-6.0MKS

150

—

2.00

33

680 Ω

—

Built-in

33

Built-in

33

4.00

6.00

Built-in

33

Built-in

33

Built-in

33

Built-in

33

—

Kyocera Corporation

PBRC6.00A

PBRC6.00B

KBR-8.0M

—

Built-in

33

Built-in

33

—

8.00

560 Ω

—

PBRC8.00A

PBRC8.00B

KBR-10.0M

PBRC10.00B

KBR-12.0M

PBRC12.00B

33

Built-in

33

Built-in

33

—

330 Ω

680 Ω

330 Ω

680 Ω

(Continued)

10.00

12.00

Built-in

33

Built-in

33

Built-in

52

MB90660A Series

(Continued)

Resonator

manufacturer*

Resonator

Frequency (MHz)

C1 (pF)

C2 (pF)

R

CSA2.00MG040

CST2.00MG040

CSA4.00MG040

CST4.00MGW040

CSA6.00MG

100

Built-in

100

Built-in

100

—

2.00

4.00

Built-in

30

Built-in

30

6.00

CST6.00MGW

CSA8.00MTZ

Built-in

30

Built-in

30

8.00

CST8.00MTW

Built-in

30

Built-in

30

Murata Mfg. Co., Ltd. CSA10.00MTZ

CST10.00MTW

10.00

12.00

16.00

Built-in

30

Built-in

30

CSA12.00MTZ

CST12.00MTW

Built-in

15

Built-in

15

CSA16.00MXZ040

CST16.00MXW0C3

CSA20.00MXZ040

CSA24.00MXZ040

CSA32.00MXZ040

Built-in

10

Built-in

10

20.00

24.00

32.00

5

Inquiry: Kyocera Corporation

• AVX Corporation

North American Sales Headquarters: TEL 1-803-448-9411

• AVX Limited

European Sales Headquarters: TEL 44-1252-770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters: TEL 852-363-3303

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL 1-404-436-1300

• Murata Europe Management GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

53

MB90660A Series

• Clock Timing

tC

0.8 VCC

0.2 VCC

PWH

PWL

tcr

tcf

• PLL Operation Warranty Range

Relationship between clock frequency and supply voltage

5.5

PLL operation

warranty range

Normal operating

range

4.5

3.3

2.7

f^CP

(MHz)

0 1.5

3

8

16

Internal clock

Relationship between oscillator frequency and internal operating clock frequency

Multiplied Multiplied

No multiplication

by 4

by 3

16

Multiplied

by 2

Multiplied by 1

12

9

8

4

F^C

(MHz)

0

3 4

8

16

Oscillation clock

24

32

Note: Even in the case of evaluation tool, operation is assured down to 2.7 V.

AC speciﬁcation values are speciﬁed for the measured reference voltages given below.

• Input Signal Waveforms

Hysteresis input pin

0.8 VCC

• Output Signal Waveforms

Output pin

2.4 V

0.2 VCC

0.8 V

Pins except hysteresis input and MD input

0.7 VCC

0.3 VCC

54

MB90660A Series

(3) Reset Input Speciﬁcations

(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Reset input time

Symbol Pin name Conditions

t^RSTLRST

Unit

Remarks

Min.

Max.

—

16

—

Machine cycle

tRSTL

RST

0.2 VCC

(4) Power-On Reset

Parameter

(VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name Conditions

Unit

Remarks

Min.

Max.

Power supply rise time

Power supply cutoff time

t^R

VCC

—

30

ms

*

—

Due to repeated

operations

tOFF

1

—

* : VCC should be lower than 0.2 V before power supply rise.

Notes: • The above speciﬁcations are the numeric values needed for causing a power-on reset.

• There are built in resisters initialized only by power on reset in the device.

Turn on power supply according to the speciﬁcation at the point of this initialization.

t^R

2.7 V

VCC

0.2 V

An abrupt change in the supply voltage may activate power-on reset.

If the supply voltage must be changed during operation, the voltage change should be smooth without

sudden fluctuations.

5.0 V

VCC

A rise time of 50 mV/ms or less

is recommended.

2.0 V

RAM data maintained

VSS

55

MB90660A Series

(5) UART timing

(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

tSCYC

Conditions

Unit

Remarks

name

Min.

8 tCP

–80

Max.

—

Serial clock cycle time

SCK ↓ → SOT delay time

SCK

—

ns

VCC = 5.0 V ±10%

80

SCK

SOT

tSLOV

VCC = 3.0 V ±10% –120

120

—

CL = 80 pF + 1 TTL

for internal clock

operation output

VCC = 5.0 V ±10%

VCC = 3.0 V ±10%

VCC = 5.0 V ±10%

VCC = 3.0 V ±10%

100

200

60

SCK

SIN

Valid SIN → SCK ↑

tIVSH

tSHIX

—

SCK ↑ → valid SIN hold

SCK

SIN

time

120

—

Serial clock

H pulse width

tSHSL

tSLSH

SCK

—

4 tCP

—

ns

Serial clock

L pulse width

CL = 80 pF + 1 TTL

for external clock

operation output

VCC = 5.0 V ±10%

VCC = 3.0 V ±10%

VCC = 5.0 V ±10%

VCC = 3.0 V ±10%

VCC = 5.0 V ±10%

VCC = 3.0 V ±10%

—

150

200

—

ns

SCK

SOT

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

tSLOV

tIVSH

tSHIX

60

SCK

SIN

120

60

—

SCK ↑ → valid SIN hold

time

SCK

SIN

120

—

Notes: • These are AC speciﬁcation during CLK synchronous mode.

• CL is the load capacity value assigned to the pin during testing.

• tCP is the machine cycle time (unit: ns).

56

MB90660A Series

• Internal Shift Clock Mode

tSCYC

2.4 V

SCK

SOT

0.8 V

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SIN

• External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK

SOT

0.2 VCC

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SIN

57

MB90660A Series

(6) Timer input timing

(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min.

Max.

tTIWH

tTIWL

Input pulse width

TIM0 to TIM3

—

4 tCP

—

ns

0.7 VCC

0.3 VCC

tTIWH

tTIWL

(7) Trigger input timing

Parameter

(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol

Pin name

Conditions

Unit

Remarks

Min.

Max.

ATG, DTTI, TRG,

INT4 to INT7

5 tCP

—

ns

t^TRGH

tTRGL

Input pulse width

—

ATG, DTTI, TRG,

INT0 to INT3

5 tCP

—

• INT4 to INT7

0.7 VCC

0.3 VCC

tTRGH

tTRGL

• INT0 to INT3

0.7 VCC

0.8 VCC

0.2 VCC

tTRGH

tTRGL

58

MB90660A Series

5. Electrical Characteristics of A/D Converter

(AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V ≤ AVR, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name

Unit

Min.

—

Typ.

10

Max.

10

Resolution

Total error

—

bit

—

±3.0

±2.0

±1.5

+2.5

LSB

Linearity error

—

Differential linearity error

Zero transition voltage

—

V^OT

AN0 to AN7

–1.5

+0.5

Full-scale transition voltage

VFST

AN0 to AN7 AVR – 4.5 AVR – 1.5 AVR + 0.5 LSB

6.125^*1

12.25^*2

—

0.1

—

3

—

µs

Conversion time

—

Analog port input voltage

Analog input voltage

Reference voltage

I^AIN

AN0 to AN7

AVR

10

µA

V

VAIN

0

AVR

AVCC

—

3.5

—

V

IA

AVCC

mA

µA

LSB

Supply current

5^*3

I^AH

I^R

AVCC

—

200

—

AVR

—

5^*3

Reference voltage supply current

Variation between channels

I^RH

AVR

—

AN0 to AN7

—

4

*1: VCC = 5.0 V ±10% at 16 MHz machine clock

*2: VCC = 3.0 V ±10% at 8 MHz machine clock

*3: Current when CPU is stopped and A/D converter is not operating (when VCC = AVCC = AVR = 5.0 V)

Notes: • The relative error becomes larger as the reference voltage (AVR) becomes smaller.

• Be sure to use the A/D converter only when output impedance of the external analog input circuit meets

the following conditions.

External circuit output impedance < approx. 7 kΩ

• If the output impedance of the external circuit is too high, there may not be enough time to sample the

analog voltage. (Sampling time = 3.75 µs @4 MHz (equivalent to internal 16 MHz when multiplying by 4))

• For an external capacitor to be provided outside the chip, its capacity should desirably be thousands times

larger than of the capacity in the chip taking in consideration the inﬂuence of the capacity destribution of

the external and internal capacitors.

• Figure Model of Analog Input Circuit

Sample and hold circuit

C0

Analog input

Comparator

R^ON1

RON2

RON3

RON4

C1

RON1 = Approx. 1.5 kΩ (VCC = 5.0 V)

R^ON2= Approx. 0.5 kΩ (VCC = 5.0 V)

R^ON3= Approx. 0.5 kΩ (VCC = 5.0 V)

R^ON4= Approx. 0.5 kΩ (VCC = 5.0 V)

C⁰= Approx. 60 pF

C¹= Approx. 4 pF

Note: Use the values shown here as guidelines.

59

MB90660A Series

6. Deﬁnitions of A/D Converter Terms

Resolution

: Analog transition observed with an A/D converter.

Analog voltage can be divided in 1024 = 2¹⁰parts at 10-bit resolution.

Total error

: This refers to the difference between actual and logical values. This error is

caused by offset errors, gain errors, non-linearity errors and noise.

Linearity error

: Deviation of the line drawn between the zero transition point (00 0000 0000 ↔

00 0000 0001) and the full-scale transition point (11 1111 1110 ↔ 11 1111

1111) for the device from actual conversion characteristics.

Differential linearity error

: Deviation from ideal input voltage required to shift output code by one LSB.

Digital output

11 1111 1111

11 1111 1110

•

(1LSB × N + VOT)

Linearity error

00 0000 0010

00 0000 0001

00 0000 0000

V^OT

Analog input

VNT V(N + 1)T

VFST

VFST – VOT

1LSB =

1022

VNT – (1LSB × N + VOT )

1LSB

Linearity error =

(LSB)

V(N + 1) T – VNT

– 1 (LSB)

Differential linearity error =

1LSB

60

MB90660A Series

■ EXAMPLES CHARACTERISTICS

(1) “H” Level Output Voltage

(2) “L” Level Output Voltage

VOH – IOH

VOH (V)

VOL – IOL

VOL (V)

1.0

V^CC= 2.7 V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.9

TA = +25°C

V^CC= 2.7 V

V^CC= 3.0 V

VCC = 3.5 V

V^CC= 4.0 V

V^CC= 4.5 V

V^CC= 5.0 V

V^CC= 3.0 V

V^CC= 3.5 V

V^CC= 4.0 V

V^CC= 4.5 V

V^CC= 5.0 V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

–2

–4

–6

–8

I^OH(mA)

0

2

4

6

8

I^OL(mA)

(3) “L” Level Output Voltage (P60 to P65)

(4) “H” Level Input Voltage/“L” Level Input

Voltage

VIN – VCC (CMOS input)

TA = +25°C

V^IN(V)

5.0

VOL – IOL

VOL (V)

1.0

VCC = 2.7 V

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

TA = +25°C

VCC = 3.0 V

VCC = 3.5 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

0

5

10

15

20

25

I^OL(mA)

0

2

3

4

5

6

V^CC(V)

(5) “H” Level Input Voltage/“L” Level Input Voltage

VIN – VCC (Hysteresis input)

TA = +25°C

V ^IN(V)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIHS

VILS

VIHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

VILS: Threshold when input voltage in hysteresis

characteristics is set to “L” level

0

2

3

4

5

6

VCC (V)

(Continued)

61

MB90660A Series

(6) Power Supply Current (fcp = Internal frequency)

ICC (mA)

70

ICC – VCC

I^CCS(mA)

25

ICCS – VCC

TA = +25°C

f^CP= 16 MHz

60

50

40

30

20

10

0

20

15

10

5

f^CP= 12.5 MHz

f^CP= 16 MHz

f^CP= 12.5 MHz

f^CP= 8 MHz

f^CP= 4 MHz

f^CP= 8 MHz

f^CP= 4 MHz

0

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

I ^A(mA)

6.0

IA – AVCC

I R (mA)

0.30

IR – AVR

TA = +25°C

f^CP= 16 MHz

TA = +25°C

f^CP= 16 MHz

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0.20

0.10

0

3.0

4.0

5.0

6.0

AV CC (V)

3.0

4.0

5.0

6.0

AVR (V)

(7) Pull-up Resistor

R – VCC

R (kΩ)

1000

TA = +25°C

100

10

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V^CC(V)

62

MB90660A Series

■ INSTRUCTIONS (340 INSTRUCTIONS)

Table 1 Explanation of Items in Tables of Instructions

Meaning

Upper-case letters and symbols: Represented as they appear in assembler.

Item

Mnemonic

Lower-case letters: Replaced when described in assembler.

Numbers after lower-case letters:Indicate the bit width within the instruction.

#

~

Indicates the number of bytes.

Indicates the number of cycles.

m: When branching

n : When not branching

See Table 4 for details about meanings of other letters in items.

RG

B

Indicates the number of accesses to the register during execution of the instruction.

It is used calculate a correction value for intermittent operation of CPU.

Indicates the correction value for calculating the number of actual cycles during execution of the

instruction. (Table 5)

The number of actual cycles during execution of the instruction is the correction value summed

with the value in the “~” column.

Operation

LH

Indicates the operation of instruction.

Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.

Z : Transfers “0”.

X : Extends with a sign before transferring.

– : Transfers nothing.

AH

Indicates special operations involving the upper 16 bits in the accumulator.

* : Transfers from AL to AH.

– : No transfer.

Z : Transfers 00^Hto AH.

X : Transfers 00H or FFH to AH by signing and extending AL.

I

S

Indicates the status of each of the following ﬂags: I (interrupt enable), S (stack), T (sticky bit),

N (negative), Z (zero), V (overﬂow), and C (carry).

* : Changes due to execution of instruction.

– : No change.

S : Set by execution of instruction.

R : Reset by execution of instruction.

T

N

Z

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction. (a single instruction that

reads data from memory, etc., processes the data, and then writes the result to memory.)

* : Instruction is a read-modify-write instruction.

– : Instruction is not a read-modify-write instruction.

Note: A read-modify-write instruction cannot be used on addresses that have different

meanings depending on whether they are read or written.

63

MB90660A Series

Table 2 Explanation of Symbols in Tables of Instructions

Meaning

Symbol

A

32-bit accumulator

The bit length varies according to the instruction.

Byte : Lower 8 bits of AL

Word : 16 bits of AL

Long : 32 bits of AL:AH

AH

AL

Upper 16 bits of A

Lower 16 bits of A

SP

PC

Stack pointer (USP or SSP)

Program counter

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB, SPB

DTB, ADB, SSB, USB, DPR, SPB

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

Compact direct addressing

addr16

addr24

ad24 0 to 15

ad24 16 to 23

Direct addressing

Physical direct addressing

Bit 0 to bit 15 of addr24

Bit 16 to bit 23 of addr24

io

I/O area (000000^Hto 0000FFH)

imm4

imm8

4-bit immediate data

8-bit immediate data

imm16

imm32

ext (imm8)

16-bit immediate data

32-bit immediate data

16-bit data signed and extended from 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

bp

Bit offset

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

( )b

Bit address

(Continued)

64

MB90660A Series

(Continued)

Symbol

Meaning

rel

Branch speciﬁcation relative to PC

ear

eam

Effective addressing (codes 00 to 07)

Effective addressing (codes 08 to 1F)

rlst

Register list

Table 3 Effective Address Fields

Address format

Number of bytes in address

extension *

Code

Notation

00

01

02

03

04

05

06

07

R0

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

RL0 Register direct

(RL0)

RL1 “ea” corresponds to byte, word, and

(RL1) long-word types, starting from the

RL2 left

(RL2)

RL3

R1

R2

R3

R4

R5

R6

R7

—

(RL3)

08

09

0A

0B

@RW0

Register indirect

@RW1

@RW2

@RW3

0

0C

0D

0E

0F

@RW0 +

@RW1 +

@RW2 +

@RW3 +

Register indirect with post-increment

10

11

12

13

14

15

16

17

@RW0 + disp8

@RW1 + disp8

@RW2 + disp8

@RW3 + disp8

@RW4 + disp8

@RW5 + disp8

@RW6 + disp8

@RW7 + disp8

Register indirect with 8-bit

displacement

1

2

18

19

1A

1B

@RW0 + disp16

@RW1 + disp16

@RW2 + disp16

@RW3 + disp16

Register indirect with 16-bit

displacement

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)

column in the tables of instructions.

65

MB90660A Series

Table 4 Number of Execution Cycles for Each Type of Addressing

(a)

Number of register

accesses for each type of

addressing

Code

Operand

Number of execution cycles

for each type of addressing

Ri

RWi

RLi

00 to 07

Listed in tables of instructions Listed in tables of instructions

08 to 0B

0C to 0F

10 to 17

18 to 1B

@RWj

2

4

2

1

2

1

@RWj +

@RWi + disp8

@RWj + disp16

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

4

2

1

2

0

Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.

Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles

(b) byte

(c) word

(d) long

Operand

Number of Number of Number of Number of Number of Number of

cycles

access

cycles

access

cycles

access

Internal register

+0

1

+0

1

+0

2

Internal memory even address

Internal memory odd address

+0

1

+0

+2

1

2

+0

+4

2

4

Even address on external data bus (16 bits)

Odd address on external data bus (16 bits)

+1

1

+1

+4

1

2

+2

+8

2

4

External data bus (8 bits)

+1

1

+4

2

+8

4

Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)

in the tables of instructions.

• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction

Internal memory

Byte boundary

Word boundary

—

+3

+2

+3

—

External data bus (16 bits)

External data bus (8 bits)

Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

• Because instruction execution is not slowed down by all program fetches in actuality, these correction

values should be used for “worst case” calculations.

66

MB90660A Series

Table 7 Transfer Instructions (Byte) [41 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V C RMW

MOV

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RLi+disp8

2

3

1

2

3

4

2

0

1

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

Z

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a) 0

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

1

3

2

3

10

1

0

2

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ← ((RLi)+disp8)

MOVN A, #imm4

0

byte (A) ← imm4

R

MOVX A, dir

MOVX A, addr16

MOVX A, Ri

MOVX A, ear

MOVX A, eam

MOVX A, io

MOVX A, #imm8

MOVX A, @A

MOVX A,@RWi+disp8

MOVX A, @RLi+disp8

2

3

2

3

4

2

0

1

(b) byte (A) ← (dir)

(b) byte (A) ← (addr16)

X

*

–

*

–

*

–

0

byte (A) ← (Ri)

byte (A) ← (ear)

2+ 3+ (a) 0

(b) byte (A) ← (eam)

(b) byte (A) ← (io)

2

3

2

3

5

10

0

1

2

0

byte (A) ← imm8

(b) byte (A) ← ((A))

(b) byte (A) ← ((RWi)+disp8)

(b) byte (A) ← ((RLi)+disp8)

MOV

dir, A

addr16, A

Ri, A

ear, A

eam, A

io, A

@RLi+disp8, A

Ri, ear

Ri, eam

ear, Ri

eam, Ri

Ri, #imm8

io, #imm8

dir, #imm8

ear, #imm8

eam, #imm8

@AL, AH

2

3

1

2

3

4

2

0

1

(b) byte (dir) ← (A)

(b) byte (addr16) ← (A)

–

*

–

*

–

*

–

*

–

*

–

0

byte (Ri) ← (A)

byte (ear) ← (A)

2+ 3+ (a) 0

(b) byte (eam) ← (A)

(b) byte (io) ← (A)

(b) byte ((RLi) +disp8) ← (A)

2

3

2

3

10

3

0

2

0

byte (Ri) ← (ear)

(b) byte (Ri) ← (eam)

byte (ear) ← (Ri)

(b) byte (eam) ← (Ri)

byte (Ri) ← imm8

2+ 4+ (a) 1

2

2+ 5+ (a) 1

2

3

4

2

0

2

5

2

1

0

1

0

(b) byte (io) ← imm8

(b) byte (dir) ← imm8

0

byte (ear) ← imm8

3+ 4+ (a) 0

2

(b) byte (eam) ← imm8

(b) byte ((A)) ← (AH)

3

0

/MOV @A, T

XCH

A, ear

2

4

2

0

byte (A) ↔ (ear)

Z

–

A, eam

Ri, ear

Ri, eam

2+ 5+ (a) 0 2× (b) byte (A) ↔ (eam)

byte (Ri) ↔ (ear)

2+ 9+ (a) 2 2× (b) byte (Ri) ↔ (eam)

2

7

4

0

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

67

MB90660A Series

Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]

Mnemonic

MOVW A, dir

MOVW A, addr16

MOVW A, SP

MOVW A, RWi

MOVW A, ear

MOVW A, eam

MOVW A, io

MOVW A, @A

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V C RMW

2

3

1

2

3

4

1

2

0

1

(c) word (A) ← (dir)

(c) word (A) ← (addr16)

0

(c) word (A) ← (eam)

(c) word (A) ← (io)

(c) word (A) ← ((A))

–

*

–

*

–

*

–

word (A) ← (SP)

word (A) ← (RWi)

word (A) ← (ear)

2+ 3+ (a) 0

2

3

2

3

2

5

10

0

1

2

MOVW A, #imm16

MOVW A, @RWi+disp8

MOVW A, @RLi+disp8

0

word (A) ← imm16

(c) word (A) ← ((RWi) +disp8)

(c) word (A) ← ((RLi) +disp8)

MOVW dir, A

MOVW addr16, A

MOVW SP, A

MOVW RWi, A

MOVW ear, A

MOVW eam, A

MOVW io, A

MOVW @RWi+disp8, A

MOVW @RLi+disp8, A

MOVW RWi, ear

MOVW RWi, eam

MOVW ear, RWi

MOVW eam, RWi

MOVW RWi, #imm16

MOVW io, #imm16

MOVW ear, #imm16

MOVW eam, #imm16

2

3

1

2

3

4

1

2

0

1

(c) word (dir) ← (A)

(c) word (addr16) ← (A)

–

*

–

*

–

*

–

*

–

0

word (SP) ← (A)

word (RWi) ← (A)

word (ear) ← (A)

2+ 3+ (a) 0

(c) word (eam) ← (A)

(c) word (io) ← (A)

(c) word ((RWi) +disp8) ← (A)

(c) word ((RLi) +disp8) ← (A)

(0) word (RWi) ← (ear)

(c) word (RWi) ← (eam)

2

3

2

3

5

10

3

0

1

2

2+ 4+ (a) 1

2

2+ 5+ (a) 1

3

4

2

0

word (ear) ← (RWi)

(c) word (eam) ← (RWi)

word (RWi) ← imm16

(c) word (io) ← imm16

word (ear) ← imm16

2

5

2

1

0

1

0

4+ 4+ (a) 0

(c) word (eam) ← imm16

MOVW AL, AH

/MOVW @A, T

2

3

0

(c) word ((A)) ← (AH)

–

*

–

XCHW A, ear

2

4

2

0

word (A) ↔ (ear)

–

XCHW A, eam

XCHW RWi, ear

XCHW RWi, eam

2+ 5+ (a) 0 2× (c) word (A) ↔ (eam)

word (RWi) ↔ (ear)

2+ 9+ (a) 2 2× (c) word (RWi) ↔ (eam)

2

7

4

0

MOVL A, ear

MOVL A, eam

MOVL A, #imm32

2

4

2

0

long (A) ← (ear)

–

*

–

2+ 5+ (a) 0

5

(d) long (A) ← (eam)

0

3

0

long (A) ← imm32

long (ear) ← (A)

MOVL ear, A

MOVL eam, A

2

4

2

0

–

*

–

2+ 5+ (a) 0

(d) long (eam) ← (A)

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

68

MB90660A Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V C RMW

ADD

A,#imm8

A, dir

A, ear

A, eam

ear, A

eam, A

A

2

5

3

0

1

0

byte (A) ← (A) +imm8

Z

–

Z

–

*

–

*

–

*

ADD

ADDC

ADDC A, ear

ADDC A, eam

ADDDC A

SUB

SUBC

SUBC A, ear

SUBC A, eam

SUBDC A

(b) byte (A) ← (A) +(dir)

byte (A) ← (A) +(ear)

(b) byte (A) ← (A) +(eam)

byte (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) + (A)

0

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (A) ← (AH) + (AL) + (C)

byte (A) ← (A) + (ear) + (C)

2+ 4+ (a) 0

(b) byte (A) ← (A) + (eam) + (C)

0

1

2

3

2

5

3

0

1

byte (A) ← (AH) + (AL) + (C) (decimal) Z

byte (A) ← (A) –imm8

A, #imm8

A, dir

A, ear

A, eam

ear, A

eam, A

A

Z

–

Z

(b) byte (A) ← (A) – (dir)

byte (A) ← (A) – (ear)

(b) byte (A) ← (A) – (eam)

byte (ear) ← (ear) – (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) – (A)

0

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (A) ← (AH) – (AL) – (C)

byte (A) ← (A) – (ear) – (C)

–

2+ 4+ (a) 0

1

(b) byte (A) ← (A) – (eam) – (C)

0

3

0

byte (A) ← (AH) – (AL) – (C) (decimal) Z

ADDW A

1

2

3

0

1

0

word (A) ← (AH) + (AL)

word (A) ← (A) +(ear)

–

*

–

*

–

*

ADDW A, ear

ADDW A, eam

ADDW A, #imm16

ADDW ear, A

ADDW eam, A

ADDCWA, ear

ADDCWA, eam

SUBW A

SUBW A, ear

SUBW A, eam

SUBW A, #imm16

SUBW ear, A

SUBW eam, A

SUBCW A, ear

SUBCW A, eam

2+ 4+ (a) 0

3

2

(c) word (A) ← (A) +(eam)

0

2

3

0

2

word (A) ← (A) +imm16

word (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) + (A)

word (A) ← (A) + (ear) + (C)

(c) word (A) ← (A) + (eam) + (C)

2

3

1

0

2+ 4+ (a) 0

1

2

3

0

1

0

word (A) ← (AH) – (AL)

word (A) ← (A) – (ear)

2+ 4+ (a) 0

3

2

(c) word (A) ← (A) – (eam)

0

2

3

0

2

word (A) ← (A) –imm16

word (ear) ← (ear) – (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) – (A)

word (A) ← (A) – (ear) – (C)

(c) word (A) ← (A) – (eam) – (C)

2

3

1

0

–

2+ 4+ (a) 0

ADDL A, ear

ADDL A, eam

ADDL A, #imm32

SUBL A, ear

SUBL A, eam

2

6

2

0

long (A) ← (A) + (ear)

–

*

–

2+ 7+ (a) 0

5

2

2+ 7+ (a) 0

5

(d) long (A) ← (A) + (eam)

0

4

6

0

2

long (A) ← (A) +imm32

long (A) ← (A) – (ear)

(d) long (A) ← (A) – (eam)

long (A) ← (A) –imm32

SUBL

A, #imm32

4

0

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

69

MB90660A Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V

C RMW

INC

ear

eam

2

0

byte (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1

DEC

ear

eam

2

3

2

0

byte (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1

INCW ear

INCW eam

2

3

2

0

word (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1

DECW ear

DECW eam

2

3

2

0

word (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1

INCL ear

INCL eam

2

7

4

0

long (ear) ← (ear) +1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1

DECL ear

DECL eam

2

7

4

0

long (ear) ← (ear) –1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V

C RMW

CMP

A

1

2

1

2

0

1

0

byte (AH) – (AL)

byte (A) ← (ear)

–

*

–

CMP

A, ear

A, eam

A, #imm8

2+ 3+ (a) 0

2

(b) byte (A) ← (eam)

0

2

0

byte (A) ← imm8

CMPW A

1

2

1

2

0

1

0

word (AH) – (AL)

word (A) ← (ear)

–

*

–

CMPW A, ear

CMPW A, eam

CMPW A, #imm16

2+ 3+ (a) 0

3

(c) word (A) ← (eam)

0

2

0

word (A) ← imm16

CMPL A, ear

CMPL A, eam

CMPL A, #imm32

2

6

2

0

word (A) ← (ear)

–

*

–

2+ 7+ (a) 0

5

(d) word (A) ← (eam)

word (A) ← imm32

3

0

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

70

MB90660A Series

Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

Mnemonic

#

~

RG B

Operation

LH AH I

S

T

N

Z

V

C RMW

1

DIVU

A

1

0

1

0

1

0

0 word (AH) /byte (AL)

Quotient → byte (AL) Remainder → byte (AH)

0 word (A)/byte (ear)

–

*

–

*

2

DIVU

A, ear

2

–

*

Quotient → byte (A) Remainder → byte (ear)

word (A)/byte (eam)

6

3

A, eam 2+

*

Quotient → byte (A) Remainder → byte (eam)

long (A)/word (ear)

4

DIVUW A, ear

2

0

*

Quotient → word (A) Remainder → word (ear)

long (A)/word (eam)

7

5

*

DIVUW A, eam 2+

Quotient → word (A) Remainder → word (eam)

8

byte (AH) *byte (AL) →word (A)

byte (A) *byte (ear) →word (A)

byte (A) *byte (eam) →word (A)

0

(b)

MULU

A

A, ear

A, eam 2+

1

2

*

0

1

0

–

9

*

10

*

11

12

13

word (AH) *word (AL) →long (A)

word (A) *word (ear) →long (A)

word (A) *word (eam) →long (A)

0

(c)

MULUW A

MULUW A, ear

MULUW A, eam 2+

1

2

0

1

0

–

*

*1: 3 when the result is zero, 7 when an overﬂow occurs, and 15 normally.

*2: 4 when the result is zero, 8 when an overﬂow occurs, and 16 normally.

*3: 6 + (a) when the result is zero, 9 + (a) when an overﬂow occurs, and 19 + (a) normally.

*4: 4 when the result is zero, 7 when an overﬂow occurs, and 22 normally.

*5: 6 + (a) when the result is zero, 8 + (a) when an overﬂow occurs, and 26 + (a) normally.

*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.

*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.

*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

71

MB90660A Series

Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions]

Mnemonic

AND A, #imm8

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V

C RMW

2

3

0

1

0

byte (A) ← (A) and imm8

byte (A) ← (A) and (ear)

–

*

R

–

*

AND

A, ear

A, eam

ear, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) and (A) –

(b) byte (A) ← (A) and (eam)

byte (ear) ← (ear) and (A)

3

2

0

eam, A

OR

A, #imm8

A, ear

A, eam

ear, A

2

3

0

1

0

byte (A) ← (A) or imm8

byte (A) ← (A) or (ear)

–

*

R

–

*

2+ 4+ (a) 0

(b) byte (A) ← (A) or (eam)

byte (ear) ← (ear) or (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) or (A)

2

3

2

0

eam, A

XOR A, #imm8

XOR A, ear

XOR A, eam

XOR ear, A

XOR eam, A

2

3

0

1

0

byte (A) ← (A) xor imm8

byte (A) ← (A) xor (ear)

–

*

R

–

*

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) xor (A) –

(b) byte (A) ← (A) xor (eam)

byte (ear) ← (ear) xor (A)

3

2

0

NOT

A

ear

eam

1

2

3

0

2

0

byte (A) ← not (A)

byte (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)

ANDW A

1

3

2

3

0

1

0

word (A) ← (AH) and (A)

word (A) ← (A) and imm16

word (A) ← (A) and (ear)

–

*

R

–

*

ANDW A, #imm16

ANDW A, ear

ANDW A, eam

ANDW ear, A

ANDW eam, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) and (A) –

(c) word (A) ← (A) and (eam)

word (ear) ← (ear) and (A)

3

2

0

ORW

A

1

3

2

3

0

1

0

word (A) ← (AH) or (A)

word (A) ← (A) or imm16

word (A) ← (A) or (ear)

–

*

R

–

*

ORW A, #imm16

ORW A, ear

ORW A, eam

ORW ear, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) or (A) –

(c) word (A) ← (A) or (eam)

word (ear) ← (ear) or (A)

3

2

0

ORW eam, A

XORW A

1

3

2

3

0

1

0

word (A) ← (AH) xor (A)

word (A) ← (A) xor imm16

word (A) ← (A) xor (ear)

–

*

R

–

*

XORW A, #imm16

XORW A, ear

XORW A, eam

XORW ear, A

XORW eam, A

2+ 4+ (a) 0

(c) word (A) ← (A) xor (eam)

word (ear) ← (ear) xor (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) xor (A)

2

3

2

0

NOTW A

NOTW ear

NOTW eam

1

2

3

0

2

0

word (A) ← not (A)

word (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

72

MB90660A Series

Table 14 Logical 2 Instructions (Long Word) [6 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V

C RMW

ANDL A, ear

ANDL A, eam

2

6

2

0

long (A) ← (A) and (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) and (eam)

ORL

A, ear

A, eam

2

6

2

0

long (A) ← (A) or (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) or (eam)

XORL A, ea

XORL A, eam

2

6

2

0

long (A) ← (A) xor (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) xor (eam)

Table 15 Sign Inversion Instructions (Byte/Word) [6 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V

C RMW

NEG

A

1

2

0

byte (A) ← 0 – (A)

X

–

*

–

NEG ear

NEG eam

2

3

2

0

byte (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)

NEGW A

1

2

0

word (A) ← 0 – (A)

–

*

–

NEGW ear

NEGW eam

2

3

2

0

word (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)

Table 16 Normalize Instruction (Long Word) [1 Instruction]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V

C RMW

1

NRML A, R0

2

1

0

long (A) ← Shift until first digit is “1” –

byte (R0) ← Current shift count

–

*

–

*

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

73

MB90660A Series

Table 17 Shift Instructions (Byte/Word/Long Word) [18 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V C RMW

RORC A

ROLC A

2

0

byte (A) ← Right rotation with carry

byte (A) ← Left rotation with carry

–

*

–

*

–

RORC ear

RORC eam

ROLC ear

ROLC eam

2

3

2

0

byte (ear) ← Right rotation with carry

–

*

–

*

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← Right rotation with carry

2

2+ 5+ (a) 0 2× (b) byte (eam) ← Left rotation with carry

3

2

0

byte (ear) ← Left rotation with carry

1

ASR A, R0

LSR A, R0

LSL A, R0

2

1

0

byte (A) ← Arithmetic right barrel shift (A, R0) –

–

*

–

*

–

*

–

*

1

byte (A) ← Logical right barrel shift (A, R0)

byte (A) ← Logical left barrel shift (A, R0)

–

ASRW A

LSRW A/SHRW A 1

LSLW A/SHLW A 1

1

2

0

word (A) ← Arithmetic right shift (A, 1 bit)

word (A) ← Logical right shift (A, 1 bit)

word (A) ← Logical left shift (A, 1 bit)

–

*

–

*

R

*

–

*

–

1

ASRW A, R0

LSRW A, R0

LSLW A, R0

2

1

0

word(A)←Arithmetic right barrel shift (A, R0) –

–

*

–

*

–

*

–

*

1

word (A) ← Logical right barrel shift (A, R0)

word (A) ← Logical left barrel shift (A, R0)

–

*

1

2

ASRL A, R0

LSRL A, R0

LSLL A, R0

2

1

0

long (A) ← Arithmetic right shift (A, R0)

long (A) ← Logical right barrel shift (A, R0)

long (A) ← Logical left barrel shift (A, R0)

–

*

–

*

–

*

–

*

*1: 6 when R0 is 0, 5 + (R0) in all other cases.

*2: 6 when R0 is 0, 6 + (R0) in all other cases.

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

74

MB90660A Series

Table 18 Branch 1 Instructions [31 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V C RMW

1

BZ/BEQ

BNZ/BNE rel

BC/BLO

BNC/BHS rel

rel

2

0

Branch when (Z) = 1

Branch when (Z) = 0

Branch when (C) = 1

Branch when (C) = 0

Branch when (N) = 1

Branch when (N) = 0

Branch when (V) = 1

Branch when (V) = 0

Branch when (T) = 1

Branch when (T) = 0

Branch when (V) xor (N) = 1

Branch when (V) xor (N) = 0

Branch when ((V) xor (N)) or (Z) = 1 –

Branch when ((V) xor (N)) or (Z) = 0 –

Branch when (C) or (Z) = 1

Branch when (C) or (Z) = 0

Branch unconditionally

–

*

1

*

1

rel

*

1

*

1

*

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

1

*

–

1

*

1

*

2

3

JMP

@A

1

3

2

2+

2

2+

4

0

1

0

2

0

word (PC) ← (A)

word (PC) ← addr16

word (PC) ← (ear)

–

addr16

@ear

@eam

3

4+ (a)

5

6+ (a)

4

(c) word (PC) ← (eam)

0

(d) word(PC)←(eam), (PCB)←(eam+2) –

0

JMPP @ear *³

JMPP @eam *³

JMPP addr24

word (PC) ← (ear), (PCB) ← (ear +2)

word (PC) ← ad24 0 to 15,

(PCB) ← ad24 16 to 23

–

CALL @ear *⁴

CALL @eam *⁴

CALL addr16 *⁵

CALLV #vct4 *⁵

CALLP @ear *⁶

6

7+ (a)

6

7

10

2

2+

3

1

2

1

(c) word (PC) ← (ear)

–

0 2× (c) word (PC) ← (eam)

(c) word (PC) ← addr16

0

0 2× (c) Vector call instruction

2 2× (c) word (PC) ← (ear) 0 to 15

(PCB) ← (ear) 16 to 23

2

CALLP @eam *⁶

CALLP addr24 *⁷

11+ (a)

10

2+

4

0

word (PC) ← (eam) 0 to 15

(PCB) ← (eam) 16 to 23

word (PC) ← addr0 to 15,

(PCB) ← addr16 to 23

–

*

2× (c)

*1: 4 when branching, 3 when not branching.

*2: (b) + 3 × (c)

*3: Read (word) branch address.

*4: W: Save (word) to stack; R: read (word) branch address.

*5: Save (word) to stack.

*6: W: Save (long word) to W stack; R: read (long word) R branch address.

*7: Save (long word) to stack.

Note: Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

75

MB90660A Series

Table 19 Branch 2 Instructions [19 Instructions]

Mnemonic

#

~ RG

B

Operation

LH AH I

S

T

N

Z

V

C RMW

1

CBNE A, #imm8, rel

CWBNE A, #imm16, rel

3

4

0

Branch when byte (A) ≠ imm8

Branch when word (A) ≠ imm16

–

*

–

*

1

2

3

4

3

CBNE ear, #imm8, rel

CBNE eam, #imm8, rel*

CWBNE ear, #imm16, rel

4

4+

5

*

1

0

1

0

Branch when byte (ear) ≠ imm8

–

*

–

9

(b) Branch when byte (eam) ≠ imm8

0

(c) Branch when word (eam) ≠ imm16 –

Branch when word (ear) ≠ imm16

9

5+

CWBNE eam, #imm16, rel*

5

3

2

0

Branch when byte (ear) =

(ear) – 1, and (ear) ≠ 0

–

*

–

*

DBNZ ear, rel

6

3+

2 2× (b) Branch when byte (eam) =

DBNZ eam, rel

(eam) – 1, and (eam) ≠ 0

5

3

*

2

0

Branch when word (ear) =

(ear) – 1, and (ear) ≠ 0

–

*

–

*

DWBNZ ear, rel

DWBNZ eam, rel

6

3+

2 2× (c) Branch when word (eam) =

(eam) – 1, and (eam) ≠ 0

8× (c)

6× (c)

8× (c)

6× (c)

2

3

4

1

0

Software interrupt

Return from interrupt

–

R

*

S

*

–

*

–

*

–

*

–

*

–

*

–

20

16

17

20

15

INT

INTP

INT9

RETI

#vct8

addr16

addr24

(c)

2

0

At constant entry, save old frame

pointer to stack, set new frame

pointer, and allocate local pointer

area

At constant entry, retrieve old

frame pointer from stack.

–

6

LINK

#local8

(c)

1

0

–

5

UNLINK

RET *⁷

(c)

(d)

1

0

Return from subroutine

–

4

6

RETP *⁸

*1: 5 when branching, 4 when not branching

*2: 13 when branching, 12 when not branching

*3: 7 + (a) when branching, 6 + (a) when not branching

*4: 8 when branching, 7 when not branching

*5: 7 when branching, 6 when not branching

*6: 8 + (a) when branching, 7 + (a) when not branching

*7: Retrieve (word) from stack

*8: Retrieve (long word) from stack

*9: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

76

MB90660A Series

Table 20 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]

Mnemonic

PUSHW A

PUSHW AH

PUSHW PS

PUSHW rlst

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V C RMW

1

2

4

0

(c) word (SP) ← (SP) –2, ((SP)) ← (A)

(c) word (SP) ← (SP) –2, ((SP)) ← (AH)

–

(c) word (SP) ← (SP) –2, ((SP)) ← (PS)

3

5

4

(SP) ← (SP) –2n, ((SP)) ← (rlst)

word (A) ← ((SP)), (SP) ← (SP) +2

word (AH) ← ((SP)), (SP) ← (SP) +2 –

word (PS) ← ((SP)), (SP) ← (SP) +2

(rlst) ← ((SP)), (SP) ← (SP) +2n

*

POPW A

POPW AH

POPW PS

POPW rlst

1

2

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

3

4

0

(c)

–

2

5

4

–

*

JCTX @A

1

Context switch instruction

0 6× (c)

–

*

–

14

AND

OR

CCR, #imm8

2

byte (CCR) ← (CCR) and imm8 –

–

*

–

3

0

byte (CCR) ← (CCR) or imm8

–

MOV RP, #imm8

MOV ILM, #imm8

2

byte (RP) ←imm8

byte (ILM) ←imm8

–

2

0

MOVEA RWi, ear

MOVEA RWi, eam

MOVEA A, ear

2

2+

2

word (RWi) ←ear

word (RWi) ←eam

word(A) ←ear

–

*

–

3

1

0

2+ (a) 1

1

0

MOVEA A, eam

2+

word (A) ←eam

*

1+ (a) 0

ADDSP #imm8

ADDSP #imm16

2

3

word (SP) ← (SP) +ext (imm8)

word (SP) ← (SP) +imm16

–

3

0

1

MOV A, brgl

MOV brg2, A

2

byte (A) ← (brgl)

byte (brg2) ← (A)

Z

–

*

–

*

–

0

*

1

NOP

ADB

DTB

PCB

SPB

NCC

CMR

1

No operation

–

0

1

Preﬁx code for accessing AD space

Preﬁx code for accessing DT space

Preﬁx code for accessing PC space

Preﬁx code for accessing SP space

Preﬁx code for no ﬂag change

Preﬁx code for common register bank

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB, DPR : 2 states

*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)

*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)

*4: Pop count × (c), or push count × (c)

*5: Pop count or push count.

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

77

MB90660A Series

Table 21 Bit Manipulation Instructions [21 Instructions]

Mnemonic

#

~

RG

B

Operation

LH AH I

S

T

N

Z

V C RMW

MOVB A, dir:bp

MOVB A, addr16:bp

MOVB A, io:bp

3

4

3

5

4

0

(b) byte (A) ← (dir:bp) b

(b) byte (A) ← (addr16:bp) b

(b) byte (A) ← (io:bp) b

Z

*

–

*

–

MOVB dir:bp, A

MOVB addr16:bp, A

MOVB io:bp, A

3

4

3

7

6

0 2× (b) bit (dir:bp) b ← (A)

0 2× (b) bit (addr16:bp) b ← (A)

0 2× (b) bit (io:bp) b ← (A)

–

*

–

*

SETB dir:bp

SETB addr16:bp

SETB io:bp

3

4

3

7

0 2× (b) bit (dir:bp) b ← 1

0 2× (b) bit (addr16:bp) b ← 1

0 2× (b) bit (io:bp) b ← 1

–

*

CLRB dir:bp

CLRB addr16:bp

CLRB io:bp

3

4

3

7

0 2× (b) bit (dir:bp) b ← 0

0 2× (b) bit (addr16:bp) b ← 0

0 2× (b) bit (io:bp) b ← 0

–

*

1

BBC dir:bp, rel

BBC addr16:bp, rel

BBC io:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 0

(b) Branch when (addr16:bp) b = 0

(b) Branch when (io:bp) b = 0

–

*

–

*

1

*

2

*

1

BBS

dir:bp, rel

addr16:bp, rel

io:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 1

(b) Branch when (addr16:bp) b = 1

(b) Branch when (io:bp) b = 1

–

*

–

*

1

*

2

*

3

SBBS addr16:bp, rel

WBTS io:bp

5

3

0 2× (b) Branch when (addr16:bp) b = 1, bit = 1

–

*

–

*

5

4

0

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

–

*

4

5

WBTC io:bp

*

*1: 8 when branching, 7 when not branching

*2: 7 when branching, 6 when not branching

*3: 10 when condition is satisfied, 9 when not satisfied

*4: Undefined count

*5: Until condition is satisfied

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

78

MB90660A Series

Table 22 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]

Mnemonic

SWAP

SWAPW/XCHW AL, AH

EXT

EXTW

ZEXT

ZEXTW

#

~

RG B

Operation

LH AH I

S

T

N

Z

V

C RMW

1

3

2

1

2

1

0

0 byte (A) 0 to 7 ↔ (A) 8 to 15

0 word (AH) ↔ (AL)

0 byte sign extension

0 word sign extension

0 byte zero extension

0 word zero extension

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

*

Table 23 String Instructions [10 Instructions]

Mnemonic

#

~

RG B

Operation

LH AH I

S

T

N

Z

V

C RMW

2

5

3

MOVS/MOVSI

MOVSD

2

Byte transfer @AH+ ← @AL+, counter = RW0

Byte transfer @AH– ← @AL–, counter = RW0

–

*

2

5

3

*

1

5

4

SCEQ/SCEQI

SCEQD

2

*

Byte retrieval (@AH+) – AL, counter = RW0

Byte retrieval (@AH–) – AL, counter = RW0

–

*

–

1

*

5

3

6m +6

FISL/FILSI

2

Byte filling @AH+ ← AL, counter = RW0

–

*

–

*

2

8

6

MOVSW/MOVSWI 2

MOVSWD

Word transfer @AH+ ← @AL+, counter = RW0

Word transfer @AH– ← @AL–, counter = RW0

–

*

2

8

6

2

*

1

8

7

SCWEQ/SCWEQI 2

*

Word retrieval (@AH+) – AL, counter = RW0

Word retrieval (@AH–) – AL, counter = RW0

–

*

–

1

SCWEQD

2

*

8

6

6m +6

FILSW/FILSWI

2

Word filling @AH+ ← AL, counter = RW0

–

*

–

*

m: RW0 value (counter value)

n: Loop count

*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs

*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case

*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately

for each.

*4: (b) × n

*5: 2 × (RW0)

*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately

for each.

*7: (c) × n

*8: 2 × (RW0)

Note: For an explanation of“(a)”to“(d)”, refer toTable 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

79

MB90660A Series

■ MASK OPTION LIST

MB60662A

MB90663A

Part number

MB90P663A

No.

Specifying

procedure

Specify when

ordering masking

Set with EPROM

programmer

P00 to P07

P10 to P17

P20 to P27

P30 to P33

P40 to P47

P60 to P66

RST

Pull-up resistor can be selected for

each pin

Pull-up resistor can be selected for

each pin

1

DTTI

Cannot be selected; pull-down

resistor not provided

MD2

Pull-down resistor

Can be selected

2

3

MD1

MD0

Pull-up resistor

all at once

Pull-up resistor

Can be selected

all at once

Pull-up resistor

Accept asynchronous reset

input

Can be selected

Accepted

Not accepted

Notes: • A speciﬁcation of “yes” for accept asynchronous reset input refers to a function whereby reset input is

accepted when oscillation for output ports (including peripheral resource output) is stopped and port output

(including peripheral resource output) is forced Hi-z. Note, however, that since internal reset (reset of the

CPU and peripheral resources) is synchronized with the clock, the CPU and peripheral resources are not

initialized when the clock is stopped.

• For details on writing to the MB90P663A, see Chapter 6, “■PROGRAMMINGTHE MB90P663A EPROM”.

• Use of a pull-up/pull-down resistors for the mode pins (MD2 to MD0) can be selected separately for each

pin. If “yes” is selected, a pull-up is attached to MD0 and MD1 and a pull-down to MD2 for mask ROM

versions. A pull-up is attached to MD0 and MD1, but a pull-down is not attached to MD2 for OTP versions.

• Since it takes eight machine cycles to make option settings for the MB90P663A, options cannot be set

between when power is ﬁrst turned on and the clock is supplied. (This results in a setting of no pull-up for

all pins and accept asynchronous reset input.)

80

MB90660A Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90662AP-SH

MB90663AP-SH

MB90P663AP-SH

64-pin plastic SH-DIP (DIP-64P-M01)

64-pin plastic LQFP (FTP-64P-M09)

MB90662APFM

MB90663APFM

MB90P663APFM

81

MB90660A Series

■ PACKAGE DIMENSIONS

64-pin Plastic SH-DIP

(DIP-64P-M01)

58.00⁺^–0⁰^.^.⁵²⁵²

2.283–⁺.^.0⁰2⁰2⁸

INDEX-1

INDEX-2

17.00±0.25

(.669±.010)

5.65(.222)MAX

3.00(.118)MIN

0.25±0.05

(.010±.002)

1.00 ^–⁺⁰^0.50

.039 ^–⁺⁰^.020

0.45±0.10

(.018±.004)

0.51(.020)MIN

19.05(.750)

TYP

15°MAX

1.778±0.18

(.070±.007)

1.778(.070)

MAX

55.118(2.170)REF

C

1994 FUJITSU LIMITED D64001S-3C-4

Dimensions in mm (inches)

64-pin Plastic LQFP

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

1.50⁺^–0⁰^.^.¹²⁰⁰

.059⁺^–.^.⁰⁰⁰⁰⁴⁸

48

33

32

49

9.75

(.384)

REF

13.00

(.512)

NOM

1 PIN INDEX

64

17

1

16

Details of "A" part

LEAD No.

"A"

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.127⁺^–0⁰^.^.⁰⁰²⁵

0.10±0.10

(.004±.004)

M

0.13(.005)

+.002

(STAND OFF)

.005^–.001

0.50±0.20

(.020±.008)

0.10(.004)

0

10°

C

1994 FUJITSU LIMITED F64018S-1C-2

Dimensions in mm (inches)

82

MB90660A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-88, Japan

Tel: (044) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: (044) 754-3329

The information and circuit diagrams in this document presented

as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the

use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, U.S.A.

Tel: (408) 922-9000

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Fax: (408) 432-9044/9045

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Asia Paciﬁc

FUJITSU MICROELECTRONICS ASIA PTE. LIMITED

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.

F9703

FUJITSU LIMITED Printed in Japan

83


型号：	MB90660A
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller CMOS 16位微控制器的专有CMOS 微控制器
文件：	总83页 (文件大小：768K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90660A [FUJITSU]

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