MB90803PF_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

Preliminary

2004.07.22

16-bit Proprietary Microcontroller

CMOS

R

MB90800 Series

MB90803/F804/V800

■ DESCRIPTION

The MB90800 series is a general-purpose 16-bit microcontroller that has been developed for high-speed real-

time processing required for industrial and office automation equipment and process control, etc. The LCD

controller of 48 segment four common is built into.

Instruction set has taken over the same AT architecture as in the F²MC*-8L and F²MC 16L, and is further enhanced

to support high level languages, extend addressing mode, enhanced divide/multiply instructions with sign and

enrichmentofbitprocessing. Inaddition, longwordprocessingisnowavailablebyintroducinga32-bitaccumulator.

* : F²MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.

■ FEATURES

• Clock

• Built-in PLL clock frequency multiplication circuit

• Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or 1 to 4 times the oscillation (at

oscillation of 6.25 MHz, 6.25 MHz to 25 MHz).

• Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times the PLL clock, operation

at Vcc = 3.3 V)

• The maximum memory space:16 MB

• 24-bit internal addressing

• Bank addressing

(Continued)

■ PACKAGE

100-pin plastic QFP

(FPT-100P-M06)

MB90800 Series

(Continued)

• Optimized instruction set for controller applications

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• High code efficiency

• Enhanced high-precision computing with 32-bit accumulator

• Enhanced Multiply/Divide instructions with sign and the RETI instruction

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Instruction set has symmetry and barrel shift instructions

• Program Patch Function (2 address pointer)

• 4-byte instruction queue

• Interrupt function

• The priority level can be set to programmable.

• Interrupt function with 32 factors

• Data transfer function

• Expanded intelligent I/O service function (EI 2 OS): Maximum of 16 channels]

• Low Power Consumption Mode

• Sleep mode (a mode that helts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock and time-base timer)

• Watch timer mode (mode in which only the subclock and watch timers operate)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode (operating CPU at each set cycle)

• Package

• LQFP-120P (FPT-100P-M06:0.65 mm pin pitch)

• Process : CMOS technology

2

MB90800 Series

■ BUILT-IN PERIPHERAL FUNCTION (RESOURCE)

• I/O port : 68 or less (sub-clocking 70 unused)

• Time-base timer : 1channel

• Watchdog timer : 1 channel

• Watch timer : 1channel

• LCD Controller

• 48SEG 4COM

• 8/10-bit A/D converter : 12 channels

• 8-bit resolution or 10-bit resolution can be set.

• 16-bit reload timer : 3 channels

• Multi-functional timer

• 16-bit free run timer : 1 channel

• 16-bit Output Compare : 2 channels

An interrupt request can be output when the count value of the 16-bit free-run timer and the setting value in

the compare register match.

• Input capture : 2 channels

Upon detecting a valid edge of the signal input from the external input pin, the count value of the 16-bit free-

run timer is loaded into the input capture data register and an interrupt request can be output.

• 16-bit PPG timer : 2 channels

• 16-bit reload timer : 3 channels

• UART : 2 channels

• Extended I/O serial interface : 2 channels

• DTP/External interrupt circuit : 4 channels

• Activate the extended intelligent I/O service by external interrupt input

• Interrupt output by external interrupt input

• Timer clock output circuit

• Delay interrupt output module

• Output an interrupt request for task switching

• I²C Interface : 1 channel

3

MB90800 Series

■ PRODUCT LINEUP

1. MB90800 Series

Part number

MB90V800

MB90F804-101/201

MB90803/S

FLASH MEMORY

built-in type

Mask ROM

built-in type

Type

For evaluation

On-chip PLL clock multiplication method( × 1, × 2, × 3, × 4, 1/2 when PLL stops)

Minimum instruction execution time of 40.0 ns

System clock

(at oscillation of 6.25 MHz, four times the PLL clock)

ROM capacity

RAM capacity

No

256 Kbytes

16 Kbytes

128 Kbytes

4 Kbytes

28 Kbytes

Number of basic instructions : 351

Minimum instruction execution time : 40.0 ns/6.25 MHz oscillator

(When four times is used : machine clock

25 MHz, Power supply voltage : 3.3 V ± 0.3 V)

CPU functions

Addressing type : 23 types

Program Patch Function : 2 address pointers

The maximum memory space : 16MB

I/O port (CMOS) 68 ports (shared with resources), (70 ports when the subclock is

not used)

Ports

Segment driver that can drive the LCD panel (liquid crystal display) directly, and

common driver 48 SEG × 4 COM

LCD controller/driver

16-bit free-run

1 channel

timer

Overflow interrupt

16-bit

input/

output

timer

Output compare

(OCU)

2 channels

Pin input factor: matching of the compare register

Input capture

(ICU)

2 channels

Rewriting a register value upon a pin input (rising edge, falling edge, or both edges)

16-bit reload timer operation (toggle output, single shot output selectable)

The event count function is optional. The event count function is optional.

Three channels are built in.

16-Bit Reload Timer

16-bit PPG timer

Output pin × 2 ports

Operating clock frequency : fcp, fcp/22, fcp/24, fcp/26

Two channels are built in.

Clock with a frequency of external input clock divided by 16/32/64/128 can be

output externally.

I²C Interface. 1 channel is built-in.

Timer clock output circuit

I²C bus

12 channels (input multiplex)

8/10-bit A/D converter

UART

The 8-bit resolution or 10-bit resolution can be set.

Conversion time : 5.9 µs (When machine clock 16.8 MHz works).

Full-duplex double buffer

Asynchronous/synchronous transmit (with start/stop bits) are supported.

Two channels are built in.

Extended I/O serial interface

Interrupt delay interrupt

Two channels are built in.

Four channel independence (A/D input and using combinedly)

Interrupt causes : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable

8 channels (The 8 channels include with the shared A/D input)

Interrupt causes：“L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable

DTP/External interrupt

Low Power Consumption Mode Sleep mode/Timebase timer mode/Watch mode/Stop mode/CPU intermittent mode

Process

CMOS

Operating voltage

2.7 V to 3.6 V

4

MB90800 Series

■ PIN ASSIGNMENT

(TOP VIEW)

P24/SEG32

P25/SEG33

P26/SEG34

1

2

3

4

5

6

7

8

9

80 P03/SEG15

79 P02/SEG14

78 P01/SEG13

77 P00/SEG12

76 SEG11

75 SEG10

74 SEG9

73 SEG8

72 SEG7

71 SEG6

70 SEG5

69 SEG4

68 SEG3

67 SEG2

66 VSS

P27/SEG35

P30/SEG36/SO3

P31/SEG37/SC3

P32/SEG38/SI3

P33/SEG39/TMCK

P34/SEG40/IC0

P35/SEG41/IC1 10

P36/SEG42/OCU0 11

P37SEG43/OCU1 12

X0A/P90 13

X1A/P91 14

VCC 15

VSS 16

65 VCC

P40/LED0 17

P41/LED1 18

P42/LED2 19

P43/LED3 20

64 SEG1

63 SEG0

62 P84/COM3

61 P83/COM2

60 COM1

59 COM0

58 V3

57 V2/P82

56 V1/P81

55 V0/P80

54 RST

P44/LED4 21

P45/LED5/TOT0 22

P46/LED6/TOT1 23

P47/LED7/TOT2 24

P50/SEG44/TIN0 25

P51/SEG45/TIN1 26

P52/SEG46/TIN2/PPG0 27

P53/SEG47/PPG1 28

P54/SI0 29

53 MD0

52 MD1

P55/SO0 30

51 MD2

(FPT-100P-M06)

5

MB90800 Series

■ PIN DESCRIPTION

Pin No.

Circuit Status/function

Pin Name

Description

Type*

at reset

QFP

It is a terminal which connects the oscillator.

When connecting an external clock, leave the x1 pin

side unconnected.

Oscillation

status

92, 93

X0, X1

A

Oscillation

status

It is 32 kHz oscillation pin.

(Dual-line model)

X0A, X1A

P90, P91

MD2

B

G

M

13, 14

51

Port input

(High-Z)

General purpose input/output port.

(Single-line model)

Input pin for selecting operation mode.

Connect directly to Vss.

Mode Pins

Input pin for selecting operation mode.

Connect directly to Vcc.

52, 53

54

MD1, MD0

RST

L

Mode Pins

Reset input

K

External reset input pin.

63, 64,

67 to 72,

73 to 76

SEG0 to

SEG11

LCD SEG

output

A segment output terminal of the LCD controller/

driver.

D

E

SEG12 to

SEG19

A segment output terminal of the LCD controller/

driver.

77 to 84

P00 to P07

General purpose input/output port.

SEG20 to

SEG27

A segment output terminal of the LCD controller/

driver.

85 to 89,

94 to 96

E

P10 to P17

General purpose input/output port.

SEG28 to

SEG35

A segment output terminal of the LCD controller/

driver.

97 to 100,

1 to 4

P20 to P27

SEG36

P30

General purpose input/output port.

A segment output terminal of the LCD controller/

driver.

Port input

(High-Z)

General purpose input/output port.

5

6

E

Serial data output pin of serial I/O channel 3.

Valid when serial data output of serial I/O channel 3

is enabled.

SO3

A segment output terminal of the LCD controller/

driver.

SEG37

P31

General purpose input/output port.

Serial clock I/O pin of serial I/O channel 3.

Valid when serial clock output of serial I/O channel 3

is enabled.

SC3

* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.

(Continued)

6

MB90800 Series

Pin No.

QFP

Circuit Status/function

Pin Name

Description

Type*

at reset

A segment output terminal of the LCD controller/

driver.

SEG38

P32

General purpose input/output port.

7

E

Serial data input pin of serial I/O channel 3.

This pin may be used at any time during serial I/O

channel 3 in input mode, so do not use it as other pin

function.

SI3

A segment output terminal of the LCD controller/

driver.

SEG39

P33

8

E

General purpose input/output port.

Timer clock output pin.

It is effective when permitting the power output.

TMCK

SEG40,

SEG41

A segment output terminal of the LCD controller/

driver.

9, 10

P34, P35

General purpose input/output port.

External trigger input pin of input capture channel 0/

channel 1.

IC0, IC1

SEG42,

SEG43

A segment output terminal of the LCD controller/

driver.

Port input

(High-Z)

11, 12

P36, P37

E

F

General purpose input/output port.

OCU0,

OCU1

Output terminal for the Output Compares.

LED0 to

LED4

It is a output terminal for LED (I^OL= 15 mA).

General purpose input/output port.

17 to 21

P40 to P44

LED5 to

LED7

It is a output terminal for LED (I^OL= 15 mA).

P45 to P47

General purpose input/output port.

22 to 24

F

External event output pin of reload timer channel 0

TOT0 to

TOT2

to chanel 2.

It is effective when permitting the external event

output.

SEG44 to

SEG45

A segment output terminal of the LCD controller/

driver.

P50, P51

General purpose input/output port.

25, 26

E

External clock input pin of reload timer channel 0,

TIN0,

TIN1

channel 1.

It is effective when permitting the external clock

input.

* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.

(Continued)

7

MB90800 Series

Pin No.

Circuit Status/function

Pin Name

Description

Type*

at reset

QFP

A segment output terminal of the LCD controller/

driver.

SEG46

P52

General purpose input/output port.

27

E

External clock input pin of reload timer channel 2.

It is effective when permitting the external clock

input.

TIN2

PPG0

PPG timer (ch0) output pin.

A segment output terminal of the LCD controller/

driver.

SEG47

28

29

E

P53

General purpose input/output port.

PPG (ch1) timer output pin.

PPG1

Serial data input pin of UART channel 0.

This pin may be used at any time during UART

channel 0 in receiving mode, so do not use it as other

pin function.

SIO

G

P54

SC0

P55

SO0

P56

General purpose input/output port.

Port input

(High-Z)

Serial clock input/output pin of UART channel 0.

It is effective when permitting the serial clock output

of UART channel 0.

30

31

G

General purpose input/output port.

Serial data output pin of UART channel 0.

It is effective when permitting the serial clock output

of UART channel 0.

General purpose input/output port.

Serial data input pin of UART channel 1.

This pin may be used at any time during UART

channel 1 in receiving mode, so do not use it as other

pin function.

SI1

33

G

P57

P76

General purpose input/output port.

34

G

I

Analog input pin channel 0 to channel 4 of A/D

converter. Enabled when analog input setting is

" enabled "(set by ADER).

AN0 to

AN4

36 to 40

P60 to P64

General purpose input/output port.

* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.

(Continued)

8

MB90800 Series

Pin No.

QFP

Circuit Status/function

Pin Name

Description

Type*

at reset

Analog input pin channel 5 to channel 7 of A/D

converter. Enabled when analog input setting is

" enabled "(set by ADER).

AN5 to

AN7

41 to 43

I

P65 to P67

General purpose input/output port.

INT0 to

INT2

Functions as an external interrupt ch0 to ch2 input

pin.

Analog input

(High-Z)

Analog input pin channel 8 of A/D converter.

Enabled when analog input setting is " enabled "(set

by ADER).

AN8

45

I

P70

General purpose input/output port.

INT3

Functions as an external interrupt ch3 input pin.

Analog input pin channel 9 of A/D converter.

Enabled when analog input setting is " enabled "(set

by ADER).

AN9

P71

SC1

46

47

General purpose input/output port.

Serial clock input/output pin of UART channel 1.

It is effective when permitting the serial clock output

of UART channel 1.

Analog input pin channel 10 of A/D converter.

Enabled when analog input setting is " enabled "(set

by ADER).

AN10

P72

I

Port input

(High-Z)

General purpose input/output port.

Serial data output pin of serial I/O channel 1.

Valid when serial data output of serial I/O channel 1

is enabled.

SO1

Analog input pin channel 11 of A/D converter.

Enabled when analog input setting is " enabled "(set

by ADER).

AN11

P73

General purpose input/output port.

48

I

Serial data input pin of serial I/O channel 2.

This pin may be used at any time during serial I/O

channel 2 in input mode, so do not use it as other pin

function.

SI2

* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.

(Continued)

9

MB90800 Series

(Continued)

Pin No.

Circuit Status/function

Pin Name

Description

Type*

at reset

QFP

Data input/output pin of I²C Interface.

This function is enabled when the operation of the

I²C interface is permitted. While the I²C interface is

running, the port must be set for input use.

SDA

49

H

General purpose input/output port.

(N-ch open drain)

P74

SC2

Serial clock input pin of serial I/O channel 2.

Valid when serial clock output of serial I/O channel 2

is enabled.

Port input

(High-Z)

Clock input/output pin of I²C Interface.

This function is enabled when the operation of the

I²C interface is permitted. While the I²C interface is

running, the port must be set for input use.

SCL

50

H

General purpose input/output port.

(N-ch open drain)

P75

Serial data output pin of serial I/O channel 2.

Valid when serial data output of serial I/O channel 2

is enabled.

SO2

LCD controller/driver.

Reference power terminals of LCD controller/driver.

V0 to V2

LCD drive power

supply input

55 to 57

59, 60

61, 62

J

D

E

P80 to P82

General purpose input/output port.

COM0,

COM1

LCD COM

output

A common output terminal of the LCD controller/

driver.

P83, P84

General purpose input/output port.

Port input

(Hi-Z)

COM2,

COM3

A common output terminal of the LCD controller/

driver.

32

35

AVCC

AVSS

C

A/D converter exclusive power supply input pin.

A/D converter-exclusive GND power supply pin.

LCD controller/driver

58

V3

J

Power supply Reference power terminals of LCD controller/driver.

15, 65, 90

VCC

VSS

These are power supply input pins.

16, 44,

66, 91

GND power supply pin.

* : For the circuit type, see section “■ I/O CIRCUIT TYPE”.

10

MB90800 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistance :

1 MΩ approx.

X1

Clock input

Pch Nch

X0

A

Standby control signal

Clock input

• Low-rate oscillation feedbackresistor,

approx.10 MΩ

X1A

Pch Nch

X0A

B

Standby control signal

• Analog power supply input protection

circuit

Pch

AVP

C

Nch

• LCDC output

Pch

LCDC output

D

Nch

• CMOS output

• LCDC output

Pch

• Hysteresis input

(With input interception function at

standby)

Nch

E

LCDC output

Input signal

Standby control signal

(Continued)

11

MB90800 Series

Type

Circuit

Remarks

• CMOS output

(Heavy-current I^OL=15 mA for LED

drive)

• Hysteresis input

Pch

Nch

(With input interception function at

standby)

F

Input signal

Standby control signal

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Pch

Nch

<Note>

G

Output of input/output port and built-in

resource share one output buffer.

Input of input/output port and built-in

resource share one input buffer.

Input signal

Standby control signal

• Hysteresis input

(With input interception function at

standby)

Nch

Nout

• N-ch open drain output

H

Input signal

Standby control signal

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Pch

Nch

• Analog input

(If the bit of analog input enable

register = 1, the analog input of A/D

converter is enabled.)

I

Input signal

Standby control signal

<Note>

A/D converter

Analog input

Outp put of input/output port and built-in

resource share one output buffer.

Input of input/output port and built-in

resource share one input buffer.

(Continued)

12

MB90800 Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Pch

Nch

• LCD drive power supply input

J

Input signal

Standby control signal

LCD drive power supply

• CMOS hysteresis input with pull-up

resistor.

K

L

Reset input

• CMOS hysteresis input

Reset input

Input

• CMOS hysteresis input with pull-down

resistor

M

13

MB90800 Series

■ HANDLING DEVICES

1. Preventing Latchup, Turning on Power Supply

Latchup may occur on CMOSICs under the following conditions:

• If a voltage higher than VCC or lower than VSS is applied to input and output pins,

• A voltage higher than the rated voltage is applied between V^CCand VSS.

• If the AV^CCpower supply is turned on before the VCC voltage.

Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the

digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as

VCC and the digital power supply).

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using CMOSICs, take great care to prevent the occurrence of latchup.

2. Treatment of unused pins

Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down

registor. If the A/D converter is not used, connect the pins under the following conditions: AVcc = Vcc and

AVss = Vss.

3. About the attention when the external clock is used

・Using external clock

X0

OPEN

X1

4. Treatment of power supply pins (V^CC/V^SS)

To prevent malfunctions of strobe signals due to the rise in the ground level, lower the level of unnecessary

electro-magnetic emission, and prevent latchup, and conform to the total current rating in designing devices if

multiple VCC or VSS pins exist. Pay attention to connect a power supply to VCC and VSS of MB90800 series device

in a lowest-possible impedance. In addition, near pins of MB90800 series device, connecting a bypass capacitor

is recommended at 0.1 µF across VCC and VSS.

5. Crystal oscillators circuit

Noise near the X0/X1 and X0A/X1A pin may cause the device to malfunction. Design a print circuit so that X0/

X1 and X0A/X1A, a crystal oscillator (or a ceramic oscillator) , and bypass capacitor to the ground become as

close as possible to each other. Furthermore, avoid wires to crossing each other as much as possible. It is highly

recommended that you should use a printed circuit board artwork because you can expect stable operations

from it.

6. Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed. Performance of this operation, however, cannot be guaranteed.

14

MB90800 Series

7. Stabilization of Supply Power Supply

A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage

operating range.Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should

be controlled so that VCC ripple variations (peak- to-peak values) at commercial frequencies (50 MHz/60 Mhz)

fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at

instantaneous power switching.

8. Note on Using the two-subsystem product as one-subsystem product

If you are using only one subsystem of the MB90800 series that come in one two-subsystem product, use it with

X0A = VSS and X1A = OPEN.

9. Write to FLASH

Ensure that you must write to FLASH at the operating voltage VCC = 3.13 V to 3.6 V.

Ensure that you must normal write to FLASH at the operating voltage V^CC= 3.0 V to 3.6 V.

15

MB90800 Series

■ BLOCK DIAGRAM

X0, X1

X0A , X1A

RST

CPU F²MC-16LX

core

Clock control

circuit

V0/P80

RAM (4/16/28 KB)

V1/P81

V2/P82

V3

COM0

COM1

ROM/FLASH (128/256 KB)

Port

8

Interrupt controller

P83/COM2

P84/COM3

12

SEG0-SEG11

P60/AN0

P61/AN1

P62/AN2

P63/AN3

10 bits PPG

A/D converter

LCD

Controller/

Driver

8

P00-P07/SEG12-SEG19

Port

0

Port

6

P64/AN4

P65/AN5/INT0

P66/AN6/INT1

P67/AN7/INT2

External

interrupt (4 ch)

Port

1

P10-P17/SEG20-SEG27

P20-P27/SEG28-SEG35

P70/AN8/INT3

P71/AN9/SC1

P72/AN10/SO1

P73/AN11/SI2

P74/SDA/SC2

P75/SCL/SO2

P76

I²C

Port

7

Port

2

Serial I/O 2/3

P30/SEG36/SO3

P31/SEG37/SC3

P32/SEG38/SI3

P33/SEG39/TMCK

P34/SEG40/IC0

P35/SEG41/IC1

P36/SEG42/OCU0

P37/SEG43/OCU1

Prescaler

2/3

Port

3

Port

9

P90

P91

OCU0/1

Free-run timer

P40/LED0

P41/LED1

＊：X0A/X1A and P90/P91 can be switched

Port

4

by mask option.

ICU0/1

P42/LED2

P43/LED3

P44/LED4

Timer clock output

P45/LED5/TOT0

P46/LED6/TOT1

P47/LED7/TOT2

Reload timer

0/1/2

P50/SEG44/TIN0

P51/SEG45/TIN1

P52/SEG46/TIN2/PPG0

P53/SEG47/PPG1

P54/SI0

Specification of the evaluation device (MB90V800)

• Built-in ROM is not exist.

• The device has 28 KB built-in RAM.

PPG0/1

Port

5

UART0/1

P55/SC0

P56/SO0

P57/SI1

Prescaler

0/1

16

MB90800 Series

■ MEMORY MAP

ROM mirror function

ROM area

FFFFFFH

Address #2

00FFFFH

008000H

ROM mirror area

007917H

007900H

Extended IO area 2

Address #2

RAM area

Register

000100H

0000CFH

0000C0H

Extended IO area 1

IO area

0000BFH

000000H

Part number

Address #1

0010FFH

0040FFH

0070FFH

Address #2

FE0000H

MB90803

MB90F804

MB90V800

FC0000H

F80000H*

* : ROM is not built into V products.

I must think ROM decipherment region on the tool side.

Memory Map of MB90800 Series

Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses

( "FF4000H to FFFFFFH" ) of bank FF is visible from the higher addresses ( " 008000H to 00FFFFH " ) of

bank 00.

• For setting of the ROM mirror function, see “■ PERIPHERAL RESOURCE 17. ROM Mirror Function

Selection Module”.

Reference:

• The ROM mirror function is for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Note that because the ROM area

of bank FF exceeds

32 K bytes, all data in the ROM area cannot be shown in mirror image in bank 00.

• When the C compiler small model is used, the data table mirror image can be shown at " 008000^Hto 00FFFFH

" by storing the data table at " FF8000H to FFFFFFH. Therefore, data tables in the ROM area can be referenced

without declaring the far addressing with the pointer.

17

MB90800 Series

■ F²MC^-16L CPUProgramming model

• Dedicated Registers

AH

AL

Accumulator

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

DPR

Direct page register

PCB

DTB

USB

SSB

ADB

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

8 bit

16 bit

32 bit

• General purpose registers

MSB

LSB

16 bit

000180^H+ RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

RL2

RL3

R1

R3

R5

R7

R0

R2

R4

R6

RW4

RW5

RW6

RW7

• Processor status

15

13 12

ILM

8 7

0

PS

RP

CCR

18

MB90800 Series

■ I/O MAP

Register

abbreviation

Read/

Write

Address

Register

Port 0 data register

Resource name

Initial Value

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

PDR0

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

XXXXXXXXB

- XXXXXXXB

- - - XXXXXB

- - - - - - XXB

PDR1

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

00000AH

to

Prohibited

00000FH

000010^H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

000018H

000019H

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

0 0 0 0 0 0 0 0B

- 0 0 0 0 0 0 0B

- - - 0 0 0 0 0B

- - - - - - 0 0B

00001AH

to

Prohibited

00001DH

00001E^H

00001FH

000020H

000021H

ADER0

ADER1

SMR0

SCR0

Analog input enable 0

Analog input enable 1

Mode Register ch0

Control register ch0

R/W

Port 6, A/D

Port 7, A/D

1 1 1 1 1 1 1 1B

- - - - 1 1 1 1B

0 0 0 0 0 - 0 0B

0 0 0 0 0 1 0 0B

UART0

S1DR0/

SODR0

000022H

Input/output data register ch0

Status register ch0

R/W

XXXXXXXX^B

000023H

000024H

SSR0

0 0 0 0 10 0 0B

Prohibited.

Communication prescaler control

register ch0

000025^H

CDCR0

R/W

Prescaler 0

0 0 - - 0 0 0 0B

000026H

to

Prohibited

000027^H

(Continued)

19

MB90800 Series

Register

Address

Read/

Write

Register

Mode Register ch1

Resource name

Initial Value

abbreviation

000028^H

000029H

SMR1

SCR1

R/W

0 0 0 0 0 - 0 0B

0 0 0 0 0 1 0 0B

Control register ch1

UART1

SIDR1/

SODR1

00002AH

Input/output data register ch1

Status register ch1

R/W

XXXXXXXXB

00002BH

00002CH

SSR1

0 0 0 0 1 0 0 0B

Prohibited

Communication prescaler control reg-

ister ch1

00002D^H

CDCR1

R/W

Prescaler 1

0 0 - - 0 0 0 0B

00002EH

00002F^H

000030H

000031H

000032H

000033H

000034^H

000035H

000036H

000037H

000038H

000039^H

00003AH

00003BH

00003CH

00003DH

00003EH

00003FH

Prohibited

ENIR

EIRR

ELVR

External interrupt enable

External interrupt request

External interrupt level (lower)

R/W

- - - - 0 0 0 0B

XXXXXXXXB

0 0 0 0 0 0 0 0B

External interrupt

Prohibited

ADCS0

ADCS1

ADCR0

ADCR1

A/D control status register (lower)

A/D control status register (upper)

A/D data register (lower)

R/W

R

0 0 - - - - - - B

0 0 0 0 0 0 0 0B

XXXXXXXXB

A/D converter

A/D data register (upper)

R/W

0 0 1 0 1 XXXB

Prohibited

ADMR

A/D conversion channel set register

R/W

0 0 0 0 0 0 0 0B

XXXXXXXX^B

CPCLR

Compare clear register

XXXXXXXXB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

0 - - 0 0 0 0 0B

16-bit free-run

timer

TCDT

Timer Data register

R/W

TCCSL

TCCSH

Timer control status register (lower)

Timer control status register (upper)

R/W

000040H

to

Prohibited

000043H

000044^H

000045H

000046H

000047H

000048H

000049H

00004A^H

00004BH

00004CH

00004DH

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

IPCP0

Input Capture register 0

R

Input Capture 0/1

IPCP1

ICS01

Input Capture register 1

Input capture control status 0/1

R/W

Prohibited

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

(Continued)

OCCP0

OCCP1

Output Compare register 0

Output Compare register 1

R/W

Output compare 0

Output compare 1

20

MB90800 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

00004E^H

00004FH

000050H

OCSL

OCSH

Output compare control status (lower)

Output compare control status (upper)

R/W

0 0 0 0 - - 0 0B

- - - 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

- - - - 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

- - - - 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 0B

- - - - 0 0 0 0B

XXXXXXXX^B

XXXXXXXXB

0 0 0 1 0 0 0 0B

0 0 0 0 0 0 0 0B

Output Compare

0/1

TMCSR0L Timer control status register 0 (lower)

000051H TMCSR0H Timer Control Status register 0 (upper)

16-bit reload

timer 0

000052H

000053H

000054H

TMR0/

TMRLR0

Timer register 0/Reload register 0

R/W

TMCSR1L Timer control status register 1 (lower)

R/W

000055H TMCSR1H Timer control status register 1 (upper)

Reload timer 1

Reload timer 2

000056H

000057H

000058H

TMR1/

TMRLR1

Timer register 1/Reload register 1

R/W

TMCSR2L Timer control status register 2 (lower)

R/W

000059H TMCSR2H Timer control status register 2 (upper)

00005AH

00005BH

00005CH

00005DH

00005EH

00005FH

000060^H

000061H

000062H

TMR2/

TMRLR2

Timer register 2/Reload register 2

R/W

LCRL

LCRH

LCRR

LCDC control register (lower)

LCDC control register (upper)

LCDC range register

R/W

LCD controller/

driver

Prohibited

- - - - 0 0 0 0^B

Serial mode control status register

(ch2)

SIO

SMCS0

R/W

(Extended Serial 0 0 0 0 0 0 1 0B

I/O)

SDR0

Serial Data Register (ch2)

R/W

XXXXXXXXB

Control register of clock dividing

frequency (ch2)

Communication

0 - - - 0 0 0 0B

prescaler (SIO)

000063H

SDCR0

000064H

000065H

000066H

- - - - 0 0 0 0^B

SIO

(Extended Serial 0 0 0 0 0 0 1 0B

Serial mode control status register

(ch3)

SMCS1

R/W

I/O)

SDR1

Serial Data Register (ch3)

R/W

XXXXXXXXB

Control register of clock dividing

frequency (ch3)

Communication

0 - - - 0 0 0 0B

prescaler (SIO)

000067H

SDCR1

000068H

000069^H

00006AH

00006BH

00006CH

00006DH

00006EH

00006FH

Prohibited

IBSR

IBCR

ICCR

IADR

IDAR

ROMM

I²C bus status register

I²C bus control register

I²C bus clock selection register

I²C bus address register

I²C bus data register

ROM mirror

R

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

R/W

W

I²C

- - 0XXXXXB

- XXXXXXXB

XXXXXXXXB

XXXXXXX1B

(Continued)

ROM mirror

21

MB90800 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

000070^H

000071H

000072H

000073H

000074H

000075H

000076H

000077H

000078H

000079H

00007AH

00007BH

00007CH

00007DH

00007EH

00007FH

PDCRL0

PDCRH0

PCSRL0

PCSRH0

PDUTL0

PDUTH0

PCNTL0

PCNTH0

PDCRL1

PDCRH1

PCSRL1

PCSRH1

PDUTL1

PDUTH1

PCNTL1

PCNTH1

1 1 1 1 1 1 1 1^B

1 1 1 1 1 1 1 1B

XXXXXXXXB

- - 0 0 0 0 0 0B

0 0 0 0 0 0 0 -B

1 1 1 1 1 1 1 1^B

1 1 1 1 1 1 1 1B

XXXXXXXXB

- - 0 0 0 0 0 0B

0 0 0 0 0 0 0 -B

PPG0 down counter register

R

W

PPG0 cycle set register

16 bit

PPG0

PPG0 duty setting register

PPG0 control status register

PPG1 down counter register

PPG1 cycle set register

W

R/W

R

W

16 bit

PPG1

PPG1 duty setting register

PPG1 control status register

W

R/W

000080H

to

(Reserved)

000095H

000096^H

000097^H

Prohibited

(Reserved)

000098^H

to

Prohibited

00009DH

00009E^H

00009FH

0000A0H

PACSR

DIRR

ROM correction control register

Delayed interrupt/release

R/W

ROM Correction 0 0 0 0 0 0 0 0B

Delayed interrupt

- - - - - - - 0B

LPMCR

Low power consumption mode

Low power

consumption

control circuit

0 0 0 1 1 0 0 0B

0000A1H

CKSCR

Clock selector

R/W

1 1 1 1 1 1 0 0B

0000A2H

to

Prohibited

0000A7H

0000A8^H

0000A9H

WDTC

TBTC

Watchdog control

R/W

Watchdog timer

XXXXX 1 1 1B

Time-base timer control register

Time-base timer 1 - - 0 0 1 0 0B

Watch timer

1 X0 1 1 0 0 0B

(Sub clock)

0000AAH

WTC

Watch timer control register

R/W

0000AB^H

to

Prohibited

0000ADH

(Continued)

22

MB90800 Series

(Continued)

Register

abbreviation

Read/

Write

Address

Register

Flash control register

Resource name

Initial Value

0 0 0 X 0 0 0 0B

XXXXX 0 0 0B

0000AE^H

0000AFH

FMCS

R/W

Flash I/F

Timer clock

devide

TMCS

Timer clock output control register

R/W

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

001FF0H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

R/W

0 0 0 0 0 1 1 1B

XXXXXXXX^B

Interrupt

controller

PADR0

Program address detection register 0

XXXXXXXXB

Address

matching

detection function

XXXXXXXXB

XXXXXXXX^B

PADR1

VRAM

Program address detection register 1

LCD display RAM

XXXXXXXXB

007900H

to

007917H

LCD controller/

driver

R/W

XXXXXXXXB

• Read/Write

R/W Readable and Writable

R

Read only

Write only

W

• Initial values

0

Initial Value is “0”.

1

Initial Value is “1”.

X

Initial Value is Indeterminate.

23

MB90800 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS

EI²OS

readiness

Interrupt vector

Number* Address

08H FFFFDCH

Interrupt control register

Interrupt source

Priority

ICR

Address

Reset

×

#08

#09

#10

#11

#13

#15

#16

#17

#18

#19

#21

#23

#24

#25

#26

#27

#29

#31

#33

#35

#36

#37

#38

#39

#40

#41

#42

High

INT 9 instruction

09^HFFFFD8H

0AH FFFFD4H

0BH FFFFD0H

0DH FFFFC8H

0FH FFFFC0H

10H FFFFBCH

11H FFFFB8H

12H FFFFB4H

13H FFFFB0H

15H FFFFA8H

17H FFFFA0H

18H FFFF9CH

19H FFFF98H

1AH FFFF94H

1BH FFFF90H

1DH FFFF88H

1FH FFFF80H

21H FFFF78H

23H FFFF70H

24H FFFF6CH

25H FFFF68H

26H FFFF64H

27H FFFF60H

28H FFFF5CH

29H FFFF58H

2AH FFFF54H

Exceptional treatment

DTP/External interrupt ch0

DTP/External interrupt ch1

Serial I/O ch2

ICR00

ICR01

0000B0H

0000B1H

×

ICR02

ICR03

0000B2H

0000B3H

DTP/External interrupt ch2/3

Serial I/O ch3

16-bit free-run timer

Watch timer

ICR04

ICR05

0000B4H

0000B5H

16-Bit Reload Timer ch2

16-Bit Reload Timer ch0

16-Bit Reload Timer ch1

Input capture ch0

ICR06

ICR07

0000B6H

0000B7H

Input capture ch1

PPG timer ch0 counter-borrow

Output compare match

PPG timer ch1 counter-borrow

Time-base timer

ICR08

ICR09

ICR10

ICR11

0000B8H

0000B9H

0000BAH

0000BBH

×

UART0 reception end

UART0 transmission end

A/D converter conversion termination

I²C Interface

ICR12

ICR13

ICR14

ICR15

0000BCH

0000BDH

0000BEH

0000BFH

UART1 : Reception

UART1 : Transmission

Flash memory status

Delayed interrupt output module

×

Low

: Available

× : Unavailable

: Available El²OS function is provided.

: Available when a cause of interrupt sharing a same ICR is not used.

* : When interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector

number has the priority.

• When there are two interrupt causes in the same interrupt control register (ICR) and use of IIOS is enabled,

IIOS is started upon detection of one of the interrupt causes. As interrupts other than the start cause are

masked during IIOS start, masking one of the interrupt requests is recommended when using IIOS.

• For a resource that has two interrupt causes in the same interrupt control register (ICR), the interrupt flag is

cleared by an IIOS interrupt clear signal.

24

MB90800 Series

■ PERIPHERAL RESOURCES

1. I/O port

The I/O ports function to output data from the CPU to I/O pins via their port data register (PDR) and send signals

input to I/O pins to the CPU. In addition, the port can randomly set the direction of the input/output of the I/O pin

in bit by the port direction register (DDR).

The MB90800 series has 68 (70 ports when the subclock is not used) input/output pins. Port0 to port8 (port0 to

port9 when the subclock is not used) are input/output port.

(1) Port data register

PDR0

Initial Value Access

Indeterminate R/W*

7

6

5

4

3

2

1

0

Address : 000000^H

P07

P06

P05

P04

P03

P02

P01

P00

PDR1

15

14

13

12

11

10

9

8

Address : 000001^H

Indeterminate R/W*

P17

P16

P15

P14

P13

P12

P11

P10

PDR2

7

6

5

4

3

2

1

0

Address : 000002^H

P27

P26

P25

P24

P23

P22

P21

P20

PDR3

15

14

13

12

11

10

9

8

Address : 000003^H

P37

P36

P35

P34

P33

P32

P31

P30

PDR4

7

6

5

4

3

2

1

0

Address : 000004^H

P47

P46

P45

P44

P43

P42

P41

P40

PDR5

15

14

13

12

11

10

9

8

Address : 000005^H

P57

P56

P55

P54

P53

P52

P51

P50

PDR6

7

6

5

4

3

2

1

0

Address : 000006^H

P67

P66

P65

P64

P63

P62

P61

P60

PDR7

15

7

14

13

12

11

10

9

8

Address : 000007^H

P76

P75

P74

P73

P72

P71

P70

PDR8

6

5

4

3

2

1

0

Address : 000008^H

P84

P83

P82

P81

P80

PDR9

15

14

13

12

11

10

9

8

Address : 000009^H

P91

P90

When reading : Read the corresponding pin level.

When writing : Write into the latch for the input/output.

• Output mode

When reading : Read the value of the data register latch.

When writing : Write into the corresponding pin.

25

MB90800 Series

(2) Port direction register

DDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 000010^H

00000000B

- 0000000B

- - - 00000B

- - - - - - 00B

R/W

D07

D06

D05

D04

D03

D02

D01

D 00

DDR1

15

14

13

12

11

10

9

8

Address : 000011^H

D17

D16

D15

D14

D13

D12

D11

D10

DDR2

7

6

5

4

3

2

1

0

Address : 000012^H

D27

D26

D25

D24

D23

D22

D21

D20

DDR3

15

14

13

12

11

10

9

8

Address : 000013^H

D37

D36

D35

D34

D33

D32

D31

D30

DDR4

7

6

5

4

3

2

1

0

Address : 000014^H

D47

D46

D45

D44

D43

D42

D41

D40

DDR5

15

14

13

12

11

10

9

8

Address : 000015^H

D57

D56

D55

D54

D53

D52

D51

D50

DDR6

7

6

5

4

3

2

1

0

Address : 000016^H

D67

D66

D65

D64

D63

D62

D61

D60

DDR7

15

7

14

13

12

11

10

9

8

Address : 000017^H

D75

D74

D73

D72

D71

D70

D76

DDR8

6

5

4

3

2

1

0

Address : 000018^H

D84

D83

D82

D81

D80

DDR9

15

14

13

12

11

10

9

8

Address : 000019^H

D91

D90

• When each terminal functions as a port, each correspondent pin are controlled to following;

0 : Input mode

1 : Output mode This bit becomes “0” after a reset.

Note : When accessing this register by using the instruction of the read modify write system (instructions such as

bit set) is mode, the bit targeted by an instruction becomes the defined value, while the content of the output

register set with the other. Therefore, be sure to write an expected value into PDR firstly, and then set DDR

and finally change to the output when changing the input pin to the output pin is made.

26

MB90800 Series

(3) Analog Input Enable register

ADER0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001E^H

11111111B

R/W

ADE3

ADE2

ADE1

ADE0

ADE7

ADE6

ADE5

ADE4

ADER1

15

14

13

12

11

10

9

8

Address : 00001F^H

- - - -1111B

R/W

ADE11 ADE10 ADE9

ADE8

Control each pin of Port 6 as follows.

0 : Port input/output mode.

1 : Analog input mode.This bit becomes “1” after a reset.

27

MB90800 Series

2. UART

UART is a serial I/O port for asynchronous (start-stop synchronization) communication or CLK synchronous

communications.

• With full-duplex double buffer

• Clock asynchronous (start-stop synchronization) , CLK synchronous communications (no start-bit/stop-bit)

can be used.

• Supports multi-processor mode

• Built-in dedicated baud rate generator

Asynchronous

: 120192/60096/30048/15024/781.25 K/390.625 Kbps

CLK synchronous : 25 M/12.5 M/6.25 M/3.125 M/1.5627 M/781.25 Kbps

• Variable baud rate can be set by an external clock.

• 7-bits data length (only asynchronous normal mode) /8-bits length

• Master/slave type communication function (at multiprocessor mode) : The communication between one (mas-

ter) to n (slave) can be operating.

• Error detection functions(parity, framing, overrun)

• Transmission signal format is NRZ

28

MB90800 Series

(1) Register list

15

8

7

0

CDCR

SCR

SSR

8 bit

SMR

SIDR (R)/SODR (W)

8 bit

Serial mode register (SMR)

7

6

5

4

3

2

1

0

000020^H

Address :

MD1

MD0

CS2

CS1

CS0

SCKE

SOE

000028H

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(

)

(R/W)

( 0 )

(R/W)

( 0 )

Initial Value

Serial control register(SCR)

15

14

P

13

12

11

10

9

8

000021^H

Address :

PEN

SBL

CL

A/D

REC

RXE

TXE

000029H

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

( W )

( 1 )

(R/W)

( 0 )

(R/W)

( 0 )

Serial input/output register (SIDR/SODR)

7

6

5

4

3

2

1

0

000022^H

00002AH

D7

D6

D5

D4

D3

D2

D1

D0

Address :

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

Serial Data Register (SSR)

15

14

13

12

11

10

9

8

000023^H

Address :

PE

ORE

FRE

RDRF TDRE

BDS

RIE

TIE

00002BH

( R )

( 0 )

( R )

( 0 )

( R )

( 0 )

( R )

( 0 )

( R )

( 1 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

Communication prescaler control register (CDCR)

15

14

13

12

11

10

9

8

000025^H

00002DH

Reserved

MD

URST

DIV2

DIV1

DIV0

Address :

(R/W)

( 0 )

(R/W)

( 0 )

(

)

(

)

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

29

MB90800 Series

(2) Block Diagram

Control signal

RXinterrupt

(to CPU)

Special-purpose

baud-rate generator

Clock

Transmission clock

TX interrupt

(to CPU)

selection

circuit

16-bit reload timer 0

Reception clock

Receptioncontrol

Transmission

control circuit

circuit

Start bit

detection circuit

Transmission

start circuit

Reception bit

counter

Transmission bit

counter

Transmission

parity counter

Reception

parity counter

Receive status

decision circuit

RX shifter

TX shifter

Reception

control

circuit

Reception error

occurrence signal

for EI²OS (to CPU)

Start

transmission

SIDR

SODR

F²MC-16LX BUS

MD1

MD0

CS2

PEN

PE

ORE

P

SBL

CL

FRE

RDRF

TDRE

BDS

RIE

SMR

Register

SCR

Register

SSR

Register

CS1

CS0

A/D

REC

REX

TXE

SCKE

SOE

TIE

Control signal

30

MB90800 Series

3. I²C Interface

I²C interface is the serial input/output port that support Inter IC BUS and functions as the master/slave device

on the I²C bus. MB90800 series have 1 channel of the built-in I²C interface.

It has the features of I²C interface below.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Detecting transmitting direction function

• Repeat generating and detecting function of the start conditions

• Bus error detection function

• The forwarding rate can be supported to 100 Kbps.

(1) Register list

I²C status register (IBSR)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address :00006A^H

BB

RSC

AL

LRB

TRX

AAS

GCA

FBT

R

I²C control register (IBCR)

Address :00006BH

15

14

13

12

11

10

9

8

00000000B

BER

R/W

BEIE

R/W

SCC

R/W

MSS

R/W

ACK

R/W

GCAA

R/W

INTE

R/W

INT

R/W

I²C clock control register (ICCR)

7

6

5

4

3

2

1

0

Address :00006CH

XX0XXXXXB

XXXXXXXXB

EN

R/W

CS4

R/W

CS3

R/W

CS2

R/W

CS1

R/W

CS0

R/W

I²C data register(IDAR)

15

14

13

12

11

10

9

8

Address :00006EH

D7

D6

D5

D4

D3

D2

D1

D0

R/W

I²C address register (IADR)

Address :00006DH

7

6

5

4

3

2

1

0

A6

A5

A4

A3

A2

A1

A0

R/W

31

MB90800 Series

(2) Block Diagram

ICCR

EN

I²C Enable

Clock divide 1

Machine clock

ICCR

CS4

5

6

7

8

Clock selector 1

Clock divide 2

CS3

CS2

CS1

CS0

Sync

2

4 8

16

32 64 128 256

Generating shift clock

Clock selector 2

Change timing of

shift clock edge

IBSR

BB

Bus busy

Repeat start

Last Bit

RSC

LRB

TRX

FBT

AL

Start stop Condition detection

Transfer/

reception

Error

First Byte

Arbitration lost detection

IBCR

BER

SCL

SDA

BEIE

INTE

INT

IRQ

Interrupt request

End

IBCR

SCC

Start

Master

MSS

ACK

Start stop Condition detection

ACK enable

GC-ACK enable

GCAA

IDAR

IBSR

AAS

Slave

Global call

Slave address

compare

GCA

IADR

32

MB90800 Series

4. Extended I/O serial interface

The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8 bit ×

2 channel configured clock synchronization scheme. The extended I/O serial interface also has two alternatives

in data transfer called LSB first and MSB sirst.

The serial I/O interface operates in two modes:

• Internal shift clock mode : Transfer data in sync with the internal clock.

• External shift clock mode : Transfers data in sync with the clock input through an external pin (SCK) . In this

mode, transfer operation performed by the CPU instruction is also available by

operating the general-use port sharing an external pin (SCK) .

(1) Register list

Serial mode control status register(SMCS)

Initial Value

15

14

13

12

11

10

9

8

000060^H

000064H

Address :

00000010B

SMD2 SMD1 SMD0

SIE

SIR

BUSY

STOP

STRT

R/W

7

R/W

6

R/W

5

R/W

4

R/W

R

R/W

3

2

1

0

000061H

000065H

Address :

----0000B

MODE

BDS

SOE

SCOE

R/W

Serial Data Register (SDR)

7

6

5

4

3

2

1

0

000062H

Address :

XXXXXXXX

0---0000

D7

D6

D5

D4

D3

D2

D1

D0

000066H

R/W

Communication Prescaler control register (SDCR0, SDCR1)

15

14

13

12

11

10

9

8

000063^H

000067H

Reserved

Address :

MD

DIV2

DIV1

DIV0

R/W

33

MB90800 Series

(2) Block Diagram

Internal data bus

Initial Value

(MSB fast) D0 to D7

(LSB fast) D7 to D0

Transfer direction selection

SI2, SI3

Read

Write

SDR (Serial Data Register)

SO2, SO3

SC2, SC3

Shift clock counter

Control circuit

Internal clock

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

34

MB90800 Series

5. 8/10-bit A/D converter

A/D converter converts an analog input voltage into digital value. The feature of A/D converter is shown as follows.

• conversion time : 3.1 µs minimum per 1 channel

(78 machine cycle/at machine clock 25 MHz/including the sampling time)

• Sampling time : 2.0 µs minimum per 1channel

(50 machine cycle/at machine clock 25 MHz)

• Uses RC-type successive approximation conversion method with a sample & hold circuit

• 8-bit resolution or 10-bit resolution can be select.

• 12 channel program-selectable analog inputs.

Single conversion mode

Scan conversion mode

: Convert 1 specified channel

: Continuous plural channels (maximum 12 channels can be programmed) are

converted.

Continuous conversion mode : Selected channel converted continuously.

Stop conversion time : Perform conversion for one channel, then wait for the next activation trigger

(synchronizes the conversion start timing)

• EI²OS can be activated by outputting the interrupt request when the A/D conversion completes.

• If the A/D conversion is performed under the condition of the interrupt enable, the converting data will be

protected.

• Selectable conversion activation trigger : Software, or reload timer (rising edge)

(1) Register list

ADCS1, ADCS0 (Control status register)

ADCS0

7

6

5

4

3

2

1

0

8

Address : 000034^H

MD1

MD0

←Initial Value

←bit

0

R/W

ADCS1

bit

15

14

13

12

11

10

9

Address : 000035H

BUSY

INT

INTE

PAUS

STS1

STS0

STRT Reserved

←Initial Value

←bit

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

W

0

R/W

ADCR1, ADCR0 (data register)

ADCR0

bit

7

6

5

4

3

2

1

0

Address : 000036H

D7

D6

D5

D4

D3

D2

D1

D0

←Initial Value

←bit

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

ADCR1

bit

15

14

13

12

11

10

9

8

Address : 000037^H

S10

ST1

ST0

CT1

CT0

D9

D8

←Initial Value

←bit

0

W

0

W

1

W

0

W

1

W

X

R

X

R

35

MB90800 Series

(2) Block Diagram

AVCC

AVR

MP

AVSS

AN0

AN1

AN2

AN3

D/A converter

AN4

Input

circuit

AN5

AN6

AN7

AN8

AN9

AN10

AN11

Sequential compare

register

Comparator

Sample & hold circuit

Data register

ADCR0, ADCR1

Decoder

A/D channel set register

A/D Control register 0

A/D Control register 1

ADCS0, ADCS1,

ADMR

Timer start-up

16-Bit Reload Timer

Operation clock

φ

Prescaler

36

MB90800 Series

6. 16 bits PPG

The PPG timer consists of the prescaler, one 16-bit down-counter, one 16-bit data register with a cycle setting

buffer, a 16-bit compare register with a duty setting buffer, and the pin control unit.

The PPG timer can output pulses synchronized to the software trigger.

The period and duty of the output pulse can be changed freely by updating two 16-bit register values.

• PWM function

The PPG timer can output pulses programmably by updating the values of the registers described above in

synchronization to the trigger.

Can also be used as a D/A converter by an external circuit.

• Single shot function

By detecting an edge of the trigger input, a single pulse can be output.

• 16-bit down counter

The counter operation clock comes from eight kinds optional. There are eight kinds of internal clocks.

(φ, φ2, φ4, φ8, φ16, φ32, φ64, φ128) φ : machine clock

The counter is initialized to " FFFF^H" at a reset or counter borrow.

• Interrupt request

The PPG timer generates an interrupt request when :

Timer start-up/counter borrow occurs (cycle match) /duty match occurs/counter borrow occurs (cycle match) ,

or duty match occurs.

37

MB90800 Series

(1) Register list

PCNTH (PCNTH0/1 Control Status register)

15

14

13

12

11

10

9

8

000077^H

00007FH

CNTE STGR MDSE RTRG

CSK2

CSK1

CSK0 PGMS

(R/W) ( R/W ) (R/W)

( 0 ) ( 0 ) ( 0 )

(R/W)

( 0 )

(R/W) ( R/W ) ( R/W ) ( R/W )

Read/Write

Initial Value

( 0 )

( X )

PCNTL (PCNTL0/1 Control Status register)

7

6

5

4

3

2

1

0

000076H

00007EH

IREN

IRQF

IRS1

IRS0

POEN

OSEL

(

)

(

)

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

Read/Write

Initial Value

PDCRH (PDCRH0/1 PPG Down Counter Register)

15

14

13

12

11

10

9

8

000071^H

000079H

DC15

DC14

DC13

DC12

DC11

DC10

DC09

DC08

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

Read/Write

Initial Value

PDCRL (PDCRL0/1 PPG Down Counter Register)

7

6

5

4

3

2

1

0

000070^H

000078H

DC07

DC06

DC05

DC04

DC03

DC02

DC01

DC00

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

(R)

( 1 )

Read/Write

Initial Value

PCSRH (PCSRH0/1 PPG cycle set register)

15

14

13

12

11

10

9

8

Read/Write

Initial Value

000073^H

00007BH

CS15

CS14

CS13

CS12

CS11

CS10

CS09

CS08

(W)

( X )

PCSRL (PCSRH0/1 PPG cycle set register)

7

6

5

4

3

2

1

0

000072^H

00007AH

CS07

CS06

CS05

CS04

CS03

CS02

CS01

CS00

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

Read/Write

Initial Value

PDUTH (PDUTH0/1 PPG duty set register)

15

14

13

12

11

10

9

8

000075H

00007DH

DU15

DU14

DU13

DU12

DU11

DU10

DU09

DU08

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

Read/Write

Initial Value

PDUTL (PDUTL0/1 PPG duty set register)

7

6

5

4

3

2

1

0

000074H

00007CH

DU07

DU06

DU05

DU04

DU03

DU02

DU01

DU00

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

(W)

( X )

Read/Write

Initial Value

38

MB90800 Series

(2) Block Diagram

・16-bit G ch0/1 block diagram

Prescaler

1/1

1/2

PCSR

PDUT

1/4

1/8

1/16

1/32

1/64

1/128

Load

CK

CMP

PCNT

16-bit down counter

Start Borrow

PPG mask

Machine clock φ

S

R

Q

PPG output

Reverse bit

Enable

Interrupt

select

Interrupt

Soft trigger

39

MB90800 Series

7. Delay interrupt generator module

The delayed interrupt generation module outputs an interrupt request for task swiching. When the delayed

interrupt generation module is used, software is allowed to output and clear task switching interrupts for the

MB90800 Series CPU.

(1) Register list

Delayed Interrupt/release register(DIRR)

DIRR

Initial Value

15

14

13

12

11

10

9

8

Address : 00009F^H

- - - - - - - 0B

R0

R/W

(2) Block diagram

2

F MC-16LX bus

Delay interruption factor generation/

release decoder

Factor latch

40

MB90800 Series

8. DTP/External interrupt

DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external

interrupt input terminal, and outputs the interrupt request.

(1) Register list

Interrupt/DTP enable register (ENIR : Enable Interrupt Request Register)

ENIR

Initial Value

7

6

5

4

3

2

1

0

Address : 000030^H

- - - - 0000B

EN3

R/W

EN2

R/W

EN1

R/W

EN0

R/W

Interrupt/DTP source register (EIRR : External Interrupt Request Register)

EIRR

Initial Value

15

14

13

12

11

10

9

8

Address : 000031^H

- - - - XXXXB

ER3

R/W

ER2

R/W

ER1

R/W

ER0

R/W

Request level setting register (ELVR : External Level Register)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 000032H

LB3

R/W

LA3

R/W

LB2

R/W

LA2

R/W

LB1

R/W

LA1

R/W

LB0

R/W

LA0

R/W

(2) Block diagram

2

F MC-16LX bus

4

8

Interrupt/DTP enable register

4

Edge detection circuit

Source F/F

Request input

Gate

Interrupt/DTP source register

Request level setting register

41

MB90800 Series

9. 16-bit input/output timer

The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare and two input capture modules.

This function enables six independent waveforms to be output based on the 16-bit free-run timer, and input pulse

widths and external clock frequencies to be measured.

・Register list

・16-bit free-run timer

15

0

00003B/3AH

00003D/3CH

00003F/3EH

CPCLR

TCDT

TCCS

Compare clear register

Timer counter data register

Timer counter

control status register

・16-bit Output Compare

15

0

00004AH/00004BH/

00004CH/00004DH

Compare register

OCCP0 OCCP1

Control status register

00004FH/00004EH

OCSH

OCSL

・16-bit Input Capture

15

0

000044H/000045H/

000046H/000047H

Data register

IPCP0, IPCP1

Control status register

000048H

ICS01

42

MB90800 Series

・Block diagram

Control logic

Interrupt

16-bit free-run timer

To each

block

16-bit timer

Clear

Output

compare 0

OTE0

OTE1

Compare register 0

Compare register 1

TQ

Output

compare 1

Input capture 0

Input capture 1

Capture register 0

Capture register 1

Edge select

IC0

IC1

43

MB90800 Series

(1) 16-bit free-run timer

The 16-bit free-run timer consists of a 16-bit up-down counter and control status register.

Counter value of 16-bit free-run timer is available as base timer for input capture and output compare.

• Clock for the counter operation can be selected from eight types.

• The counter overflow interruption can be generated.

• Setting the mode enables initialization of the counter through compare-match operation with the value of the

compare clear register in the output compare.

・Register list

Compare clear register (CPCLR)

Initial Value

15

14

13

12

11

10

9

8

00003B^H

XXXXXXXXB

CL15

(R/W)

CL14

(R/W)

CL13

(R/W)

CL12

(R/W)

CL11

(R/W)

CL10

(R/W)

CL09

(R/W)

CL08

(R/W)

Initial Value

7

6

5

4

3

2

1

0

00003AH

XXXXXXXXB

CL07

(R/W)

CL06

(R/W)

CL05

(R/W)

CL04

(R/W)

CL03

(R/W)

CL02

(R/W)

CL01

(R/W)

CL00

(R/W)

Timer counter data register (TCDT)

Initial Value

00000000B

15

14

13

12

11

10

9

8

00003D^H

T15

T14

T13

T12

T11

T10

T09

T08

(R/W)

Initial Value

00000000B

7

6

5

4

3

2

1

0

00003C^H

T07

T06

T05

T04

T03

T02

T01

T00

(R/W)

Timer counter control/status register (TCCS)

Initial Value

0--00000B

15

14

13

12

11

10

9

8

00003FH

ECKE

(R/W)

MSI2

(R/W)

MSI1

(R/W)

MSI0

(R/W)

ICLR

(R/W)

ICRE

(R/W)

Initial Value

00000000B

7

6

5

4

3

2

1

0

00003EH

IVF

IVFE

(R/W)

STOP MODE SCLR

(R/W) (R/W) (R/W)

CLK2

(R/W)

CLK1

(R/W)

CLK0

(R/W)

44

MB90800 Series

・Block diagram

φ

Interrupt request

Divider

IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0

Clock

16-bit free-run timer

Count value output T15 to T00

16-bit compare clear register

MSI2 MSI0

Compare cir-

ICLR ICRE

Interrupt request

45

MB90800 Series

(2) Output compare

The output compare consists of 16-bit compare registers, compare output pin part and a control register. It can

reverse the output level for the pin and at the same time, generate an interrupt when the 16-bit free-run timer

value matches a value set in one of the 16-bit compare registers of this module.

• It has a total of six compare registers that can operate independently. In addition, the output can be set to be

controlled by using two compare registers.

• An interrupt can be set by a comparing match.

・Register list

Compare register (OCCP0, OCCP1)

Initial Value

15

14

13

12

11

10

9

8

00004BH

00004DH

00000000B

OP15

(R/W)

OP14

(R/W)

OP13

(R/W)

OP12

(R/W)

OP11

(R/W)

OP10

(R/W)

OP09

(R/W)

OP08

(R/W)

Initial Value

00000000B

7

6

5

4

3

2

1

0

00004AH

00004CH

OP07

(R/W)

OP06

(R/W)

OP05

(R/W)

OP04

(R/W)

OP03

(R/W)

OP02

(R/W)

OP01

(R/W)

C00

(R/W)

Control register (OCSH)

00004F^H

Initial Value

---00000B

15

14

13

12

11

10

9

8

CMOD OTE1

OTE0

(R/W)

OTD1

(R/W)

OTD0

(R/W)

(

)

(

)

(

)

(R/W)

Control register (OCSL)

00004E^H

Initial Value

0000--00B

7

6

5

4

3

2

1

0

IOP1

IOP0

IOE1

IOE0

(R/W)

CST1

(R/W)

CST0

(R/W)

(

)

(

)

46

MB90800 Series

・Block diagram

16-bit timer counter value (T15 to T00)

Compare control

TQ

CMOD

TQ

OTE0

Compare register 0

16-bit timer counter value (T15 to T00)

Compare control

OTE1

Compare register 1

ICP1 ICP0 ICE0 ICE0

Interrupt

#29

Control logic

#29

Each control blocks

47

MB90800 Series

(3) Input capture

This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16-

bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.

The input capture consists of input capture and control registers. Each input capture has its corresponding

external input pin.

• The detection edge of an external input can be selected from among three types. Rising edge/falling edge/

both edges.

• It can generate an interrupt when it detects the valid edge of the external input.

・Register list

Input capture data register (IPCP0, IPCP1)

Initial Value

15

14

13

12

11

10

9

8

XXXXXXXXB

000045^H

000047H

CP15

( R )

CP14

( R )

CP13

( R )

CP12

( R )

CP11

( R )

CP10

( R )

CP09

( R )

CP08

( R )

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

000044^H

000046H

CP07

( R )

CP06

( R )

CP05

( R )

CP04

( R )

CP03

( R )

CP02

( R )

CP01

( R )

CP00

( R )

Control status register (ICS01)

Initial Value

00000000B

7

6

5

4

3

2

1

0

000048^H

ICP1

ICP0

(R/W)

ICE1

(R/W)

ICE0

(R/W)

EG11

(R/W)

EG10

(R/W)

EG01

(R/W)

EG00

(R/W)

48

MB90800 Series

・Block diagram

IC0

Capture data register 0

Edge detection

16-bit timer counter value (T15 to T00)

Capture data register 1

EG11 EG10 EG01 EG00

Edge detection

IC1

ICP1 ICP0 ICE1 ICE0

Interrupt #25

49

MB90800 Series

10. 16-bit reload timer

The 16-bit reload timer provides two functions either one which can be selected, the internal clock the performs

the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count

down by detecting the arbitration. This timer defines an underflow as a transition of the count value from 0000H

to FFFFH. Therefore, when the equation (counted value = reload register setting value+1) holds, an underflow

occurs. Either mode can be selected for the count operation from the reload mode which repeats the count by

reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at

the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to corre-

spond to the DTC.

(1) Register list

• TMCSRTimer control status register

Timer control status register (upper) (TMCSR)

15

14

13

12

11

10

9

8

000051^H

000055H

000059H

CSL1

CSL0

MOD2 MOD1

Read/Write

Initial Value

(

)

(

)

(

)

(

)

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

Timer control status register (lower) (TMCSR)

7

6

5

4

3

2

1

0

000050^H

000054H

000058H

MOD0 OUTE OUTL

RELD

INTE

UF

CNTE

TRG

Read/Write

Initial Value

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

• 16-bit timer register/16-bit reload register TMR/TMRLR (upper)

15

14

13

12

11

10

9

8

000053^H

000057H

00005BH

D15

D14

D13

D12

D11

D10

D9

D8

Read/Write

Initial Value

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

TMR/TMRLR (low)

7

6

5

4

3

2

1

0

000052^H

000056H

00005AH

D7

D6

D5

D4

D3

D2

D1

D0

Read/Write

Initial Value

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

(R/W)

( X )

50

MB90800 Series

(2) Block diagram

Internal data bus

TMRLR

16-bit reload register

Reload signal

TMR

Reload control

circuit

16-bit timer register

(down counter)

UF

CLK

Count clock generation circuit

Gate

input

Wait signal

3

Valid clock

identification circuit

Machine

clock φ

Prescaler

Clear

CLK

Output signal

generation circuit

Re-

verse

Clock

selector

Inputcontrol

Output signal

generation circuit

circuit

EN

External clock

Operation

control circuit

OUTL

RELD

3

2

Select

function

Select signal

OUTE

Timer control status register (TMCSR)

51

MB90800 Series

11. Watch timer

The watch timer is a 15-bit timer using the subclock. It can generate interval interrupts. The watch timer can also

be used as the clock source of the watchdog timer by setting so.

(1) Register list

Watch timer control register (WTC)

7

6

5

4

3

2

1

0

0000AA^H

WDCS

SCE

WTIE

WTOF

WTR

WTC2 WTC1

WTC0

(R/W)

( 1 )

( R )

( X )

(R/W)

( 0 )

(R/W)

( 1 )

(R/W)

( 1 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

Initial Value

(2) Block diagram

Watch timer control register (WTC)

WDCS

SCE

WTIE

WTOF

WTR

WTC2

WTC1 WTC0

Clear

2⁸

2⁹

Sub clock

Interrupt

generation

circuit

Interval

selector

2¹⁰

2¹¹

2¹²

2¹³

2¹⁴

Watch timer

interrupt

Watch counter

2¹⁰2¹³2¹⁴2¹⁵

To watchdog timer

52

MB90800 Series

12. Watchdog timer

The watchdog timer is a 2-bit counter operating with an output of the timebase timer or watch timer and resets

the CPU when the counter is not cleared for a preset period of time.

(1) Register list

Watchdog timer control register (WDTC)

7

6

5

4

3

2

1

0

0000A8^H

PONR

WRST

ERST

SRST

WTE

WT1

WT0

( R )

( X )

(

)

( R )

( X )

( R )

( X )

( R )

( X )

( W )

( 1 )

( W )

( 1 )

( W )

( 1 )

Initial Value

( X )

(2) Block diagram

Watchdog timer control register (WDTC)

PONR

―

WRST ERST SRST WTE WT1 WT0

WDCS bit of watch timer

control register (WTO)

2

SCM bit of clock selection

register (CKSCR)

Watch mode start

Timebase timer mode start

Sleep mode start

Hold status start

CLR and start-up

Watchdog timer

CLR

Counter

clear control

circuit

Count

clock

selector

Watchdog reset

generation

circuit

2-bit

counter

Internal

reset

generation

circuit

Stop mode start

CLR

4

Clear

Time base counter

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

Dividing HCLK by 2

SCLK

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

HCLK: Oscillation clock

SCLK: Sub clock

53

MB90800 Series

13. Time-base timer

The time-base timer has a function that enables a selection of four interval times using 18-bit free-run counter

(time-base counter) with synchronizing to the internal count clock (two division of original oscillation). Further-

more, the function of timer output of oscillation stabilization wait or function supplying operation clocks for

watchdog timer are provided.

(1) Register list

Timer base timer control register (TBTC)

15

14

13

12

11

10

9

8

0000A9^H

Reserved

TBIE

TBOF

TBR

TBC1

TBC0

(R/W)

( 1 )

(

)

(

)

(R/W)

( 0 )

(R/W)

( 0 )

( W )

( 1 )

(R/W)

( 0 )

(R/W)

( 0 )

(2) Block diagram

To PPG timer

Time-base timer counter

To watchdog timer

Dividing HCLK by 2

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

OF

Power-on reset

Stop mode start

To clock controller

Oscillationstabilizing

Wait time selector

Counter

clear

control

circuit

Hold status start

CKSCR : MCS = 0*¹

Interval timer selector

TBOF clear

CKSCR : SCS = 0→1*²

TBOF set

Time-base timer control register (TBTC)

Time-base timer interrupt signal

: Unused

RESV

TBIE TBOF TBR TBC1 TBC0

OF

: Overflow

HCLK : Oscillation clock

*1

*2

: The machine clock is switched from main/sub clock to PLL clock.

: The machine clock is switched from sub clock to main clock.

54

MB90800 Series

14. Clock

TheclockgeneratorcontrolsoperationoftheinternalclockwhichistheoperationclockfortheCPUandperipheral

devices. This internal clock is referred to as machine clock and its one cycle as machine cycle. In addition, the

clock generated by original oscillation is referred to as oscillation clock and that by internal PLL oscillation as

PLL clock.

(1) Register list

Clock selection register (CKSCR)

15

14

13

12

11

10

9

8

0000A1^H

SCM

MCM

WS1

WS0

SCS

MCS

CS1

CS0

( R )

( 1 )

( R )

( 1 )

(R/W)

( 1 )

(R/W)

( 1 )

(R/W)

( 1 )

(R/W)

( 1 )

(R/W) ( R/W )

( 0 ) ( 0 )

Initial Value

55

MB90800 Series

(2) Block diagram

Standby control circuit

Low power consumption mode control register (LPMCR)

Reserved

STP SLP SPL RST TMD CG1 CG0

Pin High-Z

control circuit

Pin High-Z control

Internal reset

generation circuit

RST

Internal reset

CPU intermittent

operation selector

Intermittent cycle selection

CPU clock

control circuit

Standby control

circuit

Stop, sleep signal

Release

interrupting

Stop signal

Peripheral clock

control circuit

Peripheral clock

Machine clock

Oscillation stabilization wait

Clock generation block

Clock

selector

Oscillation

stabilization

wait time

2

SCLK

Dividing

by 4

selector

2

PLL multiplying

circuit

SCM MCM WS1 WS0 SCS MCS CS1 CS0

Sub clock

generation

circuit

Clock selection register (CKSCR)

System

clock

generation

circuit

X0A

Dividing

by 2

Dividing

by 2

Dividing

by 4

Dividing

by 2

Dividing

by 4

Dividing

by 4

by

1024

X1A Pin

HCLK MCLK

X0

X1

Time-base timer

To watchdog timer

HCLK : Oscillation clock

MCLK : Main clock

SCLK : Sub clock

56

MB90800 Series

(3) Clock supply map

Clock generation circuit

Timer clock divider

Watchdog timer

X0

X1

Watch timer

Oscillation

circuit

Internal resources

Selector

X0A

X1A

Oscillation

circuit

LCD controller

16-Bit Reload Timer

8/10-bit A/D converter

Serial I/O

Time-base timer

Free-run timer

Input capture

1

2

3

4

PLL multiplying circuit

PCLK

CPU (F²MC-16LX)

2 division circuit

Selector

HCLK

MCLK

ROM/RAM (memory)

2 division circuit

SCLK

HCLK : Oscillation clock frequency

MCLK : Main clock frequency

PCLK : PLL clock frequency

SCLK : Sub clock frequency

57

MB90800 Series

15. Low power consumption mode

The MB90800 Series have the following CPU operation modes by selecting the operation clock and operating

the control of the clock.

• Clock mode

(PLL clock mode, main clock mode and sub clock mode)

• CPU intermittent operation mode

(PLL clock intermittent operation mode, main clock intermittent operation mode and subclock intermittent

operation mode)

• Standby mode

(Sleep mode, time base timer mode, stop mode and watch mode)

(1) Register list

Low power consumption mode control register (LPMCR)

7

6

5

4

3

2

1

0

0000A0^H

Reserved

STP

SLP

SPL

RST

TMD

CG1

CG0

( W )

( 0 )

( W )

( 0 )

(R/W)

( 0 )

( W )

( 1 )

(R/W)

( 1 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

Initial Value

58

MB90800 Series

(2) Block diagram

Standby control circuit

Low power consumption mode control register (LPMCR)

Reserved

STP SLP SPL RST TMD CG1 CG0

Pin High-Z

control circuit

Pin High-Z control

Internal reset

RST

generation

Internal reset

circuit

CPU intermittent

operation selector

Intermittent cycle selection

CPU clock

control circuit

Standby control

Stop, sleep signal

Stop signal

Release of

interrupt

circuit

Peripheral

Peripheralclock

clock control

Machine clock

Release of oscillation stabilization wait

Clock generation block

Clock

selector

Oscillation

stabilization

wait time

2

SCLK

selector

Dividing

by 4

2

PLL multiplying

circuit

SCM MCM WS1 WS0 SCS MCS CS1 CS0

Sub

clock

Clock selection register (CKSCR)

generation

circuit

System

clock

generation

circuit

X0A

X1A

Dividing

by 1024

Dividing

by 4

Dividing

by 2

Dividing

by 2

Dividing

by 2

Dividing

by 4

Dividing

by 4

HCLK MCLK

X0

X1

Time-base timer

To watchdog timer

HCLK : Oscillation clock

MCLK : Main clock

SCLK : Sub clock

59

MB90800 Series

(3) Figure of status transition

External reset, watchdog timer reset, software reset,

Power supply

Power-on reset

Reset

SCS = 0

SCS = 1

MCS = 0

MCS = 1

SCS = 0

SCS = 1

Endofoscillation

stabilization wait

PLL clock mode

Main clock mode

Sub clock mode

SLP = 1

Interrupt

Main sleep mode

Interrupt

PLL sleep mode

Sub sleep mode

TMD = 0

Interrupt

Timebase

timer mode

Timebase

timer mode

Watch mode

STP = 1

PLL stop mode

Main stop mode

Sub stop mode

End of oscillation

stabilization wait

End of oscillation

stabilization wait

End of oscillation

stabilization wait

Interrupt

Main clock Oscillation

stabilization wait

Sub clock Oscillation

stabilization wait

Main clock Oscillation

stabilization wait

60

MB90800 Series

16. Timer clock output

The timer clock output circuit divides the oscillation clock by the time-base timer and generates and outputs the

set division clock. Selectable from 32/64/128/256 division of the oscillation clock.

The timer clock output circuit is inactive in reset or stop mode. Normally, it is active in run, sleep, or pseudo-

timer mode.

Pseudo

clock

PLL_Run

Main_Run

Sleep

STOP

Reset

Operation status

×

Note : When the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output.

For detail of the timebase timer’s clear condition, see the section of timebase timer in Hardware Manual.

(1) Register list

bit

Initial Value

XXXXX000B

15

14

13

12

11

10

9

8

Address : 0000AF^H

TEN

TS1

TS0

R/W

- : Unused

(2) Block diagram

Timer clock selection circuit

Selector

X0

X1

Timer clock output

Oscillation

circuit

Time-base timer

Dividing by 2

61

MB90800 Series

17. ROM mirrorring function selection module

ROM mirrorring function selection module can select that FF bank where ROM is located look into 00 bank

among the settings of the register.

(1) Register list

bit

Address : 00006F^H

Initial Value

XXXXXXX1B

15

14

13

12

11

10

9

8

―

MI

R/W

- : Unused

(2) Block diagram

2

F MC-16LX bus

ROM mirroring function selection

Address area

Address

FF bank

00 bank

Data

ROM

Note : Do not access to this register in the middle of the operation of the address 008000^Hto 00FFFFH.

62

MB90800 Series

18. Interrupt controller

Interrupt control register is in the interrupt controller. The register corresponds to all I/O of interrupt function. The

register has following functions;

• Setting of Interrupt level at correspondent peripheral circuit.

(1) Register list (at writing)

Interrupt control register

Address :

ICR01 0000B1^H

ICR03 0000B3H

Bit

15

14

13

12

11

10

9

8

ICR05 0000B5H

ICR07 0000B7H

ICR09 0000B9H

ICR11 0000BBH

ICR13 0000BDH

ICR15 0000BFH

ICR01, 03,

05, 07, 09, 11,

13, 15

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

Read/Write →

Initial Value →

W

( 0 )

W

( 0 )

W

( 0 )

W

( 0 )

R/W

( 0 )

R/W

( 1 )

R/W

( 1 )

R/W

( 1 )

Interrupt control register

Address :

ICR00 0000B0^H

ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR10 0000BAH

ICR12 0000BCH

ICR14 0000BEH

Bit

7

6

5

4

3

2

1

0

ICR00, 02,

04, 06, 08,

10, 12, 14

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

Read/Write →

Initial Value →

W

( 0 )

W

( 0 )

W

( 0 )

W

( 0 )

R/W

( 0 )

R/W

( 1 )

R/W

( 1 )

R/W

( 1 )

63

MB90800 Series

(2)Register list (at reading)

Interrupt control register

Address :

ICR01 0000B1^H

ICR03 0000B3H

ICR05 0000B5H

Bit

ICR01,

03, 05, 07,

09, 11, 13,

15

14

13

12

11

10

9

8

ICR07 0000B7H

ICR09 0000B9H

ICR11 0000BBH

ICR13 0000BDH

ICR15 0000BFH

S1

S0

ISE

IL2

IL1

IL0

Read/Write →

Initial Value →

R

( 0 )

R

( 0 )

R/W

( 0 )

R/W

( 1 )

R/W

( 1 )

R/W

( 1 )

(

)

(

)

Interrupt control register

Address :

ICR00 0000B0^H

ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR10 0000BAH

ICR12 0000BCH

ICR14 0000BEH

ICR00,

02, 04, 06,

08, 10, 12,

14

Bit

7

6

5

4

3

2

1

0

S1

S0

ISE

IL2

IL1

IL0

Read/Write →

Initial Value →

R

( 0 )

R

( 0 )

R/W

( 0 )

R/W

( 1 )

R/W

( 1 )

R/W

( 1 )

(

)

(

)

Note : Do not access using the read modify write instruction because it causes a malfunction.

64

MB90800 Series

(3) Block diagram

Interrupt request

(Peripheral resources)

3

32

IL2

IL1

IL0

Judging the priority

of interrupt

3

(CPU)

Interrupt level

65

MB90800 Series

19. LCD controller/driver

The LCD controller/driver contains 24 × 8-bit display data memory and controls the LCD display with four common

output lines and 48 segment output lines. Three duty outputs can be selected to directly drive the LCD panel

(liquid crystal display).

• Contains an LCD driving voltage split resistor. Moreover, the external division resistance can be connected.

• A maximum of four common output lines (COM0 to COM3) and 48 segment output lines (SEG0 to SEG47)

are available.

• Contains 24-byte display data memory (display RAM).

• For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting).

• The LCD can directly be driven.

Bias

1/2 duty

1/3 duty

1/4 duty

1/2 bias

1/3 bias

×

：Recommended mode

× ：Disable

(1) Register list

・LCR (LCD control register)

LCD control register (higher) (LCRH)

15

14

13

12

11

10

9

8

SS4

VS0

CS1

CS0

SS3

SS2

SS1

SS0

00005DH

Read/Write

Initial Value

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

LCD control register (lower) (LCRL)

7

6

5

4

3

2

1

0

CSS

LCEN

VSEL

BK

MS1

MS0

FP1

FP0

00005C^H

Read/Write

Initial Value

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 1 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

・LCDC range register (LCRR)

7

6

5

4

3

2

1

0

Reserved Reserved

SE4

SE3

SE2

SE1

SE0

LCR

00005E^H

Read/Write

Initial Value

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

(R/W)

( 0 )

66

MB90800 Series

(2) Block diagram

LCDC range register

(LCRR)

V0 V1 V2 V3

LCD Control register

(LCRL)

Division resistor

Main

Clock

4

COM0

Timing

controller

Common

driver

COM1

COM2

COM3

Prescaler

Sub clock

(32 kHz)

Circuit

of

making

to

exchange

SEG00

SEG01

SEG02

SEG03

SEG04

48

Segment

driver

Display RAM

24 × 8 bit

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

LCD Control register

(LCRH)

Controller

Driver

67

MB90800 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

VSS − 0.3

VSS + 4.0

V

Power supply voltage

AVCC

VCC ≥ AVCC*¹

*2

Input voltage

VI

N-ch O.D

(5 V withstand voltageI/O)

V^SS− 0.3

VSS − 0.3

VSS + 6.0

VSS + 4.0

10

V

Output voltage

VO

*2

Other than P74, P75,

P40 to P47*³

I^OL11

mA

“L” level maximum output current

“L” level average output current

P74, P75, P40 to P47

IOL12

I^OLAV1

IOLAV2

30

3

mA

(Heavy-current output port) *³

Other than P74, P75,

P40 to P47*⁴

P74, P75, P40 to P47

(Heavy-current output port) *⁴

15

mA

“L” level maximum total output current

“L” level average total output current

ΣIOL

120

60

ΣI^OLAV

mA *5

Other than P74, P75,

I^OH11

− 10

mA

P40 to P47*³

“H” level maximum output current

“H” level average output current

P40 to P47

(Heavy-current output port) *³

IOH12

IOHAV

ΣIOH

− 12

− 3

mA *4

mA

“H” level maximum total output

current

− 120

“H” level average total output current

Power consumption

ΣI^OHAV

Pd

− 60

351

mA *5

mW

Operating temperature

Storage temperature

TA

− 40

− 55

+ 85

+ 150

°C

Tstg

°C

The Absolute Maximum Ratings is based on VSS = AVSS = 0.0 V.

*1 : AV^CCshould not be exceeding VCC at power-on etc.

*2 : VI, VO, should not exceed Vcc + 0.3 V.

*3 : A peak value of an applicable one pin is specified as a maximum output current.

*4 : An average current value of an applicable one pin within 100 ms is specified as an average output current.

(Average value is found by multiplying operating current by operating rate.)

*5 : An average current value of all pins within 100 ms is specified as an average total output current.

(Average value is found by multiplying operating current by operating rate.)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

68

MB90800 Series

2. Recommended Operating Conditions

Value

Parameter

Symbol

Unit

Remarks

Min

2.7

Max

3.6

V

At normal operating

Power supply voltage

V^CC

1.8

3.6

Stop operation state maintenance

CMOS input pin

VIH

0.7 VCC

VCC + 0.3

CMOS hysteresis input pin

(Resisting pressure of 5 V is VCC = 5.0 V)

“H” level input voltage

V^IHS

0.8 VCC

VCC + 0.3

V

V^IHM

V^IL

VCC − 0.3

VSS − 0.3

− 40

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

+ 85

V

MD pin input

CMOS input pin

CMOS hysteresis input pin

MD pin input

“L” level input voltage

Operating temperature

V^ILS

VILM

T^A

V

°C

The Recommended Operating Conditions is based on VSS = AVSS = 0.0 V.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

69

MB90800 Series

3. DC Characteristics

Sym-

(VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C)

Value

Parameter

Pin name

Conditions

Unit

Remarks

bol

Min

Typ

Max

Outputpins

other than

P40toP47,

P74, P75

V^OH

IOH = − 4.0 mA VCC − 0.5

Vcc

V

“H” level output

voltage

Heavy-current

output port

VOH1 P40 to P47 IOH = − 8.0 mA VCC − 0.5

Vcc

Outputpins

other than

P40toP47,

P74, P75

V^OL

IOL = 4.0 mA

Vss

Vss + 0.4

“L” level output

voltage

Heavy-current

output port

V^OL1P40 to P47 IOL = 15.0 mA

Vss + 0.6

Vss + 0.8

Vss + 5.5

V

V^OL2P74, P75

IOL = 15.0 mA

0.5

Open-drain pin

Open-drain output

application voltage

VD1

P74, P75

Vss − 0.3

− 10

25

All output

VCC = 3.3 V,

VSS < VI < VCC

Input leak current

Pull-up resistor

I^IL

10

100

10

µA

kΩ

µA

Vcc = 3.3 V,

TA = + 25 °C

R^UPRST

50

Vcc = 3.3 V,

TA = + 25 °C

Except FLASH

products

Pull-down resistor R^DOWNMD2

Open drain output

25

I^leak

P74, P75

0.1

current

The DC Characteristics is based on V^SS= AVSS = 0.0 V.

(Continued)

70

MB90800 Series

(V^CC= AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Typ Max

VCC = 3.3 V,

Internal frequency 25 MHz

At normal operating

48

60

75

mA

V^CC= 3.3 V,

Internal frequency 25 MHz

At Flash writing

FLASH

products

I^CC

V^CC= 3.3 V,

Internal frequency 25 MHz

At Flash erasing

FLASH

products

VCC = 3.3 V,

Internal frequency 25 MHz

at sleep mode

I^CCS

22.5 30

VCC = 3.3 V,

Internal frequency 3 MHz

at timer mode

I^CCTS

0.75

7

Power

supply

current

VCC

MASK

products

VCC = 3.3 V,

Internal frequency 8 kHz

at subclock operation,

(TA = + 25 °C)

15

140 µA

I^CCL

FLASH

products

0.5

0.9 mA

VCC = 3.3 V,

Internal frequency 8 kHz

at subclock sleep operation,

(T^A= + 25 °C)

I^CCLS

23

40

µA

VCC = 3.3 V,

Internal frequency 8 kHz

at watch mode

I^CCT

1.8

0.8

40

µA

(TA = + 25 °C)

At Stop mode,

(TA = + 25 °C)

I^CCH

VCC − V3

At LCR = 0 setting

At LCR = 1 setting

100

200 400

25 50

V^CC− V3

12.5

V0 − V1,

V1 − V2,

V2 − V3

LCD division

resistance

At LCR = 0 setting

At LCR = 1 setting

50

100 200

R^LCD

kΩ

*

V0 − V1,

V1 − V2,

V2 − V3

6.25 12.5 25

COM0 to COM3

output impedance

COM0 to

COM3

R^VCOM

2.5

15

kΩ

V1 to V3 = 3.3 V

SEG00 to SEG47

output impedance

SEG00 to

SEG47

R^VSEG

The DC Characteristics is based on V^SS= AVSS = 0.0 V.

(Continued)

71

MB90800 Series

(Continued)

(VCC = AVCC = 3.3 V ± 0.3 V, TA = − 40 to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

V0 to V3,

Conditions

Unit Remarks

Min

Typ

Max

LCD leak current I^LCDCCOM0 to COM3,

SEG00 to SEG47

− 5

5

µA

The DC Characteristics is based on V^SS= AVSS = 0.0 V.

* : LCD internal diveded resistor can be select two type resistor by LCR (internal diveded resistor selecting bit) of

LCRR (LCDC range register) .

72

MB90800 Series

4. AC Characteristics

(1) Clock timing

(V^CC= AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Sym

bol

Condi-

tions

Parameter

Pin name

Unit

Remarks

Min

Typ

Max

External crystal

oscillation

f^CH

X0, X1

3

16

MHz

3

4.5

4

25

At external clock*

Multiply by 1

Clock frequency

f^CH

X0, X1

12.5 MHz Multiply by 2

4

8.33

6.25

Multiply by 3

Multiply by 4

4

f^CLX0A, X1A

X0, X1

32.768

30.5

kHz

ns

tHCYL

40

5

333

Clock cycle time

t^LCYLX0A, X1A

µs

P^WH

X0

ns Set Duty ratio 50% ± 3%

PWL

Input clock pulse width

P^WLH

X0A

PWLL

Set duty ratio at 30% to

µs

15.2

70% as a guideline.

Input clock rise time and

fall time

tcr

X0

tcf

5

ns At external clock

When main clock is

f^CP

f^CP1

t^CP

1.5

40

25

MHz

used

Internal operating clock

frequency

8.192

122.1

kHz When sub clock is used

When main clock is

used

666

ns

Internal operating clock

cycle time

t^CP1

µs When sub clock is used

The Clock timing is based on V^SS= AVSS = 0.0 V.

* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned

in “Base oscillator frequency vs. Internal operating clock frequency”.

• X0, X1 clock timing

tC

0.8 VCC

0.2 VCC

PWH

PWL

tcr

tcf

• X0A, X1A clock timing

tCL

0.8 VCC

0.2 VCC

PWLH

PWLL

tcr

tcf

73

MB90800 Series

PLL operation guarantee range

Relation between internal operation clock frequency and power supply voltage

PLL operation guarantee range

3.6

3.0

2.7

Normal operation

assurance range

1.5

4.5

16

25

Internal clock f^CP(MHz)

Relation between oscillation frequency and internal operating clock frequency

Multiply by 1

Multiply by 4 Multiply by 3

Multiply by 2

25

16

12

8

6

External clock

4.5

4

3

4.5

6

8

12

16

25

4

Original oscillation clock fCH (MHz)

Rating values of alternating current is defined by the measurement reference voltage values shown below :

• Input signal waveform

• Output signal waveform

Hysteresis input pin

Output pin

0.8 VCC

2.4 V

0.2 VCC

0.8 V

74

MB90800 Series

(2) Reset input timing

(V^CC= AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Min

Sym-

bol

Condi-

tions

Parameter

Pin name

Unit

Remarks

Max

At normal operating,

at time base timer mode,

at main leep mode,

at PLL sleep mode

500

ns

Reset input time

t^RSTL

RST

At stop mode,

Oscillation time

of oscillator*+

500 ns

at sub clock mode,

at sub sleep mode,

at watch mode

µs

The Reset input timing is based on V^SS= AVSS = 0.0 V.

* : Oscillation time of oscillator is time until oscillation reaches 90% of amplitude. It takes several milliseconds to

several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds

on a FAR/ceramic oscillator, and 0 milliseconds on an external clock.

• In normal operating, time base timer mode, main sleep mode and PLL sleep mode

t

RSTL

RST

0.2 VCC

• In stop mode, sub clock mode, sub sleep mode and watch mode

t

RSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operating

clock

Oscillationtime

of oscillator

500 ns

Wait time for stabilization oscillator

Execute instruction

Internal reset

75

MB90800 Series

(3) Power-on reset

(V^CC= AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

Power supply rising time

t^R

VCC

30

ms At normal operating

Power supply shutdown

time

t^OFF

1

ms For repeated operation

The Power-on reset is based on V^SS= AVSS = 0.0 V.

Notes : • V^CCshould be set under 0.2 V before power-on rising up.

• These value are for power-on reset.

• In the device, there are internal registers which is initialized only by a power-on reset. If these initialization

is executing, power-on prosedure must be obeyed by these value.

tR

2.7 V

0.2 V

VCC

0.2 V

tOFF

Sudden change of power supply voltage may activate the power-on reset function. When changing

power supply voltages during operation, raise the power smoothly by suppressing variation of

voltages as shown below. When raising the power, do not use PLL clock. However, if voltage drop is

1mV/s or less, use of PLL clock is allowed during operation.

VCC

Limiting the slope of rising within

50 mV/ms is recommended.

2.7 ± 0.3 V

RAM data hold

VSS

76

MB90800 Series

(4) Serial I/O

(V^CC= AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Sym

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Max

Serial clock cycle time

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SCYCSC0 to SC3

8 t^CP

ns

SC0 to SC3

t^SLOV

−80

100

60

80

Internal shift clock

mode output pin :

C^L= 80 pF + 1TTL

SO0 to SO3

t^IVSH

SC0 to SC3

SCK ↑ → Valid

SIN hold time

SI0 to SI3

t^SHIX

Serial clock H pulse width

Serial clock L pulse width

t^SHSL

4 t^CP

ns

SC0 to SC3

t^SLSH

4 tCP

SC0 to SC3 External shift clock

SO0 to SO3 mode output pin :

C^L= 80 pF + 1TTL

SC0 to SC3

SI0 to SI3

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

150

ns

60

SCK ↑ → valid

SIN hold time

The Serial I/O is based on V^SS= AVSS = 0.0 V.

Notes : • AC rating in CLK synchronous mode.

• C L is a load capacitance value on pins for testing.

• tCP is machine cycle frequency (ns) .

• Internal shift clock mode

tSCYC

SC

2.4 V

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SI

• External shift clock mode

tSLSH

tSHSL

SC

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

77

MB90800 Series

(5) Timer input timing

(V^CC= AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

Max

t^TIWH

tTIWL

TIN0 to TIN2

IC0 to IC1

Input pulse width

4 tCP

ns

The Timer input timing is based on V^SS= AVSS = 0.0 V.

• Timer Input Timing

0.8 VCC

TINx

ICx

0.2 VCC

tTIWH

tTIWL

(6) Timer output timing

Parameter

(V^CC= AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Sym-

bol

Condi-

tions

Pin name

Unit

Remarks

Min

Max

TOT0 to TOT2,

PPG0 to PPG1,

OCU0 to OCU1

CLK ↑ → T^OUTchange time

tTO

30

ns

The Timer output timing is based on V^SS= AVSS = 0.0 V.

• Timer Output Timing

2.4 V

CLK

tTO

TOTx

PPGx

OCUx

2.4 V

0.8 V

(7) Trigger Input Timing

(V^CC= AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Condi-

tions

Parameter

Symbol

Pin name

Unit

Remarks

Min

5 t^CP

1

Max

ns

At normal operating

In Stop mode

t^TRGH

tTRGL

Input pulse width

INT0 to INT3

µs

The Trigger Input Timing is based on V^SS= AVSS = 0.0 V.

• Trigger Input Timing

0.8 VCC

0.2 VCC

INTx

0.2 VCC

tTRGH

tTRGL

78

MB90800 Series

(8) I²C Timing

(AV^CC= VCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Standard-

mode

Parameter

Symbol

Conditions

Unit

Min Max

SCL clock frequency

f^SCL

0

100 kHz

Hold time (repeated) START condition

SDA ↓ → SCL ↓

t^HDSTA

4.0

µs

When power supply voltage of external

pull-up resistor is 5.0 V

“L” width of the SCL clock

“H” width of the SCL clock

tLOW

tHIGH

4.7

4.0

µs

R = 1.0 kΩ, C = 50 pF*²

When power supply voltage of external

pull-up resistor is 3.6 V

Set-up time for a repeated START condition

SCL ↑ → SDA ↓

t^SUSTA

4.7

0

µs

R = 1.0 kΩ, C = 50 pF*²

Data hold time

SCL ↓ → SDA ↓ ↑

3.45

*

tHDDAT

µs

3

When power supply voltage of external

pull-up resistor is 5.0 V

fCP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

When power supply voltage of external

pull-up resistor is 3.6 V

250

200

ns

fCP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

Data set-up time

SDA ↓ ↑ → SCL ↑

t^SUDAT

When power supply voltage of external

pull-up resistor is 5.0 V

f^CP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

When power supply voltage of external

pull-up resistor is 3.6 V

fCP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

Set-up time for STOP condition

SCL ↑ → SDA ↑

When power supply voltage of external

pull-up resistor is 5.0 V

t^SUSTO

4.0

4.7

µs

R = 1.0 kΩ, C = 50 pF*²

When power supply voltage of external

pull-up resistor is 3.6 V

Bus free time between a STOP and START

condition

t^BUS

R = 1.0 kΩ, C = 50 pF*²

The I²C trriger is based on AVSS = VSS = 0.0 V.

*1 : fCP is internal operation clock frequency. Refer to “ (1) Clock timing”.

*2 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*3 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

SDA

tBUS

tSUDAT

tHDSTA

t^LOW

SCL

tHIGH

tHDSTA

tHDDAT

tSUSTA

tSUSTO

79

MB90800 Series

5. Electrical Characteristics for the A/D Converter

Sym-

(VCC = AVCC = 3.3 V ± 0.3 V, Ta = − 40 to + 85 °C)

Value

Parameter

Pin name

Unit

Remarks

bol

Min

Typ

Max

10

Resolution

bit

Total error

± 3.0

± 2.5

± 1.9

LSB

Nonlinear error

Differential linear error

AVSS − 1.5 AVss + 0.5 AVSS + 2.5

Zero transition voltage

V^OT

AN0 to AN11

mV

LSB

1 LSB = AVcc/1024

Full-scale transition

voltage

AVcc − 3.5 AVcc − 1.5 AVcc + 0.5

V^FST

LSB

8.64*¹

2

LSB

Conversion time

µs

Sampling time

Analog port input current

Analog input voltage

Reference voltage

I^AIN

AN0 to AN11

AVcc

10

AVcc

3.5

µA

V

V^AIN

0

3.0

V

I^A

I^AH

I^R

AVcc

1.4

94

mA

µA

LSB

Power supply current

AVcc

5*²

AVcc

150

5*²

Reference voltage

supplying current

I^RH

AVcc

Interchannel disparity

AN0 to AN11

4

The Electrical characteristics for the A/D converter is based on V^SS= AVSS = 0.0 V.

*1 : At operating, main clock 25 MHz.

*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (at Vcc − CPU = AVcc = 3.3 V)

80

MB90800 Series

• A/D converter with sample and hold circuit. If the extrernal impedance is too high to keep sufficient sampling

time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

Analog input circuit model

R

Comparator

Analog input

C

During sampling : ON

R

C

MB90803

1.9 kΩ (Max) 32.3 pF (Max)

1.9 kΩ (Max) 25.0 pF (Max)

1.9 kΩ (Max) 32.3 pF (Max)

MB90F804

MB90V800

Note : The values are reference values.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

[External impedance = 0 kΩ to 100 kΩ]

[External impedance = 0 kΩ to 20 kΩ]

MB90803/

MB90F804

MB90V800

MB90F804

MB90V800

20

18

16

14

12

10

8

100

90

80

70

60

50

40

30

20

10

0

6

4

2

0

1

2

3

4

5

6

7

8

0

5

10

15

20

25

30

35

→ Minimum sampling time [µs]

The relationship between external impedance and minimum sampling time

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

•

As | AV^CC| becomes smaller, values of relative errors grow larger.

81

MB90800 Series

6. Definition of A/D Converter Terms

Resolution

Analog variation that is recognized by an A/D converter.

The 10-bit can resolve analog voltage into 2¹⁰= 1024.

Total error

This shows the difference between the actual voltage and the ideal value and means a total of error because of

offset error, gain error, non-linearity error and noise.

Linearity error

Deviation between a line across zero-transition line (00 0000 0000↔00 0000 0001) and full-scale transition line

(11 1111 1110↔11 1111 1111) and actual conversion characteristics.

Differential linear error

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Total error

3FF

0.5 LSB

3FE

Actual conversion

characteristic

3FD

{1 LSB × (N − 1) + 0.5 LSB}

004

V^NT

003

002

001

(measurement value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVCC

(AVRL)

Analog input

(AVRH)

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

Total error of digital output N =

[LSB]

1 LSB

AVCC − AVSS

1LSB(Ideal value) =

[V]

1024

VOT(Ideal value) = AVSS + 0.5 LSB [V]

V^FST(Ideal value) = AVCC − 1.5 LSB [V]

VNT: A voltage at which digital output transitions from (N-1) to N.

(Continued)

82

MB90800 Series

(Continued)

Linearity error

Differential linear error

Actual conversion characteristic

Ideal characteristics

3FF

3FE

3FD

Actual conversion

characteristics

N + 1

{1 LSB (N 1) V^OT}

V^FST

(measurement value)

N

VNT

(measurement value)

004

003

002

001

V^(N1)T

Actual conversion

characteristics

(measurement value)

N − 1

N − 2

VNT

(measurement value)

Ideal characteristics

V^OT(actual measurement value)

Actual conversion

characteristics

AVCC

(AVRH)

AVSS

(AVRL)

AVCC

(AVRH)

AVSS

(AVRL)

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

Linear error in digital output N =

[LSB]

1 LSB

V^{(N + 1) T}− VNT}

− 1LSB

Differential linear error in digital output N =

1 LSB =

1 LSB

V^FST− VOT

[V]

1022

V^OT: Voltage at which digital output transits from 000H to 001H.

VFST : Voltage at which digital output transits from 3FEH to 3FFH.

83

MB90800 Series

7. FLASH MEMORY

Value

Typ

Parameter

Conditions

Unit

Remarks

Min

Max

Excludes 00 H programming

prior to erasure.

Sector erase time

Chip erase time

1

9

15

s

T^A= + 25 °C

Vcc = 3.0 V

Excludes 00 H programming

prior to erasure.

µs

Word (16 bit width)

programming time

Except for the over head time

of the system.

16

3,600

s

Program/erase cycle

10,000

20

cycle

Flash data retension

time

Average

T^A= + 85 °C

Yearss *

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measuremunts into normalized value at + 85 °C).

84

MB90800 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F804-101PF-G

MB90F804-201PF-G

100-pin plastic QFP

(FPT-100P-M06)

MB90803PF

MB90803SPF

85

MB90800 Series

■ PACKAGE DIMENSION

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

100-pin plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

*

20.00±0.20(.787±.008)

80

51

81

50

0.10(.004)

17.90±0.40

(.705±.016)

*

14.00±0.20

(.551±.008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8

˚

1

30

0.65(.026)

0.32±0.05

(.013±.002)

0.17±0.06

(.007±.002)

M

0.13(.005)

0.25±0.20

(.010±.008)

(Stand off)

0.80±0.20

(.031±.008)

"A"

0.88±0.15

(.035±.006)

C

2002 FUJITSU LIMITED F100008S-c-5-5

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

86

MB90800 Series

MEMO

87

MB90800 Series

FUJITSU LIMITED

For further information please contact:

Japan

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

FUJITSU LIMITED

Marketing Division

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94088-3470, U.S.A.

Tel: +1-408-737-5600

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Tel: +65-6281-0770

Fax: +65-6281-0220

http://www.fmal.fujitsu.com/

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

Preliminary 2004.07.22

FUJITSU LIMITED Printed in Japan


型号：	MB90803PF
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller CMOS 16位微控制器的专有CMOS 微控制器和处理器外围集成电路时钟
文件：	总88页 (文件大小：816K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90803PF [FUJITSU]

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