MB90867E [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB90867E |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总67页 (文件大小：973K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13748-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90860E Series
MB90867E(S), MB90F867E(S),
MB90V340E-101/102
■ DESCRIPTION
MB90860E-series with Flash ROM is especially designed for automotive and other industrial applications. With
the new 0.35 µm CMOS technology, Fujitsu now offers on-chip Flash ROM program memory up to 512 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB90860E Series
■ FEATURES
• CPU
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes(23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Serial interface
• UART (LIN/SCI) : up to 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface* : up to 2 channels
• Up to 400 Kbits/s transfer rate
• Interrupt controller
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• Automatic data transfer function independent of CPU
• Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
• 8/10-bit A/D converter
• 8/10-bit A/D converter : 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 16 channels, or 16-bit × 8 channels
• 16-bit reload timer : 4 channels
• 16-bit input/output timer
- 16-bit free run timer : 2 channel
(FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16-bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
2
MB90860E Series
• Variety of mode
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (time-base timer mode that is transferred from main clock mode)
• PLL timer mode (time-base timer mode that is transferred from PLL clock mode)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Technology
• 0.35 µm CMOS technology
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-
ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
3
MB90860E Series
■ PRODUCT LINEUP
Part Number
MB90867E(S)
MB90F867E(S)
MB90V340E-101/102
Parameter
CPU
F2MC-16LX CPU
Type
MASK ROM product
Flash memory product
Evaluation product
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
System clock
MASK ROM
128 Kbytes
Flash memory
128 Kbytes
ROM
RAM
External
30 Kbytes
Yes
6 Kbytes
6 Kbytes
Emulator-specific
power supply*1
⎯
0.35 µm CMOS with on-chip
0.35 µm CMOS with on-chip voltage regulator for internal 0.35 µm CMOS with on-chip
voltage regulator for internal power supply + Flash memory voltage regulator for internal
Technology
power supply
with on-chip charge pump for power supply
programming voltage
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
Operating
voltage range
5 V 10%
Temperature range
Package
−40 °C to +105 °C
QFP-100, LQFP-100
⎯
PGA-299
5 channels
4 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 kbps)
2 channels
24 channels
8/10-bit
A/D converter
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit reload timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (ch.0, ch.4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit
I/O timer
(2 channels)
16-bit output
compare
(8 channels)
Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.
16-bit input capture Rising edge, falling edge or rising & falling edge sensitive
(8 channels) Signals an interrupt upon external event
(Continued)
4
MB90860E Series
(Continued)
Part Number
MB90867E(S)
MB90F867E(S)
MB90V340E-101/102
Parameter
Supports 8-bit and 16-bit operation modes
Sixteen 8-bit reload counters
8/16-bit
Sixteen 8-bit reload registers for L pulse width
programmable pulse Sixteen 8-bit reload registers for H pulse width
generator
(8 channels)
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
CAN interface
⎯
3 channels
External interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A converter
⎯
2 channels
Up to 100 kHz
sub clock for low
power operation
Only for MB90V340E-
102
Devices without ‘S’-suffix
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
I/O ports
Bit-wise settable as input/output or peripheral signal
Settable in pin-wise of 8 as CMOS schmitt trigger/automotive inputs (default)
TTL input level settable for external bus (32-pin only for external bus)
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Flash memory
Data retention time : 20 years
Boot block configuration
⎯
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90860E Series
■ PIN ASSIGNMENTS
• MB90V340E-101/102
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
P14/AD12/SCK3
Vcc
Vss
QFP - 100
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRL
AVRH
AVcc
P57/AN15/DA01
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
(Continued)
6
MB90860E Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
MD1
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
LQFP - 100
Vss
X1
X0
P15/AD13/SIN4
P16/AD14/SOT4
P17/AD15/SCK4
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
AVRL
AVRH
AVcc
P57/AN15/DA01
P56/AN14/DA00
P55/AN13
P54/AN12/TOT3
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M05)
* : X0A, X1A : MB90V340E-102
P40, P41 : MB90V340E-101
7
MB90860E Series
• MB90867E(S)/MB90F867E(S)
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
QFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVss
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRH
AVcc
P57/AN15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : X0A, X1A : MB90867E, MB90F867E
P40, P41 : MB90867ES/MB90F867ES
(Continued)
8
MB90860E Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD1
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
LQFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M05)
* : X0A, X1A : MB90867E, MB90F867E
P40, P41 : MB90867ES, MB90F867ES
9
MB90860E Series
■ PIN DESCRIPTION
Pin No.
I/O
Pin name Circuit
Function
QFP100*1 LQFP100*2
type*3
General purpose I/O pins. The register can be set to select
whether to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding bit
in the external address output control register (HACR) is 1.
P24 to P27
1 to 4
99 to 2
G
Output pins of the external address bus. When the corresponding
bit in the external address output control register (HACR) is 0, the
pins are enabled as high address output pins (A20 to A23).
A20 to A23
IN0 to IN3
P30
Trigger input pins for input captures 0 to 3.
General purpose I/O pin.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
5
6
3
4
G
Address latch enable output pin. This function is enabled when
the external bus is enabled.
ALE
IN4
Trigger input pin for input capture 4.
General purpose I/O pin.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
P31
G
External read strobe output pin. This function is enabled when the
external bus is enabled.
RD
IN5
Trigger input pin for input capture 5.
General purpose I/O pin. The register can be set to select whether
to use a pull-up resistor. This function is enabled either in single-
chip mode or with the WR/WRL pin output disabled.
P32
Write strobe output pin for the external data bus. This function is
enabled when both the external bus and the WR/WRL pin output
are enabled. WRL is used to write-strobe 8 lower bits of the data
bus in 16-bit access while WR is used to write-strobe 8 bits of the
data bus in 8-bit access.
7
5
G
WR / WRL
INT10R
P33
External interrupt request input pin (sub) .
General purpose I/O pin. The register can be set to select whether
to use a pull-up resistor.This function is enabled either in single-
chip mode or with the WRH pin output disabled.
8
6
G
Write strobe output pin for the 8 higher bits of the external data
bus. This function is enabled when the external bus is enabled,
when the external bus 16-bit mode is selected, and when the
WRH output pin is enabled.
WRH
(Continued)
10
MB90860E Series
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1 LQFP100*2
type*3
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the hold function disabled.
P34
9
7
8
9
G
G
G
G
Hold request input pin. This function is enabled when both the
external bus and the hold function are enabled.
HRQ
OUT4
Waveform output pin for output compare 4.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the hold function disabled.
P35
10
11
Hold acknowledge output pin. This function is enabled when
both the external bus and the hold function are enabled.
HAK
OUT5
Waveform output pin for output compare 5.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the external ready function disabled.
P36
External ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
RDY
OUT6
Waveform output pin for output compare 6.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the clock output disabled.
P37
12
10
Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
CLK
OUT7
Waveform output pin for output compare 7.
General purpose I/O pins.
(devices with S-suffix)
P40, P41
F
B
13, 14
11, 12
Input pins for sub-clock
(devices without S-suffix)
X0A , X1A
15
16
13
14
VCC
VSS
⎯
⎯
Power (3.5 V to 5.5 V) input pin
GND pin
This is the power supply stabilization capacitor pin. It should be
connected to a higher than or equal to 0.1 µF ceramic
capacitor.
17
18
15
16
C
K
P42
IN6
General purpose I/O pin.
F
Trigger input pin for input capture 6.
External interrupt request input pin (sub)
(Continued)
INT9R
11
MB90860E Series
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1 LQFP100*2
type*3
P43
General purpose I/O pin.
19
20
17
18
F
IN7
P44
Trigger input pin for input capture 7.
General purpose I/O pin.
Serial data I/O pin for I2C 0
SDA0
FRCK0
P45
H
Input pin for the 16-bit I/O Timer 0
General purpose I/O pin.
21
19
SCL0
FRCK1
P46
H
Serial clock I/O pin for I2C 0
Input pin for the 16-bit I/O Timer
General purpose I/O pin.
Serial data I/O pin for I2C 1
22
23
20
21
H
H
SDA1
P47
General purpose I/O pin.
Serial clock I/O pin for I2C 1
SCL1
P50
General purpose I/O pin.
24
25
26
27
22
23
24
25
AN8
O
I
Analog input pin for the A/D converter
Serial data input pin for UART2
General purpose I/O pin.
SIN2
P51
AN9
Analog input pin for the A/D converter
Serial data output pin for UART2
General purpose I/O pin.
SOT2
P52
AN10
SCK2
P53
I
Analog input pin for the A/D converter
Clock I/O pin for UART2
General purpose I/O pin.
AN11
TIN3
I
Analog input pin for the A/D converter
Event input pin for the reload timer 3
General purpose I/O pin.
P54
28
29
26
27
AN12
TOT3
P55
I
I
Analog input pin for the A/D converter
Output pin for the reload timer 3
General purpose I/O pin.
AN13
P56, P57
AN14, AN15
AVCC
Analog input pin for the A/D converter
General purpose I/O pins.
30, 31
32
28, 29
30
J
Analog input pin for the A/D converter
Power input pin for the A/D Converter analog
K
(Continued)
12
MB90860E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
Reference voltage input pin for the A/D Converter. This power
supply must be turned on or off while a voltage higher than or
equal to AVRH is applied to AVCC.
33
31
AVRH
L
34
35
32
33
AVRL
AVSS
K
K
Lower reference voltage input pin for the A/D Converter
GND pin for the A/D Converter analog
General purpose I/O pins.
P60 to P67
AN0 to AN7
Analog input pins for the A/D converter
36 to 43
34 to 41
42
I
PPG0, 2, 4, 6,
8, A, C, E
Output pins for PPGs
44
VSS
⎯
GND pin
P70 to P75
General purpose I/O pins.
45 to 50
43 to 48 AN16 to AN21
INT0 to INT5
I
Analog input pins for the A/D converter
External interrupt request input pins
Input pin for specifying the operating mode.
Input pins for specifying the operating mode.
Reset input
51
52, 53
54
49
50, 51
52
MD2
MD1, MD0
RST
D
C
E
P76, P77
AN22, AN23
INT6, INT7
P80
General purpose I/O pins.
55, 56
53, 54
I
Analog input pins for the A/D converter
External interrupt request input pins
General purpose I/O pin.
TIN0
Event input pin for the reload timer 0
Trigger input pin for the A/D converter
External interrupt request input pin (sub)
General purpose I/O pin.
57
55
F
ADTG
INT12R
P81
TOT0
Output pin for the reload timer 0
Output pin for the clock monitor
External interrupt request input pin (sub)
General purpose I/O pin.
58
59
56
57
F
CKOT
INT13R
P82
SIN0
Serial data input pin for UART0
Event input pin for the reload timer 2
External interrupt request input pin (sub)
General purpose I/O pin.
M
TIN2
INT14R
P83
60
61
58
59
SOT0
F
F
Serial data output pin for UART0
Output pin for the reload timer 2
General purpose I/O pin.
TOT2
P84
SCK0
Clock I/O pin for UART0
INT15R
External interrupt request input pin (sub)
(Continued)
13
MB90860E Series
Pin No.
I/O
Pin name
Circuit
Function
QFP100*1 LQFP100*2
type*3
P85
General purpose I/O pin.
62
63
64
60
61
62
M
F
SIN1
P86
Serial data input pin for UART1
General purpose I/O pin.
Serial data output pin for UART1
General purpose I/O pin.
Clock I/O pin for UART1
Power (3.5 V to 5.5 V) input pins
GND pins
SOT1
P87
F
SCK1
65
66
63
64
VCC
⎯
⎯
VSS
P90 to P93
PPG1, 3, 5, 7
P94 to P97
General purpose I/O pin
Output pins for PPGs
67 to 70
65 to 68
F
General purpose I/O pin
71 to 74
69 to 72
F
OUT0 to
OUT3
Waveform output pins for output compares 0 to 3. This function
is enabled when the OCU enables waveform output.
PA0
INT8R
PA1
General purpose I/O pin.
75
76
73
74
F
F
External interrupt request input pin (sub)
General purpose I/O pin.
General purpose I/O pins. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
P00 to P07
77 to 84
75 to 82
G
G
G
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
AD00 to AD07
INT8 to INT15
External interrupt request input pins.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
P10
85
83
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD08
TIN1
Event input pin for the reload timer 1
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
P11
86
84
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD09
TOT1
Output pin for the reload timer 1
(Continued)
14
MB90860E Series
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1 LQFP100*2
type*3
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
P12
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
87
85
N
AD10
SIN3
Serial data input pin for UART3
INT11R
External interrupt request input pin (sub)
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
P13
88
89
86
87
G
G
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD11
SOT3
Serial data output pin for UART3
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
P14
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD12
SCK3
VCC
VSS
X1
Clock I/O pin for UART3
Power (3.5 V to 5.5 V) input pin
GND pin
90
91
92
93
88
89
90
91
⎯
⎯
Main clock output pin
Main clock input pin
A
X0
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
P15
AD13
P16
94
95
96
92
93
94
G
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
G
G
I/O pin for the external address/data bus.
This function is enabled when the external bus is enabled.
AD14
P17
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled in
single-chip mode.
I/O pin for the external address/data bus. This function is
enabled when the external bus is enabled.
AD15
(Continued)
15
MB90860E Series
(Continued)
Pin No.
I/O
Circuit
Pin name
Function
QFP100*1 LQFP100*2
type*3
General purpose I/O pins. The register can be set to select
whether to use a pull-up resistor.In external bus mode, the pin
is enabled as a general-purpose I/O port when the
corresponding bit in the external address output control
register (HACR) is 1.
P20 to P23
97 to 100
95 to 98
G
Output pins of the external address bus. When the
corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A16 to A19).
A16 to A19
PPG9,PPGB,
PPGD,PPGF
Output pins for PPGs
*1 : FPT-100P-M06
*2 : FPT-100P-M05
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
16
MB90860E Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 MΩ
X1
Xout
A
X0
Standby control signal
• Oscillation circuit
X1A
Low-speed oscillation feedback
resistor = approx. 10 MΩ
Xout
B
X0A
Standby control signal
• Mask ROM and evaluation device:
CMOS Hysteresis input pin
• Flash device:
R
Hysteresis
C
D
inputs
CMOS input pin
• Mask ROM and evaluation device:
CMOS Hysteresis input pin
Pull-down resistor value: approx. 50 kΩ
• Flash memory device:
CMOS input pin
R
Hysteresis
inputs
Pull-down
Resistor
No Pull-down
CMOS Hysteresis input pin
Pull-up resistor value: approx. 50 kΩ
Pull-up
E
Resistor
R
Hysteresis
inputs
(Continued)
17
MB90860E Series
Type
Circuit
Remarks
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
Nout
R
F
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
Pull-up control
Pout
P-ch
P-ch
• TTL input (With the standby-time input
shutdown function)
N-ch
Nout
• Programmable pull-up resistor: 50 kΩ
approx.
R
G
Hysteresis inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• CMOS level output (IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
Nout
H
R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
18
MB90860E Series
Type
Circuit
Remarks
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time in-
put shutdown function)
P-ch
N-ch
Pout
Nout
• A/D converter analog input
R
I
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• D/A analog output
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time in-
put shutdown function)
P-ch
N-ch
Pout
Nout
R
• A/D converter analog input
Hysteresis inputs
J
Automotive inputs
Standby control for
input shutdown
Analog input
Analog output
Power supply input protection circuit
P-ch
N-ch
K
• A/D converter reference voltage power
supply input pin, with the protection circuit
• Flash devices do not have a protection
circuit against VCC for pin AVRH
ANE
AVR
P-ch
L
N-ch
ANE
(Continued)
19
MB90860E Series
(Continued)
Type
Circuit
Remarks
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
Nout
M
R
CMOS inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output (IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
Pull-up control
P-ch
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
P-ch
Pout
Nout
N-ch
Programmable pull-up registor:50 kΩ
approx
R
N
CMOS inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
Nout
• A/D converter analog input
R
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
20
MB90860E Series
■ HANDLING DEVICES
1. Preventing latch-up
CMOS IC may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90860E
Series
Vcc
Vss
Vcc
Vss
4. Mode Pin (MD0 to MD2)
Connect the mode pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection.
21
MB90860E Series
5. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable) .
6. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
7. Crystal Oscillator Circuit
X0, X1 pins and X0A, X1A pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic oscillator)
and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other
circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
8. Pull-up/down resistors
The MB90860E Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
9. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90860E Series
X0
Open
X1
10. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
11. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the MB90860 series attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
12. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V)
22
MB90860E Series
13. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For the reference, stabilize the supply voltage by setting the following value.
• VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the
standard VCC supply voltage
• The coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
14. Initialization
Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,
turn on the power again.
15. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, in spite of reset input, there is a possibility that
output signal of Port 0 to Port 3 might be unstable.
1/2VCC
VCC
Port 0 to Port 3
Port 0 to Port 3 outputs = Hi-Z
Port 0 to Port 3 outputs
might be unstable
16. Flash security Function
The security bit is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
Flash memory size
Address for security bit
MB90F867E(S)
Embedded 1 Mbit Flash Memory
FE0001H
23
MB90860E Series
■ BLOCK DIAGRAMS
• MB90V340E-101/102
X0,X1
X0A,X1A*
RST
Clock
16LX
CPU
Controller
FRCK0
RAM
I/O Timer 0
30 Kbytes
Input
Capture
IN7 to IN0
8 channels
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
5 channels
I/O Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 channels
UART
5 channels
RX2 to RX0
TX2 to TX0
16-bit Reload
Timer
4 channels
AVCC
TIN3 to TIN0
AVSS
AN23 to AN0
AVRH
TOT3 to TOT0
8/10-bit
ADC
24 channels
AD15 to AD00
A23 to A16
ALE
AVRL
ADTG
RD
10-bit
DAC
2 channels
External
Bus
Interface
WR/WRL
WRH
DA01, DA00
HRQ
HAK
8/16-bit
PPG
16 channels
PPGF to PPG0
RDY
CLK
I2C
Interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
External
Interrupt
16 channels
INT7 to INT0
DMAC
Clock
CKOT
Monitor
* : Only for MB90V340E-102
24
MB90860E Series
• MB90867E(S), MB90F867E(S)
X0,X1
Clock
16LX
CPU
X0A,X1A*
Controller
RST
FRCK0
RAM
I/O Timer 0
6 Kbytes
Input
Capture
8 channels
IN7 to IN0
OUT7 to OUT0
FRCK1
ROM/Flash
128 Kbytes
Output
Compare
8 channels
Prescaler
4 channels
I/O Timer 1
SOT3 to SOT0
UART
SCK3 to SCK0
4 channels
SIN3 to SIN0
AVCC
AVSS
AN15 to AN0
AN23 to AN16
AVRH
16-bit Reload
Timer
4 channels
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
ADC
24 channels
AD15 to AD00
A23 to A16
ALE
AVRL
ADTG
RD
External
Bus
Interface
WR/WRL
WRH
8/16-bit
PPG
16 channels
HRQ
PPGF to PPG0
HAK
RDY
CLK
I2C
Interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
External
Interrupt
16 channels
INT7 to INT0
DMAC
Clock
Monitor
CKOT
* : Only for devices without ‘S’ Suffix
25
MB90860E Series
■ MEMORY MAP
MB90867E(S)
MB90F867E(S)
MB90V340E-101/102
000000
0000EF
H
H
000000
0000EF
H
H
Peripheral
Peripheral
External access area
External access area
000100
H
000100
H
RAM 6 Kbytes
003FFF
H
RAM 30 Kbytes
0078FF
H
007900
H
007900
H
Peripheral
Peripheral
007FFF
H
007FFF
H
008000
H
008000
H
ROM
(image of FF bank)
ROM (image
of FF bank)
00FFFF
H
00FFFFH
External access area
ROM (F8 bank)
F80000
H
F8FFFF
H
F90000
H
ROM (F9 bank)
ROM (FA bank)
ROM (FB bank)
ROM (FC bank)
ROM (FD bank)
ROM (FE bank)
ROM (FF bank)
F9FFFF
H
H
FA0000
FAFFFF
FB0000
H
H
External
access area
FBFFFF
FC0000
H
H
FCFFFF
H
H
FD0000
FDFFFF
FE0000
H
H
FE0000
H
ROM (FE bank)
ROM (FF bank)
FEFFFF
FF0000
H
H
FEFFFF
FF0000
H
H
FFFFFF
H
FFFFFF
H
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
26
MB90860E Series
■ I/O MAP
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
000000H Port 0 Data Register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
ADER5
ADER6
ADER7
ILSR0
ILSR1
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
11111111B
11111111B
XXXXXXXXB
XXXX0XXXB
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000100B
000001H Port 1 Data Register
000002H Port 2 Data Register
Port 2
000003H Port 3 Data Register
Port 3
000004H Port 4 Data Register
Port 4
000005H Port 5 Data Register
Port 5
000006H Port 6 Data Register
Port 6
000007H Port 7 Data Register
Port 7
000008H Port 8 Data Register
Port 8
000009H Port 9 Data Register
Port 9
00000AH Port A Data Register
Port A
Port 5, A/D
Port 6, A/D
Port 7, A/D
Ports
00000BH Port 5 Analog Input Enable Register
00000CH Port 6 Analog Input Enable Register
00000DH Port 7 Analog Input Enable Register
00000EH Input Level Select Register 0
00000FH Input Level Select Register 1
000010H Port 0 Direction Register
000011H Port 1 Direction Register
000012H Port 2 Direction Register
000013H Port 3 Direction Register
000014H Port 4 Direction Register
000015H Port 5 Direction Register
000016H Port 6 Direction Register
000017H Port 7 Direction Register
000018H Port 8 Direction Register
000019H Port 9 Direction Register
00001AH Port A Direction Register
00001BH
Ports
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Reserved
00001CH Port 0 Pull-up Control Register
00001DH Port 1 Pull-up Control Register
00001EH Port 2 Pull-up Control Register
00001FH Port 3 Pull-up Control Register
PUCR0
PUCR1
PUCR2
PUCR3
R/W
R/W
Port 0
Port 1
Port 2
Port 3
00000000B
00000000B
00000000B
00000000B
R/W
W, R/W
(Continued)
27
MB90860E Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
000020H Serial Mode Register 0
000021H Serial Control Register 0
SMR0
SCR0
W,R/W
W,R/W
00000000B
00000000B
RDR0/
TDR0
000022H Reception/Transmission Data Register 0
000023H Serial Status Register 0
R/W
00000000B
00001000B
000000XXB
SSR0
R,R/W
UART0
Extended Communication Control
R,W,
R/W
000024H
ECCR0
Register 0
000025H Extended Status/Control Register 0
000026H Baud Rate Generator Register 00
000027H Baud Rate Generator Register 01
000028H Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W
W,R/W
W,R/W
000029H Serial Control Register 1
SCR1
RDR1/
TDR1
00002AH Reception/Transmission Data Register 1
00002BH Serial Status Register 1
R/W
00000000B
00001000B
000000XXB
SSR1
R,R/W
UART1
Extended Communication Control
R,W,
R/W
00002CH
ECCR1
Register 1
00002DH Extended Status/Control Register 1
00002EH Baud Rate Generator Register 10
00002FH Baud Rate Generator Register 11
000030H PPG 0 Operation Mode Control Register
000031H PPG 1 Operation Mode Control Register
000032H PPG 0/PPG 1 Count Clock Select Register
000033H
ESCR1
BGR10
BGR11
PPGC0
PPGC1
PPG01
Reserved
PPGC2
PPGC3
PPG23
Reserved
PPGC4
PPGC5
PPG45
R/W
R/W
00000100B
00000000B
00000000B
0X000XX1B
0X000001B
000000X0B
R/W
W,R/W
W,R/W
R/W
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
000034H PPG 2 Operation Mode Control Register
000035H PPG 3 Operation Mode Control Register
000036H PPG 2/PPG 3 Count Clock Select Register
000037H
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
000038H PPG 4 Operation Mode Control Register
000039H PPG 5 Operation Mode Control Register
00003AH PPG 4/PPG 5 Clock Select Register
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
Address Match
Detection 1
00003BH Address Detect Control Register 1
PACSR1
R/W
00000000B
00003CH PPG 6 Operation Mode Control Register
00003DH PPG 7 Operation Mode Control Register
00003EH PPG 6/PPG 7 Count Clock Control Register
00003FH
PPGC6
PPGC7
PPG67
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit PPG 6/7
Reserved
(Continued)
28
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
000040H PPG 8 Operation Mode Control Register
000041H PPG 9 Operation Mode Control Register
PPGC8
PPGC9
W,R/W
W,R/W
0X000XX1B
0X000001B
16-bit PPG 8/9
PPG 8/PPG 9 Count Clock Control
000042H
Register
PPG89
R/W
000000X0B
000043H
Reserved
000044H PPG A Operation Mode Control Register PPGCA
000045H PPG B Operation Mode Control Register PPGCB
PPG A/PPG B Count Clock Select
W,R/W
W,R/W
0X000XX1B
0X000001B
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
000046H
PPGAB
R/W
000000X0B
Register
000047H
Reserved
000048H PPG C Operation Mode Control Register PPGCC
000049H PPG D Operation Mode Control Register PPGCD
PPG C/PPG D Count Clock Select
W,R/W
W,R/W
0X000XX1B
0X000001B
00004AH
PPGCD
R/W
000000X0B
Register
00004BH
Reserved
00004CH PPG E Operation Mode Control Register PPGCE
00004DH PPG F Operation Mode Control Register PPGCF
PPG E/PPG F Count Clock Select
W,R/W
W,R/W
0X000XX1B
0X000001B
00004EH
PPGEF
R/W
000000X0B
Register
00004FH
Reserved
ICS01
ICE01
ICS23
ICE23
ICS45
ICE45
ICS67
ICE67
OCS0
OCS1
OCS2
OCS3
OCS4
OCS5
OCS6
OCS7
000050H Input Capture Control Status 0/1
000051H Input Capture Edge 0/1
R/W
R/W, R
R/W
R
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXX000XXB
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
000052H Input Capture Control Status 2/3
000053H Input Capture Edge 2/3
000054H Input Capture Control Status 4/5
000055H Input Capture Edge 4/5
R/W
R
000056H Input Capture Control Status 6/7
000057H Input Capture Edge 6/7
R/W
R/W, R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000058H Output Compare Control Status 0
000059H Output Compare Control Status 1
00005AH Output Compare Control Status 2
00005BH Output Compare Control Status 3
00005CH Output Compare Control Status 4
00005DH Output Compare Control Status 5
00005EH Output Compare Control Status 6
00005FH Output Compare Control Status 7
0XX00000B
(Continued)
29
MB90860E Series
Abbrevia-
tion
Address
Register
Access Resource name Initial value
000060H Timer Control Status 0
000061H Timer Control Status 0
000062H Timer Control Status 1
000063H Timer Control Status 1
000064H Timer Control Status 2
000065H Timer Control Status 2
000066H Timer Control Status 3
000067H Timer Control Status 3
000068H A/D Control Status 0
000069H A/D Control Status 1
00006AH A/D Data 0
TMCSR0
TMCSR0
TMCSR1
TMCSR1
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
16-bit Reload
Timer 0
16-bit Reload
Timer 1
16-bit Reload
Timer 2
16-bit Reload
Timer 3
ADCS1
ADCR0
A/D Converter
ROM Mirror
00006BH A/D Data 1
ADCR1
R
00006CH ADC Setting 0
ADSR0
R/W
R/W
00006DH ADC Setting 1
ADSR1
00006EH
Reserved
ROMM
00006FH ROM Mirror Function Select
W
XXXXXXX1B
000070H
to
Reserved
00009AH
DMA Descriptor Channel Specified
00009BH
Register
DCSR
R/W
00000000B
DMA
00009CH DMA Status L Register
00009DH DMA Status H Register
DSRL
DSRH
R/W
R/W
00000000B
00000000B
Address Match
Detection 0
00009EH Address Detect Control Register 0
00009FH Delayed Interrupt/release
PACSR0
DIRR
R/W
R/W
00000000B
Delayed Interrupt XXXXXXX0B
Low Power
00011000B
0000A0H Low-power Mode Control Register
LPMCR
W,R/W
Control Circuit
Low Power
11111100B
0000A1H Clock Selection Register
CKSCR
R,R/W
Control Circuit
0000A2H,
0000A3H
Reserved
0000A4H DMA Stop Status Register
DSSR
ARSR
HACR
ECSR
WDTC
R/W
W
DMA
00000000B
0011XX00B
00000000B
0000000XB
0000A5H Automatic Ready Function Select Register
0000A6H External Address Output Control Register
0000A7H Bus Control Signal Selection Register
0000A8H Watchdog Control Register
External Memory
Access
W
W
R,W
Watchdog Timer XXXXX111B
(Continued)
30
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000A9H Time Base Timer Control Register
0000AAH Watch Timer Control Register
0000ABH
TBTC
WTC
W,R/W
R,R/W
Time Base Timer
Watch Timer
1XX00100B
1X001000B
Reserved
0000ACH DMA Enable L Register
0000ADH DMA Enable H Register
DERL
DERH
R/W
R/W
00000000B
00000000B
DMA
Flash Control Status Register
0000AEH (Flash Devices only.
Otherwise reserved)
FMCS
R,R/W
Flash Memory
000X0000B
0000AFH
Reserved
0000B0H Interrupt Control Register 00
0000B1H Interrupt Control Register 01
0000B2H Interrupt Control Register 02
0000B3H Interrupt Control Register 03
0000B4H Interrupt Control Register 04
0000B5H Interrupt Control Register 05
0000B6H Interrupt Control Register 06
0000B7H Interrupt Control Register 07
0000B8H Interrupt Control Register 08
0000B9H Interrupt Control Register 09
0000BAH Interrupt Control Register 10
0000BBH Interrupt Control Register 11
0000BCH Interrupt Control Register 12
0000BDH Interrupt Control Register 13
0000BEH Interrupt Control Register 14
0000BFH Interrupt Control Register 15
0000C0H D/A Converter Data 0 Register
0000C1H D/A Converter Data 1 Register
0000C2H D/A Control 0 Register
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
DAT0
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
XXXXXXXXB
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
Interrupt Control
DAT1
R/W
D/A Converter
DACR0
DACR1
R/W
0000C3H D/A Control 1 Register
R/W
0000C4H,
0000C5H
Reserved
0000C6H External Interrupt Enable 0
0000C7H External Interrupt Source 0
0000C8H External Interrupt Level Setting 0
0000C9H External Interrupt Level Setting 0
ENIR0
EIRR0
ELVR0
ELVR0
R/W
R/W
R/W
R/W
00000000B
XXXXXXXXB
00000000B
External Interrupt 0
00000000B
(Continued)
31
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000CAH External Interrupt Enable 1
ENIR1
EIRR1
ELVR1
ELVR1
EISSR
PSCCR
BAPL
R/W
R/W
R/W
R/W
R/W
W
00000000B
XXXXXXXXB
00000000B
0000CBH External Interrupt Source 1
0000CCH External Interrupt Level Setting 1
0000CDH External Interrupt Level Setting 1
0000CEH External Interrupt Source Select
0000CFH PLL/Sub Clock Control Register
0000D0H DMA Buffer Address Pointer L Register
0000D1H DMA Buffer Address Pointer M Register
0000D2H DMA Buffer Address Pointer H Register
0000D3H DMA Control Register
External Interrupt 1
PLL
00000000B
00000000B
XXXX0000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
BAPM
BAPH
DMACS
I/O Register Address Pointer L
DMA
0000D4H
Register
IOAL
IOAH
R/W
R/W
XXXXXXXXB
XXXXXXXXB
I/O Register Address Pointer H
0000D5H
Register
0000D6H Data Counter L Register
0000D7H Data Counter H Register
0000D8H Serial Mode Register 2
0000D9H Serial Control Register 2
DCTL
DCTH
SMR2
SCR2
R/W
R/W
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
W,R/W
W,R/W
Reception/Transmission Data
Register 2
RDR2/
TDR2
0000DAH
R/W
00000000B
00001000B
000000XXB
0000DBH Serial Status Register 2
SSR2
R,R/W
UART2
Extended Communication Control
Register 2
R,W,
R/W
0000DCH
ECCR2
0000DDH Extended Status Control Register 2
0000DEH Baud Rate Generator Register 20
0000DFH Baud Rate Generator Register 21
ESCR2
BGR20
BGR21
R/W
R/W
R/W
00000100B
00000000B
00000000B
0000E0H
to
External area
0000FFH
007900H Reload Register L0
007901H Reload Register H0
007902H Reload Register L1
007903H Reload Register H1
007904H Reload Register L2
007905H Reload Register H2
007906H Reload Register L3
007907H Reload Register H3
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16-bit PPG 0/1
16-bit PPG 2/3
XXXXXXXXB
(Continued)
32
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
007908H Reload Register L4
007909H Reload Register H4
00790AH Reload Register L5
00790BH Reload Register H5
00790CH Reload Register L6
00790DH Reload Register H6
00790EH Reload Register L7
00790FH Reload Register H7
007910H Reload Register L8
007911H Reload Register H8
007912H Reload Register L9
007913H Reload Register H9
007914H Reload Register LA
007915H Reload Register HA
007916H Reload Register LB
007917H Reload Register HB
007918H Reload Register LC
007919H Reload Register HC
00791AH Reload Register LD
00791BH Reload Register HD
00791CH Reload Register LE
00791DH Reload Register HE
00791EH Reload Register LF
00791FH Reload Register HF
007920H Input Capture 0
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
IPCP4
IPCP4
IPCP5
IPCP5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
16-bit PPG 4/5
16-bit PPG 6/7
16-bit PPG 8/9
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
007921H Input Capture 0
R
007922H Input Capture 1
R
007923H Input Capture 1
R
007924H Input Capture 2
R
007925H Input Capture 2
R
007926H Input Capture 3
R
007927H Input Capture 3
R
007928H Input Capture 4
R
007929H Input Capture 4
R
00792AH Input Capture 5
R
00792BH Input Capture 5
R
33
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
00792CH Input Capture 6
00792DH Input Capture 6
00792EH Input Capture 7
00792FH Input Capture 7
IPCP6
IPCP6
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
R
Input Capture 6/7
IPCP7
R
IPCP7
R
007930H Output Compare 0
007931H Output Compare 0
007932H Output Compare 1
007933H Output Compare 1
007934H Output Compare 2
007935H Output Compare 2
007936H Output Compare 3
007937H Output Compare 3
007938H Output Compare 4
007939H Output Compare 4
00793AH Output Compare 5
00793BH Output Compare 5
00793CH Output Compare 6
00793DH Output Compare 6
00793EH Output Compare 7
00793FH Output Compare 7
007940H Timer Data 0
OCCP0
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
OCCP4
OCCP4
OCCP5
OCCP5
OCCP6
OCCP6
OCCP7
OCCP7
TCDT0
TCDT0
TCCSL0
TCCSH0
TCDT1
TCDT1
TCCSL1
TCCSH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
I/O Timer 0
007941H Timer Data 0
00000000B
007942H Timer Control Status 0
007943H Timer Control Status 0
007944H Timer Data 1
00000000B
0XXXXXXXB
00000000B
007945H Timer Data 1
00000000B
I/O Timer 1
007946H Timer Control Status 1
007947H Timer Control Status 1
00000000B
0XXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
007948H
TMR0/
TMRLR0
16-bit Reload
Timer 0
Timer 0/Reload 0
007949H
00794AH
TMR1/
TMRLR1
16-bit Reload
Timer 1
Timer 1/Reload 1
00794BH
00794CH
TMR2/
TMRLR2
16-bit Reload
Timer 2
Timer 2/Reload 2
00794DH
00794EH
TMR3/
TMRLR3
16-bit Reload
Timer 3
Timer 3/Reload 3
00794FH
34
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
007950H Serial Mode Register 3
007951H Serial Control Register 3
SMR3
SCR3
W,R/W
W,R/W
00000000B
00000000B
Reception/Transmission Data
Register 3
RDR3/
TDR3
007952H
R/W
00000000B
00001000B
000000XXB
007953H Serial Status Register 3
SSR3
R,R/W
UART3
Extended Communication Control
Register 3
R,W,
R/W
007954H
ECCR3
007955H Extended Status Control Register
007956H Baud Rate Generator Register 30
007957H Baud Rate Generator Register 31
007958H Serial Mode Register 4
ESCR3
BGR30
BGR31
SMR4
R/W
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W
W,R/W
W,R/W
007959H Serial Control Register 4
SCR4
Reception/Transmission Data
Register 4
RDR4/
TDR4
00795AH
R/W
00000000B
00001000B
000000XXB
00795BH Serial Status Register 4
SSR4
R,R/W
UART4
Extended Communication Control
Register 4
R,W,
R/W
00795CH
ECCR4
00795DH Extended Status Control Register
00795EH Baud Rate Generator Register 40
00795FH Baud Rate generator Register 41
ESCR4
BGR40
BGR41
R/W
R/W
R/W
00000100B
00000000B
00000000B
007960H
to
Reserved
00796BH
00796CH Clock Output Enable Register
CLKR
R/W
Clock Monitor
XXXX0000B
00796DH
to
Reserved
00796FH
007970H I2C Bus Status Register 0
007971H I2C bus Control Register 0
IBSR0
IBCR0
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
R
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
007972H
I2C 10-bit Slave Address Register 0
007973H
007974H
I2C Interface 0
I2C 10-bit Slave Address Mask
Register 0
007975H
007976H I2C 7-bit Slave Address Register 0
007977H I2C 7-bit Slave Address Mask Register 0
007978H I2C Data Register 0
ISMK0
IDAR0
007979H,
00797AH
Reserved
(Continued)
35
MB90860E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
00797BH I2C Clock Control Register 0
ICCR0
R/W
I2C Interface 0
00011111B
00797CH
to
Reserved
00797FH
007980H I2C Bus Status Register 1
007981H I2C Bus Control Register 1
IBSR1
IBCR1
ITBAL1
ITBAH1
ITMKL1
ITMKH1
ISBA1
R
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
007982H
I2C 10-bit Slave Address Register 1
007983H
007984H
I2C Interface 1
I2C 10-bit Slave Address Mask
Register 1
007985H
007986H I2C 7-bit Slave Address Register 1
007987H I2C 7-bit Slave Address Mask Register 1
007988H I2C Data Register 1
ISMK1
IDAR1
007989H,
00798AH
Reserved
00798BH I2C Clock Control Register 1
ICCR1
R/W
I2C Interface 1
00011111B
0001X000B
00798CH
to
0079C1H
Reserved
Clock modulator control register
0079C2H
Clock modulator
(using prohibited)
CMCR
R, R/W
(setting prohibited)
0079C3H
to
Reserved
0079DFH
0079E0H Detect Address Setting 0
0079E1H Detect Address Setting 0
0079E2H Detect Address Setting 0
0079E3H Detect Address Setting 1
0079E4H Detect Address Setting 1
0079E5H Detect Address Setting 1
0079E6H Detect Address Setting 2
0079E7H Detect Address Setting 2
0079E8H Detect Address Setting 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
0079E9H
to
Reserved
0079EFH
(Continued)
36
MB90860E Series
(Continued)
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0079F0H Detect Address Setting 3
0079F1H Detect Address Setting 3
0079F2H Detect Address Setting 3
0079F3H Detect Address Setting 4
0079F4H Detect Address Setting 4
0079F5H Detect Address Setting 4
0079F6H Detect Address Setting 5
0079F7H Detect Address Setting 5
0079F8H Detect Address Setting 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
Reserved
007FFFH
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
37
MB90860E Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
EI2OS
clear
DMA ch
number
register
Interrupt cause
Number
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
Number
Address
Reset
N
N
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
N
(Reserved)
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
(Reserved)
N
Input Capture 6
Y1
Y1
N
Input Capture 7
I2C0
(Reserved)
N
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
PPG 0/1/4/5
Y1
Y1
Y1
Y1
N
1
2
⎯
⎯
⎯
⎯
⎯
⎯
3
PPG 2/3/6/7
N
PPG 8/9/C/D
N
PPG A/B/E/F
N
Time Base Timer
External Interrupt 0 to 3, 8 to 11
Watch Timer
N
Y1
N
⎯
4
External Interrupt 4 to 7, 12 to 15
8/10-bit A/D Converter
I/O Timer 0, I/O Timer 1
Input Capture 4/5, I2C1
Output Compare 0/1/4/5
Input Capture 0 to 3
Output Compare 2/3/6/7
UART 0 Reception
UART 0 Transmission
Y1
Y1
N
5
⎯
6
Y1
Y1
Y1
Y1
Y2
Y1
7
8
9
10
11
UART 1 Reception /
UART 3 Reception
Y2
Y1
12
13
#37
#38
FFFF68H
FFFF64H
ICR13
0000BDH
UART 1 Transmission /
UART 3 Transmission
(Continued)
38
MB90860E Series
(Continued)
Interrupt cause
Interrupt control
Interrupt vector
EI2OS
clear
DMA ch
number
register
Number
Address
Number
Address
UART 2 Reception /
UART 4 Reception
Y2
Y1
14
15
#39
FFFF60H
ICR14
ICR15
0000BEH
UART 2 Transmission /
UART 4 Transmission
#40
FFFF5CH
Flash Memory
N
N
⎯
⎯
#41
#42
FFFF58H
FFFF54H
0000BFH
Delayed interrupt
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
39
MB90860E Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
AVCC
VCC = AVCC*2
Power supply voltage*1
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
VSS − 0.3 VSS + 6.0
V
Input voltage*1
Output voltage*1
VI
VO
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
*3
*3
Maximum Clamp Current
ICLAMP
Σ|ICLAMP|
IOL
−4.0
⎯
+4.0
40
mA *5
mA *5
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mW
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
Power consumption
⎯
15
IOLAV
ΣIOL
⎯
4
⎯
100
50
ΣIOLAV
IOH
⎯
⎯
−15
−4
IOHAV
ΣIOH
ΣIOHAV
PD
⎯
⎯
−100
−50
340
+105
+150
⎯
⎯
Operating temperature
TA
−40
−55
°C
Storage temperature
TSTG
°C
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
(Continued)
40
MB90860E Series
(Continued)
*5 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47,
P50 to P57 (evaluation device : P50 to P55) , P60 to P67, P70 to P77, P80 to P87,
P90 to P97, PA0 to PA1
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0 V to 16 V)
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
41
MB90860E Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
4.0
5.0
5.5
V
Under normal operation
Under normal operation, when not
using the A/D converter and not
Flash programming.
3.5
5.0
5.5
V
VCC,
AVCC
Power supply voltage
4.5
3.0
5.0
5.5
5.5
V
V
When External bus is used.
⎯
Maintains RAM data in stop mode
Use a ceramic capacitor or capac-
itor of better AC characteristics.
Capacitor at the VCC should be
greater than this capacitor.
Smooth capacitor
CS
0.1
⎯
⎯
1.0
µF
°C
Operating temperature
TA
−40
+105
C
CS
C Pin Connection Diagram
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
42
MB90860E Series
3. DC Characteristics
Sym-
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P44, P45, P46,
P47, P50, P82, P83)
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Port inputs if
Automotive input levels
are selected
VIHA
VIHT
VIHS
⎯
⎯
⎯
⎯
⎯
⎯
0.8 VCC
2.0
⎯
⎯
⎯
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
Input H
voltage
(At VCC =
5 V 10%)
Port inputs if TTL input
levels are selected
P12, P50, P82, P85
inputs if CMOS input
levels are selected
0.7 VCC
P44, P45, P46, P47 in-
putsifCMOShysteresis
input levels are selected
VIHI
⎯
⎯
0.7 VCC
⎯
VCC + 0.3
V
RST input pin (CMOS
hysteresis)
VIHR
VIHM
⎯
⎯
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VCC − 0.3
MD input pin
Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P44, P45, P46,
P47, P50, P82, P83)
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Port inputs if
Automotive input levels
are selected
VILA
VILT
VILS
⎯
⎯
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VSS − 0.3
⎯
⎯
⎯
0.5 VCC
0.8
V
V
V
Input L
voltage
(At VCC =
5 V 10%)
Port inputs if TTL
input levels are selected
P12, P50, P82, P85
inputs if CMOS input
levels are selected
0.3 VCC
P44, P45, P46, P47 in-
putsifCMOShysteresis
input levels are selected
VILI
⎯
⎯
VSS − 0.3
⎯
0.3 VCC
V
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
⎯
⎯
Normal
outputs
I2Ccurrent VCC = 4.5 V,
outputs
⎯
⎯
VSS − 0.3
VSS − 0.3
VCC − 0.5
⎯
⎯
⎯
0.2 VCC
VSS + 0.3
⎯
V
V
V
MD input pin
Output H
voltage
VCC = 4.5 V,
IOH = −4.0 mA
Output H
voltage
VOHI
VOL
VOLI
VCC − 0.5
⎯
⎯
⎯
⎯
V
V
V
IOH = −3.0 mA
VCC = 4.5 V,
IOL = 4.0 mA
Output L
voltage
Normal
outputs
I2Ccurrent VCC = 4.5 V,
outputs IOL = 3.0 mA
⎯
⎯
0.4
0.4
Output L
voltage
(Continued)
43
MB90860E Series
(Continued)
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
Parameter
Pin
Condition
Unit Remarks
+ 1 µA
bol
Min Typ Max
Input leak current
IIL
⎯
VCC = 5.5 V, VSS < VI < VCC
−1
⎯
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-up
resistance
RUP
⎯
⎯
25
50
100 kΩ
Except
Pull-down
resistance
RDOWN
MD2
25
⎯
⎯
⎯
⎯
⎯
50
55
70
75
25
0.3
100 kΩ Flash
devices
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
70
85
90
35
0.8
mA
mA
mA
mA
mA
VCC = 5.0 V,
Flash
devices
ICC
Internal frequency : 24 MHz,
At writing FLASH memory.
VCC = 5.0 V,
Flash
devices
Internal frequency : 24 MHz,
At erasing FLASH memory.
VCC = 5.0 V,
ICCS
Internal frequency : 24 MHz,
At Sleep mode.
VCC = 5.0 V,
ICTS
Internal frequency : 2 MHz,
At Main Timer mode
VCC = 5.0 V,
Power supply
current*
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency = 4 MHz
VCC
ICTSPLL6
⎯
⎯
⎯
4
7
mA
VCC = 5.0 V
Internal frequency : 8 kHz,
At sub operation
TA = +25°C
VCC = 5.0 V
Internal frequency : 8 kHz,
At sub sleep
ICCL
70
20
140 µA
ICCLS
50
µA
TA = +25°C
VCC = 5.0 V
Internal frequency : 8 kHz,
At watch mode
TA = +25°C
VCC = 5.0 V,
At Stop mode,
TA = +25°C
ICCT
ICCH
CIN
⎯
⎯
⎯
10
7
35
25
15
µA
µA
pF
Other than C,
AVCC, AVSS,
AVRH,AVRL,
VCC, VSS,
Input capacity
⎯
5
* : The power supply current is measured with an external clock.
44
MB90860E Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
When using an oscillation
circuit
X0, X1
3
⎯
16
MHz
fC
Clock frequency
When using an external
clock*
X0, X1
X0A, X1A
X0, X1
3
⎯
24
MHz
kHz
ns
fCL
—
32.768 100
When using an oscillation
circuit
62.5
⎯
⎯
333
333
tCYL
Clock cycle time
When using an external
clock
X0, X1
41.67
ns
tCYLL
PWH, PWL
PWHL, PWLL
tCR, tCF
fCP
X0A, X1A
10
10
30.5
⎯
—
⎯
⎯
5
µs
ns
µs
ns
X0
X0A
X0
⎯
Duty ratio is about 30% to
70%.
Input clock pulse width
5
15.2
⎯
Input clock rise and fall time
⎯
When using external clock
1.5
⎯
⎯
24
50
666
⎯
MHz When using main clock
kHz When using sub clock
Internal operating clock
frequency (machine clock)
fCPL
⎯
8.192
⎯
tCP
⎯
41.67
20
ns
When using main clock
When using sub clock
Internal operating clock
cycle time (machine clock)
tCPL
⎯
122.1
µs
* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as
mentioned in “Relation among external clock frequency and machine clock frequency”.
t
CYL
0.8 VCC
0.2 VCC
X0
P
WH
PWL
t
CF
tCR
t
CYLL
0.8 VCC
0.2 VCC
X0A
P
WHL
PWLL
t
CF
tCR
Clock Timing
45
MB90860E Series
• Guaranteed PLL operation range
Guaranteed operation range
5.5
4.0
Guaranteed A/D Converter
operation range
3.5
Guaranteed PLL operation range
1.5
24
4
Machine clock fCP (MHz)
Guaranteed operation range of MB90860E series
Guaranteed oscillation frequency range
× 2
× 1
× 6 × 4
× 3
24
16
12
× 1/2
(PLL off)
8
4.0
1.5
12
16
3
8
4
24
External clock fC (MHz) *
* : When using crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz
46
MB90860E Series
(2) Reset Standby Input
Parameter Symbol
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
Value
Pin
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
Reset input
tRSTL
Oscillation time of oscillator*
RST
⎯
⎯
ns
time
+ 100 µs
100
µs
In Time Timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode, Power-on:
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
47
MB90860E Series
(3) Power On Reset
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
30
Power on rise time
Power off time
tR
VCC
VCC
0.05
1
ms
⎯
tOFF
⎯
ms Due to repetitive operation
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur. We
recommend that you startup smoothly by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below. Perform while
not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate
VCC
We recommend a rise of
50 mV/ms maximum.
3 V
Holds RAM data
VSS
(4) Clock Output Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
CLK
CLK
Condition
Unit
Remarks
Min
62.5
41.76
20
Max
⎯
ns
ns
ns
ns
fCP = 16 MHz
Cycle time
tCYC
⎯
⎯
⎯
fCP = 24 MHz
fCP = 16 MHz
fCP = 24 MHz
⎯
CLK ↑ → CLK ↓
tCHCL
13
⎯
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
48
MB90860E Series
(5) Bus Timing (Read)
Parameter
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Sym-
bol
Pin
Condition
Unit
Min
Max
ALE pulse width
tLHLL ALE
tCP/2 − 10
⎯
ns
ns
ns
ns
ALE, A23 to A16,
AD15 to AD00
Valid address → ALE ↓ time
ALE ↓ → Address valid time
Valid address → RD ↓ time
tAVLL
tCP/2 − 20
tCP/2 − 15
tCP − 15
⎯
⎯
⎯
tLLAX ALE, AD15 to AD00
A23 to A16,
tAVRL
AD15 to AD00, RD
A23 to A16,
AD15 to AD00
Valid address → Valid data input tAVDV
⎯
5 tCP/2 − 60
ns
RD pulse width
tRLRH RD
3 tCP/2 − 20
⎯
⎯
ns
ns
ns
ns
ns
⎯
RD ↓ → Valid data input
RD ↑ → Data hold time
RD ↓ → ALE ↑ time
tRLDV RD, AD15 to AD00
tRHDX RD, AD15 to AD00
tRHLH RD, ALE
3 tCP/2 − 50
0
⎯
⎯
⎯
tCP/2 − 15
tCP/2 − 10
RD ↑ → Address valid time
tRHAX RD, A23 to A16
A23 to A16,
tAVCH
Valid address → CLK ↑ time
tCP/2 − 16
⎯
ns
AD15 to AD00, CLK
RD ↓ → CLK ↑ time
ALE ↓ → RD ↓ time
tRLCH RD, CLK
tLLRL ALE, RD
tCP/2 − 15
tCP/2 − 15
⎯
⎯
ns
ns
tRLCH
tAVCH
2.4 V
2.4 V
CLK
ALE
RD
tLLAX
tAVLL
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
tLHLL
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
VIH
VIL
2.4 V
0.8 V
VIH
VIL
AD15 to AD00
Address
Read data
49
MB90860E Series
(6) Bus Timing (Write)
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
A23 to A16,
AD15 to AD00,
WR
Valid address → WR ↓ time
tAVWL
tCP−15
⎯
ns
WR pulse width
tWLWH
tDVWH
WR
3 tCP/2 − 20
3 tCP/2 − 20
⎯
⎯
ns
ns
AD15 to AD00,
WR
Valid data output → WR ↑ time
⎯
AD15 to AD00,
WR
WR ↑ → Data hold time
tWHDX
15
⎯
ns
WR ↑ → Address valid time
WR ↑ → ALE ↑ time
tWHAX
tWHLH
tWLCH
A23 to A16, WR
WR, ALE
tCP/2 − 10
tCP/2 − 15
tCP/2 − 15
⎯
⎯
⎯
ns
ns
ns
WR ↓ → CLK ↑ time
WR, CLK
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
50
MB90860E Series
(7) Ready Input Timing
Parameter
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Rated Value
Test
Sym-
bol
Pin
Units
Remarks
Condition
Min
45
32
0
Max
⎯
ns fCP = 16 MHz
ns fCP = 24 MHz
ns
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
⎯
⎯
⎯
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
51
MB90860E Series
(8) Hold Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Units
Min
30
Max
tCP
Pin floating → HAK ↓ time
HAK ↑ time → Pin valid time
tXHAL
tHAHV
HAK
HAK
ns
ns
⎯
tCP
2 tCP
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
High-Z
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
52
MB90860E Series
(9) UART0/1/2/3/4
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK4
8 tCP
⎯
ns
ns
SCK0 to SCK4,
SOT0 to SOT4
SCK ↓ → SOT delay time
tSLOV
−80
100
60
+80
⎯
Internal clock
operation output pins
are
SCK0 to SCK4,
SIN0 to SIN4
Valid SIN → SCK ↑
tIVSH
tSHIX
ns
ns
CL = 80 pF + 1 TTL.
SCK0 to SCK4,
SIN0 to SIN4
SCK ↑ → Valid SIN hold time
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
SCK0 to SCK4
SCK0 to SCK4
4 tCP
⎯
⎯
ns
ns
tSLSH
4 tCP
SCK0 to SCK4, External clock
SOT0 to SOT4 operation output pins
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
⎯
60
60
150
⎯
ns
ns
ns
are
SCK0 to SCK4,
SIN0 to SIN4
CL = 80 pF + 1 TTL.
SCK0 to SCK4,
SIN0 to SIN4
SCK ↑ → Valid SIN hold time
⎯
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
tSHIX
VIH
VIL
VIH
VIL
SIN
Internal Shift Clock Mode
53
MB90860E Series
tSLSH
tSHSL
VIH
VIH
SCK
SOT
VIL
tSLOV
VIL
2.4 V
0.8 V
tIVSH
tSHIX
VIH
VIL
VIH
VIL
SIN
External Shift Clock Mode
(10) Trigger Input Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
INT0 to INT15,
INT0R to INT15R,
ADTG
tTRGH
tTRGL
Input pulse width
⎯
5 tCP
⎯
ns
VIH
VIH
INT0 to INT15,
INT0R to INT15R,
ADTG
VIL
VIL
tTRGH
tTRGL
54
MB90860E Series
(11) Timer Related Resource Input Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
tTIWL
TIN0 to TIN3,
IN0 to IN7
Input pulse width
⎯
4 tCP
⎯
ns
VIH
VIH
VIL
VIL
TIN0 to TIN3,
IN0 to IN7
tTIWH
tTIWL
(12) Timer Related Resource Output Timing
(TA = –40°C to +105°C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
TOT0 to TOT3,
PPG0 to PPGF
CLK ↑ → TOUT change time
tTO
⎯
30
⎯
ns
2.4 V
CLK
2.4 V
0.8 V
TOT0 to TOT3,
PPG0 to PPGF
tTO
55
MB90860E Series
(13) I2C Timing
(TA = –40°C to +105°C, VCC = 5.0 V 10%, VSS = 0.0 V)
Fast-mode*1
Standard-mode
Parameter
Symbol
Condition
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
tHIGH
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
⎯
3.45*3
⎯
0.6
0
⎯
0.9*4
⎯
µs
µs
ns
µs
µs
R = 1.7 kΩ,
C = 50 pF*2
Data hold time
SCL ↓ → SDA ↓ ↑
Data set-up time
SDA ↓ ↑ → SCL ↑
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL ↑ → SDA ↑
⎯
⎯
Bus free time between a STOP and START
condition
⎯
⎯
*1 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
SDA
tBUS
tSUDAT
tHDSTA
tLOW
SCL
tHIGH
tHDSTA
tHDDAT
tSUSTA
tSUSTO
56
MB90860E Series
5. A/D Converter
(TA
= −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
Resolution
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
3.0
2.5
LSB
LSB
Nonlinearity error
⎯
⎯
Differential
nonlinearity error
⎯
⎯
⎯
⎯
1.9
LSB
Zero reading
voltage
VOT
VFST
AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB
Full scale reading
voltage
AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
1.0
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
⎯
⎯
16500
µs
µs
2.0
0.5
1.2
∞
Analog port input
current
IAIN
AN0 to AN23
AN0 to AN23
−0.3
⎯
⎯
+0.3
µA
Analog input
voltage range
VAIN
AVRL
AVRH
V
⎯
⎯
IA
AVRH
AVRL
AVCC
AVRL + 2.7
⎯
⎯
AVCC
V
V
Reference
voltage range
0
AVRH − 2.7
⎯
⎯
⎯
⎯
3.5
⎯
7.5
5
mA
µA
µA
µA
Power supply
current
IAH
IR
AVCC
*
*
AVRH
AVRH
600
⎯
900
5
Reference
voltage current
IRH
Offset between
input channels
⎯
AN0 to AN23
⎯
⎯
4
LSB
* : IF A/D convertor is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as AVRH − AVRL becomes smaller.
57
MB90860E Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
Total error
: Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Zero reading
voltage
: Input voltage which results in the minimum conversion value.
Full scale
: Input voltage which results in the maximum conversion value.
reading voltage
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB (Ideal value) =
1 LSB
AVRH − AVRL
[V]
1024
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
58
MB90860E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
3FE
3FD
H
H
H
Actual conversion
characteristics
N + 1
H
H
H
H
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT
}
V
FST (actual
measurement
value)
N
V
NT (actual
measurement value)
004
003
002
001
H
H
H
H
V
(N + 1) T
(actual measurement
Actual conversion
characteristics
N − 1
N − 2
value)
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
V
OT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
59
MB90860E Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period ≤ 0.5 µs)
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.
• Analog input circuit model
R
Analog input
Comparator
C
4.5 V ≤ AVCC ≤ 5.5 V : R=: 2.52 kΩ, C=: 10.7 pF
4.0 V ≤ AVCC < 4.5 V : R=: 13.6 kΩ, C=: 10.7 pF
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics
Value
Parameter
Conditions
Unit
Remarks
Min
Typ
Max
Excludes programming
prior to erasure
Sector erase time
Chip erase time
⎯
1
9
15
s
s
TA = +25 °C
VCC = 5.0 V
Excludes programming
prior to erasure
⎯
⎯
Word (16-bit width)
programming time
Except for the over head
time of the system
⎯
10000
20
16
⎯
⎯
3600
⎯
µs
Programs/Erase cycle
⎯
cycle
Year
Flash Data Retention
Time
Average
TA = +85 °C
⎯
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
60
MB90860E Series
■ EXAMPLE CHARACTERISTICS
• MB90F867E, MB90F867ES
ICC − VCC
ICCL − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 8 kHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
ICCS − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICCLS − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
35
50
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
6.5
ICTS − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
ICCT − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
400
350
300
250
200
150
100
50
20
18
16
14
12
10
8
6
4
2
0
f = 2 MHz
f = 8 kHz
0
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
6.5
ICTSPLL6 − VCC
ICCH − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at stop
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
4.5
VCC (V)
5.5
6.5
61
MB90860E Series
• MB90867E, MB90867ES
ICC − VCC
ICCL − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 8 kHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
2.5
2.5
2.5
3.5
3.5
3.5
4.5
VCC (V)
5.5
6.5
2.5
3.5
3.5
3.5
3.5
4.5
VCC (V)
5.5
6.5
ICCS − VCC
ICCLS − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
50
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
f = 24 MHz
f = 20 MHz
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 8 kHz
f = 4 MHz
f = 2 MHz
0
0
2.5
4.5
VCC (V)
5.5
6.5
4.5
5.5
6.5
VCC (V)
ICTS − VCC
ICCT − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at external clock operating
f = Internal operation frequency
20
18
16
14
12
10
8
6
4
2
0
400
350
300
250
200
150
100
50
f = 2 MHz
f = 8 kHz
0
2.5
4.5
VCC (V)
5.5
6.5
4.5
VCC (V)
5.5
6.5
ICTSPLL6 − VCC
ICCH − VCC
TA = +25 °C, at external clock operating
f = Internal operation frequency
TA = +25 °C, at stop
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
f = 24 MHz
2.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
VCC (V)
62
MB90860E Series
• I/O characteristics
(VCC−VOH) − IOH
VOL − IOL
TA = +25 °C, VCC = 4.5 V
TA = +25 °C, VCC = 4.5 V
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
IOH (mA)
Automotive VIN − VCC
CMOS VIN − VCC
UART-SIN pin, other than I2C pin
TA = +25 °C
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
VIHA
VILA
VIHS
VILS
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
TTL VIN − VCC
CMOS VIN − VCC
UART-SIN pin, I2C pin
TA = +25 °C
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
2.3
2.0
1.8
1.5
1.3
1.0
0.8
0.5
0.3
0.0
VIHS
VILS
VIHT
VILT
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
63
MB90860E Series
■ ORDERING INFORMATION
Part number
MB90F867EPF
Package
Remarks
100-pin Plastic QFP
(FPT-100P-M06)
MB90F867ESPF
MB90F867EPFV
MB90F867ESPFV
MB90867EPF
Flash memory product
100-pin Plastic LQFP
(FPT-100P-M05)
100-pin Plastic QFP
(FPT-100P-M06)
MB90867ESPF
MB90867EPFV
MB90867ESPFV
MB90V340E-101
MB90V340E-102
MASK ROM product
Evaluation product
100-pin Plastic LQFP
(FPT-100P-M05)
299-pin Ceramic PGA
(PGA-299C-A01)
64
MB90860E Series
■ PACKAGE DIMENSIONS
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90 0.40(.941 .016)
*
20.00 0.20(.787 .008)
80
51
81
50
0.10(.004)
17.90 0.40
(.705 .016)
*
14.00 0.20
(.551 .008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8˚
1
30
0.65(.026)
0.32 0.05
(.013 .002)
0.17 0.06
(.007 .002)
M
0.13(.005)
0.25 0.20
(.010 .008)
(Stand off)
0.80 0.20
(.031 .008)
"A"
0.88 0.15
(.035 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
65
MB90860E Series
(Continued)
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.65g
Code
(Reference)
(FPT-100P-M05)
P-LFQFP100-14×14-0.50
100-pin plastic LQFP
(FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*
14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
INDEX
0.10 0.10
(.004 .004)
(Stand off)
100
26
0˚~8˚
"A"
0.50 0.20
(.020 .008)
0.25(.010)
1
25
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
(.008 .002)
0.145 0.055
(.0057 .0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F100007S-c-4-6
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
66
MB90860E Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited
Business Promotion Dept.
F0610
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