MB90F352ESPMC [FUJITSU]
16-bit Proprietary Microcontrollers; 16位微控制器专用型号: | MB90F352ESPMC |
厂家: | FUJITSU |
描述: | 16-bit Proprietary Microcontrollers |
文件: | 总85页 (文件大小:900K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13744-2E
16-bit Proprietary Microcontrollers
CMOS
F2MC-16LX MB90350E Series
MB90F351E (S) , MB90F351TE (S) , MB90F352E (S) , MB90F352TE (S) , MB90351E (S) ,
MB90351TE (S) , MB90352E (S) , MB90352TE (S) , MB90F356E (S) , MB90F356TE (S) ,
MB90F357E (S) , MB90F357TE (S) , MB90356E (S) , MB90356TE (S) , MB90357E (S) ,
MB90357TE(S) , MB90V340E-101/102/103/104
■ DESCRIPTION
The MB90350E series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose FUJITSU
16-bit microcontroller designing for automotive and industrial applications. Its main feature is the on-board CAN
interface, which conforms to CAN standard Version2.0 Part A and Part B, while supporting a very flexible message
buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 µm CMOS
technology, Fujitsu now offers on-chip Flash ROM program memory up to 128 Kbytes.
The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major
advantage in terms of EMI and power consumption.
The PLL clock multiplication circuit provides an internal 42 ns instruction execution time from an external 4 MHz
clock. Also, the clock supervisor function can monitor main clock and sub clock independently.
As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit,
2 separate 16-bit free-run timers, 2-channel UART and 15-channel 8/10-bit A/D converter built-in.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB90350E Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed (devices without
S-suffix only) .
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time
multiplied PLL clock).
• Built-in clock modulation circuit
• 16 Mbytes CPU memory space
24-bit internal addressing
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
• Clock supervisor (MB90x356x and MB90x357x only)
• Main clock or sub clock is monitored independently.
• Internal CR oscillation clock (100 kHz typical) can be used as sub clock.
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported.
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that stops CPU operating clock)
• Main timer mode (a timebase timer mode switched from the main clock mode)
• PLL timer mode (a timebase timer mode switched from the PLL clock mode)
• Watch mode (a mode that operates sub clock and watch timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU intermittent operation mode
• Process
CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 49 ports (devices without S-suffix : devices that correspond to sub clock)
- 51 ports (devices with S-suffix : devices that do not correspond to sub clock)
(Continued)
2
MB90350E Series
• Sub clock pin (X0A, X1A)
• Yes (using the external oscillation) : devices without S-suffix
• No (using the sub clock mode at internal CR oscillation) : devices with S-suffix
• Timer
• Timebase timer, watch timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 10 channels or 16-bit × 6 channels
• 16-bit reload timer : 2 channels (only Evaluation products has 4 channels)
• 16- bit input/output timer
- 16-bit free-run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU4/5/6/7, OCU4/5/6/7)
- 16- bit input capture: (ICU) : 6 channels
- 16-bit output compare : (OCU) : 4 channels
• FULL-CAN interface : 1 channel
• Compliant with CAN standard Version2.0 Part A and Part B
• 16 message buffers are built-in
• CAN wake-up function
• UART (LIN/SCI) : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available.
• I2C interface*1 : 1 channel
Up to 400 kbps transfer rate
• DTP/External interrupt : 8 channels, CAN wakeup : 1 channel
Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt by
external input.
• Delay interrupt generator module
Generates interrupt request for task switching.
• 8/10-bit A/D converter : 15 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 6 address pointers.
• Capable of changing input voltage level for port
• Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)
• TTL level (corresponds to external bus pins only, initial level of these pins is TTL in external bus mode)
• Low voltage/CPU operation detection reset (devices with T-suffix)
• Detects low voltage (4.0 V 0.3 V) and resets automatically
• Resets automatically when program is runaway and counter is not cleared within interval time
(approx. 262 ms : external 4 MHz)
• Dual operation Flash memory
• Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
• Supported TA = + 125 °C
The maximum operating frequency is 24 MHz*2 : (at TA = +125 °C) .
(Continued)
3
MB90350E Series
(Continued)
• Flash security function
• Protects the content of Flash memory
(MB90F352x, MB90F357x only)
• External bus interface
• 4 Mbytes external memory space
MB90F351E(S), MB90F351TE(S), MB90F352E(S), MB90F352TE(S) : External bus Interface can not be used
in internal vector mode. It can be used only in external vector mode.
*1 : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
*2 : If used exceeding TA = + 105 °C, be sure to contact Fujitsu for reliability limitations.
4
MB90350E Series
■ PRODUCT LINEUP1 (Without Clock supervisor function)
•Flash memory products
Part Number
MB90F351E,
MB90F352E
MB90F351TE,
MB90F352TE
MB90F351ES,
MB90F352ES
MB90F351TES,
MB90F352TES
Parameter
Type
Flash memory products
F2MC-16LX CPU
CPU
PLL clock multiplication circuit (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
System clock
64 Kbytes Flash memory : MB90F351E(S), MB90F351TE(S)
128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the
same time) : MB90F352E(S), MB90F352TE(S)
ROM
RAM
4 Kbytes
Emulator-specific
power supply*1
⎯
Sub clock pin
(X0A, X1A)
Yes
No
(Max 100 kHz)
Clock supervisor
No
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
Operating voltage
Operating
temperature
−40 °C to +125 °C
Package
LQFP-64
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 kbps)
A/D converter
1 channel
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs includes sample time (per one channel)
16-bit reload timer
(2 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function.
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU4/5/6/7.
16-bit I/O timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when it matches Output Compare (ch.0, ch.4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock frequency)
4 channels
16-bit output
compare
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
(Continued)
5
MB90350E Series
(Continued)
Part Number
MB90F351E,
MB90F351TE,
MB90F352TE
MB90F351ES,
MB90F352ES
MB90F351TES,
MB90F352TES
MB90F352E
Parameter
6 channels
16-bit Input capture
Retains free-run timer value by (rising edge, falling edge or rising & falling edge) , signals
an interrupt.
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
8/16-bit
programmable pulse
generator
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler + 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
1 channel
Compliant with CAN standard Version2.0 Part A and Part B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
16 prioritized message buffers for data and ID
Supports multiple messages.
CAN interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External interrupt
D/A converter
Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
⎯
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
I/O ports
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 times
Data retention time : 20 years
Boot block configuration
Flash memory
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F352E(S) and
MB90F352TE(S) only)
Corresponding
evaluation name
MB90V340E-102
MB90V340E-101
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trademark of Advanced Micro Devices Inc.
6
MB90350E Series
• MASK ROM products/Evaluation products
Part Number
MB90351E,
MB90352E
MB90351TE,
MB90352TE
MB90351ES, MB90351TES, MB90V340E- MB90V340E-
MB90352ES MB90352TES
101
102
Parameter
Type
MASK ROM products
F2MC-16LX CPU
Evaluation products
CPU
PLL clock multiplication circuit (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
System clock
MASK ROM
ROM
RAM
64 Kbytes : MB90351E(S), MB90351TE(S)
128 Kbytes :MB90352E(S), MB90352TE(S)
External
4 Kbytes
30 Kbytes
Yes
Emulator-specific
power supply*
⎯
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Yes
No
No
No
Yes
Clock supervisor
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
Operating
voltage range
5 V 10%
Operating
temperature range
−40 °C to +125 °C
⎯
Package
LQFP-64
2 channels
PGA-299
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 kbps)
A/D converter
1 channel
2 channels
15 channels
24 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs includes sample time (per one channel)
2 channels
4 channels
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function.
16-bit reload timer
I/O Timer 0 corresponds to
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1.
ICU0/1/2/3, OCU0/1/2/3.
I/O Timer 1 (clock input FRCK1) corresponds to
I/O Timer 1 corresponds to
ICU4/5/6/7, OCU4/5/6/7.
ICU4/5/6/7, OCU4/5/6/7.
16-bit I/O timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when it matches Output Compare (ch.0, ch.4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock frequency)
(Continued)
7
MB90350E Series
(Continued)
Part Number
MB90351E,
MB90351TE, MB90351ES, MB90351TES, MB90V340E- MB90V340E-
MB90352TE MB90352ES MB90352TES 101 102
MB90352E
Parameter
4 channels
8 channels
16-bit output
compare
Signals an interrupt when 16-bit I/O Timer matches output compare registers.
A pair of compare registers can be used to generate an output signal.
6 channels
8 channels
16-bit input capture
Retains free-run timer value by (rising edge, falling edge, or the both edges), signals an
interrupt.
8 channels (16-bit)/
16 channels (8-bit)
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 16
8-bit reload counters × 12
8-bit reload registers for
8-bit reload registers for L pulse width × 12
L pulse width × 16
8-bit reload registers for H pulse width × 12
8-bit reload registers for
8/16-bit
programmable pulse
generator
H pulse width × 16
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler + 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
1 channel
3 channels
Compliant with CAN standard Version 2.0 Part A and Part B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
16 prioritized message buffers for data and ID
Supports multiple messages.
CAN interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
16 channels
External interrupt
D/A converter
Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
⎯
2 channels
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
I/O ports
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash memory
⎯
Corresponding
evaluation name
MB90V340E-102
MB90V340E-101
⎯
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
8
MB90350E Series
■ PRODUCT LINEUP 2 (With Clock supervisor function)
• Flash memory products
Part Number
MB90F356E,
MB90F357E
MB90F356TE,
MB90F357TE
MB90F356ES,
MB90F357ES
MB90F356TES,
MB90F357TES
Parameter
Type
Flash memory products
F2MC-16LX CPU
CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
System clock
Dual operation flash memory
ROM
RAM
64 Kbytes : MB90F356E(S), MB90F356TE(S)
128 Kbytes :MB90F357E(S), MB90F357TE(S)
4 Kbytes
Emulator-specific
power supply*1
⎯
No
Sub clock pin
(X0A, X1A)
Yes
(internal CR oscillation can be used as
sub clock)
Clock supervisor
Yes
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter)
3.5 V to 5.5 V : at using A/D converter/Flash programming
3.5 V to 5.5 V : at using external bus
Operating
voltage range
Operating
temperature range
−40 °C to +125 °C
Package
LQFP-64
2 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 kbps)
A/D Converter
1 channel
15 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs includes sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
(4 channels)
Supports External Event Count function.
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock frequency)
4 channels
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
(Continued)
9
MB90350E Series
(Continued)
Part Number
MB90F356E,
MB90F356TE,
MB90F357TE
MB90F356ES,
MB90F357ES
MB90F356TES,
MB90F357TES
MB90F357E
Parameter
6 channels
16-bit Input Capture
Retains free-run timer value by (rising edge, falling edge or rising & falling edge), signals
an interrupt.
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
8/16-bit
ProgrammablePulse
Generator
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler + 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
1 channel
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
CAN Interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External Interrupt
D/A converter
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
⎯
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
I/O Ports
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 times
Flash Memory
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F357x only)
Corresponding EVA
name
MB90V340E-104
MB90V340E-103
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trademark of Advanced Micro Devices Inc.
10
MB90350E Series
• MASK ROM products/Evaluation products
Part Number
MB90356E,
MB90357E
MB90356TE,
MB90357TE
MB90356ES, MB90356TES, MB90V340E- MB90V340E-
MB90357ES MB90357TES
103
104
Parameter
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6)
System clock
MASK ROM
ROM
RAM
64 Kbytes :MB90356E(S), MB90356TE(S)
128 Kbytes :MB90357E(S), MB90357TE(S)
External
4 Kbytes
30 Kbytes
Yes
Emulator-specific
power supply*
⎯
No
No
(internal CR
oscillation
can be used
as sub clock)
Sub clock pin
(X0A, X1A)
Yes
(internal CR oscillation can
be used as sub clock)
Yes
Clock supervisor
Yes
Low voltage/CPU
operation detection
reset
No
Yes
No
Yes
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
Operating
voltage range
5 V 10%
Operating
temperature range
−40 °C to +125 °C
⎯
Package
LQFP-64
2 channels
PGA-299
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 kbps)
A/D Converter
1 channel
2 channels
15 channels
24 channels
10-bit or 8-bit resolution
Conversion time : Min 3 µs includes sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
(4 channels)
Supports External Event Count function.
I/O Timer 0 corresponds to
ICU 0/1/2/3, OCU 0/1/2/3.
I/O Timer 1 corresponds to
ICU 4/5/6/7, OCU 4/5/6/7.
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
I/O Timer 1 (clock input FRCK1) corresponds to
ICU 4/5/6/7, OCU 4/5/6/7.
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock frequency)
(Continued)
11
MB90350E Series
(Continued)
Part Number
MB90356E,
MB90356TE, MB90356ES, MB90356TES, MB90V340E- MB90V340E-
MB90357TE MB90357ES MB90357TES 103 104
MB90357E
Parameter
4 channels
8 channels
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
6 channels
8 channels
16-bit Input Capture
Retains free-run timer value by (rising edge, falling edge or rising & falling edge), signals
an interrupt.
8 channels (16-bit)/
16 channels (8-bit)
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters × 16
8-bit reload counters × 12
8-bit reload registers for
8-bit reload registers for L pulse width × 12
L pulse width × 16
8-bit reload registers for H pulse width × 12
8-bit reload registers for
8/16-bit
ProgrammablePulse
Generator
H pulse width × 16
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler + 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
1 channel
3 channels
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
CAN Interface
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
16 channels
External Interrupt
D/A converter
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
⎯
2 channels
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
I/O Ports
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash Memory
⎯
Corresponding EVA
name
MB90V340E-104
MB90V340E-103
⎯
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
12
MB90350E Series
■ PACKAGES AND PRODUCT CORRESPONDENCE
MB90F351E (S) , MB90F351TE (S)
MB90F352E (S) , MB90F352TE (S)
MB90F356E (S) , MB90F356TE (S)
MB90F357E (S) , MB90F357TE (S)
MB90351E (S) , MB90351TE (S)
MB90352E (S) , MB90352TE (S)
MB90356E (S) , MB90356TE (S)
MB90357E (S) , MB90357TE (S)
MB90V340E-101,
MB90V340E-102,
Package
MB90V340E-103,
MB90V340E-104
PGA-299C-A01
×
FPT-64P-M23
(12.0 mm , 0.65 mm pitch)
×
FPT-64P-M24
(10.0 mm , 0.50 mm pitch)
×
: Yes, × : No
Note : Refer to “■ PACKAGE DIMENSIONS” for detail of each package.
13
MB90350E Series
■ PIN ASSIGNMENTS
• MB90F351E(S), MB90F351TE(S), MB90F352E(S), MB90F352TE(S),MB90F356E(S), MB90F356TE(S),
MB90F357E(S), MB90F357TE(S), MB90351E(S), MB90351TE(S), MB90352E(S), MB90352TE(S),
MB90356E(S), MB90356TE(S), MB90357E(S), MB90357TE(S)
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P10/AD08/TIN1
Vcc
C
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P07/AD07/INT15
P25/A21/IN1/ADTG
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P30/ALE/IN4
P31/RD/IN5
P06/AD06/INT14
P05/AD05/INT13
P04/AD04/INT12
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
MD0
P32/WRL/WR/INT10R
P33/WRH
P34/HRQ/OUT4
P35/HAK/OUT5
P36/RDY/OUT6
P37/CLK/OUT7
P60/AN0
MD1
MD2
P41/X1A*
P40/X0A*
P61/AN1
Vss
AVcc
P43/IN7/TX1
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FPT-64P-M23, FPT-64P-M24)
* : Devices without S-suffix : X0A, X1A
Devices with S-suffix : P40, P41
14
MB90350E Series
■ PIN DESCRIPTION
I/O
Circuit
type*
Pin No.
Pin name
Function
46
47
45
X1
X0
Oscillation output pin
Oscillation input pin
Reset input pin
A
E
RST
P62 to P67
AN2 to AN7
General purpose I/O ports
Analog input pins for A/D converter
3 to 8
I
PPG4 (5) , 6 (7) ,
8 (9) , A (B) ,
C (D) , E (F)
Output pins for PPGs
P50
AN8
General purpose I/O port
9
O
I
Analog input pin for A/D converter
Serial data input pin for UART2
General purpose I/O port
SIN2
P51
10
11
12
AN9
Analog input pin for A/D converter
Serial data output pin for UART2
General purpose I/O port
SOT2
P52
AN10
SCK2
P53
I
Analog input pin for A/D converter
Serial clock I/O pin for UART2
General purpose I/O port
AN11
TIN3
I
Analog input pin for A/D converter
Event input pin for reload timer3
General purpose I/O port
P54
13
AN12
TOT3
P55, P56
AN13, AN14
P42
I
I
Analog input pin for A/D converter
Output pin for reload timer3
General purpose I/O ports
14, 15
Analog input pins for A/D converter
General purpose I/O port
IN6
Data sample input pin for input capture ICU6
RX input pin for CAN1
16
17
F
F
RX1
INT9R
P43
External interrupt request input pin for INT9
General purpose I/O port
IN7
Data sample input pin for input capture ICU7
TX output pin for CAN1
TX1
General purpose I/O ports
(devices with S-suffix and MB90V340E-101/103)
P40, P41
F
B
19, 20
X0A : Oscillation input pins for sub clock
X1A : Oscillation output pins for sub clock
(devices without S-suffix and MB90V340E-102/104)
X0A, X1A
(Continued)
15
MB90350E Series
I/O
Circuit
type*
Pin No.
Pin name
Function
General purpose I/O ports. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P00 to P07
24 to 31
G
G
G
Input/output pins of external address data bus lower 8 bits. This function is
enabled when the external bus is enabled.
AD00 to AD07
INT8 to INT15
P10
External interrupt request input pins for INT8 to INT15
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
32
33
Input/output pin for external bus address data bus bit 8.
This function is enabled when external bus is enabled.
AD08
TIN1
P11
Event input pin for reload timer1
General purpose I/O port. The register can be set to select whether to use a
pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 9. This function is
enabled when external bus is enabled.
AD09
TOT1
P12
Output pin for reload timer1
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 10. This function is
enabled when external bus is enabled.
AD10
34
N
SIN3
Serial data input pin for UART3
INT11R
External interrupt request input pin for INT11
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P13
35
36
G
G
Input/output pin for external bus address data bus bit 11.
This function is enabled when external bus is enabled.
AD11
SOT3
P14
Serial data output pin for UART3
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 12.
This function is enabled when external bus is enabled.
AD12
SCK3
P15
Clock input/output pin for UART3
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
37
38
N
G
Input/output pin for external bus address data bus bit 13.
This function is enabled when external bus is enabled.
AD13
P16
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 14.
This function is enabled when external bus is enabled.
AD14
(Continued)
16
MB90350E Series
I/O
Circuit
type*
Pin No.
Pin name
Function
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P17
39
G
Input/output pin for external bus address data bus bit 15.
This function is enabled when external bus is enabled.
AD15
General purpose I/O ports. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pins are enabled as a general-
purpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
P20 to P23
Output pins for A16 to A19 of the external address data bus.
40 to 43
A16 to A19
G
When the corresponding bit in the external address output control register
(HACR) is 0, the pins are enabled as high address output pins A16 to A19.
PPG9 (8) ,
PPGB (A) ,
PPGD (C) ,
PPGF (E)
Output pins for PPGs
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a general-
purpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
P24
44
G
Output pin for A20 of the external address data bus. When the correspond-
ing bit in the external address output control register (HACR) is 0, the pin is
enabled as high address output pin A20.
A20
IN0
Data sample input pin for input capture ICU0
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a general-
purpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
P25
Output pin for A21 of the external address data bus. When the correspond-
ing bit in the external address output control register (HACR) is 0, the pin is
enabled as high address output pin A21.
51
G
A21
IN1
ADTG
P44
Data sample input pin for input capture ICU1
Trigger input pin for A/D converter
General purpose I/O port
52
53
SDA0
FRCK0
P45
H
H
Serial data I/O pin for I2C 0
Input pin for the 16-bit I/O Timer 0
General purpose I/O port
Serial clock I/O pin for I2C 0
SCL0
FRCK1
Input pin for the 16-bit I/O Timer 1
(Continued)
17
MB90350E Series
I/O
Circuit
type*
Pin No.
Pin name
Function
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P30
54
G
G
Address latch enable output pin. This function is enabled when external bus
is enabled.
ALE
IN4
Data sample input pin for input capture ICU4
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
P31
55
56
Read strobe output pin for data bus. This function is enabled when external
bus is enabled.
RD
IN5
Data sample input pin for input capture ICU5
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the WR/WRL pin output disabled.
P32
Write strobe output pin for the data bus. This function is enabled when both
the external bus and the WR/WRL pin output are enabled. WRL is used to
write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to
write-strobe 8 bits of the data bus in 8-bit access.
G
WR/WRL
INT10R
P33
External interrupt request input pin for INT10
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode, in
external bus 8-bit mode or with the WRH pin output disabled.
57
58
G
G
Write strobe output pin for the 8 higher bits of the data bus. This function is
enabled when the external bus is enabled, when the external bus 16-bit
mode is selected, and when the WRH output pin is enabled.
WRH
P34
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.
Hold request input pin. This function is enabled when both the external bus
and the hold function are enabled.
HRQ
OUT4
Wave form output pin for output compare OCU4
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.
P35
59
60
G
G
Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.
HAK
OUT5
Wave form output pin for output compare OCU5
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the external ready function disabled.
P36
Ready input pin. This function is enabled when both the external bus and
the external ready function are enabled.
RDY
OUT6
Wave form output pin for output compare OCU6
(Continued)
18
MB90350E Series
(Continued)
I/O
Circuit
type*
Pin No.
Pin name
Function
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the CLK output disabled.
P37
CLK
61
G
CLK output pin. This function is enabled when both the external bus and
CLK output are enabled.
OUT7
P60, P61
AN0, AN1
AVCC
Wave form output pin for output compare OCU7
General purpose I/O ports
62, 63
64
I
Analog input pins for A/D converter
VCC power input pin for analog circuits
K
Reference voltage input for the A/D converter. This power supply must be
turned on or off while a voltage higher than or equal to AVRH is applied to
AVCC.
2
AVRH
L
1
AVSS
MD1, MD0
MD2
K
C
VSS power input pin for analog circuits
Input pins for specifying the operating mode
Input pin for specifying the operating mode
Power (3.5 V to 5.5 V) input pin
22, 23
21
D
49
VCC
⎯
⎯
18, 48
VSS
Power (0 V) input pins
This is the power supply stabilization capacitor pin. It should be connected
to a higher than or equal to 0.1 µF ceramic capacitor.
50
C
K
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
19
MB90350E Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 MΩ
X1
X0
Xout
A
Standby control signal
Xout
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 MΩ
X1A
X0A
B
C
Standby control signal
CMOS
• MASK ROM device
CMOS hysteresis input pin
• Flash memory device
CMOS input pin
R
hysteresis
inputs
• MASK ROM device
CMOS hysteresis input pin
Pull-down resistor value: approx. 50 kΩ
• Flash memory device
CMOS input pin
R
CMOS
hysteresis
inputs
D
Pull-down
resistor
No Pull-down
CMOS hysteresis input pin
Pull-up resistor value: approx. 50 kΩ
Pull-up
resistor
E
R
CMOS
hysteresis
inputs
(Continued)
20
MB90350E Series
Type
Circuit
Remarks
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With input
shutdown function when is standby)
• Automotive input (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
Nout
R
F
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
Pull-up control
Pout
Pull-up
resistor
• CMOS hysteresis inputs (With the stand-
by-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
P-ch
P-ch
N-ch
Nout
R
G
• Programmable pull-up resistor:
approx. 50 kΩ
CMOS
hysteresis inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• CMOS level output
(IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis inputs (With the stand-
by-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
Nout
H
R
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
21
MB90350E Series
Type
Circuit
Remarks
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the stand-
by-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
Nout
R
• Analog input for A/D converter
I
CMOS
hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
Protection circuit for power supply input
P-ch
N-ch
K
• With the protection circuit of A/D
converter reference voltage power
input pin
• Flash memory devices do not have a
protection circuit against VCC for pin
AVRH.
ANE
AVR
P-ch
N-ch
L
ANE
(Continued)
22
MB90350E Series
(Continued)
Type
Circuit
Remarks
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
Pull-up control
Pull-up
resistor
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
P-ch
N-ch
P-ch
Pout
Nout
R
N
• Programmable pull-up resistor:
approx. 50 kΩ
CMOS inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• CMOS level output
(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
P-ch
N-ch
Pout
• Automotive input (With the standby-time
input shutdown function)
• Analog input for A/D converter
Nout
R
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
23
MB90350E Series
■ HANDLING DEVICES
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage (VCC) .
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ.
Unused I/O pins should be set to the output state and can be left open, or the input state with the above described
connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90350E Series
X0
Open
X1
4. Precautions for when not using a sub clock signal
X0A and X1A are oscillation pins for sub clock. If you do not connect pins X0A and X1A to an oscillator, use
pull-down handling on the X0A pin, and leave the X1A pin open.
5. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
24
MB90350E Series
6. Treatment of Power Supply Pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected inside of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
Connect VCC and VSS pins to the device from the current supply source at a possibly low impedance.
• As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 µF as a
bypass capacitor between VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90350E
Series
Vcc
Vss
Vcc
Vss
7. Pull-up/down resistors
The MB90350E series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
8. Crystal oscillator circuit
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable
operation it is strongly recommended that printed circuit artwork places ground bypass capacitors as close as
possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross
the lines of other circuits.
Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.
9. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after
turning-on the digital power supply (VCC) .Turn-off the digital power after turning off the A/D converter power
supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/
off the analog and digital power supplies simultaneously is acceptable).
10. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
11. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V) .
25
MB90350E Series
12. Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified
power supply voltage VCC operating range. Therefore, the power supply voltage VCC should be stabilized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value)
at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard power supply voltage VCC and the
coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these
registers, turn on the power again.
14. Port 0 to port 3 output during power-on (External-bus mode)
As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable regardless of reset inputs.
1/2 VCC
VCC
Port 0 to Port 3
Port 0 to Port 3 outputs Port 0 to Port 3 outputs = Hi-Z
might be unstable.
15. Setting using CAN function
To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR).
If DIRECT bit is set to “0” (initial value), wait states will be performed when accessing CAN registers.
Note : Please refer to section “23.12 CAN Direct Mode Register” in Hardware Manual of MB90350E series for detail
of CAN direct mode register.
16. Flash security function
The security byte is located in the area of the Flash memory. If protection code 01H is written in the security byte,
the Flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security byte.
Product name
MB90F352E(S)
Flash memory size
Address for security bit
MB90F352TE(S)
MB90F357E(S)
MB90F357TE(S)
Embedded 1 Mbit Flash memory
FE0001H
17. Operation with TA = +105 °C or more
If used exceeding TA = +105 °C, please contact Fujitsu sales representatives for reliability limitations.
26
MB90350E Series
18. Low voltage/CPU operation reset circuit
The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when
a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal
is generated.
The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates
an internal reset signal if not cleared within a given time after startup.
(1) Low voltage detection reset circuit
Detection voltage
4.0 V 0.3 V
When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an
internal reset signal is output.
Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage
condition generates an internal reset and releases stop mode.
During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the
output of this internal reset, the reset output from the low voltage detection reset circuit is suppressed.
(2) CPU operation detection reset circuit
The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts
automatically after a power-on reset, and must be continually and regularly cleared within a given time. If the
given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is
assumedandaninternalresetsignalisgenerated. TheinternalresetgeneratedfromtheCPUoperationdetection
circuit has a width of 5 machine cycles.
Interval time
220/FC (approx. 262 ms*)
* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.
During recovery from standby mode, the detection period is the maximum interval plus 20 µs.
This circuit does not operate in modes where CPU operation is stopped.
The CPU operation detection reset circuit counter is cleared under any of the following conditions.
• “0” writing to CL bit of LVRC register
• Internal reset
• Main oscillation clock stop
• Transit to sleep mode
• Transit to timebase timer mode and watch mode
19. Internal CR oscillation circuit
Value
Parameter
Symbol
Unit
Min
Typ
Max
Oscillation frequency
fRC
50
100
200
kHz
Oscillation stabilization
wait time
tstab
⎯
⎯
100
µs
27
MB90350E Series
■ BLOCK DIAGRAMS
• MB90V340E-101/102
X0
X0A*
Clock
controller
F2MC-16LX
CPU
RST
X1
X1A*
RAM
30 Kbytes
FRCK0
I/O Timer 0
Input
Capture
IN7 to IN0
8 channels
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
5 channels
I/O Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 channels
UART
5 channels
RX2 to RX0
TX2 to TX0
16-bit
Reload Timer
4 channels
AVCC
AVSS
TIN3 to TIN0
8/10-bit
A/D
Converter
24 channels
TOT3 to TOT0
AN23 to AN0
AVRH
AD15 to AD00
A21 to A16
ALE
AVRL
ADTG
10-bit
D/A
Converter
2 channels
RD
External
Bus
Interface
WR/WRL
WRH
DA00,DA01
HRQ
HAK
8/16-bit
PPG
PPGF to PPG0
RDY
16 channels
CLK
SDA0,SDA1
SCL0,SCL1
I2C interface
2 channels
INT7 to INT0
DTP/
External
Interrupt
INT15 to INT8
(INT11R to INT9R)
DMAC
Clock
CKOT
Monitor
* : MB90V340E-102 only
28
MB90350E Series
• MB90V340E-103/104
X0
X0A*
RST
X1
X1A*
Clock
controller/
Monitor
F2MC-16LX
CPU
I/O Timer 0
FRCK0
CRoscillation
circuit
Input
Capture
IN7 to IN0
8 channels
RAM
30 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
5 channels
I/O Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 channels
UART
5 channels
RX2 to RX0
TX2 to TX0
16-bit
Reload
AVCC
AVSS
AN23 to AN0
AVRH
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
A/D
Converter
24 channels
Timer
4 channels
AVRL
ADTG
AD15 to AD00
A23 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
10-bit
D/A
Converter
2 channels
External
Bus
Interface
DA01, DA00
8/16-bit
PPG
16 channels
PPGF to PPG0
CLK
I2C interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/External
Interrupt
DMA
Clock
Monitor
CKOT
* : MB90V340E-104 only
29
MB90350E Series
• MB90F352E (S) , MB90F352TE (S) , MB90F351E (S) , MB90F351TE (S) , MB90352E (S) ,
MB90352TE (S) , MB90351E (S) , MB90351TE (S)
X0
X0A *1
Clock
controller
F2MC-16LX
CPU
RST
X1
X1A*1
Low voltage/
CPU operation
detection
FRCK0
I/O Timer 0
reset*2
Input
Capture
6 channels
RAM
4 Kbytes
IN7 to IN4,
IN1, IN0
ROM/Flash
128 Kbytes/
64 Kbytes
Output
Compare
4 channels
OUT7 to OUT4
FRCK1
Prescaler
2 channels
I/O Timer 1
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
CAN
Controller
1 channel
UART
2 channels
RX1
TX1
16-bit
ReloadTimer
2 channels
AVCC
AVSS
TIN3, TIN1
8/10-bit
A/D
TOT3, TOT1
AN14 to AN0
Converter
15 channels
AVRH
ADTG
AD15 to AD00
A21 to A16
ALE
RD
External
Bus
Interface
WR/WRL
WRH
HRQ
8/16-bit
PPG
PPGF to PPG8
PPG6, PPG4
HAK
RDY
CLK
10/6 channels
SDA0
SCL0
I2C interface
1 channel
DTP/
INT15 to INT8
External
Interrupt
(INT11R to INT9R)
DMAC
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
30
MB90350E Series
• MB90F357E (S) , MB90F357TE (S) , MB90F356E (S) , MB90F356TE (S) , MB90357E (S) , MB90357TE (S) ,
MB90356E (S) , MB90356TE (S)
X0
Clock
controller/
Monitor
X0A*1
RST
X1
F2MC-16LX
CPU
X1A*1
CR
oscillation
circuit
FRCK0
I/O Timer 0
Input
Capture
6 channels
Low voltage/
CPU operation
detector reset*2
IN7 to IN4,
IN1, IN0
Output
Compare
4 channels
OUT7 to OUT4
FRCK1
RAM
4 Kbytes
I/O Timer 1
ROM/Flash
128 Kbytes/
64 Kbytes
CAN
Controller
1 channel
RX1
TX1
Prescaler
2 channels
16-bit
Reload Timer
4 channels
TIN3, TIN1
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
UART
2 channels
TOT3, TOT1
AVCC
AVSS
AD15 to AD00
A21 to A16
ALE
8/10-bit
A/D
AN14 to AN0
Converter
15 channels
RD
External
Bus
Interface
AVRH
ADTG
WR/WRL
WRH
HRQ
HAK
8/16-bit
PPG
10/6 channels
PPGF to PPG8
PPG6, PPG4
RDY
CLK
SDA0
SCL0
I2C interface
1 channel
External
Interrupt
INT15 to INT8
(INT11R to INT9R)
DMAC
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
31
MB90350E Series
■ MEMORY MAP
MB90352E (S)
MB90352TE (S)
MB90F352E (S)
MB90F352TE (S)
MB90357E (S)
MB90357TE (S)
MB90F357E (S)
MB90F357TE (S)
MB90351E (S)
MB90351TE (S)
MB90F351E (S)
MB90F351TE (S)
MB90356E (S)
MB90356TE (S)
MB90F356E (S)
MB90F356TE (S)
MB90V340E-101
MB90V340E-102
MB90V340E-103
MB90V340E-104
FFFFFFH
FF0000H
FFFFFFH
FFFFFFH
ROM (FF bank)
ROM (FF bank)
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
ROM (FE bank)
FE0000H
FDFFFFH
FE0000H
FDFFFFH
ROM (FD bank)
FDFFFFH
FD0000H
FCFFFFH
ROM (FC bank)
External access
area
External access
area
FC0000H
FBFFFFH
ROM (FB bank)
FB0000H
FAFFFFH
C00100H
00FFFFH
C00100H
00FFFFH
ROM (FA bank)
FA0000H
F9FFFFH
ROM (F9 bank)
F90000H
F8FFFFH
ROM
(image of FF bank)
ROM
(image of FF bank)
ROM (F8 bank)
External access area
F80000H
008000H
007FFFH
008000H
007FFFH
00FFFFH
ROM
(image of FF bank)
Peripheral
Peripheral
008000H
007FFFH
007900H
007900H
Peripheral
007900H
0078FFH
RAM 30 Kbytes
001100H
0010FFH
001100H
0010FFH
RAM 4 Kbytes
External access area
Peripheral
RAM 4 Kbytes
000100H
000100H
000100H
External access area
External access area
0000EFH
000000H
0000EFH
000000H
0000EFH
000000H
Peripheral
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H practically accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
32
MB90350E Series
■ I/O MAP
Address
Register
Abbreviation Access
Resource name
Port 0
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
000000H Port 0 Data Register
000001H Port 1 Data Register
000002H Port 2 Data Register
000003H Port 3 Data Register
000004H Port 4 Data Register
000005H Port 5 Data Register
000006H Port 6 Data Register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
000007H
to
Reserved
00000AH
00000BH Port 5 Analog Input Enable Register
00000CH Port 6 Analog Input Enable Register
00000DH
ADER5
ADER6
R/W
R/W
Port 5, A/D
Port 6, A/D
11111111B
11111111B
Reserved
00000EH Input Level Select Register 0
00000FH Input Level Select Register 1
000010H Port 0 Direction Register
000011H Port 1 Direction Register
000012H Port 2 Direction Register
000013H Port 3 Direction Register
000014H Port 4 Direction Register
000015H Port 5 Direction Register
000016H Port 6 Direction Register
ILSR0
ILSR1
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Ports
Ports
00000000B
00000000B
00000000B
00000000B
XX000000B
00000000B
XX000000B
X0000000B
00000000B
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
000017H
to
Reserved
000019H
00001AH SIN input Level Setting Register
00001BH
DDRA
Reserved
W
UART2, UART3
X00XXXXXB
00001CH Port 0 Pull-up Control Register
00001DH Port 1 Pull-up Control Register
00001EH Port 2 Pull-up Control Register
00001FH Port 3 Pull-up Control Register
PUCR0
PUCR1
PUCR2
PUCR3
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
00000000B
00000000B
00000000B
00000000B
000020H
to
Reserved
000037H
(Continued)
33
MB90350E Series
Address
Register
Abbreviation Access
Resource name
Initial value
0X000XX1B
0X000001B
000000X0B
000038H PPG 4 Operation Mode Control Register
000039H PPG 5 Operation Mode Control Register
00003AH PPG 4/5 Count Clock Select Register
PPGC4
PPGC5
PPG45
W, R/W
W, R/W
R/W
16-bit Programmable
Pulse Generator 4/5
Address Match
Detection 1
00003BH Address Detect Control Register 1
PACSR1
R/W
00000000B
00003CH PPG 6 Operation Mode Control Register
00003DH PPG 7 Operation Mode Control Register
00003EH PPG 6/7 Count Clock Select Register
00003FH
PPGC6
PPGC7
PPG67
W, R/W
W, R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator 6/7
Reserved
000040H PPG 8 Operation Mode Control Register
000041H PPG 9 Operation Mode Control Register
000042H PPG 8/9 Count Clock Select Register
000043H
PPGC8
PPGC9
PPG89
W, R/W
W, R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator 8/9
Reserved
PPGCA
PPGCB
PPGAB
Reserved
PPGCC
PPGCD
PPGCD
Reserved
PPGCE
PPGCF
PPGEF
Reserved
000044H PPG A Operation Mode Control Register
000045H PPG B Operation Mode Control Register
000046H PPG A/B Count Clock Select Register
000047H
W, R/W
W, R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator A/B
000048H PPG C Operation Mode Control Register
000049H PPG D Operation Mode Control Register
00004AH PPG C/D Count Clock Select Register
00004BH
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator C/D
00004CH PPG E Operation Mode Control Register
00004DH PPG F Operation Mode Control Register
00004EH PPG E/F Count Clock Select Register
00004FH
W,R/W
W,R/W
R/W
0X000XX1B
0X000001B
000000X0B
16-bit Programmable
Pulse Generator E/F
Input Capture Control Status
Register 0/1
000050H
ICS01
R/W
00000000B
Input Capture 0/1
000051H Input Capture Edge Register 0/1
ICE01
R/W, R
XXX0X0XXB
000052H,
000053H
Reserved
Input Capture Control Status
Register 4/5
000054H
ICS45
ICE45
ICS67
ICE67
R/W
R
00000000B
XXXXXXXXB
00000000B
Input Capture 4/5
Input Capture 6/7
000055H Input Capture Edge Register 4/5
Input Capture Control Status
Register 6/7
000056H
R/W
R/W, R
000057H Input Capture Edge Register 6/7
XXX000XXB
(Continued)
34
MB90350E Series
Address
Register
Abbreviation Access
Resource name
Initial value
000058H
to
Reserved
00005BH
Output Compare Control Status
Register 4
00005CH
00005DH
00005EH
00005FH
OCS4
OCS5
OCS6
OCS7
R/W
R/W
R/W
R/W
0000XX00B
0XX00000B
0000XX00B
0XX00000B
Output Compare 4/5
Output Compare 6/7
Output Compare Control Status
Register 5
Output Compare Control Status
Register 6
Output Compare Control Status
Register 7
000060H Timer Control Status Register 0
000061H Timer Control Status Register 0
000062H Timer Control Status Register 1
000063H Timer Control Status Register 1
000064H Timer Control Status Register 2
000065H Timer Control Status Register 2
000066H Timer Control Status Register 3
000067H Timer Control Status Register 3
000068H A/D Control Status Register 0
000069H A/D Control Status Register 1
00006AH A/D Data Register 0
TMCSR0
TMCSR0
TMCSR1
TMCSR1
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
ADCS1
ADCR0
A/D Converter
00006BH A/D Data Register 1
ADCR1
R
00006CH ADC Setting Register 0
ADSR0
R/W
R/W
00006DH ADC Setting Register 1
ADSR1
Low Voltage/CPU
R/W, W Operation Detection
Reset
Low Voltage/CPU Operation Detection
00006EH
LVRC
00111000B
Reset Control Register
00006FH ROM Mirror Function Select Register
ROMM
W
ROM Mirror
XXXXXXX1B
000070H
to
Reserved
00007FH
000080H
to
Reserved for CAN controller 1. Refer to “■ CAN CONTROLLERS”
00008FH
000090H
to
Reserved
00009AH
(Continued)
35
MB90350E Series
Address
Register
Abbreviation Access Resource name Initial value
DMA Descriptor Channel Specification
Register
00009BH
DCSR
R/W
00000000B
DMA
00009CH DMA Status Register L Register
00009DH DMA Status Register H Register
DSRL
DSRH
R/W
R/W
00000000B
00000000B
Address Match
Detection 0
00009EH Address Detect Control Register 0
00009FH Delayed Interrupt/Release Register
PACSR0
DIRR
R/W
R/W
00000000B
Delayed Interrupt XXXXXXX0B
Low Power
Consumption
Control Circuit
Low-power Consumption Mode
0000A0H
LPMCR
CKSCR
W,R/W
R,R/W
00011000B
Control Register
Low Power
Consumption
Control Circuit
0000A1H Clock Selection Register
11111100B
0000A2H,
0000A3H
Reserved
DSSR
0000A4H DMA Stop Status Register
R/W
W
DMA
00000000B
0011XX00B
Automatic Ready Function Selection
0000A5H
Register
ARSR
External Memory
Access
0000A6H External Address Output Control Register
0000A7H Bus Control Signal Selection Register
0000A8H Watchdog Control Register
0000A9H Timebase Timer Control Register
0000AAH Watch Timer Control Register
0000ABH
HACR
ECSR
WDTC
TBTC
W
W
00000000B
0000000XB
R,W
Watchdog Timer XXXXX111B
W,R/W Timebase timer 1XX00100B
WTC
R,R/W
Watch Timer
1X001000B
Reserved
DERL
0000ACH DMA Enable Register L Register
0000ADH DMA Enable Register H Register
R/W
R/W
00000000B
00000000B
DMA
DERH
Flash Control Status Register
0000AEH (Flash Devices only. Otherwise
reserved)
FMCS
R,R/W
Flash memory
000X0000B
0000AFH
Reserved
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
0000B0H Interrupt Control Register 00
0000B1H Interrupt Control Register 01
0000B2H Interrupt Control Register 02
0000B3H Interrupt Control Register 03
0000B4H Interrupt Control Register 04
0000B5H Interrupt Control Register 05
0000B6H Interrupt Control Register 06
0000B7H Interrupt Control Register 07
0000B8H Interrupt Control Register 08
W,R/W
W,R/W
W,R/W
W,R/W
00000111B
00000111B
00000111B
00000111B
W,R/W Interrupt Control 00000111B
W,R/W
W,R/W
W,R/W
W,R/W
00000111B
00000111B
00000111B
00000111B
(Continued)
36
MB90350E Series
Address
Register
Abbreviation Access Resource name Initial value
0000B9H Interrupt Control Register 09
0000BAH Interrupt Control Register 10
0000BBH Interrupt Control Register 11
0000BCH Interrupt Control Register 12
0000BDH Interrupt Control Register 13
0000BEH Interrupt Control Register 14
0000BFH Interrupt Control Register 15
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
W,R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
Interrupt Control
0000C0H
to
Reserved
0000C9H
0000CAH External Interrupt Enable Register 1
0000CBH External Interrupt Source Register 1
0000CCH External Interrupt Level Register 1
0000CDH External Interrupt Level Register 1
ENIR1
EIRR1
ELVR1
ELVR1
R/W
R/W
R/W
R/W
00000000B
XXXXXXXXB
00000000B
00000000B
External Interrupt 1
External Interrupt Source Select
0000CEH
Register
EISSR
PSCCR
BAPL
R/W
W
00000000B
XXXX0000B
XXXXXXXXB
0000CFH PLL/Sub clock Control register
PLL
DMA Buffer Address Pointer L
0000D0H
Register
R/W
DMA Buffer Address Pointer M
0000D1H
Register
BAPM
R/W
XXXXXXXXB
DMA Buffer Address Pointer H
0000D2H
Register
BAPH
DMACS
IOAL
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0000D3H DMA Control Register
DMA
I/O Register Address Pointer L
0000D4H
Register
I/O Register Address Pointer H
0000D5H
Register
IOAH
R/W
XXXXXXXXB
0000D6H Data Counter L Register
0000D7H Data Counter H Register
0000D8H Serial Mode Register 2
0000D9H Serial Control Register 2
DCTL
DCTH
SMR2
SCR2
R/W
R/W
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
W,R/W
W,R/W
Reception/Transmission Data
Register 2
0000DAH
RDR2/TDR2
SSR2
R/W
00000000B
00001000B
000000XXB
00000100B
0000DBH Serial Status Register 2
R,R/W
UART2
Extended Communication Control
Register 2
R,W,
R/W
0000DCH
ECCR2
0000DDH Extended Status/Control Register 2
0000DEH Baud Rate Generator Register 20
ESCR2
BGR20
R/W
R/W
00000000B
(Continued)
37
MB90350E Series
Address
Register
Abbreviation Access
Resource name
Initial value
0000DFH Baud Rate Generator Register 21
BGR21
R/W
UART2
00000000B
0000E0H
to
Reserved
0000EFH
0000F0H
to
0000FFH
External area
Reserved
007900H
to
007907H
007908H Reload Register L4
007909H Reload Register H4
00790AH Reload Register L5
00790BH Reload Register H5
00790CH Reload Register L6
00790DH Reload Register H6
00790EH Reload Register L7
00790FH Reload Register H7
007910H Reload Register L8
007911H Reload Register H8
007912H Reload Register L9
007913H Reload Register H9
007914H Reload Register LA
007915H Reload Register HA
007916H Reload Register LB
007917H Reload Register HB
007918H Reload Register LC
007919H Reload Register HC
00791AH Reload Register LD
00791BH Reload Register HD
00791CH Reload Register LE
00791DH Reload Register HE
00791EH Reload Register LF
00791FH Reload Register HF
007920H Input Capture Register 0
007921H Input Capture Register 0
007922H Input Capture Register 1
007923H Input Capture Register 1
PRLL4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bitProgrammable
Pulse
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
Generator 4/5
16-bitProgrammable
Pulse
Generator 6/7
16-bitProgrammable
Pulse
Generator 8/9
16-bitProgrammable
Pulse
Generator A/B
16-bitProgrammable
Pulse
Generator C/D
16-bitProgrammable
Pulse
Generator E/F
R
Input Capture 0/1
R
R
XXXXXXXXB
(Continued)
38
MB90350E Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
007924H
to
Reserved
007927H
007928H Input Capture Register 4
007929H Input Capture Register 4
00792AH Input Capture Register 5
00792BH Input Capture Register 5
00792CH Input Capture Register 6
00792DH Input Capture Register 6
00792EH Input Capture Register 7
00792FH Input Capture Register 7
IPCP4
IPCP4
IPCP5
IPCP5
IPCP6
IPCP6
IPCP7
IPCP7
R
R
R
R
R
R
R
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input Capture 4/5
Input Capture 6/7
007930H
to
Reserved
007937H
007938H Output Compare Register 4
007939H Output Compare Register 4
00793AH Output Compare Register 5
00793BH Output Compare Register 5
00793CH Output Compare Register 6
00793DH Output Compare Register 6
00793EH Output Compare Register 7
00793FH Output Compare Register 7
007940H Timer Data Register 0
OCCP4
OCCP4
OCCP5
OCCP5
OCCP6
OCCP6
OCCP7
OCCP7
TCDT0
TCDT0
TCCSL0
TCCSH0
TCDT1
TCDT1
TCCSL1
TCCSH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
Output Compare 4/5
Output Compare 6/7
I/O Timer 0
007941H Timer Data Register 0
00000000B
007942H Timer Control Status Register 0
007943H Timer Control Status Register 0
007944H Timer Data Register 1
00000000B
0XXXXXXXB
00000000B
007945H Timer Data Register 1
00000000B
I/O Timer 1
007946H Timer Control Status Register 1
007947H Timer Control Status Register 1
00000000B
0XXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
007948H
TMR0/
TMRLR0
16-bit Reload
Timer 0
Timer Register 0/Reload Register 0
007949H
00794AH
TMR1/
TMRLR1
16-bit Reload
Timer 1
Timer Register 1/Reload Register 1
00794BH
00794CH
TMR2/
TMRLR2
16-bit Reload
Timer 2
Timer Register 2/Reload Register 2
00794DH
00794EH
TMR3/
TMRLR3
16-bit Reload
Timer 3
Timer Register 3/Reload Register 3
00794FH
39
MB90350E Series
Address
Register
Abbreviation Access
Resource name
Initial value
00000000B
00000000B
007950H Serial Mode Register 3
007951H Serial Control Register 3
SMR3
SCR3
W, R/W
W, R/W
Reception/Transmission Data
Register 3
007952H
RDR3/TDR3
SSR3
R/W
00000000B
00001000B
000000XXB
007953H Serial Status Register 3
R,R/W
UART3
Extended Communication Control
Register 3
R,W,
R/W
007954H
ECCR3
007955H Extended Status Control Register 3
007956H Baud Rate Generator Register 30
007957H Baud Rate Generator Register 31
ESCR3
BGR30
BGR31
R/W
R/W
R/W
00000100B
00000000B
00000000B
007958H,
007959H
Reserved
CSVCR
007960H Clock supervisor Control Register
R, R/W
Clock supervisor
CAN Clock Sync
00011100B
007961H
to
Reserved
00796DH
00796EH CAN Direct Mode Register
00796FH
007970H I2C Bus Status Register 0
007971H I2C Bus Control Register 0
CDMR
Reserved
IBSR0
R/W
XXXXXXX0B
R
W,R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
11111111B
00111111B
00000000B
01111111B
00000000B
IBCR0
007972H
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
I2C 10-bit Slave Address Register 0
007973H
007974H
I2C Interface 0
I2C 10-bit Slave Address Mask
Register 0
007975H
007976H I2C 7-bit Slave Address Register 0
007977H I2C 7-bit Slave Address Mask Register 0
007978H I2C data register 0
ISMK0
IDAR0
007979H,
00797AH
Reserved
ICCR0
00797BH I2C Clock Control Register 0
R/W
I2C Interface 0
00011111B
00797CH
to
Reserved
0079A1H
0079A2H Flash Write Control Register 0
0079A3H Flash Write Control Register 1
0079A4H Sector Change Setting Register 0
FWR0
FWR1
SSR0
R/W
R/W
R/W
00000000B
00000000B
00XXXXX0B
Dual Operation
Flash
0079A5H
to
Reserved
0079C1H
0079C2H
Setting Prohibited
(Continued)
40
MB90350E Series
(Continued)
Address
Register
Abbreviation Access
Resource name
Initial value
0079C3H
to
Reserved
0079DFH
0079E0H Detect Address Setting Register 0
0079E1H Detect Address Setting Register 0
0079E2H Detect Address Setting Register 0
0079E3H Detect Address Setting Register 1
0079E4H Detect Address Setting Register 1
0079E5H Detect Address Setting Register 1
0079E6H Detect Address Setting Register 2
0079E7H Detect Address Setting Register 2
0079E8H Detect Address Setting Register 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
0079E9H
to
Reserved
0079EFH
0079F0H Detect Address Setting Register 3
0079F1H Detect Address Setting Register 3
0079F2H Detect Address Setting Register 3
0079F3H Detect Address Setting Register 4
0079F4H Detect Address Setting Register 4
0079F5H Detect Address Setting Register 4
0079F6H Detect Address Setting Register 5
0079F7H Detect Address Setting Register 5
0079F8H Detect Address Setting Register 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
Reserved
007BFFH
007C00H
to
Reserved for CAN controller 1. Refer to “■ CAN CONTROLLERS”
007DFFH
007E00H
to
Reserved
007FFFH
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results reading unknown value.
41
MB90350E Series
■ CAN CONTROLLERS
• Compliant with CAN standard Version2.0 Part A and Part B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers
Address
Register
Abbreviation
BVALR
TREQR
TCANR
TCR
Access
R/W
R/W
W
Initial Value
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
00000000B
00000000B
Message buffer enable register
Transmit request register
Transmit cancel register
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Transmission complete register
Receive complete register
Remote request receiving register
Receive overrun register
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
RCR
00000000B
00000000B
RRTRR
ROVRR
RIER
00000000B
00000000B
Reception interrupt
enable register
00000000B
00000000B
(Continued)
42
MB90350E Series
(Continued)
Address
Register
Abbreviation
CSR
Access
Initial Value
CAN1
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007D0DH
007D0EH
007D0FH
007D10H
007D11H
007D12H
007D13H
007D14H
007D15H
007D16H
007D17H
007D18H
007D19H
007D1AH
007D1BH
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
Control status register
Last event indicator register
Receive/transmit error counter
Bit timing register
000X0000B
XXXXXXXXB
LEIR
R/W
R
00000000B
00000000B
RTEC
BTR
11111111B
X1111111B
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
IDE register
IDER
00000000B
00000000B
Transmit RTR register
TRTRR
RFWTR
TIER
Remote frame receive waiting
register
XXXXXXXXB
XXXXXXXXB
Transmit interrupt
enable register
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
Acceptance mask
select register
AMSR
AMR0
AMR1
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance mask register 0
Acceptance mask register 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
43
MB90350E Series
List of Message Buffers (ID Registers)
Address
CAN1
Register
Abbreviation
Access
Initial Value
007C00H
to
007C1FH
XXXXXXXXB
to
XXXXXXXXB
General-purpose RAM
⎯
R/W
007C20H
007C21H
007C22H
007C23H
007C24H
007C25H
007C26H
007C27H
007C28H
007C29H
007C2AH
007C2BH
007C2CH
007C2DH
007C2EH
007C2FH
007C30H
007C31H
007C32H
007C33H
007C34H
007C35H
007C36H
007C37H
007C38H
007C39H
007C3AH
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
XXXXXXXXB
XXXXXXXXB
ID register 0
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
ID register 7
IDR0
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
44
MB90350E Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
CAN1
007C40H
007C41H
007C42H
007C43H
007C44H
007C45H
007C46H
007C47H
007C48H
007C49H
007C4AH
007C4BH
007C4CH
007C4DH
007C4EH
007C4FH
007C50H
007C51H
007C52H
007C53H
007C54H
007C55H
007C56H
007C57H
007C58H
007C59H
007C5AH
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
XXXXXXXXB
XXXXXXXXB
ID register 8
IDR8
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 9
ID register 10
ID register 11
ID register 12
ID register 13
ID register 14
ID register 15
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
45
MB90350E Series
List of Message Buffers (DLC Registers and Data Registers)
Address
CAN1
Register
Abbreviation
DLCR0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
(Continued)
46
MB90350E Series
Address
CAN1
Register
Abbreviation
Access
Initial Value
007C80H
to
007C87H
XXXXXXXXB
to
XXXXXXXXB
Data register 0
(8 bytes)
DTR0
R/W
007C88H
to
007C8FH
XXXXXXXXB
to
XXXXXXXXB
Data register 1
(8 bytes)
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
007C90H
to
007C97H
XXXXXXXXB
to
XXXXXXXXB
Data register 2
(8 bytes)
007C98H
to
007C9FH
XXXXXXXXB
to
XXXXXXXXB
Data register 3
(8 bytes)
007CA0H
to
007CA7H
XXXXXXXXB
to
XXXXXXXXB
Data register 4
(8 bytes)
007CA8H
to
007CAFH
XXXXXXXXB
to
XXXXXXXXB
Data register 5
(8 bytes)
007CB0H
to
007CB7H
XXXXXXXXB
to
XXXXXXXXB
Data register 6
(8 bytes)
007CB8H
to
007CBFH
XXXXXXXXB
to
XXXXXXXXB
Data register 7
(8 bytes)
007CC0H
to
007CC7H
XXXXXXXXB
to
XXXXXXXXB
Data register 8
(8 bytes)
007CC8H
to
007CCFH
XXXXXXXXB
to
XXXXXXXXB
Data register 9
(8 bytes)
007CD0H
to
007CD7H
XXXXXXXXB
to
XXXXXXXXB
Data register 10
(8 bytes)
007CD8H
to
007CDFH
XXXXXXXXB
to
XXXXXXXXB
Data register 11
(8 bytes)
007CE0H
to
007CE7H
XXXXXXXXB
to
XXXXXXXXB
Data register 12
(8 bytes)
007CE8H
to
007CEFH
XXXXXXXXB
to
XXXXXXXXB
Data register 13
(8 bytes)
(Continued)
47
MB90350E Series
(Continued)
Address
Register
CAN1
Abbreviation
Access
Initial Value
007CF0H
Data register 14
to
XXXXXXXXB
to
XXXXXXXXB
DTR14
R/W
(8 bytes)
007CF7H
007CF8H
Data register 15
to
XXXXXXXXB
to
XXXXXXXXB
DTR15
R/W
(8 bytes)
007CFFH
48
MB90350E Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
EI2OS
DMA ch
corresponding number
register
Interrupt cause
Number
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
Number
Address
Reset
N
N
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
N
Reserved
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
Reserved
N
CAN 1 RX / Input Capture 6
CAN 1 TX/NS / Input Capture 7
I2C
Y1
Y1
N
Reserved
N
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
PPG 4/5
Y1
Y1
Y1
Y1
N
1
2
⎯
⎯
⎯
⎯
⎯
⎯
3
PPG 6/7
N
PPG 8/9/C/D
N
PPG A/B/E/F
N
Timebase Timer
External Interrupt 8 to 11
Watch Timer
N
Y1
N
⎯
4
External Interrupt 12 to 15
A/D Converter
Y1
Y1
N
5
I/O Timer 0 / I/O Timer 1
Input Capture 4/5
Output Compare 4/5
Input Capture 0/1
Output Compare 6/7
Reserved
⎯
6
Y1
Y1
Y1
Y1
N
7
8
9
10
11
12
13
Reserved
N
UART 3 RX
Y2
Y1
0000BDH
UART 3 TX
(Continued)
49
MB90350E Series
(Continued)
Interrupt control
register
Interrupt vector
EI2OS
DMA ch
Interrupt cause
corresponding number
Number
Address
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
Number
Address
UART 2 RX
Y2
Y1
N
14
15
⎯
⎯
#39
#40
#41
#42
ICR14
0000BEH
UART 2 TX
Flash memory
Delayed interrupt
ICR15
0000BFH
N
Y1 : Usable
Y2 : Usable, with EI2OS stop function
: Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
N
• When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one
can use EI2OS at a time.
• When either of the two peripheral resources sharing the ICR register specifies EI2OS, the other one
cannot use interrupts.
50
MB90350E Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
−4.0
⎯
Max
VSS + 6.0
VSS + 6.0
VSS + 6.0
VSS + 6.0
VSS + 6.0
+4.0
VCC
AVCC
AVRH
VI
V
V
V
V
V
Power supply voltage*1
VCC = AVCC*2
AVCC ≥ AVRH*2
Input voltage*1
Output voltage*1
*3
*3
VO
Maximum Clamp Current
ICLAMP
Σ|ICLAMP|
IOL
mA *5
mA *5
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mW
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
Power consumption
40
⎯
15
IOLAV
ΣIOL
⎯
4
⎯
100
ΣIOLAV
IOH
⎯
50
⎯
−15
IOHAV
ΣIOH
ΣIOHAV
PD
⎯
−4
⎯
−100
−50
⎯
⎯
320
−40
+105
+125
+150
°C
Operating temperature
Storage temperature
TA
−40
°C *6
°C
TSTG
−55
(Continued)
51
MB90350E Series
(Continued)
*1: This parameter is based on VSS = AVSS = 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67
*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,
P50 to P56 (for evaluation device : P50 to P55) , P60 to P67
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a connecting limit resistance between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Recommended circuit sample:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0 V to 16 V)
R
*6 : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
52
MB90350E Series
2. Recommended Operating Conditions
(VSS = AVSS = 0 V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
4.0
5.0
5.5
V
V
Under normal operation
Under normal operation, when not using the
A/D converter and not Flash programming.
3.5
5.0
5.5
VCC,
AVCC
Power supply voltage
4.5
3.0
5.0
5.5
5.5
V
V
When External bus is used.
⎯
Maintains RAM data in stop mode
Use a ceramic capacitor or comparable
capacitor of the AC characteristics. Bypass
capacitor at the VCC pin should be greater
than this capacitor.
Smoothing capacitor
CS
TA
0.1
⎯
1.0
µF
°C
Operating temperature
−40
⎯
+125
*
* : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
53
MB90350E Series
3. DC Characteristics
Sym-
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Pin inputs if CMOS
hysteresis input levels
areselected(exceptP12,
P15, P44, P45, P50)
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Pin inputs if
VIHA
VIHT
VIHS
⎯
⎯
⎯
⎯
⎯
⎯
0.8 VCC
2.0
⎯
⎯
⎯
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
Automotive input
levels are selected
“H” level
input
voltage
(At VCC =
5 V 10%)
Pin inputs if TTL input
levels are selected
P12, P15, P50 inputs if
CMOS input levels are
selected
0.7 VCC
P44, P45 inputs if CMOS
hysteresis input levels
are selected
VIHI
⎯
⎯
0.7 VCC
⎯
VCC + 0.3
V
RST input pin (CMOS
hysteresis)
VIHR
VIHM
⎯
⎯
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VCC − 0.3
MD input pin
Pin inputs if CMOS
hysteresis input levels
areselected(exceptP12,
P15, P44, P45, P50)
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Pin inputs if
VILA
VILT
VILS
⎯
⎯
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VSS − 0.3
⎯
⎯
⎯
0.5 VCC
0.8
V
V
V
Automotive input
levels are selected
“L” level
input
voltage
(At VCC =
5 V 10%)
Pin inputs if TTL
input levels are selected
P12, P15, P50 inputs if
CMOS input levels are
selected
0.3 VCC
P44, P45 inputs if CMOS
hysteresis input levels
are selected
VILI
⎯
⎯
VSS − 0.3
⎯
0.3 VCC
V
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VCC − 0.5
⎯
⎯
⎯
0.2 VCC
VSS + 0.3
⎯
V
V
V
MD input pin
Output “H”
voltage
Normal
outputs
VCC = 4.5 V,
IOH = −4.0 mA
Output “H”
voltage
I2Ccurrent VCC = 4.5 V,
outputs IOH = −3.0 mA
VOHI
VCC − 0.5
⎯
⎯
V
(Continued)
54
MB90350E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Output “L”
Pin
Condition
Unit
Remarks
Min Typ Max
Normal
outputs
I2C current VCC = 4.5 V,
outputs
VCC = 4.5 V,
IOL = 4.0 mA
VOL
VOLI
IIL
⎯
⎯
⎯
⎯
⎯
0.4
0.4
+ 1
V
V
voltage
Output “L”
voltage
IOL = 3.0 mA
Input leak
current
VCC = 5.5 V,
VSS < VI < VCC
⎯
− 1
µA
P00 to P07,
P10 to P17,
P20 to P25,
P30 to P37,
RST
Pull-up
resistance
RUP
⎯
25
50
100 kΩ
100 kΩ
Pull-down
resistance
Except Flash
memory devices
RDOWN
MD2
⎯
25
50
48
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
⎯
60
65
70
35
mA
mA
mA
mA
VCC = 5.0 V,
Flash memory
devices
ICC
Internal frequency : 24 MHz,
At writing Flash memory.
⎯
⎯
⎯
53
58
25
VCC = 5.0 V,
Flash memory
devices
Internal frequency : 24 MHz,
At erasing Flash memory.
VCC = 5.0 V,
Power supply
current
ICCS
VCC
Internal frequency : 24 MHz,
At Sleep mode.
Devices
⎯
⎯
0.3
0.4
0.8
1.0
mA without
“T”-suffix
VCC = 5.0 V,
Internal frequency : 2 MHz,
At Main Timer mode
ICTS
Devices
mA
with “T”-suffix
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency = 4 MHz
ICTSPLL6
⎯
4
7
mA
(Continued)
55
MB90350E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
MB90F351E
MB90F352E
MB90351E
MB90352E
MB90F356E
MB90F357E
MB90356E
MB90357E
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At sub clock operation
TA = +25°C
⎯
70
140 µA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub clock operation
TA = +25°C
MB90F356E
MB90F357E
MB90356E
MB90357E
⎯
⎯
100
100
200
200
µA
µA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub clock operation
TA = +25°C
MB90F356ES
MB90F357ES
MB90356ES
MB90357ES
Power supply
current
ICCL
VCC
MB90F351TE
MB90F352TE
MB90351TE
MB90352TE
MB90F356TE
MB90F357TE
MB90356TE
MB90357TE
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At sub clock operation
TA = +25°C
⎯
120
240
µA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub clock operation
TA = +25°C
MB90F356TE
MB90F357TE
MB90356TE
MB90357TE
⎯
⎯
150
150
300
300
µA
µA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub clock operation
TA = +25°C
MB90F356TES
MB90F357TES
MB90356TES
MB90357TES
(Continued)
56
MB90350E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
MB90F351E
MB90F352E
MB90351E
MB90352E
MB90F356E
MB90F357E
MB90356E
MB90357E
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At sub sleep
TA = +25°C
⎯
20
50
µA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub sleep
TA = +25°C
MB90F356E
MB90F357E
MB90356E
MB90357E
⎯
⎯
60
60
200 µA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub sleep
TA = +25°C
MB90F356ES
MB90F357ES
MB90356ES
MB90357ES
200 µA
Power supply
current
ICCLS
VCC
MB90F351TE
MB90F352TE
MB90351TE
MB90352TE
MB90F356TE
MB90F357TE
MB90356TE
MB90357TE
VCC = 5.0 V,
Internal frequency: 8 kHz,
At sub sleep
⎯
70
150 µA
TA = +25°C
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub sleep
TA = +25°C
MB90F356TE
MB90F357TE
MB90356TE
MB90357TE
⎯
⎯
110
110
300 µA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub sleep
TA = +25°C
MB90F356TES
MB90F357TES
MB90356TES
MB90357TES
300 µA
(Continued)
57
MB90350E Series
(Continued)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
MB90F351E
MB90F352E
MB90351E
MB90352E
MB90F356E
MB90F357E
MB90356E
MB90357E
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At watch mode
TA = +25°C
⎯
10
35
µA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock su-
pervisor,
At watch mode
TA = +25°C
MB90F356E
MB90F357E
MB90356E
MB90357E
⎯
⎯
25
25
150 µA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At watch mode
TA = +25°C
MB90F356ES
MB90F357ES
MB90356ES
MB90357ES
150 µA
ICCT
MB90F351TE
MB90F352TE
MB90351TE
MB90352TE
MB90F356TE
MB90F357TE
MB90356TE
MB90357TE
VCC = 5.0 V,
Power supply
current
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At watch mode
TA = +25°C
VCC
⎯
60
140 µA
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At watch mode
TA = +25°C
MB90F356TE
MB90F357TE
MB90356TE
MB90357TE
⎯
⎯
80
80
250 µA
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At watch mode
TA = +25°C
MB90F356TES
MB90F357TES
MB90356TES
MB90357TES
250 µA
Devices
⎯
⎯
7
25
µA without
VCC = 5.0 V,
At stop mode,
TA = +25°C
“T”-suffix
ICCH
Devices
with “T”-suffix
60
130 µA
Other than
C, AVCC, AVSS,
AVRH, VCC,
VSS
Input capacity
CIN
⎯
⎯
5
15
pF
58
MB90350E Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
1/2 (at PLL stop)
When using an oscillation circuit
3
⎯
16
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1 multiplied PLL
When using an oscillation circuit
4
4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
16
12
8
2 multiplied PLL
When using an oscillation circuit
X0, X1
3 multiplied PLL
When using an oscillation circuit
4
4 multiplied PLL
When using an oscillation circuit
4
6
6 multiplied PLL
When using an oscillation circuit
⎯
3
4
fC
Clock frequency
1/2 (at PLL stop),
When using an external clock
24
24
12
8
1 multiplied PLL
When using an external clock
4
2 multiplied PLL
When using an external clock
4
X0
3 multiplied PLL
When using an external clock
4
4 multiplied PLL
When using an external clock
4
6
6 multiplied PLL
When using an external clock
⎯
4
fCL
X0A, X1A
X0, X1
X0
—
62.5
41.67
10
32.768 100
kHz When using sub clock
⎯
⎯
333
333
—
ns
ns
µs
ns
µs
When using an oscillation circuit
When using an external clock
tCYL
Clock cycle time
tCYLL
X0A, X1A
X0
30.5
⎯
PWH, PWL
PWHL, PWLL
10
⎯
Duty ratio should be about
30% to 70%.
Input clock pulse width
X0A
5
15.2
⎯
Input clock rise and fall
time
tCR, tCF
X0
⎯
⎯
5
ns
When using an external clock
(Continued)
59
MB90350E Series
(Continued)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
Internal operating
clock frequency
(machine clock)
fCP
fCPL
tCP
⎯
⎯
⎯
⎯
1.5
⎯
24
MHz When using main clock
kHz When using sub clock
⎯
41.67
20
8.192
⎯
50
666
⎯
Internal operating
clock cycle time
(machine clock)
ns
When using main clock
When using sub clock
tCPL
122.1
µs
• Clock Timing
tCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
tCF
tCR
60
MB90350E Series
• PLL guaranteed operation range
Guaranteed operation range
5.5
4.0
Guaranteed A/D converter
operation range
3.5
Guaranteed PLL operation range
1.5
4
24
Main clock fCP (MHz)
Guaranteed operation range of MB90350E series
Guaranteed A/D converter operation range
× 6 × 4 × 3
× 2
× 1
24
16
12
8
× 1/2
(PLL off)
4.0
1.5
3
4
8
12
24
16
External clock fC (MHz) *
* : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz.
External clock frequency and internal operation clock frequency
61
MB90350E Series
(2) Reset Standby Input
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter Symbol
Pin
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
Reset input
tRSTL
Oscillation time of oscillator* + 100 µs
⎯
⎯
µs
µs
RST
time
In Main timer mode and
PLL timer mode
100
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation
time is between several ms to tens of ms. In ceramic oscillators, the oscillation time is between hundreds
of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode and, Watch mode:
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
62
MB90350E Series
(3) Power On Reset
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
30
Power on rise time
Power off time
tR
VCC
VCC
ms
⎯
tOFF
⎯
ms Waiting time until power-on
tR
2.7 V
V
CC
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within
1 V/s, you can operate while using the PLL clock.
VCC
We recommend the slope for
a rise of 50 mV/ms maximum.
3 V
Holds RAM data
VSS
(4) Clock Output Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V 10%, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
tCYC
Pin
CLK
CLK
Condition
Unit
Remarks
Min
62.5
41.76
20
Max
⎯
ns
ns
ns
ns
fCP = 16 MHz
fCP = 24 MHz
fCP = 16 MHz
fCP = 24 MHz
Cycle time
⎯
⎯
⎯
⎯
CLK ↑ → CLK ↓
tCHCL
13
⎯
tCYC
tCHCL
2.4 V
2.4 V
CLK
0.8 V
63
MB90350E Series
(5) Bus Timing (Read)
(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Sym-
Parameter
bol
Pin
Condition
Unit
Min
Max
ALE pulse width
tLHLL
tAVLL
tLLAX
tAVRL
ALE
tCP/2 − 10
⎯
ns
ns
ns
ns
ALE, A21 to A16,
AD15 to AD00
Valid address → ALE ↓ time
ALE ↓ → Address valid time
Valid address → RD ↓ time
tCP/2 − 20
tCP/2 − 15
tCP − 15
⎯
⎯
⎯
ALE, AD15 to AD00
A21 to A16,
AD15 to AD00, RD
Valid address → Valid data
input
A21 to A16,
AD15 to AD00
tAVDV
⎯
5 tCP/2 − 60
ns
RD pulse width
tRLRH RD
(n*+3/2) tCP − 20
⎯
ns
ns
ns
ns
ns
⎯
(n*+3/2) tCP − 50
RD ↓ → Valid data input
RD ↑ → Data hold time
RD ↑ → ALE ↑ time
tRLDV RD, AD15 to AD00
tRHDX RD, AD15 to AD00
tRHLH RD, ALE
⎯
0
⎯
⎯
⎯
tCP/2 − 15
tCP/2 − 10
RD ↑ → Address valid time
tRHAX RD, A21 to A16
A21 to A16,
Valid address → CLK ↑ time tAVCH AD15 to AD00,
tCP/2 − 16
⎯
ns
CLK
RD ↓ → CLK ↑ time
ALE ↓ → RD ↓ time
tRLCH RD, CLK
tCP/2 − 15
tCP/2 − 15
⎯
⎯
ns
ns
tLLRL
ALE, RD
* : Number of ready cycles
64
MB90350E Series
For 1 cycle of auto-ready
CLK
tRLCH
tAVCH
2.4 V
2.4 V
tLLAX
tAVLL
tLHLL
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
ALE
RD
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A21 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
VIH
VIL
2.4 V
0.8 V
VIH
VIL
AD15 to AD00
Address
Read data
65
MB90350E Series
(6) Bus Timing (Write)
(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
A21 to A16,
AD15 to AD00,
WR
Valid address → WR ↓ time
tAVWL
tCP−15
⎯
ns
(n*+3/2)tCP − 20
(n*+3/2)tCP − 20
WR pulse width
tWLWH
tDVWH
WR
⎯
⎯
ns
ns
Valid data output → WR ↑
time
AD15 to AD00,
WR
⎯
AD15 to AD00,
WR
WR ↑ → Data hold time
tWHDX
tWHAX
15
⎯
⎯
ns
ns
A21 to A16,
WR
WR ↑ → Address valid time
tCP/2 − 10
WR ↑ → ALE ↑ time
WR ↓ → CLK ↑ time
tWHLH
tWLCH
WR, ALE
WR, CLK
tCP/2 − 15
tCP/2 − 15
⎯
⎯
ns
ns
* : Number of ready cycles
For 1 cycle of auto-ready
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A21 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
66
MB90350E Series
(7) Ready Input Timing
Parameter
(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Sym-
bol
Pin
Condition
Units
Remarks
Min
45
32
0
Max
⎯
ns fCP = 16 MHz
ns fCP = 24 MHz
ns
RDY set-up time
RDY hold time
tRYHS
tRYHH
RDY
RDY
⎯
⎯
⎯
Note : If the RDY set-up time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
VIH
VIH
RDY
(When WAIT is not used.)
RDY
(When WAIT is used.)
VIL
67
MB90350E Series
(8) Hold Timing
(TA = –40°C to +105°C, VCC = 5.0 V 10 %, VSS = 0.0 V, fCP ≤ 24 MHz)
Value
Parameter
Symbol
Pin
Condition
Units
Min
Max
Pin floating → HAK ↓
tXHAL
tHAHV
HAK
HAK
30
tCP
ns
ns
time
⎯
HAK ↑ time → Pin valid
time
tCP
2 tCP
Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Hi-Z
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
68
MB90350E Series
(9) UART 2/3
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOV
SCK2, SCK3
8 tCP*
⎯
ns
ns
SCK2, SCK3,
SOT2, SOT3
SCK ↓ → SOT delay time
−80
100
60
+80
⎯
Internal shift clock mode output
SCK2, SCK3,
SIN2, SIN3
pins are C = 80 pF + 1 TTL
L
Valid SIN → SCK ↑
tIVSH
ns
ns
SCK2, SCK3,
SIN2, SIN3
SCK ↑ → Valid SIN hold time
tSHIX
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
SCK2, SCK3
SCK2, SCK3
4 tCP
⎯
⎯
ns
ns
tSLSH
4 tCP
SCK2, SCK3,
SOT2, SOT3
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
External shift clock mode out-
put pins are
CL = 80 pF + 1 TTL
⎯
60
60
150
⎯
ns
ns
ns
SCK2, SCK3,
SIN2, SIN3
SCK2, SCK3,
SIN2, SIN3
SCK ↑ → Valid SIN hold time
⎯
* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time).
Notes : • AC characteristic in CLK synchronous mode.
• CL is load capacity value of pins when testing.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
tSHIX
VIH
VIL
VIH
VIL
SIN
69
MB90350E Series
• External Shift Clock Mode
tSLSH
tSHSL
VIH
VIH
SCK
VIL
tSLOV
VIL
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
VIH
VIL
VIH
VIL
(10) Trigger Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTRGH
tTRGL
INT8 to INT15,
INT9R to INT11R, ADTG
Input pulse width
⎯
5 tCP
⎯
ns
VIH
VIH
INT8 to INT15,
VIL
VIL
INT9R to INT11R,
ADTG
tTRGH
tTRGL
70
MB90350E Series
(11) Timer Related Resource Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
tTIWL
TIN1, TIN3,IN0, IN1,
IN4 to IN7
Input pulse width
⎯
4 tCP
⎯
ns
VIH
VIH
TIN1, TIN3,
IN0, IN1,
VIL
VIL
tTIWH
IN4 to IN7
tTIWL
(12) Timer Related Resource Output Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
TOT1, TOT3, PPG4, PPG6,
PPG8 to PPGF
CLK ↑ → TOUT change time
tTO
⎯
30
⎯
ns
2.4 V
CLK
2.4 V
0.8 V
TOT1, TOT3,
PPG4, PPG6
PPG8 to PPGF
tTO
71
MB90350E Series
(13) I2C Timing
(TA = −40 °C to +125 °C, VCC = AVCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Fast-mode*4
Standard-mode
Parameter
SCL clock frequency
Symbol
Condition
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
Hold time for (repeated) START condition
SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
tHIGH
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
⎯
3.45*2
⎯
0.6
0
⎯
0.9*3
⎯
µs
µs
ns
µs
µs
R = 1.7 kΩ,
C = 50 pF*1
Data hold time
SCL ↓ → SDA ↓ ↑
Data set-up time
SDA ↓ ↑ → SCL ↑
250*5
4.0
4.7
100*5
0.6
1.3
Set-up time for STOP condition
SCL ↑ → SDA ↑
⎯
⎯
Bus free time between STOP condition and
START condition
⎯
⎯
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT has to meet at least that the device does not exceed the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*5 : Refer to “• Note of SDA, SCL set-up time”.
• Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tCP
72
MB90350E Series
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending
on the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be
satisfied.
• Timing definition
SDA
tBUS
tHDSTA
tSUDAT
tLOW
SCL
tHDSTA
tSUSTA
tHIGH
tSUSTO
tHDDAT
fSCL
73
MB90350E Series
5. A/D Converter
(
TA
=
−
40 °C to
+
125 °C, 3.0 V
≤
AVRH, VCC
=
AVCC
=
5.0 V 10
%,
fCP
≤ 24 MHz, VSS = AVSS = 0 V)
Value
Typ
⎯
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
3.0
2.5
LSB
LSB
Nonlinearity error
⎯
⎯
Differential
nonlinearity error
⎯
⎯
⎯
⎯
1.9
LSB
V
Zero reading
voltage
VOT
VFST
AN0 to AN14 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5
Full scale reading
voltage
AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5
V
1.0
4.5 V ≤ AVCC ≤ 5.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
⎯
⎯
16500
µs
µs
2.0
0.5
1.2
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
∞
Analog port input
current
IAIN
VAIN
⎯
AN0 to AN14
AN0 to AN14
AVRH
− 0.3
AVSS
⎯
⎯
⎯
+ 0.3
AVRH
AVCC
µA
V
Analog input
voltage range
Reference
voltage range
AVSS + 2.7
V
IA
AVCC
AVCC
⎯
⎯
3.5
7.5
5
mA
Power supply
current
IAH
⎯
µA
*
*
Reference
voltage supply
current
IR
AVRH
AVRH
⎯
⎯
600
900
5
µA
µA
IRH
⎯
Offset between
channels
⎯
AN0 to AN14
⎯
⎯
4
LSB
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
74
MB90350E Series
Notes on A/D Converter Section
• About the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
· Analog input equivalence circuit
R
Analog input
Comparator
C
ON at sampling
MB90F351E(S), MB90F352E(S), MB90F356E(S), MB90F357E(S),
MB90F351TE(S), MB90F352TE(S),MB90F356TE(S), MB90F357TE(S)
R
C
4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max) 16.0 pF (Max)
4.0 V ≤ AVCC ≤ 4.5 V 8.2 kΩ (Max) 16.0 pF (Max)
MB90V340E-101/102/103/104,
MB90351E(S), MB90352E(S),MB90356E(S), MB90357E(S),
MB90351TE(S), MB90352TE(S),MB90356TE(S), MB90357TE(S)
R
C
4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max) 14.4 pF (Max)
4.0 V ≤ AVCC ≤ 4.5 V 8.2 kΩ (Max) 14.4 pF (Max)
Note : The value is reference value.
75
MB90350E Series
• Flash memory device
· Relation between External impedance and minimum sampling time
(MB90F351E(S), MB90F352E(S), MB90F356E(S), MB90F357E(S),
MB90F351TE(S), MB90F352TE(S),MB90F356TE(S), MB90F357TE(S))
[External impedance = 0 kΩ to 100 kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
[External impedance = 0 kΩ to 20 kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
4.0 V ≤ AVCC ≤ 4.5 V
4.0 V ≤ AVCC ≤ 4.5 V
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• MASK ROM device
· Relation between External impedance and minimum sampling time
(MB90V340E-101/102/103/104,
MB90351E(S), MB90352E(S), MB90356E(S), MB90357E(S),
MB90351TE(S), MB90352TE(S), MB90356TE(S), MB90357TE(S))
[External impedance = 0 kΩ to 100 kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
[External impedance = 0 kΩ to 20kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
4.0 V ≤ AVCC ≤ 4.5 V
4.0 V ≤ AVCC ≤ 4.5 V
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• About the error
Values of relative errors grow larger, as |AVRH − AVSS| becomes smaller.
76
MB90350E Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
Total error
: Difference between an actual value and a theoretical value. A total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actual measurement value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB (Ideal value) =
1 LSB
AVRH − AVSS
[V]
1024
N
: A/D converter digital output value
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
77
MB90350E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Actual conversion
characteristics
3FEH
N + 1H
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
3FDH
VFST (actual
measurement
value)
NH
VNT (actual
measurement value)
004H
003H
002H
001H
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1H
N − 2H
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVSS
AVRH
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H”.
VFST : Voltage at which digital output transits from “3FEH” to “3FFH”.
78
MB90350E Series
7. Flash Memory Program/Erase Characteristics
• Dual Operation Flash Memory
Value
Typ
Parameter
Conditions
Unit
Remarks
Min
Max
Sector erase time
(4 Kbytes sector)
Excludes programming
prior to erasure
⎯
0.2
0.5
4.6
0.5
s
s
s
Sector erase time
(16 Kbytes sector)
Excludes programming
prior to erasure
⎯
⎯
7.5
TA = +25 °C
VCC = 5.0 V
Excludes programming
prior to erasure
Chip erase time
⎯
Word (16-bit width)
programming time
Except for the overhead
time of the system level
⎯
10000
20
64
⎯
⎯
3600
⎯
µs
Program/Erase cycle
⎯
cycle
year
Flash memory Data
Retention Time
Average
TA = +85 °C
⎯
*
* : Corresponding value comes from the technology reliability evaluation result.
(UsingArrheniusequationtotranslatehightemperaturemeasurementstestresultintonormalizedvalueat
+85°C)
79
MB90350E Series
■ ORDERING INFORMATION
Part number
MB90F351EPMC
MB90F351ESPMC
MB90F351TEPMC
MB90F351TESPMC
MB90F356EPMC
MB90F356ESPMC
MB90F356TEPMC
MB90F356TESPMC
MB90F352EPMC
MB90F352ESPMC
MB90F352TEPMC
MB90F352TESPMC
MB90F357EPMC
MB90F357ESPMC
MB90F357TEPMC
MB90F357TESPMC
MB90351EPMC
Package
Remarks
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
Dual operation
Flash memory products
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
Dual operation
Flash memory products
(128 Kbytes)
MB90351ESPMC
MB90351TEPMC
MB90351TESPMC
MB90356EPMC
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
MASK ROM products
(64 Kbytes)
MB90356ESPMC
MB90356TEPMC
MB90356TESPMC
MB90352EPMC
MB90352ESPMC
MB90352TEPMC
MB90352TESPMC
MB90357EPMC
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
MASK ROM products
(128 Kbytes)
MB90357ESPMC
MB90357TEPMC
MB90357TESPMC
(Continued)
80
MB90350E Series
(Continued)
Part number
Package
Remarks
MB90F351EPMC1
MB90F351ESPMC1
MB90F351TEPMC1
MB90F351TESPMC1
MB90F356EPMC1
MB90F356ESPMC1
MB90F356TEPMC1
MB90F356TESPMC1
MB90F352EPMC1
MB90F352ESPMC1
MB90F352TEPMC1
MB90F352TESPMC1
MB90F357EPMC1
MB90F357ESPMC1
MB90F357TEPMC1
MB90F357TESPMC1
MB90351EPMC1
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
Dual operation
Flash memory products
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
Dual operation
Flash memory products
(128 Kbytes)
MB90351ESPMC1
MB90351TEPMC1
MB90351TESPMC1
MB90356EPMC1
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
MASK ROM products
(64 Kbytes)
MB90356ESPMC1
MB90356TEPMC1
MB90356TESPMC1
MB90352EPMC1
MB90352ESPMC1
MB90352TEPMC1
MB90352TESPMC1
MB90357EPMC1
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
MASK ROM products
(128 Kbytes)
MB90357ESPMC1
MB90357TEPMC1
MB90357TESPMC1
MB90V340E-101
MB90V340E-102
299-pin ceramic PGA
PGA-299C-A01
Device for evaluation
MB90V340E-103
MB90V340E-104
81
MB90350E Series
■ PACKAGE DIMENSIONS
64-pin plastic LQFP
Lead pitch
0.65 mm
12.0 × 12.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
P-LFQFP64-12×12-0.65
Code
(Reference)
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00 0.20(.551 .008)SQ
*12.00 0.10(.472 .004)SQ
0.145 0.055
(.0057 .0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 –+00..1200
(Mounting height)
.059 –+..000048
0.25(.010)
INDEX
0~8˚
64
17
0.50 0.20
(.020 .008)
0.10 0.10
(.004 .004)
(Stand off)
"A"
1
16
0.60 0.15
(.024 .006)
0.65(.026)
0.32 0.05
(.013 .002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2003 FUJITSU LIMITED F64034S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
82
MB90350E Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.50 mm
10.0 × 10.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.32g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00 0.20(.472 .008)SQ
*
10.00 0.10(.394 .004)SQ
0.145 0.055
(.006 .002)
48
33
49
32
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0.10 0.10
(.004 .004)
(Stand off)
0˚~8˚
64
17
"A"
0.25(.010)
0.50 0.20
(.020 .008)
1
16
LEAD No.
0.60 0.15
(.024 .006)
0.50(.020)
0.20 0.05
(.008 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 FUJITSU LIMITED F64036S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
83
MB90350E Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Added the following part numbers.
MB90356E(S)/TE(S),MB90F356E(S)/TE(S),
MB90357E(S)/TE(S), MB90F357E(S)/TE(S),
MB90V340E-103/104)
⎯
⎯
1
2
■DESCRIPTION
Added a description of the "Clock supervisor".
Added a description of the "Clock supervisor".
■FEATURES
13
■PACKAGES AND PRODUCT
Changed the description of "FPT-64P-M24" as follows:
CORRESPONDENCE
* →
Removed the table footnote "* : This device is under
development."
27
40
■HANDLING DEVICES
■ I/O MAP
Added section "19.Internal CR oscillation circuit".
Added the “Clock supervisor Control Register”.
■ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Added the ratings for the "Clock supervisor" to the
"ICCL" section of the power supply current ratings.
56
57
Added the ratings for the "Clock supervisor" to the
"ICCLS" section of the power supply current ratings.
Added the ratings for the "Clock supervisor" to the
"ICCT" section of the power supply current ratings.
58
81
■ORDERING INFORMATION
Removed the footnote asterisks from the "Dual operation
Flash memory products*" and "MASK ROM products*" of
the "FPT-64P-M24" package.
Removed the table footnote "* : This device is under
development."
The vertical lines marked in the left side of the page show the changes.
84
MB90350E Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
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party or does Fujitsu warrant non-infringement of any third-party’s
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Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
The company names and brand names herein are the trademarks or
registered trademarks of their respective owners.
Edited
Business Promotion Dept.
F0701
相关型号:
MB90F352ESPMC1
Microcontroller, 16-Bit, FLASH, F2MC-16LX CPU, 24MHz, CMOS, PQFP64, 10 X 10 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-64
CYPRESS
MB90F352ESPMC1
Microcontroller, 16-Bit, FLASH, 24MHz, CMOS, PQFP64, 10 X 10 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LFQFP-64
SPANSION
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