MB90F362TS [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有型号: | MB90F362TS |
厂家: | FUJITSU |
描述: | 16-bit Proprietary Microcontroller |
文件: | 总59页 (文件大小:579K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13736-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90360 Series
MB90F362/T/S/TS, MB90362/T/S/TS, MB90F367/T/S/TS,
MB90367/T/S/TS, MB90V340A-101, MB90V340A-102,
MB90V340A-103, MB90V340A-104
■ DESCRIPTION
The MB90360-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed for automotive
and other industrial applications. Its main feature is the on-board CAN Interfaces, which conform to Ver 2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM
program memory up to 64 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external
4 MHz clock. Also, main and sub-clock can be monitored independently using the clock monitor function.
The unit features a 4 channel input capture unit 1 channel 16-bit free running timer, 2-channel LIN-UART, and
16-channel 8/10-bit A/D converter as the peripheral resource.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ PACKAGE
48-pin Plastic LQFP
(FPT-48P-M26)
MB90360 Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz) .
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed (devices without S-
suffix only) .
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock and 6-time multiplied
PLL clock) .
• Clock monitor function (MB90x367x only)
• Main clock or sub-clock is monitored independently
• Internal CR oscillation clock (100 kHz typical) can be used as sub-clock
• Instruction system best suited to controller
• 16 Mbytes CPU memory space
• 24-bit internal addressing
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channel external interrupts are supported
• Automatic data transfer function independent of CPU
• Expanded intelligent I/O service function (EI2OS) : up to 16 channels
• Low-power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (timebase timer mode that is transferred from main clock mode)
• PLL timer mode (timebase timer mode that is transferred from PLL clock mode)
• Watch mode (a mode that operates sub-clock and watch timer only, devices without S-suffix)
• Stop mode (a mode that stops oscillation clock and sub-clock)
• CPU blocking operation mode
• Process
• CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 34 ports (devices without S-suffix)
- 36 ports (devices with S-suffix)
• Sub-clock pin (X0A and X1A)
• Provided (used for external oscillation), devices without S-suffix
• Not provided (used with internal CR oscillation in sub-clock mode) , devices with S-suffix
(Continued)
2
MB90360 Series
(Continued)
• Timer
• Timebase timer, watch timer (device without S-suffix) , watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 2 channels or 16-bit × 2 channels
• 16-bit reload timer : 2 channels
• 16- bit input/output timer
- 16-bit free run timer : 1 channel (FRT0 : ICU 0/1/2/3)
- 16- bit input capture : (ICU) : 4 channels
• Full-CAN interface : up to 1 channel
• Compliant with Ver 2.0A and Ver 2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
• UART (LIN/SCI) : up to 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• DTP/External interrupt : up to 8 channels, CAN wakeup : up to 1 channel
• Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external
input.
• Delay interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 16 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 6 address pointers.
• Low voltage/CPU operation detection reset (devices with T-suffix)
• Detects low voltage (4.0 V 0.3 V) and resets automatically
• Resets automatically when program is runaway and counter is not cleared within interval time
(approx. 262 ms : external 4 MHz)
• Capable of changing input voltage for port
• Automotive/CMOS-Schmitt (initial level is Automotive in single-chip mode)
• FLASH memory security function
• Protects the content of FLASH memory (FLASH memory device only)
3
MB90360 Series
■ PRODUCT LINEUP
MB90V340
A-101
MB90V340
A-102
Features
CPU
MB90362
MB90362T
MB90362S
F2MC-16LX CPU
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
MB90362TS
System clock
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
Sub-clock pin
(X0A, X1A)
Yes
No
No
No
Yes
Clock monitor
function
ROM
MASK ROM, 64 Kbytes
3 Kbytes
External
RAM capacitance
30 Kbytes
CAN
interface
1 channel
3 channels
Low voltage/CPU
operation
No
Yes
No
Yes
No
detection reset
Package
LQFP-48P
PGA-299C
Yes
Emulator-specific
power supply *
⎯
Corresponding
EVA product
MB90V340A-102
MB90V340A-101
⎯
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator
hardware manual for the details.
Features
CPU
MB90F362
MB90F362T MB90F362S MB90F362TS
F2MC-16LX CPU
PLL clock multiplier
( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns
(4 MHz oscillation clock, PLL × 6)
System clock
Sub-clock pin
(X0A, X1A)
Yes
No
Clock monitor
function
No
ROM
Flash memory, 64 Kbytes
3 Kbytes
RAM capacitance
CAN
interface
1 channel
Low voltage/CPU
operation detec-
tion reset
No
Yes
No
Yes
Package
LQFP-48P
Corresponding
EVA product
MB90V340A-102
MB90V340A-101
4
MB90360 Series
MB90V340 MB90V340
Features
CPU
MB90367
MB90367T
MB90367S
MB90367TS
A-103
A-104
F2MC-16LX CPU
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
System clock
Sub-clock pin
(X0A, X1A)
No
Yes
Yes
(internal CR oscillation can be used as sub-clock)
Clock monitor
function
Yes
ROM
MASK ROM, 64 Kbytes
External
RAM capacitance
3 Kbytes
30 Kbytes
CAN
interface
1 channel
3 channels
Low voltage/CPU
operation
No
Yes
No
Yes
No
detection reset
Package
LQFP-48P
PGA-299C
Yes
Emulator-specific
power supply *
⎯
Corresponding
EVA product
MB90V340A-104
MB90V340A-103
⎯
* : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator
hardware manual for the details.
Features
CPU
MB90F367
MB90F367T MB90F367S MB90F367TS
F2MC-16LX CPU
PLL clock multiplier
( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns
(4 MHz oscillation clock, PLL × 6)
System clock
No
Sub-clock pin
(X0A, X1A)
Yes
(internal CR oscillation can be
used as sub-clock)
Clock monitor
function
Yes
ROM
Flash memory, 64 Kbytes
3 Kbytes
RAM capacitance
CAN
interface
1 channel
Low voltage/CPU
operation
No
Yes
No
Yes
detection reset
Package
LQFP-48P
Corresponding
EVA product
MB90V340A-104
MB90V340A-103
5
MB90360 Series
■ PIN ASSIGNMENT
• MB90F362/T/S/TS, MB90362/T/S/TS, MB90F367/T/S/TS, MB90367/T/S/TS
(TOP VIEW)
(LQFP-48P)
P20 *2
P21 *2
1
2
36
35
34
33
32
31
30
29
28
27
26
25
AVcc
AVR
P22/PPGD(C) *2
P60/AN0
3
P61/AN1
4
P23/PPGF(E) *2
P24/IN0
P25/IN1
P26/IN2
P27/IN3
X1
P62/AN2
5
P63/AN3
6
7
P64/AN4
8
P65/AN5
9
P66/AN6/PPGC(D)
P67/AN7/PPGE(F)
P80/ADTG/INT12R
P50/AN8
10
11
12
X0
C
Vss
(FPT-48P-M26)
*1 : MB90F362/T, MB90362/T, MB90F367/T, MB90367/T : X0A, X1A
MB90F362S/TS, MB90362S/TS, MB90F367S/TS, MB90367S/TS : P40, P41
*2 : High current port
6
MB90360 Series
■ PIN DESCRIPTION
Pin No.
Pin name
LQFP-48P*
Circuit type
Function
1
AVCC
I
VCC power input pin for analog circuit.
Power (Vref+) input pin for A/D converter.
It should be below VCC.
2
AVR
⎯
P60 to P65
AN0 to AN5
P66, P67
General-purpose I/O port.
3 to 8
9, 10
H
Analog input pin for A/D converter.
General-purpose I/O port.
AN6, AN7
Analog input pin for A/D converter.
H
PPGC (D) ,
PPGE (F)
Output pin for PPG.
P80
General-purpose I/O port.
11
12 to 14
15
ADTG
INT12R
F
H
H
Trigger input pin for A/D converter.
External interrupt request input pin for INT12.
General-purpose I/O port. (P50 has different I/O circuit type
from MB90V340A.)
P50 to P52
AN8 to AN10
P53
Analog input pin for A/D converter.
General-purpose I/O port.
AN11
Analog input pin for A/D converter.
Event input pin for reload timer 3.
General-purpose I/O port.
TIN3
P54
AN12
Analog input pin for A/D converter.
Output pin for reload timer 3
16
H
H
TOT3
INT8
External interrupt request input pin for INT8.
General-purpose I/O port.
P55 to P57
AN13 to AN15
Analog input pin for A/D converter.
17 to 19
INT10, INT11,
INT13
External interrupt request input pin for INT10, INT11, INT13.
Input pin for operation mode specification.
20
MD2
D
C
MD1,
MD0
21, 22
Input pin for operation mode specification.
23
24
25
RST
VCC
VSS
E
Reset input.
⎯
⎯
Power input pin (3.5 V to 5.5 V) .
Power input pin (0 V) .
Power supply stabilization capacitor pin. It should be connected
to a higher than or equal to 0.1 µF ceramic capacitor.
26
C
I
* : FPT-48P-M26
(Continued)
7
MB90360 Series
Pin No.
Pin name
Circuit type
Function
LQFP-48P*
27
28
X0
X1
Oscillation input pin.
A
Oscillation output pin.
General-purpose I/O port.
P27 to P24
IN3 to IN0
The register can be set to select whether to use a pull-up resis-
tor. This function is enabled in single-chip mode.
29 to 32
G
Event input pin for input capture 0 to 3.
General-purpose I/O port.
The register can be set to select whether to use a pull-up resis-
tor. This function is enabled in single-chip mode.
High current output port.
P23, P22
33, 34
35, 36
J
J
PPGF (E) ,
PPGD (C)
Output pin for PPG.
General-purpose I/O port.
The register can be set to select whether to use a pull-up resis-
tor. This function is enabled in single-chip mode.
High current output port.
P21, P20
P85
SIN1
P87
General-purpose I/O port.
37
38
39
40
K
F
F
F
Serial data input pin for UART1.
General-purpose I/O port.
SCK1
P86
Clock I/O pin for UART1.
General-purpose I/O port.
SOT1
P43
Serial data output pin for UART1.
General-purpose I/O port.
TX1
TX output pin for CAN1 interface.
General-purpose I/O port.
P42
41
42
RX1
F
F
F
RX input pin for CAN1 interface.
External interrupt request input pin for INT9 (Sub) .
General-purpose I/O port.
INT9R
P83
SOT0
TOT2
P84
Serial data output pin for UART0.
Output pin for reload timer 2
General-purpose I/O port.
43
SCK0
INT15R
Clock I/O pin for UART0.
External interrupt request input pin for INT15.
* : FPT-48P-M26
(Continued)
8
MB90360 Series
(Continued)
Pin No.
Pin name
Circuit type
Function
LQFP-48P*
P82
SIN0
General-purpose I/O port.
Serial data input pin for UART0.
44
K
INT14R
TIN2
External interrupt request input pin for INT14.
Event input pin for reload timer 2.
General-purpose I/O port. (Different I/O circuit type from
MB90V340A.)
P44
45
F
F
FRCK0
P40, P41
Free-run timer 0 clock pin.
General-purpose I/O port.
(Devices with S-suffix and MB90V340A-101/103 only.)
46, 47
Oscillation input pin for sub-clock.
(Devices without S-suffix and MB90V340A-102/104 only.)
X0A, X1A
AVSS
B
I
48
VSS power input pin for analog circuit.
* : FPT-48P-M26
9
MB90360 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Oscillation circuit
X1
X0
• High-speed oscillation feedback
resistor = approx. 1 MΩ
Xout
A
Standby control signal
Oscillation circuit
X1A
X0A
Xout
• Low-speed oscillation feedback
resistor = approx. 10 MΩ
B
Standby control signal
Mask ROM device :
R
• CMOS hysteresis input pin
Hysteresis
inputs
C
D
Flash device :
• CMOS input pin
Mask ROM device :
R
• CMOS hysteresis input pin
• Pull-down resistor value : approx. 50 kΩ
Hysteresis
inputs
Pull-down
resistor
Flash device :
• CMOS input pin
• No Pull-down
CMOS hysteresis input pin
• Pull-up resistor value : approx. 50 kΩ
Pull-up
resistor
E
R
Hysteresis
inputs
(Continued)
10
MB90360 Series
Type
Circuit
Remarks
• CMOS level output (IOL = 4 mA,
IOH = −4 mA)
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
Pout
Nout
R
F
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output (IOL = 4 mA,
IOH = −4 mA)
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
Pull-up control
Pout
Pull-up
resistor
• Settablepull-upresistor:approx. 50kΩ
Nout
G
R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output (IOL = 4 mA,
IOH = −4 mA)
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
• A/D analog input
Pout
Nout
R
H
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
(Continued)
11
MB90360 Series
(Continued)
Type
Circuit
Remarks
• Power supply input protection circuit
I
• CMOS level output (IOL = 20 mA,
IOH = −14 mA)
• CMOS hysteresis inputs (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
Pull-up control
Pull-up
resistor
Pout high current output
Nout high current output
• Settable pull-up resistor : approx. 50 kΩ
J
R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output (IOL = 4 mA,
IOH = −4 mA)
• CMOS input (With standby-time input
shutdown function)
• Automotive input (With standby-time in-
put shutdown function)
Pout
Nout
R
K
CMOS inputs
Automotive inputs
Standby control for
input shutdown
12
MB90360 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub-clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal oscillator circuit
• Turning-on sequence of power supply to A/D converter and analog inputs
• Connection of unused pins of A/D converter
• Notes on energization
• Stabilization of power supply voltage
• Initialization
• Notes on using CAN Function
• Flash security function
• Correspondence with +105 °C or more
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Use meticulous care not to exceed the rating.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90360 Series
X0
X1
Open
13
MB90360 Series
4. Precautions for when not using a sub-clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin and leave the
X1A pin open.
5. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempts to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90360
Series
VCC
VSS
VCC
VSS
7. Pull-up/down resistors
The MB90360 Series does not support internal pull-up/down resistors (Port 2 : built-in pull-up resistors) . Use
external components where needed.
8. Crystal oscillator circuit
Noises around X0 or X1 pin may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
9. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC and AVR) and analog inputs (AN0 to AN15) after
turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make
sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies
simultaneously is acceptable) .
14
MB90360 Series
10. Connection of unused pins of A/D converter if A/D converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
11. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified
VCC power supply voltage operating guarantee range. Therefore, the VCC power supply voltage should be stabi-
lized.
For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value)
at commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC power supply voltage and the
coefficient of transient fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,
turn on the power again.
14. Notes on using CAN function
To use CAN function, please set ’1’ to DIRECT bit of CAN direct mode register (CDMR) .
If DIRECT bit is set to ’0’ (initial value) , wait states will be performed when accessing CAN registers.
Note : Please refer to Hardware Manual of MB90360 series for detail of CAN Direct Mode Register.
15. Flash security function
The security bit is located in the area of the flash memory.
If protection code 01H is written in the security bit, the flash memory is in the protected state by security.
Therefore, please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security bit.
Flash memory size
Address for security bit
MB90F362
MB90F362S
MB90F362T
MB90F362TS
MB90F367
Embedded 512 Kbit Flash Memory
FF0001H
MB90F367S
MB90F367T
MB90F367TS
16. Correspondence with +105 °C or more
If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations.
15
MB90360 Series
■ BLOCK DIAGRAMS
• MB90V340A-101/102
X0, X1
X0A, X1A*
Clock
Controller
F2MC-16LX
Core
RST
16-bit
I/O Timer 0
FRCK0
Input
Capture
IN7 to IN0
8 channels
RAM
30 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler
(5 channels)
16-bit
I/O Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
UART
5 channels
16-bit
Reload Timer
4 channels
AVCC
TIN3 to TIN0
TOT3 to TOT0
AVSS
AN23 to AN0
8/10-bit
A/D
converter
24 channels
AVRH
AVRL
ADTG
AD15 to AD00
A23 to A16
ALE
RD
WRL
WRH
HRQ
10-bit
D/A converter
2 channels
External
Bus
DA01, DA00
8/16-bit
PPG
16 channels
HAK
RDY
CLK
PPGF to PPG0
I2C
interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/
External
Interrupt
DMA
Clock
Monitor
CKOT
* : Only for MB90V340A-102
16
MB90360 Series
• MB90V340A-103/104
X0, X1
X0A, X1A*
Clock
Controller/
monitor
F2MC-16LX
Core
RST
16-bit
I/O Timer 0
FRCK0
CR
oscillator
circuit
Input
IN7 to IN0
OUT7 to OUT0
FRCK1
Capture
8 channels
RAM
30 Kbytes
Output
Compare
8 channels
Prescaler
(5 channels)
16-bit
I/O Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
UART
5 channels
16-bit
Reload Timer
4 channels
AVCC
TIN3 to TIN0
TOT3 to TOT0
AVSS
AN23 to AN0
8/10-bit
A/D
converter
24 channels
AVRH
AVRL
ADTG
AD15 to AD00
A23 to A16
ALE
RD
WRL
WRH
HRQ
10-bit
D/A converter
2 channels
External
Bus
DA01, DA00
8/16-bit
PPG
16 channels
HAK
RDY
CLK
PPGF to PPG0
I2C
interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/
External
Interrupt
DMA
Clock
Monitor
CKOT
* : Only for MB90V340A-104
17
MB90360 Series
• MB90F362/T/S/TS, MB90362/T/S/TS, MB90F367/T/S/TS, MB90367/T/S/TS
X0, X1
Clock
Controller/
monitor *3
F2MC-16LX
Core
X0A, X1A*1
RST
CR
oscillator
circuit
Input
Capture
4 channels
IN0 to IN3
FRCK0
Low voltage detection *2
16-bit
I/O
Timer 0
CPU operation detection *2
RAM
3 Kbytes
CAN
RX1
TX1
controller
1 channels
ROM
64 Kbytes
16-bit
Reload
TIN2, TIN3
TOT2, TOT3
Timer
2 channels
Prescaler
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
UART
2 channels
AVCC
AVSS
AN15 to AN0
8/10-bit
A/D
converter
16 channels
AVR
ADTG
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
DTP/
External
Interrupt
8/16-bit
PPG
2 channels
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
*1 : Only for devices without S-suffix
*2 : Only for devices with T-suffix
*3 : CR oscillation circuit/clock monitor correspond to MB90F367/T/S/TS and MB90367/T/S/TS only.
18
MB90360 Series
■ MEMORY MAP
MB90F362/T/S/TS
MB90362/T/S/TS
MB90F367/T/S/TS
MB90367/T/S/TS
MB90V340A-101/102/103/104
FFFFFFH
FFFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM (FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
010000H
00FFFFH
ROM (image
of FF bank)
ROM (image
of FF bank)
008000H
007FFFH
008000H
007FFFH
Peripheral
Peripheral
007900H
007900H
0078FFH
RAM 30 Kbytes
000CFFH
000100H
RAM 3 Kbytes
Peripheral
000100H
0000FFH
0000F0H
0000EFH
000000H
0000EFH
000000H
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using
the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
19
MB90360 Series
■ I/O MAP
(Address : 000000H-0000FFH)
Abbrevia-
tion
Address
Register
Access
Resource name Initial value
000000H,
000001H
Reserved
000002H Port 2 Data Register
000003H Reserved
PDR2
R/W
Port 2
XXXXXXXXB
000004H Port 4 Data Register
000005H Port 5 Data Register
000006H Port 6 Data Register
000007H Reserved
PDR4
PDR5
PDR6
R/W
R/W
R/W
Port 4
Port 5
Port 6
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
000008H Port 8 Data Register
PDR8
R/W
Port 8
XXXXXXXXB
000009H,
Reserved
00000AH
00000BH Port 5 Analog Input Enable Register
00000CH Port 6 Analog Input Enable Register
00000DH Reserved
ADER5
ADER6
R/W
R/W
Port 5, A/D
Port 6, A/D
11111111B
11111111B
00000EH Input Level Select Register
00000FH Input Level Select Register
ILSR0
ILSR1
R/W
R/W
Ports
Ports
XXXX0XXXB
XXXXXXXXB
000010H,
Reserved
000011H
000012H Port 2 Direction Register
000013H Reserved
DDR2
R/W
Port 2
00000000B
000014H Port 4 Direction Register
000015H Port 5 Direction Register
000016H Port 6 Direction Register
000017H Reserved
DDR4
DDR5
DDR6
R/W
R/W
R/W
Port 4
Port 5
Port 6
XXX00000B
00000000B
00000000B
000018H Port 8 Direction Register
000019H Reserved
DDR8
DDRA
R/W
W
Port 8
Port A
000000X0B
00001AH Port A Direction Register
XXX00XXXB
00001BH
to
Reserved
00001DH
00001EH Port 2 Pull-up Control Register
00001FH Reserved
PUCR2
R/W
Port 2
00000000B
(Continued)
20
MB90360 Series
Abbrevia-
tion
Address
Register
Access
Resource name Initial value
000020H Serial Mode Register 0
000021H Serial Control Register 0
SMR0
SCR0
W, R/W
W, R/W
00000000B
00000000B
RDR0/
TDR0
000022H Reception/Transmission Data Register 0
000023H Serial Status Register 0
R/W
00000000B
SSR0
R, R/W
00001000B
UART0
Extended Communication Control
R, W,
R/W
000024H
ECCR0
000000XXB
Register 0
000025H Extended Status/Control Register 0
000026H Baud Rate Generator Register 00
000027H Baud Rate Generator Register 01
000028H Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
R/W, R
R/W, R
W, R/W
W, R/W
000029H Serial Control Register 1
SCR1
RDR1/
TDR1
00002AH Reception/Transmission Data Register 1
R/W
00000000B
00002BH Serial Status Register 1
SSR1
R, R/W
00001000B
UART1
Extended Communication Control
R, W,
R/W
00002CH
ECCR1
000000XXB
Register 1
00002DH Extended Status/Control Register 1
00002EH Baud Rate Generator Register 10
00002FH Baud Rate Generator Register 11
000030H
ESCR1
BGR10
BGR11
R/W
00000100B
00000000B
00000000B
R/W, R
R/W, R
to
Reserved
00003AH
Address Match
00000000B
00003BH Address Detect Control Register 1
PACSR1
R/W
Detection 1
00003CH
to
Reserved
000047H
000048H PPG C Operation Mode Control Register PPGCC
000049H PPG D Operation Mode Control Register PPGCD
PPG C/PPG D Count Clock Select
Register
00004BH Reserved
W, R/W
W, R/W
0X000XX1B
0X000001B
16-bit PPG C/D
00004AH
PPGCD
R/W
000000X0B
00004CH PPG E Operation Mode Control Register PPGCE
00004DH PPG F Operation Mode Control Register PPGCF
PPG E/PPG F Count Clock Select
Register
00004FH Reserved
W, R/W
W, R/W
0X000XX1B
0X000001B
16-bit PPG E/F
00004EH
PPGEF
R/W
000000X0B
(Continued)
21
MB90360 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
000050H Input Capture Control Status 0/1
000051H Input Capture Edge 0/1
000052H Input Capture Control Status 2/3
000053H Input Capture Edge 2/3
000054H
ICS01
ICE01
ICS23
ICE23
R/W
R/W, R
R/W
R
00000000B
XXX0X0XXB
00000000B
Input Capture 0/1
Input Capture 2/3
XXXXXXXXB
to
Reserved
000063H
000064H Timer Control Status 2
000065H Timer Control Status 2
000066H Timer Control Status 3
000067H Timer Control Status 3
000068H A/D Control Status 0
000069H A/D Control Status 1
00006AH A/D Data 0
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
R/W
R/W
R/W
R/W
R/W
R/W, W
R
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
16-bit Reload Timer
2
16-bit Reload Timer
3
A/D Converter
00006BH A/D Data 1
R
00006CH ADC Setting 0
R/W
R/W
00006DH ADC Setting 1
Low voltage/CPU
R/W, W operation detection
reset
Low Voltage/CPU Operation Detection
Reset Control Register
00006EH
LVRC
00111000B
00006FH ROM Mirror Function Select
000070H
ROMM
W
ROM Mirror
XXXXXXX1B
to
Reserved
00007FH
000080H
to
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
00008FH
000090H
to
Reserved
00009DH
Address Match
Detection 0
00009EH Address Detect Control Register 0
00009FH Delayed Interrupt/Release Register
PACSR0
DIRR
R/W
R/W
00000000B
Delayed Interrupt
generation module
XXXXXXX0B
Low-Power
consumption
Control Circuit
Low-power Consumption Mode
0000A0H
LPMCR
CKSCR
W, R/W
R, R/W
00011000B
Control Register
Low-Power
consumption
Control Circuit
0000A1H Clock Selection Register
11111100B
(Continued)
22
MB90360 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000A2H
to
Reserved
0000A7H
0000A8H Watchdog Control Register
0000A9H Timebase Timer Control Register
0000AAH Watch Timer Control register
0000ABH
WDTC
TBTC
WTC
R, W
Watchdog Timer
Timebase Timer
Watch Timer
XXXXX111B
1XX00100B
1X001000B
W, R/W
R, R/W
to
Reserved
0000ADH
Flash Control Status
0000AEH (Flash Devices only.
Otherwise reserved)
FMCS
R, R/W
Flash Memory
000X0000B
0000AFH Reserved
0000B0H Interrupt Control Register 00
0000B1H Interrupt Control Register 01
0000B2H Interrupt Control Register 02
0000B3H Interrupt Control Register 03
0000B4H Interrupt Control Register 04
0000B5H Interrupt Control Register 05
0000B6H Interrupt Control Register 06
0000B7H Interrupt Control Register 07
0000B8H Interrupt Control Register 08
0000B9H Interrupt Control Register 09
0000BAH Interrupt Control Register 10
0000BBH Interrupt Control Register 11
0000BCH Interrupt Control Register 12
0000BDH Interrupt Control Register 13
0000BEH Interrupt Control Register 14
0000BFH Interrupt Control Register 15
0000C0H
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
Interrupt Control
to
Reserved
0000C9H
0000CAH External Interrupt Enable 1
0000CBH External Interrupt Source 1
ENIR1
EIRR1
R/W
R/W
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
(Continued)
0000CCH
External Interrupt 1
Detection Level Setting 1
0000CDH
ELVR1
EISSR
R/W
R/W
0000CEH External Interrupt Source Select
23
MB90360 Series
(Continued)
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
0000CFH PLL/Subclock Control Register
0000D0H
PSCCR
W
PLL
XXXX0000B
to
Reserved
0000FFH
24
MB90360 Series
(Address : 7900H-7FFFH)
Address
Abbrevia-
tion
Register
Access
Resource name
Initial value
7900H
to
Reserved
7917H
7918H
7919H
Reload Register LC
Reload Register HC
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 2/3
791AH Reload Register LD
791BH Reload Register HD
791CH Reload Register LE
791DH Reload Register HE
791EH Reload Register LF
791FH Reload Register HF
7920H
7921H
7922H
7923H
7924H
7925H
7926H
7927H
Input Capture 0
Input Capture 0
Input Capture 1
Input Capture 1
Input Capture 2
Input Capture 2
Input Capture 3
Input Capture 3
R
R
R
R
R
R
R
7928H
to
Reserved
793FH
7940H
7941H
7942H
7943H
Timer Data 0
TCDT0
TCDT0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
0XXXXXXXB
Timer Data 0
I/O Timer 0
Timer Control Status 0
Timer Control Status 0
TCCSL0
TCCSH0
7944H
to
Reserved
794BH
794CH
794DH
794EH
794FH
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
TMR2/
TMRLR2
16-bit Reload
Timer 2
Timer 2/Reload 2
Timer 3/Reload 3
TMR3/
TMRLR3
16-bit Reload
Timer 3
7950H
to
Reserved
795FH
(Continued)
25
MB90360 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
Clock Monitor Function Control
Register
7960H
CSVCR
R, R/W
Clock monitor
00011100B
7961H
to
Reserved
796DH
CAN Direct Mode Register
(MB90V340 only)
796EH
CDMR
R/W
CAN clock sync
XXXXXXX0B
796FH
to
Reserved
79DFH
79E0H Detect Address Setting 0
79E1H Detect Address Setting 0
79E2H Detect Address Setting 0
79E3H Detect Address Setting 1
79E4H Detect Address Setting 1
79E5H Detect Address Setting 1
79E6H Detect Address Setting 2
79E7H Detect Address Setting 2
79E8H Detect Address Setting 2
79E9H
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
to
Reserved
79EFH
79F0H Detect Address Setting 3
79F1H Detect Address Setting 3
79F2H Detect Address Setting 3
79F3H Detect Address Setting 4
79F4H Detect Address Setting 4
79F5H Detect Address Setting 4
79F6H Detect Address Setting 5
79F7H Detect Address Setting 5
79F8H Detect Address Setting 5
79F9H
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
to
Reserved
7BFFH
7C00H
to
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
7CFFH
(Continued)
26
MB90360 Series
(Continued)
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
7D00H
to
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
7DFFH
7E00H
to
Reserved
7FFFH
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
27
MB90360 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbps/s to 2 Mbps/s (when input clock is at 16 MHz)
List of Control Registers (1)
Address
Register
Abbreviation
BVALR
TREQR
TCANR
TCR
Access
R/W
R/W
W
Initial Value
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
Message buffer
valid register
00000000B
00000000B
Transmit request
register
00000000B
00000000B
Transmit cancel
register
00000000B
00000000B
Transmission
complete register
00000000B
00000000B
R/W
R/W
R/W
R/W
R/W
Receive complete
register
00000000B
00000000B
RCR
Remote request
receiving register
00000000B
00000000B
RRTRR
ROVRR
RIER
Receive overrun
register
00000000B
00000000B
Reception interrupt
enable register
00000000B
00000000B
28
MB90360 Series
List of Control Registers (2)
Abbreviation
Address
CAN1
Register
Access
Initial Value
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
Control status
register
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
CSR
LEIR
Last event
indicator register
000X0000B
XXXXXXXXB
R/W
R
Receive and transmit
error counter
00000000B
00000000B
RTEC
BTR
Bit timing
register
11111111B
X1111111B
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
IDE register
IDER
Transmit RTR
register
00000000B
00000000B
TRTRR
Remote frame
receive waiting
register
XXXXXXXXB
XXXXXXXXB
RFWTR
TIER
R/W
R/W
007D0DH
007D0EH
007D0FH
007D10H
007D11H
007D12H
007D13H
007D14H
007D15H
007D16H
007D17H
007D18H
007D19H
007D1AH
007D1BH
Transmit interrupt
enable register
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
Acceptance mask
select register
AMSR
AMR0
AMR1
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance mask
register 0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance mask
register 1
XXXXXXXXB
XXXXXXXXB
29
MB90360 Series
List of Message Buffers (ID Registers) (1)
Address
Register
Abbreviation
Access
Initial Value
CAN1
007C00H
to
007C1FH
XXXXXXXXB
to
XXXXXXXXB
General-purpose RAM
⎯
R/W
007C20H
007C21H
007C22H
007C23H
007C24H
007C25H
007C26H
007C27H
007C28H
007C29H
007C2AH
007C2BH
007C2CH
007C2DH
007C2EH
007C2FH
007C30H
007C31H
007C32H
007C33H
007C34H
007C35H
007C36H
007C37H
007C38H
007C39H
007C3AH
007C3BH
007C3CH
007C3DH
007C3EH
007C3FH
XXXXXXXXB
XXXXXXXXB
ID register 0
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
ID register 7
IDR0
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
30
MB90360 Series
List of Message Buffers (ID Registers) (2)
Address
CAN1
Register
Abbreviation
Access
Initial Value
007C40H
007C41H
007C42H
007C43H
007C44H
007C45H
007C46H
007C47H
007C48H
007C49H
007C4AH
007C4BH
007C4CH
007C4DH
007C4EH
007C4FH
007C50H
007C51H
007C52H
007C53H
007C54H
007C55H
007C56H
007C57H
007C58H
007C59H
007C5AH
007C5BH
007C5CH
007C5DH
007C5EH
007C5FH
XXXXXXXXB
XXXXXXXXB
ID register 8
ID register 9
ID register 10
ID register 11
ID register 12
ID register 13
ID register 14
ID register 15
IDR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR15
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
31
MB90360 Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
CAN1
Register
Abbreviation
DLCR0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
32
MB90360 Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
CAN1
Register
Abbreviation
Access
Initial Value
007C80H
to
007C87H
XXXXXXXXB
to
XXXXXXXXB
Data register 0
(8 bytes)
DTR0
R/W
007C88H
to
007C8FH
XXXXXXXXB
to
XXXXXXXXB
Data register 1
(8 bytes)
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
007C90H
to
007C97H
XXXXXXXXB
to
XXXXXXXXB
Data register 2
(8 bytes)
007C98H
to
007C9FH
XXXXXXXXB
to
XXXXXXXXB
Data register 3
(8 bytes)
007CA0H
to
007CA7H
XXXXXXXXB
to
XXXXXXXXB
Data register 4
(8 bytes)
007CA8H
to
007CAFH
XXXXXXXXB
to
XXXXXXXXB
Data register 5
(8 bytes)
007CB0H
to
007CB7H
XXXXXXXXB
to
XXXXXXXXB
Data register 6
(8 bytes)
007CB8H
to
007CBFH
XXXXXXXXB
to
XXXXXXXXB
Data register 7
(8 bytes)
007CC0H
to
007CC7H
XXXXXXXXB
to
XXXXXXXXB
Data register 8
(8 bytes)
007CC8H
to
007CCFH
XXXXXXXXB
to
XXXXXXXXB
Data register 9
(8 bytes)
007CD0H
to
007CD7H
XXXXXXXXB
to
XXXXXXXXB
Data register 10
(8 bytes)
007CD8H
to
007CDFH
XXXXXXXXB
to
XXXXXXXXB
Data register 11
(8 bytes)
007CE0H
to
007CE7H
XXXXXXXXB
to
XXXXXXXXB
Data register 12
(8 bytes)
007CE8H
to
007CEFH
XXXXXXXXB
to
XXXXXXXXB
Data register 13
(8 bytes)
33
MB90360 Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
CAN1
Register
Abbreviation
Access
Initial Value
007CF0H
to
007CF7H
XXXXXXXXB
to
XXXXXXXXB
Data register 14
(8 bytes)
DTR14
R/W
007CF8H
to
007CFFH
XXXXXXXXB
to
XXXXXXXXB
Data register 15
(8 bytes)
DTR15
R/W
34
MB90360 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
Number Address
EI2OS
corresponding
register
Interrupt cause
Number
Address
Reset
N
N
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
N
Reserved
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
Reserved
N
CAN 1 reception
CAN 1 transmission/node status
Reserved
N
N
N
Reserved
N
Reserved
N
Reserved
N
16-bit reload timer 2
16-bit reload timer 3
Reserved
Y1
Y1
N
Reserved
N
PPG C/D
N
PPG E/F
N
Timebase timer
External interrupt 8 to 11
Watch timer
N
Y1
N
External interrupt 12 to 15
A/D converter
I/O timer 0
Y1
Y1
N
Reserved
N
Reserved
N
Input capture 0 to 3
Reserved
Y1
N
UART 0 reception
UART 0 transmission
UART 1 reception
UART 1 transmission
Y2
Y1
Y2
Y1
0000BDH
(Continued)
35
MB90360 Series
(Continued)
Interrupt control
register
Interrupt vector
Number Address
EI2OS
corresponding
Interrupt cause
Number
Address
Reserved
N
N
N
N
#39
#40
#41
#42
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR14
0000BEH
Reserved
Flash memory
ICR15
0000BFH
Delayed interrupt generation module
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When 2 peripheral resources share the ICR register, only one can use extended intelligent I/O service
at a time.
• When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O
service, the other one cannot use interrupts.
36
MB90360 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
AVR
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
V
V
V
Power supply voltage*1
VCC = AVCC*2
AVCC ≥ AVR*2
Input voltage*1
*3
*3
Output voltage*1
VO
Maximum clamp current
Total Maximum clamp current
ICLAMP
Σ|ICLAMP|
IOL1
−2.0
⎯
+2.0
40
mA *6
mA *6
mA *4
mA *5
mA *4
mA *5
mA *4
mA *5
⎯
15
“L” level maximum output current
“L” level average output current
IOL2
⎯
40
IOLAV1
IOLAV2
ΣIOL1
⎯
4
⎯
30
⎯
125
160
“L” level maximum overall output current
ΣIOL2
⎯
ΣIOLAV1
ΣIOLAV2
ΣIOLAV1
ΣIOLAV2
IOH1
*4 +105 °C < TA ≤ +125 °C
⎯
⎯
40
40
mA
mA
*5 +105 °C < TA ≤ +125 °C
*4 −40 °C ≤ TA ≤ +105 °C
*5 −40 °C ≤ TA ≤ +105 °C
“L” level average overall output current
⎯
⎯
⎯
⎯
⎯
⎯
−15
−40
−4
mA *4
mA *5
mA *4
mA *5
mA *4
mA *5
“H” level maximum output current
“H” level average output current
IOH2
IOHAV1
IOHAV2
ΣIOH1
ΣIOH2
ΣIOHAV1
ΣIOHAV2
ΣIOHAV1
ΣIOHAV2
−30
−125
−160
“H” level maximum overall output current
*4 +105 °C < TA ≤ +125 °C
⎯
−40
mA
mA
*5 +105 °C < TA ≤ +125 °C
*4 −40 °C ≤ TA ≤ +105 °C
*5 −40 °C ≤ TA ≤ +105 °C
“H” level average overall output current
Power consumption
⎯
⎯
−40
MB90F362/T/S/TS,
MB90F367/T/S/TS
PD
300
mW
−40
−40
−55
+105
+125
+150
°C
Operating temperature
Storage temperature
TA
°C *7
°C
TSTG
(Continued)
37
MB90360 Series
(Continued)
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P24 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
*5 : Applicable to pins : P20 to P23
*6 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits :
• Input/output equivalent circuits
Protective diode
VCC
Limiting
Pch
resistance
+B input (0 V to 16 V)
Nch
R
*7 : If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB90360 Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Remarks
Value
Typ
Parameter
Symbol
Unit
Min
Max
4.0
5.0
5.5
V
Under normal operation
Under normal operation when not
using the A/D converter and not
Flash programming.
VCC,
AVCC
Power supply voltage
3.5
3.0
5.0
5.5
5.5
V
V
⎯
Maintains RAM data in stop mode
Use a ceramic capacitor or capac-
itor of better AC characteristics.
Bypass capacitor at the VCC pin
should be greater than this capac-
itor.
Smooth capacitor
CS
TA
0.1
⎯
1.0
µF
−40
−40
⎯
⎯
+105
+125
°C
°C
Operating temperature
*
* : If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
39
MB90360 Series
3. DC Characteristics
Sym-
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
Pin inputs if
VIHA
⎯
⎯
⎯
⎯
0.8 VCC
0.7 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
Automotive input
levels are selected
Input “H”
voltage
P82, P85
inputs if CMOS input
levels are selected
VIHS
RST input pin (CMOS
hysteresis)
VIHR
VIHM
⎯
⎯
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VCC − 0.3
MD input pin
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
Pin inputs if
VILA
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.5 VCC
0.3 VCC
V
V
Automotive input
levels are selected
Input “L”
voltage
P82, P85
inputs if CMOS input
levels are selected
VILS
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VCC − 0.5
⎯
⎯
⎯
0.2 VCC
VSS + 0.3
⎯
V
V
V
MD input pin
Output “H”
voltage
Other than VCC = 4.5 V,
P20 to P23 IOH = −4.0 mA
Output “H”
voltage
VCC = 4.5 V,
VOHI P20 to P23
VCC − 0.5
⎯
⎯
⎯
⎯
50
50
⎯
0.4
0.4
1
V
V
IOH = −14.0 mA
Output “L”
voltage
Other than VCC = 4.5 V,
P20 to P23 IOL = 4.0 mA
VOL
⎯
⎯
−1
25
25
Output “L”
voltage
VCC = 4.5 V,
IOL = 20.0 mA
VOLI P20 to P23
V
Input leak
current
VCC = 5.5 V, VSS
< VI < VCC
IIL
⎯
µA
kΩ
kΩ
Pull-up
resistance
P20 to P27,
RST
RUP
⎯
⎯
100
100
Pull-down
resistance
Except Flash
devices
RDOWN
MD2
(Continued)
40
MB90360 Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
⎯
⎯
⎯
⎯
35 45 mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing FLASH memory.
ICC
50 60 mA Flash devices
50 60 mA Flash devices
12 20 mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing FLASH memory.
VCC = 5.0 V,
Internal frequency : 24 MHz,
At sleep mode.
ICCS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At main timer mode
⎯
⎯
0.3 0.8
0.4 1.0
Without T model
With T model
ICTS
mA
mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL timer mode,
ICTSPLL6
⎯
4
7
External frequency = 4 MHz
Stopping clock
monitor function
MB90F362, MB90F367,
MB90362, MB90367
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
40 100
60 150
90 200
110 250
10 50
30 100
60 150
80 200
Power supply
current*
VCC
VCC = 5.0 V
Operating clock
Internalfrequency:
monitor function
MB90F367, MB90367
ICCL
8 kHz,
At sub operation,
TA = +25°C
µA
µA
µA
Stopping clock
monitor function
MB90F362T, MB90F367T,
MB90362T, MB90367T
Operating clock
monitor function
MB90F367T, MB90367T
Stopping clock
monitor function
MB90F362, MB90F367,
MB90362, MB90367
VCC = 5.0 V
Operating clock
Internalfrequency:
monitor function
MB90F367, MB90367
ICCLS
8 kHz,
At sub sleep,
TA = +25°C
Stopping clock
monitor function
MB90F362T, MB90F367T,
MB90362T, MB90367T
Operating clock
monitor function
MB90F367T, MB90367T
Stopping clock
monitor function
MB90F362, MB90F367,
MB90362, MB90367
8
30
VCC = 5.0 V
Operating clock
Internalfrequency:
monitor function
30 70
60 130
80 170
MB90F367, MB90367
ICCT
8 kHz,
At watch mode,
TA = +25°C
Stopping clock
monitor function
MB90F362T, MB90F367T,
MB90362T, MB90367T
Operating clock
monitor function
MB90F367T, MB90367T
⎯
⎯
5
25
µA Without T model
VCC = 5.0 V,
At stop mode, TA = +25°C
ICCH
50 130 µA With T model
* : The power supply current is measured with an external clock.
(Continued)
41
MB90360 Series
(Continued)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
Other than
AVCC, AVSS,
AVR, VCC, VSS,
C
Input capacity
CIN
⎯
⎯
5
15
pF
42
MB90360 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
1/2 when PLL stops,
When using an oscillation circuit
3
⎯
16
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL × 1,
When using an oscillation circuit
4
4
4
4
4
3
4
4
4
4
4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
16
12
8
PLL × 2,
When using an oscillation circuit
X0, X1
PLL × 3,
When using an oscillation circuit
PLL × 4,
When using an oscillation circuit
6
PLL × 6,
When using an oscillation circuit
4
fC
Clock frequency
1/2 when PLL stops,
When using an external clock
24
24
12
8
PLL × 1,
When using an external clock
PLL × 2,
When using an external clock
X0, X1
PLL × 3,
When using an external clock
PLL × 4,
When using an external clock
6
PLL × 6,
When using an external clock
4
MHz
kHz
fCL
X0A, X1A
X0, X1
—
32.768 100
62.5
⎯
⎯
333
333
—
ns When using an oscillation circuit
ns When using an external clock
µs
tCYL
Clock cycle time
X0, X1 41.67
X0A, X1A 10
tCYLL
30.5
⎯
PWH, PWL
PWHL, PWLL
X0
10
5
⎯
ns
Input clock pulse width
Duty ratio is about 30% to 70%.
µs
X0A
15.2
⎯
Input clock rise and fall
time
tCR, tCF
X0
⎯
⎯
5
ns When using external clock
Internal operating clock
frequency (machine
clock)
fCP
⎯
⎯
1.5
⎯
24
50
MHz When using main clock
kHz When using sub clock
fCPL
⎯
8.192
tCP
⎯
⎯
41.67
20
⎯
666
ns When using main clock
Internal operating clock
cycle time (machine clock)
tCPL
122.1
⎯
µs When using sub clock
43
MB90360 Series
• Clock Timing
t
CYL
0.8 VCC
0.2 VCC
X0
P
WH
PWL
t
CF
tCR
t
CYLL
0.8 VCC
0.2 VCC
X0A
P
WHL
PWLL
t
CF
tCR
44
MB90360 Series
• Guaranteed PLL Operation Range
Guaranteed operation range
5.5
4.0
3.5
Guaranteed A/D converter
operation range
Guaranteed PLL operation range
1.5
4
24
Internal clock fCP (MHz)
Guaranteed operation range of MB90360 series
Guaranteed oscillation frequency range
× 6 × 4
× 3
× 2
× 1
24
16
12
8
×1/2
(PLL off)
4.0
1.5
3
4
8
12
24
16
External clock fC (MHz) *
* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz.
45
MB90360 Series
(2) Reset Standby Input
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter Symbol
Pin
Unit
Remarks
Min
Max
500
⎯
ns
Under normal operation
In stop mode, sub clock
mode, sub sleep mode
and watch mode
Reset input
tRSTL
Oscillation time of oscillator*
RST
⎯
⎯
ns
time
+ 100 µs
100
µs
In timebase timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs and several ms. With an external clock, the oscillation time is 0 ms.
• Under normal operation :
t
RSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, sub clock mode, sub sleep mode, watch mode :
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
46
MB90360 Series
(3) Power-on Reset
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
30
Power on rise time
Power off time
tR
VCC
VCC
ms
⎯
tOFF
⎯
ms Due to repetitive operation
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power-on reset may occur.
We recommend that you start up smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
Holds RAM data
3 V
VSS
47
MB90360 Series
(4) UART0/1
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
tSCYC
tSLOV
tIVSH
tSHIX
Pin
Condition
Unit Remarks
Min
Max
Serial clock cycle time
SCK0, SCK1
8 tCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
−80
100
60
+80
⎯
Internal shift clock
mode output pins
are
SCK0, SCK1,
SIN0, SIN1
Valid SIN → SCK ↑
ns
ns
C = 80 pF + 1 TTL.
L
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0, SCK1
SCK0, SCK1
4 tCP
4 tCP
⎯
⎯
ns
ns
SCK0, SCK1, External shift clock
SOT0, SOT1 mode output pins
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
⎯
60
60
150
⎯
ns
ns
ns
are
SCK0, SCK1,
SIN0, SIN1
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
⎯
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
VIH
VIL
VIH
VIL
48
MB90360 Series
• External Shift Clock Mode
t
SLSH
t
SHSL
V
IH
V
IH
SCK
V
IL
VIL
t
SLOV
2.4 V
SOT
SIN
0.8 V
t
IVSH
t
SHIX
V
V
IH
IL
V
IH
IL
V
(5) Trigger Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
tTRGH
tTRGL
Input pulse width
⎯
5 tCP
⎯
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
V
IH
VIH
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
V
IL
VIL
t
TRGH
t
TRGL
49
MB90360 Series
(6) Timer Related Resource Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
tTIWH
tTIWL
TIN2, TIN3
IN0 to IN3
Input pulse width
⎯
4 tCP
⎯
ns
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.
VIH
VIH
VIL
VIL
TIN2, TIN3
IN0 to IN3
tTIWH
tTIWL
(7) Timer Related Resource Output Timing
(TA = –40°C to +125°C, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
TOT2, TOT3
PPGC to PPGF
CLK ↑ → TOUT change time
tTO
⎯
30
⎯
ns
2.4 V
CLK
2.4 V
0.8 V
TOT2, TOT3
PPGC to PPGF
tTO
50
MB90360 Series
5. A/D Converter
(T
Parameter
Resolution
A
= −40 °C to +125 °C, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Symbol
Pin
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
3.0
2.5
LSB
LSB
Nonlinearity error
⎯
⎯
Differential
nonlinearity error
⎯
⎯
⎯
⎯
1.9
LSB
Zero reading voltage
VOT
VFST
AN0 to AN15 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB
AN0 to AN15 AVR − 3.5 AVR − 1.5 AVR + 0.5 LSB
1.0
Full scale reading
voltage
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
16,500
µs
2.0
0.5
1.2
⎯
⎯
µs
∞
Analog port input
current
IAIN
VAIN
⎯
AN0 to AN15
AN0 to AN15
AVR
−0.3
AVSS
⎯
⎯
⎯
+0.3
AVR
AVCC
µA
V
Analog input
voltage range
Reference
voltage range
AVSS + 2.7
V
IA
IAH
IR
AVCC
AVCC
AVR
AVR
⎯
⎯
⎯
⎯
3.5
⎯
7.5
5
mA
µA
µA
µA
Power supply current
*
*
600
⎯
900
5
Reference
voltage supply current
IRH
Offset between
input channels
⎯
AN0 to AN15
⎯
⎯
4
LSB
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .
(Continued)
51
MB90360 Series
• About the external impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Comparator
Analog input
C
During sampling : ON
MB90F362/T/S/TS, MB90F367/T/S/TS
R
C
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
2.0 kΩ (Max)
8.2 kΩ (Max)
16.0 pF (Max)
16.0 pF (Max)
MB90362/T/S/TS, MB90367/T/S/TS, MB90V340A-101/102/103/104
R
C
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
2.0 kΩ (Max)
8.2 kΩ (Max)
14.4 pF (Max)
14.4 pF (Max)
Note : The values are reference values.
(Continued)
52
MB90360 Series
(Continued)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90362/T/S/TS,
MB90367/T/S/TS,
MB90V340A-101/102/103/104
MB90362/T/S/TS,
MB90367/T/S/TS,
MB90V340A-101/102/103/104
20
100
18
16
14
12
10
8
90
80
70
60
50
40
30
20
MB90F362/T/S/TS,
MB90F367/T/S/TS
MB90F362/T/S/TS,
MB90F367/T/S/TS
6
4
2
0
10
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
Minimum sampling time [µs]
• At 4.0 V ≤ AVCC < 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90362/T/S/TS,
MB90367/T/S/TS,
MB90V340A-101/102/103/104
MB90362/T/S/TS,
MB90367/T/S/TS,
MB90V340A-101/102/103/104
20
100
18
16
14
12
10
8
90
80
70
60
50
40
30
20
MB90F362/T/S/TS,
MB90F367/T/S/TS
MB90F362/T/S/TS,
MB90F367/T/S/TS
6
4
2
0
10
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
53
MB90360 Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” )
and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion
characteristics.
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
Total error
: Difference between an actual value and an theoretical value. A total error includes zero transi-
tion error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVR − AVSS
1 LSB = (Ideal value)
[V]
1024
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) to N.
(Continued)
54
MB90360 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
3FEH
3FDH
Actual conversion
characteristics
N + 1
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004H
003H
002H
001H
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVSS
AVR
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
55
MB90360 Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
• Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period = 0.5 µs)
• If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as
high as internal capacitor.
• If output impedance of an external circuit is too high, a sampling period for an analog voltage may be
insufficient.
• Analog input circuit model
Analog input
R
Comparator
C
4.5 V ≤ AVCC ≤ 5.5 V : R=: 2.52 kΩ, C=: 10.7 pF
4.0 V ≤ AVCC < 4.5 V : R=: 13.6 kΩ, C=: 10.7 pF
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics
Value
Parameter
Conditions
Unit
Remarks
Min
Typ
Max
Excludes programming
prior to erasure
Chip erase time
⎯
1
15
s
TA = +25 °C
VCC = 5.0 V
Word (16-bit width)
programming time
Except for the overhead
time of the system level
⎯
10,000
20
16
⎯
⎯
3,600
⎯
µs
Program/Erase cycle
⎯
cycle
Year
Flash memory data
retention time
Average
TA = +85 °C
⎯
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
56
MB90360 Series
■ ORDERING INFORMATION
Part number
MB90F362PMT
MB90F362TPMT
MB90F362SPMT
MB90F362TSPMT
MB90F367PMT
MB90F367TPMT
MB90F367SPMT
MB90F367TSPMT
MB90362PMT
Package
Remarks
48-pin Plastic LQFP
(FPT-48P-M26)
MB90362TPMT
MB90362SPMT
MB90362TSPMT
MB90367PMT
MB90367TPMT
MB90367SPMT
MB90367TSPMT
MB90V340A-101
MB90V340A-102
MB90V340A-103
MB90V340A-104
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
57
MB90360 Series
■ PACKAGE DIMENSION
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin Plastic LQFP
(FPT-48P-M26)
9.00±0.20(.354±.008)SQ
+0.40
7.00 –0.10 .276 –+..000146 SQ
0.145±0.055
(.006±.002)
*
36
25
37
24
Details of "A" part
0.08(.003)
1.50 –+00..1200
(Mounting height)
.059 –+..000048
INDEX
48
13
0.10±0.10
(.004±.004)
(Stand off)
"A"
0˚~8˚
1
12
LEAD No.
0.50(.020)
0.25(.010)
0.20±0.05
(.008±.002)
M
0.08(.003)
0.60±0.15
(.024±.006)
C
2003 FUJITSU LIMITED F48040S-c-2-2
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
58
MB90360 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0501
© 2005 FUJITSU LIMITED Printed in Japan
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