MB90F583C [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB90F583C |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总124页 (文件大小：2424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13710-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90580C Series
MB90583C/583CA/F583C/F583CA/587C/587CA/V580B
■ DESCRIPTION
The MB90580C series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control
applications which require high-speed real-time processing, such as consumer products.
While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the
MB90580C series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90580C has an on-chip 32-bit accumulator which
enables processing of long-word data.
The peripheral resources integrated in the MB90580C series include: an 8/10-bit A/D converter, an 8-bit D/A
converter, UARTs (SCI) 0 to 4, an 8/16-bit PPG timer, 16-bit I/O timers (16-bit free-run timer, input capture units
(ICUs) 0 to 3, output compare units (OCUs) 0 and 1), and an IEBusTM controller *2.
Notes: *1: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
*2: IEBusTM is a trademark of NEC Corporation.
■ FEATURES
• Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4
• Maximum memory space
16 Mbyte
Linear/bank access
(Continued)
■ PACKAGES
100-pin plastic LQFP
100-pin plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90580C Series
(Continued)
• Instruction set optimized for controller applications
Supported data types: bit, byte, word, and long-word types
Standard addressing modes: 23 types
32-bit accumulator enhancing high-precision operations
Signed multiplication/division and extended RETI instructions
• Enhanced high level language (C) and multitasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4 byte instruction queue
• Enhanced interrupt function
Up to eight priority levels programmable
External interrupt inputs: 8 lines
• Automatic data transmission function independent of CPU operation
Up to 16 channels for the extended intelligent I/O service
DTP request inputs: 8 lines
• Internal ROM
FLASH: 128 Kbyte
MASKROM: 128 Kbyte (MB90583C/CA) , 64 Kbyte (MB90587C/CA)
• Internal RAM
FLASH: 6 Kbyte
MASKROM: 6 Kbyte (MB90583C/CA) , 4 Kbyte (MB90587C/CA)
• General-purpose ports
Up to 77 channels (Input pull-up resistor settable for: 22 channels. Output open drain settable for: 8 channels)
• IEBusTM controller*
Three different data transfer rates selectable
Mode 0: 3.9 Kbps (16 bytes/frame)
Mode 1: 17.0 Kbps (32 bytes/frame)
Mode 2: 26.0 Kbps (128 bytes/frame)
*: IEBusTM is a trademark of NEC Corporation.
• A/D Converter (RC) : 8 ch
8/10-bit resolution
Conversion time: 34.7 µs (Min.) , 12 MHz operation
• D/A Converter: 2 ch
8-bit resolutions
Setup time: 12.5 µs
• UART : 5 ch
• 8/16 bit PPG : 1 ch
8 bits × 2 channels: 16 bits × 1 channel: Mode switching function provided
• 16 bit reload timer: 3 ch
• 16-bit PWC timer: 1 channel
Noise filter provided. Available to pulse width counter
• 16 bit I/O timer
Input capture : 4 ch
Output compare : 2 ch
Free run timer: 1 ch
• Internal clock generator
• Time-base counter/watchdog timer: 18-bit
(Continued)
2
MB90580C Series
(Continued)
• Clock monitor function integrated
• Low-power consumption mode
Sleep mode
Stop mode
Hardware standby mode
CPU intermittent operation mode
• Package: LQFP-100 / QFP-100
• CMOS technology
3
MB90580C Series
■ PRODUCT LINEUP
Part number
MB90587C/CA
MB90583C/CA
MB90F583C/CA
MB90V580B
Item
Development/
evaluation
product
Mass-produced products
(MASK ROM)
Mass-produced products
(Flash ROM)
Classification
ROM size
RAM size
64 Kbytes
128 Kbytes
6 Kbytes
128 Kbytes
6 Kbytes
None
4 Kbytes
6 Kbytes
Two clocks /
one clock system one clock system
Two clocks /
Two clocks /
one clock system
Clock*1
Two clocks system
None
Emulator-specific
power supply *2
The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
CPU functions
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5 ms (at machine clock of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output)
General-purpose I/O port (Can be set as open-drain)
General-purpose I/O ports (Input pull-up resistors available)
Total:
: 45
: 8
: 22
: 77
Ports
Communication mode: Half-duplex, asynchronous communication
Multi-master system
Access control: CDMA/CD
Three modes selectable for different transmission speeds
Transmit buffer: 8-byte FIFO buffer
IEBusTM controller
None
Receive buffer: 8-byte FIFO buffer
18-bit counter
Timebase timer
Watchdog timer
Clock timer
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (At oscillation of 4 MHz)
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
15-bit counter
Interrupt interval: 1 s, 0.5 s, 0.25 s, 31.25 ms (At oscillation of 32.768 kHz)
Number of channels: 1 (8-bit × 2 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz)
8/16-bit PPG timer
Number of channels: 3
16-bit reload timer
PWC timer
Event count provided
Interval: 125 ns to 131 ms (at oscillation of 4 MHz, machine clock of 16 MHz)
Number of channels: 1
Timer function (select the counter timer from three internal clocks.)
Pulse width measuring function (select the counter timer from three internal clocks.)
(Continued)
4
MB90580C Series
(Continued)
Part number
MB90587C/CA
MB90583C/CA
MB90F583C/CA
MB90V580B
Item
Number of channels: 1
Overflow interrupts
16-bit
free run timer
16-bit
I/O
timer
Number of channels: 2
Pin input factor: A match signal of compare register
Output compare
(OCU)
Number of channels: 4
Input capture (ICU)
Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of inputs: 8
DTP/external interrupt circuit Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI2OS) can be used.
An interrupt generation module for switching tasks used in real time operating
systems.
Delayed interrupt generation
module
Clock synchronized transmission (62.5 Kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
UART0, 1, 2, 3, 4
Resolution: 8/10-bit changeable
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode
(converts two or more successive channels and can program up to 8 channels.)
Continuous conversion mode (converts selected channel repeatedly)
Stop conversion mode (converts selected channel and stop operation repeatedly)
A/D converter
D/A converter
8-bit resolution
Number of channels: 2 channels
Based on the R-2R system
Low-power consumption
(standby) mode
Sleep/stop/CPU intermittent operation/clock timer/hardware standby
Process
CMOS
4.5 V to 5.5 V*3
Power supply voltage for operation
*1: Connect the oscillator to both terminals XA0 and XA1 for MB90F587C / 583C / F583C.
*2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
*3: Varies with conditions such as the operating frequency (See section “■ ELECTRICAL CHARACTERISTICS”).
Assurance for the MB90V580B is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5
V, an operating temperature of 0 to +25 °C, and an operating frequency of 1 MHz to 16 MHz.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
FPT-100P-M05
MB90583C/CA
MB90587C/CA
MB90F583C/CA
FTP-100P-M06
: Available ×: Not available
Note: For more information about each package, see section “■ PACKAGE DIMENSIONS”.
5
MB90580C Series
■ DIFFERENCES AMONG PRODUCTS
Memory Size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V580B does not have an internal ROM, however, operations equivalent to chips with an internal
ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of
the development tool.
• In the MB90V580B, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to
mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)
• In the MB90583C/583CA/587C/587CA/F583C/F583CA, images from FF4000H to FFFFFFH are mapped to
bank 00, and FF0000H to FF3FFFH to bank FF only.
IEBusTM Controller
• MB90587C/CA does not have an IEBusTM Controller.
6
MB90580C Series
■ PIN ASSIGNMENT
(TOP VIEW)
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
1
2
3
4
5
75
74 PA1
73
72
71
70
RST
PA0
P97/POT
P96/PWC
P95/TOT2/OUT1
6
7
8
9
69 P94/TOT1/OUT0
P30/ALE
P31/RD
VSS
68
67
P93/TOT0/IN3
P92/TIN2/IN2
P32/WRL
P33/WRH 11
P34/HRQ 12
P35/HAK
P36/RDY
P37/CLK
P40/SIN0 16
P41/SOT0
10
66 P91/TIN1/IN1
65
64 RX
P90/TIN0/IN0
*
*
13
14
15
63
62
61
60
59
TX
P65/CKOT
P64/PPG0
P63/PPG1
P62/SCK2
17
P42/SCK0 18
P43/SIN1 19
58 P61/SOT2
57
P60/SIN2
P44/SOT1
VCC
P45/SCK1
20
21
22
56 P87/IRQ7
55 P86/IRQ6
54 P85/IRQ5
53 P84/IRQ4
52 P83/IRQ3
P46/ADTG 23
P47 24
25
51
C
P82/IRQ2
* : N.C. pin on the MB90587C/CA
(FPT-100P-M05)
7
MB90580C Series
(TOP VIEW)
80
79
78
77 RST
76
75
74
73
72
71
1
2
3
4
5
6
7
8
9
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
X0A
X1A
PA2
PA1
PA0
P97/POT
P96/PWC
P95/TOT2/OUT1
P94/TOT1/OUT0
10
11
12
70 P93/TOT0/IN3
69 P92/TIN2/IN2
P32/WRL
68
67
66
P33/WRH 13
P91/TIN1/IN1
P90/TIN0/IN0
14
P34/HRQ
*
P35/HAK 15
P36/RDY 16
P37/CLK 17
P40/SIN0 18
RX
*
65 TX
64 P65/CKOT
63 P64/PPG0
62 P63/PPG1
19
P41/SOT0
61
P42/SCK0 20
P43/SIN1 21
P44/SOT1 22
P62/SCK2
60 P61/SOT2
59
P60/SIN2
58 P87/IRQ7
VCC
23
P45/SCK1 24
P46/ADTG
57
56
55
54
53
52
51
P86/IRQ6
P85/IRQ5
P84/IRQ4
P83/IRQ3
P82/IRQ2
HST
25
P47 26
C
P71
27
28
P72 29
DVRH 30
MD2
* : N.C. pin on the MB90587C/CA
(FPT-100P-M06)
8
MB90580C Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
QFP*1 LQFP*2
82
83
52
77
80
81
50
75
X0
X1
A
A
C
B
Oscillator pin
Oscillator pin
HST
RST
Hardware standby input pin
Reset input pin
General-purpose I/O ports.
P00 to
P07
A pull-up resistor can be assigned (RD07 to RD00=“1”) by the pull-
up resistor setting register (RDR0). [These pins are disabled with
the output setting (DDR0 register: D07 to D00=“1”).]
D
85 to 92 83 to 90
(CMOS/H)
AD00 to
AD07
In external bus mode, the pins function as the lower data I/O or low-
er address outputs (AD00 to AD07).
General-purpose I/O ports.
P10 to
P17
A pull-up resistor can be assigned (RD17 to RD10=“1”) by the pull-
up resistor setting register (RDR1). [These pins are disabled with
the output setting (DDR1 register: D17 to D10 =“1”).]
93 to
D
91 to 98
100
(CMOS/H)
AD08 to
AD15
In 16-bit external bus mode, the pins function as the upper data
I/O or middle address outputs (AD08 to AD15).
General-purpose I/O ports
In external bus mode, pins for which the corresponding bit in the
HACR register is “1” function as the A16 to A23 pins.
P20 to
P27
99,100,
1 to 8
F
1 to 6
(CMOS/H)
In external bus mode, pins for which the corresponding bit in the
HACR register is “1” function as the upper address output pins
(A16 to A23).
A16 to
A23
General-purpose I/O port
Functions as the ALE pin in external bus mode.
P30
ALE
F
9
7
8
(CMOS/H)
Functions as the address latch enable signal pin (ALE) in external
bus mode.
General-purpose I/O port
Functions as the RD pin in external bus mode.
P31
RD
F
10
(CMOS/H)
Functions as the read strobe output pin (RD) in external bus mode.
General-purpose I/O port
Functions as the WRL pin in external bus mode if the WRE bit is
“1”.
P32
WRL
P33
F
12
13
10
11
(CMOS/H)
Functions as the lower data write strobe output pin (WRL) in
external bus mode.
General-purpose I/O port
Functions as the WRH pin in 16-bit external bus mode if the WRE
bit in the EPCR register is “1”
F
(CMOS/H)
Functions as the upper data write strobe output pin (WRH) in
external bus mode.
WRH
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
9
MB90580C Series
Pin no.
Circuit
Pin name
Function
type
QFP*1 LQFP*2
General-purpose I/O port
Functions as the HRQ pin in external bus mode if the HDE bit in the
EPCR register is “1”.
P34
HRQ
P35
F
14
15
16
17
12
13
14
15
(CMOS/H)
Functions as the hold request input pin (HRQ) in external bus mode.
General-purpose I/O port
Functions as the HAK pin in external bus mode if the HDE bit in the
EPCR register is “1”.
F
(CMOS/H)
Functions as the hold acknowledge output pin (HAK) in external bus
mode.
HAK
General-purpose I/O port
Functions as the RDY pin in external bus mode if the RYE bit in the
EPCR register is “1”.
P36
RDY
P37
F
(CMOS/H)
Functions as the external ready input pin (RDY) in external bus mode.
General-purpose I/O port
Functions as the CLK pin in external bus mode if the CKE bit in the
EPCR register is “1”.
F
(CMOS/H)
Functions as the machine cycle clock output pin (CLK) in external bus
mode.
CLK
P40
General-purpose I/O port.
This pin serves as an open-drain output port with OD40 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D40=“0”).]
E
18
16
(CMOS/H)
UART0 serial data input (SIN0) pin.
When UART0 is operating for input, this input is used as required and
thus the output from any other function to the pin must be off unless
used intentionally.
SIN0
General-purpose I/O port.
This pin serves as an open-drain output port with OD41 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D41=“0”).]
P41
SOT0
P42
E
19
20
17
18
(CMOS/H)
UART0 serial data output pin (SOT0).
This pin is enabled with the UART0 serial data output enabled.
General-purpose I/O port.
This pin serves as an open-drain output port with OD42 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D42=“0”).]
E
(CMOS/H)
UART0 serial clock I/O pin (SCK0).
This pin is enabled with the UART0 clock output enabled.
SCK0
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
10
MB90580C Series
Pin no.
Circuit
type
Pin name
Function
QFP*1 LQFP*2
General-purpose I/O port.
This pin serves as an open-drain output port with OD43 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D43=“0”).]
P43
E
21
19
(CMOS/H)
UART1 serial data input (SIN1) pin.
When UART1 is operating for input, this input is used as required and
thus the output from any other function to the pin must be off unless
used intentionally.
SIN1
General-purpose I/O port.
This pin serves as an open-drain output port with OD44 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D44=“0”).]
P44
SOT1
P45
E
22
24
20
22
(CMOS/H)
UART1 serial data output pin (SOT1).
This pin is enabled with the UART1 serial data output enabled.
General-purpose I/O port.
This pin serves as an open-drain output port with OD45 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D45=“0”).]
E
(CMOS/H)
UART1 serial clock I/O pin (SCK1).
This pin is enabled with the UART1 clock output enabled.
SCK1
General-purpose I/O port.
This pin serves as an open-drain output port with OD46 in the open-
drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D46=“0”).]
P46
ADTG
P47
E
25
26
23
24
(CMOS/H)
External trigger input pin (ADTG) for the A/D converter.
General-purpose I/O port.
This pin serves as an open-drain output port with OD47 in the open-
(CMOS/H) drain control setting register (ODR4) set to “1”. [The pin is disabled
with the input setting (DDR4 register: D47=“0”).]
E
P50
AN0
General-purpose I/O port.
Analog input pin (AN0) for use during A/D converter operation.
G
UART3 serial data input pin (SIN3).
When UART3 is operating for input, this input is used as required and
thus the output from any other function to the pin must be off unless
used intentionally.
38
36
(CMOS/H)
SIN3
P51
AN1
General-purpose I/O port.
G
Analog input pin (AN1) for use during A/D converter operation.
39
37
(CMOS/H)
UART3 serial data output pin (SOT3).
This pin is enabled with the UART3 serial data output enabled.
SOT3
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
11
MB90580C Series
Pin no.
Pin name Circuit type
Function
QFP*1 LQFP*2
P52
General-purpose I/O port.
AN2
G
Analog input pin (AN2) for use during A/D converter operation.
40
41
38
39
(CMOS/H)
UART3 serial clock I/O pin (SCK3).
This pin is enabled with the UART3 clock output enabled.
SCK3
P53
AN3
P54
AN4
General-purpose I/O port.
G
(CMOS/H)
Analog input pin (AN3) for use during A/D converter operation.
General-purpose I/O port.
Analog input pin (AN4) for use during A/D converter operation.
G
UART4 serial data input pin (SIN4).
43
44
41
42
(CMOS/H)
When UART4 is operating for input, this input is used as required
and thus the output from any other function to the pin must be off
unless used intentionally.
SIN4
P55
AN5
General-purpose I/O port.
G
Analog input pin (AN5) for use during A/D converter operation.
(CMOS/H)
UART4 serial data output pin (SOT4).
This pin is enabled with the UART4 serial data output enabled.
SOT4
P56
AN6
General-purpose I/O port.
G
Analog input pin (AN6) for use during A/D converter operation.
45
46
43
44
(CMOS/H)
UART4 serial clock output pin (SCK4).
This pin is enabled with the UART4 clock output enabled.
SCK4
P57
AN7
C
General-purpose I/O port.
G
(CMOS/H)
Analog input pin (AN7) for use during A/D converter operation.
0.1 µF capacitor coupling pin for regulating the power supply.
27
28
29
25
26
27
P71
P72
F (CMOS/H) General-purpose I/O port.
F (CMOS/H) General-purpose I/O port.
General-purpose I/O port.
P73
DA00
P74
This pin serves as a D/A output pin (DA00) when the DAE0 bit in
the D/A control register (DACR) is “1”.
H
32
30
(CMOS/H)
D/A converter output 0 (DA00) pin.
General-purpose I/O port.
This pin serves as a D/A output pin (DA01) when the DAE1 bit in
the D/A control register (DACR) is “1”.
H
33
47
31
45
(CMOS/H)
DA01
P80
D/A converter output 1 pin (DA01).
General-purpose I/O port.
F
(CMOS/H)
IRQ0
Functions as external interrupt request input 0 pin (IRQ0).
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
12
MB90580C Series
Pin no.
Pin name Circuit type
Function
QFP*1 LQFP*2
P81
IRQ1
P82
General-purpose I/O port.
F
48
53
54
55
56
57
58
46
51
52
53
54
55
56
(CMOS/H)
Functions as external interrupt request input 1 pin (IRQ1).
General-purpose I/O port.
F
(CMOS/H)
IRQ2
P83
Functions as external interrupt request input 2 pin (IRQ2).
General-purpose I/O port.
F
(CMOS/H)
IRQ3
P84
Functions as external interrupt request input 3 pin (IRQ3).
General-purpose I/O port.
F
(CMOS/H)
IRQ4
P85
Functions as external interrupt request input 4 pin (IRQ4).
General-purpose I/O port.
F
(CMOS/H)
IRQ5
P86
Functions as external interrupt request input 5 pin (IRQ5).
General-purpose I/O port.
F
(CMOS/H)
IRQ6
P87
Functions as external interrupt request input 6 pin (IRQ6).
General-purpose I/O port.
F
(CMOS/H)
IRQ7
Functions as external interrupt request input 7 pin (IRQ7).
General-purpose I/O port.
A pull-up resistor can be assigned (RD60=“1”) by the pull-up resistor
setting register (RDR6). [This pin is disabled with the output setting
(DDR6 register: D60=“1”).]
P60
D
59
57
(CMOS/H)
UART2 serial data input pin (SIN2).
When UART2 is operating for input, this input is used as required
and thus the output from any other function to the pin must be off
unless used intentionally.
SIN2
General-purpose I/O port.
A pull-up resistor can be assigned (RD61=“1”) by the pull-up resistor
setting register (RDR6). [This pin is disabled with the output setting
(DDR6 register: D61=“1”).]
P61
SOT2
P62
D
60
61
58
59
(CMOS/H)
UART2 serial data output pin (SOT2).
This pin is enabled with the UART2 serial data output enabled.
General-purpose I/O port.
A pull-up resistor can be assigned (RD62=“1”) by the pull-up resistor
setting register (RDR6). [This pin is disabled with the output setting
(DDR6 register: D62=“1”).]
D
(CMOS/H)
UART2 serial clock I/O pin (SCK2).
This pin is enabled with the UART2 clock output enabled.
SCK2
*1: FPT-100P-M06
*2: FPT-100P-M05
(Continued)
13
MB90580C Series
(Continued)
Pin no.
Pin name Circuit type
Function
QFP*1 LQFP*2
General-purpose I/O port.
A pull-up resistor can be assigned (RD63=“1”) by the pull-up resis-
tor setting register (RDR6). [This pin is disabled with the output set-
ting (DDR6 register: D63=“1”).]
P63
PPG1
P64
D
62
63
64
60
61
62
(CMOS/H)
The pin serves as the PPG1 output when PPGs are enabled.
General-purpose I/O port.
A pull-up resistor can be assigned (RD64=“1”) by the pull-up resis-
tor setting register (RDR6). [This pin is disabled with the output set-
ting (DDR6 register: D64=“1”).]
D
(CMOS/H)
PPG0
P65
The pin serves as the PPG0 output when PPGs are enabled.
General-purpose I/O port.
A pull-up resistor can be assigned (RD65=“1”) by the pull-up resis-
tor setting register (RDR6). [This pin is disabled with the output set-
ting (DDR6 register: D65=“1”).]
D
(CMOS/H)
CKOT
TX*3
This pin serves as the CKOT output during CKOT operation.
This pin serves as the IEBusTM output.
65
66
63
64
I
J
RX*3
This pin serves as the IEBusTM input.
(CMOS)
P90 to
P92
General-purpose I/O port.
Event input pins for reload timers 0, 1, and 2.
F
67 to 69 65 to 67 TIN0 to
TIN2
During reload timer input, these inputs are used continuously and
thus the output from any other function to the pins must be avoided
unless used intentionally.
(CMOS/H)
IN0 to IN2
P93
Trigger inputs for input capture channels 0 to 2
General-purpose I/O port.
F
Reload timer output pin. This function is applied when the output
70
68
TOT0
(CMOS/H) for reload timer 0 is enabled.
IN3
Trigger inputs for input capture channel 3.
P94, P95
General-purpose I/O port.
TOT1,
TOT2
Reload timer output pins. This function is applied when the output
for reload timer 1 and 2 are enabled.
F
71, 72 69, 70
(CMOS/H)
OUT0,
OUT1
Event output for channel 0 and 1 of the output compare
P96
General-purpose I/O port.
73
71
F (CMOS/H)
PWC
This pin serves as the PWC input with the PWC timer enabled.
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: N.C. pin on the MB90587C/CA.
(Continued)
14
MB90580C Series
(Continued)
Pin no.
Pin name Circuit type
Function
QFP*1 LQFP*2
P97
General-purpose I/O port.
74
72
F (CMOS/H)
POT
This pin serves as the PWC output with the PWC timer enabled.
75, 76 73, 74 PA0, PA1 F (CMOS/H) General-purpose I/O port.
78
76
PA2
F (CMOS/H) General-purpose I/O port.
Oscillation input pin.
A
79
77
X1A
Leave the terminal open for the one clock system parts.
Oscillation input pin.
Pull-down the terminal externally for the one clock system parts.
80
78
X0A
A
34
37
35
36
30
31
32
35
33
34
28
29
AVCC
AVSS
A/D converter power supply pin.
A/D converter power supply pin.
AVRH
AVRL
DVRH
DVSS
A/D converter external reference power supply pin.
A/D converter external reference power supply pin.
D/A converter external reference power supply pin.
D/A converter power supply pin.
MD0 to
MD2
Input pin for specifying the operation mode.
Connect these pins directly to Vcc or Vss.
49 to 51 47 to 49
C
23, 84 21, 82
11, 42, 9, 40,
VCC
Power supply (5 V) input pin.
VSS
Power supply (0 V) input pin.
81
79
*1: FPT-100P-M06
*2: FPT-100P-M05
15
MB90580C Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation feedback resistance
X1, X1A
X0, X0A
: Approx. 1 MΩ
Clock input
A
HARD,SOFT
STANDBY
CONTROL
• Hysteresis input with pull-up
Resistance approx. 50 kΩ
B
C
• Hysteresis input
• Incorporates pull-up resistor control
(for input)
• CMOS level output
Pull-up resistor
control
• Hysteresis input with standby control
Resistance approx. 50 kΩ
D
Standby control signal
(Continued)
16
MB90580C Series
Type
Circuit
Remarks
• CMOS level output
• Hysteresis input with standby control
• Incorporates open-drain control
• Open-drain
control signal
E
Standby control signal
• CMOS level output
• Hysteresis input with standby control
F
Standby control signal
• CMOS level output
• Hysteresis input with standby control
• Analog input
G
Analog input
Standby control signal
(Continued)
17
MB90580C Series
(Continued)
Type
Circuit
Remarks
• CMOS level output
• Hysteresis input with standby control
• DA output
H
DA output
Standby control signal
• CMOS level output
I
• CMOS input with standby control
J
Standby control signal
18
MB90580C Series
■ HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations:
• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.
• When a voltage exceeding the rating is applied between Vcc and Vss.
• When AVcc power is supplied prior to the Vcc voltage.
If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let it occur.
For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply
voltage.
2. Handling unused input pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
3. Treatment of the TX and RX pins with the IEBusTM unused
When the IEBus is not used, connect a pull-down resistor to the TX pin and a pull-down/pull-up resistor to the
RX pin.
4. Use of the external clock
When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration
below).
MB90580C series
X0
X1
Open
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to
lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in
the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via lowest impedance to power lines.
19
MB90580C Series
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90580C
Series
VCC
VSS
VCC
VSS
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand
area for stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVRH, AVRL) and analog inputs (AN0 to
AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage of AVRH dose not exceed AVCC (turning on/off the analog and digital power supplies simulta-
neously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
9. Connection of Unused Pins of D/A Converter
Connect unused pin of D/A converter to DVRH = VSS, DVSS = VSS.
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
µs or more (0.2 V to 2.7 V).
12. Use of the sub-clock
Use the one clock system parts when the sub-clock is not used. Connected the oscillator under 32 kHz to the
both terminals XA0 and X1A for the two clocks system parts. Pull-down the terminal X0A and leave the terminal
X0A open for the one clock system parts.
20
MB90580C Series
13. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during a power-on reset after the power is turned on.
Pay attention to the port output timing shown as follow.
Oscillation settling time*2
Power-on reset*1
VCC (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
Period of indeterminate
*1: Power-on reset time: Period of “clock frequency x 217” (Clock frequency of 16 MHz: 8.192 ms)
*2: Oscillation settling time: Period of “clock frequency x 218” (Clock frequency of 16 MHz: 16.384 ms)
14. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers
turning on the power again.
15. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may
fail to return from the standby state. In this case, reset the device via the external reset pin to return to the
normal state.
16. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, RWi’ Instructions
The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre-
sponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,
ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the
instruction will not be placed in the instruction operand register.
17. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used.
21
MB90580C Series
■ BLOCK DIAGRAM
X0, X1
X0A, X1A
RST
CPU Core of
F2MC-16LX family
Clock control
circuit
6
HST
Interrupt controller
CMOS I/O port A
RAM
ROM
3
3
PA0 to PA2
8
8
8
P00 to P07/
AD00 to AD07
P90 to P92/
TIN0 to TIN2/
IN0 to IN2
CMOS I/O port 0
I/O timer
16 bit ICU × 4 ch
16 bit OCU × 2 ch
16 bit free run timer
P10 to P17/
AD08 to AD15
CMOS I/O port 1
P93/
TOT0/
IN3
P20 to P27/
A16 to A23
CMOS I/O port 2
CMOS I/O port 3
P30/ALE
16 bit reload
timer × 3 ch
2
P94, P95/
P31/RD
P32/WRL
P33/WRH
P34/HRQ
P35/HAK
TOT1, TOT2/
OUT0, OUT1
Noise filter
P96/PWC
P97/POT
PWC timer
16 bit × 1 ch
P36/RDY
P37/CLK
Prescaler
× 2 ch
CMOS I/O port 9
Prescaler × 1 ch
UART × 1 ch
P47
UART
× 2 ch
3
3
SIN0, SOT0, SCK0/
P40 to P42
SIN1, SOT1, SCK1/
P43 to P45
2
2
3
P63, P64/
PPG1, PPG0
8 / 16 PPG × 1 ch
Clock monitor
P65/CKOT
ADTG / P46
SIN2, SOT2,
SCK2/
P60 to P62
8
8
CMOS I/O port 6
External interrupt
AVCC
AVRH, AVRL
AVSS
A/D converter
(8/10 bit)
8
2
P80 to P87/
IRQ0 to IRQ7
P71, P72
3
CMOS I/O port 8
CMOS I/O port 7
SIN3, SOT3, SCK3/
P50 to P52/
Prescaler × 2 ch
AN0 to AN2
P73, P74
/DA00, DA01
DVRH
2
D/A converter
2
3
P53/AN3, P57/AN7
(8 bit) × 2 ch
UART
× 2 ch
DVSS
SIN4, SOT4, SCK4/
P54 to P56/
Evaluation device (MB90V580B)
This chip has no internal ROM.
Internal RAM is 6 Kbytes.
AN4 to AN6
CMOS I/O port 5
IEBusTM controller
*
TX
RX
Internal resources are common.
The package is PGA-256C-A02.
P00 to 07 (8 channels): Provided with a register available as an input pull-up resistor.
P10 to 17(8 channels): Provided with a register available as an input pull-up resistor.
P60 to 65(6 channels): Provided with a register available as an input pull-up resistor.
P40 to 47 (8 channels): Provided with a register available as an open drain.
*: The MB90587C/CA has no IEBusTM controller. The TX and RX pins are N.C. pins.
Other pins
MD2 to MD0
C,VCC,VSS
22
MB90580C Series
■ MEMORY MAP
FFFFFFH
ROM area
ROM area
Address#1
FC0000H
010000H
ROM area
(image of bank
FF)
ROM area
(image of bank
FF)
Address#2
: Internal
: External
004000H
002000H
Address#3
: Inhibited area
RAM Register
RAM Register
RAM Register
000100H
0000C0H
Peripheral
Peripheral
Peripheral
000000H
Single chip mode
A mirror function
is supported
External ROM
external bus
mode
Internal ROM
external bus mode
A mirror function is
supported
Parts No.
Address#1
Address#2
Address#3
001900H
001900H
001100H
001900H
MB90583C/CA
MB90F583C/CA
MB90587C/CA
MB90V580B
FE0000H
FE0000H
FF0000H
(FE0000H)
004000H
004000H
004000H
004000H
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on
the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents
of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the
whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks,
therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table
be stored in the area of FF4000H to FFFFFFH.
23
MB90580C Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
: Accumulator (A)
AH
AL
Dual 16-bit register used for storing results of calculation
etc. The two 16-bit registers can be combined to be used
as a 32-bit register.
: User stack pointer (USP)
The 16-bit pointer indicating a user stack address.
USP
SSP
: System stack pointer (SSP)
The 16-bit pointer indicating the status of the system stack
address.
: Processor status (PS)
The 16-bit register indicating the system status.
PS
PC
: Program counter (PC)
The 16-bit register indicating storing location of the current
instruction code.
: Direct page register (DPR)
DPR
The 8-bit register indicating bit 8 through 15 of the operand
address in the short direct addressing mode.
: Program bank register (PCB)
The 8-bit register indicating the program space.
PCB
DTB
USB
SSB
: Data bank register (DTB)
The 8-bit register indicating the data space.
: User stack bank register (USB)
The 8-bit register indicating the user stack space.
: System stack bank register (SSB)
The 8-bit register indicating the system stack space.
: Additional data bank register (ADB)
The 8-bit register indicating the additional data space.
ADB
8 bit
16 bit
32 bit
24
MB90580C Series
• General-purpose registers
Maximum of 32 banks
R7
R5
R3
R1
R6
R4
R2
R0
RW7
RW6
RW5
RW4
RL3
RL2
RL1
RL0
RW3
RW2
RW1
RW0
000180H + (RP × 10H)
16 bit
• Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PS
ILM2 ILM1 ILM0 B4
B3
0
B2
0
B1
0
B0
0
I
S
1
T
X
N
X
Z
X
V
X
C
X
0
0
0
0
0
Initial value
: Unused
: Undefined
X
25
MB90580C Series
■ I/O MAP
Abbreviated
register
name
Address
Register name
Read/write Resource name
Initial value
00H
01H
Port 0 data register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
− − XXXXXXB
− − − XXXX −B
XXXXXXXXB
XXXXXXXXB
− − − − − XXXB
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Port 9 data register
Port A data register
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH to 0FH
10H
(Disabled)
Port 0 direction register
Port 1 direction register
Port 2 direction register
Port 3 direction register
Port 4 direction register
Port 5 direction register
Port 6 direction register
Port 7 direction register
Port 8 direction register
Port 9 direction register
Port A direction register
Port 4 output pin register
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
ODR4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port 4
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
− − 0000000B
− − − 0000− B
00000000B
00000000B
− − − − − 000B
00000000B
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
Port 5 analog input enable
register
1CH
ADER
R/W
Port 4, A/D
11111111B
1DH to 1FH
20H
(Disabled)
Serial mode register 0
Serial control register 0
SMR0
SCR0
R/W
R/W
00000000B
00000100B
21H
UART0
SIDR0/
SODR0
Serial input data register 0/
serial output data register 0
22H
23H
R/W
R/W
XXXXXXXXB
Serial status register 0
SSR0
00001−00B
(Continued)
26
MB90580C Series
Abbreviated
register
name
Read/
write
Address
Register name
Resource name
Initial value
24H
25H
Serial mode register 1
Serial control register 1
SMR1
SCR1
R/W
R/W
00000000B
00000100B
UART1
SIDR1/
SODR1
Serial input data register 1/
serial output data register 1
26H
R/W
XXXXXXXXB
27H
28H
29H
Serial status register 1
Serial mode register 2
Serial control register 2
SSR1
SMR2
SCR2
R/W
R/W
R/W
00001−00B
00000000B
00000100B
UART2
SIDR2/
SODR2
Serial input data register 2/
serial output data register 2
2AH
2BH
2CH
2DH
2EH
R/W
R/W
R/W
XXXXXXXXB
00001−00B
0− − − 1111B
Serial status register 2
SSR2
Communications
prescaler 0
Clock division control register 0
CDCR0
(Disabled)
Communications
prescaler 1
Clock division control register 1
CDCR1
R/W
0− − − 1111B
2FH
30H
31H
(Disabled)
DTP/interrupt enable register
DTP/interrupt factor register
ENIR
EIRR
R/W
R/W
00000000B
XXXXXXXXB
DTP/external
interrupt
Request level setting register
lower
32H
33H
34H
00000000B
00000000B
0− − − 1111B
ELVR
R/W
R/W
Request level setting register
upper
Communications
prescaler 2
Clock division control register 2
CDCR2
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
(Disabled)
Control status register lower
Control status register upper
Data register lower
ADCS1
ADCS2
ADCR1
ADCR2
DAT0
R/W
R/W
R
00000000B
00000000B
XXXXXXXXB
00001−XXB
00000000B
00000000B
− − − − − − − 0B
− − − − − − − 0B
A/D converter
D/A converter
Data register upper
R or W
R/W
R/W
R/W
R/W
D/A converter data register 0
D/A converter data register 1
D/A control register 0
DAT1
DACR0
DACR1
D/A control register 1
Clock monitor
function
3EH
3FH
Clock output enable register
CLKR
R/W
− − − − 0000B
(Disabled)
(Continued)
27
MB90580C Series
Abbreviated
register
name
Read/
write
Address
Register name
Resource name
Initial value
40H
41H
42H
43H
Reload register L (ch.0)
Reload register H (ch.0)
Reload register L (ch.1)
Reload register H (ch.1)
PRLL0
PRLH0
PRLL1
PRLH1
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
8/16 bit
PPG0/1
PPG0 operating mode control
register
44H
45H
46H
PPGC0
PPGC1
PPGOE
R/W
R/W
R/W
0X000XX1B
0X000001B
00000000B
PPG1 operating mode control
register
PPG0 and 1 operating output control
registers
47H
48H
49H
(Disabled)
Timer control status register lower
Timer control status register upper
00000000B
TMCSR0
R/W
R/W
R/W
R/W
R/W
R/W
− − − − 0000B
16 bit
reload timer 0
16 bit timer register lower/
16 bit reload register lower
4AH
4BH
XXXXXXXXB
XXXXXXXXB
TMR0/
TMRLR0
16 bit timer register upper/
16 bit reload register upper
4CH
4DH
Timer control status register lower
Timer control status register upper
00000000B
TMCSR1
− − − − 0000B
16 bit
reload timer 1
16bit timer register lower/
16 bit reload register lower
4EH
4FH
XXXXXXXXB
XXXXXXXXB
TMR1/
TMRLR1
16 bit timer register upper/
16 bit reload register upper
50H
51H
Timer control status register lower
Timer control status register upper
00000000B
TMCSR2
− − − − 0000B
16 bit
reload timer 2
16 bit timer register lower/
16 bit reload register lower
52H
53H
XXXXXXXXB
XXXXXXXXB
TMR2/
TMRLR2
16 bit timer register upper/
16 bit reload register upper
54H
55H
56H
57H
58H
59H
PWC control status register lower
PWC control status register upper
PWC data buffer register lower
PWC data buffer register upper
Divide ratio control register
00000000B
00000000B
XXXXXXXXB
XXXXXXXXB
− − − − − − 00B
R/W
or R
PWCSR
16 bit
PWC timer
PWCR
DIVR
R/W
R/W
(Disabled)
(Continued)
28
MB90580C Series
Abbreviated
register
name
Address
Register name
Read/write Resource name
Initial value
5AH
5BH
5CH
5DH
Compare register lower
Compare register upper
Compare register lower
Compare register upper
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Output compare
(ch.0)
OCCP0
OCCP1
R/W
R/W
Output compare
(ch.1)
Output compare
(ch.0)
5EH
5FH
Compare control status register 0
Compare control status register 1
OCS0
OCS1
R/W
R/W
0000− − 00B
− − − 00000B
Output compare
(ch.1)
60H
61H
62H
63H
64H
65H
66H
67H
Input capture register lower
Input capture register upper
Input capture register lower
Input capture register upper
Input capture register lower
Input capture register upper
Input capture register lower
Input capture register upper
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input capture
(ch.0)
IPCP0
IPCP1
IPCP2
R
R
R
Input capture
(ch.1)
Input capture
(ch.2)
Input capture
(ch.3)
IPCP3
ICS01
R
Input capture control status
register 01
Input capture
(ch.0, ch.1)
68H
69H
6AH
R/W
00000000B
(Disabled)
Input capture control status
register 23
Input capture
(ch.2, ch.3)
ICS23
R/W
00000000B
6BH
6CH
6DH
6EH
(Disabled)
Timer data register lower
Timer data register upper
Timer control status register
TCDTL
TCDTH
TCCS
R/W
R/W
R/W
00000000B
00000000B
00000000B
Free-run timer
ROM mirroring function selection
register
6FH
70H
71H
ROMM
MAWL
MAWH
W
ROM mirror function − − − − − − − 1B
XXXXXXXXB
Local-office address setting
register L
R/W
R/W
Local-office address setting
register H
XXXXXXXXB
IEBusTM
controller
72H
73H
74H
Slave address setting register L
Slave address setting register H
Message length bit setting register
SAWL
SAWH
DEWR
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
00000000B
Broadcast control bit setting
register
75H
DCWR
R/W
00000000B
(Continued)
29
MB90580C Series
Abbreviated
register
name
Address
Register name
Command register L
Read/write Resource name
Initial value
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
CMRL
CMRH
STRL
STRH
LRRL
LRRH
MARL
MARH
DERR
DCRR
WDB
R/W
R/W
R
11000000B
0000000XB
0011XXXXB
00XX0000B
XXXXXXXXB
1110XXXXB
XXXXXXXXB
1111XXXXB
XXXXXXXXB
000XXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000100B
Command register H
Status register L
Status register H
R/W or R
R
Lock read register L
IEBusTM
Lock read register H
R/W or R
controller
Master address read register L
Master address read register H
Message length bit read register
Broadcast control bit read register
Write data buffer
R
R
R
R
W
Read data buffer
RDB
R
Serial mode register 3
Serial control register 3
SMR3
SCR3
R/W
R/W
UART3
Serial input register 3/
serial output register 3
SIDR3/
SODR3
84H
R/W
XXXXXXXXB
85H
86H
Serial status register 3
PWC noise filter register
SSR3
R/W
R/W
00001−00B
− − − − − 000B
RNCR
PWC noisefilter
Communications
prescaler 3
87H
Clock division control register 3
CDCR3
R/W
0− − − 1111B
88H
89H
Serial mode register 4
Serial control register 4
SMR4
SCR4
R/W
R/W
00000000B
00000100B
UART4
SIDR4/
SODR4
Serial input register 4/
serial output register 4
8AH
8BH
8CH
R/W
R/W
R/W
XXXXXXXXB
00001−00B
00000000B
Serial status register 4
SSR4
Port 0 input pull-up resistor setup
register
RDR0
Port 0
Port 1
Port 6
Port 1 input pull-up resistor setup
register
8DH
8EH
8FH
RDR1
RDR6
R/W
R/W
R/W
00000000B
− − 000000B
0− − − 1111B
Port 6 input pull-up resistor setup
register
Communications
prescaler 4
Clock division control register 4
CDCR4
90H to
9DH
(Disabled)
(Continued)
30
MB90580C Series
Abbreviated
register
name
Read/
write
Address
Register name
Resource name
Initial value
Address match
detection
Program address detection control/
status register
9EH
9FH
PACSR
DIRR
R/W
R/W
00000000B
function
Delayed interrupt generation/release
register
Delayed interrupt
generation module
− − − − − − − 0B
Low-power consumption mode
control register
A0H
A1H
LPMCR
CKSCR
R/W or W
R/W or R
0001100−B
Low-power
consumption mode
Clock selection register
11111100B
A2H to
A4H
(Disabled)
A5H
A6H
Auto-ready function selection register
ARSR
HACR
W
W
0011− − 00B
External address output control
register
External bus pin
control circuit
00000000B
A7H
A8H
A9H
AAH
Bus control signal selection register
Watch dog timer control register
Time-base timer control register
Clock timer control register
ECSR
WDTC
TBTC
WTC
W
0000000−B
XXXXX111B
1− − 00100B
1X000000B
R or W
R/W, W
R/W or R
Watch dog timer
Timebase timer
Clock timer
ABH to
ADH
(Disabled)
R/W or R
or W
AEH
Flash memory control status register
FMCS
Flash interface
000X0000B
AFH
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
(Disabled)
Interrupt control register 00
Interrupt control register 01
Interrupt control register 02
Interrupt control register 03
Interrupt control register 04
Interrupt control register 05
Interrupt control register 06
Interrupt control register 07
Interrupt control register 08
Interrupt control register 09
Interrupt control register 10
Interrupt control register 11
Interrupt control register 12
Interrupt control register 13
Interrupt control register 14
Interrupt control register 15
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
Interrupt controller
31
MB90580C Series
(Continued)
(Continued)
Abbreviated
register
name
Address
Register name
Read/write Resource name
Initial value
C0H to
FFH
(External area)
100H to
(RAM area)
#H
#H to
1FEFH
(Reserved area)
Program address detection register 0
(lower)
1FF0H
1FF1H
1FF2H
1FF3H
1FF4H
1FF5H
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Program address detection register 0
(middle)
PADR0
PADR1
R/W
R/W
R/W
R/W
R/W
Program address detection register 0
(upper)
Address match
detection
Program address detection register 1
(lower)
function
Program address detection register 1
(middle)
Program address detection register 1
(upper)
1FF6H to
1FFFH
(Reserved area)
• Explanation of initial values→“0” : initial value“0” / “1” : initial value“1” / “X” : undefined / “−” : undefined (not used)
• The addresses following 00FFH are reserved. No external bus access signal is generated.
• Boundary #H between the RAM area and the reserved area varies with the product model.
Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial
value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases
where initialization is performed or not performed, depending on the types of the reset. However initial value
for resets that initializes the value are listed.
32
MB90580C Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
EI2OS
support
register
Interrupt source
Priority
No.
Address
ICR
Address
Reset
×
×
×
#08 FFFFDCH
High
INT9 instruction
Exception
#09
#10
#11
FFFFD8H
FFFFD4H
FFFFD0H
A/D converter
Timebase timer
ICR00
ICR01
0000B0H
0000B1H
×
#12 FFFFCCH
DTP0 (external interrupt #0) /UART3 reception
complete
#13
#14
#15
#16
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
DTP1 (external interrupt #1) /UART4 reception
complete
DTP2 (external interrupt #2) /UART3 transmission
complete
ICR02
0000B2H
DTP3 (external interrupt #3) /UART4 transmission
complete
DTP4 to 7 (external interrupt #4 to #7)
Output compare (ch.1) match (I/O timer)
UART2 reception complete
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#37
#39
#41
#42
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
UART1 reception complete
Input capture (ch.3) include (I/O timer)
Input capture (ch.2) include (I/O timer)
Input capture (ch.1) include (I/O timer)
Input capture (ch.0) include (I/O timer)
8/16 bit PPG0 counter borrow
16 bit reload timer 2 to 0
×
×
Clock prescaler
Output compare (ch.0) match (I/O timer)
UART2 transmission complete
PWC timer measurement complete / over flow
UART1 transmission complete
16-bit free run timer (I/O timer) over flow
UART0 transmission complete
8/16 bit PPG1 counter borrow
IEBus reception complete
ICR10 0000BAH
ICR11 0000BBH
×
FFFF70H ICR12 0000BCH
FFFF68H ICR13 0000BDH
FFFF60H ICR14 0000BEH
IEBus transmission start
UART0 reception complete
Flash memory status
×
×
FFFF58H
ICR15 0000BFH
Delayed interrupt
FFFF54H
Low
: Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal (stop request present).
: Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal.
× : Indicates that the interrupt request flag is not cleared by the EI2OS interrupt clear signal.
33
MB90580C Series
■ PERIPHERAL RESOURCES
1. I/O Ports
(1) Outline of I/O ports
Whenadataregisterservingforcontroloutputisread, thedataoutputfromitasacontroloutputisreadregardless
of the value in the direction register. Note that, if a read modify write instruction (such as a bit set instruction)
is used to preset output data in the data register when changing its setting from input to output, the data read
is not the data register latched value but the input data from the pin.
Ports 0 to 4 and 6 to A are input/output ports which serve as inputs when the direction register value is “0” or
as outputs when the value is “1”.
On the MB90580C series, ports 0 to 3 also serve as external bus pins. When the device is used in external bus
mode, therefore, these ports are restricted on use.
Ports 2 and 3 can be used as ports even in external bus mode depending on the setting of the corresponding
function select bit.
(2) Register configuration
• Port 0 data register (PDR0)
…………
15
8
7
6
5
4
3
2
1
0
bit
Address : 000000H
(PDR1)
P07 P06 P05 P04 P03 P02 P01 P00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Port 1 data register (PDR1)
…………
0
bit
15
14
13
12
11
10
9
8
7
Address
: 000001H
P17 P16 P15 P14 P13 P12 P11 P10
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(PDR0)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Port 2 data register (PDR2)
Address : 000002H
…………
bit
15
8
7
6
5
4
3
2
1
0
(PDR3)
P27 P26 P25 P24 P23 P22 P21 P20
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Port 3 data register (PDR3)
…………
0
bit
15
14
13
12
11
10
9
8
7
Address
: 000003H
P37 P36 P35 P34 P33 P32 P31 P30
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(PDR2)
Access
Initial value
• Port 4 data register (PDR4)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
…………
bit
15
8
7
6
5
4
3
2
1
0
Address
: 000004H
(PDR5)
P47 P46 P45 P44 P43 P42 P41 P40
(R/W) (RW) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(X) (X) (X) (X) (X) (X) (X) (X)
(Continued)
34
MB90580C Series
(Continued)
• Port 5 data register (PDR5)
…………
0
bit
15
14
13
12
11
10
9
8
7
Address
: 000005H
P57 P56 P55 P54 P53 P52 P51 P50
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(PDR4)
Access
Initial value
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
• Port 6 data register (PDR6)
Address : 000006H
…………
bit
15
8
7
6
5
4
3
2
1
0
(PDR7)
P65 P64 P63 P62 P61 P60
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(
(
)
)
(
(
)
)
(X)
(X)
(X)
(X)
(X)
(X)
• Port 7 data register (PDR7)
…………
0
bit
15
14
13
12
11
10
9
8
7
Address
: 000007H
P74 P73 P72 P71
(R/W) (R/W) (R/W) (R/W)
(PDR6)
Access
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
Initial value
(X)
(X)
(X)
(X)
• Port 8 data register (PDR8)
Address : 000008H
…………
bit
15
8
7
6
5
4
3
2
1
0
(PDR9)
P87 P86 P85 P84 P83 P82 P81 P80
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Port 9 data register (PDR9)
…………
0
bit
15
14
13
12
11
10
9
8
7
Address
: 000009H
P97 P96 P95 P94 P93 P92 P91 P90
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(PDR8)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Port A data register (PDRA)
Address : 00000AH
…………
bit
15
8
7
6
5
4
3
2
1
0
PA2 PA1 PA0
(R/W) (R/W) (R/W)
(Disabled)
Access
Initial value
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(X)
(X)
(X)
• Port 0 direction register (DDR0)
bit
…………
15
8
7
6
5
4
3
2
1
0
Address
: 000010H
(DDR1)
D07 D06 D05 D04 D03 D02 D01 D00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(Continued)
35
MB90580C Series
(Continued)
• Port 1 direction register (DDR1)
…………
0
bit
15
14
13
12
11
10
9
8
7
Address : 000011H
D17 D16 D15 D14 D13 D12 D11 D10
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(DDR0)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 2 direction register (DDR2)
bit
…………
15
8
7
6
5
4
3
2
1
0
Address : 000012H
(DDR3)
D27 D26 D25 D24 D23 D22 D21 D20
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 3 direction register (DDR3)
bit
…………
0
15
14
13
12
11
10
9
8
7
Address
: 000013H
D37 P36 P35 P34 P33 P32 P31 P30
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(DDR2)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 4 direction register (DDR4)
bit
…………
15
8
7
6
5
4
3
2
1
0
Address : 000014H
(DDR5)
D47 D46 D45 D44 D43 D42 D41 D40
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 5 direction register (DDR5)
bit
…………
0
15
14
13
12
11
10
9
8
7
Address
: 000015H
D57 D56 D55 D54 D53 D52 D51 D50
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(DDR4)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 6 direction register (DDR6)
bit
…………
15
8
7
6
5
4
3
2
1
0
Address
: 000016H
(DDR7)
D65 D64 D63 D62 D61 D60
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(
(
)
)
(
(
)
)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 7 direction register (DDR7)
bit
…………
0
15
14
13
12
11
10
9
8
7
Address : 000017H
D74 D73 D72 D71
(R/W) (R/W) (R/W) (R/W)
(DDR6)
Access
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
Initial value
(0)
(0)
(0)
(0)
(Continued)
36
MB90580C Series
• Port 8 direction register (DDR8)
bit
…………
15
8
7
6
5
4
3
2
1
0
Address
: 000018H
(DDR9)
D87 D86 D85 D84 D83 D82 D81 D80
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 9 direction register (DDR9)
bit
…………
0
…………
15 14
13
12
11
10
9
8
7
Address : 000019H
D97 D96 D95 D94 D93 D92 D91 D90
(DDR8)
Access
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
1
0
• Port A direction register (DDRA)
bit
…………
15
8
7
6
5
4
3
2
Address : 00001AH
(ODR4)
DA2 DA1 DA0
(R/W) (R/W) (R/W)
Access
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
Initial value
(0)
(0)
(0)
• Port 4 output pin register (ODR4)
bit
…………
0
15
14
13
12
11
10
9
8
7
Address
: 00001BH
OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(DDRA)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 5 analog input enable register (ADER)
…………
bit
15
8
7
6
5
4
3
2
1
0
Address : 00001CH
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
• Port 0 input pull-up resistor setup register (RDR0)
…………
bit
15
8
7
6
5
4
3
2
1
0
Address
: 00008CH
(RDR1)
RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 1 input pull-up resistor setup register (RDR1)
…………
0
bit
15
14
13
12
11
10
9
8
7
Address
: 00008DH
RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(RDR0)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Port 6 input pull-up resistor setup register (RDR6)
…………
bit
15
8
7
6
5
4
3
2
1
0
Address : 00008EH
(CDCR4)
RD65 RD64 RD63 RD62 RD61 RD60
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
(
(
)
)
(
(
)
)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
37
MB90580C Series
(3) Block Diagram
• Input/output port
Internal data bus
Data register read
Data register write
Data register
Pin
Direction register
Direction register write
Direction register read
• Input pull-up resistor setup register
Pull-up resistor (About 50 kΩ)
Data register
Port I/O
Direction register
Inputpull-upresistor
setup register
Bus
38
MB90580C Series
• Output pin register
Data register
Direction register
Pin register
Port I/O
Bus
39
MB90580C Series
2. Timebase Timer
The time-base timer consists of a 18-bit timer and an interval interrupt control circuit. Note that the time-base
timer uses the oscillation clock regardless of the setting of the MCS bit in the CKSCR.
(1) Register configuration
• Timebase timer control register
bit
15
14
13
12
11
10
9
8
Reserved
Address : 0000A9H
TBIE TBOF TBR TBC1 TBC0
(R/W) (R/W) (W) (R/W) (R/W)
TBTC
Access
Initial value
(R/W)
(1)
(
(
)
)
(
(
)
)
(0)
(0)
(1)
(0)
(0)
(2) Block Diagram
Main clock
TBTC
212
Clock input
Selector
214
216
219
TBC1
TBC0
Time-base timer
TBR
TBIE
TBOF
211 213 215 218
TBTRES
S
R
AND
Q
Time-base
interrupt
WDTC
2-bit
counter
CLR
WT1
Watchdog reset
generator
To WDGRST
internal reset
generator
Selector
OF
WT0
WTE
CLR
WTC
AND
S
WDCS
SCE
R
Q
29
210 213 214 215
210
WTC2
WTC1
WTC0
211
212
Clock timer
Clock input
Selector
213
214
WTR
WTIE
215
WTRES
S
R
AND
Q
WTOF
Subclock
Clock
interrupt
WDTC
From power-on reset
generator
Fromhardwarestandby
control circuit
PONR
STBR
WRST
From RST pin
From RST bit in STBYC
register
ERST
SRST
40
MB90580C Series
3. Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit time-base timer as
the clock source, a control register, and a watchdog reset control section.
(1) Register configuration
• Watchdog timer control register
bit
7
6
5
4
3
2
1
0
Address : 0000A8H
PONR STBR WRST ERST SRST WTE WT1 WT0
WDTC
Access
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W) (W) (W)
(1) (1) (1)
(2) Block Diagram
Main clock
TBTC
212
214
216
219
Clock input
TBC1
TBC0
Selector
Time-base timer
TBR
TBIE
TBOF
211 213 215 218
TBTRES
S
R
AND
Q
Time-base
interrupt
WDTC
2-bit
counter
CLR
Watchdog reset
generator
CLR
WT1
To WDGRST
internal reset
generator
Selector
OF
WT0
WTE
WTC
AND
S
WDCS
SCE
R
Q
29
210 213 214 215
210
WTC2
WTC1
WTC0
Clock timer
211
Selector
212
213
214
WTR
WTIE
215
WTRES
Clock input
S
R
AND
Subclock
Q
WTOF
Clock
interrupt
WDTC
Frompower-onreset
generator
PONR
STBR
WRST
From hardware
standby control circuit
From RST pin
ERST
SRST
From RST bit in STBYC
register
41
MB90580C Series
4. Clock timer
The clock timer has the functions of a watchdog timer clock source, a subclock oscillation settling time wait timer,
and of a periodically interrupt generating interval timer.
(1) Register configuration
• Clock timer control register
bit
7
6
5
4
3
2
1
0
Address : 0000AAH
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
(R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
WTC
Access
Initial value
(1)
(X)
(0)
(0)
(0)
(0)
(0)
(0)
(2) Block Diagram
Main clock
TBTC
212
214
216
219
Clock input
TBC1
TBC0
Selector
Time-base timer
TBR
TBIE
TBOF
211 213 215 218
TBTRES
S
R
AND
Q
Time-base
interrupt
WDTC
Watchdog reset
generator
2-bit
WT1
To WDGRST
internal reset
generator
Selector
counter
OF
CLR
WT0
WTE
CLR
WTC
AND
S
WDCS
SCE
R
Q
29
210 213 214 215
210
WTC2
WTC1
WTC0
Clock timer
211
Selector
212
213
214
WTR
WTIE
215
Clock input
WTRES
S
R
AND
Subclock
Q
WTOF
Clock
interrupt
WDTC
PONR
STBR
WRST
From power-on reset
generator
From hardware standby
control circuit
From RST pin
ERST
SRST
From RST bit in STBYC
register
42
MB90580C Series
5. External Memory Access (External Bus Pin Control Circuit)
The external bus pin control circuit controls external bus pins used to expand the address/data buses of the
CPU outside.
(1) Register configuration
• Automatic ready function selection register
15
14
13
12
11
10
9
8
bit
IOR1 IOR0 HMR1 HMR0
LMR1 LMR0
ARSR
Address : 0000A5H
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(1)
(
(
)
)
(
(
)
)
(W)
(0)
(W)
(0)
Access
Initial value
• External address output control register
bit
7
6
5
4
3
2
1
0
Address : 0000A6H
E23 E22 E21 E20 E19 E18 E17 E16
HACR
ECSR
Access
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
Initial value
• Bus control signal selection register
bit
15
14
13
12
11
10
9
8
CKE RYE HDE IOBS HMBS WRE LMBS
Address : 0000A7H
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(
(
)
)
Access
Initial value
(2) Block Diagram
P3
P2
P1
P3
P0
P0 data
P0
P0 direction
RB
Data control
Address control
Access control
Access control
43
MB90580C Series
6. PWC Timer
The PWC (pulse width count) timer is a 16-bit multifunction up-counter with reload timer functions and input-
signal pulse-width count functions as well.
The PWC timer consists of a 16-bit counter, a input pulse divider, a divide ratio control register, a count input
pin, a pulse output pin, and a 16-bit control register.
(1) Features of the PWC timer
The PWC timer has the following features:
• Timer functions
Generates an interrupt request at set time intervals.
Outputs pulse signals synchronized with the timer cycle.
Selects the counter clock from among three internal clocks.
• Pulse-width count functions
Counts the time between external pulse input events.
Selects the counter clock from among three internal clocks.
Count mode
•H pulse width (rising edge to falling edge)/L pulse width (falling edge to rising edge)
•Rising-edge cycle (rising edge to falling edge)/Falling-edge cycle (falling edge to rising edge)
•Count between edges (rising or falling edge to falling or rising edge)
Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider.
Generates an interrupt request upon the completion of count operation.
Selects single or consecutive count operation.
44
MB90580C Series
(2) Register configuration
• PWC control status register Upper
bit
15
STRT STOP EDIR EDIE OVIR OVIE ERR POUT
Access (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R) (R/W)
14
13
12
11
10
9
8
PWCSR upper
PWCSR lower
PWCR upper
PWCR lower
DIVR
Address : 000055H
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• PWC control status register Lower
bit
7
6
5
4
3
2
1
0
ReservedReserved
S/C MOD2 MOD1 MOD0
Address : 000054H
CKS1 CKS0
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
15
(0)
14
(0)
13
(0)
12
(0)
11
(0)
10
(0)
9
(0)
8
• PWC data buffer register Upper
bit
Address : 000057H
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• PWC data buffer register Lower
bit
7
6
5
4
3
2
1
0
Address : 000056H
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
• Divide ratio control register
Address : 000058H
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
7
6
5
4
3
2
1
0
DIV1 DIV0
(R/W) (R/W)
(0)
Access
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
Initial value
• PWC noise filter register
Address : 000086H
(0)
bit
7
6
5
4
3
2
1
0
SW1 SW0
EN
RNCR
Access
Initial value
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(R/W) (R/W) (R/W)
(0) (0) (0)
45
MB90580C Series
(3) Block Diagram
PWCR read
Error
ERR
detection
16
PWCR
16
16
Internal clock
(Machine clock/4)
Reload
Data
transfer
16
Overflow
Clock
22
Clock
divider
16-bit up-count timer
Timer
23
CKS1, CKS0
Count
clear
enable
Control circuit
Divider clear
Start edge
End edge
selection
Divider ON/OFF
SW0
SW1
selection
Count end
edge
Noise
Edge
PWC
detec-
tion
Canceller
Count
start edge
EN
8-bit
divider
CKS1
CKS0
Count end interrupt request
ERR
Overflow interrupt
request
15
POT
F.F.
Overflow
ratio selection
PWCSR
Divide
2
DIVR
46
MB90580C Series
7. 16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, four input capture circuits, and two output
comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run
timer. Input pulse width and external clock periods can, therefore, be measured.
(1) 16-bit free-run timer (1 channel)
The 16-bit free run timer consists of a 16-bit up-counter, a control register, and a prescaler. The value output
from this timer/counter is used as the base time for the input capture and output compare modules.
• Counter operation clock (Selectable from among the following four)
Four internal clock cycles: φ/4, φ/16, φ/64, φ/256
φ: Machine clock
• Interrupts
An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or by compare/match
operation with compare register 0. (The compare/match operation requires the mode setting).
• Counter value
An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or when a match with
compare register 0 occurs (The compare/match function can be used by the appropriate mode setting).
• Initialization
The counter value can be initialized to “0000H” at a reset, soft clear operation, or a match with compare register
0.
(2) Output compare module (2 channels)
The output compare module consists of two 16-bit compare registers, compare output latches, and control
registers. When the 16-bit free-run timer value matches the compare register value, this module generates an
interrupt while inverting the output level.
• Two compare registers can operate independently.
Output pin and interrupt flag for each compare register
• A pair of compare registers can be used to control the output pin.
Two compare registers can be used to invert the output pin polarity.
• The initial value for each output pin can be set.
• An interrupt can be generated by compare/match operation.
(3) Input capture module (4 channels)
The input capture module consists of capture registers and control registers respectively associated with four
independent external input pins. This module can hold the 16-bit free run timer value in the capture register. In
addition, it can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt.
• The external input signal edge to be detected can be selected.
One or both of the rising and falling edges can be selected.
• Four input capture channels can operate independently.
• An interrupt can be generated at a valid edge of the external input signal.
The extended intelligent I/O service can be activated by the interrupt by the input capture module.
47
MB90580C Series
(4) Register configuration
• Timer data register (upper)
bit
15
14
13
12
11
10
9
8
Address : 00006DH
T15 T14 T13 T12 T11 T10 T09 T08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
TCDTH
TCDTL
TCCS
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Timer data register (lower)
bit
7
6
5
4
3
2
1
0
Address : 00006CH
T07 T06 T05 T04 T03 T02 T01 T00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Timer control status register
bit
7
6
5
4
3
2
1
0
Re-
Address : 00006EH
IVF IVFE STOPMODE CLR CLK1 CLK0
served
Access
(
) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Compare register (upper)
bit
15
14
13
12
11
10
9
8
Address
: ch0 00005BH
: ch1 00005DH
OCCP0
OCCP1
C15 C14 C13 C12 C11 C10 C09 C08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Compare register (lower)
bit
7
6
5
4
3
2
1
0
Address
: ch0 00005AH
: ch1 00005CH
OCCP0
OCCP1
C07 C06 C05 C04 C03 C02 C01 C00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Compare control status register 1
bit
15
14
13
12
11
10
9
8
Address : ch1 00005FH
Access
CMOD OTE1 OTE0 OTD1 OTD0
(R/W) (R/W) (R/W) (R/W) (R/W)
OCS1
(
(
)
)
(
(
)
)
(
(
)
)
Initial value
(0)
(0)
(0)
(0)
(0)
• Compare control status register 0
bit
7
6
5
4
3
2
1
0
Address : ch0 00005EH
ICP1 ICP0 ICE1 ICE0
(R/W) (R/W) (R/W) (R/W)
CST1 CST0
OCS0
Access
Initial value
(
(
)
)
(
(
) (R/W) (R/W)
(0)
(0)
(0)
(0)
)
(0)
(0)
(Continued)
48
MB90580C Series
(Continued)
• Input capture register (upper)
bit
Address : ch0 000061H
15
14
13
12
11
10
9
8
IPCP0 upper
IPCP1 upper
IPCP2 upper
: ch1 000063H
: ch2 000065H
: ch3 000067H
Access
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
(R) (R) (R) (R) (R) (R) (R) (R)
IPCP3 upper
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Input capture register (lower)
bit
7
6
5
4
3
2
1
0
Address : ch0 000060H
: ch1 000062H
: ch2 000064H
: ch3 000066H
Access
IPCP0 lower
IPCP1 lower
IPCP2 lower
IPCP3 lower
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
(R) (R) (R) (R) (R) (R) (R) (R)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Input capture control status register 01
bit
7
6
5
4
3
2
1
0
Address : 000068H
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
ICS01
ICS23
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
7
(0)
6
(0)
5
(0)
4
(0)
3
(0)
2
(0)
1
(0)
0
• Input capture control status register 23
bit
Address : 00006AH
ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
49
MB90580C Series
(5) Block Diagram
φ
Interrupt
request
Frequency
divider
IVF IVFE STOP MODE CLR CLK1 CLK0
Comparator 0
16-bit up-counter
Clock
Output count value (T15 to T00)
Compare control
OUT0
OUT1
T
Q
OTE0
OTE1
Compare register ch.0
CMOD
T
Q
Compare control
Compare register ch.1
ICP1 ICP0 ICE1 ICE0
Compare interrupt 0
Compare interrupt 1
Control block
Each control block
Edge
detection
IN0, IN2
Input capture data register ch.0, ch.2
EG11 EG10 EG01 EG00
Edge
detection
Input capture data register ch.1, ch.3
IN1, IN3
ICP1 ICP0 ICE1 ICE0
Capture interrupt 1/3
Capture interrupt 0/2
50
MB90580C Series
8. 16-bit Reload Timer
The 16-bit reload timer has three channels, each of which consists of a 16-bit down counter, a 16-bit reload
register, an input pin (TIN), an output pin (TOT), and a control register. The input clock can be selected from
among three internal clocks and one external clock.
(1) Register configuration
• Timer control status register (upper)
bit
Address : ch0 000049H
15
14
13
12
11
10
9
8
TMCSR0 upper
TMCSR1 upper
TMCSR2 upper
: ch1 00004DH
: ch2 000051H
CSL1 CSL0 MOD2 MOD1
) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
(0)
(0)
(0)
(0)
• Timer control status register (lower)
bit
7
6
5
4
3
2
1
0
Address : ch0 000048H
: ch1 00004CH
TMCSR0 lower
TMCSR1 lower
TMCSR2 lower
MOD0OUTEOUTL RELD INTE UF CNTE TRG
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
: ch2 000050H
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(read)
• 16-bit timer register (upper) /16 bit reload register (upper)
bit
Address : ch0 00004BH
: ch1 00004FH
15
14
13
12
11
10
9
8
TMR0 upper
TMR1 upper
TMR2 upper
(write)
: ch2 000053H
Access
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
TMRLR0 upper
TMRLR1 upper
TMRLR2 upper
(read)
• 16-bit timer register (lower) /16 bit reload register (lower)
bit
Address : ch0 00004AH
: ch1 00004EH
7
6
5
4
3
2
1
0
TMR0 lower
TMR1 lower
TMR2 lower
(write)
: ch2 000052H
Access
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
TMRLR0 lower
TMRLR1 lower
TMRLR2 lower
51
MB90580C Series
(2) Block Diagram
16
16-bit reload register
8
Reload
RELD
OUTE
OUTL
INTE
UF
16-bit down-counter UF
16
2
OUT
CTL.
GATE
IRQ
CSL1
Clock selector
CSL0
CNTE
TRG
Clear
EI2OSCLR
Retrigger
2
IN CTL
Port (TIN)
Output
enable
EXCK
3
Port (TOT)
φ
φ
φ
Prescaler
clear
—
—
—
21 23 25
MOD2
Serial baud rate
(channel n)
MOD1
MOD0
Machine clock
3
Note: Reload timer channels and UART channels are connected as follows
•Reload timer channel 0 : UART0, UART3
•Reload timer channel 1 : UART1, UART4
•Reload timer channel 2 : UART2
52
MB90580C Series
9. 8/16-bit PPG
8/16-bit PPG is an 8/16-bit reload timer module. The block performs PPG output in which the pulse output is
controlled by the operation of the timer.
The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two
external pulse output pins, and two interrupt outputs. The PPG has the following functions.
• 8-bit PPG output in two channels independent operation mode:
Two independent PPG output channels are available.
• 16-bit PPG output operation mode :
One 16-bit PPG output channel is available.
• 8 + 8-bit PPG output operation mode :
Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to
channel 1.
• PPG output operation :
Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction
with an external circuit.
(1) Register configuration
• PPG0 operating mode control register
bit
7
6
5
4
3
2
1
0
Re-
Address : ch0 0000044H
PEN0
POE0 PIE0 PUF0
PPGC0
PPGC1
PPGOE
served
Access
Initial value
(R/W) ( ) (R/W) (R/W) (R/W) (
(0) (X) (0) (0) (0) (X)
)
(
) (R/W)
(X)
(1)
• PPG1 operating mode control register
bit
15
PEN1
14
13
12
11
10
9
8
Re-
served
Address : ch1 0000045H
POE1 PIE1 PUF1 MD1 MD0
Access
Initial value
(R/W) ( ) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(X)
(0)
(0)
(0)
(0)
(0)
(1)
• PPG0 and 1 output control registers
bit
7
6
5
4
3
2
1
0
Re-
served
Re-
Address : ch0, 1 0000046H
PCS2 PCS1 PCS0PCM2PCM1PCM0 served
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Reload register H
bit
15
14
13
12
11
10
9
8
Address : ch0 000041H
: ch1 000043H
Access
PRLH0
PRLH1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
Initial value
• Reload register L
bit
7
6
5
4
3
2
1
0
Address : ch0 000040H
: ch1 000042H
Access
PRLL0
PRLL1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
Initial value
53
MB90580C Series
(2) Block Diagram
• Block diagram (8 bit PPG (ch.0) )
PPG0 output enable
PPG0
Machine clock divided by 16
Machine clock divided by 8
Machine clock divided by 4
Machine clock divided by 2
Machine clock
PPG0
output latch
Invert Clear
PEN0
S
R
Q
PCNT (Down-counter)
Reload
IRQ
Count clock selection
ch.1 borrow
Timebase counter output
oscillation clock divided
by 512
L/H Selector
L/H select
PRLL0
PRLH0
PRLBH0
PIE0
PUF0
L-side data bus
H-side data bus
PPGC0
(Operation mode control)
54
MB90580C Series
• Block Diagram (8/16 bit PPG (ch.1) )
PPG1 output enable
PPG1
Machine clock divided by 16
Machine clock divided by 8
Machine clock divided by 4
Machine clock divided by 2
Machine clock
A/D converter
PPG1
output latch
Invert
Clear
PEN1
Count clock selection
S
ch0 borrow
PCNT(Down-counter)
Reload
Q
R
IRQ
Timebase counter output
oscillation clock divided
by 512
L/H Selector
L/H select
PRLL1
PRLH1
PRLBH1
PIE
PUF
L-side data bus
H-side data bus
PPGC1
(Operation mode control)
55
MB90580C Series
10. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. Two request levels
(“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts
on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types.
(1) Register configuration
• Interrupt/DTP enable register
bit
7
6
5
4
3
2
1
0
Address : 0000030H
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
ENIR
EIRR
Access
Initial value
• Interrupt/DTP source register
Address : 0000031H
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
15
14
13
12
11
10
9
8
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Request level setting register (lower)
bit
7
6
5
4
3
2
1
0
Address : 0000032H
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
ELVR lower
ELVR upper
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Request level setting register (upper)
bit
15
14
13
12
11
10
9
8
Address : 0000033H
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(2) Block Diagram
F2MC-16LX bus
8
Interrupt/DTP enable register
Source F/F
8
8
8
8
Gate
Edge detect circuit
Request input
Interrupt/DTP source register
Request level setting register
56
MB90580C Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to
the F2MC-16LX CPU can be generated and cleared by software using this module.
(1) Register configuration
The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register
generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register
is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However,
considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for
register access.
• Delayed interrupt generation/release register
bit
15
14
13
12
11
10
9
8
R0
Address : 00009FH
DIRR
Access
Initial value
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
) (R/W)
)
(0)
(2) Block Diagram
F2MC-16LX bus
Delayed interrupt generation/
release decode
Interrupt
latch
57
MB90580C Series
12. A/D Converter
The A/D converter converts analog input voltages to digital values. The A/D converter has the following features.
• Conversion time: Minimum of 34.7 µs per channel (for a 12 MHz machine clock)
• Uses RC-type successive approximation conversion with a sample and hold circuit.
• 8/10-bit resolution
• Eight program-selectable analog input channels
Single conversion mode: Selectively convert one channel.
Scan conversion mode: Continuously convert multiple channels. Maximum of 8 program selectable channels.
Continuous conversion mode : Repeatedly convert specified channels.
Stop conversion mode:Convert one channel then halt until the next activation. (Enables synchronization of the
conversion start timing.)
• An A/D conversion completion interrupt request.
An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conversion. This interrupt can activate EI2OS to transfer the result of A/D conversion to memory and is suitable
for continuous operation.
• Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
(1) Register configuration
• Control status register (upper)
bit
15
14
13
12
11
10
9
8
Re-
Address : 000037H
BUSY INT INTE PAUS STS1 STS0 STRT served
ADCS2
ADCS1
ADCR2
ADCR1
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ( )
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Control status register (lower)
bit
7
6
5
4
3
2
1
0
Address : 000036H
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Data register (upper)
bit
15
14
13
12
11
10
9
8
Address : 000039H
SELB ST1 ST0 CT1 CT0
(W) (W) (W) (W) (W)
D9
D8
Access
(
(
)
)
(R) (R)
Initial value
(0)
(0)
(0)
(0)
(1)
(X)
1
(X)
• Data register (lower)
bit
7
6
5
4
3
2
0
Address : 000038H
D7
(R) (R) (R) (R) (R) (R) (R) (R)
(X) (X) (X) (X) (X) (X) (X) (X)
D6
D5
D4
D3
D2
D1
D0
Access
Initial value
58
MB90580C Series
(2) Block Diagram
AVCC
AVRH,AVRL
AVSS
D/A converter
MPX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive approxi-
mation register
F2
M
C
1
Comparator
Sample and
hold circuit
6
L
X
b
u
Data register
ADCR1, 2
s
Control status
register upper
Control status
register lower
ADCS1, 2
Trigger activation
ADTG
Timer activation
Operating
clock
PPG1 output
Prescaler
φ
59
MB90580C Series
13. D/A Converter
D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The
D/A control register controls the output of the two D/A converters independently.
(1) Register configuration
• D/A converter data register 1
bit 15
14
13
12
11
10
9
8
Address : 00003BH
DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10
DAT1
DAT0
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• D/A converter data register 0
Address : 00003AH
bit
7
6
5
4
3
2
1
0
DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• D/A control register 1
bit 15
14
13
12
11
10
9
8
Address : 00003DH
DAE1
DACR1
DACR0
Access
Initial value
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
) (R/W)
)
(0)
• D/A control register 0
Address : 00003CH
bit
7
6
5
4
3
2
1
0
DAE0
Access
Initial value
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
)
)
(
(
) (R/W)
) (0)
60
MB90580C Series
(2) Block Diagram
F2MC16LX - BUS
DA DA DA DA DA DA DA DA
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
07 06 05 04 03 02 01 00
DVR
DVR
DA17
DA07
2R
2R
R
R
DA16
DA06
2R
R
2R
R
DA15
DA11
DA05
DA01
2R
R
2R
R
DA10
DA00
2R
2R
2R
2R
DAE1
DAE0
Standby control
Standby control
DA output
channel 1
DA output
channel 0
61
MB90580C Series
14. Communication Prescaler
The register (clock division control register) of the communication prescaler controls division of the machine
clock frequency. It is designed to provide a fixed baud rate for a variety of machine clock frequencies depending
on the user setting.
The output from the communication prescaler is used by the UARTs.
(1) Register configuration
• Clock division control registers 0 to 4
bit
15
14
13
12
11
10
9
8
Address : 00002CH
00002EH
MD
DIV3 DIV2 DIV1 DIV0
CDCR0
CDCR1
CDCR2
CDCR3
CDCR4
Access (R/W) (
Initial value (0)
)
)
(
(
)
)
(
(
) (R/W) (R/W) (R/W) (R/W)
000034H
000087H
00008FH
(
)
(1)
(1)
(1)
(1)
62
MB90580C Series
15. UART
The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication.
The UART has the following features:
• Full-duplex double buffering
• Capable of asynchronous (start-stop) and CLK-synchronous communications
• Support for the multiprocessor mode
• Dedicated baud rate generator integratedBaud rate
Operation
Baud rate
Asynchronous
31250/9615/4808/2404/1202 bps
CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps
* : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz
• Capable of setting an arbitrary baud rate using an external clock
• Error detection functions (parity, framing, overrun)
• HRz sign transfer signal
(1) Register configuration
• Serial mode register 0 to 4
Address : 0000020H
0000024H
bit
7
6
5
4
3
2
1
0
SMR0
SMR1
SMR2
SMR3
SMR4
Re-
MD1 MD0 CS2 CS1 CS0 served SCKE SOE
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
0000028H
0000082H
0000088H
Access
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Serial control register 0 to 4
Address : 0000021H
0000025H
bit
15
PEN
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
14
13
12
11
10
9
8
SCR0
SCR1
SCR2
SCR3
SCR4
P
SBL CL A/D REC RXE TXE
0000029H
0000083H
0000089H
Initial value
(0)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
• Serial input register 0 to 4/serial output register 0 to 4
bit
7
6
5
4
3
2
1
0
(read) (write)
SIDR0SODR0
SIDR1SODR1
SIDR2SODR2
SIDR3SODR3
SIDR4SODR4
0000022H
0000026H
Address :
D7
D6
D5
D4
D3
D2
D1
D0
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (X) (X) (X) (X) (X)
000002AH Initial value
0000084H
000008AH
• Serial status register 0 to 4
Address : 0000023H
0000027H
bit
15
PE ORE FRE RDRFTDRE
Access (R/W) (R/W) (R/W) (R/W) (R/W) ( ) (R/W) (R/W)
(0) (0) (0) (0) (1) (0) (0)
14
13
12
11
10
9
8
SSR0
SSR1
SSR2
SSR3
SSR4
RIE TIE
000002BH
0000085H
000008BH Initial value
(
)
63
MB90580C Series
(2) Block Diagram
Control
signals
Receive interrupt
signal (to CPU)
SCK0 to SCK4
Dedicatedbaud
rate generator
Transmitinterrupt
signal (to CPU)
Transmit clock
Clock select
circuit
16bitreloadtimer
channel 0 to 2
Receive clock
External clock
Transmit control
Receive control
circuit
circuit
Start bit
detection circuit
Transmit start
circuit
SIN0 SIN4
Transmit bit
counter
Receive bit
counter
Receive parity
counter
Transmit parity
counter
SOT0 to SOT4
Shift register
for reception
Shift register
for transmission
Receive condition
decision circuit
Reception
complete
Start
transmission
SODR0 to SODR4
SIDR0 to SIDR4
Reception error
generation
signal for EI2OS
(to CPU)
F2MC-16LX bus
MD1
MD0
CS2
CS1
CS0
PEN
P
PE
ORE
FRE
SBL
SMR0 to
SMR4
register
SCR0 to
SCR4
register
SSR0 to
SSR4
register
CL
RDRF
TDRE
A/D
REC
SCKE
SOE
RXE
TXE
RIE
TIE
Control signal
64
MB90580C Series
16. IEBusTM Controller
The IEBusTM (Inter-Equipment Bus) is a small-scale, two-wire serial bus interface designed for data transfer
between pieces of equipment.
This interface is applicable, for example, as a bus interface for controlling vehicle-mounted devices.
IEBusTM has the following features:
• Multitasking
Any of the units connected to the IEBusTM can transmit data to another one.
• Broadcast function (Communication from one unit to multiple units)
Group broadcast : Broadcast to a group of units
All-unit broadcast
: Broadcast to all units
• Three modes can be selected for different transmission speeds.
IEBusTM internal frequency
6 MHz
6.29 MHz
Mode 0
Mode 1
Mode 2
About 3.9 Kbps
About 17 Kbps
About 26 Kbps
About 4.1 Kbps
About 18 Kbps
About 27 Kbps
• Data buffer for transmission
8-byte FIFO buffer
• Data buffer for reception
8-byte FIFO buffer
• CPU internal operating frequency (12 MHz, 12.58 MHz)
• Frequency tolerance
In mode 0 or 1 : ±1.5%
In mode 2 : ±0.5%
(1) Register configuration
• Local-office address setting register H
bit
15
14
13
12
11
MA11 MA10 MA09 MA08 MAWH
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
10
9
8
ReservedReservedReservedReserved
Address : 000071H
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Local-office address setting register L
bit
7
6
5
4
3
2
1
0
Address : 000070H
MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 MAWL
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Slave address setting register H
bit
15
14
13
12
11
10
9
8
ReservedReservedReservedReserved
Address : 000073H
SA11 SA10 SA09 SA08
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value (X) (X) (X) (X) (X) (X) (X) (X)
SAWH
(Continued)
65
MB90580C Series
• Slave address setting register L
bit
7
6
5
4
3
2
1
0
Address : 000072H
SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
SAWL
DCWR
DCRR
DEWR
DERR
CMRH
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
• Broadcast control bit setting register
bit
15
14
13
12
11
10
9
8
Address : 000075H
DO3 DO2 DO1 DO0 C3
C2
C1
C0
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Broadcast control bit read register
bit
15
14
13
12
11
10
9
8
Address : 00007FH
DO3 DO2 DO1 DO0 C3
C2
C1
C0
Access
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Initial value
• Message length bit setting register
bit
7
6
5
4
3
2
1
0
Address : 000074H
DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
• Message length bit read register
bit
7
6
5
4
3
2
1
0
Address : 00007EH
DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0
Access
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Initial value
• Command register H
bit
15
14
13
12
11
10
9
8
Reserved
MD1 MD0 PCOM RIE TIE GOTMGOTS
Address : 000077H
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(X)
• Command register L
bit
7
6
5
4
3
2
1
0
Address : 000076H
RXS TXS TIT1 TIT0 CS1 CS0 RDBC WDBC CMRL
Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(1)
(1)
(0)
(0)
(0)
(0)
(0)
(0)
• Status register H
bit
15
14
13
12
11
10
9
8
Address : 000079H
COM TE PEF ACK RIF TIF TSL EOD
STRH
Access
Initial value
(R) (R/W) (R)
(0) (0) (X)
(R) (R/W) (R/W) (R)
(X) (0) (0) (0)
(R)
(0)
(Continued)
66
MB90580C Series
(Continued)
• Status register L
bit
7
6
5
4
3
2
1
0
Address : 000078H
WDBF RDBF WDBE RDBE ST3 ST2 ST1 ST0
STRL
Access
(R)
(0)
(R)
(0)
(R)
(1)
(R)
(1)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Initial value
• Lock read register H
bit
15
14
13
12
11
10
9
8
Reserved Reserved Reserved
Address : 00007BH
LOC LD11 LD10 LD09 LD08 LRRH
Access
Initial value
(R)
(1)
(R)
(1)
(R)
(1)
(R/W) (R)
(R)
(X)
(R)
(X)
(R)
(X)
(0)
(X)
• Lock read register L
bit
7
6
5
4
3
2
1
0
Address : 00007AH
LD07 LD06 LD05 LD04 LD03 LD02 LD01 LD00 LRRL
Access
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
• Master address read register H
bit
15
14
13
12
11
10
9
8
Reserved Reserved Reserved Reserved
Address : 00007DH
MA11 MA10 MA09 MA08 MARH
Access
Initial value
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(1)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
• Master address read register L
bit
7
6
5
4
3
2
1
0
Address : 00007CH
MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 MARL
Access
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
• Read data buffer
bit
15
14
13
12
11
10
9
8
Address : 000081H
RD7
RD6
RD5
RD4 RD3 RD2 RD1 RD0 RDB
Access
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
• Write data buffer
bit
7
6
5
4
3
2
1
0
Address : 000080H
WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 WDB
Access
Initial value
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
67
MB90580C Series
(2) Block Diagram
Local-office address setting register
Slave address setting register
Broadcast control bit setting register
Message length bit setting register
8-byte FIFO, write data buffer
Master address read register
Broadcast control bit read register
Message length bit read register
Lock read register
TX
Control circuit
8-byte FIFO, read data buffer
RX
Command register
Status register
Interrupt request signal
(transmission/reception)
2
Prescaler
Internal clock
12 MHz/12.58 MHz
6 MHz/6.29 MHz
IEBusTM
controller
The control circuit in the IEBusTM controller executes the following control functions:
• Controls the number of bytes in data to be transmitted and received.
• Controls the maximum number of bytes transmitted.
• Detects the results of arbitration.
• Evaluates the return of acknowledgment of each field.
• Generates interrupt signals.
68
MB90580C Series
17. Clock Monitor Function
The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from
the CKOT pin.
(1) Register configuration
• Clock output enable register
bit
7
6
5
4
3
2
1
0
Address : 00003EH
CKENFRQ2 FRQ1 FRQ0 CLKR
) (R/W) (R/W) (R/W) (R/W)
Access
(
(
)
)
(
(
)
)
(
(
)
)
(
(
Initial value
)
(0)
(0)
(0)
(0)
(2) Block Diagram
CKEN
FRQ2
FRQ1
FRQ0
Machine clock φ
Divider
circuit
P65/CKOT
69
MB90580C Series
18. Address Match Detection Function
When an address matches the value set in the address detection register, the instruction code to be loaded into
the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the
CPU executes the INT9 instruction. The address match detection function is implemented by processing using
the INT9 interrupt routine.
The device contains two address detection registers, each provided with a compare enable bit. When the value
set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code.
(1) Register configuration
• Program address detection register 0 to 2 (PADR0)
7
6
5
4
3
2
1
0
bit
PADR0 (lower) Address : 001FF0H
Access
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
17
16
15
14
13
12
11
10
Address : 001FF1H
PADR0 (middle)
PADR0 (upper)
Access
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
7
6
5
4
3
2
1
0
Address : 001FF2H
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
• Program address detection register 3 to 5 (PADR1)
bit
Address : 001FF3H
17
16
15
14
13
12
11
10
PADR1 (lower)
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
bit
7
6
5
4
3
2
1
0
PADR1 (middle) Address : 001FF4H
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
bit
17
16
15
14
13
12
11
10
PADR1 (upper) Address : 001FF5H
Access
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
• Program address detection control/status register (PACSR)
bit
7
Re-
6
Re-
5
Re-
4
Re-
3
2
Re-
1
0
Re-
Address
: 00009EH
AD1E
AD0E
servedservedservedserved
served
served
Access
Initial value
(−)
(0)
(−)
(0)
(−)
(0)
(−) (R/W) (−) (R/W) (−)
(0) (0) (0) (0) (0)
70
MB90580C Series
(2) Block Diagram
Address latch
Address detection
register
INT9
Instruction
Enable bit
F2MC-16LX
CPU core
F2MC-16LX bus
71
MB90580C Series
19. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the
00 bank according to register settings.
(1) Register configuration
• ROM mirroring function selection register
bit 15
14
13
12
11
10
9
8
Address : 00006FH
MI
ROMM
Access
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(W)
(2) Block Diagram
F2MC-16LX bus
ROM mirroring function
selection register
Address area
Address
FF bank
00 bank
Data
ROM
72
MB90580C Series
20. One-Megabit Flash Memory
The 1Mbit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM,
flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit.
The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface
circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under
integrated CPU control, allowing program code and data to be improved efficiently.
Note that sector operations such as “enable sector protect” cannot be used.
Features of 1Mbit flash memory
• 128K words x 8 bits or 64K words x 16 bits (16K + 512 x 2 + 7K + 8K + 32K + 64K) sector configuration
• Automatic program algorithm (Embedded Algorithm*: Same as the MBM29F400TA)
• Erasure suspend/resume function integrated
• Detection of programming/erasure completion using the data polling or toggle bit
• Detection of programming/erasure completion using CPU interrupts
• Compatible with JEDEC standard commands
• Capable of erasing data sector by sector (arbitrary combination of sectors)
• Minimum number of times of programming/erasure: 100,000
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(1) Register configuration
• Flash memory control status register
bit
7
6
5
4
3
2
1
0
RDY-
INT
Reserved
Reserved
Address : 0000AEH
INTE
WE
RDY
LPM1
LPM0
FMCS
Access (R/W) (R/W) (R/W)
Initial value (0) (0) (0)
(R)
(X)
(W)
(0)
(R/W)
(0)
(W)
(0)
(R/W)
(0)
73
MB90580C Series
(2) Sector configuration of 1Mbit flash memory
The 1Mbit flash memory has the sector configuration illustrated below. The addresses in the illustration are the
upper and lower addresses of each sector.
When accessed from the CPU, SA0 and SA1 to SA4 are allocated in the FE and FF bank registers, respectively.
Programmer
address *
Flash memory
CPU address
FFFFFFH
7FFFFH
SA4 (16 Kbytes)
FFC000H
FFBFFFH
7C000H
7BFFFH
SA3 (8 Kbytes)
SA2 (8 Kbytes)
SA1 (32 Kbytes)
SA0 (64 Kbytes)
FFA000H
FF9FFFH
7A000H
79FFFH
FF8000H
FF7FFFH
78000H
77FFFH
FF0000H
FEFFFFH
70000H
6FFFFH
FE0000H
60000H
* : Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel
programmer. Programmer addresses are used to program/erase data using a general-purpose programmer.
74
MB90580C Series
21. Low-Power Consumption Control Circuit
The operation modes of the MB90580C series are the PLL clock, PLL sleep, watch, main clock, main sleep,
stop, and hardware standby modes. The operation modes excluding the PLL clock mode are classified as low-
power consumption modes.
The low power consumption circuit has the following functions.
• Main clock mode/Main sleep mode
In either mode, the microcontroller operates only with the main clock (OSC oscillation clock), using the main
clock as the operating clock while suspending the PLL clock (VCO oscillation clock).
• PLL sleep mode/Main sleep mode
These modes stop only the operation clock of the CPU, leaving the other clocks active.
• Watch mode
The watch mode allows only the time-base timer to operate.
• Stop mode/Hardware standby mode
These modes stop oscillation while retaining data at the lowest power consumption. The CPU intermittent
operation function causes the clock supplied to the CPU to operate intermittently when the CPU accesses a
register, internal memory, internal resource, or external bus. This function saves power consumption by
decreasing the execution speed of the CPU while providing high-speed clock signals to the internal resources.
The PLL clock multiplication factor can be selected from among 1, 2, 3, and 4 using the CS1 and CS0 bits in
the clock selection register.
The WS1 and WS0 bits can be used to set the oscillation settling time for the main clock, which is taken to
wake up from the stop or hardware standby mode.
(1) Register configuration
• Low-power consumption mode control register
bit
7
6
5
4
3
2
1
0
Address : 0000A0H
STP SLP SPL RST TMD CG1 CG0
(W) (W) (R/W) (W) ) (R/W) (R/W) (
(0) (0) (0) (1)
LPMCR
CKSCR
Access
(
(1)
)
)
Initial value
• Clock selection register
Address : 0000A1H
(0)
(0)
(
bit
15
14
13
12
11
10
9
8
SCM MCM WS1 WS0 SCS MCS CS1 CS0
(R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1) (1) (1) (1) (1) (1) (0) (0)
Access
Initial value
75
MB90580C Series
(2) Block Diagram
CKSCR
SCM
Sub clock
Subclock switching
(OSC oscillation)
controller
SCS
CKSCR
MCM
Main clock
(OSC oscillation)
PLL multiplication
circuit
MCS
1
2
3
4
CPU clock
generation
CKSCR
CPU clock
1/2
S
CS1
CS0
0/9/17/33
intermittent
CPU clock selector
cycle selection
LPMCR
CG1
CPU intermittent
operation cycle
selector
CG0
Peripheral clock
Peripheral clock
generation
LPMCR
SLP
SCM
SLEEP
Standby
control
circuit
MSTP
STOP
Main OSC stop
Sub OSC stop
STP
TMD
HST
Start
RST
Cancel
HST pin
Interrupt request
or RST
CKSCR
210
Oscillation
stability
waiting time
selector
Clock input
213
215
218
WS1
WS0
Timebase timer
212 214 216 219
LPMCR
SPL
Pin hi-impedance
control circuit
Pin Hi-Z
LPMCR
RST
Internal reset
generation signal circuit
RST pin
Internal RST
To watchdog timer
WDGRST
76
MB90580C Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Rating
Min. Max.
Symbol
Unit
Remarks
Parameter
VCC
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
V
V
V
V
AVCC
VCC ≥ AVCC *1
Power supply voltage
AVRH, AVRL VSS − 0.3 VSS + 6.0
AVCC ≥ AVRH/L, AVRH ≥ AVRL
DVCC
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VCC ≥ DVCC
Input voltage
*2
*2
Output voltage
VO
“L” level maximum output
current
IOL
IOLAV
ΣIOL
15
4
mA
mA
mA
mA
mA
mA
mA
mA
*3
Average output current = operating
current × operating efficiency
“L” level average output
current
“L” level total maximum
output current
100
50
Average output current = operating
current × operating efficiency
“L” level total average
output current
ΣIOLAV
IOH
“H” level maximum output
current
−15
−4
*3
Average output current = operating
current × operating efficiency
“H” level average output
current
IOHAV
ΣIOH
ΣIOHAV
“H” level total maximum
output current
−100
Average output current = operating
current × operating efficiency
“H” level total average
output current
−50
Power consumption
Operating temperature
Storage temperature
PD
TA
300
mW
°C
−40
−55
+85
Tstg
+150
°C
*1 : AVCC shall never exceed VCC when power on.
*2 : VI and VO shall never exceed VCC + 0.3 V.
*3 : The maximum output current is a peak value for a corresponding pin.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
77
MB90580C Series
2. Recommended Operating Conditions
Value
(VSS = AVSS = 0.0 V)
Symbol
Unit
Remarks
Parameter
Min.
Max.
Normal operation (MB90583C/CA, MB90587C/CA,
MB90V580B)
3.0
5.5
V
VCC
Power supply
voltage
4.5
5.5
V
V
V
V
V
V
V
V
Normal operation (MB90F583C/CA)
Retains status at the time of operation stop
CMOS input pin
VCC
VIH
3.0
5.5
0.7 VCC
0.8 VCC
VCC − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VCC+0.3
VCC+0.3
VCC+0.3
0.3 VCC
0.2 VCC
VSS+0.3
“H” level input
voltage
VIHS
VIHM
VIL
CMOS hysteresis input pin
MD pin input
CMOS input pin
“L” level input
voltage
VILS
VILM
CMOS hysteresis input pin
MD pin input
Use a ceramic capacitor or a capacitor with equiv-
alent frequency characteristics. The smoothing ca-
pacitor to be connected to the VCC pin must have a
capacitance value higher than CS.
Smoothing
capacitor
CS
TA
0.1
1.0
µF
°C
Operating
temperature
−40
+85
• C pin connection circuit
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
78
MB90580C Series
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Pin
name
Parameter
Symbol
Condition
Unit
Remarks
Min.
Typ.
Max.
“H” level output
voltage
Alloutput VCC = 4.5 V,
pins IOH = −2.0 mA
VCC −
0.5
VOH
VOL
IIL
V
V
“L” level output
voltage
Alloutput VCC = 4.5 V,
pins IOL = 2.0 mA
0.4
5
All input VCC = 5.5 V,
Input leakage
current
−5
µA
mA
pins
VSS < VI< VCC
VCC = 5.0 V,
Internal operation
at 16 MHz,
MB90583C/CA,
MB90587C/CA
27
33
40
22
50
26
mA MB90F583C/CA
mA MB90583C/CA
Normal operation
VCC = 5.0 V,
Internal operation
at 12.58 MHz,
Normal operation
35
45
mA MB90F583C/CA
VCC = 5.0 V,
Internal operation
at 16 MHz,
When data written
in flash mode pro-
gramming of erasing
ICC
45
60
mA
MB90F583C/CA
mA
VCC = 5.0 V,
Internal operation
at 12.58 MHz,
When data written
in flash mode pro-
gramming of erasing
Power supply
current*
VCC
40
50
7
12
20
mA MB90587C/CA
VCC = 5.0 V,
Internal operation
at 16 MHz,
MB90583C/CA,
mA MB90F583C
/CA
15
In sleep mode
ICCS
VCC = 5.0 V
6
10
18
mA MB90587C/CA
Internal operation
at 12.58 MHz,
In sleep mode
MB90583C/CA,
mA
12
MB90F583C/CA
VCC = 5.0 V,
Internal operation
at 8 kHz,
Subsystem operatin,
TA = 25 °C
MB90583C,
mA
0.1
4
1.0
7
MB90587C
ICCL
mA MB90F583C
(Continued)
79
MB90580C Series
(Continued)
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter Symbol Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
VCC = 5.0 V,
Internal operation
at 8 kHz,
MB90583C,
µA MB90587C,
ICCLS
30
50
In subsleep mode,
TA = 25 °C
MB90F583C
VCC = 5.0 V,
Internal operation
at 8 kHz,
In clock mode,
TA = 25 °C
Powersupply
VCC
MB90583C,
µA MB90587C,
MB90F583C
current*
ICCT
15
30
MB90583C/CA
µA MB90587C/CA,
MB90F583C/CA
In stop mode,
TA = 25 °C
ICCH
5
20
80
Except
AVCC, AVSS,
C, VCC and
VSS
Input
capacitance
CIN
Ileak
RUP
10
pF
Open-drain
output
leakage
current
Open-drain
µA
P40 to P47
0.1
5
output setting
P00 to P07
P10 to P17
P60 to P65
RST
Pull-up
resistance
25
25
50
50
100
100
kΩ
kΩ
Pull-down
resistance
RDOWN MD2
* : The current value is preliminary value and may be subject to change for enhanced characteristics without
previous notice. The power supply current is measured with an external clock.
80
MB90580C Series
4. AC Characteristics
(1) Clock Timings
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Con-
dition
Parameter
Clock frequency
Clock cycle time
Symbol Pin name
Unit
Remarks
Min.
Typ.
32.768
30.5
Max.
fC
X0, X1
X0A, X1A
X0, X1
3
16
MHz
kHz
ns
fCL
tHCYL
tLCYL
62.5
10
333
5
X0A, X1A
µs
Frequency fluctuation
rate locked*
∆f
%
PWH
PWL
X0
X0A
X0
ns
Recommened duty
ratio of 30% to 70%
Input clock pulse width
PWLH
PWLL
15.2
µs
tCR
tCF
External clock
operation
Input clock rise/fall time
5
ns
fCP
fLCP
tCP
1.5
16
MHz Main clock operation
kHz Subclock operation
ns Main clock operation
µs Subclock operation
Internal operating clock
frequency
8.192
—
62.5
666
Internal operating clock
cycle time
tLCP
122.1
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied
PLL signal is locked.
+
+α
α
Center
frequency
∆f =
× 100 (%)
fo
fo
−α
−
• X0, X1 clock timing
tHCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tCF
tCR
• X0A, X1A clock timing
tLCYL
0.8 VCC
0.2 VCC
X0A
PWLH
PWLL
tCF
tCR
81
MB90580C Series
• PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage
Operation guarantee range of MB90F583C/CA
5.5
4.5
3.3
3.0
Operation guarantee range of PLL
Operation guarantee range
of MB90583C/CA,
MB90587C/CA, MB90V580B
1
3
8
12
16
Internal clock fCP (MHz)
Relationship between oscillating frequency and internal operating clock frequency
Multiplied-
by-3
Multiplied-
by-4
Multiplied-
by-2
Multiplied-
by-1
16
12
9
8
Not multiplied
4
3
4
8
16
Oscillation clock fC (MHz)
The AC ratings are measured for the following measurement reference voltages
• Input signal waveform
Hystheresis input pin
• Output signal waveform
Output pin
0.8 VCC
0.2 VCC
2.4 V
0.8 V
Pins other than hystheresis input/MD input
0.7 VCC
0.3 VCC
82
MB90580C Series
(2) Clock Output Timings
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Condition
Unit Remarks
Min.
62.5
20
Max.
Clock cycle time
tCYC
CLK
tCHCL
ns
ns
VCC = 5 V ± 10%
CLK↑ → CLK↓
tCYC
tCHCL
2.4 V
2.4 V
0.8 V
CLK
(3) Reset, Hardware Standby Input Timing
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit Remarks
Min.
4 tCP
4 tCP
Max.
Reset input time
tRSTL
tHSTL
RST
HST
ns
ns
Hardware standby input time
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
83
MB90580C Series
(4) Power-on Reset
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
Max.
Power supply rising time
Power supply cut-off time
tR
VCC
VCC
0.05
30
ms
ms
Due to repeated
operations
tOFF
4
* : VCC must be kept lower than 0.2 V before power-on.
Note The above values are used for causing a power-on reset.
If HST = “L”, be sure to turn the power supply on using the above values to cause a power-on reset whether
or not the power-on reset is required.
Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the
power supply using the above values.
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recom-
mended to raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the volt-
age drop is 1 mV or fewer per second, however, you can use the PLL clock.
VCC
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
3.0 V
RAM data hold
VSS
84
MB90580C Series
(5) Bus Timing (Read)
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
ALE pulse width
tLHLL
tAVLL
ALE
tCP/2 − 20
ns
ns
Effective address →
ALE ↓ time
ALE, A23 to A16,
AD15 to AD00
tCP/2 − 20
tCP/2 − 15
tCP − 15
ALE ↓ → address
effective time
tLLAX
ALE, AD15 to AD00
ns
ns
Effective address →
RD ↓ time
A23 to A16,
AD15 to AD00, RD
tAVRL
Effective address →
valid data input
A23 to A16,
AD15 to AD00
tAVDV
tRLRH
tRLDV
5 tCP/2 − 60 ns
ns
RD pulse width
RD
3 tCP/2 − 20
RD ↓ → valid data
input
RD, AD15 to AD00
3 tCP/2 − 60 ns
RD ↑ → data hold
time
tRHDX
tRHLH
tRHAX
RD, AD15 to AD00
RD, ALE
0
ns
ns
ns
RD ↑ → ALE ↑ time
tCP/2 − 15
tCP/2 − 10
RD ↑ → address
effective time
ALE, A23 to A16
Effective address →
CLK ↑ time
A23 to A16,
AD15 to AD00, CLK
tAVCH
tCP/2 − 20
ns
RD ↓ → CLK ↑ time
ALE ↓ → RD ↓ time
tRLCH
tLLRL
RD, CLK
ALE, RD
tCP/2 − 20
tCP/2 − 15
ns
ns
85
MB90580C Series
• Bus Timing (Read)
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
ALE
RD
tLHLL
tAVLL
tRLRH
2.4 V
tLLAX
tLLRL
0.8 V
tAVRL
tRLDV
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tAVDV
tRHDX
2.4 V
0.8 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
AD15 to
AD00
Write data
Address
86
MB90580C Series
(6) Bus Timing (Write)
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
A23 to A16,
AD15 to AD00,
WRH, WRL
Effective address →
WRH, WRL↓ time
tAVWL
tWLWH
tDVWH
tWHDX
tWHAX
tCP − 15
ns
ns
ns
ns
ns
WRH, WRL pulse
width
WRH, WRL
3 tCP/2 − 20
3 tCP/2 − 20
20
Effectivedataoutput
→ WRH, WRL ↑
time
AD15 to AD00,
WRH, WRL
WRH, WRL ↑ →
data hold time
WRH, WRL,
AD15 to AD00
WRH, WRL ↑ → ad-
dress
WRH, WRL, A23 to A16
tCP/2 − 10
effective time
WRH, WRL ↑ →
ALE ↑ time
tWHLH
tWLCH
WRH, WRL, ALE
WRH, WRL, CLK
tCP/2 − 15
tCP/2 − 20
ns
ns
WRH, WRL ↓ →
CLK ↑ time
• Bus Timing (Write)
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tWLWH
WRH, WRL
2.4 V
0.8 V
tAVWL
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to
AD00
Write data
Address
87
MB90580C Series
(7) Ready Input Timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
45
Max.
RDY setup time
RDY hold time
tRYHS
tRYHH
ns
ns
RDY
0
Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.
2.4 V
2.4 V
CLK
ALE
RD/
WRH/
WRL
tRYHS
tRYHS
0.2 VCC
0.8 VCC
0.2 VCC
RDY
(wait inserted)
0.8 VCC
RDY
(wait not
inserted)
tRYHH
88
MB90580C Series
(8) Hold Timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name Condition
Unit Remarks
Parameter
Min.
30
Max.
tCP
Pins in floating status → HAK ↓ time
HAK ↑ → pin valid time
tXHAL
tHAHV
HAK
HAK
ns
ns
tCP
2 tCP
Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
HAK
2.4 V
0.8 V
tXHAL
tHAHV
2.4 V
0.8 V
2.4 V
0.8 V
Pins
High impedance
89
MB90580C Series
(9) UART0 to UART4
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min. Max.
Serial clock cycle time
tSCYC
tSLOV
SCK0 to SCK4
8 tCP
ns
ns
SCK0 to SCK4,
SOT0 to SOT4
SCK ↓ → SOT delay time
−80
100
60
80
CL = 80 pF + 1 TTL
for an output pin of
internal shift clock
mode
SCK0 to SCK4,
SIN0 to SIN4
Valid SIN → SCK ↑
tIVSH
ns
ns
SCK0 to SCK4,
SIN0 to SIN4
SCK ↑ → valid SIN hold time
tSHIX
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
SCK0 to SCK4
SCK0 to SCK4
4 tCP
ns
ns
tSLSH
4 tCP
SCK0 to SCK4,
SOT0 to SOT4
CL = 80 pF + 1 TTL
for an output pin of
external shift clock
mode
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
150
ns
ns
ns
SCK0 to SCK4,
SIN0 to SIN4
60
60
SCK0 to SCK4,
SIN0 to SIN4
SCK ↑ → valid SIN hold time
Note : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
• tCP is machine cycle time (unit:ns).
90
MB90580C Series
• Internal shift clock mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
0.2 VCC
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
91
MB90580C Series
(10)Timer Input Timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
tTIWH
tTIWL
IN0 to IN3,
TIN0 to TIN2
Input pulse width
4 tCP
ns
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(11) Timer Output Timing
Parameter
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
OUT0, OUT1,
PPG0, PPG1,
TOT0 to TOT2
CLK↑→TOUT transition time
tTO
30
ns
2.4 V
CLK
tTO
2.4 V
0.8 V
TOUT
92
MB90580C Series
(12) Trigger Input Timimg
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
tTRGH
tTRGL
IRQ0 to IRQ7,
ADTG
Input pulse width
5 tCP
ns
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL
93
MB90580C Series
(13) IEBusTM Timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Condition
Unit Remarks
Parameter
Min.
Max.
1000
1000
TX → RX delay time (rise)
TX → RX delay time (fall)
tDLY1
TX, RX
TX, RX
0
0
ns
ns
tDLY2
0.7 VCC
tDLY1
TX
RX
0.3 VCC
0.7 VCC
0.3 VCC
tDLY2
MB90580C
series
Driver/ receiver
TX
RX
TX
RX
BUS+
BUS−
IEBusTM
94
MB90580C Series
5. A/D Converter Electrical Characteristics
(3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Unit Remarks
Parameter
Resolution
Min.
Typ.
Max.
10
bit
Total error
±5.0
±2.5
±1.9
LSB
LSB
LSB
Non-linear error
Differential linearity error
AN0 to
AN7
Zero transition voltage
VOT
AVSS − 3.5
+0.5
AVSS + 4.5
mV
AN0 to
Full-scale transition voltage
VFST
AN7
AVRH − 6.5 AVRH − 1.5 AVRH + 1.5 mV
Conversion time
Sampling period
176 tCP
64 tCP
ns
ns
AN0 to
AN7
Analog port input current
Analog input voltage
IAIN
10
µA
AN0 to
AN7
VAIN
AVRL
AVRH
V
AVRH
AVRL
AVRL + 2.7
AVCC
V
V
Reference voltage
0
AVRH − 2.7
IA
IAH
IR
AVCC
AVCC
5
mA
µA
µA
µA
Power supply current
5
*
*
AVRH
AVRH
400
Reference voltage supply
current
IRH
5
4
AN0 to
AN7
Offset between channels
—
LSB
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = 5.0 V)
Note: • The error increases proportionally as |AVRH - AVRL| decreases.
•The output impedance of the external circuits connected to the analog inputs should be in the following
range.
•The output impedance of the external circuit : 15.5 kΩ (Max.) (Sampling time = 4.0 µs)
•If the output impedance of the external circuit is too high, the sampling time might be insufficient.
C0
Comparator
Analog input
C1
95
MB90580C Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error : The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
0.5 LSB
3FE
Actualconversion
value
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
VNT
(Measured value)
Actualconversion
value
Theoretical
characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
Total error for digital output N =
[LSB]
1 LSB
AVRH − AVRL
[V]
1 LSB = (Theoretical value)
1024
VOT(Theoretical value) = AVRL + 0.5 LSB [V]
VFST(Theoretical value) = AVRH − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
96
MB90580C Series
(Continued)
Linearity error
Actualconversion
value
{1 LSB × (N − 1)
+ VOT }
Differential linearity error
Theoretical
characteristics
3FF
3FE
3FD
Actualconversion
value
N + 1
VFST
(Measured
value)
N
VNT
(measured value)
004
003
002
001
V(N + 1)T
Actual conversion
value
(Measured value)
N − 1
N − 2
VNT
(Measured value)
Actualconversion
value
Theoretical
characteristics
VOT(Measured value)
AVRL
AVRH
AVRL
AVRH
Analog input
Analog input
Linearity error of
digital output N
VNT − {1 LSB × (N − 1) + VOT}
=
=
[LSB]
1 LSB
Differential linearity error
of digital output N
V (N + 1) T − VNT
− 1 LSB[LSB]
1 LSB
VFST − VOT
[V]
1 LSB =
1022
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
97
MB90580C Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions.
Output impedance values of the external circuit of 7 kΩ or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor
value is recommended to minimized the effect of voltage distribution between the external capacitor and internal
capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages may not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz)
• Equipment of analog input circuit model
C0
Analog input
Comparator
C1
MB90587, MB90V580B
MB90F583B
MB90583B
R
R
R
1.5 kΩ, C 30 pF
3.0 kΩ, C 65 pF
2.2 kΩ, C 45 pF
Note: Listed values must be considered as standards.
• Error
The smaller the | AVRH - AVRL |, the greater the error would become relatively.
8. D/A Converter Electrical Characteristics
(VCC = AVCC = 5.0 V±10%, VSS = AVSS = DVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol Pin name
Unit
Remarks
Parameter
Resolution
Min.
Typ.
Max.
8
bit
LSB
%
Differential linearity error
Absolute accuracy
Linearity error
±0.9
±1.2
±1.5
20
LSB
Conversion time
10
120
20
µs *1
V
Analog reference voltage
DVRH
VSS + 3.0
AVCC
300
10
IDVR
µA
Reference voltage supply
current
DVRH
IDVRS
µA *2
kΩ
Analog output impedance
*1 : Load capacitance: 20 pF
*2 : In sleep mode
98
MB90580C Series
■ EXAMPLE CHARACTERISTICS
• Power Suppy Current of MB90F583C/CA
ICC vs. VCC
TA = 25 °C, external clock input
ICCS vs. VCC
TA = 25 °C, external clock input
45
20
15
10
5
f = 16 MHz
40
35
30
25
20
15
10
5
f = 16 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
f = 4 MHz
f = 2 MHz
0
2
3
4
5
6
VCC (V)
0
2
3
4
5
6
VCC (V)
ICCL vs. VCC
ICCLS vs. VCC
TA = 25 °C, external clock input
TA = 25 °C, external clock input
(MB90F583C only)
(MB90F583C only)
70
f = 8 kHz
50
45
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
f = 8 kHz
0
2
3
4
5
6
VCC (V)
2
3
4
5
6
VCC (V)
(Continued)
99
MB90580C Series
(Continued)
ICCT vs. VCC
TA = 25 °C, external clock input
(MB90F583C only)
30
28
26
24
22
20
28
16
14
12
10
8
f = 8 kHz
6
4
2
0
2
3
4
5
6
VCC (V)
VOH vs. IOH
TA = 25 °C, VCC = 4.5 V
VOL vs. IOL
TA = 25 °C, VCC = 4.5 V
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8 9 10 11 12
7
11
12
3
5
8
9 10
1
2
4
6
0
IOH (mA)
IOL (mA)
100
MB90580C Series
Power Suppy Current of MB90583C/CA
ICC vs. VCC
TA = 25 °C, external clock input
ICCS vs. VCC
TA = 25 °C, external clock input
30
20
15
10
5
f = 16 MHz
25
20
15
10
5
f = 16 MHz
f = 12 MHz
f = 12 MHz
f = 10 MHz
f = 8 MHz
f = 10 MHz
f = 8 MHz
f = 4 MHz
f = 2 MHz
f = 4 MHz
f = 2 MHz
0
2
3
4
5
6
VCC (V)
0
2
3
4
5
6
VCC (V)
ICCL vs. VCC
ICCLS vs. VCC
TA = 25 °C, external clock input
TA = 25 °C, external clock input
(MB90583C only)
(MB90583C only)
70
50
45
40
35
30
25
20
15
10
5
f = 8 kHz
60
50
40
30
20
10
0
f = 8 kHz
0
2
3
4
5
6
VCC (V)
2
3
4
5
6
VCC (V)
(Continued)
101
MB90580C Series
(Continued)
ICCT vs. VCC
TA = 25 °C, external clock input
(MB90583C only)
30
28
26
24
22
20
28
16
14
12
10
8
f = 8 kHz
6
4
2
0
2
3
4
5
6
VCC (V)
VOL vs. IOL
VOH vs. IOH
TA = 25 °C, VCC = 4.5 V
TA = 25 °C, VCC = 4.5 V
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
4
5
6
7
8
9
10
12
11
2
3
0
1
8
0
1
3
4
5
6
7
9
10 11
2
12
IOH (mA)
IOL (mA)
102
MB90580C Series
■ INSTRUCTIONS (351 INSTRUCTIONS)
Table 1 Explanation of Items in Tables of Instructions
Meaning
Mnemonic Upper-case letters and symbols: Represented as they appear in assembler.
Item
Lower-case letters: Replaced when described in assembler.
Numbers after lower-case letters:Indicate the bit width within the instruction code.
#
~
Indicates the number of bytes.
Indicates the number of cycles.
m: When branching
n : When not branching
See Table 4 for details about meanings of other letters in items.
RG
B
Indicates the number of accesses to the register during execution of the instruction.
It is used calculate a correction value for intermittent operation of CPU.
Indicates the correction value for calculating the number of actual cycles during execution of the
instruction. (Table 5)
The number of actual cycles during execution of the instruction is the correction value summed
with the value in the “~” column.
Operation
LH
Indicates the operation of instruction.
Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.
Z : Transfers “0”.
X : Extends with a sign before transferring.
– : Transfers nothing.
AH
Indicates special operations involving the upper 16 bits in the accumulator.
* : Transfers from AL to AH.
– : No transfer.
Z : Transfers 00H to AH.
X : Transfers 00H or FFH to AH by signing and extending AL.
I
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),
N (negative), Z (zero), V (overflow), and C (carry).
* : Changes due to execution of instruction.
– : No change.
S
T
N
Z
S : Set by execution of instruction.
R : Reset by execution of instruction.
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that
reads data from memory, etc., processes the data, and then writes the result to memory.)
* : Instruction is a read-modify-write instruction.
– : Instruction is not a read-modify-write instruction.
Note: A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
• Number of execution cycles
The number of cycles required for instruction execution is acquired by adding the number of cycles for each
instruction, a corrective value depending on the condition, and the number of cycles required for program fetch.
Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal
ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution
cycles is increased.
For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data
bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased.
When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external
bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles
specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number
of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the
number of times access is done × the number of cycles suspended as the corrective value to the number of
ordinary execution cycles.
103
MB90580C Series
Table 2 Explanation of Symbols in Tables of Instructions
Meaning
Symbol
A
32-bit accumulator
The bit length varies according to the instruction.
Byte : Lower 8 bits of AL
Word : 16 bits of AL
Long : 32 bits of AL and AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
PC
Stack pointer (USP or SSP)
Program counter
PCB
DTB
ADB
SSB
USB
SPB
DPR
brg1
brg2
Ri
Program bank register
Data bank register
Additional data bank register
System stack bank register
User stack bank register
Current stack bank register (SSB or USB)
Direct page register
DTB, ADB, SSB, USB, DPR, PCB, SPB
DTB, ADB, SSB, USB, DPR, SPB
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RW0, RW1, RW2, RW3
RWi
RWj
RLi
RL0, RL1, RL2, RL3
dir
Compact direct addressing
addr16
addr24
ad24 0 to 15
ad24 16 to 23
Direct addressing
Physical direct addressing
Bit 0 to bit 15 of addr24
Bit 16 to bit 23 of addr24
io
I/O area (000000H to 0000FFH)
imm4
imm8
4-bit immediate data
8-bit immediate data
imm16
imm32
ext (imm8)
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
disp8
disp16
8-bit displacement
16-bit displacement
bp
Bit offset
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
rel
Bit address
PC relative addressing
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
Register list
104
MB90580C Series
Table 3 Effective Address Fields
Address format
Number of bytes in address
extension *
Code
Notation
00
01
02
03
04
05
06
07
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0 Register direct
(RL0)
RL1 “ea” corresponds to byte, word, and
(RL1) long-word types, starting from the left
RL2
(RL2)
RL3
—
(RL3)
08
09
0A
0B
@RW0
Register indirect
@RW1
@RW2
@RW3
0
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
1
2
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacement
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)
column in the tables of instructions.
105
MB90580C Series
Table 4 Number of Execution Cycles for Each Type of Addressing
(a)
Number of register accesses
for each type of addressing
Code
Operand
Number of execution cycles
for each type of addressing
Ri
RWi
RLi
00 to 07
Listed in tables of instructions Listed in tables of instructions
08 to 0B
0C to 0F
10 to 17
18 to 1B
@RWj
2
4
2
2
1
2
1
1
@RWj +
@RWi + disp8
@RWj + disp16
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
(c) word
(d) long
Operand
Cycles
Access
Cycles
Access
Cycles
Access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Internal memory
Byte boundary
Word boundary
—
—
+3
+2
+3
—
External data bus (16 bits)
External data bus (8 bits)
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
106
MB90580C Series
Table 7 Transfer Instructions (Byte) [41 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
2
3
1
2
3
4
2
2
0
0
1
1
0
0
0
0
2
0
(b) byte (A) ← (dir)
(b) byte (A) ← (addr16)
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
2+ 3+ (a)
(b) byte (A) ← (eam)
(b) byte (A) ← (io)
2
2
2
3
1
3
2
3
10
1
0
byte (A) ← imm8
(b) byte (A) ← ((A))
(b) byte (A) ← ((RLi)+disp8) Z
MOVN A, #imm4
0
byte (A) ← imm4
Z
– R
MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A,@RWi+disp8
MOVX A, @RLi+disp8
2
3
2
2
3
4
2
2
0
0
1
1
0
0
0
0
1
2
(b) byte (A) ← (dir)
(b) byte (A) ← (addr16)
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (A) ← (Ri)
byte (A) ← (ear)
2+ 3+ (a)
(b) byte (A) ← (eam)
(b) byte (A) ← (io)
2
2
2
2
3
3
2
3
5
10
0
byte (A) ← imm8
(b) byte (A) ← ((A))
(b) byte (A) ← ((RWi)+disp8) X
(b) byte (A) ← ((RLi)+disp8) X
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
2
3
1
2
3
4
2
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
(b) byte (dir) ← (A)
(b) byte (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
byte (Ri) ← (A)
byte (ear) ← (A)
2+ 3+ (a)
(b) byte (eam) ← (A)
(b) byte (io) ← (A)
(b) byte ((RLi) +disp8) ← (A) –
2
3
2
3
10
3
0
byte (Ri) ← (ear)
(b) byte (Ri) ← (eam)
byte (ear) ← (Ri)
(b) byte (eam) ← (Ri)
byte (Ri) ← imm8
–
–
–
–
–
–
–
–
–
2+ 4+ (a)
2
2+ 5+ (a)
2
3
3
3
4
0
2
5
5
2
0
(b) byte (io) ← imm8
(b) byte (dir) ← imm8
0
byte (ear) ← imm8
3+ 4+ (a)
(b) byte (eam) ← imm8
/MOV @A, T
2
2
3
0
(b) byte ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCH
XCH
XCH
XCH
A, ear
4
2
0
4
2
0
byte (A) ↔ (ear)
2× (b) byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
2× (b) byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A, eam
Ri, ear
Ri, eam
2+ 5+ (a)
2
2+ 9+ (a)
7
0
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
107
MB90580C Series
Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
#
~
B
Operation
2
3
1
1
2
3
4
1
2
2
0
0
0
1
1
0
0
0
0
1
2
(c) word (A) ← (dir)
(c) word (A) ← (addr16)
0
0
0
(c) word (A) ← (eam)
(c) word (A) ← (io)
(c) word (A) ← ((A))
0
(c)
(c)
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
2+ 3+ (a)
2
2
3
2
3
3
3
2
5
10
MOVW A, #imm16
MOVW A,@RWi+disp8
MOVW A, @RLi+disp8
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
MOVW dir, A
MOVW addr16, A
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8,A
MOVW @RLi+disp8, A
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
MOVW @AL, AH
/MOVW@A, T
2
3
1
1
2
3
4
1
2
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c) word (dir) ← (A)
(c) word (addr16) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
2+ 3+ (a)
(c) word (eam) ← (A)
(c) word (io) ← (A)
2
2
3
2
3
5
10
3
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
(c)
(c)
(0) word (RWi) ← (ear)
(c) word (RWi) ← (eam)
2+ 4+ (a)
2
2+ 5+ (a)
3
4
4
4
0
word (ear) ← (RWi)
(c) word (eam) ← (RWi)
word (RWi) ← imm16
(c) word (io) ← imm16
word (ear) ← imm16
2
5
2
0
0
4+ 4+ (a)
(c) word (eam) ← imm16
2
3
4
0
(c) word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCHW A, ear
2
2
0
4
2
0
word (A) ↔ (ear)
2× (c) word (A) ↔ (eam)
word (RWi) ↔ (ear)
2× (c) word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam
2+ 5+ (a)
2
2+ 9+ (a)
7
0
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
4
2
0
0
0
long (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2+ 5+ (a)
5
(d) long (A) ← (eam)
0
3
long (A) ← imm32
long (ear) ← (A)
MOVL ear, A
MOVL eam, A
2
4
2
0
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
2+ 5+ (a)
(d) long (eam) ← (A)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
108
MB90580C Series
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
ADD A,#imm8
#
~
B
Operation
2
2
2
2
5
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
byte (A) ← (A) +imm8
Z
Z
Z
Z
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
ADD
ADD
ADD
ADD
ADD
ADDC
A, dir
A, ear
A, eam
ear, A
eam, A
A
(b) byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
(b) byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
2× (b) byte (eam) ← (eam) + (A)
0
2+ 4+ (a)
2
2+ 5+ (a)
1
2
3
0
2
3
0
0
byte (A) ← (AH) + (AL) + (C) Z
byte (A) ← (A) + (ear) + (C)
ADDC A, ear
ADDC A, eam
ADDDC A
Z
2+ 4+ (a)
(b) byte (A) ← (A) + (eam) + (C) Z
byte (A) ← (AH) + (AL) + (C) (decimal)
1
2
2
2
3
2
5
3
0
0
Z
Z
Z
Z
Z
–
–
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
byte (A) ← (A) –imm8
(b) byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
(b) byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
2× (b) byte (eam) ← (eam) – (A)
0
2+ 4+ (a)
2
2+ 5+ (a)
1
2
2+ 4+ (a)
1
3
0
2
3
0
0
byte (A) ← (AH) – (AL) – (C) Z
byte (A) ← (A) – (ear) – (C)
–
–
–
–
SUBC A, ear
SUBC A, eam
SUBDC A
Z
(b) byte (A) ← (A) – (eam) – (C) Z
byte (A) ← (AH) – (AL) – (C) (decimal)
3
0
Z
ADDW A
1
2
2
3
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCWA, ear
ADDCWA, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
2+ 4+ (a)
3
2
2+ 5+ (a)
2
2+ 4+ (a)
1
2
2+ 4+ (a)
3
2
(c) word (A) ← (A) +(eam)
0
0
2
3
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
2× (c) word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
3
0
(c) word (A) ← (A) + (eam) + (C) –
0
0
(c) word (A) ← (A) – (eam)
0
0
2
3
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
–
–
–
–
–
–
–
2
3
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
2+ 5+ (a)
2
2+ 4+ (a)
2× (c) word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
3
0
–
–
(c) word (A) ← (A) – (eam) – (C) –
ADDL A, ear
2
6
2
0
0
2
0
0
0
long (A) ← (A) + (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
ADDL A, eam
ADDL A, #imm32
SUBL A, ear
SUBL A, eam
SUBL A, #imm32
2+ 7+ (a)
5
2
2+ 7+ (a)
5
(d) long (A) ← (A) + (eam)
0
0
4
6
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
(d) long (A) ← (A) – (eam)
long (A) ← (A) –imm32
4
0
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
109
MB90580C Series
Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
INC
INC
ear
eam
2
2
2
0
0
byte (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (b) byte (eam) ← (eam) +1
DEC
DEC
ear
eam
2
3
2
0
0
byte (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (b) byte (eam) ← (eam) –1
INCW ear
INCW eam
2
3
2
0
0
word (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (c) word (eam) ← (eam) +1
DECW ear
DECW eam
2
3
2
0
0
word (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 5+ (a)
2× (c) word (eam) ← (eam) –1
INCL ear
INCL eam
2
7
4
0
0
long (ear) ← (ear) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 9+ (a)
2× (d) long (eam) ← (eam) +1
DECL ear
DECL eam
2
7
4
0
0
long (ear) ← (ear) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
2+ 9+ (a)
2× (d) long (eam) ← (eam) –1
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
CMP
A
1
2
1
2
0
1
0
0
0
0
byte (AH) – (AL)
byte (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMP
CMP
CMP
A, ear
A, eam
A, #imm8
2+ 3+ (a)
2
(b) byte (A) ← (eam)
0
2
byte (A) ← imm8
CMPW A
1
2
1
2
0
1
0
0
0
0
word (AH) – (AL)
word (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW A, ear
CMPW A, eam
CMPW A, #imm16
2+ 3+ (a)
3
(c) word (A) ← (eam)
0
2
word (A) ← imm16
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
6
2
0
0
0
word (A) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
2+ 7+ (a)
5
(d) word (A) ← (eam)
word (A) ← imm32
3
0
Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
110
MB90580C Series
Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
RG
Mnemonic
#
~
B
Operation
1
DIVU
A
1
0
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
Quotient → byte (AL) Remainder → byte (AH)
2
DIVU
DIVU
A, ear
2
1
0
1
0
0 word (A)/byte (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
Quotient → byte (A) Remainder → byte (ear)
6
3
A, eam 2+
word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
*
*
4
DIVUW A, ear
2
long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
0
*
7
5
DIVUW A, eam 2+
long (A)/word (eam)
Quotient → word (A) Remainder → word (eam)
*
*
8
MULU
MULU A, ear
MULU A, eam 2+
A
1
2
0
1
0
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
(b)
*
9
*
10
*
MULUW A
MULUW A, ear
MULUW A, eam 2+
1
2
11
12
13
0
1
0
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
(c)
*
*
*
*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.
*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.
*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.
*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.
*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.
*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.
*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.
*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.
*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.
*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
111
MB90580C Series
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
DIV
A
2
*1
0
0
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
word (A)/byte (ear)
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
DIV
A, ear
2
*2
1
0
1
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
Quotient → byte (A)
Remainder → byte (ear)
DIV
A, eam 2 + *3
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
long (A)/word (ear)
DIVW
DIVW
A, ear
2
*4
0
Quotient → word (A)
Remainder → word (ear)
A, eam 2+ *5
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
MULU
MULU
MULU
MULUW A
MULUW A, ear
A
A, ear
A, eam 2 + *10
2
2
*8
*9
0
1
0
0
1
0
0
0
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
(b) byte (A) *byte (eam) → word (A)
0
0
2
2
*11
*12
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
MULUW A, eam 2 + *13
(c) word (A) *word (eam) → long (A)
*1: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.
*2: Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.
*3: Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
*4: Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.
*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for
normal operation.
Negative dividend:Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for
normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: Setto4+(a)whenbyte(eam)iszero, 13+(a)whentheresultispositive, and14+(a)whentheresultisnegative.
*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is
negative.
Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes
two values because of detection before and after an operation.
• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”
and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
112
MB90580C Series
Table 14 Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
AND A, #imm8
#
~
B
Operation
2
2
2
3
0
1
0
2
0
0
0
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
AND
AND
AND
AND
A, ear
A, eam
ear, A
2+ 4+ (a)
2
2+ 5+ (a)
(b) byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
3
0
eam, A
2× (b) byte (eam) ← (eam) and (A) –
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
2
2
2
3
0
1
0
2
0
0
0
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
2+ 4+ (a)
2
2+ 5+ (a)
(b) byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
2× (b) byte (eam) ← (eam) or (A)
3
0
eam, A
XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
2
2
2
3
0
1
0
2
0
0
0
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
2+ 4+ (a)
2
2+ 5+ (a)
(b) byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
3
0
2× (b) byte (eam) ← (eam) xor (A) –
NOT
NOT
NOT
A
ear
eam
1
2
2
3
0
2
0
0
0
byte (A) ← not (A)
byte (ear) ← not (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
2+ 5+ (a)
2× (b) byte (eam) ← not (eam)
ANDW A
1
3
2
2
2
3
0
0
1
0
2
0
0
0
0
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A
2+ 4+ (a)
2
2+ 5+ (a)
(c) word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
2× (c) word (eam) ← (eam) and (A)
3
0
ORW
A
1
3
2
2
2
3
0
0
1
0
2
0
0
0
0
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
2+ 4+ (a)
2
2+ 5+ (a)
(c) word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
2× (c) word (eam) ← (eam) or (A)
3
0
ORW eam, A
XORW A
1
3
2
2
2
3
0
0
1
0
2
0
0
0
0
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
2+ 4+ (a)
2
2+ 5+ (a)
(c) word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
2× (c) word (eam) ← (eam) xor (A)
3
0
NOTW A
NOTW ear
NOTW eam
1
2
2
3
0
2
0
0
0
word (A) ← not (A)
word (ear) ← not (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
2+ 5+ (a)
2× (c) word (eam) ← not (eam)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
113
MB90580C Series
Table 15 Logical 2 Instructions (Long Word) [6 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
ANDL A, ear
ANDL A, eam
2
6
2
0
0
long (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) and (eam)
ORL
ORL
A, ear
A, eam
2
6
2
0
0
long (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) or (eam)
XORL A, ea
XORL A, eam
2
6
2
0
0
long (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) xor (eam)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16 Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
NEG
A
1
2
0
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
NEG ear
NEG eam
2
3
2
0
0
byte (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a)
2× (b) byte (eam) ← 0 – (eam)
NEGW A
1
2
0
0
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
NEGW ear
NEGW eam
2
3
2
0
0
word (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a)
2× (c) word (eam) ← 0 – (eam)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17 Normalize Instruction (Long Word) [1 Instruction]
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
RG
B
Operation
1
NRML A, R0
2
1
0
long (A) ← Shift until first digit is “1” –
byte (R0) ← Current shift count
–
–
–
–
–
*
–
–
–
*
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
114
MB90580C Series
Table 18 Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
RORC A
#
~
B
Operation
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
2
2
2
2
0
0
0
0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
2
2+
2
3
2
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
5+ (a)
0 2× (b)
2
0 2× (b)
0
3
2+
5+ (a)
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
ASR A, R0
LSR A, R0
LSL A, R0
1
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
1
*
1
*
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
ASRW A
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
0
0
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
R
*
*
*
*
–
–
–
*
*
*
–
–
–
1
word (A) ← Arithmetic right barrel shift (A,
R0)
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
1
*
1
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
*
2
ASRL A, R0
LSRL A, R0
LSLL A, R0
long (A) ← Arithmetic right shift (A, R0)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
2
2
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*
2
*
2
*
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
115
MB90580C Series
Table 19 Branch 1 Instructions [31 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
BZ/BEQ
BNZ/BNE rel
BC/BLO
BNC/BHS rel
rel
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1
Branch when ((V) xor (N)) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
rel
1
1
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
1
1
1
1
1
1
1
1
1
1
1
1
*
JMP
JMP
JMP
JMP
@A
1
3
2
2
3
3
0
0
1
0
2
0
0
0
0
0
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
addr16
@ear
@eam
2+ 4+ (a)
2
2+ 6+ (a)
4
(c) word (PC) ← (eam)
0
(d)
0
JMPP @ear *3
JMPP @eam *3
JMPP addr24
word (PC) ← (ear), (PCB) ← (ear +2)
5
word (PC) ← (eam), (PCB) ← (eam +2)
4
word (PC) ← ad24 0 to 15,
(PCB) ← ad24 16 to 23
CALL @ear *4
CALL @eam *4
CALL addr16 *5
CALLV #vct4 *5
CALLP @ear *6
2
6
1
0
0
0
2
(c) word (PC) ← (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2+ 7+ (a)
2× (c) word (PC) ← (eam)
(c) word (PC) ← addr16
2× (c) Vector call instruction
2× (c) word (PC) ← (ear) 0 to 15,
3
1
2
6
7
10
(PCB) ← (ear) 16 to 23
2
CALLP @eam *6
CALLP addr24 *7
2+ 11+ (a)
10
0
0
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr0 to 15,
(PCB) ← addr16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
4
2× (c)
*1: 4 when branching, 3 when not branching.
*2: (b) + 3 × (c)
*3: Read (word) branch address.
*4: W: Save (word) to stack; R: read (word) branch address.
*5: Save (word) to stack.
*6: W: Save (long word) to W stack; R: read (long word) R branch address.
*7: Save (long word) to stack.
Note:Foranexplanationof“(a)”to“(d)”, refertoTable4, “NumberofExecutionCyclesforEachTypeofAddressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
116
MB90580C Series
Table 20 Branch 2 Instructions [19 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
1
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
3
4
0
0
0
0
–
–
– – – – *
– – – – *
*
*
*
*
*
*
–
–
*
*
1
2
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
CBNE ear, #imm8, rel
4
4+
5
*
*
*
*
1
0
1
0
0
(b)
0
–
–
–
–
– – – – *
– – – – *
– – – – *
– – – – *
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CBNE
eam, #imm8, rel*10
3
4
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
3
5+
(c)
5
DBNZ ear, rel
DBNZ eam, rel
3
2
2
0
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
–
–
– – – – *
– – – – *
*
*
* –
* –
–
*
*
6
*
3+
2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
5
DWBNZ ear, rel
DWBNZ eam, rel
3
*
2
2
0
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
–
–
– – – – *
– – – – *
*
*
* –
* –
–
*
6
3+
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
*
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
8× (c)
6× (c)
6× (c)
8× (c)
2
3
4
1
1
0
0
0
0
0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
– R S – – – – –
– R S – – – – –
– R S – – – – –
– R S – – – – –
–
–
–
–
–
20
16
17
20
15
7
*
–
*
*
*
*
*
*
*
LINK
#imm8
(c)
(c)
2
0
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
– – – – – – – –
–
6
UNLINK
1
0
–
– – – – – – – –
–
5
RET *8
(c)
(d)
1
1
0
0
Return from subroutine
Return from subroutine
–
–
– – – – – – – –
– – – – – – – –
–
–
4
6
RETP *9
*1: 5 when branching, 4 when not branching
*2: 13 when branching, 12 when not branching
*3: 7 + (a) when branching, 6 + (a) when not branching
*4: 8 when branching, 7 when not branching
*5: 7 when branching, 6 when not branching
*6: 8 + (a) when branching, 7 + (a) when not branching
*7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return.
*8: Retrieve (word) from stack
*9: Retrieve (long word) from stack
*10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
117
MB90580C Series
Table 21 Other Control Instructions (Byte/Word/Long Word) [28 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
#
~
B
Operation
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
1
1
1
2
4
4
4
0
0
0
(c)
(c)
(c)
–
–
–
–
–
–
–
–
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
–
–
–
–
3
5
4
*
*
*
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
POPW A
1
1
1
2
–
–
–
–
*
– – – – – – –
– – – – – – –
–
–
–
–
3
3
4
0
0
0
(c)
(c)
(c)
POPW AH
POPW PS
POPW rlst
–
–
–
*
*
*
*
*
*
*
2
5
4
– – – – – – –
*
*
*
JCTX @A
1
Context switch instruction
–
–
*
*
*
*
*
*
*
–
14
0
6× (c)
AND CCR, #imm8
OR CCR, #imm8
2
2
byte (CCR) ← (CCR) and imm8 –
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
3
3
0
0
0
0
byte (CCR) ← (CCR) or imm8
–
MOV RP, #imm8
MOV ILM, #imm8
2
2
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
– – – – – – –
– – – – – – –
–
–
2
2
0
0
0
0
MOVEA RWi, ear
MOVEA RWi, eam 2+
MOVEA A, ear
MOVEA A, eam
2
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
–
–
–
–
–
–
*
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
–
–
–
–
3
1
1
0
0
0
0
0
0
2+ (a)
1
1+ (a)
2
2+
word (A) ←eam
*
ADDSP #imm8
ADDSP #imm16
2
3
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
– – – – – – –
– – – – – – –
–
–
3
3
0
0
0
0
1
MOV
MOV
A, brgl
brg2, A
2
2
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
– – –
– – –
*
*
*
*
– –
– –
–
–
0
0
0
0
*
1
NOP
ADB
DTB
PCB
SPB
NCC
CMR
1
1
1
1
1
1
1
No operation
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
– – – – – – –
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Prefix code for accessing AD space
Prefix code for accessing DT space
Prefix code for accessing PC space
Prefix code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state
DTB, DPR : 2 states
*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)
*3: 29 +3 × (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)
*4: Pop count × (c), or push count × (c)
*5: Pop count or push count.
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
118
MB90580C Series
Table 22 Bit Manipulation Instructions [21 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b) byte (A) ← (dir:bp) b
(b) byte (A) ← (addr16:bp) b
(b) byte (A) ← (io:bp) b
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
7
7
6
0
0
0
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
1
BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel
4
5
4
0
0
0
(b) Branch when (dir:bp) b = 0
(b) Branch when (addr16:bp) b = 0
(b) Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
1
2
1
BBS dir:bp, rel
BBS addr16:bp, rel
BBS io:bp, rel
4
5
4
0
0
0
(b) Branch when (dir:bp) b = 1
(b) Branch when (addr16:bp) b = 1
(b) Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
1
2
3
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel
WBTS io:bp
5
3
3
0
0
0
2× (b)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
–
–
*
*
5
4
Wait until (io:bp) b = 1
Wait until (io:bp) b = 0
–
–
–
–
*
*
*
4
5
WBTC io:bp
*
*1: 8 when branching, 7 when not branching
*2: 7 when branching, 6 when not branching
*3: 10 when condition is satisfied, 9 when not satisfied
*4: Undefined count
*5: Until condition is satisfied
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 23 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
SWAP
SWAPW/XCHW A,T
EXT
EXTW
ZEXT
#
~
B
Operation
1
1
1
1
1
1
3
2
1
2
1
1
0
0
0
0
0
0
0 byte (A) 0 to 7 ↔ (A) 8 to 15
0 word (AH) ↔ (AL)
0 byte sign extension
0 word sign extension
0 byte zero extension
0 word zero extension
–
–
X
–
Z
–
–
*
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ZEXTW
*
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
119
MB90580C Series
Table 24 String Instructions [10 Instructions]
RG
LH AH
I
S
T
N
Z
V
C
RMW
Mnemonic
#
~
B
Operation
2
5
3
Byte transfer @AH+ ← @AL+, counter = RW0
Byte transfer @AH– ← @AL–, counter = RW0
MOVS/MOVSI
MOVSD
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
2
5
3
*
*
1
5
4
Byte retrieval (@AH+) – AL, counter = RW0
Byte retrieval (@AH–) – AL, counter = RW0
SCEQ/SCEQI
SCEQD
2
2
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
*
*
1
5
4
*
*
5
3
Byte filling @AH+ ← AL, counter = RW0
FISL/FILSI
2
–
–
–
–
–
*
*
–
–
–
6m +6
*
*
2
8
6
Word transfer @AH+ ← @AL+, counter = RW0
Word transfer @AH– ← @AL–, counter = RW0
MOVSW/MOVSWI 2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
2
8
6
MOVSWD
2
*
*
1
8
7
Word retrieval (@AH+) – AL, counter = RW0
Word retrieval (@AH–) – AL, counter = RW0
SCWEQ/SCWEQI
SCWEQD
2
2
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*
*
*
*
1
8
7
*
*
8
6
Word filling @AH+ ← AL, counter = RW0
FILSW/FILSWI
2
–
–
–
–
–
*
*
–
–
–
6m +6
*
*
m: RW0 value (counter value)
n: Loop count
*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs
*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case
*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) sepa-
rately for each.
*4: (b) × n
*5: 2 × (RW0)
*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c)
separately for each.
*7: (c) × n
*8: 2 × (RW0)
Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
120
MB90580C Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F583CPFV
MB90F583CAPFV
MB90583CPFV
MB90583CAPFV
MB90587CPFV
MB90587CAPFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90F583CPF
MB90F583CAPF
MB90583CPF
MB90583CAPF
MB90587CPF
MB90587CAPF
100-pin Plastic QFP
(FPT-100P-M06)
121
MB90580C Series
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
(FPT-100P-M05)
1.50 –+00..1200
.059 –+..000048
16.00±0.20(.630±.008)SQ
(Mouting height)
75
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
0.15(.006)
100
26
0.15(.006)MAX
0.40(.016)MAX
"B"
1
25
LEAD No.
"A"
0.50(.0197)TYP
0.18 –+00..0038
0.127 +–00..0025
.005 +–..000012
M
Details of "B" part
0.08(.003)
.007 –+..000013
0.10±0.10
(.004±.004)
(STAND OFF)
0.50±0.20(.020±.008)
0.10(.004)
0~10°
C
2000 FUJITSU LIMITED F100007S-2C-4
Dimensions in mm (inches)
122
MB90580C Series
100-pin plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
80
51
81
50
12.35(.486)
REF
14.00±0.20 17.90±0.40
(.551±.008) (.705±.016)
16.30±0.40
(.642±.016)
INDEX
31
100
"A"
1
30
LEAD No.
0.65(.0256)TYP
0.30±0.10
(.012±.004)
0.15±0.05(.006±.002)
Details of "B" part
M
0.13(.005)
Details of "A" part
0.25(.010)
0.30(.012)
"B"
0.10(.004)
0
10°
0.18(.007)MAX
0.53(.021)MAX
18.85(.742)REF
0.80±0.20
(.031±.008)
22.30±0.40(.878±.016)
C
2000 FUJITSU LIMITED F100008-3C-3
Dimensions in mm (inches)
123
MB90580C Series
FUJITSU LIMITED
For further information please contact:
Japan
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Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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Tel: +81-3-5322-3347
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The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
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any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
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CAUTION:
Europe
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
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Am Siebenstein 6-10,
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New Tech Park,
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
Singapore 556741
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If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
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Tel: +82-2-3484-7100
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F0011
FUJITSU LIMITED Printed in Japan
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