MB90T552A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13706-2E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90550A/550B Series

MB90552A/552B/553A/553B/T552A/T553A

MB90F553A/P553A

■ DESCRIPTION

The MB90550A/550B series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for

applications which require high-speed real-time processing, such as industrial machines, OA equipment, and

process control systems.

While inheriting the AT architecture of the F²MC*-8 family, the instruction set for the MB90550A/550B series

incorporates additional instructions for high-level languages, supports extended addressing modes, and contains

enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation

instructions. In addition, the MB90550A/550B has an on-chip 32-bit accumulator which enables processing of

long-word data.

MB90552B and MB90553B are radiation noise decreased type. There are no change in the functional specifica-

tion.

*: F²MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

■ FEATURES

• Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, × four times the PLL clock)

• Maximum memory space: 16 Mbytes

• Instruction set optimized for controller applications

Supported data types: Bit, byte, word and long word

Typical addressing mode: 23 types

Enhanced precision calculation realized by 32-bit accumulator

Enhanced signed multiplication/division instruction and RETI instruction functions

(Continued)

■ PACKAGES

100-pin plastic QFP

100-pin plastic LQFP

(FPT-100P-M06)

(FPT-100P-M05)

MB90550A/550B Series

(Continued)

• Instruction set designed for high level language (C) and multi-task operations

Adoption of system stack pointer

Symmetrical instruction set and barrel shift instructions

• Integrated address match detection function (for two address pointers)

• Faster execution speed: 4-byte queue

• Powerful interrupt functions (Eight priority levels programmable)

External interrupt inputs: 8 channels

• Data transfer functions (Intelligent I/O service): Up to 16 channels

DTP request inputs: 8 channels

• Embedded ROM size (EPROM, Flash: 128 Kbytes)

Mask ROM: 64 Kbytes/128 Kbytes

• Embedded RAM size (EPROM, Flash: 4 Kbytes)

Mask ROM: 2 Kbytes/4 Kbytes

• General-purpose ports: Up to 83 channels

(Input pull-up resistor settable for: 16 channels; Open drain settable for: 8 channels; I/O open drains: 6 chan-

nels)

• A/D converter (RC successive approximation type): 8 channels

(Resolution: 8 or 10 bits selectable; Conversion time of 26.3 µs minimum)

• UART: 1 channel

• Extended I/O serial interface: 2 channels

• I²C interface: 2 channels

(Two channels, including one switchable between terminal input and output)

• 16-bit reload timer: 2 channels

• 8/16-bit PPG timer: 3 channels

(8 bits × 2 channels; 16 bits x 1 channel: Mode switching function provided)

• 16-bit I/O timer

(Input capture × 4 channels, output compare × 4 channels, free run timer ×1 channel)

• Clock monitor function integrated (Delivering the oscillation clock divided by 21 to 28)

• Timebase timer/watchdog timer: 18 bits

• Low power consumption modes (sleep, stop, hardware standby, and CPU intermittent operation modes)

• Package: QFP-100, LQFP-100

• CMOS technology

2

MB90550A/550B Series

■ PRODUCT LINEUP

Part number

MB90552A MB90553A

MB90552B MB90553B

MB90F553A MB90P553A MB90T552A MB90T553A MB90V550A

Item

Flash ROM

Mask ROM products

OTP

External ROM products

Evaluation

product

products

Mass Product

128 Kbytes

4 Kbytes

Classification

ROM size

RAM size

64 Kbytes

2 Kbytes

None

2 Kbytes

4 Kbytes

6 Kbytes

The number of instructions: 340

Instruction bit length: 8 bits, 16 bits

Instruction length: 1 byte to 7 bytes

Data bit length: 1 bit, 8 bits, 16 bits

CPU functions

Minimum execution time: 62.5 ns (at machine clock of 16 MHz)

Interrupt processing time: 1.5 ms (at machine clock of 16 MHz, minimum value)

General-purpose I/O ports (CMOS output): 53

General-purpose I/O ports (with pull-up resistor): 16

General-purpose I/O ports (N-channel open-drain output): 6

General-purpose I/O ports (N-channel open-drain function selectable): 8

Total: 83

Ports

Clock synchronized transmission (62.5 Kbps to 2 Mbps)

Clock asynchronized transmission (62500 bps to 9615 bps)

Transmission can be performed by bi-directional serial transmission or by

master/slave connection.

UART (SCI)

Conversion precision: 8/10-bit can be selectively used.

Number of inputs: 8

One-shot conversion mode (converts selected channel only once)

Scan conversion mode (converts two or more successive channels and can program up to

8 channels.)

8/10-bit A/D

converter

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

Number of channels: 1 (8-bit × 2 channels)

PPG operation of 8-bit or 16-bit

A pulse wave of given intervals and given duty ratios can be output.

Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz)

8/16-bit PPG timer

Number of channels: 1

Overflow interrupts

16-bit

free run timer

16-bit

Number of channels: 4

Pin input factor: A match signal of compare register

Output com-

I/O

pare (OCU)

timer

Number of channels: 4

Input capture

(ICU)

Rewriting a register value upon a pin input (rising, falling or both edges)

(Continued)

3

MB90550A/550B Series

(Continued)

Part number

MB90552A MB90553A

MB90552B MB90553B

MB90F553A MB90P553A MB90T552A MB90T553A MB90V550A

Item

Number of inputs: 8

DTP/external

interrupt circuit

Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.

External interrupt circuit or extended intelligent I/O service (EI²OS) can be used.

Extended I/O serial

interface

Clock synchronized transmission (3125 bps to 1 Mbps)

LSB first/MSB first

I²C interface

Serial I/O port for supporting Inter IC BUS

18-bit counter

Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms

(at oscillation of 4 MHz)

Timebase timer

Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms

(at oscillation of 4 MHz, minimum value)

Watchdog timer

Process

CMOS

Power supply volt-

age for operation*

4.5 V to 5.5 V

*:Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS”)

Assurance for the MB90V550A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an

operating temperature of 0°C to +25°C, and an operating frequency of 1 MHz to 16 MHz.

■ PACKAGE AND CORRESPONDING PRODUCTS

MB90552A

MB90552B

MB90553A

MB90553B

Package

FPT-100P-M05

MB90F553A

MB90P553A

×

FPT-100P-M06

: Available ×: Not available

Note:For more information about each package, see section “■ PACKAGE DIMENSIONS”

■ DIFFERENCES AMONG PRODUCTS

Memory Size

In evaluation with an evaluation product, note the difference between the evaluation product and the product

actually used. The following items must be taken into consideration.

• The MB90V550A does not have an internal ROM. However, operations equivalent to those performed by a

chip with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM

size by setting the development tool.

• In the MB90V550A, images from FF4000^Hto FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH

are mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.)

• In the MB90F553A/553A/553B/552A/552B, images from FF4000^Hto FFFFFFH are mapped to bank 00, and

FF0000H to FF3FFFH to bank FF only.

4

MB90550A/550B Series

■ PIN ASSIGNMENTS

• FPT-100P-M06

(Top View)

80

79

78

77 RST

76

75

74

73

72

71

1

2

3

4

5

6

7

8

9

P20/A16

P21/A17

P22/A18

P23/A19

P24/A20

P25/A21

P26/A22

P27/A23

P30/ALE

P31/RD

V^SS

PA4/CKOT

PA3

PA2

PA1/OUT3

PA0/OUT2

P97/PPG5

P96/PPG4

P95/PPG3

P94/PPG2

10

11

12

70 P93/PPG1

69 P92/PPG0

P32/WRL

68

67

66

P33/WRH 13

P91/OUT1

P92/OUT0

P87/IN3

14

P34/HRQ

P35/HAK 15

P36/RDY 16

P37/CLK 17

P40/SCK 18

65 P86/IN2

64 P85/IN1

63 P84/IN0

62 P83/TOT1

19

P41/SOT

61

P42/SIN 20

P43/SCK1 21

P44/SOT1 22

P82/TOT0

60 P81/TIN1

59

P80/TIN0

58 P77/IRQ7

V^CC

23

P45/SIN1 24

P46/ADTG

57

56

55

54

53

52

51

P76/IRQ6

P75/IRQ5

P74/IRQ4

P73/IRQ3

P72/IRQ2

HST

25

P47/SCK0 26

C

27

28

P50/SDA0/SOT0

P51/SCL0/SIN0 29

P52/SDA1 30

MD2

(FPT-100P-M06)

5

MB90550A/550B Series

• FPT-100P-M05

(Top view)

P22/A18

P23/A19

P24/A20

P25/A21

P26/A22

P27/A23

1

2

3

4

5

75

RST

74 PA1/OUT3

73

72

71

70

PA0/OUT2

P97/PPG5

P96/PPG4

P95/PPG3

6

7

8

9

69 P94/PPG2

P30/ALE

P31/RD

V^SS

68

67

P93/PPG1

P92/PPG0

P32/WRL

P33/WRH 11

P34/HRQ 12

10

66 P91/OUT1

65

P90/OUT0

64 P87/IN3

P35/HAK

P36/RDY

P37/CLK

P40/SCK 16

P41/SOT

13

14

15

63

62

61

60

59

P86/IN2

P85/IN1

P84/IN0

P83/TOT1

P82/TOT0

17

P42/SIN 18

P43/SCK1 19

58 P81/TIN1

57

P80/TIN0

P44/SOT1

V^CC

P45/SIN1

20

21

22

56 P77/IRQ7

55 P76/IRQ6

54 P75/IRQ5

53 P74/IRQ4

52 P73/IRQ3

P46/ADTG 23

P47/SCK0 24

25

51

C

P72/IRQ2

(FPT-100P-M05)

6

MB90550A/550B Series

■ PIN DESCRIPTION

Pin no.

Pin name

Circuit type

Function

QFP

82

LQFP

80

X0

X1

A

B

C

Oscillation pin

83

81

Oscillation pin

77

75

RST

HST

Reset input pin

52

50

Hardware standby input pin

General-purpose I/O ports.

A pull-up resistor can be added (RD07 to RD00 = 1) by using

the pull-up resistor setting register (RDR0).

D07 to D00 = 1: Disabled when the port is set for output.

P00 to P07

D

85 to 92 83 to 90

(CMOS)

AD00 to

AD07

Serve as lower data I/O/lower address output (AD00 to AD07)

pins in the external bus mode.

General-purpose I/O ports.

A pull-up resistor can be added (RD17 to RD10 = 1) by using the

pull-up resistor setting register (RDR1).

D17 to D10 = 1: Disabled when the port is set for output.

P10 to P17

93 to

D

91 to 98

100

(CMOS)

AD08 to

AD15

Serve as upper data I/O/middle address output (AD08 to AD15)

pins in the 16-bit bus-width, external bus mode.

General-purpose I/O ports.

P20 to P27

A16 to A23

This function is enabled either in single-chip mode or with the

external address output control register set to “Port”.

99,100,

1 to 8

E

1 to 6

(CMOS)

External address bus A16 to A23 output pins.

This function is enabled in an external-bus enabled mode with

the external address output register set to “Address”.

General-purpose I/O port.

This function is enabled in single-chip mode.

P30

ALE

P31

RD

E

9

7

8

(CMOS)

Address latch enable output pin.

This function is enabled in an external-bus enabled mode.

General-purpose I/O port.

This function is enabled in single-chip mode.

E

10

12

13

(CMOS)

Read strobe output pin for the data bus.

This function is enabled in an external-bus enabled mode.

General-purpose I/O port.

This function is enabled in single-chip mode.

P32

WRL

P33

WRH

E

10

11

(CMOS)

Write strobe output pin for the lower eight bits of the data bus.

This function is enabled in an external-bus enabled mode.

General-purpose I/O port.

This function is enabled in single-chip mode.

E

(CMOS)

Write strobe output pin for the upper eight bits of the data bus.

This function is enabled in an external-bus enabled mode.

(Continued)

7

MB90550A/550B Series

Pin no.

Pin name Circuit type

QFP LQFP

Function

General-purpose I/O port.

This function is enabled in single-chip mode

P34

HRQ

P35

E

14

15

16

17

12

13

14

15

(CMOS)

Hold request input pin.

This function is enabled in an external-bus enabled mode.

General-purpose I/O port.

This function is enabled in single-chip mode.

E

(CMOS)

Hold acknowledge output pin.

This function is enabled in an external-bus enabled mode.

HAK

P36

General-purpose I/O port.

This function is enabled in single-chip mode.

E

(CMOS)

Ready signal input pin.

This function is enabled in an external-bus enabled mode.

RDY

P37

General-purpose I/O port.

This function is enabled in single-chip mode.

E

(CMOS)

CLK output pin.

This function is enabled in an external-bus enabled mode.

CLK

General-purpose I/O port.

Serves as an open-drain output port (OD40 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D40 = 0: Disabled when the port is set for input.)

P40

SCK

P41

SOT

P42

F

18

19

16

17

(CMOS/H)

UART serial clock I/O pin.

This function is enabled with the UART clock output enabled.

General-purpose I/O port.

Serves as an open-drain output port (OD41 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D41 = 0: Disabled when the port is set for input.)

F

(CMOS/H)

UART serial data output pin.

This function is enabled with the UART serial data output enabled.

General-purpose I/O port.

Serves as an open-drain output port (OD42 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D42 = 0: Disabled when the port is set for input.)

F

20

21

18

19

(CMOS/H)

UART serial data input pin. Since this input is used as required while

the UART is operating for input, the output by any other function

must be off unless used intentionally.

SIN

General-purpose I/O port.

Serves as an open-drain output port (OD43 = 1) depending on the

setting of the open-drain control setting register (ODR4).

(D43 = 0: Disabled when the port is set for input.)

P43

F

(CMOS/H)

Extended I/O serial clock I/O pin. This function is enabled with the

extended I/O serial clock output enabled.

SCK1

(Continued)

8

MB90550A/550B Series

Pin no.

Pin name Circuit type

Function

QFP

LQFP

General-purpose I/O port.

Serves as an open-drain output port (OD44 = 1) depending on

the setting of the open-drain control setting register (ODR4).

(D44 = 0: Disabled when the port is set for input.)

P44

F

22

24

20

(CMOS/H)

Extended I/O serial data output pin.

This function is enabled with the extended I/O serial data output

enabled.

SOT1

P45

General-purpose I/O port.

Serves as an open-drain output port (OD45 = 1) depending on

the setting of the open-drain control setting register (ODR4).

(D45 = 0: Disabled when the port is set for input.)

F

22

(CMOS/H)

Extended I/O serial data input pin.

Since this input is used as required while the extended I/O serial

interface is operating for input, the output by any other function

must be off unless used intentionally.

SIN1

P46

General-purpose I/O port.

Serves as an open-drain output port (OD46 = 1) depending on

the setting of the open-drain control setting register (ODR4).

(D46 = 0: Disabled when the port is set for input.)

F

25

23

(CMOS/H)

A/D converter external trigger input pin.

Since this input is used as required while the A/D converter is op-

erating for input, the output by any other function must be off un-

less used intentionally.

ADTG

General-purpose I/O port.

Serves as an open-drain output port (OD47 = 1) depending on

the setting of the open-drain control setting register (ODR4).

D47 = 0: Disabled when the port is set for input.

P47

F

26

27

24

25

(CMOS/H)

SCK0

Extended I/O serial clock I/O pin. This function is enabled with

the extended I/O serial clock output enabled.

Capacitance pin for regulating the power supply.

Connect an external ceramic capacitor of about 0.1 µF.

C

—

P50

N-channel open-drain I/O port.

I²C interface data I/O pin.

This function is enabled with the I²C interface enabled for

operation.

SDA0

SOT0

G

28

26

While the I²C interface is operating, place the port output in the

Hi-Z state (PDR = 1).

(NchOD/H)

Extended I/O serial data output pin.

This function is enabled with the extended I/O serial data output

enabled.

(Continued)

9

MB90550A/550B Series

Pin no.

Pin name

Circuit type

Function

N-channel open-drain I/O port.

QFP

LQFP

P51

I²C interface clock I/O pin. This function is enabled with the

I²C interface enabled for operation.

SCL0

SIN0

While the I²C interface is operating, place the port output in

the Hi-Z state (PDR = 1).

G

29

27

(NchOD/H)

Extended I/O serial data input pin.

Since this input is used as required while the extended I/O

serial interface is operating for input, the output by any other

function must be off unless used intentionally.

P52,P54

SDA1,SDA2

P53,P55

N-channel open-drain I/O ports.

I²C interface data I/O pins. This function is enabled with the

I²C interface enabled for operation.

G

30,32

31,33

28,30

29,31

(NchOD/H)

While the I²C interface is operating, place the port output in

the Hi-Z state (PDR = 1).

N-channel open-drain I/O ports.

I²C interface clock I/O pins. This function is enabled with the

I²C interface enabled for operation.

G

(NchOD/H)

SCL1,SCL2

While the I²C interface is operating, place the port output in

the Hi-Z state (PDR = 1).

P60 to P67

AN0 to AN7

P70 to P77

General-purpose I/O ports.

38 to 41, 36 to 39,

43 to 46 41 to 44

H

A/D converter analog input pin. This function is enabled with

the analog input enabled.

(CMOS/H)

General-purpose I/O ports.

External interrupt request input pins.

47,48,

I

45,46,

Since this input is used as required while external interrupts

remain enabled, the output by any other function must be off

unless used intentionally.

51 to 56

53 to 58

(CMOS/H)

IRQ0 to IRQ7

P80,P81

General-purpose I/O ports.

Reload timer event input pins.

J

59,60

61,62

57,58

59,60

Since this input is used as required while the reload timer is

operating for input, the output by any other function must be

off unless used intentionally.

(CMOS/H)

TIN0,TIN1

P82,P83

TOT0,TOT1

P84 to P87

General-purpose I/O ports.

J

Reload timer output pins.This function is enabled with reroad

timer output enabled.

(CMOS/H)

General-purpose I/O ports.

Input capture trigger input pins.

J

63 to 66 61 to 64

Since this input is used as required while the input capture

unit is operating for input, the output by any other function

must be off unless used intentionally.

(CMOS/H)

IN0 to IN3

P90,P91

General-purpose I/O ports.

Output compare event output pins.

(Continued)

J

67,68

65,66

(CMOS/H)

OUT0,OUT1

10

MB90550A/550B Series

(Continued)

Pin no.

Pin name

Circuit type

Function

QFP

LQFP

P92 to P97

General-purpose I/O ports.

J

69 to 74 67 to 72

PPG0 to

PPG5

PPG output pins. This function is enabled with the PPG output

enabled.

(CMOS/H)

PA0,PA1

General-purpose I/O ports.

J

75,76

78,79

80

73,74

76,77

78

(CMOS/H)

OUT2,OUT3

Output compare event output pins.

J

PA2,PA3

General-purpose I/O ports.

(CMOS/H)

PA4

CKOT

AV^CC

General-purpose I/O port.

J

(CMOS/H)

Serves as the CKOT output while the CKOT is operating.

A/D converter power-supply pin.

34

35

36

37

32

33

34

35

AVRH

AVRL

AV^SS

A/D converter external reference voltage source pin.

A/D converter power-supply pin.

Operation mode setting input pins.

Connect these pins directly to Vcc or Vss.

49,50

47,48

MD0,MD1

C

K

C

Operation mode setting input pin.

Connect this pin directly to Vcc or Vss. (MB90552A/552B/553A/

553B/V550A)

51

49

MD2

Operation mode setting input pin.

Connect this pin directly to Vcc or Vss. (MB90P553A/F553A)

23,84

21,82

V^CC

V^SS

Power (5 V) input pins.

11,42,

81

9,40,

79

Power (0 V) input pins.

11

MB90550A/550B Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• 3 MHz to 32 MHz

Clock input

• Oscillator recovery resistor approx. 1MΩ

X1

X0

A

HARD,SOFT

STANDBY

CONTROL

• CMOS level hysteresis input

• Pull-up resistor provided

Resistor: About 50 kΩ

B

C

• CMOS level hysteresis input

• CMOS level output

• CMOS level input

• Standby control provided

• Input pull-up resistor control provided

Resistor: About 50 kΩ

Pull-up resistor control

Digital output

Digital input

D

HARD,SOFT

STANDBY

CONTROL

(Continued)

12

MB90550A/550B Series

Type

Circuit

Remarks

• CMOS level output

• CMOS level input

• Standby control provided

Digital output

E

Digital input

HARD,SOFT

STANDBY

CONTROL

• CMOS level output

• CMOS level hysteresis input

• Open-drain control provided

Open- drain

control

signal

Digital input

F

Digital input

HARD,SOFT

STANDBY

CONTROL

• N-channel open-drain output

• CMOS level hysteresis input

• Standby control provided

Digital output

Digital input

Note: Unlike normal CMOS I/O pins, this

pin is not provided with any P-channel

transistor. Therefore the pin does not allow

a current to flow to the Vcc side even when

applied with a voltage from an external

device with the IC’s power supply left off.

G

HARD,SOFT

STANDBY

CONTROL

• CMOS level output

• CMOS level hysteresis input

• Standby control provided

• Analog input

Digital output

H

Analog input

Digital input

HARD,SOFT

STANDBY

CONTROL

A/D

DISABLE

(Continued)

13

MB90550A/550B Series

(Continued)

Type

Circuit

Remarks

• CMOS level output

• CMOS level hysteresis input

• Standby control provided

Digital output

I

Digital input

HARD

STANDBY

CONTROL

• CMOS level output

• CMOS level hysteresis input

• Standby control provided

Digital output

J

Digital input

HARD,SOFT

STANDBY

CONTROL

• CMOS level hysteresis input

• Pull-up resistor provided

Resistor: About 50 kΩ

K

14

MB90550A/550B Series

■ HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may cause latchup in the following situations:

• When a voltage higher than Vcc or lower than Vss is applied to input or output pins.

• When a voltage exceeding the rating is applied between Vcc and Vss.

• When AVcc power is supplied prior to the Vcc voltage.

If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the

device. Use meticulous care not to let it occur.

For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply

voltage.

2. Handling unused input pins

Leaving unused input pins open may cause a malfunction or latch-up which leads to fatal damage to the device.

Therefore they must be pulled up or pulled down through at least 2 kΩ resistance. Also, unused input/output

pins should be left open in output state or handled in the same way as unused input pins.

3. Notes on Using External Clock

In using the external clock, drive X0 pin only and leave X1 pin unconnected.

• Using external clock

MB90550A/550B series

X0

X1

Open

4. Power Supply Pins (V^CC/V^SS)

In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to

avoid abnormal operations including latch-up. However, the pins should be connected to external power and

ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by

the rise in the ground level, and to conform to the total current rating.

Make sure to connect VCC and VSS pins via lowest impedance to power lines.

It is recommended that a bypass capacitor of around 0.1 µF be placed between the VCC and VSS pins near the

device.

• Using power supply pins

V

CC

SS

V

CC

V

SS

V

SS

CC

MB90550A/550B

series

V

CC

SS

V

CC

V

SS

15

MB90550A/550B Series

5. Crystal Oscillator Circuit

Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via

shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure

that lines of oscillation circuit not cross the lines of other circuits.

A printed circuit board artwork surrounding the X0 and X1 pins with grand area for stabilizing the operation is

highly recommended.

6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL) and

analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage does not exceed AVRH or AV^CC(turning on/off the analog and digital power supplies simulta-

neously is acceptable).

7. Connection of Unused Pins of A/D Converter

Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.

8. N.C. Pin

The N.C. (internally connected) pin must be opened for use.

9. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

µs or more.

10. Indeterminate outputs from ports 0 and 1

The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during

a power-on reset) after the power is turned on. (MB90552A, MB90552B, MB90553A, MB90553B, MB90F553A,

MB90V550A)

The series without built-in step-down circuit has no oscillation setting time of step-down circuit, so outputs should

not become indeterminate. (MB90P553A)

Timing chart of indeterminate outputs from ports 0 and 1

Oscillation setting time *²

Step-down circuit setting time *¹

VCC (power-supply pin)

PONR (power-on reset) signal

RST (external asynchronous reset) signal

RST (internal reset) signal

Oscillation clock signal

KA (internal operating clock A) signal

KB (internal operating clock B) signal

Period of indeterminate

PORT (port output) signal

*1: Step-down circuit setting time 2¹⁷/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms)

*2: Oscillation setting time

2¹⁸/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)

16

MB90550A/550B Series

11. Initialization

In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers

turning on the power again.

12. Return from standby state

If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may

fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal

state.

13. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions

The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corre-

sponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB,

ADB, USB, SSB) are set to a value other than ’00h,’ the remainder obtained after the execution of the instruction

will not be placed in the instruction operand register.

14. Using of REALOS

The use of EI²OS is not possible the REALOS real time operating system.

17

MB90550A/550B Series

■ BLOCK DIAGRAM

X0, X1

CPU

Core of F²MC-16LX

family

Clock control

circuit*

4

RST

HST

Interrupt controller

Port A

RAM

ROM

F

M

C

Clock monitor function

Port 0

CKOT/PA4

PA2, A3

P00 to P07/

AD00 to AD07

Port 1

Port 2

Port 3

P10 to P17/

AD08 to AD15

OUT2, OUT3/

PA0, A1

16

L

X

B

U

S

P20 to P27/

A16 to A23

Port 9

PPG5/P97

PPG4/P96

PPG3/P95

PPG2/P94

PPG1/P93

PPG0/P92

P30/ALE

P31/RD

8/16 PPG × 3c h

P32/WRL

P33/WRH

P34/HRQ

P35/HAK

P36/RDY

I/O timer

16-bit output compare

unit x 4 channels

OUT0, OUT1/

P90, P91

16-bit input capture

unit x 4 channels

P37/CLK

IN0 to IN3/

P84 to P87

16-bit free-run timer

Port 4

TOT0, TOT1/

P82, P83

TIN0, TIN1/

P80, P81

Communication prescaler

16-bitreloadtimer

x 2 channels

P40/SCK

P41/SOT

UART

Port 8

P42/SIN

Port 7

P43/SCK1

P44/SOT1

P45/SIN1

P46/ADTG

Extended I/O

serial interface 1

External interrupt

IRQ0 to IRQ7/

P70 to P77

AV^CC

P47/SCK0

A/D converter

(8/10 bits)

AVRH, AVRL

AV^SS

Extended I/O

serial interface 0

P50/SDA0/SOT0

P51/SCL0/SIN0

AN0 to AN7/

P60 to P67

I²C interface 0

Port 6

P52/SDA1

P53/SCL1

P54/SDA2

P55/SCL2

*: Specifications of evaluation model

(MB90V550A)

Contains no internal ROM.

I²C interface 1

Port 5

Contains 6 KB of internal RAM.

Contains the same internal resources as the

other products in the MB90550A/550B series.

18

MB90550A/550B Series

Note: The clock control circuit contains a watchdog timer, time-base timer, and a low power consumption control

circuit.

P00 to P07 (8 pins): Input pull-up resistor setting register provided

P10 to P17 (8 pins): Input pull-up resistor setting register provided

P40 to P47 (8 pins): Open-drain control setting register provided

P50 to P55 (6 pins): N-channel open drain

Ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and A are CMOS level input/output ports.

19

MB90550A/550B Series

■ MEMORY MAP

The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler

small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address,

enabling reference of the table on the ROM without stating “far”.

Forexample, ifanattempthasbeenmadetoaccess00C000^H, thecontentsoftheROMatFFC000H areaccessed.

Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the

00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH.

Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.

Internal ROM

Single chip mode

A mirror function

is supported

external bus mode

A mirror function

is supported

External ROM

external bus mode

FFFFFFH

ROM

area

ROM

area

Address#1

FF0000H

010000H

ROM area

(image of

bank FF)

ROM area

(image of

bank FF)

Address#2

: Internal access memory

: External access memory

: Inhibited area

004000^H

002000H

Address#3

Registor

RAM

000100H

0000C0H

0000D0H

Peripheral

Parts No.

Address#1

Address#2

Address#3

MB90552A/552B

MB90553A/553B

MB90F553A

FF0000H

FE0000H

(FE0000H)

004000H

000900H

001100H

001900H

MB90P553A

MB90V550A

20

MB90550A/550B Series

■ F²MC-16LX CPU PROGRAMMING MODEL

• Dedicated registers

: Accumulator (A)

AH

AL

Dual 16-bit register used for storing results of calculation, etc. The two 16-bit

registers can be combined and used as a 32-bit register.

: User stack pointer (USP)

The 16-bit pointer indicating a user stack address.

USP

SSP

: System stack pointer (SSP)

The 16-bit pointer indicating the status of the system stack address.

: Processor status (PS)

The 16-bit register indicating the system status.

PS

PC

: Program counter (PC)

The 16-bit register indicating storing location of the current instruction code.

: Direct page register (DPR)

The 8-bit register indicating bits 8 through 15 of the operand address in the short

direct addressing mode.

DPR

: Program bank register (PCB)

The 8-bit register indicating the program space.

PCB

DTB

USB

SSB

: Data bank register (DTB)

The 8-bit register indicating the data space.

: User stack bank register (USB)

The 8-bit register indicating the user stack space.

: System stack bank register (SSB)

The 8-bit register indicating the system stack space.

: Additional data bank register (ADB)

The 8-bit register indicating the additional data space.

ADB

8 bit

16 bit

32 bit

21

MB90550A/550B Series

■ I/O MAP

Abbreviated

Address

Register name

Port 0 data register

Read/write Resource name

Initial value

register name

00^H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

XXXXXXXX

_ _ 1 1 1 1 1 1

XXXXXXXX

_ _ _XXXXX

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

0BH to

0FH

(Disabled)

0 0 0 0 0 0 0 0

10^H

11H

12H

13H

14H

15H

16^H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

DDR0

DDR1

DDR2

DDR3

DDR4

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

(Disabled)

0 0 0 0 0 0 0 0

_ _ _ 0 0 0 0 0

0 0 0 0 0 0 0 0

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

Port 4 output pin register

Port 0 resistor setting register

Port 1 resistor setting register

DDR6

DDR7

DDR8

DDR9

DDRA

ODR4

RDR0

RDR1

R/W

Port 6

Port 7

Port 8

Port 9

Port A

Port 4

Port 0

Port 1

(Disabled)

Port 6,

A/D converter

Analog input enable register

ADER

R/W

1 1 1 1 1 1 1 1

1F^H

20H

21H

Serial mode register

Serial control register

SMR

SCR

R/W

0 0 0 0 0 0 0 0

0 0 0 0 0 10 0

UART

Serial input data register /

serial output data register

XXXXXXXX

22H

23H

SIDR/SODR

SSR

R/W

0 0 0 0 1 _ 0 0

(Continued)

Serial status register

22

MB90550A/550B Series

Abbreviated

register name

Address

Register name

Read/write Resource name

Initial value

Serial mode control status

register 0

_ _ _ _ 0 0 0 0

24^H

R/W

SMCS0

Extended I/O

Serial mode control status

register 0

0 0 0 0 0 0 1 0

XXXXXXXX

25H

26H

27H

R/W!

R/W

serial interface 0

Serial data register 0

SDR0

CDCR

Clock frequency-divider control

register

Communication

prescaler

0 _ _ _ 1 1 1 1

Serial mode control status

register 1

_ _ _ _ 0 0 0 0

28H

29H

R/W

SMCS1

SDR1

Extended I/O

serial interface 1

Serial mode control status

register 1

0 0 0 0 0 0 1 0

XXXXXXXX

R/W!

R/W

2AH

2BH

2C^H

2DH

2EH

2FH

30H

31H

32^H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

Serial data register 1

(Disabled)

I²C bus status register 0

I²C bus control register 0

IBSR0

IBCR0

ICCR0

IADR0

IDAR0

R

0 0 0 0 0 0 0 0

_ _ 0XXXXX

_ XXXXXXX

XXXXXXXX

R/W

2

I C bus clock select register 0

I C interface 0

I²C bus address register 0

I²C bus data register 0

(Disabled)

I²C bus status register 1

I²C bus control register 1

IBSR1

IBCR1

ICCR1

IADR1

IDAR1

ISEL

R

0 0 0 0 0 0 0 0

_ _ 0XXXXX

_ XXXXXXX

XXXXXXXX

R/W

2

I C bus clock select register 1

2

I C interface 1

I²C bus address register 1

I²C bus data register 1

2

_ _ _ _ _ _ _ 0

0 0 0 0 0 0 0 0

XXXXXXXX

I C bus port select register

Interrupt/DTP enable register

Interrupt/DTP factor register

ENIR

EIRR

DTP/external

interrupt

0 0 0 0 0 0 0 0

XXXXXXXX

Request level setting register

Control status register

Data register

ELVR

R/W

ADCS0

ADCS1

ADCR0

ADCR1

R/W

R/W!

R

A/D convertor

R/W!

0 0 0 0 1 _XX

(Continued)

23

MB90550A/550B Series

Abbreviated

register name

Address

Register name

Read/write Resource name

Initial value

XXXXXXXX

40^H

41H

42H

43H

Reload register L (ch.0)

Reload register H (ch.0)

Reload register L (ch.1)

Reload register H (ch.1)

PRLL0

PRLH0

PRLL1

PRLH1

R/W

PPG0 operating mode control

register

8/16-bit PPG0/1

R/W

0 _ 0 0 0 _ _ 1

0 _ 0 0 0 0 0 1

0 0 0 0 0 0 0 0

44H

45H

46H

PPGC0

PPGC1

PPGE1

PPG1 operating mode control

register

R/W

PPG0 and 1 output control

register

(Disabled)

47H

48^H

49H

4AH

4BH

Reload register L (ch.2)

Reload register H (ch.2)

Reload register L (ch.3)

Reload register H (ch.3)

PRLL2

PRLH2

PRLL3

PRLH3

R/W

XXXXXXXX

PPG2 operating mode control

register

8/16-bit PPG2/3

R/W

0 _ 0 0 0 _ _ 1

0 _ 0 0 0 0 0 1

0 0 0 0 0 0 0 0

4CH

4DH

4EH

PPGC2

PPGC3

PPGE2

PPG3 operating mode control

register

R/W

PPG2 and 3 output control

register

4FH

50^H

51H

52H

53H

(Disabled)

XXXXXXXX

Reload register L (ch.4)

Reload register H (ch.4)

Reload register L (ch.5)

Reload register H (ch.5)

PRLL4

PRLH4

PRLL5

PRLH5

R/W

PPG4 operating mode control

register

8/16-bit PPG4/5

0 _ 0 0 0 _ _ 1

0 _ 0 0 0 0 0 1

0 0 0 0 0 0 0 0

54H

55H

PPGC4

PPGC5

PPGE3

R/W

PPG5 operating mode control

register

PPG4 and 5 output control

register

56H

57H

58^H

59H

(Disabled)

Clock monitor

function

_ _ _ _ 0 0 0 0

(Continued)

Clock output enable register

CLKR

R/W

(Disabled)

24

MB90550A/550B Series

Abbreviated

register name

Address

Register name

Read/write Resource name

Initial value

0 0 0 0 0 0 0 0

_ _ _ _ 0 0 0 0

XXXXXXXX

0 0 0 0 0 0 0 0

_ _ _ _ 0 0 0 0

XXXXXXXX

5A^H

5BH

5CH

5DH

5EH

5FH

60H

61H

Control status register 0

TMCSR0

R/W

16-bit

reload timer 0

R/W

16 bit timer register 0/

16 bit reload register 0

TMR0/

TMRLR0

Control status register 1

TMCSR1

R/W

16-bit

reload timer 1

R/W

16 bit timer register 1/

16 bit reload register 1

TMR1/

TMRLR1

Input capture register,

channel-0 lower bits

62H

63H

64H

65H

66H

67H

68H

69H

6AH

6BH

XXXXXXXX

0 0 0 0 0 0 0 0

IPCP0

IPCP1

IPCP2

IPCP3

R

Input capture register,

channel-0 upper bits

Input capture register,

channel-1 lower bits

R

Input capture register,

channel-1 upper bits

Input capture register,

channel-2 lower bits

16-bit

I/O timer

Input capture

(ch.0 to ch.3)

R

Input capture register,

channel-2 upper bits

Input capture register,

channel-3 lower bits

R

Input capture register,

channel-3 upper bits

Input capture control

status register

ICS01

ICS23

R/W

Input capture control

status register

6CH

6DH

6EH

Timer data register, lower bits

Timer data register, upper bits

Timer control status register

R/W

0 0 0 0 0 0 0 0

16-bit

I/O timer

free run timer

TCDT

R/W

TCCS

ROM mirroring

function

ROM mirroring function

selection register

6FH

ROMM

W

_ _ _ _ _ _ _ 1

(Continued)

25

MB90550A/550B Series

Abbreviated

Address

Register name

Compare register,

Read/write Resource name

Initial value

register name

XXXXXXXX

70^H

channel-0 lower bits

OCCP0

OCCP1

OCCP2

OCCP3

R/W

Compare register,

channel-0 upper bits

XXXXXXXX

71H

72H

73H

74H

75H

76H

Compare register,

channel-1 lower bits

R/W

Compare register,

channel-1 upper bits

Compare register,

channel-2 lower bits

R/W

16-bit

Compare register,

channel-2 upper bits

I/O timer

output compare

(ch.0 to ch.3)

Compare register,

channel-3 lower bits

R/W

Compare register,

XXXXXXXX

0 0 0 0 _ _ 0 0

_ _ _ 0 0 0 0 0

0 0 0 0 _ _ 0 0

_ _ _ 0 0 0 0 0

77H

78H

79H

7AH

7BH

channel-3 upper bits

Compare control status

register, channel-0

OCS0

OCS1

OCS2

OCS3

R/W

Compare control status

register, channel-1

Compare control status

register, channel-2

Compare control status

register, channel-3

7CH to

9DH

(Disabled)

Address match

Program address detection

control register

9E^H

9FH

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0

_ _ _ _ _ _ _ 0

detection function

Delayed

interrupt

Delayed interrupt factor

generation/cancellation register

Low-power consumption mode

control register

Low power

consumptioncontrol

circuit

0 0 0 1 1 0 0 0

1 1 1 1 1 1 0 0

A0H

A1H

LPMCR

CKSCR

R/W!

Clock select register

A2H to

A4H

(Disabled)

Automatic ready function select

register

A5^H

A6H

A7H

ARSR

HACR

ECSR

W

0 0 1 1 _ _ 0 0

0 0 0 0 0 0 0 0

External bus pin

control circuit

External address output

control register

Bus control signal select

register

0 0 0 0 0 0 0 _

(Continued)

26

MB90550A/550B Series

Abbreviated

register name

Address

Register name

Read/write Resource name

Initial value

Watchdog timer control register

Timebase timer control register

XXXXX 1 1 1

1 _ _ 0 0 1 0 0

A8^H

A9H

WDTC

TBTC

R/W!

Watchdog timer

Timebase timer

AAH to

ADH

(Disabled)

Flash memory

interface circuit

Flash memory control status

register

0 0 0 0 0 _ _ 0

AE^H

FMCS

R/W

(Disabled)

AFH

B0^H

B1H

B2H

B3H

B4H

B5H

B6H

B7H

B8H

B9H

BAH

BBH

BCH

BDH

BEH

BFH

0 0 0 0 0 1 1 1

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

R/W!

Interrupt controller

C0H to

FF^H

(External area)

100H to

#H

(RAM area)

#^Hto

(Reserved area)

1FEF^H

(Continued)

27

MB90550A/550B Series

(Continued)

Abbreviated

Address

1FF0^H

1FF1H

1FF2H

1FF3H

1FF4H

1FF5H

Register name

Read/write Resource name

Initial value

XXXXXXXX

register name

Program address detection

register 0

R/W

Program address detection

register 1

PADR0

PADR1

Program address detection

register 2

R/W

Address match

detection function

R/W

Program address detection

register 3

Program address detection

register 4

R/W

Program address detection

register 5

1FF6H to

1FFFH

(Reserved area)

• Initial value representations

0: Initial value of 0

1: Initial value of 1

X: Initial value undefined

_: Initial value undefined (none)

• Addresses that follow 00FFH are a reserved area.

• The boundary #^Hbetween the RAM and reserved areas is different depending on each product.

Note : For writable bits, the initial value column contains the initial value to which the bit is initialized at a reset.

Notice that it is not the value read from the bit.

The LPMCR, CKSCR, and WDTC registers may be initialized or not at a reset, depending on the type of the

reset. Their initial values in the above list are those to which the registers are initialized, of course.

“R/W!” in the access column indicates that the register contains read-only or write-only bits.

If a read-modify-write instruction (such as a bit setting instruction) is used to access a register marked “R/

W!” “R/W*”, or “W” in the access column, the bit focused on by the instruction is set to the desired value but

a malfunction occurs if the other bits contains a write-only bit. Do not use such instructions to access those

registers.

28

MB90550A/550B Series

■ INTERRUPT FACTORS

INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS

Interrupt vectors

Interrupt control registers

EI²OS

Interrupt source

support

Number

# 08

# 09

# 10

# 11

# 12

# 13

# 14

# 15

# 16

# 17

# 18

# 19

# 20

# 21

# 22

# 23

# 24

# 25

# 26

# 27

# 28

# 29

# 30

# 31

# 32

#33

Address

FFFFDC^H

FFFFD8H

FFFFD4H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64^H

FFFF60H

FFFF5C^H

FFFF58H

FFFF54H

ICR

—

Address

Reset

×

—

INT9 instruction

—

Exception

—

A/D converter

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

Timebase timer

×

DTP0 (external interrupt 0)

DTP4/5 (external interrupt 4/5)

DTP1 (external interrupt 1)

8/16-bit PPG timer0 counter borrow

DTP2 (external interrupt 2)

×

8/16-bit PPG timer 1 counter borrow

DTP3 (external interrupt 3)

8/16-bit PPG timer 2 counter borrow

Extended I/O serial interface 0

8/16-bit PPG timer 3 counter borrow

Extended I/O serial interface 1

16-bit free-run timer (I/O timer) overflow

16-bit re-load timer 0

DTP6/7 (external interrupt 6/7)

16-bit re-load timer 1

8/16-bit PPG timer 4/5 counter borrow

Input capture (ch.0) include (I/O timer)

Input capture (ch.1) include (I/O timer)

Input capture (ch.2) include (I/O timer)

Input capture (ch.3) include (I/O timer)

Output compare (ch.0) match (Output timer)

Output compare (ch.1) match (Output timer)

Output compare (ch.2) match (Output timer)

Output compare (ch.3) match (Output timer)

UART transmission complete

I²C interface 0

×

# 34

# 35

# 36

# 37

# 38

# 39

# 40

# 41

# 42

×

UART0 reception complete

I²C interface 1

×

Flash memory status

Delayed interrupt generation module

:The interrupt request flag is cleared by the EI²OS interrupt clear signal. The stop request is available.

:The interrupt request flag is cleared by the EI²OS interrupt clear signal.

::The interrupt request flag is not cleared by the EI²OS interrupt clear signal.

×

29

MB90550A/550B Series

Note: On using the EI²OS Function with Extended I/O Serial Interface 2

If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags

are cleared by the EI²OS interrupt clear signal. When the EI²OS function is used for one of the two

interrupt sources, therefore, the other interrupt function cannot be used. Set the interrupt request enable

bit for the relevant resource to “0” for software polling processing.

Interrupt source

Interrupt No. Interrupt control register

Resource interrupt request

Extended I/O serial interface 1

# 23

Enabled

ICR06

# 24

16-bit free-run timer

(I/O timer) overflow

Disabled

30

MB90550A/550B Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

VSS + 6.0

10

V^CC

AV^CC

AVRH

AVRL

V^I

VSS − 0.3

V^SS− 0.3

VSS − 0.3

V

1

VCC ≥ AVCC

*

Power supply voltage

AV^CC≥ AVRH ≥ AVRL

5

Input voltage

*

5

Output voltage

VO

*

IOL1

mA Other than P20 to P27

“L” level maximum output current *²

IOL2

20

mA P20 to P27

I^OLAV1

IOLAV2

∑IOL

∑I^OLAV

IOH

4

mA Other than P20 to P27

“L” level average output current

12

mA P20 to P27

“L” level total maximum output current

“L” level total average output current

“H” level maximum output current *²

“H” level average output current *³

“H” level total maximum output current

“H” level total average output current *⁴

150

mA

80

mA

−15

mA

IOHAV

∑I^OH

∑IOHAV

−4

mA

−100

−50

mA

550

mW MB90P553A

mW MB90F553A

mW MB90553A/553B

mW MB90552A/552B

°C

450

Power consumption

P^D

200

180

Operating temperature

Storage temperature

T^A

−40

−55

+85

TSTG

+150

°C

*1 : Be careful not to let AVcc exceed Vcc, for example, when the power supply is turned on.

*2 : The maximum output current is a peak value for a corresponding pin.

*3 : Average output current is an average current value observed for a 100 ms period for a corresponding pin.

*4 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.

*5 : V^Iand VO should not exceed VCC + 0.3V.

Note: Average output current = operating current × operating efficiency

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

31

MB90550A/550B Series

2. Recommended Operating Conditions

Value

(VSS = AVSS = 0.0 V)

Symbol

Unit

Remarks

Parameter

Min.

Max.

Normal operation (MB90F553A,

MB90P553A, MB90V550A)

4.5

5.5

V

V^CC

AVCC

Power supply voltage

Normal operation (MB90553A, MB90553B,

MB90552A, MB90552B)

3.5

5.5

3.5

0.1

5.5

1.0

V

Retains status at the time of operation stop

*

Smoothing capacitor

C^S

T^A

µF

°C

Operating temperature

–40

+85

* : Use a ceramic capacitor or a capacitor with equivqlent frequency characteristics. The smoothing capacitor to

be connected to the V^CCpin must have a capacitance value higher than CS.

For connecting smoothing capacitor CS, see the diagram below:

• C pin connection circuit

C

AVSS

VSS

C^S

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

32

MB90550A/550B Series

3. DC Characteristics

(VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = –40 °C to +85 °C)

Value

Typ. Max.

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min.

V^IH

V^IHS

VIHM

VIL

V^ILS

VILM

CMOS input pin*¹

^{CMOS hysteresys input pin}*²

MD pin input*³

CMOS input pin*¹

^{CMOS hysteresys input pin}*²

MD pin input*³

—

0.7VCC

0.8VCC

VCC − 0.3

VSS − 0.3

—

VCC+0.3

0.3VCC

0.2VCC

VSS +0.3

V

“H” level input

voltage

“L” level input

voltage

Open-drain output

pin voltage

“H” level output

voltage

“L” level output

voltage 1

“L” level output

voltage 2

Input leakage

current

VD

V^OH

VOL1

V^OL2

IIL

P50 to P55

—

VSS – 0.3

—

VSS + 6.0

V

Other than

P50 to P55

Other than

P20 to P27

VCC = 4.5V,

IOH = −4.0mA

VCC = 4.5V,

IOL = 4.0mA

VCC = 4.5V,

IOL = 12.0mA

VCC = 5.5V,

VSS < VI < VCC

VCC – 0.5

—

0.4

5

—

–5

V

P20 to P27

V

All output pins

µA

MB90V550A

mA

mA MB90P553A

mA MB90F553A

Internal

operation at 16

MHz

V^CC= 5.5 V

Normal opera-

tion

—

30

80

60

30

40

110

90

MB90553A/B

40

mA

ICC

MB90552A/B

—

25

35

When data writ-

ten in flash

mode

MB90F553A

—

100

150

mA

Power supply

current *⁴

MB90V550A

MB90P553A

MB90F553A

—

7

25

10

7

5

0.1

5

10

30

20

10

20

10

20

mA

Internal

operation at 16

MHz

V^CC= 5.5 V

In sleep mode

VCC

ICCS

mA MB90553A/B

MB90552A/B

MB90V550A

mA

µA

µA MB90P553A

VCC = 5.5V,

TA = +25°C

In stop mode

MB90F553A

MB90553A/B

ICCH

µA

5

µA MB90552A/B

Input

capacitance

Open-drain output

leakage current

Other than AVCC,

AVSS, C, VCC and VSS

CIN

—

10

—

5

pF

I^leak

P50 to P55

0.1

µA

Other than

kΩ

P00 to P07 and P10

to P17 (In pull-up

setting),RST

25

20

50

40

100

Pull-up

resistance

MB90V550A

R^UP

—

kΩ MB90V550A

*1 : P00 to P07, P10 to P17, P20 to P27, P30 to P37

*2 : X0, HST, RST, P40 to P47, P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA4

*3 : MD0, MD1 and MD2

*4 : The current value is preliminary value and may be subject to change for enhanced characteristics without

previous notice. The power supply current is measured with an external clock.

33

MB90550A/550B Series

4. AC Characteristics

(1) Clock Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol Pin name

Unit

Parameter

Oscillation clock

Min.

Typ.

Max.

F^C

tC

X0, X1

—

3

—

16

MHz

ns

frequency

Oscillation clock

cycle time

62.5

—

333

5

Frequency fluctuation rate

locked*

∆f

%

P^WH

PWL

Recommended duty ratio

of 40% to 60%

Input clock pulse width

X0

10

—

5

ns

Input clock rising/falling

time

t^CR, tCF

X0

—

ns External clock operation

8.0

1.5

—

16

MHz PLL operation

MHz Main clock operation

ns PLL operation

Internal operating clock

frequency

F^CP

—

62.5

125

666

Internal operating clock

cycle time

t^CP

ns

Main clock operation

* :The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied

PLL signal is locked.

+

+α

α

fo

Center frequency

∆f =

× 100 (%)

fo

−α

−

• X0, X1 clock timing

t^HCYL

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

X0

PWH

PWL

tCF

tCR

34

MB90550A/550B Series

• PLL operation guarantee range

Relationship between internal operating clock frequency and power supply voltage

Operation guarantee range

MB90F553A, MB90P553A,

MB90V550A

5.5

4.5

3.5

PLL Operation guarantee

range

Operation guarantee range MB90553A/553B,

MB90552A/552B

1.5

3

8

12

16

Internal operating clock frequency FCP (MHz)

Relationship between oscillation clock frequency and internal operating clock frequency

Multiplied-

by-4

Multiplied-

by-3

Multiplied-by-1

Multiplied-by-2

16

12

9

8

Not multiplied

4

1.5

3

4

8

16

Oscillation clock frequency F^C(MHz)

The AC ratings are measured for the following measurement reference voltages.

• Input signal waveform

Hystheresis input pin

0.8 VCC

• Output signal waveform

Output pin

2.4 V

0.2 VCC

0.8 V

Pins other than hystheresis input / MD input

0.7 V^CC

0.3 VCC

35

MB90550A/550B Series

(2) Clock Output Timing

(V^CC= 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Pin name

Unit

Remarks

Parameter

Min.

62.5

Max.

—

Cycle time

CLK ↑ → CLK ↓ time

t^CYC

ns

CLK

t^CHCL

tCP/2 − 20

tCP/2+20

tCYC

t^CHCL

2.4 V

0.8 V

CLK

(3) Reset, Hardware Standby Input Timing

(V^CC= 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol Pin name

Unit

Remarks

Parameter

Reset input time

Min.

16 tCP

Max.

—

t^RSTL

t^HSTL

RST

HST

ns

Hardware standby input time

—

tRSTL, tHSTL

RST

HST

0.2 VCC

36

MB90550A/550B Series

(4) Specification for Power-on Reset

(V^CC= 5.0 V ± 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name

Unit

Remarks

Min.

0.05

—

Max.

30

Power supply rising time

Power-supply start voltage

Power-supply end voltage

Power supply cut-off time

t^R

ms

V

V^OFF

VON

tOFF

0.2

—

VCC

2.7

4

V

—

ms

Due to repeated operations

Note • V^CCmust be kept lower than 0.2 V before power-on.

• The above values are used for creating a power-on reset.

• Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on

the power supply using the above values.

tR

2.7 V

0.2 V

VCC

t^OFF

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended to

raise the voltage smoothly to suppress fluctuations as shown below.

In this case, change the supply voltage with the PLL clock not used. If the voltage drop is

1 V or fewer per second, however, you can use the PLL clock.

VCC

5.0 V

3.0 V

It is recommended to keep the rising speed of

the supply voltage at 50 mV/ms or slower.

RAM data being held

V^SS

0 V

37

MB90550A/550B Series

(5) Bus Read Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

ALE pulse width

Symbol

Pin name

Unit Remarks

Min.

Max.

t^LHLL

tAVLL

t^LLAX

tAVRL

ALE

tCP/2 − 20

—

ns

ALE, A23 to A16,

AD15 to AD00

Effective address → ALE ↓ time

ALE ↓ → address effective time

Effective address → RD ↓ time

tCP/2 − 20

—

ALE, AD15 to AD00 tCP/2 − 15

A23 to A16,

tCP − 15

AD15 to AD00, RD

A23 to A16,

—

Effective address → valid data

input

t^AVDV

5 tCP/2 − 60

ns

AD15 to AD00

RD pulse width

tRLRH

tRLDV

tRHDX

tRHLH

tRHAX

RD

3 tCP/2 − 20

—

ns

RD ↓ → valid data input

RD ↑ → data hold time

RD ↑ → ALE ↑ time

RD, AD15 to AD00

RD, ALE

3 tCP/2 − 60

0

—

tCP/2 − 15

tCP/2 − 10

RD ↑ → address effective time

ALE, A23 to A16

A23 to A16,

AD15 to AD00, CLK

Effective address → CLK ↑ time

t^AVCH

tCP/2 − 20

—

ns

RD ↓ → CLK ↑ time

ALE ↓ → RD ↓ time

tRLCH

tLLRL

RD, CLK

ALE, RD

tCP/2 − 20

tCP/2 − 15

—

ns

• Bus read timing

tAVCH

tRLCH

2.4 V

CLK

tRHLH

2.4 V

0.8 V

2.4 V

tLHLL

tAVLL

ALE

tLLAX

tRLRH

RD

2.4 V

0.8 V

tLLRL

• Multiplex mode

tRHAX

tAVRL

tRLDV

A23 to A16

2.4 V

0.8 V

2.4 V

0.8 V

tRHDX

tAVDV

2.4 V

0.8 V

2.4 V

0.8 V

0.7 VCC

0.3 VCC

0.7 V^CC

0.3 VCC

Read data

Address

AD15 to AD00

38

MB90550A/550B Series

(6) Bus Write Timing

Parameter

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Unit

Symbol

Pin name

Remarks

Min.

Max.

—

A23 to A16, AD15 to

AD00, WRH, WRL

Effective address → WR ↓ time

WR pulse width

tAVWL

tWLWH

tDVWH

tCP – 15

ns

WRH, WRL

3 tCP/2 – 20

—

AD15 to AD00,

WRH, WRL

valid data output→ WR ↑ time

—

AD15 to AD00,

WRH, WRL

Multiplex

mode

WR ↑ → data hold time

tWHDX

tWHAX

20

—

ns

A23 to A16,

WRH, WRL

WR ↑ → address effective time

tCP/2 – 10

WR ↑ → ALE ↑ time

WR ↓ → CLK ↑ time

tWHLH

tWLCH

WRH, WRL, ALE

WRH, WRL, CLK

tCP/2 – 15

tCP/2 – 20

—

ns

• Bus write timing

tWLCH

2.4 V

CLK

ALE

tWHLH

2.4 V

tAVWL

tWLWH

WR

2.4 V

(WRL, WRH)

0.8 V

• Multiplex mode

tWHAX

2.4 V

0.8 V

2.4 V

0.8 V

A23 to A16

tWHDX

tDVWH

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to AD00

Address

Write data

0.8 V

39

MB90550A/550B Series

(7) Ready Input Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Unit

Remarks

Min.

45

Max.

—

RDY setup time

RDY hold time

t^RYHS

t^RYHH

ns

RDY

CLK

0

—

Note : Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.

• Ready input timing

2.4 V

CLK

ALE

WR

(WRL, WRH)

0.8 V

tRYHS

tRYHH

RDY

wait not

inserted

0.8 V^CC

0.8 VCC

RDY

wait inserted

(1 cycle)

0.2 VCC

40

MB90550A/550B Series

(8) Hold Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name

Unit

Remarks

Min.

30

Max.

tCP

Pins in floating status → HAK ↓ time

HAK ↑ → pin valid time

tXHAL

HAK

tHAHV

ns

tCP

2 tCP

Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.

• Hold timing

HAK

tXHAL

tHAHV

Pins

High impedance

(9) UART, Extended I/O Serial 0, 1 Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min. Max.

Serial clock cycle time

t^SCYC

SCK0 to SCK2

8 t^CP

—

ns

SCK0 to SCK2,

SOT0 to SOT2

Internal shift clock

mode

SCK ↓ → SOT delay time

tSLOV

–80

80

C^L= 80 pF

+ 1 TTL for an out-

put pin

SCK0 to SCK2,

SIN0 to SIN2

Valid SIN → SCK ↑

t^IVSH

t^SHIX

100

—

ns

SCK0 to SCK2,

SIN0 to SIN2

SCK ↑ → valid SIN hold time

tCP

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SCK0 to SCK2

4 t^CP

—

ns

4 tCP

External shift clock

mode

C^L= 80 pF

+ 1 TTL for an

output pin

SCK0 to SCK2,

SOT0 to SOT2

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

tSLOV

t^IVSH

t^SHIX

—

60

150

—

ns

SCK0 to SCK2,

SIN0 to SIN2

SCK0 to SCK2,

SIN0 to SIN2

SCK ↑ → valid SIN hold time

—

Notes: • These are AC ratings in the CLK synchronous mode.

• C^Lis the load capacitance value connected to pins while testing.

41

MB90550A/550B Series

• Internal shift clock mode

tSCYC

SCK

0.8 V

tSLOV

2.4 V

0.8 V

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

SIN

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 V^CC

0.2 VCC

0.8 VCC

0.2 VCC

SIN

(10) Timer Input Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Pin name

Unit

Remarks

Parameter

Min.

Max.

t^TIWH

TIN0, TIN1

IN0 to IN3

Input pulse width

4 tCP

—

ns

tTIWL

• Timer input timing

0.8 VCC

0.2 VCC

TIN0 to TIN1

IN0 to IN3

0.2 VCC

tTIWH

tTIWL

42

MB90550A/550B Series

(11) Timer Output Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Unit Remarks

Min.

Max.

TOT0,TOT1,OUT0,

OUT1,PPG0 to PPG5

CLK ↑ → T^OUTtransition time

tTO

30

—

ns

• Timer output timing

2.4 V

CLK

t^TO

TOT0,TOT1

OUT0,OUT1

PPG0 to PPG5

2.4 V

0.8 V

(12) Trigger Input Timing

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

IRQ0 to IRQ7

Unit

Remarks

Min.

Max.

Input pulse width

t^TRGL

5 tCP

—

ns

• Trigger input timing

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

IRQ0 to IRQ7

tTRGH

tTRGL

43

MB90550A/550B Series

(13) I²C Interface

(V^CC= 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Unit

Remarks

Min.

Max.

Internal clock cycle time

Start condition output

t^CP

—

62.5

666

ns All products

t^STAO

t^CP× m × n/2 – 20 tCP × m × n/2 + 20 ns

Only as master

Only as slave

Only as master

tCP (m × n/2 + 4) tCP (m × n/2 + 4)

Stop condition output

t_STOO

ns

SDA0 to SDA2

SCL0 toSCL2

– 20

+ 20

Start condition detection

Stop condition detection

SCL output “L” width

t^STAI

t^STOI

3 tCP + 40

—

ns

—

tLOWO

t^CP× m × n/2 – 20 tCP × m × n/2 + 20 ns

SCL0 to SCL2

tCP (m × n/2 + 4) tCP (m × n/2 + 4)

SCL output “H” width

SDA output delay time

t^HIGHO

t^DOO

ns

– 20

+ 20

2 t^CP– 20

2 tCP + 20

ns

SDA0 to SDA2

SCL0 to SCL2

Setup after SDA output

interrupt period

tDOSUO

4 tCP – 20

—

SCL input “L” width

SCL input “H” width

SDA input setup time

SDA input hold time

t^LOWI

t^HIGHI

t^SUI

3 t^CP+ 40

—

ns

SCL0 to SCL2

tCP + 40

40

0

SDA0 to SDA2

SCL0 to SCL2

t^HOI

Notes: • “m” and“n” in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in the

clock control register “ICCR”. For details, refer to the register description in the hardware manual.

• t^DOSUOrepresents the minimum value when the interrupt period is equal to or greater than the SCL “L” width.

• The SDA and SCL output values indicate that that rise time is 0 ns.

44

MB90550A/550B Series

• I²C interface [data transmitter (master/slave)]

tLOWO

tHIGHO

0.8 VCC

0.8 V^CC0.8 VCC

SCL

SDA

0.2 VCC

tDOO

0.2 VCC

8

1

9

tSUI

tHOI

tDOSUO

tSTAO

tDOO

ACK

• I²C interface [data receiver (master/slave)]

tHIGHI

tLOWI

0.8 VCC

SCL

SDA

0.2 VCC

tHOI

0.2 VCC

8

0.2 VCC

6

7

9

tSTOI

t^SUI

tDOO

tDOSUO

ACK

45

MB90550A/550B Series

5. A/D Converter

(1)Electrical Characteristics

(4.5 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Typ.

10

Parameter

Resolution

Symbol Pin name

Unit

Remarks

Min.

—

Max.

—

bit

Total error

—

±5.0

±2.5

±1.9

LSB

Non-linearity error

Differential linearity error

—

AVRL−

3.5LSB

AVRL+

0.5LSB

AVRL+

4.5LSB

Zero transition voltage

V^OT

AN0 to AN7

V

1LSB=

(AVRH−AVRL)

/1024

Full-scale transition

voltage

AVRH−

6.5LSB

AVRH−

1.5LSB

AVRH+

1.5LSB

V^FST

tCP

µs

µA

V

Sampling period

tSMP

tCMP

t^CNV

IAIN

VAIN

—

64

22

—

4096

—

*1

*2

Compare time

A/D Conversion time

Analog port input current

Analog input voltage

—

26.3

—

AN0 to AN7

AVRH

AVRL

—

10

AVRL

0

—

AVRH

AV^CC

AVRH

7.0

5

V

—

Reference voltage

V

—

I^A

—

3.5

—

mA

µA

LSB

Power supply current

AVCC

IAH

I^R

—

*3

—

300

—

500

5

Reference voltage

supply current

AVRH

IRH

—

Offset between channels

AN0 to AN7

—

4

*1: When F^CP= 8 MHz, tCMP = 176 × tCP. When FCP = 16 MHz, tCMP = 352 × tCP.

*2: Equivalent to the time for conversion per channel if “t^SMP= 64 × tCP” or “tCMP = 352 × tCP” is selected when FCP =

16 MHz.

*3: Specifies the power-supply current (Vcc = AVcc = AVRH = 5.0 V) when the A/D converter is inactive and the

CPU has been stopped.

Notes: • The error becomes larger relatively as |AVRH-AVRL| becomes smaller.

• Use the output impedance r^Sof the external circuit for analog input under the following condition:

External circuit output impedance rS = 10 kΩ Max.

• If the output impedance of the external circuit is too high, the analog voltage sampling time may be

insufficient.

• If you insert a DC-blocking capacitor between the external circuit and the input pin, select a capacitance

that is about several thousands times the sampling capacitance CSH in the chip to suppress the effect of

capacity potential division with CSH.

46

MB90550A/550B Series

• Analog input circuit model

Microcontroller internal circuit

Input pin AN0

CSH

rS

RSH

Comparator

Input pin AN7

VS

S/H circuit

Analog channel selector

External circuit

r^S= 10 kΩ or less

R^SH= About 3 kΩ

C^SH= About 25 pF

Note: Device parameter values are provided as reference values for design purposes; they

are not guaranteed.

47

MB90550A/550B Series

(2) Definitions of Terms

• Resolution: Analog transition identifiable by the A/D converter.

Analog voltage can be divided into 1024 (2¹⁰) components at 10-bit resolution.

• Total error: Difference between actual and logical values. This error is the sum of an offset error, gain error,

non-linearity error and an error caused by noise.

• Linearity error: Deviation of the straight line drawn between the zero transition point (00 0000 0000 <-> 00

0000 0001) and the full-scale transition point (11 1111 1110 <-> 11 1111 1111) of the device

from actual conversion characteristics

• Differential linearity error: Deviation from the ideal input voltage required to shift output code by one LSB

• 10-bit A/D converter conversion characteristics

11 1111 1111

11 1111 1110

11 1111 1101

11 1111 1100

•

1LSB × N + VOT

Linearity error

00 0000 0011

00 0000 0010

00 0000 0001

00 0000 0000

VOT

VNT V(N + 1)T

VFST

Analog input

V^FST− VOT

1LSB =

1022

V^NT− (1LSB × N + VOT)

1LSB

Linearity error =

[ LSB ]

V (N + 1) T − VNT

Differential linearity error =

− 1 [ LSB ]

1LSB

48

MB90550A/550B Series

■ EXAMPLE CHARACTERISTICS

1. “L” level output voltage

VOL − IOL

Other than P20 to P27

700

600

500

400

300

200

100

0

2

4

6

8

10

I^OL(mA)

V^OL− IOL

P20 to P27

700

T^A= 25 °C

VCC = 3.5 V

VCC = 4.0 V

600

500

400

300

200

100

VCC = 5.0 V

VCC = 6.0 V

0

5

10

15

20

25

30

I^OL(mA)

49

MB90550A/550B Series

2. “H” level output voltage

(VCC − VOH) − IOH

Other than P50 to P55

700

600

500

400

300

T^A= 25 °C

VCC = 3.5 V

V^CC= 4.0 V

V^CC= 5.0 V

VCC = 6.0 V

200

100

0

−2

−4

−6

−8

−10

I^OH(mA)

3. “H” level input voltage / “L” level input voltage (CMOS input)

VIH / VIL − VCC

5

TA = 25 °C

4.5

4

3.5

3

2.5

2

1.5

1

1.5

0

3.5

4

4.5

5

5.5

V^CC(V)

50

MB90550A/550B Series

4. “H” level input voltage / “L” level input voltage (CMOS hysteresis input)

VIHS / VILS − VCC

5

TA = 25 °C

4.5

4

3.5

3

VIHS

2.5

2

V^IHL

1.5

1

1.5

0

3.5

4

4.5

5

5.5

VCC (V)

51

MB90550A/550B Series

5. Power supply current

(f^CP= internal operating clock frequency)

• MB90552A

• Measurement conditions: External clock mode, ROM read loop operation,

without resource operation, Typ. sample,

internal operating frequency = 4MHz (external rectangular wave

clock at 8MHz), T^A= 25 °C

ICC − VCC

30

T^A= 25 °C

fCP = 16 MHz

25

20

15

10

5

fCP = 10.6 MHz

fCP = 8 MHz

f^CP= 4 MHz

0

3.5

4

4.5

5

5.5

V^CC(V)

ICCS − VCC

10

T^A= 25 °C

9

8

fCP = 16 MHz

7

6

5

4

3

2

1

0

fCP = 10.6 MHz

fCP = 8 MHz

fCP = 4 MHz

3.5

4

4.5

5

5.5

V^CC(V)

52

MB90550A/550B Series

• MB90F553A

• Measurement conditions: External clock mode, ROM read loop operation,

without resource operation, Typ. sample,

internal operating frequency = 4MHz (external rectangular wave

clock at 8MHz), T^A= 25 °C

ICC − VCC

70

T^A= 25 °C

60

50

40

30

20

10

fCP = 16 MHz

fCP = 10 MHz

fCP = 4 MHz

4.5

5

5.5

V^CC(V)

ICCS − VCC

12

T^A= 25 °C

10

8

f^CP= 16 MHz

6

fCP = 10 MHz

f^CP= 4MHz

4

2

0

4.5

5

5.5

V^CC(V)

53

MB90550A/550B Series

6. Pull-up resistance

Pull-up resistance − VCC

90

80

70

60

50

40

30

20

10

TA = 85 °C

T^A= 25 °C

T^A= −40 °C

4

4.5

5

5.5

V^CC(V)

54

MB90550A/550B Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90552APF

MB90552BPF

MB90553APF

MB90553BPF

MB90T552APF

MB90T553APF

MB90F553APF

MB90P553APF

100-pin plastic QFP

(FPT-100P-M06)

MB90552APFV

MB90552BPFV

MB90553APFV

MB90553BPFV

MB90T552APFV

MB90T553APFV

MB90F553APFV

MB90P553APFV

100-pin plastic LQFP

(FPT-100P-M05)

55

MB90550A/550B Series

■ PACKAGE DIMENSIONS

100-pin plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

3.35(.132)MAX

(Mounting height)

20.00±0.20(.787±.008)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

REF

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

16.30±0.40

(.642±.016)

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.53(.021)MAX

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

2000 FUJITSU LIMITED F100008-3C-3

Dimensions in mm (inches)

(Continued)

56

MB90550A/550B Series

(Continued)

100-pin plastic LQFP

(FPT-100P-M05)

16.00±0.20(.630±.008)SQ

14.00±0.10(.551±.004)SQ

75

51

76

50

0.08(.003)

Details of "A" part

1.50 ⁺–0⁰.^.1²0⁰.059 –⁺.^.0⁰0⁰4⁸

(Mounting height)

INDEX

0.10±0.10

(.004±.004)

(Stand off)

100

26

0°~8°

"A"

0.50±0.20

(.020±.008)

0.25(.010)

1

25

0.60±0.15

(.024±.006)

0.50(.020)

0.20±0.05

(.008±.002)

0.145±0.055

(.0057±.0022)

M

0.08(.003)

C

2000 FUJITSU LIMITED F100007S-3c-5

Dimensions in mm (inches)

57

MB90550A/550B Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0101

FUJITSU LIMITED Printed in Japan


型号：	MB90T552A
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总58页 (文件大小：658K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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