MB91101APMC_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-16301-6E

32-bit RISC Microcontroller

CMOS

FR30 MB91101 Series

MB91101A

■ DESCRIPTION

The MB91101 Series is a standard single-chip microcontroller constructed around the 32-bit RISC CPU

(FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/

high-speed CPU processing for embedded controller applications. To support the vast memory space

accessed by the 32-bit CPU, the MB91101A Series normally operates in the external bus access mode and

executes instructions on the internal 1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance.

The MB91101A Series is optimized for applications requiring high-performance CPU processing such as

navigation systems, high-performance FAXs and printer controllers.

*: FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Semiconductor Limited.

■ FEATURES

FR CPU

• 32-bit RISC, load/store architecture, 5-stage pipeline

• Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz)

• General purpose registers: 32 bits × 16

• 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle

• Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications

• Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems

supporting high level languages

• Register interlock functions, efficient assembly language coding

• Branch instructions with delay slots: Reduced overhead time in branch executions

(Continued)

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

2011.1

MB91101 Series

• Internal multiplier/supported at instruction level

Signed 32-bit multiplication: 5 cycles

Signed 16-bit multiplication: 3 cycles

• Interrupt (push PC and PS): 6 cycles, 16 priority levels

External bus interface

• Clock doubler: Internal 50 MHz, external bus 25 MHz operation

• 25-bit address bus (32 Mbytes memory space)

• 8/16-bit data bus

• Basic external bus cycle: 2 clock cycles

• Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6

• Interface supported for various memory technologies

DRAM interface (area 4 and 5)

• Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area

• Unused data/address pins can be configured as input/output ports.

• Little endian mode supported (Select 1 area from area 1 to 5)

DRAM interface

• 2 banks independent control (area 4 and 5)

• Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM

• Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode

• Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles

• DRAM refresh

CBR refresh (interval time configurable by 6-bit timer)

Self-refresh mode

• Supports 8/9/10/12-bit column address width

• 2CAS/1WE, 2WE/1CAS selective

Cache memory

• 1-Kbyte instruction cache memory

• 32 block/way, 4 entry(4 word)/block

• 2 way set associative

• Lock function: For specific program code to be resident in cashe memory

DMA controller (DMAC)

• 8 channels

• Transfer incident/external pins/internal resource interrupt requests

• Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer

• Transfer data length: 8 bits/16 bits/32 bits selective

• NMI/interrupt request enables temporary stop operation.

UART

• 3 independent channels

• Full-duplex double buffer

• Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity)

• Asynchronous (start-stop system), CLK-synchronized communication selective

• Multi-processor mode

• Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud

rate

• External clock can be used as a transfer clock.

• Error detection: Parity, frame, overrun

(Continued)

2

DS07-16301-6E

MB91101 Series

(Continued)

10-bit A/D converter (successive approximation conversion type)

• 10-bit resolution, 4 channels

• Successive approximation type: Conversion time of 5.6 μs at 25 MHz

• Internal sample and hold circuit

• Conversion mode: Single conversion/scanning conversion/repeated conversion/stop conversion selective

• Start: Software/external trigger/internal timer selective

16-bit reload timer

• 3 channels

• Internal clock: 2 clock cycle resolution, divide by 2/8/32 selective

Other interval timers

• 16-bit timer: 3 channels (U-TIMER)

• PWM timer: 4 channels

• Watchdog timer: 1 channel

Bit search module

First bit transition “1” or “0” from MSB can be detected in 1 cycle.

Interrupt controller

• External interrupt input: Non-maskable interrupt (NMI), normal interrupt × 4 (INT0 to INT3)

• Internal interrupt incident:UART, DMA controller (DMAC), A/D converter, U-TIMER and delayed interrupt

module

• Priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps).

Others

• Reset cause: Power-on reset/hardware standby/watchdog timer/software reset/external reset

• Low-power consumption mode: Sleep mode/stop mode

• Clock control

Gear function: Operating clocks for CPU and peripherals are independently selective.

Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16).

However, operating frequency for peripherals is less than 25 MHz.

• Packages: LQFP-100 and QFP-100

• CMOS technology (0.35 μm)

• Power supply voltage

5 V: CPU power supply 5.0 V 10% (internal regulator)

A/D power supply 2.7 V to 3.6 V

3 V: CPU power supply 2.7 V to 3.6 V (without internal regulator)

A/D power supply 2.7 V to 3.6 V

DS07-16301-6E

3

MB91101 Series

■ PIN ASSIGNMENT

(Top view)

CS1L/PB5/DREQ2

CS1H/PB6/DACK2

DW1/PB7

V^CC3

CLK/PA6

CS5/PA5

CS4/PA4

CS3/PA3/EOP1

CS2/PA2

CS1/PA1

CS0

NMI

HST

RST

V^SS

MD0

MD1

MD2

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

AN3

AN2

AN1

AN0

2

3

4

5

AV^SS/AVRL

AVRH

AVCC

A24/EOP0

A23/P67

A22/P66

VSS

A21/P65

A20/P64

A19/P63

A18/P62

A17/P61

A16/P60

A15

A14

A13

A12

A11

A10

A09

A08

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

RDY/P80

BGRNT/P81

BRQ/P82

RD

WR0

WR1/P85

D16/P20

(FPT-100P-M20)

(Continued)

4

DS07-16301-6E

MB91101 Series

(Continued)

(Top view)

CS0H/PB2

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SO0/TRG1/PF1

SI0/TRG0/PF0

AN3

AN2

AN1

DW0/PB3

RAS1/PB4/EOP2

CS1L/PB5/DREQ2

CS1H/PB6/DACK2

DW1/PB7

VCC3

2

3

4

5

6

AN0

7

AV^SS/AVRL

AVRH

AV^CC

A24/EOP0

A23/P67

A22/P66

V^SS

A21/P65

A20/P64

A19/P63

A18/P62

A17/P61

A16/P60

A15

A14

A13

A12

A11

A10

A09

A08

A07

CLK/PA6

CS5/PA5

CS4/PA4

CS3/PA3/EOP1

CS2/PA2

CS1/PA1

CS0

NMI

HST

RST

VSS

MD0

MD1

MD2

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

RDY/P80

BGRNT/P81

BRQ/P82

RD

WR0

WR1/P85

D16/P20

D17/P21

D18/P22

A06

A05

(FPT-100P-M06)

DS07-16301-6E

5

MB91101 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Description

LQFP*¹

QFP*²

D16 to D23

P20 to P27

Bit 16 to bit 23 of external data bus

25 to 32 28 to 35

C

Can be configured as I/O ports when external data bus width is

set to 8-bit.

33 to 39, 36 to 42, D24 to D30,

C

F

Bit 24 to bit 31 of external data bus

41

44

D31

42,

45,

A00,

Bit 00 to bit 15 of external address bus

44 to 58 47 to 61 A01 to A15

A16 to A21,

A22,

Bit 16 to bit 23 of external address bus

59 to 64, 62 to 67,

A23

66,

67

69,

70

F

P60 to P65,

P66,

Can be configured as I/O ports when not used as address bus.

Bit 24 of external address bus

P67

A24

68

19

20

71

22

23

L

C

F

Can be configured as DMAC EOP output (ch. 0) when DMAC

EOP output is enabled.

EOP0

External ready input

Inputs “0” when bus cycle is being executed and not completed.

RDY

P80

Can be configured as a port when RDY is not used.

External bus release acknowledge output

Outputs “L” level when external bus is released.

BGRNT

P81

Can be configured as a port when BGRNT is not used.

External bus release request input

Inputs “1” when release of external bus is required.

BRQ

21

22

24

25

C

L

P82

RD

Can be configured as a port when BRQ is not used.

Read strobe output pin for external bus

Write strobe output pin for external bus

Relation between control signals and effective byte locations is

as follows:

23

24

26

27

WR0

L

F

16-bit bus width

WR0

8-bit bus width

WR0

D15 to D08

D07 to D00

WR1

(I/O port enabled)

WR1 is High-Z during resetting.

Attach an external pull-up resister when using at 16-bit bus

width.

WR1

P85

Can be configured as a port when WR1 is not used.

*1: FPT-100P-M20

*2: FPT-100P-M06

(Continued)

6

DS07-16301-6E

MB91101 Series

Pin no.

Circuit

type

Pin name

Description

LQFP*¹

QFP*²

11

14

CS0

CS1

PA1

CS2

PA2

CS3

L

F

Chip select 0 output (“L” active)

Chip select 1 output (“L” active)

10

13

12

Can be configured as a port when CS1 is not used.

Chip select 2 output (“L” active)

9

8

F

Can be configured as a port when CS2 is not used.

Chip select 3 output (“L” active)

Can be configured as a port when CS3 and EOP1 are not

used.

PA3

11

F

EOP output pin for DMAC (ch. 1)

EOP1

This function is available when EOP output for DMAC is en-

abled.

CS4

PA4

CS5

PA5

Chip select 4 output (“L” active)

7

6

10

9

F

Can be configured as a port when CS4 is not used.

Chip select 5 output (“L” active)

Can be configured as a port when CS5 is not used.

System clock output

Outputs clock signal of external bus operating frequency.

CLK

PA6

5

8

99

100

1

F

Can be configured as a port when CLK is not used.

RAS output for DRAM bank 0

Refer to the DRAM interface for details.

RAS0

PB0

96

97

98

99

Can be configured as a port when RAS0 is not used.

CASL output for DRAM bank 0

Refer to the DRAM interface for details.

CS0L

PB1

Can be configured as a port when CS0L is not used.

CASH output for DRAM bank 0

Refer to the DRAM interface for details.

CS0H

PB2

Can be configured as a port when CS0H is not used.

WE output for DRAM bank 0 (“L” active)

Refer to the DRAM interface for details.

DW0

PB3

2

Can be configured as a port when DW0 is not used.

RAS output for DRAM bank 1

Refer to the DRAM interface for details.

RAS1

Can be configured as a port when RAS1 and EOP2 are not

used.

100

3

PB4

F

DMAC EOP output (ch. 2)

This function is available when DMAC EOP output is enabled.

EOP2

*1: FPT-100P-M20

*2: FPT-100P-M06

(Continued)

DS07-16301-6E

7

MB91101 Series

Pin no.

Circuit

type

Pin name

Description

CASL output for DRAM bank 1

LQFP*¹

QFP*²

CS1L

PB5

Refer to the DRAM interface for details.

Can be configured as a port when CS1L and DREQ2 are not used.

1

4

F

External transfer request input pin for DMA

This pin is used for input when external trigger is selected to cause

DMAC operation, and it is necessary to disable output for other

functions from this pin unless such output is made intentionally.

DREQ2

CASH output for DRAM bank 1

Refer to the DRAM interface for details.

CS1H

PB6

Can be configured as a port when CS1H and DACK2 are not used.

2

3

5

6

External transfer request acknowledge output pin for DMAC (ch. 2)

This function is available when transfer request output for DMAC is

enabled.

DACK2

WE output for DRAM bank 1 (“L” active)

Refer to the DRAM interface for details.

DW1

PB7

F

Can be configured as a port when DW1 is not used.

Mode pins 0 to 2

MCU basic operation mode is set by these pins.

Directly connect these pins with V^CCor VSS for use.

MD0 to

MD2

16 to 18 19 to 21

G

92

91

14

13

12

95

94

17

16

15

X0

X1

A

B

H

Clock (oscillator) input

Clock (oscillator) output

RST

HST

NMI

External reset input

Hardware standby input (“L” active)

NMI (non-maskable interrupt pin) input (“L” active)

External interrupt request input pins

INT0,

INT1

These pins are used for input during corresponding interrupt is en-

abled, and it is necessary to disable output for other functions from

these pins unless such output is made intentionally.

95,

94

98,

97

F

PE0,

PE1

Can be configured as I/O ports when INT0, INT1 are not used.

External interrupt request input pin

This pin is used for input during corresponding interrupt is enabled,

and it is necessary to disable output for other functions from this pin

unless such output is made intentionally.

INT2

89

92

F

Clock I/O pin for UART1

Clock output is available when clock output of UART1 is enabled.

SC1

PE2

Can be configured as the I/O port when INT2 and SC1 are not used.

This function is available when UART1 clock output is disabled.

*1: FPT-100P-M20

*2: FPT-100P-M06

(Continued)

8

DS07-16301-6E

MB91101 Series

Pin no.

name

Circuit

type

Description

External interrupt request input pin

LQFP*¹

QFP*²

This pin is used for input during corresponding interrupt is enabled,

and it is necessary to disable output for other functions from this pin

unless such output is made intentionally.

INT3

88

91

F

UART2 clock I/O pin

Clock output is available when UART2 clock output is enabled.

SC2

PE3

Can be configured as the I/O port when INT3 and SC2 are not used.

This function is available when UART2 clock output is disabled.

External transfer request input pins for DMA

These pins are used for input when external trigger is selected to

cause DMAC operation, and it is necessary to disable output for

other functions from these pins unless such output is made inten-

tionally.

DREQ0,

DREQ1

87,

86

90,

89

PE4,

PE5

Can be configured as I/O ports when DREQ0, DREQ1 are not

used.

External transfer request acknowledge output pin for DMAC (ch. 0)

This function is available when transfer request output for DMAC is

enabled.

DACK0

PE6

85

84

88

87

F

Can be configured as the I/O port when DACK0 is not used.

This function is available when transfer request acknowledge out-

put for DMAC or DACK0 output is disabled.

External transfer request acknowledge output pin for DMAC (ch. 1)

This function is available when transfer request output for DMAC is

enabled.

DACK1

PE7

Can be configured as the I/O port when DACK1 is not used.

This function is available when transfer request output for DMAC or

DACK1 output is disabled.

UART0 data input pin

This pin is used for input during UART0 is in input operation, and it

is necessary to disable output for other functions from this pin un-

less such output is made intentionally.

SI0

76

79

F

PWM timer external trigger input pin

This pin is used for input during PWM timer external trigger is in in-

put operation, and it is necessary to disable output for other func-

tions from this pin unless such output is made intentionally.

TRG0

PF0

Can be configured as the I/O port when SI0 and TRG0 are not used.

*1: FPT-100P-M20

*2: FPT-100P-M06

(Continued)

DS07-16301-6E

9

MB91101 Series

Pin no.

name

Circuit

type

Description

LQFP*¹

QFP*²

UART0 data output pin

This function is available when UART0 data output is enabled.

SO0

PWM timer external trigger input pin

This function is available when serial data output of PF1, UART0

are disabled.

TRG1

77

78

79

80

F

Can be configured as the I/O port when SO0 and TRG1 are not

used.

This function is available when serial data output of UART0 is dis-

abled.

PF1

UART0 clock I/O pin

Clock output is available when UART0 clock output is enabled.

SC0

PWM timer output pin

This function is available when PWM timer output is enabled.

OCPA3

81

Can be configured as the I/O port when SC0 and OCPA3 are not

used.

This function is available when UART0 clock output is disabled.

PF2

SI1

UART1 data input pin

This pin is used for input during UART1 is in input operation, and it

is necessary to disable output for other functions from this pin un-

less such output is made intentionally.

82

PWM timer external trigger input pin

This pin is used for input during PWM timer external trigger is in in-

put operation, and it is necessary to disable output for other func-

tions from this pin unless such output is made intentionally.

TRG2

PF3

SO1

Can be configured as the I/O port when SI1 and TRG2 are not used.

UART1 data output pin

This function is available when UART1 data output is enabled.

PWM timer external trigger input pin

TRG3

PF4

This function is available when PF4, UART1 data outputs are dis-

abled.

80

83

F

Can be configured as the I/O port when SO1 and TRG3 are not

used.

This function is available when UART1 data output is disabled.

UART2 data input pin

This pin is used for input during UART2 is in input operation, and it

is necessary to disable output for other functions from this pin un-

less such output is made intentionally.

SI2

81

84

F

PWM timer output pin

This function is available when PWM timer output is enabled.

OCPA1

PF5

Can be configured as the I/O port when SI2 and OCPA1 are not

used.

*1: FPT-100P-M20

*2: FPT-100P-M06

(Continued)

10

DS07-16301-6E

MB91101 Series

(Continued)

Pin no.

Circuit

type

Pin name

Description

LQFP*¹

QFP*²

UART2 data output pin

This function is available when UART2 data output is enabled.

SO2

PWM timer output pin

This function is available when PWM timer output is enabled.

OCPA2

82

85

F

Can be configured as the I/O port when SO2 and OCPA2 are

not used.

This function is available when UART2 data output is disabled.

PF6

OCPA0

PF7

PWM timer output pin

This function is available when PWM timer output is enabled.

Can be configured as the I/O port when OCPA0 and ATG are

not used.

This function is available when PWM timer output is disabled.

83

86

F

External trigger input pin for A/D converter

This pin is used for input when external trigger is selected to

cause A/D converter operation, and it is necessary to disable

output for other functions from this pin unless such output is

made intentionally.

ATG

72 to 75 75 to 78 AN0 to AN3

D

Analog input pins of A/D converter

69

72

AV^CC

—

Power supply pin (VCC) for A/D converter

Reference voltage input (high) for A/D converter

Make sure to turn on and off this pin with potential of AVRH or

more applied to AV^CC.

70

73

AVRH

—

Power supply pin (VSS) for A/D converter and reference voltage

input pin (low)

71

74

AVSS / AVRL

VCC5

5 V power supply pin (VCC) for digital circuit

Always two pins must be connected to the power supply (con-

nect to 3 V power supply when operating at 3 V).

43,

93

46,

96

Bypass capacitor pin for internal capacitor.

4

7

V^CC3

—

Also connect this pin to 3 V power supply when operating at

3 V.

15,

40,

65,

90

18,

43,

68,

93

VSS

Earth level (VSS) for digital circuit

*1: FPT-100P-M20

*2: FPT-100P-M06

Note: In most of the above pins, I/O ports and resource I/O are multiplexed, e.g. P82 and BRQ. In case of conflict

between output of I/O ports and resource I/O, priority is always given to the output of resource I/O.

DS07-16301-6E

11

MB91101 Series

■ DRAM CONTROL PIN

Data bus 16-bit mode

Data bus 8-bit mode

—

Pin name

Remarks

2CAS/1WR mode

1CAS/2WR mode

RAS0

RAS1

CS0L

CS0H

CS1L

CS1H

DW0

Area 4 RAS

Area 5 RAS

Area 4 CAS

Area 5 CAS

Area 4 WE

Area 5 WE

Correspondence of “L”,

“H” to lower address 1

bit (A0) in data bus 16-

bit mode

“L”: “0”

“H”: “1”

Area 5 RAS

Area 4 CASL

Area 4 CASH

Area 5 CASL

Area 5 CASH

Area 4 WE

Area 5 RAS

Area 4 CAS

Area 4 WEL

Area 5 CAS

Area 5 WEL

Area 4 WEH

Area 5 WEH

CASL:CAS which A0

corresponds to “0” area

CASH:CAS which A0

corresponds to “1” area

WEL: WE which A0 cor-

responds to “0” area

WEH:WE which A0 cor-

responds to “1” area

DW1

Area 5 WE

12

DS07-16301-6E

MB91101 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistance 1 MΩ

approx.

With standby control

X1

Clock input

X0

A

Standby control signal

• CMOS level Hysteresis input

Without standby control

With pull-up resistance

V^CC

P-ch

R

B

N-ch

VSS

Digital input

• CMOS level I/O

With standby control

P-ch

N-ch

Digital output

R

C

Digital input

Standby control signal

• Analog input

P-ch

Digital output

Analog input

D

N-ch

R

(Continued)

DS07-16301-6E

13

MB91101 Series

(Continued)

Type

Circuit

Remarks

• CMOS level output

• CMOS level Hysteresis input

With standby control

P-ch

N-ch

Digital output

R

F

Digital input

Standby control signal

• CMOS level input

Without standby control

P-ch

N-ch

R

G

Digital input

• CMOS level Hysteresis input

Without standby control

P-ch

N-ch

R

H

Digital input

• CMOS level output

P-ch

N-ch

Digital output

L

14

DS07-16301-6E

MB91101 Series

■ HANDLING DEVICES

1. Preventing Latchup

In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over

rating across VCC and VSS may cause latchup.

This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the

device. Make sure to prevent the voltage from exceeding the maximum rating.

Take care that the analog power supply (AVCC, AVRH) and the analog input do not exceed the digital power

supply (VCC) when the analog power supply turned on or off.

2. Treatment of Unused Pins

Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.

3. External Reset Input

It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly.

4. Remarks for External Clock Operation

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock

to X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin

stops at “H” output in stop mode).

And it can be used to supply only to X0 pin with 5 V power supply at 12.5 MHz and less than.

• Using an external clock

X0

X1

MB91101 Series

Using an external clock (normal)

Note: Stop mode (oscillation stop mode) can not be used.

X0

Open

X1

MB91101 Series

Using an external clock (can be used at 12.5 MHz and less than.)

(5 V power supply only)

DS07-16301-6E

15

MB91101 Series

5. Power Supply Pins

When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside

of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,

to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and

to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND.

It is preferred to connect VCC and VSS of the MB91101 Series to power supply with minimal impedance

possible.

It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 μF between VCC

and VSS at a position as close as possible to the MB91101 Series.

The MB91101 Series has an internal regulator. When using with 5 V power supply, supply 5 V to VCC5 pin

and make sure to connect about 0.1 μF bypass capacitor to VCC3 pin for regulator. And another 3 V power

supply is needed for the A/D convertor. When using with 3 V power supply, connect both VCC5 pin and VCC3

pin to the 3 V power supply.

• Connecting to a power supply

[Using with 3 V power supply]

[Using with 5 V power supply]

3 V

5 V

VCC3

V 5

CC

VCC3

V 5

CC

AV^CC

AVRH

AV^SS

3 V

AV^CC

AVRH

AV^SS

About

0.1 μF

VSS

GND

6. Crystal Oscillator Circuit

Noises around X0 and X1 pins may cause the malfunction of the MB91101 Series. In designing the PC

board, layout X0 and X1 pins, crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding

as close as possible.

It is strongly recommended to design PC board so that X1 and X0 pins are surrounded by grounding area

for stable operation.

7. Turning-on Sequence of A/D Converter Power Supply and Analog Input

Make sure to turn on the digital power supply (VCC) before turning on the A/D converter (AVCC, AVRH) and

applying voltage to analog input (AN0 to AN3).

Make sure to turn off digital power supply after power supply to A/D converters and analog inputs have been

switched off. (There are no such limitations in turning on power supplies. Analog and digital power supplies

may be turned on simultaneously.) Make sure that AVRH never exceeds AV^CCwhen turning on/off power

supplies.

8. Fluctuation of Power Supply Voltage

Warranty range for normal operation against fluctuation of power supply voltage VCC is as given in rating.

However, sudden fluctuation of power supply voltage within the warranty range may cause malfunctions. It

is recommended to make every effort to stabilize the power supply voltage to IC. It is also recommended

that by controlling power supply as a reference of stabilizing, VCC ripple fluctuation (P-P value) at the com-

mercial frequency (50 Hz to

60 Hz) should be less than 10% of the standard VCC value and the transient regulation should be less than

0.1 V/ms at instantaneous deviation like turning off the power supply.

9. Mode Setting Pins (MD0 to MD2)

Connect mode setting pins (MD0 to MD2) directly to VCC or VSS.

Arrange each mode setting pin and VCC or VSS patterns on the printed circuit board as close as possible and

make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises.

16

DS07-16301-6E

MB91101 Series

10. Internal DC Regulator

Internal DC regulator stops in stop mode. When the regulator stops owing to the increase of inner leakage

current (ICCH) in stop mode, malfunction caused by noise or any troubles about power supply in normal

operation, the internal 3 V power supply voltage may decrease less than the warranty range for normal

operation. So when using the internal regulator and stop mode with 5 V power supply, never fail to support

externally so that 3 V power supply voltage might not decrease. However, even in such a case, the internal

regulator can be restarted by inputting the reset procedure. (In this case, set the reset to “L” level within the

oscillation stabilizing waiting time.)

• Using STOP mode with 5 V power supply

5 V

VCC5

3.6 kΩ

V^CC3

6.8 kΩ

0.1 μF

approx.

V^SS

11. Pin Condition at Turning on the Power Supply

The pin condition at turning on the power supply is unstable. The circuit starts being initialized after turning

on the power supply and then starting oscillation and then the operation of the internal regulator becomes

stable. So it takes about 42 ms for the pin to be initialized from the oscillation starting at the source oscillation

12.5 MHz. Take care that the pin condition may be output condition at initial unstable condition.

(With the MB91101A, however, initalization can be achieved in less than about 42 ms after turning on the

internal power supply by maintaining the RST pin at "L" level.)

12. Source Oscillation Input at Turning on the Power Supply

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing

waiting.

13. Hardware Stand-by at Turning on the Power Supply

When turning on the power supply with the HST pin being set to “L” level, the hardware does not stand by.

However the HST pin becomes available after the reset cancellation, the HST pin must once be back to “H”

level.

14. Power on Reset

Make sure to make power on reset at turning on the power supply or returning on the power supply when

the power supply voltage is below the warranty range for normal operation.

15. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self oscillating circuit

evevn when there is no external oscillator or external clock input is stopped. Performance of this operation,

however, cannot be guaranteed.

16. Watchdog timer function

The watchdog timer supported by the FR family monitors the program that performs the reset delay operation

for a specified time. If the program hangs up and the reset delay operation is not performed, the watchdog

timer resets the CPU. Therefore, once the watchdog timer is enabled, operation continues until the CPU is

reset.

As an exception, a reset delay automatically occurs if the CPU stops program execution.

DS07-16301-6E

17

MB91101 Series

■ BLOCK DIAGRAM

FR CPU

RAM (2 Kbytes)

Bit search module

Instruction cache (1 Kbyte)

3

DREQ0 to

DREQ2

Bus converter

(Harvard↔Princeton)

3

DMA controller (DMAC)

(8 ch.)

DACK0 to

DACK2

EOP0 to

EOP2

Bus converter (32 bits↔16 bits)

16

25

D16 to D31

A00 to A24

RD

WR0, WR1

RDY

CLK

CS0 to CS5

BRQ

X0

X1

RST

HST

Clock control unit

(Watchdog timer)

2

6

Bus controller

4

INT0 to INT3

NMI

BGRNT

Interrupt control unit

4

AN0 to AN3

AV^CC

RAS0

RAS1

CS0L

CS0H

CS1L

CS1H

DW0

AVSS /AVRL

AVRH

ATG

10-bit A/D converter

(4 ch.)

DRAM controller

DW1

Reload timer (3 ch.)

Port 0 to port B

Port

3

SI0 to SI2

SO0 to SO2

SC0 to SC2

UART (3 ch.)

(Baud rate timer)

Other pins

MD0 to MD2, P20 to P27, P60 to P67,

P80 to P82, P85, PA1 to PA6,

PB0 to PB7, PE0 to PE7, PF0 to PF7,

V

CC3, VCC5, VSS

4

OCPA0 to OCPA3

TRG0 to TRG3

PWM timer (4 ch.)

Note: Pins are display for functions (Actually some pins are multiplexer).

When using REALOS, time control should be done by using external interrupt or inner timer.

18

DS07-16301-6E

MB91101 Series

■ CPU CORE

1. Memory Space

The FR family has a logical address space of 4 Gbytes (2³²addesses) and the CPU linearly accesses the

memory space.

• Memory space

Address

External ROM/external bus mode

I/O area

0000 0000

H

Direct addressing area

See “ I/O MAP”

0000 0400

H

■

I/O area

0000 0800

0000 1000

0000 1800

H

Access inhibited

Embedded RAM

H

Access inhibited

0001 0000

H

External area

FFFF FFFF

H

• Direct addressing area

The following areas on the memory space are assigned to direct addressing area for I/O. In these areas,

an address can be specified in a direct operand of a code.

Direct areas consists of the following areas dependent on accessible data sizes.

Byte data access:

Half word data access: 000H to 1FFH

Word data access: 000H to 3FFH

000^Hto 0FFH

DS07-16301-6E

19

MB91101 Series

2. Registers

The FR family has two types of registers; dedicated registers embedded on the CPU and general-purpose

registers on memory.

• Dedicated registers

Program counter (PC):

Program status (PS):

32-bit length, indicates the location of the instruction to be executed.

32-bit length, register for storing register pointer or condition codes

Table base register (TBR): Holds top address of vector table used in EIT (Exceptional/Interrupt/Trap)

processing.

Return pointer (RP):

Holds address to resume operation after returning from a subroutine.

System stack pointer (SSP): Indicates system stack space.

User's stack pointer (USP): Indicates user’s stack space.

Multiplication/division result register (MDH/MDL): 32-bit length, register for multiplication/division

Initial value

32 bits

Indeterminate

XXXX XXXXH

PC

Program counter

Program status

PS

000F FC00H

XXXX XXXXH

0000 0000 H

XXXX XXXXH

Table base register

Return pointer

TBR

RP

Indeterminate

System stack pointer

User’s stack pointer

SSP

USP

MDH

MDL

XXXX XXXXH

Multiplication/division result

register

Indeterminate

• Program status (PS)

The PS register is for holding program status and consists of a condition code register (CCR), a system

condition code register (SCR) and an interrupt level mask register (ILM).

31 to 21 20

19

18

17

16 15 to 11 10

D1

9

8

T

7

6

5

4

I

3

2

Z

1

0

PS

—

ILM4 ILM3 ILM2 ILM1 ILM0

ILM

—

D0

—

S

N

V

C

SCR

CCR

20

DS07-16301-6E

MB91101 Series

• Condition code register (CCR)

S-flag: Specifies a stack pointer used as R15.

I-flag: Controls user interrupt request enable/disable.

N-flag: Indicates sign bit when division result is assumed to be in the 2’s complement format.

Z-flag: Indicates whether or not the result of division was “0”.

V-flag: Assumes the operand used in calculation in the 2’s complement format and indicates whether or

not overflow has occurred.

C-flag: Indicates if a carry or borrow from the MSB has occurred.

• System condition code register (SCR)

T-flag: Specifies whether or not to enable step trace trap.

• Interrupt level mask register (ILM)

ILM4 to ILM0:Register for holding interrupt level mask value. The value held by this register is used as a

level mask. When an interrupt request issued to the CPU is higher than the level held by

ILM, the interrupt request is accepted.

ILM4

ILM3

ILM2

ILM1

ILM0

Interrupt level

High-low

0

High

:

0

1

0

1

0

1

15

:

1

31

Low

DS07-16301-6E

21

MB91101 Series

■ GENERAL-PURPOSE REGISTERS

R0toR15aregeneral-purposeregistersembeddedontheCPU. Theseregistersfunctionsasanaccumulator

and a memory access pointer (field for indicating address).

• Register bank structure

32 bits

Initial value

XXXX XXXX^H

R0

R1

:

R12

R13

R14

R15

AC (accumulator)

FP (frame pointer)

SP (stack pointer)

XXXX XXXX^H

0000 0000H

Of the above 16 registers, following registers have special functions. To support the special functions, part

of the instruction set has been sophisticated to have enhanced functions.

R13: Virtual accumulator (AC)

R14: Frame pointer (FP)

R15: Stack pointer (SP)

Upon reset, values in R0 to R14 are not fixed. Value in R15 is initialized to be 0000 0000^H(SSP value).

22

DS07-16301-6E

MB91101 Series

■ SETTING MODE

1. Pin

• Mode setting pins and modes

Mode setting pins

Reset vector

access area

External data

bus width

Mode name

Bus mode

MD2 MD1 MD0

0

1

0

1

External vector mode 0

External

—

8 bits

16 bits

—

External ROM/external

bus mode

External vector mode 1

1

0

—

Inhibited

1

Internal vector mode

—

Internal

—

(Mode register) Single-chip mode*

Inhibited

—

*: The MB91101 Series does not support single-chip mode.

2. Registers

• Mode setting registers (MODR) and modes

Address

Initial value

Access

W

0000 07FFH

M1

M0

XXXX XXXX^B

*

Bus mode setting bits

W :Write only

X :Indeterminate

* :Always write “0” except for M1 and M0.

• Bus mode setting bits and functions

M1

0

M0

0

Functions

Remarks

Single-chip mode

Internal ROM/external bus mode

0

1

0

External ROM/external bus mode

—

1

Inhibited

Note: Because of not having internal ROM, the MB91101 Series allows “10^B” setting value only.

DS07-16301-6E

23

MB91101 Series

■ I/O MAP

Address Abbreviation

Register name

(Reserved)

Read/write

Initial value

0000^H

0001H PDR2

Port 2 data register

R/W

XXXXXXXXB

0002H

to

0004H

(Reserved)

0005^HPDR6

0006H

Port 6 data register

R/W

XXXXXXXXB

0007H

0008H PDRB

0009H PDRA

000AH

Port B data register

Port A data register

R/W

XXXXXXXXB

_ XXXXXX _B

(Reserved)

000B^HPDR8

Port 8 data register

R/W

_ _ X _ _ XXXB

000CH

to

0011H

0012^HPDRE

0013H PDRF

Port E data register

Port F data register

R/W

XXXXXXXXB

0014H

to

(Reserved)

001BH

001C^HSSR0

Serial status register 0

R/W

0 0 0 0 1 _ 0 0B

XXXXXXXXB

001DH SIDR0/SODR0

001EH SCR0

Serial input register 0/serial output register 0

Serial control register 0

0 0 0 0 0 1 0 0B

0 0 _ _ 0 _ 0 0B

0 0 0 0 1 _ 0 0B

XXXXXXXXB

001FH SMR0

Serial mode register 0

0020H SSR1

Serial status register 1

0021H SIDR1/SODR1

0022H SCR1

Serial input register 1/serial output register 1

Serial control register 1

0 0 0 0 0 1 0 0B

0 0 _ _ 0 _ 0 0B

0 0 0 0 1 _ 0 0B

XXXXXXXXB

0023H SMR2

Serial mode register 1

0024H SSR2

Serial status register 2

0025H SIDR2/SODR2

0026H SCR2

Serial input register 2/serial output register 2

Serial control register 2

0 0 0 0 0 1 0 0B

0 0 _ _ 0 _ 0 0B

(Continued)

0027H SMR2

Serial mode register 2

24

DS07-16301-6E

MB91101 Series

Address Abbreviation

Register name

16-bit reload register ch. 0

Read/write

Initial value

XXXXXXXXB

0028^H

TMRLR0

0029H

W

002AH

TMR0

002BH

16-bit timer register ch. 0

R

002CH

002DH

(Reserved)

002EH

_ _ _ _ 0 0 0 0B

0 0 0 0 0 0 0 0B

XXXXXXXXB

16-bit reload timer control status register

ch. 0

TMCSR0

002FH

R/W

W

0030H

TMRLR1

0031H

16-bit reload register ch. 1

16-bit timer register ch. 1

(Reserved)

0032H

TMR1

0033H

R

0034H

0035H

0036H

_ _ _ _ 0 0 0 0B

0 0 0 0 0 0 0 0B

_ _ _ _ _ _ XXB

XXXXXXXXB

0 0 0 0 0 0 0 0B

XXXXXXXXB

16-bit reload timer control status register

ch. 1

TMCSR1

0037H

R/W

R

0038H

ADCR

0039H

A/D converter data register

A/D converter control status register

16-bit reload register ch. 2

16-bit timer register ch. 2

(Reserved)

003AH

ADCS

003BH

R/W

W

003CH

TMRLR2

003DH

003EH

TMR2

003FH

R

0040H

0041^H

0042H

_ _ _ _ 0 0 0 0B

0 0 0 0 0 0 0 0B

16-bit reload timer control status register

ch. 2

TMCSR2

0043H

R/W

0044H

to

(Reserved)

0077H

(Continued)

DS07-16301-6E

25

MB91101 Series

Address Abbreviation

Register name

Read/write

Initial value

0 0 0 0 0 0 0 0B

0078H

UTIM0/UTIMR0 U-TIMER register ch. 0/reload register ch. 0

R/W

0079H

007AH

(Reserved)

007BH UTIMC0

007CH

U-TIMER control register ch. 0

R/W

0 _ _ 0 0 0 0 1B

0 0 0 0 0 0 0 0B

UTIM1/UTIMR1 U-TIMER register ch. 1/reload register ch. 1

007DH

007EH

(Reserved)

007FH UTIMC1

0080H

U-TIMER control register ch. 1

R/W

0 _ _ 0 0 0 0 1B

0 0 0 0 0 0 0 0B

UTIM2/UTIMR2 U-TIMER register ch. 2/reload register ch. 2

0081H

0082H

(Reserved)

0083^HUTIMC2

U-TIMER control register ch. 2

(Reserved)

R/W

0 _ _ 0 0 0 0 1B

0084H

to

0093H

0094^HEIRR

0095H ENIR

External interrupt cause register

Interrupt enable register

R/W

0 0 0 0 0 0 0 0B

0096H

to

(Reserved)

0098H

External interrupt request level setting regis-

ter

0099^HELVR

R/W

0 0 0 0 0 0 0 0B

009AH

to

(Reserved)

00D1H

00D2^HDDRE

00D3H DDRF

Port E data direction register

Port F data direction register

W

0 0 0 0 0 0 0 0B

00D4H

to

(Reserved)

00DBH

00DC^H

GCN1

00DDH

0 0 1 1 0 0 1 0B

0 0 0 1 0 0 0 0B

General control register 1

R/W

00DEH

(Reserved)

00DF^HGCN2

General control register 2

0 0 0 0 0 0 0 0B

(Continued)

26

DS07-16301-6E

MB91101 Series

Address Abbreviation

Register name

Ch. 0 timer register

Read/write

Initial value

1 1 1 1 1 1 1 1B

XXXXXXXXB

0 0 0 0 0 0 0 _B

0 0 0 0 0 0 0 0B

1 1 1 1 1 1 1 1B

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 _B

0 0 0 0 0 0 0 0B

1 1 1 1 1 1 1 1B

XXXXXXXXB

0 0 0 0 0 0 0 _B

0 0 0 0 0 0 0 0B

1 1 1 1 1 1 1 1B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

0 0 0 0 0 0 0 _B

00E0H

PTMR0

00E1H

R

00E2H

PCSR0

00E3H

Ch. 0 cycle setting register

Ch. 0 duty setting register

W

00E4H

PDUT0

00E5H

00E6H PCNH0

00E7H PCNL0

Ch. 0 control status register H

Ch. 0 control status register L

R/W

00E8H

PTMR1

00E9H

Ch. 1 timer register

R

W

00EAH

PCSR1

00EBH

Ch. 1 cycle setting register

Ch. 1 duty setting register

00ECH

PDUT1

00EDH

00EEH PCNH1

00EFH PCNL1

Ch. 1 control status register H

Ch. 1 control status register L

R/W

00F0H

PTMR2

00F1H

Ch. 2 timer register

R

W

00F2H

PCSR2

00F3H

Ch. 2 cycle setting register

Ch. 2 duty setting register

00F4H

PDUT2

00F5H

00F6H PCNH2

00F7H PCNL2

Ch. 2 control status register H

Ch. 2 control status register L

R/W

00F8H

PTMR3

00F9H

Ch. 3 timer register

R

W

00FAH

PCSR3

00FBH

Ch. 3 cycle setting register

Ch. 3 duty setting register

00FCH

PDUT3

00FDH

00FEH PCNH3

00FFH PCNL3

Ch. 3 control status register H

Ch. 3 control status register L

R/W

0 0 0 0 0 0 0 0B

(Continued)

DS07-16301-6E

27

MB91101 Series

Address Abbreviation

Register name

(Reserved)

Read/write

Initial value

0100H

to

01FFH

0200H

0201H

XXXXXXXXB

DPDP

DMAC parameter descriptor pointer

DMAC control status register

R/W

0202H

0203H

0204H

0205H

0206H

0207H

0208H

0209H

020AH

020BH

XXXXXXXXB

X 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

XXXXXXXX^B

DACSR

DATCR

XXXX 0 0 0 0B

DMAC pin control register

020CH

to

(Reserved)

03E3H

03E4^H

03E5H

03E6H

03E7H

_ _ _ _ _ _ _ _^B

_ _ _ _ _ _ _ _B

_ _ 0 0 0 0 0 0B

ICHCR

Instruction cache control register

R/W

03E8H

to

(Reserved)

03EFH

03F0^H

03F1H

03F2H

03F3H

03F4H

03F5H

03F6H

03F7H

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

BSD0

BSD1

Bit search module 0-detection data register

W

Bit search module 1-detection data register

R/W

XXXXXXXXB

(Continued)

28

DS07-16301-6E

MB91101 Series

Address Abbreviation

Register name

Read/write

Initial value

XXXXXXXXB

03F8H

03F9H

BSDC

03FAH

XXXXXXXXB

Bit search module transition-detection data

register

W

XXXXXXXXB

03FBH

03FCH

XXXXXXXXB

03FDH

BSRR

03FEH

XXXXXXXXB

Bit search module detection result register

R

XXXXXXXXB

03FFH

XXXXXXXXB

0400H ICR00

0401H ICR01

0402H ICR02

0403H ICR03

0404H ICR04

0405H ICR05

0406H ICR06

0407H ICR07

0408H ICR08

0409H ICR09

040AH ICR10

040BH ICR11

040CH ICR12

040DH ICR13

040EH ICR14

040FH ICR15

0410H ICR16

0411H ICR17

0412H ICR18

0413H ICR19

0414H ICR20

0415H ICR21

0416H ICR22

Interrupt control register 0

Interrupt control register 1

Interrupt control register 2

Interrupt control register 3

Interrupt control register 4

Interrupt control register 5

Interrupt control register 6

Interrupt control register 7

Interrupt control register 8

Interrupt control register 9

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

Interrupt control register 16

Interrupt control register 17

Interrupt control register 18

Interrupt control register 19

Interrupt control register 20

Interrupt control register 21

Interrupt control register 22

R/W

_ _ _ 1 1 1 1 1B

(Continued)

DS07-16301-6E

29

MB91101 Series

Address Abbreviation

Register name

Read/write

R/W

Initial value

0417^HICR23

0418H ICR24

0419H ICR25

041AH ICR26

041BH ICR27

041CH ICR28

041DH ICR29

041EH ICR30

041FH ICR31

042FH ICR47

0430H DICR

Interrupt control register 23

Interrupt control register 24

Interrupt control register 25

Interrupt control register 26

Interrupt control register 27

Interrupt control register 28

Interrupt control register 29

Interrupt control register 30

Interrupt control register 31

Interrupt control register 47

Delayed interrupt control register

_ _ _ 1 1 1 1 1B

_ _ _ _ _ _ _ 0B

R/W

Hold request cancel request level setting reg-

ister

0431H HRCL

R/W

_ _ _ 1 1 1 1 1B

0432H

to

(Reserved)

047FH

Reset cause register/

watchdog peripheral control register

0480^HRSRR/WTCR

R/W

1 XXXX _ 0 0B

0481H STCR

0482H PDRR

0483H CTBR

0484H GCR

0485H WPR

0486H

Standby control register

R/W

W

0 0 0 1 1 1 _ _B

_ _ _ _ 0 0 0 0B

XXXXXXXXB

DMA controller request squelch register

Timebase timer clear register

Gear control register

R/W

W

1 1 0 0 1 1 _ 1B

XXXXXXXXB

Watchdog reset occurrence postpone register

(Reserved)

0487^H

0488H PCTR

PLL control register

R/W

W

0 0 _ _ 0 _ _ _B

0 0 0 0 0 0 0 0B

0489H

to

0600H

(Reserved)

Port 2 data direction register

(Reserved)

0601^HDDR2

0602H

to

0604^H

0605^HDDR6

0606H

Port 6 data direction register

(Reserved)

W

0 0 0 0 0 0 0 0B

0607^H

(Continued)

30

DS07-16301-6E

MB91101 Series

Address Abbreviation

0608^HDDRB

0609H DDRA

060AH

Register name

Port B data direction register

Port A data direction register

Read/write

Initial value

0 0 0 0 0 0 0 0B

_ 0 0 0 0 0 0 _B

W

(Reserved)

060BH DDR8

Port 8 data direction register

W

_ _ 0 _ _ 0 0 0B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 1 0B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 1 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 1 0 0B

0 0 0 0 0 0 0 0B

0 0 0 0 0 1 0 1B

0 0 0 0 0 0 0 0B

_ _ _ 0 0 1 1 1B

0 _ _ 0 0 0 0 0B

0 0 0 0 0 0 0 0B

0 _ _ 0 0 0 0 0B

0 0 0 0 0 0 0 0B

_ _ XXXXXX^B

060CH

ASR1

060DH

Area select register 1

060EH

AMR1

060FH

Area mask register 1

Area select register 2

Area mask register 2

Area select register 3

Area mask register 3

Area select register 4

Area mask register 4

Area select register 5

Area mask register 5

W

0610H

ASR2

0611H

0612H

AMR2

0613H

0614H

ASR3

0615H

0616H

AMR3

0617H

0618H

ASR4

0619H

061AH

AMR4

061BH

061CH

ASR5

061DH

061EH

AMR5

061FH

0620H AMD0

0621H AMD1

0622H AMD32

0623H AMD4

0624H AMD5

0625H DSCR

Area mode register 0

Area mode register 1

Area mode register 32

Area mode register 4

Area mode register 5

DRAM signal control register

R/W

W

0626H

RFCR

0627H

Refresh control register

R/W

0 0 _ _ _ 0 0 0B

(Continued)

DS07-16301-6E

31

MB91101 Series

(Continued)

Address Abbreviation

Register name

External pin control register 0

(Reserved)

Read/write

Initial value

_ _ _ _ 1 1 0 0B

_ 1 1 1 1 1 1 1B

0628H

EPCR0

W

0629H

062AH

062BH EPCR1

External pin control register 1

W

1 1 1 1 1 1 1 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 _B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 _B

062CH

DMCR4

062DH

DRAM control register 4

R/W

062EH

DMCR5

062FH

DRAM control register 5

R/W

0630H

to

(Reserved)

07FDH

07FE^HLER

Little endian register

Mode register

W

_ _ _ _ _ 0 0 0B

XXXXXXXXB

07FFH MODR

Note : Do not use (reserved).

32

DS07-16301-6E

MB91101 Series

■ INTERRUPT CAUSES, INTERRUPT VECTORS

AND INTERRUPT CONTROL REGISTER ALLOCATIONS

Interrupt number

Interrupt level

Register

TBR default

address

Interrupt causes

Decimal Hexadecimal

Offset

3FC^H

3F8H

3F4H

3F0H

3ECH

3E8H

3E4H

3E0H

3DCH

3D8H

3D4H

3D0H

3CCH

3C8H

3C4H

3C0H

3BCH

3B8H

3B4H

3B0H

3ACH

3A8H

3A4H

3A0H

39CH

398H

394H

390H

38CH

388H

384H

380H

Reset

0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

—

000FFFFCH

000FFFF8H

000FFFF4H

000FFFF0H

000FFFECH

000FFFE8H

000FFFE4H

000FFFE0H

000FFFDCH

000FFFD8H

000FFFD4H

000FFFD0H

000FFFCCH

000FFFC8H

000FFFC4H

000FFFC0H

000FFFBCH

000FFFB8H

000FFFB4H

000FFFB0H

000FFFACH

000FFFA8H

000FFFA4H

000FFFA0H

000FFF9CH

000FFF98H

000FFF94H

000FFF90H

000FFF8CH

000FFF88H

000FFF84H

000FFF80H

System reserved

1

System reserved

2

—

System reserved

3

—

System reserved

4

—

System reserved

5

—

System reserved

6

—

System reserved

7

—

System reserved

8

—

System reserved

9

—

System reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

—

System reserved

—

System reserved

—

System reserved

—

Exception for undefined instruction

NMI request

—

FH fixed

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

UART0 receive complete

UART1 receive complete

UART2 receive complete

UART0 transmit complete

UART1 transmit complete

UART2 transmit complete

DMAC0 (complete, error)

DMAC1 (complete, error)

DMAC2 (complete, error)

DMAC3 (complete, error)

DMAC4 (complete, error)

DMAC5 (complete, error)

(Continued)

DS07-16301-6E

33

MB91101 Series

Interrupt number

Interrupt level

TBR default

address

Interrupt causes

Decimal Hexadecimal

Register

Offset

37C^H

378H

DMAC6 (complete, error)

DMAC7 (complete, error)

32

33

20

21

ICR16

ICR17

000FFF7CH

000FFF78H

A/D converter (successive approx-

imation conversion type)

34

22

ICR18

374H

000FFF74H

16-bit reload timer 0

16-bit reload timer 1

16-bit reload timer 2

PWM 0

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

370H

36CH

368H

364H

360H

35CH

358H

354H

350H

34CH

348H

344H

340H

33CH

338H

334H

330H

32CH

328H

324H

320H

31CH

318H

314H

310H

30CH

308H

304H

300H

000FFF70H

000FFF6CH

000FFF68H

000FFF64H

000FFF60H

000FFF5CH

000FFF58H

000FFF54H

000FFF50H

000FFF4CH

000FFF48H

000FFF44H

000FFF40H

000FFF3CH

000FFF38H

000FFF34H

000FFF30H

000FFF2CH

000FFF28H

000FFF24H

000FFF20H

000FFF1CH

000FFF18H

000FFF14H

000FFF10H

000FFF0CH

000FFF08H

000FFF04H

000FFF00H

(Continued)

PWM 1

PWM 2

PWM 3

U-TIMER 0

U-TIMER 1

U-TIMER 2

System reserved

Delayed interrupt cause bit

34

DS07-16301-6E

MB91101 Series

(Continued)

Interrupt causes

Interrupt number

Interrupt level

TBR default

address

Decimal Hexadecimal Register

Offset

2FC^H

2F8H

System reserved (used in REALOS*)

64

65

40

41

—

000FFEFCH

000FFEF8H

66

to

42

to

2F4H

to

000FFEF4H

to

Used in INT instructions

—

255

FF

000H

000FFC00H

*: REALOS/FR uses interrupt number 0x40 and 0x41 for system code.

DS07-16301-6E

35

MB91101 Series

■ PERIPHERAL RESOURCES

1. I/O Ports

There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register

(DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit

on the register corresponds to an external pin. In port registers input/output register of the port configures

input/outputfunctionoftheport, while correspondingbit(pin)configuresinput/outputfunctionindatadirection

registers. Bit “0” specifies input and “1” specifies output.

•For input (DDR = “0”) setting;

PDR reading operation: reads level of corresponding external pin.

PDR writing operation: writes setting value to PDR.

•For output (DDR = “1”) setting;

PDR reading operation: reads PDR value.

PDR writing operation: outputs PDR value to corresponding external pin.

•Block diagram

Resource input

0

1

PDR read

0

1

PDR

(Port data register)

Resource output

Resource output enable

DDR

(Data direction register)

36

DS07-16301-6E

MB91101 Series

• Port data register

Address

000001^H

Initial value

bit 7

bit 0

(R/W)

XXXXXXXX^B

XXXXXXXXB

- - X - - XXXB

PDR2

PDR6

PDR8

PDRA

PDRB

PDRE

PDRF

000005H

00000BH

000009H

000008H

000012H

000013H

- XXXXXX -

B

XXXXXXXXB

( ) :Access

R/W :Readable and writable

:Indeterminate

X

• Data direction register

Address

bit 7

Initial value

00000000B

bit 0

(W)

000601^H

000605H

00060BH

000609H

000608H

0000D2H

0000D3H

DDR2

DDR6

DDR8

DDRA

DDRB

DDRE

DDRF

00000000B

- - 0 - - 0 0 0B

- 000000 -B

00000000B

(W)

( ) :Access

W :Write only

– :Unused

DS07-16301-6E

37

MB91101 Series

2. DMA Controller (DMAC)

The DMA controller is a module embedded in FR family devices, and performs DMA (direct memory access)

transfer.

DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to

enhanced performance of the system.

• 8 channels

• Mode: single/block transfer, burst transfer and continuous transfer: 3 kinds of transfer

• Transfer all through the area

• Max 65536 of transfer cycles

• Interrupt function right after the transfer

• Selectable for address transfer increase/decrease by the software

• External transfer request input pin, external transfer request accept output pin, external transfer complete

output pin: three pins for each

• Block diagram

3

5

3

Edge/level

detection circuit

DREQ0 to DREQ2

DACK0 to DACK2

EOP0 to EOP2

Interrupt request

3

8

Sequencer

Internal resource

Transfer request

Data buffer

Switcher

DPDP

DACSR

DATCR

Mode

BLK DEC

BLK

DMACT

SADR

DADR

INC / DEC

38

DS07-16301-6E

MB91101 Series

• Registers (DMAC internal registers)

Address

bit 31

bit 16

bit 0

Initial value

XXXXXXXXB

00000200^H

00000201H

00000202H

00000203H

XXXXXXXXB

(R/W)

DPDP

XXXXXXXXB

X0000000B

00000000B

00000204H

00000205H

00000206H

00000207H

00000000B

(R/W)

DACSR

DATCR

00000000B

XXXXXXXXB

00000208H

00000209H

0000020AH

0000020BH

XXXX0000B

(R/W)

( ) :Access

R/W:Readable and writable

:Indeterminate

X

• Registers (DMA descriptor)

Address

bit 31

bit 0

DMA

ch.0

DPDP + 0^H

Descriptor

DMA

ch.1

DPDP + 0CH

DPDP + 54H

Descriptor

DMA

ch.7

Descriptor

DS07-16301-6E

39

MB91101 Series

3. UART

The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK

synchronous communication, and it has the following features.

The MB91101 Series consists of 3 channels of UART.

• Full-duplex double buffer

• Both a synchronous (start-stop system) communication and CLK synchronous communication are avail-

able.

• Supporting multi-processor mode

• Perfect programmable baud rate

Any baud rate can be set by internal timer (refer to section “4. U-TIMER”).

• Any baud rate can be set by external clock.

• Error checking function (parity, framing and overrun)

• Transfer signal: NRZ code

• Enable DMA transfer/start by interrupt.

40

DS07-16301-6E

MB91101 Series

• Block diagram

Control signals

Receive interrupt

(to CPU)

SC (clock)

Transmit interrupt

(to CPU)

Transmit clock

From U-TIMER

Clock select

circuit

Receive clock

External clock

SC

Receive control circuit

Transmit control circuit

Start bit detect

circuit

Transmit start

circuit

SI

(receive data)

Receive bit counter

Transmit bit counter

Receive parity

counter

Transmit parity

counter

SO (transmit data)

Transmit shifter

Receive status

judge circuit

Receive shifter

Receive

complete

Transmit

start

Receive error

generate signal

for DMA

SODR

SIDR

(to DMAC)

R-bus

MD1

MD0

PEN

P

PE

ORE

SMR

register

SCR

register

SBL

CL

A/D

REC

RXE

TXE

SSR

register

FRE

RDRF

TDRE

CS0

SCKE

SOE

RIE

TIE

Control signals

DS07-16301-6E

41

MB91101 Series

• Register configuration

Address

bit 15

Initial value

00000100B

bit 8

bit 0

(R/W)

0000001E^H

00000022H

00000026H

0000001FH

00000023H

00000027H

0000001CH

00000020H

00000024H

0000001DH

00000021H

00000002H

SCR0

SCR1

SCR2

00000100B

00 - - 0 - 00B

00001 - 00B

XXXXXXXXB

SMR0

SMR1

SMR2

SSR0

SSR1

SSR2

SIDR0/SODR0

SIDR1/SIDR1

SIDR2/SIDR2

( ) :Access

R/W :Readable and writable

–

:Unused

X

:Indeterminate

42

DS07-16301-6E

MB91101 Series

4. U-TIMER (16-bit Timer for UART Baud Rate Generation)

The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency

and reload value of U-TIMER allows flexible setting of baud rate.

The U-TIMER operates as an interval timer by using interrupt issued on counter underflow.

The MB91101 Series has 3 channel U-TIMER embedded on the chip. An interval of up to 2¹⁶× φ can be

counted.

• Block diagram

bit 15

bit 0

UTIMR (reload register)

Load

bit 15

bit 0

UTIM ( U-TIMER register)

Underflow

Clock

φ

Control

(Peripheral clock)

f.f.

To UART

• Register configuration

Address

bit 15

Initial value

bit 0

00000078H

00000079H

0000007CH

0000007DH

00000080H

00000081H

(R/W)

00000000B

UTIM0/UTIMR0

UTIM1/UTIMR1

UTIM2/UTIMR2

00000000B

0000007BH

0000007FH

00000083H

0 - - 00001B

UTIMC0

UTIMC1

UTIMC2

0 - - 00001B

( ) :Access

R/W :Readable and writable

–

:Unused

DS07-16301-6E

43

MB91101 Series

5. PWM Timer

The PWM timer can output high accurate PWM waveform efficiently.

The MB91101 Series has internal 4-channel PWM timers, and has the following features.

• Each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for scyde setting, a 16-

bit compare resister with a buffer for duty setting, and a pin controller.

• The count clock of a 16-bit down counter can be selected from the following four internal clocks.

Internal clock φ, φ/4, φ/16, φ/64

• The counter value can be initialized “FFFF^H” by the resetting or the counter borrow.

• PWM output (for each channel)

• Register description

• Block diagram (general construction)

16-bit reload timer

ch.0

TRG input

PWM timer ch.0

PWM0

PWM1

16-bit reload timer

ch.1

TRG input

PWM timer ch.1

General control

register 1

(cause selection)

4

General control

register 2

TRG input

PWM timer ch.2

PWM2

PWM3

TRG input

PWM timer ch.3

External TRG0 to TRG3

44

DS07-16301-6E

MB91101 Series

• Block diagram (for one channel)

PCSR

PDUT

Prescaler

1 / 1

cmp

1 / 4

1 / 16

1 / 64

ck

Load

16-bit down counter

Start

Borrow

PPG mask

S

Q

PWM output

Peripheral clock

R

Reverse bit

Enable

IRQ

Edge detect

Soft trigger

TRG input

DS07-16301-6E

45

MB91101 Series

• Register configuration

bit 8

bit 15

bit 0

Initial value

Address

000000DCH

000000DDH

0 01 10 01 0B

0 00 10 00 0B

(R/W)

GCN1

0 00 00 00 0B

000000DFH

(R/W)

(R)

GCN2

PCNL0

PCNL1

PCNL2

000000E0H

000000E1H

1 11 11 11 1B

PTMR0

PCSR0

PDUT0

000000E2H

000000E3H

XXXXXXXXB

(W)

XXXXXXXXB

000000E4H

000000E5H

(R/W)

0 00 00 00 - B

000000E6H

000000E7H

PCNH0

PCNH1

PCNH2

0 00 00 00 0B

(R/W)

(R)

1 11 11 11 1B

000000E8H

000000E9H

PTMR1

PCSR1

PDUT1

(W)

XXXXXXXXB

000000EAH

000000EBH

(W)

XXXXXXXXB

000000ECH

000000EDH

(R/W)

0 00 00 00 -B

0 00 00 00 0B

000000EEH

000000EFH

(R/W)

(R)

000000F0H

000000F1H

1 11 11 11 1B

PTMR2

PCSR2

PDUT2

XXXXXXXXB

(W)

000000F2H

000000F3H

XXXXXXXXB

(W)

000000F4H

000000F5H

(R/W)

0 00 00 00 - B

0 00 00 00 0B

000000F6H

000000F7H

(R/W)

(R)

1 11 11 11 1B

000000F8H

000000F9H

PTMR3

PCSR3

PDUT3

XXXXXXXXB

(W)

000000FAH

000000FBH

XXXXXXXXB

000000FCH

000000FDH

(R/W)

0 00 00 00 - B

000000FEH

000000FFH

PCNH3

0 00 00 00 0B

PCNL3

( )

:Access

R/W :Readable and writable

R

W

–

:Read only

:Write only

:Unused

X

:Indeterminate

46

DS07-16301-6E

MB91101 Series

6. 16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating

internal count clock and control registers.

Internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock).

The DMA transfer can be started by the interruption.

The MB91101 Series consists of 3 channels of the 16-bit reload timer.

• Block diagram

16

16-bit reload register

8

Reload

RELD

16

16-bit down counter

UF

OUTE

OUTL

INTE

UF

2

OUT

CTL.

GATE

2

IRQ

CSL1

Clock selector

CNTE

TRG

CSL0

2

Trigger

IN CTL.

EXCK

PWM (ch.0, ch.1)

A/D (ch.2)

3

Prescaler

clear

1

3

5

MOD2

MOD1

MOD0

Internal clock

3

DS07-16301-6E

47

MB91101 Series

• Register configuration

Address

bit 15

bit 0

Initial value

0000002EH

0000002FH

- - - - 0 00 0B

00 00 00 00B

(R/W)

(R)

TMCSR0

TMCSR1

TMCSR2

TMR0

00000036H

00000037H

- - - - 0 00 0B

00 00 00 00B

00000042H

00000043H

- - - - 0 00 0B

00 00 00 00B

0000002AH

0000002BH

XXXXXXXXB

00000032H

00000033H

(R)

XXXXXXXXB

TMR1

0000003EH

0000003FH

XXXXXXXXB

(R)

TMR2

00000028H

00000029H

XXXXXXXXB

(W)

TMRLR0

TMRLR1

TMRLR2

00000030H

00000031H

XXXXXXXXB

0000003CH

0000003DH

( ) :Access

R/W :Readable and writable

R

W

–

:Read only

:Write only

:Unused

X

:Indeterminate

48

DS07-16301-6E

MB91101 Series

7. Bit Search Module

The bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers

and returns locations of the transitions.

• Block diagram

Input latch

Address

decoder

Detection

mode

Single-detection data recovery

Bit search circuit

Search result

• Register configuration

Address

bit 31

bit 16

BSD0

bit 0

Initial value

000003F0H

000003F1H

000003F2H

000003F3H

XXXXXXXXB

(W)

XXXXXXXXB

000003F4H

000003F5H

000003F6H

000003F7H

(R/W)

BSD1

BSDC

BSRR

XXXXXXXXB

000003F8H

000003F9H

000003FAH

000003FBH

(W)

(R)

XXXXXXXXB

000003FCH

000003FEH

000003FDH

000003FFH

( )

:Access

R/W :Readable and writable

R

W

X

:Read only

:Write only

:Indeterminate

DS07-16301-6E

49

MB91101 Series

8. 10-bit A/D Converter (Successive Approximation Conversion Type)

The A/D converter is the module which converts an analog input voltage to a digital value, and it has following

features.

• Minimum converting time: 5.6 μs/ch. (system clock: 25 MHz)

• Internal sample and hold circuit

• Resolution: 10 bits

• Analog input can be selected from 4 channels by program.

Single convert mode: 1 channel is selected and converted.

Scan convert mode: Converting continuous channels. Maximum 4 channels are programmable.

Continuous convert mode: Converting the specified channel repeatedly.

Stop convert mode: After converting one channel then stop and wait till next activation synchronizing at

the beginning of conversion can be performed.

• DMA transfer operation is available by interruption.

• Operating factor can be selected from the software, the external trigger (falling edge), and 16-bit reload

timer (rising edge).

• Block diagram

AV^CC

AVR

AVSS

Internal voltage generator

MPX

AN0

AN1

AN2

AN3

Successive approximation

register

Comparator

Sample & hold circuit

Data register (ADCR)

A/D control register (ADCS)

Trigger start

ATG

Timer start

TIM2

Operating clock

Prescaler

(Output signal of 16-bit reload timer ch.2)

φ

(Peripheral clock)

50

DS07-16301-6E

MB91101 Series

• Register configuration

Initial value

Address

bit 0

bit 15

0000003AH

0000003BH

0 00 00 00B

(R/W)

(R)

ADCS

ADCR

- - - - - - XXB

XXXXXXXXB

00000038H

00000039H

( )

:Access

R/W :Readable and writable

R

–

:Read only

:Unused

X

:Indeterminate

DS07-16301-6E

51

MB91101 Series

9. Interrupt Controller

The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.

• Block diagram

6

INT0*²

OR

IM

*

Priority judgment

5

LEVEL4 to

LEVEL0*⁴

NMI

NMI processing

4

HLDREQ

cancel

HLDCAN*³

request

Level judgment

Level

vector

generation

ICR00

RI00*⁷

6

VCT5 to

•

VCT0*⁵

Vector judgment

•

ICR47

7

*

RI47

DLYI*¹

(DLYIRQ)

R-bus

*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11.

Delayed Interrupt Module” for details).

*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.

*3: HLDCAN is a bus release request signal for bus masters other than CPU.

*4: LEVEL4 to LEVEL0 indicate interrupt level outputs.

*5: VCT5 to VCT0 indicate interrupt vector outputs.

*6: IM is an interrupt mask signal.

*7: RI00 to RI47 are interrupt request signals.

52

DS07-16301-6E

MB91101 Series

• Register configuration

Address

bit 7

Initial value

Address

bit 7

bit 0

Initial value

bit 0

00000400H

00000401H

00000402H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

00000411H

00000412H

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR47

HRCL

DICR

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

00000413H

00000414H

00000415H

00000416H

00000417H

00000418H

00000419H

0000041AH

0000041BH

0000041CH

0000041DH

0000041EH

0000041FH

0000042FH

00000431H

00000430H

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - 11111 B (R/W)

- - - 11111 ^B(R/W)

- - - - - - - 0 ^B(R/W)

00000403H

00000404H

00000405H

00000406H

00000407H

00000408H

00000409H

0000040AH

0000040BH

0000040CH

0000040DH

0000040EH

0000040FH

00000410H

( )

R/W :Readable and writable

:Unused

:Access

–

DS07-16301-6E

53

MB91101 Series

10. External Interrupt/NMI Control Block

The external interrupt/NMI control block controls external interrupt request signals input to NMI pin and INT0

to INT3 pins.

Detecting levels can be selected from “H”, “L”, rising edge and falling edge (except NMI pin).

• Block diagram

8

Interrupt enable register

9

8

5

INT0 to INT3

NMI

Interrupt

request

Gate

Cause F/F

Edge detection circuit

Interrupt cause register

Request level setting register

• Register configuration

Address

Initial value

bit 15

bit 8

bit 0

00000095H

00000094H

00000099H

ENIR

ELVR

00000000 B (R/W)

00000000 ^B(R/W)

00000000 B (R/W)

EIRR

( )

:Access

R/W :Readable and writable

54

DS07-16301-6E

MB91101 Series

11. Delayed Interrupt Module

Delayed interrupt module is a module which generates a interrupt for changing a task. By using this delayed

interrupt module, an interrupt request to CPU can be generated/canceled by the software.

Refer to the section “9. Interrupt Controller” for delayed interrupt module block diagram.

• Register configuration

Address

bit 7

bit 0

Initial value

- - - - - - - 0B

(R/W)

00000430^H

DICR

( ) :Access

R/W :Readable and writable

–

:Unused

DS07-16301-6E

55

MB91101 Series

12. Clock Generation Block (Low-power consumption mechanism)

The clock generation block is a module which undertakes the following functions.

• CPU clock generation (including gear function)

• Peripheral clock generation (including gear function)

• Reset generation and cause hold

• Standby function (including hardware standby)

• DMA request suppressed

• PLL (multiplier circuit) embedded

• Block diagram

[Gear control block]

Gear control register (GCR)

CPU gear

Peripheral

gear

PCTR register

CPU clock

X0

X1

PLL

1/2

Oscillator

circuit

Internal bus clock

Internal clock

generation

circuit

External bus clock

Peripheral

DMA clock

Internal

peripheral clock

[Stop/sleep control block]

Internal

interrupt request

Internal reset

Standby control

register (STCR)

STOP state

Status

SLEEP state

CPU hold request

Internal reset

CPU hold enable

HST pin

transition

control circuit

Reset

generation

F/F

[DMA prohibit circuit]

DMA

request

DMA request prohibit

register (PDRR)

[Reset cause circuit]

Power on reset

RST pin

Reset cause register (RSRR)

[Watchdog control block]

Watchdog reset generation

postpone register (WPR)

Watchdog reset

postpone register

Timebase timer clear

register (CTBR)

Timebase timer

Count clock

56

DS07-16301-6E

MB91101 Series

• Register configuration

bit 15

bit 8

Address

Initial value

bit 0

(R/W)

(W)

00000480H

00000481H

1XXXX - 00B

00 01 11 - -B

- - - - 0 00 0B

XXXXXXXXB

11 00 11 - 1B

XXXXXXXXB

00 - - 0 - - -B

RSRR/WTCR

STCR

CTBR

WPR

00000482H

00000483H

00000484H

00000485H

00000488H

PDRR

GCR

(R/W)

(W)

(R/W)

PCTR

( )

:Access

R/W :Readable and writable

W

–

:Write only

:Unused

X

:Indeterminate

DS07-16301-6E

57

MB91101 Series

13. External Bus Interface

The external bus interface controls the interface between the device and the external memory and also the

external I/O, and has the following features.

• 25-bit (32 Mbytes) address output

• 6 independent banks owing to the chip select function.

Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.

Total 32 Mbytes × 6 area setting is available by the address pin and the chip select pin.

• 8/16-bit bus width setting are available for every chip select area.

• Programmable automatic memory wait (Max for 7 cycles) can be inserted.

• DRAM interface support

Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)

Single CAS DRAM

Hyper DRAM

2 banks independent control (RAS, CAS, etc. control signals)

DRAM select is available from 2CAS/1WE and 1CAS/2WE.

Hi-speed page mode supported

CBR/self refresh supported

Programmable waveform

• Unused address/data pin can be used for I/O port.

• Little endian mode supported

• Clock doubler: Internal bus 50 MHz, external bus 25 MHz operation

58

DS07-16301-6E

MB91101 Series

• Block diagram

A-OUT

Address bus

32

Data bus

32

External data bus

Write buffer

Read buffer

Switch

MUX

DATA BLOCK

ADDRESS BLOCK

+1 or +2

External address bus

Inpage

Shifter

Address buffer

6

8

ASR

AMR

CS0 to CS5

Comparator

RAS0, RAS1

CS0L, CS1L

CS0H, CS1H

DW0, DW1

DRAM control

Underflow

DMCR

Refresh counter

To TBT

3

4

RD

WR0, WR1

External pin control block

All blocks control

Registers and control

BRQ

BGRNT

CLK

RDY

DS07-16301-6E

59

MB91101 Series

• Register configuration

bit 31

bit 16

Address

bit 0

Initial value

0000060CH

0000060DH

00000000B

00000001B

(W)

ASR1

ASR2

ASR3

ASR4

0000060EH

0000060FH

00000000B

AMR1

00000610H

00000611H

00000000B

00000010B

00000000B

00000011B

(W)

00000612H

00000613H

AMR2

AMR3

00000614H

00000615H

00000000B

00000616H

00000617H

00000000B

00000100B

00000618H

00000619H

(W)

00000000B

0000061AH

0000061BH

(W)

AMR4

AMR5

00000000B

00000101B

0000061CH

0000061DH

ASR5

00000000B

0000061EH

0000061FH

(R/W)

- - - 00111B

0 - - 00000B

00000000B

0 - - 00000B

00000000B

00000620H

AMD0

AMD1

00000621H

00000622H

AMD32

00000623H

00000624H

00000625H

AMD4

AMD5

(W)

DSCR

- - XXXXXXB

00 - - - 000B

(R/W)

00000626H

00000627H

RFCR

(W)

- - - - 1100B

-1111111B

00000628H

00000629H

EPCR0

(W)

0000062BH

11111111B

EPCR1

0000062CH

0000062DH

(R/W)

00000000B

DMCR4

0000000 -

B

(R/W)

0000062EH

0000062FH

00000000B

0000000 -

DMCR5

LER

B

000007FEH

(W)

- - - - - 000B

XXXXXXXXB

000007FFH

MODR

( )

:Access

R/W :Readable and writable

W

–

:Write only

:Unused

X

:Indeterminate

60

DS07-16301-6E

MB91101 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Rating

Symbol

Unit

Remarks

Parameter

Min

VSS – 0.3

—

Max

VSS + 6.5

—

V^CC5

V^CC3

V^CC5

VCC3

AV^CC

AVRH

VIA

V

At 5 V power supply

At 3 V power supply

Power supply

voltage

VCC3 – 0.3

VSS – 0.3

V^SS– 0.3

VSS – 0.3

—

VSS + 6.5

VSS + 3.6

AVCC + 0.3

VCC5 + 0.3

10

V

*1

V

*1

*2

Analog supply voltage

V

Analog reference voltage

Analog pin input voltage

V

Input voltage

V^I

V

Output voltage

V^O

V

“L” level maximum output current

“L” level average output current

“L” level maximum total output current

“L” level average total output current

“H” level maximum output current

“H” level average output current

IOL

mA

mW

°C

*3

*4

I^OLAV

ΣI^OL

ΣI^OLAV

I^OH

—

4

—

100

—

50

*5

*3

*4

—

–10

I^OHAV

—

–4

“H” level maximum total output current ΣI^OH

—

–50

“H” level average total output current

Power consumption

ΣI^OHAV

—

–20

*5

PD

—

500

Operating temperature

Storage temperature

TA

–40

+70

Tstg

–55

+150

*1: V^CC5 must not be less than VSS – 0.3 V.

*2: Care must be taken that AV^CCand AVRH do not exceed VCC5 + 0.3 V and VSS + 3.6 V.

Also care must be taken that AVRH does not exceed AVCC.

*3: Maximum output current is a peak current value measured at a corresponding pin.

*4: Average output current is an average current for a 100 ms period at a corresponding pin.

*5: Average total output current is an average current for a 100 ms period for all corresponding pins.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

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MB91101 Series

2. Recommended Operating Conditions

(1) At 5 V operation (4.5 V to 5.5 V)

(VSS = AVSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min

Max

V^CC5

4.5

5.5

V

Normal operation

Retaining the RAM state in

stop mode

Power supply voltage

VCC5

*1

V^CC3

AV^CC

AVRH

T^A

—

VSS + 3.6

AVCC

+70

V

*2

Analog supply voltage

Analog reference voltage

Operating temperature

Smoothing capacitor

VSS + 2.7

VSS – 0.3

–40

V

°C

μF

C^S

0.1

1.0

VCC3 pin, *3

*1: At V^CC5, the RAM state holding is not warranted in stop mode.

*2: VCC3 is used for the bypass capacitor pin.

*3: Use the ceramic capacitor or the capacitor whose frequency characteristic is equivalent to that of the ceramic

capacitor.

And select the larger capacity bypass capacitor to connect to the power supply (V^CC5) than CS.

(2) At 3 V operation (2.7 V to 3.6 V)

(V^SS= AVSS = 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min

Max

V^CC5

2.7

3.6

V

Normal operation

Retaining the RAM state in

stop mode

Power supply voltage

2.7

3.6

VCC3

AVCC

AVRH

T^A

2.7

VSS + 2.7

AV^SS

3.6

VSS + 3.6

AVCC

V

*

Analog power supply voltage

Analog reference voltage

Operating temperature

V

–40

+70

°C

*: Connect to V^CC5 for the power supply pin.

• Connecting to a power supply

Using with 3 V power supply

Using with 5 V power supply

3 V

5 V

VCC3

VCC5

AV^CC

AVRH

AV^SS

VSS

VCC3

VCC5

AVCC

AVRH

AVSS

VSS

3 V

About

0.1 μF

GND

62

DS07-16301-6E

MB91101 Series

· Normal operation warranty range

V^CC(V)

Normal operation warranty range (TA = −40°C to +70°C)

Net masked area are f^CPP.

Power supply at 5 V

5.5

4.5

3.0 V 0.3 V

Power supply at 3 V

3.6

3.3

3.0

2.7

3.3 V 0.3 V

f^CP/fCPP

(MHz)

0

0.625

25

Internal clock

40

50

· External/internal clock setting available range

f^CP/fCPP

(MHz)

fCP

50

CPU

40

PLL system (4 multiplication)

fCPP

25

20

Peripheral

Divide-by-2 system

12.5

5

0

f^C

(MHz)

0

10 12.5

25

50

External clock

Self-oscillation

Source oscillating input clock

Notes: • When using PLL, the external clock must be used between 10.0 MHz and 12.5 MHz.

• PLL oscillation stabilizing period > 100 μs

• The gear setting of internal clock must be within above ranges.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact

their representatives beforehand.

DS07-16301-6E

63

MB91101 Series

3. DC Characteristics

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Sym-

bol

Parameter

Pin name

Condition

Unit Remarks

Min

Typ

Max

Input pin ex-

cept for hyster-

esis input

V^IH

—

0.65 × V^CC3

—

VCC5 + 0.3

V

*

HST, NMI,

RST,

PA1 to PA6,

PB0 to PB7,

PE0 to PE7,

PF0 to PF7

“H” level input

voltage

Hysteresis

input *

V^IHS

—

0.8 × V^CC3

—

VCC5 + 0.3

Inputotherthan

following sym-

bols

V^IL

V^SS– 0.3

0.25 × VCC3

*

HST, NMI,

RST,

PA1 to PA6,

PB0 to PB7,

PE0 to PE7,

PF0 to PF7

“L” level input

voltage

Hysteresis

input *

V^ILS

V^SS– 0.3

—

0.2 × VCC3

D16 to D31,

A00 to A24,

P60 to P67,

P80 to P82,

P85,

PA1 to PA6,

PB0 to PB7,

PE0 to PE7,

PF0 to PF7

CS0, WR0

VCC5 = 4.5 V

I^OH= – 4.0 mA

V^CC5– 0.5

—

“H” level output

voltage

V^OH

V

V^CC5 = VCC3 = 2.7 V

IOH = – 4.0 mA

V^CC5– 0.8

—

D16 to D31,

A00 to A24,

P60 to P67,

P80 to P82,

P85,

PA1 to PA6,

PB0 to PB7,

PE0 to PE7,

PF0 to PF7

CS0, WR0

VCC5 = 4.5 V

I^OL= 4.0 mA

—

0.4

0.6

“L” level output

voltage

V^OL

V

V^CC5 = VCC3 = 2.7 V

I^OL= 4.0 mA

D16 to D31,

A00 to A23,

P80 to P82,

P85,

PA1 to PA6,

PB0 to PB7,

PE0 to PE7,

PF0 to PF7

V^CC5 = 5.5 V

0.45 V < VI < VCC

–5

—

+5

Input leakage

current

(High-Z output

leakage current)

I^LI

μA

V^CC5 = VCC3 = 3.6 V

0.45 V < VI < VCC

(Continued)

64

DS07-16301-6E

MB91101 Series

(Continued)

Value

Sym-

bol

Parameter

Pin name

Condition

VCC5 = 5.5 V

Unit Remarks

Min

Typ

Max

25

50

100

VI = 0.45 V

Pull-up

resistance

R^PULLRST

kΩ

VCC5 = VCC3 = 3.6 V

VI = 0.45 V

60

—

125

75

40

10

250

100

60

FC = 12.5 MHz

VCC5 = 5.5 V

(4 multipli-

cation)

Operationat

50 MHz

I^CC

VCC5, VCC3

mA

FC = 12.5 MHz

VCC5 = VCC3 = 3.6 V

F^C= 12.5 MHz

VCC5 = 5.5 V

Power supply

current

I^CCS

VCC5, VCC3

mA Sleep mode

F^C= 12.5 MHz

VCC5 = VCC3 = 3.6 V

60

TA = +25°C

V^CC5 = 5.5 V

100

I^CCH

μA Stop mode

T^A= +25°C

VCC5 = VCC3 = 3.6 V

ExceptforVCC5,

VCC3, AVCC,

AVSS, VSS

Input

capacitance

CIN

—

10

—

pF

*: V^CC3 = 3.3 0.2 V (internal regulator output voltage) when using 5 V power supply, VCC3 = power supply

voltage when using 3 V power supply (internal regulator unused).

DS07-16301-6E

65

MB91101 Series

4. AC Characteristics

Measurement Conditions

• V^CC5 = 5.0 V 10%

Parameter

Value

Typ

2.4

Symbol

V^IH

Unit

Remarks

Min

—

Max

—

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

V

V^IL

—

0.8

—

VOH

V^OL

—

2.4

—

0.8

—

Input

Output

VCC

VIH

VOH

VIL

VOL

0.0 V

• V^CC5 = VCC3 = 2.7 V to 3.6 V

Parameter

Value

Typ

Symbol

Unit

Remarks

Min

—

Max

—

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

V^IH

1/2 × VCC3

V

VIL

—

V^OH

VOL

—

Input

Output

VCC

VIH

VIL

VOH

VOL

0.0 V

• Load conditions

Output pin

C = 50 pF

(VCC = 5.0V 10%)

66

DS07-16301-6E

MB91101 Series

• Load capacitance - Delay characteristics (Output delay with reference to the internal)

35

30

25

20

15

10

5

5 V Fall

3 V Rise

5 V Rise

3 V Fall

0

20

40 50 60

80

100

120

Load capacitance (pF)

DS07-16301-6E

67

MB91101 Series

(1) Clock Timing Rating

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

name

Symbol

Condition

Unit

Remarks

Parameter

Min

Max

f^C

X0, X1 When using PLL

10

12.5

MHz

Self-oscillation

X0, X1

fC

10

25

Clock frequency

(divide-by-2 input)

External clock

X0, X1

f^C

MHz

(divide-by-2 input)

tC

X0, X1 When using PLL

80

40

100

ns

Clock cycle time

X0, X1

—

Input to X0

only, when

using 5 V

P^WH,

PWL

X0, X1

25

—

ns

Input clock pulse width

power supply

—

P^WH,

PWL

Input to X0,

X1

X0, X1

10

—

8

ns

Input clock rising/falling

time

tCR,

tCF

(tCR + tCF)

fCP

—

CPU system

Bus system

Peripheral system 0.625*¹

0.625*¹

50

25*²

MHz

ns

Internal operating clock

frequency

f^CPB

fCPP

tCP

25

CPU system

20

40*²

40

1600*¹

Internal operating clock

cycle time

t^CPB

tCPP

Bus system

ns

Peripheral system

ns

*1: These values are for a minimum clock of 10 MHz input to X0, a divide-by-2 system of the source oscillation

and a 1/8 gear.

*2: Values when using the doubler and CPU operation at 50 MHz.

• Clock timing rating measurement conditions

tC

0.8 VCC5

0.2 V^CC5

PWH

PWL

tCR

tCF

68

DS07-16301-6E

MB91101 Series

(2) Clock Output Timing

Parameter

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol Pin name Condition

Unit Remarks

Min

Max

t^CYC

CLK

—

tCP

—

ns *1

ns

Cycle time

Using the

doubler

tCYC

tCPB

—

CLK ↑ → CLK ↓

CLK ↓ → CLK ↑

t^CHCL

CLK

1/2 × tCYC – 10 1/2 × tCYC + 10

ns *2

ns *3

—

tCLCH

t^CP, tCPB (internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”

*1: t^CYCis a frequency for 1 clock cycle including a gear cycle.

Use the doubler when CPU frequency is above 25 MHz.

*2: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,

respectively.

Min : (1 – n/2) × t^CYC– 10

Max : (1 – n/2) × tCYC + 10

Select a gear cycle of × 1 when using the doubler.

*3: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations with 1/2, 1/4, 1/8,

respectively.

Min : n/2 × t^CYC– 10

Max : n/2 × t^CYC+ 10

Select a gear cycle of × 1 when using the doubler.

tCYC

tCLCH

tCHCL

VOH

V^OH

CLK

VOL

DS07-16301-6E

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MB91101 Series

The relation between the input waveform of source oscillation and the output waveform of CLK pin for

configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows:

However, in this chart source oscillation input means X0 input clock.

tC

Source oscillation input

(when using the doubler)

(1) PLL system

(CHC bit of GCR set to “0”)

tCYC

(a) Gear × 1 CLK pin

CCK1/0: “00”

tC

Source oscillation input

(2) 2 dividing system

(CHC bit of GCR set to “1”)

(a) Gear × 1 CLK pin

tCYC

CCK1/0: “00”

tCYC

(b) Gear × 1/2 CLK pin

CCK1/0: “01”

(c) Gear × 1/4 CLK pin

tCYC

CCK1/0: “10”

(d) Gear × 1/8 CLK pin

tCYC

CCK1/0: “11”

70

DS07-16301-6E

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• Ceramic oscillator applications

Recommended circuit (2 contacts)

Recommended circuit (3 contacts)

X0

X1

X0

X1

*

C1

C1, C2 internally

connected.

C2

C1

C2

* : Murata Mfg. Co., Ltd.

• Discreet type

Oscillation frequency

Load capacitance

Power supply voltage

VCC5 [V]

Model

[MHz]

C¹= C2 [pF]

30

CSA

CST

CSA

CST

CSA

CST

CSA

CST

CSA

CST

CSA

CST

CSA

CST

MG

2.9 to 5.5

MGW

(30)

30

5.00 to 6.30

6.31 to 10.0

MG093

MGW093

MTZ

2.7 to 5.5

2.9 to 5.5

2.7 to 5.5

3.0 to 5.5

2.9 to 5.5

3.2 to 5.5

(30)

30

MTW

(30)

30

MTZ093

MTW093

MTZ

(30)

30

MTW

(30)

30

10.1 to 13.0

MTZ093

MTW093

MXZ040

MXW0C3

(30)

15

13.01 to 15.00

(15)

( ): C¹and C2 internally connected 3 contacts type.

DS07-16301-6E

71

MB91101 Series

(3) Reset/Hardware Standby Input Ratings

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol Pin name Condition

Unit Remarks

Parameter

Min

Max

—

Reset input time

Hardware standby input time

t^RSTL

RST

HST

tCP × 5

ns

—

tHSTL

—

t^CP(internal operating clock cycle time): Refer to “(1) Clock Timing Rating.”

tRSTL, tHSTL

RST

HST

0.2 VCC5

72

DS07-16301-6E

MB91101 Series

(4) Power on Supply Specifications (Power-on Reset)

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol Pin name

Condition

Unit Remarks

Parameter

Min

50

—

Max

—

t^R

tR

t^R

VCC

μs

ms

μs

*

VCC = 5.0 V

30

Power supply rising time

50

—

VCC = 3.0/3.3 V

—

18

ms

Repeated

operations

Power supply shut off time t^OFF

VCC

1

—

ms

t^C(clock cycle time): Refer to “(1) Clock Timing Rating.”

*: V^CC< 0.2 V before the power supply on

t^R

0.9 × VCC5

VCC

0.2 V

tOFF

Note: Sudden change in supply voltage during operation may initiate a power-on sequence.

To change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid

fluctuations in the supply voltage.

VCC

A voltage rising rate of 50 mV/ms or

less is recommended.

VSS

42 ms approx.

Regulator

VCC

Stabilizing time *

RST

0.2 × V^CC5

tRSTL + (tC × 2¹⁹)

t^RSTL: Reset input time

*: Reset cannot be done during regulator stabilizing time.

Note: Set RST pin to “L” level when turning on the device, at least the described above duration after the

supply voltage reaches Vcc is necessary before turning the RST to “H” level.

DS07-16301-6E

73

MB91101 Series

(5) Normal Bus Access Read/Write Operation

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min

Max

CLK,

CS0 to CS5

t^CHCSL

t^CHCSH

t^CHAV

—

15

ns

CS0 to CS5 delay time

CLK,

CS0 to CS5

—

15

CLK,

A24 to A00

Address delay time

Data delay time

CLK,

D31 to D16

tCHDV

tCLRL

CLK, RD

—

6

ns

RD delay time

t^CLRH

CLK,

WR0, WR1

—

t^CLWL

tCLWH

tAVDV

—

10

0

6

ns

WR0, WR1 delay time

CLK,

WR0, WR1

Valid address → valid data

input time

A24 to A00,

D31 to D16

3/2 × tCYC

*1

ns

– 25

*2

RD,

D31 to D16

RD ↓→ valid data input time tRLDV

tCYC – 10

ns *1

ns

RD,

D31 to D16

Data set up → RD ↑ time

RD ↑→ data hold time

tDSRH

tRHDX

—

RD,

D31 to D16

ns

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

*1: When bus timing is delayed by automatic wait insertion or RDY input, add (t^CYC× extended cycle number)

to this rating.

*2: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,

respectively.

Equation: (2 – n/2) × t^CYC– 25

74

DS07-16301-6E

MB91101 Series

BA2

BA1

tCYC

VOH

V^OH

VOH

CLK

VOL

tCHCSL

tCHCSH

VOH

CS0 to CS5

VOL

tCHAV

VOH

VOL

VOH

VOL

A24 to A00

tCLRL

tCLRH

VOH

RD

VOL

tRLDV

tRHDX

tAVDV

VIH

VIL

VIH

VIL

D31 to D16

WR0, WR1

Read

tDSRH

tCLWL

VOH

VOL

tCLWH

tCHDV

VOH

VOL

VOH

V^OL

D31 to D16

Write

DS07-16301-6E

75

MB91101 Series

(6) Ready Input Timing

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min

15

0

Max

—

RDY set up time → CLK ↓ t^RDYS

RDY, CLK

ns

—

CLK ↓→ RDY hold time

tRDYH

—

tCYC

CLK

VOH

VOL

tRDYH

tRDYS

RDY

When wait(s)

is inserted.

VIH

VIL

VIH

VIL

VIH

VIL

VIH

RDY

When no wait

is inserted.

VIL

76

DS07-16301-6E

MB91101 Series

(7) Hold Timing

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Min

Max

CLK,

t^CHBGL

—

6

ns

BGRNT

BGRNT delay time

CLK,

t^CHBGH

—

6

—

BGRNT

Pin floating → BGRNT ↓ time tXHAL

BGRNT ↑→ pin valid time

tCYC – 10

tCYC + 10

ns

tHAHV

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

Note : There is a delay time of more than 1 cycle from BRQ input to BGRNT change.

tCYC

VOH

CLK

BRQ

tCHBGH

tCHBGL

VOH

BGRNT

VOL

tXHAL

tHAHV

VOH

VOL

VOH

VOL

Each pin

High-Z

DS07-16301-6E

77

MB91101 Series

(8) Normal DRAM Mode Read/Write Cycle

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

RAS delay time

Min

—

Max

6

t^CLRAH

CLK, RAS0, RAS1

ns

tCHRAL

—

6

CLK, CS0H, CS0L,

CS1H, CS1L

t^CLCASL

tCLCASH

tCHRAV

t^CHCAV

—

6

ns

CAS delay time

CLK, CS0H, CS0L,

CS1H, CS1L

CLK,

A24 to A00

ROW address delay time

15

COLUMN address delay

time

CLK,

A24 to A00

—

tCHDWL

CLK, DW0, DW1

—

15

ns

DW delay time

t^CHDWH

CLK,

D31 to D16

Output data delay time

tCHDV1

t^RLDV

tCLDV

t^CADH

—

0

15

ns

RAS ↓→ valid data input

time

RAS0, RAS1,

D31 to D16

5/2× tCYC

*1

ns

– 16

*2

CAS ↓→ valid data input

time

CS0H, CS0L, CS1H,

CS1L, D31 to D16

tCYC – 17 ns *1

CS0H, CS0L, CS1H,

CS1L, D31 to D16

CAS ↑→ data hold time

—

ns

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

*1: When Q1 cycle or Q4 cycle is extended for 1 cycle, add t^CYCtime to this rating.

*2: Rating at a gear cycle of × 1.

When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equation with 1/2, 1/4, 1/8,

respectively.

Equation: (3 – n/2) × tCYC – 16

78

DS07-16301-6E

MB91101 Series

Q1

Q2

Q3

Q4

Q5

tCYC

VOH

CLK

VOL

VOH

RAS0

RAS1

VOL

tCLRAH

tCHRAL

tCLCASH

VOH

tCLCASH

CS0H

CS0L

CS1H

CS1L

VOL

tCHCAV

tCHRAV

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

ROW address

COLUMN address

A24 to A00

D31 to D16

tRLDV

tCADH

VIH

VIL

tCLDV

VIH

Read

VIL

DW0

DW1

VOH

VOL

tCHDWH

tCHDWL

VOH

VOL

VOH

VOL

Write

D31 to D16

tCHDV1

DS07-16301-6E

79

MB91101 Series

(9) Normal DRAM Mode Fast Page Read/Write Cycle

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

RAS delay time

Min

Max

t^CLRAH

CLK, RAS0, RAS1

—

6

ns

CLK, CS0H, CS0L,

CS1H, CS1L

tCLCASL

—

6

CAS delay time

CLK, CS0H, CS0L,

CS1H, CS1L

t^CLCASH

ns

COLUMN address delay

time

CLK,

A24 to A00

tCHCAV

tCHDWH

t^CHDV1

—

15

ns

—

DW delay time

CLK, DW0, DW1

CLK,

D31 to D16

Output data delay time

CAS ↓→ valid data input

CS0H,CS0L,CS1H,

CS1L,D31 to D16

t^CLDV

—

0

t^CYC– 17 ns

ns

*

time

CS0H,CS0L,CS1H,

CS1L, D31 to D16

CAS ↑→ data hold time

tCADH

—

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

*: When Q4 cycle is extended for 1 cycle, add t^CYCtime to this rating.

80

DS07-16301-6E

MB91101 Series

Q5

Q4

Q5

Q4

Q5

V^OH

VOH

VOL

CLK

VOL

tCLRAH

VOH

RAS0

RAS1

tCLCASL

tCLCASH

VOH

CS0H

CS0L

CS1H

CS1L

VOL

tCHCAV

VOH

VOL

VOH

VOL

VOH

VOL

A24 to A00

COLUMN address

tCLDV

VIH

tCADH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

D31 to D16

Read

V^IL

tCHDWH

VOH

DW0

DW1

tCHDV1

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

Write

D31 to D16

DS07-16301-6E

81

MB91101 Series

(10) Single DRAM Timing

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

RAS delay time

Min

Max

6

t^CLRAH2

CLK, RAS0, RAS1

—

ns

tCHRAL2

6

CLK, CS0H, CS0L,

CS1H, CS1L

t^CHCASL2

—

n/2 × tCYC ns

CAS delay time

CLK, CS0H, CS0L,

CS1H, CS1L

tCHCASH2

6

ns

CLK,

A24 to A00

ROW address delay time tCHRAV2

15

COLUMN address delay

time

CLK,

A24 to A00

t^CHCAV2

—

tCHDWL2

DW delay time

CLK, DW0, DW1

—

15

ns

t^CHDWH2

CLK,

D31 to D16

Output data delay time

tCHDV2

t^CLDV2

tCADH2

—

0

15

ns

CAS ↓→ Valid data input

time

CS0H, CS0L, CS1H,

CS1L, D31 to D16

(1–n/2)×

tCYC – 17

CS0H, CS0L, CS1H,

CS1L, D31 to D16

CAS ↑→ data hold time

—

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

82

DS07-16301-6E

MB91101 Series

tCYC

*1

Q1

Q2

Q3

V^OH

Q4S

CLK

VOH

V^OL

RAS0

RAS1

VOH

VOL

tCHRAL2

tCLRAH2

tCHCASL2

tCHCASH2

CS0H

CS0L

CS1H

CS1L

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

ROW address

COLUMN-0

COLUMN-1

COLUMN-2

A24 to A00

D31 to D16

tCHRAV2

tCHCAV2

tCADH2

tCLDV2

VIH

VIL

Read-0

Read-1

Read-2

VIL

DW0

DW1

VOH

VOL

tCHDWL2

tCHDWH2

*2

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

D31 to D16

Write-0

Write-2

Write-1

tCHDV2

*1: Q4S indicates Q4SR (Read) of Single DRAM cycle or Q4SW (Write) cycle.

*2: indicates the timing when the bus cycle begins from the high-speed page mode.

DS07-16301-6E

83

MB91101 Series

(11) Hyper DRAM Timing

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

RAS delay time

Min

—

Max

6

t^CLRAH3

CLK, RAS0, RAS1

ns

tCHRAL3

—

6

CLK, CS0H, CS0L,

CS1H, CS1L

t^CHCASL3

—

n/2 × tCYC ns

CAS delay time

CLK, CS0H, CS0L,

CS1H, CS1L

tCHCASH3

6

ns

CLK,

A24 to A00

ROW address delay time tCHRAV3

15

COLUMN address delay

time

CLK,

A24 to A00

t^CHCAV3

tCHRL3

CLK, RD

—

15

ns

—

RD delay time

t^CHRH3

tCLRL3

CLK, RD

t^CHDWL3

tCHDWH3

CLK, DW0, DW1

DW delay time

CLK,

D31 to D16

Output data delay time

tCHDV3

t^CLDV3

tCADH3

—

0

15

tCYC – 17

—

ns

CAS ↓→ valid data input

time

CS0H,CS0L,CS1H,

CS1L, D31 to D16

CS0H,CS0L,CS1H,

CS1L, D31 to D16

CAS ↓→ data hold time

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

84

DS07-16301-6E

MB91101 Series

tCYC

*1

Q1

Q2

Q3

V^OH

Q4H

CLK

VOH

V^OL

VOL

RAS0

RAS1

VOH

VOL

tCHRAL3

tCLRAH3

tCHCASL3

tCHCASH3

VOH

CS0H

CS0L

CS1H

CS1L

VOL

VOH

VOL

VOH

VOL

VOH

VOL

ROW address

COLUMN-0

COLUMN-1

COLUMN-2

A24 to A00

tCHRAV3

tCHCAV3

*2

VOL

RD

VOH

VOL

tCHRL3

tCLRL3

tCHRH3

tCLDV3

tCADH3

VIH

VIL

VIH

VIL

Read-0

Read-1

D31 to D16

DW0

DW1

V^OH

VOL

tCHDWL3

tCHDWH3

*2

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

VOH

VOL

D31 to D16

Write-0

Write-2

Write-1

tCHDV3

*1: Q4H indicates Q4HR (Read) of Hyper DRAM cycle or Q4HW (Write) cycle.

*2: indicates the timing when the bus cycle begins from the high-speed page mode.

DS07-16301-6E

85

MB91101 Series

(12) CBR Refresh

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min

—

Max

6

t^CLRAH

CLK, RAS0, RAS1

ns

RAS delay time

tCHRAL

—

6

CLK, CS0H, CS0L,

CS1H, CS1L

—

t^CLCASL

—

6

ns

CAS delay time

CLK, CS0H, CS0L,

CS1H, CS1L

tCLCASH

tCYC

R1

R2

R3

R4

VOH

CLK

VOL

VOH

RAS0

RAS1

VOL

tCHRAL

tCLRAH

CS0H

CS0L

CS1H

CS1L

VOH

tCLCASH

VOL

tCLCASL

DW0

DW1

86

DS07-16301-6E

MB91101 Series

(13) Self Refresh

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min

—

Max

6

t^CLRAH

CLK, RAS0, RAS1

ns

RAS delay time

tCHRAL

—

6

CLK, CS0H, CS0L,

CS1H, CS1L

—

t^CLCASL

—

6

ns

CAS delay time

CLK, CS0H, CS0L,

CS1H, CS1L

tCLCASH

tCYC

SR1

SR2

SR3

VOH

CLK

VOL

tCLRAH

VOH

tCHRAL

RAS0

RAS1

V^OL

CS0H

CS0L

CS1H

CS1L

VOH

VOL

tCLCASH

tCLCASL

DS07-16301-6E

87

MB91101 Series

(14) UART Timing

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol Pin name Condition

Unit Remarks

Parameter

Min

Max

Serial clock cycle time

SCLK ↓→ SCLK ↑

SCLK ↑→ SCLK ↓

t^SCYC

—

8 × t^CYCP

—

ns

tSCLCH

t^SCHCL

4 × tCYCP –10 4 × tCYCP +10 ns

Internal

shift clock

mode

SCLK ↓→ SOUT delay time tSLOV

–80

100

+80

ns

Valid SIN → SCLK ↑

tIVSH

—

SCLK ↑→ valid SIN hold

time

t^SHIX

—

60

—

ns

Serial clock “H” pulse width tSHSL

Serial clock “L” pulse width

SCLK ↓→ SOUT delay time t^SLOV

—

4 × tCYCP

—

ns

tSLSH

External

shift clock

mode

150

—

Valid SIN → SCLK ↑

t^IVSH

60

SCLK ↑→ valid SIN hold

time

tSHIX

—

60

—

ns

t^CYCP: A cycle time of peripheral system clock

Note : This rating is for AC characteristics in CLK synchronous mode.

• Internal shift clock mode

tSCYC

tSCLCH

tSCHCL

VOH

SCLK

VOL

tSLOV

VOH

VOL

SOUT

tIVSH

tSHIX

VIH

VIL

VIH

VIL

SIN

• External shift clock mode

tSLSH

tSHSL

VIH

SCLK

SOUT

VIL

tSLOV

VOH

VOL

tIVSH

tSHIX

VIH

VIL

VIH

VIL

SIN

88

DS07-16301-6E

MB91101 Series

(15) Trigger System Input Timing

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

Pin name

ATG

TRG0 to TRG3

Condition

Unit

Remarks

Parameter

Min

Max

t^TRGH,

tTRGL

A/D start trigger input time

5 × t^CYCP

—

ns

—

PWM external trigger input tTRGH,

time

5 × tCYCP

—

tTRGL

t^CYCP: A cycle time of peripheral system clock

tTRGH

tTRGL

VIH

ATG

VIL

TRG0 to TRG3

DS07-16301-6E

89

MB91101 Series

(16) DMA Controller Timing

(VCC5 = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = –40°C to +70°C)

Value

Symbol

DREQ input pulse width t^DRWH

Pin name

Condition

Unit Remarks

Parameter

Min

Max

DREQ0 to DREQ2

2 × tCYC

—

ns

CLK,

DACK0 to DACK2

t^CLDL

t^CLDH

t^CLEL

tCLEH

t^CHDL

t^CHDH

t^CHEL

tCHEH

—

6

DACK delay time

(Normal bus)

(Normal DRAM)

CLK,

DACK0 to DACK2

6

ns

CLK,

EOP0 to EOP2

6

EOP delay time

(Normal bus)

(Normal DRAM)

CLK,

EOP0 to EOP2

6

—

CLK,

DACK0 to DACK2

n/2 × tCYC

DACK delay time

(Single DRAM)

(Hyper DRAM)

CLK,

DACK0 to DACK2

6

n/2 × tCYC

6

CLK,

EOP0 to EOP2

EOP delay time

(Single DRAM)

(Hyper DRAM)

CLK,

EOP0 to EOP2

t^CYC(a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”

tCYC

VOH

CLK

VOL

V

OL

t

CLDL

t

CLDH

DACK0 to DACK2

EOP0 to EOP2

(Normal bus)

t

CLEL

t

CLEH

VOH

V

OL

(Normal DRAM)

DACK0 to DACK2

EOP0 to EOP2

(Single DRAM)

(Hyper DRAM)

VOH

V

tCHDL

t

CHEL

t

CHDH

t

DRWH

VIH

DREQ0 to DREQ2

90

DS07-16301-6E

MB91101 Series

5. A/D Converter Block Electrical Characteristics

(AVCC = 2.7 V to 3.6 V, AVSS = 0.0 V, AVRH = 2.7 V, TA = –40°C to +70°C)

Value

Symbol Pin name

Unit

Parameter

Min

—

Typ

10

—

Max

10

Resolution

Total error

—

bit

—

4.0

3.5

2.0

LSB

Linearity error

—

Differentiation linearity error

—

AVRL –

1.5 LSB

AVRL +

0.5 LSB

AVRL +

2.5 LSB

Zero transition voltage

V^OT

AN0 to AN3

V

AVRH –

4.5 LSB

AVRH –

1.5 LSB

AVRH +

0.5 LSB

Full-scale transition voltage

VFST

Conversion time

—

I^AIN

VAIN

—

5.6 *¹

—

0.1

—

10

μs

μA

V

Analog port input current

Analog input voltage

Reference voltage

AN0 to AN3

AVRH

—

AVSS

AV^SS

—

AVRH

AVCC

—

V

IA

AVCC

4

mA

μA

LSB

Power supply current

I^AH

IR

AVCC

—

5 *²

AVRH

—

200

—

Reference voltage supply current

IRH

—

AVRH

—

5 *²

4

Conversion variance between channels

*1: AV^CC= 2.7 V to 3.6 V

AN0 to AN3

—

*2: Current value for A/D converters not in operation, CPU stop mode (V^CC= AVCC = AVRH = 3.6 V)

Notes: • As the absolute value of AVRH decreases, relative error increases.

• Output impedance of external circuit of analog input under following conditions;

Output impedance of external circuit < 10 kΩ.

If output impedance of external circuit is too high, analog voltage sampling time may be too short for

accurate sampling (sampling time is 5.6 μs for a machine clock of 25 MHz).

• Analog input circuit

Sample and hold circuit

Analog input

C0

Comparator

RON1

R

ON2

RON3

RON4

C1

RON1 : 0.2 kΩ

RON2 : 1.4 kΩ

RON3 : 1.4 kΩ

RON4 : 0.2 kΩ

C

0

: 16.6 pF

: 4.0 pF

C1

Note: Listed values are for reference purposes only.

DS07-16301-6E

91

MB91101 Series

6. A/D Converter Glossary

• Resolution

The smallest change in analog voltage detected by A/D converter.

• Linearity error

A deviation of actual conversion characteristic from a line connecting the zero-traction point (between

“00 0000 0000” ↔ “00 0000 0001”) to the full-scale transition point (between “11 1111 1110” ↔ “11 1111

1111”).

• Differential linearity error

A deviation of a step voltage for changing the LSB of output code from ideal input voltage.

Linearity error

Differential linearity error

3FF

3FE

3FD

Ideal characteristic

Actual conversion

characteristic

N+1

N

{1 LSB

× (N – 1) + VOT}

Actual characteristic

VFST

(measured

value)

004

003

002

001

V^NT

(measured value)

Actual conversion

characteristic

N–1

N–2

V(N + 1)T

(measured value)

V^NT

(measured value)

Ideal characteristic

VOT (measured value)

Actual conversion characteristic

AVRL

AVRH

AVRL

AVRH

Analog input

VNT – {1 LSB

×

(N – 1) + VOT}

V(N + 1)T – VNT

Linearity error of

digital output N

Differential linearity error

of digital output N

=

[LSB]

– 1 [LSB]

1 LSB

VFST – VOT

1 LSB =

[V]

1022

V^OT: A voltage for causing transition of digital output from (000)

H

to (001)

H

V^FST: A voltage for causing transition of digital output from (3FE)

H

to (3FF)H

VNT: A voltage for causing transition of digital output from (N – 1) to N

92

DS07-16301-6E

MB91101 Series

• Total error

A difference between actual value and theoretical value. The overall error includes zero-transition error,

full-scale transition error and linearity error.

Total error

3FF

1.5 LSB’

3FE

Actual conversion

characteristic

3FD

{1 LSB’ × (N – 1)

+ 0.5 LSB’}

004

V^NT

(measured value)

003

Actual conversion

characteristic

002

Ideal characteristic

001

0.5 LSB’

AVRL

AVRH

Analog input

VNT – {1 LSB’ × (N – 1) + 0.5 LSB’}

=

Total error of digital output N

[LSB]

1 LSB'

AVRH – AVRL

1024

1 LSB’ (ideal value) =

[V]

VOT’ (ideal value) = AVRL + 0.5 LSB’ [V]

V^FST’ (ideal value) = AVRL – 1.5 LSB’ [V]

VNT: A voltage for causing transition of digital output from (N – 1) to N

DS07-16301-6E

93

MB91101 Series

■ REFERENCE DATA

(1) Operating frequency vs. ICC characteristics

Internal DC - DC regulator is not used (VCC5 = VCC3 = 3 V)

Internal DC - DC regulator is used (V^CC5 = 5 V)

90

80

70

60

50

40

30

20

10

0

(VCC)

80

3.6 V

4.5 V to 5.5 V

70

3.3 V

60

3.0 V

2.7 V

50

40

30

20

10

0

10

20

f (MHz)

30

40

50

0

10

20

f (MHz)

30

40

50

Operating conditions : Source oscillation 12.5 MHz (crystal), PLL is used (50 MHz, 25 MHz, 12.5 MHz)

Gear : CPU = 1/1, Peripherals = 1/1

(Doubler is used for 50MHz, Gear peripherals = 1/2)

(2) V^CCvs. ICC characteristics

Internal DC - DC regulator is not used (VCC5 = VCC3 = 3 V)

Icc (mA)

Internal DC - DC regulator is used (VCC5= 5 V)

CC (mA)

I

18

16

14

18

16

14

Gear : 1/1

Gear : 1/2

12

10

8

12

10

8

Gear : 1/4

Gear : 1/8

Gear : 1/4

Gear : 1/8

6

Gear : 1/8

(PLL : off)

4

Gear : 1/8

(PLL : off)

2

0

2

0

2.4 2.7

3.0

3.3 3.6

4.5

5.0

5.5

VCC (V)

Operating conditions : Source oscillation 12.5 MHz (crystal), divide-by-2 input, PLL : ON

Gear : CPU = Peripherals

94

DS07-16301-6E

MB91101 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

100-pin Plastic LQFP

(FPT-100P-M20)

MB91101APMC

MB91101APF

100-pin Plastic QFP

(FPT-100P-M06)

MB91101APF-G-JNE1

DS07-16301-6E

95

MB91101 Series

■ PACKAGE DIMENSIONS

100-pin plastic LQFP

Lead pitch

0.50 mm

14.0 mm × 14.0 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.70 mm Max

0.65 g

Code

(Reference)

P-LFQFP100-14×14-0.50

(FPT-100P-M20)

100-pin plastic LQFP

(FPT-100P-M20)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

16.00 0.20(.630 .008)SQ

*

14.00 0.10(.551 .004)SQ

75

51

76

50

0.08(.003)

Details of "A" part

1.50 ⁺–⁰⁰^.^.¹²⁰⁰.059 ⁺^–^.^.⁰⁰⁰⁰⁴⁸

(Mounting height)

INDEX

0.10 0.10

(.004 .004)

(Stand off)

100

26

0°~8°

"A"

0.50 0.20

(.020 .008)

0.25(.010)

1

25

0.60 0.15

(.024 .006)

0.50(.020)

0.20 0.05

(.008 .002)

0.145 0.055

(.006 .002)

M

0.08(.003)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

C

2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

96

DS07-16301-6E

MB91101 Series

(Continued)

100-pin plastic QFP

Lead pitch

0.65 mm

14.00 × 20.00 mm

Gullwing

Package width ×

package length

Lead shape

Sealing method

Mounting height

Plastic mold

3.35 mm MAX

P-QFP100-14×20-0.65

Code

(Reference)

(FPT-100P-M06)

100-pin plastic QFP

(FPT-100P-M06)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

23.90 0.40(.941 .016)

*

20.00 0.20(.787 .008)

80

51

81

50

0.10(.004)

17.90 0.40

(.705 .016)

*14.00 0.20

(.551 .008)

INDEX

Details of "A" part

100

31

0.25(.010)

3.00 ⁺^–0⁰^.^.²³⁰⁵

.118 ⁺^–.^.⁰⁰⁰¹⁸⁴

(Mounting height)

0~8°

1

30

0.65(.026)

0.32 0.05

(.013 .002)

0.17 0.06

(.007 .002)

M

0.13(.005)

0.25 0.20

(.010 .008)

(Stand off)

0.80 0.20

(.031 .008)

"A"

0.88 0.15

(.035 .006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2002-2010 FUJITSU SEMICONDUCTOR LIMITED F100008S-c-5-7

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

DS07-16301-6E

97

MB91101 Series

■ MAJOR CHANGES IN THIS EDITION

Page

Section

Change Results

■ ORDERING INFORMATION

Added the part number as follows.

MB91101APF-G-JNE1

95

The vertical lines marked in the left side of the page show the changes.

98

DS07-16301-6E

MB91101 Series

MEMO

DS07-16301-6E

99

MB91101 Series

FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,

Kohoku-ku Yokohama Kanagawa 222-0033, Japan

Tel: +81-45-415-5858

http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU SEMICONDUCTOR AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://us.fujitsu.com/micro/

FUJITSU SEMICONDUCTOR ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fujitsu.com/sg/services/micro/semiconductor/

Europe

FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fss/

FUJITSU SEMICONDUCTOR EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/semiconductor/

Korea

FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fsp/

FUJITSU SEMICONDUCTOR KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does

not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any

third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right

by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or

other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-

ing in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-

current levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations

of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB91101APMC
厂家：	FUJITSU
描述：	RISC Microcontroller, 32-Bit, FR30 CPU, 50MHz, CMOS, PQFP100, 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFP-100 时钟微控制器外围集成电路
文件：	总100页 (文件大小：2084K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB91101APMC [FUJITSU]

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