MB91191RPFF [FUJITSU]
32-bit Proprietary Microcontroller; 32位微控制器专用
| 型号： | MB91191RPFF |
| 厂家： | 
FUJITSU |
| 描述： | 32-bit Proprietary Microcontroller |
| 文件： | 总33页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16202-2E
32-bit Proprietary Microcontroller
CMOS
FR Family MB91191/192 Series
MB91191R/MB91192/MB91F191A/MB91F192
■ DESCRIPTION
The MB91191/192 series is a single-chip microcontroller using a 32-bit RISC-CPU (FR series) as its core. It
contains peripheral I/O resources suitable for software servo control in applications such as VTRs that require
high-speed CPU processing.
■ FEATURES
CPU
• 32-bit RISC (FR series) , load/store architecture, 5-stage pipeline
• General-purpose registers : 16 × 32-bit
• 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle
• Includes memory-to-memory transfer, bit manipulation, and barrel shift instructions :
Optimized for embedded applications
• Includes function entry/exit instructions and multiple-register load/store instructions :
Instruction set supports high level languages
• Register interlock function : For efficient assembly language coding
• Branch instructions with delay slots : Reduced overhead for branch operations
• Internal multiplier unit is supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupts (PC and PS saving) : 6 cycles, 16 priority levels
(Continued)
■ PACKAGE
Plastic, LQFP, 120-pin
Plastic, FLGA, 144-pin
(FPT-120P-M05)
(LGA-144P-M02)
MB91191/192 Series
Bus Interface
• 16-bit address output, 8/16-bit data input and output
• Basic bus cycle : 2 clock cycles
• Supports interfaces for various types of memory
• Multiplexed data/address input/output
• Automatic wait cycles : Between 0 and 7 wait cycles can be specified independently for each memory area
• Unused data/address pins can be configured as input/output ports
• Supports little endian mode
Bit Search Module
• Searches, starting from the MSB, for the position of the first 1/0 bit transition in a word. The operation is
performed in one cycle.
Serial I/O
• 3 channels with internal buffer RAM (automatic transfer of up to 128 bytes)
• Independent send and receive buffer mode (automatic transfer of up to 64 bytes)
A/D Converter (Successive Approximation Type)
• 10-bit × 16 channels
• Uses successive approximation conversion method (conversion time : 8.4 µs @ 20 MHz)
• Channel scan function
• Hardware and software conversion start functions
• Internal FIFO (Software conversion : 6 stages, Hardware conversion : 6 stages)
Timers
• 16-bit × 4 channels
• 16-bit timer/counter × 1 channel (with square wave output)
• 8/16-bit timer/counter × 1 channel (with square wave output)
FG input unit
• Incorporates capstan, drum, and reel input circuits
Capture unit
• Internal 24-bit free-run counter (Minimum resolution = 50 ns @ 20 MHz)
• Internal FIFO (Data : 21-bit × 8, Detection : 8-bit × 8)
Programmable pattern generator
• Internal RAM buffer (PPG0 : 256 bytes, PPG1 : 64 bytes)
• Output timing resolution : 800 ns @ 20 MHz
• Includes an A/D converter hardware start function
Realtime timing generator
• RTG : 3 circuits
• Output timing resolution : 400 ns or 800 ns selectable
• Timing output ports : 5 ports
PWM
• 12-bit PWM × 6 channels (rate, multi-type)
• Base frequency = 78.1 kHz or 39.0 kHz (@ 20 MHz) selectable
(Continued)
2
MB91191/192 Series
(Continued)
PWC
• 8-bit PWC × 1 channel (with mask input)
• Measurement resolution : 400 ns @ 20 MHz
General-purpose prescaler
• 10-bit prescaler × 1 channel (with square wave and pulse outputs)
• Dedicated internal oscillator circuit
• Includes load function driven by PPG output
Interrupt control
• External interrupts : 3 inputs
• Key input interrupt : 8 inputs
3
MB91191/192 Series
■ PIN ASSIGNMENT
(TOP VIEW)
PA0/AN-8/KEY0
PB7/AN-7
60
55
50
45
40
35
P93/PPG02
P94/PPG03
P80/PPG04
P81/PPG05
P82/PPG06
P83/PPG07
P84/PPG08
P85/PPG09
P86/PPG10
P87/PPG11
P40/PPG12
P41/PPG13
P42/PPG14
P43/PPG15
P44/PPG16
P45/PPG17
P46/PPG18
P47
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
AVDD
95
100
105
110
115
120
AVRH
AVSS
VSS
P17/RTG4
P16/RTG3
P15/RTG2
P14/RTG1
P13/RTG0
P12/EC5/INT1
P11/EC4/INT0
P10/PMSK
P07/EXI2/PMI
P06/EXI1
P05/EXI0
P04/CFG
P03/DFG
P02/DPG
P01/RFG0
P00/RFG1
VDD
A15
A14
A13
A12
A11
A10
A09
A08
P57
P56
P55
P54
P53
P52
P51
P50
P57
P56
P55
P54
P53
P52
P51
P50
VSS
D31/A07 D31/A15
D30/A06 D30/A14
D29/A05 D29/A13
P37
P36
P35
8-bit MPX mode
16-bit MPX mode
(FPT-120P-M05)
(Continued)
4
MB91191/192 Series
(Continued)
59 56 53 50
47 44 41
38 35 32
P94 P82 P85 P40 P43 P46 P56 P53 P50 P36
58 55 52 49
46 45 42
39 36 33
P80 P83 P86 P41 P44 P45 P57 P54 P51 P37
62
63 61
60 57 54 51
48 43 40
37 34 31
P91 P90 P92 P93 P81 P84 P87 P42 P47 P55 P52 VSS P35
65
66 64
30
28
29
OSCOOSCIVDD
P34 P32 P33
68
69 67
27
25
26
PC7 PC6 VSS
P31 VDD P30
71
72 70
24
22
23
PC4 PC3 PC5
P27 P25 P26
74
75 73
21
19
20
PC1 PC0 PC2
P24 P22 P23
Top View
77
76 78
18
16
17
PD6 PD7 PD5
P21 P60 P20
80
79 81
13
15
14
PD3 PD4 PD2
P63 P61 P62
83
82 84
10
12
11
PD0 PD1 PA7
P66 P64 P65
86
85 87
7
9
8
PA5 PA6 PA4
RST P67 P70
89
88 90
4
6
5
PA2 PA3 PA1
MD2 MD0 MD1
91
94 97 100 103 108 111 114 117 120
1
3
2
PA0 PB5 PB2 AVDD VSS P13 P10 P05 P02 VDD X0
VSS X1
93
96 99 102 105 106 109 112 115 118
PB6 PB3 PB0 AVSS P16 P15 P12 P07 P04 P01
92
95 98 101 104 107 110 113 116 119
PB7 PB4 PB1 AVRH P17 P14 P11 P06 P03 P00
(LGA-144P-M02)
Note : The FLGA-144 package is not supplied for the MB91191 series.
It is supplied only for the MB91192 series.
5
MB91191/192 Series
■ PIN DESCRIPTIONS
Circuit
Type
Pin No.
Pin Name
Function
1
X0
(I)
A
Crystal oscillator pins
VSS pin
2
X1
(O)
3
VSS
4
MD2
MD1
MD0
RST
Operation mode setting pins
CMOS Schmitt inputs
5
B
6
7
B
C
Reset input pin. CMOS Schmitt input.
8
P70/XOUT
Shared pin with clock output (X0/2, PCK/2) . CMOS input.
Shared pin with timer 4 square wave output. CMOS input.
Shared pin with timer 5 square wave output. CMOS input.
General-purpose I/O port. CMOS input.
9
P67/T40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P66/T501
P65
P64
General-purpose I/O port. CMOS input.
C
P63/ALE/ALE
Shared pin with address strobe output. CMOS input.
Shared pin with write strobe output 1. CMOS input.
Shared pin with write strobe output 0. CMOS input.
Shared pin with read strobe output. CMOS input.
P62/P62/WR1
P61/WR0/WR0
P60/RD/RD
P20/P20/D16 : A00
P21/P21/D17 : A01
P22/P22/D18 : A02
P23/P23/D19 : A03
P24/P24/D20 : A04
P25/P25/D21 : A05
P26/P26/D22 : A06
P27/P27/D23 : A07
VDD
General-purpose I/O ports.
CMOS inputs.
C
Power supply pin
P30/D24 : A00/D24 : A08
P31/D25 : A01/D25 : A09
P32/D26 : A02/D26 : A10
P33/D27 : A03/D27 : A11
P34/D28 : A04/D28 : A12
P35/D29 : A05/D29 : A13
P36/D30 : A06/D30 : A14
P37/D31 : A07/D31 : A15
VSS
Shared external bus pins and high-current I/O ports.
CMOS inputs.
C
VSS pin
(Continued)
6
MB91191/192 Series
Circuit
Type
Pin No.
Pin Name
P50/A08/P50
Function
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
P51/A09/P51
P52/A10/P52
P53/A11/P53
P54/A12/P54
P55/A13/P55
P56/A14/P56
P57/A15/P57
P47
Shared external bus pins and high-current I/O ports.
CMOS inputs.
C
C
C
General-purpose I/O port. CMOS input.
P46/PPG18
P45/PPG17
P44/PPG16
P43/PPG15
P42/PPG14
P41/PPG13
P40/PPG12
P87/PPG11
P86/PPG10
P85/PPG09
P84/PPG08
P83/PPG07
P82/PPG06
P81/PPG05
P80/PPG04
P94/PPG03
P93/PPG02
P92/PPG01
P91/PPG00
P90/P0
Shared pins with PPG outputs.
CMOS inputs.
Shared pins with PPG outputs.
CMOS inputs.
Shared pins with PPG outputs.
CMOS inputs.
C
C
Shared pins with PPG outputs.
CMOS inputs.
Shared pin with general-purpose prescaler output. CMOS input.
Power supply pin
VDD
OSCO
OSCI/PCK
VSS
(O)
Crystal oscillator pins for dedicated general-purpose prescaler
oscillation.
A
(I)
VSS pin
(Continued)
7
MB91191/192 Series
Circuit
Type
Pin No.
Pin Name
PC7/PWM0
Function
68
69
70
71
PC6/PWM1
PC5/PWM2
PC4/PWM3
Shared pins with PWM outputs.
C
CMOS inputs.
Shared pin with PWM output and serial 2 chip select.
CMOS Schmitt input.
72
73
PC3/PWM4/SCS2
PC2/PWM5/SCS1
Shared pin with PWM output and serial 1 chip select.
CMOS Schmitt input.
F
C
F
Shared pin with serial 0 shift clock.
CMOS Schmitt input.
74
75
76
PC1/SCK0
PC0/SO0
PD7/SI0
Shared pin with serial 0 serial output. CMOS input.
Shared pin with serial 0 serial input.
CMOS Schmitt input.
Shared pin with serial 0 chip select input.
CMOS Schmitt input.
77
PD6/SCS0
Shared pin with serial 1 shift clock.
CMOS Schmitt input.
78
79
80
PD5/SCK1
PD4/SO1
C
F
Shared pin with serial 1 serial output. CMOS input.
Shared pin with serial 1 serial input and external interrupt 2.
CMOS Schmitt input.
PD3/SI1/INT2
Shared pin with serial 2 shift clock.
CMOS Schmitt input.
81
82
83
PD2/SCK2
PD1/SO2
PD0/SI2
C
F
Shared pin with serial 2 serial output. CMOS input.
Shared pin with serial 2 serial input.
CMOS Schmitt input.
84
85
86
87
88
89
90
91
PA7/AN-F/KEY7
PA6/AN-E/KEY6
PA5/AN-D/KEY5
PA4/AN-C/KEY4
PA3/AN-B/KEY3
PA2/AN-A/KEY2
PA1/AN-9/KEY1
PA0/AN-8/KEY0
Shared pins with analog inputs and key inputs.
CMOS Schmitt inputs
E
(Continued)
8
MB91191/192 Series
(Continued)
Circuit
Type
Pin No.
Pin Name
Function
92
93
PB7/AN-7
PB6/AN-6
94
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
AVDD
95
Shared pins with analog inputs.
CMOS Schmitt inputs.
D
96
97
98
99
100
101
102
103
104
105
106
107
108
A/D converter power supply pin
A/D converter reference power supply pin
A/D converter VSS pin
AVRH
AVSS
VSS
VSS pin
P17/RTG4
P16/RTG3
P15/RTG2
P14/RTG1
P13/RTG0
Shared pins with RTG outputs.
CMOS inputs.
C
F
Shared pin with timer 5 clock input and external interrupt input.
CMOS Schmitt input.
109
P12/EC5/INT1
Shared pin with timer 4 clock input and external interrupt input.
CMOS Schmitt input.
110
111
112
P11/EC4/INT0
P10/PMSK
Shared pin with PWC mask input. CMOS Schmitt input.
Shared pin with external capture input and PWC input.
CMOS Schmitt input.
P07/EXI2/PMI
113
114
115
116
117
118
119
120
P06/EXI1
P05/EXI0
P04/CFG
P03/DFG
P02/DPG
P01/RFG0
P00/RFG1
VDD
Shared pin with external capture input.
CMOS Schmitt input.
Shared pin with capstan FG input. CMOS Schmitt input.
Shared pin with drum FG input. CMOS Schmitt input.
Shared pin with drum pulse input. CMOS Schmitt input.
F
Shared pins with reel FG inputs.
CMOS Schmitt inputs.
Power supply pin
9
MB91191/192 Series
■ I/O CIRCUITS
Type
Circuit
Remarks
• Oscillation feedback
resistor : 1 MΩ approx.
X0,OSCI
Clock input
A
Standby control signal
X1,OSCO
• CMOS Schmitt input
B
Input
• CMOS level output
• CMOS input
No standby control
Output data
DC test
DC test
C
Input
Standby control signal = 1 (fixed)
• CMOS level output
• CMOS input
with input control
• Analog input
Output data
DC test
DC test
D
Analog input
CH selection
Digital input
Input control
(Continued)
10
MB91191/192 Series
(Continued)
Type
Circuit
Remarks
• CMOS level output
Input data
• CMOS Schmitt input
with input control
• Analog input
DC test
DC test
E
Analog input
CH selection
Digital input
Input control
• CMOS level output
• CMOS Schmitt input
No standby control
Output data
DC test
DC test
F
Input
Standby control signal = 1 (fixed)
• CMOS level output
• CMOS Schmitt input
No standby control
Output data
DC test
DC test
H
Input
11
MB91191/192 Series
■ BLOCK DIAGRAM
P47
Mode control
MD0
MD1
MD2
RST
P46/PPG18
P45/PPG17
P44/PPG16
P43/PPG15
P42/PPG14
P41/PPG13
P40/PPG12
RAM 256 byte PPG0
P37/D31
to
FR20 CPU core
PPG1
RAM 64 byte
P87/PPG11
P86/PPG10
P85/PPG09
P84/PPG08
P83/PPG07
P82/PPG06
P81/PPG05
P80/PPG04
P94/PPG03
P93/PPG02
P92/PPG01
P91/PPG00
P90/P0
I-bus
I-bus
D-bus
P30/D24
P27/D23
Bit search
to
D-bus
C-bus
MB91191R :RAM 6 KB
MB91192 :RAM 8 KB
MB91F191A :RAM 6 KB
MB91F192 :RAM 8 KB
P20/D16
P57/A15
RAM 2 KB
to
D-bus
R-bus
P50/A08
P60/RD
P61/WR0
P62/WR1
P63/ALE
P64
PD0/SI2
MB91191R :ROM 254 KB
MB91192 :ROM 384 KB
MB91F191A:FLASH 254 KB
MB91F192 :FLASH 384 KB
RAM
128 byte
Serial
ch 0
PD1/SO2
PD2/SCK2
PD3/SI1/INT2
PD4/SO1
RAM
128 byte
Serial
ch 1
P65
P66/T501
P67/T40
PD5/SCK1
PD6/SCS0
PD7/SI0
RAM
128 byte
Serial
ch 2
PC0/S00
External bus control
16-bit timers 0 to 3
PC1/SCK0
PC2/PWM5/SCS1
PC3/PWM4/SCS2
PC4/PWM3
PC5/PWM2
PC6/PWM1
PC7/PWM0
P70/XOUT
12-bit PWM00-02
12-bit PWM10-12
P17/RTG4
P16/RTG3
P15/RTG2
P14/RTG1
P13/RTG0
P12/EC5/INT1
Interrupt
controller
INT2 to INT0 (from port 1, D)
External interrupts
8/16-bit timer
16-bit timer 4
8-bit PWC
P11/EC4/INT0
RTG4 to RTG0 (to port 1)
P10/PMSK
P07/EXI2/PMI
P06/EXI1
16-bit RTG0-2
PA7/AN-F/KEY7
PA6/AN-E/KEY6
PA5/AN-D/KEY5
PA4/AN-C/KEY4
PA3/AN-B/KEY3
PA2/AN-A/KEY2
PA1/AN-9/KEY1
PA0/AN-8/KEY0
P05/EXI0
P04/CFG
P03/DFG
P02/DPG
P01/RFG0
CFG
DFG
External interrupts
(key inputs)
24-bit
FRC
RFG0
RFG1
P00/RFG1
10-bit A/DC
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
FIFO
29-bit × 8
X0
X1
OSC
OSC
C-unit
FIFO
FIFO
(software) (hardware)
OSCI
OSCO
10-bit programmable
prescaler
12
MB91191/192 Series
(Bus names)
• I bus : 16-bit bus for internal instructions. As the FR family of CPUs use the Harvard architecture, instructions
and data use separate buses. A bus converter is connected to the I bus.
• D bus : Internal 32-bit data bus. The internal peripherals are connected to the D bus.
• C bus : Internal multiplexed bus. Connected to the I and D buses via a switch. An external interface module
is connected to the C bus. Data and instructions are multiplexed on the external data bus.
• R bus : Internal 16-bit data bus. The R bus connects to the D bus via an adapter. The I/O, clock oscillator, and
interrupt controller are connected to the R bus. As the R bus is only 16 bits wide, address and data
are multiplexed on the bus and therefore multiple cycles are required when the CPU accesses these
resources.
13
MB91191/192 Series
■ MEMORY MAP
00000000H
00000000H
to
to
I/O area
I/O area
000001FFH
000001FFH
00000200H
00000200H
PPG0 Data RAM area
PPG0 Data RAM area
256 bytes
to
to
256 bytes
000002FFH
000002FFH
00000300H
to
0000037FH
00000380H
to
000003BFH
000003C0H
to
Direct
access
area
00000300H
SIO0 Data RAM area
128 bytes
SIO0 Data RAM area
to
128 bytes
0000037FH
00000380H
PPG1 Data RAM area
PPG1 Data RAM area
64 bytes
to
64 bytes
000003BFH
000003C0H
to
I/O area
I/O area
000003FFH
00000400H
000003FFH
00000400H
to
to
I/O area
I/O area
000007FFH
000007FFH
00000800H
to
00000800H
to
Access inhibited
Access inhibited
00000FFFH
00000FFFH
00001000H
to
0000107FH
00001080H
to
00001000H
SIO1 Data RAM area
SIO1 Data RAM area
128 bytes
to
128 bytes
0000107FH
00001080H
SIO2 Data RAM area
to
000010FFH
00001100H
SIO2 Data RAM area
128 bytes
128 bytes
000010FFH
00001100H
to
Access inhibited
to
Access inhibited
0000DFFFH
0000E000H
to
0000E7FFH
0000E800H
Internal RAM area
8 Kbytes
Internal RAM area
to
6 Kbytes
0000FFFFH
00010000H
to
0007FFFFH
00080000H
to
000807FFH
00080800H
to
0000FFFFH
00010000H
Access inhibited
Internal RAM area
2 Kbytes
to
Access inhibited
Access inhibited
0009FFFFH
000A0000H
000BFFFFH
000C0000H
Internal RAM area
to
000C07FFH
to
Internal ROM area
384 Kbytes
2 Kbytes
000C0800H
Internal ROM area
to
254 Kbytes
000FFFFBH
1 KB
Initial vector area
000FFFFBH
000FFFFCH
000FFFFCH
Reset vector
Reset vector
00100000H
00100000H
to
External extended area
External extended area
to
FFFFFFFFH
FFFFFFFFH
MB91191R
MB91192
Note : The single chip mode does not allow access to the external extended area.
For access to the external extended area, use the mode register to select
the internal ROM external bus mode.
14
MB91191/192 Series
■ FLASH MEMORY MAP AND SECTOR CONFIGURATION
Flash memory is address-mapped differently between when accessed from the FR-CPU and when accessed
from the ROM programmer.* Shown below is address mapping at access from the CPU.
* : While the on-board flash memory uses the little endian format, the FR-CPU interface circuit converts data into
bigendian.AsthisconversionfunctiondoesnotworkduringaccessfromtheROMprogrammer,addressmapping
is different from that in CPU mode.
• MB91F191A
MSB side 16 bit
LSB side 16 bit
31
16
15
0
00000000H
000007C0H
000C0800H
000C0801H 000C0802H
000C0803H
Status resistor
SA5 (63 Kbyte)
SA0 (63 Kbyte)
000C0000H
000C0800H
Internal RAM area
Flash Memory
area
000FFFFFH
000E0000H
000F0000H
000E0001H 000E0002H
000F0001H 000F0002H
000E0003H
000F0003H
SA6 (32 Kbyte)
SA1 (32 Kbyte)
SA7 (8 Kbyte)
SA8 (8 Kbyte)
SA2 (8 Kbyte)
SA3 (8 Kbyte)
000F4001H 000F4002H
000F8001H 000F8002H
000F4003H
000F8003H
000F4000H
000F8000H
SA9 (16 Kbyte)
SA4 (16 Kbyte)
000FFFFCH
000FFFFDH 000FFFFEH
000FFFFFH
FFFFFFFFH
Sector Configuration (SA = Sector address)
Memory Map
• MB91F192
MSB side 16 bit
LSB side 16 bit
31
16
15
0
00000000H
000007C0H
000A0000H
000A0001H 000A0002H
000A0003H
Status resistor
SA0 (64 Kbyte)
SA6 (64 Kbyte)
00080000H
Internal RAM area
00080800H
000A0000H
000C0000H
000E0000H
000C0001H 000C0002H
000C0003H
000E0003H
Flash Memory
area
SA1 (64 Kbyte)
SA2 (32 Kbyte)
SA7 (64 Kbyte)
SA8 (32 Kbyte)
000FFFFFH
000E0001H 000E0002H
000F0000H
000F4000H
000F8000H
000F0001H 000F0002H
000F4001H 000F4002H
000F8001H 000F8002H
000F0003H
000F4003H
000F8003H
SA3 (8 Kbyte)
SA4 (8 Kbyte)
SA9 (8 Kbyte)
SA10 (8 Kbyte)
SA5 (16 Kbyte)
SA11 (16 Kbyte)
000FFFFCH
000FFFFDH 000FFFFEH
000FFFFFH
FFFFFFFFH
Memory Map
Sector Configuration (SA = Sector address)
15
MB91191/192 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0 V)
Rating
Parameter
Power supply voltage
Symbol
Unit
Remarks
Min
Max
VSS + 3.5
VSS + 3.5
VSS + 3.5
VSS + 3.5
VSS + 3.5
10
VDD
AVDD
AVRH
VI
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
V
V
V
V
V
Analog power supply voltage
Analog reference voltage
*1
*1
*2
*2
Input voltage
Output voltage
VO
“L” level maximum output current
“L” level average output current
“L” level total maximum output current
“L” level total average output current
“H” level maximum output current
“H” level average output current
“H” level total maximum output current
“H” level total average output current
Power consumption
IOL
mA *3
mA *4
mA
IOLAV
ΣIOL
ΣIOLAV
IOH
8
100
50
mA *5
mA *3
mA *4
mA
−10
IOHAV
ΣIOH
ΣIOHAV
PD
−4
−50
−20
mA *5
mW
500
Operating temperature
TA
−20
−55
+70
°C
Storage temperature
Tstg
+150
°C
*1 : Care must be taken that AVDD and AVRH do not exceed VDD + 0.3 V such as when turning on the device.
Also care must be taken that AVRH does not exceed AVDD.
*2 : VI and VO may not exceed VDD + 0.3 V.
*3 : The maximum output current is the peak value for a single pin.
*4 : The average output current is the average current for a single pin over a period of 100 ms.
*5 : The total average output current is the average current for all pins over a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
16
MB91191/192 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0 V)
Value
Parameter
Symbol
Unit
Remarks
Min
Max
2.7
3.3
Normal operation
Power supply voltage
VDD
V
Maintaining RAM state in
stop mode
2.0
3.3
Analog power supply voltage
Analog reference voltage
Operating temperature
AVDD
AVRH
TA
VSS − 0.3
AVSS
VDD + 0.2
AVDD
V
V
−20
70
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
17
MB91191/192 Series
3. DC Characteristics
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Symbol
Parameter
Pin Name
Condition
Unit Remarks
Min
0.7 VDD
VDD − 0.4
0.8 VDD
VDD
Typ
Max
VIH
*3
*1
*2
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
0.2 VDD
VSS + 0.4
0.2 VDD
VSS
V
V
V
V
V
V
V
V
“H” level
input voltage
VIHS
VIHM
VIL
MD2 to MD0
*3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
2.4
“L” level
input
voltage
*1
VILS
VILM
VOH1
*2
MD2 to MD0
V
V
V
V
MB91F191A
MB91191R
MB91F191A
MB91191R
VDD = 3.0 V,
IOH = −4.0 mA
*4
“H” level
output
voltage
2.4
2.4
VDD = 3.0 V,
IOH = −8.0 mA
VOH2
*5, *6
2.4
VDD = 3.0 V,
IOL = 4.0 mA
VOL1
VOL2
VOL3
*4
0.6
0.6
0.3
V
V
V
“L” level
output
voltage
VDD = 3.0 V,
IOL = 8.0 mA
*5, *6
*4, *5, *6
VDD = 3.0 V,
IOL = 1.0 mA
MB91191R
ILI1
ILIX
*2
±1
±8
50.1
16
24
13
1
±5
±20
60
µA
µA
Input leak
current
VDD = 3.0 V,
VSS < VI < VDD
X0, OSCI
mA MB91F191A
mA MB91191R
mA MB91F191A
mA MB91191R
µA MB91F191A
µA MB91191R
IDD
VDD = 3.0 V, *7
VDD = 3.0 V, *8
25
Power
supply
current
36
IDDS
VDD
18
240
300
VDD = 3.0 V,
TA = 25 °C, *9
IDDH
CIN
10
Input
capacitance
Other than VDD, VSS,
AVDD, AVSS, and AVRH
10
pF
*1 : X0, X1, OSCI, OSCO
*2 : RST, PC3 to PC1, PD6, PD5, PD3, PD2, PA7 to PA0, P12 to P10, P07 to P00, PD7, PD0
*3 : Inputs other than *1, *2, MD2 to MD0
*4 : P07 to P00, P17 to P10, P27 to P20, P47 to P40, P67 to P60, P70, P87 to P80, P94 to P90, PA7 to PA0,
PB7 to PB0, PC7 to PC2, PD7, PD6, PD3, PD0
*5 : P37 to P30, P57 to P50
*6 : PD5, PD4, PD2, PD1, PC1, PC0
*7 : Operating current for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection : CPU = 10 MHz,
peripherals = 20 MHz
*8 : Operating current in sleep mode for X0 = 20 MHz, OSCI = VSS (fixed), all port outputs = low, gear selection :
CPU = 10 MHz, peripherals = 20 MHz
*9 : Operating current in stop mode for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection :
CPU = 10 MHz, peripherals = 20 MHz
18
MB91191/192 Series
4. AC Characteristics
(1) Clock Timings
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min
10
Max
20
Clock frequency
fC
tC
MHz
ns
Clock cycle time
50
100
10
Frequency fluctuation* (PLL locked)
∆r
%
PWH
PWL
tCR
tCF
Input clock pulse width
Input clock rise/fall time
20
ns
ns
8
CPU
fCP
5
20
20
MHz
MHz
ns
Internal operating clock
frequency
When wait
controllersetto
1 wait cycle
Peripherals
CPU
fCPP
tCP
10
50
50
200
100
Internal operating clock
cycle time
Peripherals
tCPP
ns
* : The frequency fluctuation value is the maximum percentage deviation from the preset center frequency when
using the multiplier (when PLL is locked) .
+
+α
| α |
∆f =
× 100 (%)
Center frequency f0
f0
−α
−
tc
PWH
PWL
tcr
tcf
Guaranteed operation range
3.3
2.7
fcpp
fcp
10 M 20 M
Frequency (Hz)
19
MB91191/192 Series
The figure below shows the relationship between the X0 input and the internal clock based on the GCR (Gear
Control Register) , CHC, CCK1, and CCK0 bit settings.
X0 input
Source oscillation × 1
(CHC bit in GCR = 0)
tCYC
(a) gear × 1
CCK1/0:00
Internal clock
Internal clock
Internal clock
Internal clock
tCYC
(b) gear × 1/2
CCK1/0:01
(c) gear × 1/4
CCK1/0:10
tCYC
tCYC
(d) gear × 1/8
CCK1/0:11
Source oscillation × 1/2
(CHC bit in GCR = 1)
tCYC
Internal clock
(a) gear x 1
CCK1/0:00
tCYC
(b) gear x 1/2
CCK1/0:01
(c) gear x 1/4
CCK1/0:10
Internal clock
Internal clock
tCYC
tCYC
(d) gear x 1/8
CCK1/0:11
Internal clock
Where tCYCH is the H level width of the internal clock and tCYCL is the L level width.
For example, when set to source oscillation × 1/2, gear × 1/4 and X0 input frequency = 20 MHz : tCYC = 400 ns,
tCYCH = 350 ns, tCYCL = 50 ns
20
MB91191/192 Series
(2) Multiplex Bus Read/Write Operation
(VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Condi-
tion
Re-
marks
Parameter
Symbol Pin Name
Unit
Min
Typ
Max
ALE pulse width
tEHEL
tEHAV
tEHAX
tELDV
tELRL
tRLRH
tELWL
tWLWH
tDSRH
tRHDX
ALE
tCYC − 10
tCYCH − 15
tCYCL − 2
ns
Address delay time
Address clear time
Data delay time
tCYCH
tCYCL
tCYCH + 15 ns *2
A15 to A0,
D31 to D16
tCYCL + 10
tCYCL + 26
tCYC + 11
tCYC + 11
tCYC + 11
tCYC + 11
ns *2
ns *2
ns
D31 to D16
RD
RD delay time
tCYC − 11
tCYC − 11
tCYC − 11
tCYC − 11
15
tCYC
tCYC
tCYC
tCYC
RD pulse width
ns *1
ns
WR0, WR1 delay time
WR0, WR1 pulse width
Data setup → RD ↑ time
RD ↑→ Data hold time
WR0, WR1
ns *1
ns
RD,
D31 to D16
0
ns
*1 : When the bus is delayed by automatic wait insertion, add (tCYC × number of wait cycles) to this value.
*2 : This value is for gear setting = ×1
For the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively for n in the formula below.
Formula : tCYCH = (1 − n / 2) × tCYC
tCYCL = (n / 2) × tCYC
Internal
clock
tEHEL
ALE
tELAX
tDSRH
tRHDX
tEHAV
Read time
D31 to D16
MPX bus
RD
tRLRH
tELRL
Write time
D31 to D16
MPX bus
tWHDX
tELDV
tELWL
WR0 , WR1
tWLWH
A15 to A08
When not
multiplexed
21
MB91191/192 Series
(3) Reset Input Ratings
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Parameter
Symbol
Pin Name
Unit
Remarks
Min
Max
Reset input time
tRSTL
RST
5 tCP
ns
tRSTL
RST
0.2 VDD
(4) Power-On Reset
Paramete
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Symbol
Pin Name
Unit
Remarks
Min
Max
Power supply rise time
Power supply cutoff time
tR
20
ms
ms
VDD
tOFF
2
tOFF
tR
2.7 V
0.2 V
VDD
Sudden changes in the power supply voltage may cause a power-on reset.
The recommended practice if you wish to change the power supply voltage while the device is operating
is to raise the voltage smoothly.
3.0 V
VDD
2.0 V
Recommended rate of voltage
rise is 50 mV/ms or less.
Maintain RAM data
VSS
VDD
When turning on the power, start with
the RST pin in the "L" level state and
allow a time of tRSTL after reaching
the VDD power supply level before
changing the pin to the "H" level.
RST
tRSTL
22
MB91191/192 Series
(5) Serial I/O (CH0 to 2)
Parameter
(VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Sym-
bol
Condition
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
tBUSY
tCLZO
tCLSL
tCHOZ
8 tCPP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK ↓ → SO delay time
Valid SI → SCK ↑
−10
50
Internal clock
50
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO delay time
Valid SI → SCK ↑
50
4 tCPP − 10
4 tCPP − 10
0
50
50
50
External clock
SCK ↑ → valid SI hold time
Serial busy time
6 tCPP
50
SCS ↓ → SCK, SO delay time
SCS ↓ → SCK input mask time
SCS ↓ → SCK, SO Hi-Z time
3 tCPP
50
• Internal shift clock mode
tSCYC
SCK
tSLOV
SO
SI
tIVSH
tSHIX
• External shift clock mode
tCLZO
tSLSH
tSHSL
tBUSY
tCHOZ
SCK
SO
tSLOV
SI
tIVSH
tSHIX
SCS
tCLSL
23
MB91191/192 Series
(6) FG Pulse Input
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Parameter
Symbol
Pin Name
Unit
Remarks
Min
Max
Servo input “H” pulse width
Servo input “L” pulse width
tSPWH
tSPWL
CFG, DFG, DPG,
RFG0, RFG1,
EXI0 to EXI2
tC + 50
ns
ns
tC + 50
Note : tC is the clock cycle time of the X0 and X1 pin oscillation.
CFG
DFG, DPG
RFG0, RFG1
EXI0 to EXI2
tSPWH
tSPWL
tf
tr
(7) Timer External Clock Input
(VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Parameter
Symbol
Pin Name
Unit
Remarks
Min
4 tC + 50
4 tC + 50
4 tCPP
Max
Timer 4 input “H” pulse width
Timer 4 input “L” pulse width
Timer 5 input “H” pulse width
Timer 5 input “L” pulse width
tECWH
tECWL
tECWH
tECWL
ns
ns
ns
ns
EC4
EC5
4 tCPP
EC4,
EC5
tECWH
tECWL
tf
tr
24
MB91191/192 Series
(8) General-Purpose Prescaler
(VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Parameter
Symbol
Pin Name
Unit
Remarks
Min
Max
PCK input clock frequency
PCK input “H” pulse width
PCK input “L” pulse width
fCP
tSPWH
tSPWL
tf
12
MHz
ns
PCK
33
33
ns
Fall time
PCK input
PCK
PO
100
80
ns
ns
Rise time
tr
PO output delay time
tPOPI
tSPWH
tf
tr
tSPWL
PCK
PO
tPOPI
25
MB91191/192 Series
5. Electrical Characteristics for the A/D Converter
(VDD = 3.0 V + 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Value
Typ
Pin
Name
Parameter
Resolution
Symbol
Condition
Unit Remarks
Min
Max
10
bit
Conversion time
Total error
8.4
µs
±4.0
±3.5
±2.0
LSB
LSB
LSB
VDD = AVDD = 3.0 V,
AVRH = 3.0 V
Linearity error
Differential linearity error
AN-0 to
AN-F
AVSS −
1.5
AVSS +
0.5
AVSS +
2.5
Zero transition error
Full-scale transition error
Analog input current
Analog input voltage
VOT
VFST
IAIN
LSB
LSB
µA
VDD = AVDD = 3.0 V,
AVRH = 3.0 V
AN-0 to
AN-F
AVRH −
5.5
AVRH −
1.5
AVRH +
0.5
AN-0 to
AN-F
0.1
10
AN-0 to
AN-F
VAIN
AVRH
IA
AVSS
AVRH
AVDD
V
V
Reference voltage
During
AVRH
3.0
mA
Power
conversion
supply
AVDD
VDD = AVDD = 3.0 V
Conver-
current
IAH
IR
5.0
µA
µA
sion halted
During
conversion
Reference
voltage
supply
100
VDD = AVDD = 3.0 V,
AVRH = 3.0 V
AVRH
Conver-
sion halted
IRH
10
4
µA
current
Variation between
channels
AN-0 to
AN-F
LSB
Notes : • The relative error increases as |AVRH| becomes smaller.
• Ensure that the output impedance of the external circuit connected to the analog input meets the following
condition :
Output impedance of external circuit < 7 kΩ (approx.)
If the output impedance of the external circuit is too high, the analog voltage sampling time may be too
short. (Sampling time = 6.4 µs for a 20 MHz machine clock)
26
MB91191/192 Series
6. Flash Memory Erase and Programming performance
Value
Parameter
Condition
Unit
Remarks
Min
Typ
Max
Excludes 00H programming prior
erasure
Sector erase time
1
15
s
10
12
MB91F191A Excludes 00H
programming prior
Chip erase time
TA = +25 °C,
VCC = 3.0 V
s
MB91F192
erasure
Half word
(16 bit width)
programming time
16
3,600
µs
Excludes system-level overhead
Erase/Program
cycle
10,000
cycle
h
Data holding time
100,000
27
MB91191/192 Series
7. A/D Converter Glossary
• Resolution : The change in analog voltage that can be recognized by the A/D converter.
• Linearity error
The deviation between the actual conversion characteristics and the line linking the zero transition point
(“00 0000 0000B” ←→ “00 0000 0001B”) and the full scale transition point (“11 1111 1110B” ←→ “11 1111
1111B”) .
• Differential linearity error
The variation from the ideal input voltage required to change the output code by 1 LSB.
• Total error
The total error is the difference between the actual value and the theoretical value.
Includes the zero transition error, full-scale transition error and linearity error.
Total Error
3FF
1.5 LSB’
Actual conversion
characteristic
{1 LSB’ × (N − 1) + 0.5 LSB’}
3FE
3FD
004
003
002
001
VNT
(Measured value)
Actual conversion
characteristic
Theoretical characteristic
0.5 LSB’
AVRH
AVSS
Analog Input
AVRH − AVSS
1 LSB’ (Theoretical) =
[V]
1024
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
Total error for digital output N =
1 LSB’
VOT’ (Theoretical) = AVSS + 0.5 LSB’ [V]
VFST’ (Theoretical) = AVRH − 1.5 LSB’ [V]
VNT : Voltage at which digital output changes from (N + 1) to N
28
MB91191/192 Series
Differential Linearity Error
Linearity Error
3FF
3FE
3FD
Actual conversion characteristic
Actual conversion characteristic
N + 1
{1 LSB × (N − 1) + VoT’}
VFST
(Measured
value)
Theoretical characteristic
N
004
003
002
001
VNT
(Measured
value)
N − 1
N − 2
V
FST
Actual conversion
(Measured
value)
V
NT
characteristic
(Measured value)
Theoretical characteristic
Actual conversion characteristic
VOT (Measured value)
Analog Input
Analog Input
AVSS
AVRH
AVSS
AVRH
Linearity error for
digital output N
VNT − {1 LSB × (N − 1) + VOT}
=
[LSB]
1 LSB’
Differential linearity error
for digital output N
V(N+1) T − VNT
=
− 1 LSB [LSB]
1 LSB’
VFST − VOT
VOT’ (Theoretical) =
[V]
1022
VOT : Voltage at which digital output changes from (000) H to (001) H.
VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
29
MB91191/192 Series
■ ORDERING INFOMATION
Part No.
MB91191RPFF
Package
Remarks
MB91192PFF
MB91F191APFF
MB91F192PFF
Plastic LQFP, 120-pin
(FPT-120P-M05)
MB91192LGA
MB91F192LGA
Plastic FLGA, 144-pin
(LGA-144P-M02)
30
MB91191/192 Series
■ PACKAGE DIMENSION
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Plastic LQFP, 120-pin
(FPT-120P-M05)
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
.059 +–..000048
(Mounting height)
INDEX
120
31
"A"
0~8˚
1
30
LEAD No.
0.10±0.10
(.004±.004)
(Stand off)
0.16±0.03
(.006±.001)
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
M
0.07(.003)
0.40(.016)
0.60±0.15
(.024±.006)
0.25(.010)
C
2003 FUJITSU LIMITED F120006S-c-4-5
Dimensions in mm (inches).
(Continued)
31
MB91191/192 Series
(Continued)
Plastic FLGA, 144-pin
(LGA-144P-M02)
11.00±0.10(.433±.004)SQ
0.65(.026)TYP
5.175(.204)
15
14
13
12
11
10
9
5.175
(.204)
9.10±0.10
(.358±.004)
REF
11.00±0.10
(.433±.004)
8
7
6
INDEX AREA
5
4
3
0.45(.018)
2
1
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1.40(.055)
Max.
0.45(.018)
144-ø0.35
(144-ø.014)
M
0.08(.003)
3-ø0.45
(3-ø.018)
0.08(.003)
C
2001 FUJITSU LIMITED L144002S-c-1-1
Dimensions in mm (inches).
32
MB91191/192 Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-
partyÅfs intellectual property right or other right by using such
information. Fujitsu assumes no liability for any infringement of
the intellectual property rights or other rights of third parties which
would result from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0302
FUJITSU LIMITED Printed in Japan
相关型号：
MB91213APMC-GSE1
RISC Microcontroller, 32-Bit, FLASH, FR60 CPU, 40MHz, CMOS, PQFP144, 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
CYPRESS
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