MB91248S [FUJITSU]
32-bit Microcontroller; 32位微控制器
| 型号： | MB91248S |
| 厂家： | 
FUJITSU |
| 描述： | 32-bit Microcontroller |
| 文件： | 总82页 (文件大小：748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16803-1E
32-bit Microcontroller
CMOS
FR60Lite MB91245/S Series
MB91247/247S/248/248S/F248/F248S/MB91V245A
■ OVERVIEW
MB91245/S series is Fujitsu’s general-purpose 32-bit RISC microcontroller, which is designed for embedded
control applications that require high-speed real-time processing of consumer appliances. This microcontroller
uses FR60Lite as its CPU, compatible with other products in the FR* family.
This series incorporates an LCD controller and stepping motor controller.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
• FR60Lite CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Maximum operating frequency : 32 MHz (Source oscillation is 4 MHz with x8 multiplier – PLL clock multiplier
system)
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed : 1 instruction per cycle
• Instruction set optimized for embedded application : Memory-to-memory transfer, bit manipulation, barrel shift
instructions etc.
• Instructions adapted for programming C language : Function entry/exit instructions, multiple-register load/store
instructions.
• Register interlock function : Easier assembler coding enabled
• Built-in multiplier supported at the instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
MB91245/S Series
(Continued)
• Interrupt (PC/PS save) : 6 cycles (16 priority levels)
• Harvard architecture allowing program access and data access to be executed simultaneously.
• Instruction set compatible with FR family
• Internal Peripheral Functions
• Internal ROM size & ROM type
MASK ROM
Flash Memory
: 256 Kbytes (MB91248/S) / 128 Kbytes (MB91247/S)
: 256 Kbytes
• Internal RAM size : 16 Kbytes (MB91248/S, MB91F248/S) / 8 Kbytes (MB91247/S) / 32 Kbytes (MB91V245A)
• General-purpose ports : up to 120 ports (includes 4 input-only ports)
• 8/10-bit A/D converter (Sequential comparison type)
8/10-bit resolution : 32 channels
Conversion time : 3 µs (16/32 MHz)
Set the PLL multiplier and the division ratio of peripheral circuit clocks so that the above conversion time is
achieved.
32 MHz : Source oscillation (4 MHz) with x8 multiplier, divided by 1
16 MHz : Source oscillation with x8 multiplier, divided by 2
• External interrupt input : 8 channels
• Bit search module (for REALOS)
Search function to locate the position of the first bit that changes from “1” to “0” in one word, from the MSB
(Most Significant Bit)
• UART (full duplex double buffer type) : 1 channel
Parity enable/disable selectable
Asynchronous clock operation (start-stop synchronization) and synchronous clock operation selectable
Dedicated baud-rate timer (U-Timer) embedded in each channel
External clock can be used as transfer clock
Parity, frame, overrun error detection functions provided
• LIN-UART (full duplex double buffer type) : 3 channels
Synchronous/asynchronous clock operations selectable
Sync-break detection
Dedicated built-in baud-rate generator
• Stepping motor controller (SMC) : 6 channels
8-bit PWM with 4 high-current outputs for each channel
• 8/16-bit PPG timer : 8/4 channels
• 16-bit reload timer : 3 channels
• 16-bit free-run timer : 2 channels (ICU/OCU linkage)
• 16-bit pulse width counter : 1 channel
• Input capture : 4 channels (linked to ch.0 and ch.1 of free-run timer)
ch.0 linked to PWC
• Output compare : 2 channels (linked to ch.0 of free-run timer)
• LCD controller : SEG00 to SEG31/COM0 to COM3 (shared with port)
• 16-bit timebase/watch dog timer
• Sound generator
• Real-time clock
• 32 kHz sub clock (not supported in single clock products)
• C-CAN : 2 channels
• Low power consumption modes : sleep mode, stop mode, watch mode
• Package : LQFP-144 (FPT-144P-M08)
• CMOS technology : 0.35 µm
• Power supply voltage : 5 V (Internal logic : 3.3 V, I/O : 5.0 V (step-down circuit used))
2
MB91245/S Series
■ PRODUCT LINEUP
A table below shows the product lineup of the MB91245/S series. Embedded peripheral functions which are not
listed are common functions.
MB91V245A
External SRAM
32 Kbytes
MB91247/S
128 Kbytes
8 Kbytes
MB91248/S
256 Kbytes
16 Kbytes
MB91F248/S
256 Kbytes
16 Kbytes
ROM/Flash size
RAM size
External interrupt
DMA Controller
A/D Converter
UART
8 channels
5 channels
32 channels
1 channel
LIN-UART
3 channels
Stepping Motor Controller
8 /16-bit PPG
6 channels
8 channels/4 channels
3 channels
16-bit Reload Timer
16-bit Free Run Timer
2 channels
16-bit Pulse Width
Counter
1 channel
Input Capture Unit
Output Compare Unit
LCD Controller
4 channels
2 channels
4 COM, 32 SEG
1 channel
Sound Generator
Real Time Clock
32 kHz Sub Clock
Yes
Yes
Yes/No (S series)
Yes/No (S series)
Yes/No (S series)
Addr 16 bits
Data 16 bits
External bus
Others
MASK ROM
product
MASK ROM
product
Flash memory
product
EVA device
DSU4
On Chip Debug Support
Unit
⎯
2 channels
32-message buffer
C-CAN unit
3
MB91245/S Series
■ PIN ASSIGNMENT
(TOP VIEW)
1
2
3
4
5
6
7
8
9
A04/SEG04/P24
A05/SEG05/P25
A06/SEG06/P26
A07/SEG07/P27
A08/SEG08/P30
A09/SEG09/P31
A10/SEG10/P32
A11/SEG11/P33
A12/SEG12/P34
108 INIT
107 MOD0
106 MOD1
105 MOD2
104 DVSS
103 DVCC
102 PE7/PWM2M5
101 PE6/PWM2P5
100 PE5/PWM1M5
99 PE4/PWM1P5
98 PE3/PWM2M4
97 PE2/PWM2P4
96 PE1/PWM1M4
95 PE0/PWM1P4
94 PA3/PWM2M3
93 PA2/PWM2P3
92 PA1/PWM1M3
91 PA0/PWM1P3
90 DVSS
A13/SEG13/P35 10
A14/SEG14/P36 11
A15/SEG15/P37 12
D08/SEG16/P10 13
D09/SEG17/P11 14
D10/SEG18/P12 15
X0A 16
X1A 17
VCC 18
VSS 19
VCC3C 20
89 DVCC
D11/SEG19/P13 21
D12/SEG20/P14 22
D13/SEG21/P15 23
D14/SEG22/P16 24
D15/SEG23/P17 25
D00/INT0/SEG24/P00 26
D01/INT1/SEG25/P01 27
D02/INT2/SEG26/P02 28
D03/INT3/SEG27/P03 29
D04/INT4/SEG28/P04 30
D05/INT5/SEG29/P05 31
D06/SEG30/P06 32
D07/ATG/SEG31/P07 33
RX0/INT6/P70 34
TX0/P71 35
88 PF7/AN15
87 PF6/AN14
86 PF5/AN13
85 PF4/AN12
84 PF3/AN11
83 PF2/AN10
82 PF1/AN9
81 PF0/AN8
80 P67/AN7
79 P66/AN6
78 P65/AN5
77 P64/AN4
76 P63/AN3
75 P62/AN2
74 P61/AN1
RX1/INT7/P72 36
73 P60/AN0
(FPT-144P-M08)
4
MB91245/S Series
■ PIN DESCRIPTIONS
I/O circuit
type*
Pin no.
Pin name
Function
P24 to P27
SEG04 to SEG07
A04 to A07
P30 to P37
SEG08 to SEG15
A08 to A15
P10 to P12
SEG16 to SEG18
D08 to D10
X0A
General purpose I/O port pins
1 to 4
F
F
SEG output pin for LCDC
Bits 04 to 07 pins of external address bus
General purpose I/O port pins
SEG output pins for LCDC
5 to 12
Bits 08 to 15 pins of external address bus
General purpose I/O port pins
SEG output pins for LCDC
13 to 15
G
Bits 08 to 10 pins of external data bus
Sub clock (oscillation) input
Sub clock (oscillation) output
Power supply pins
16
17
18
19
20
B
B
X1A
VCC
⎯
⎯
⎯
VSS
GND pins
VCC3C
Capacitor connection pin for internal regulator
General purpose I/O port pins
SEG output pins for LCDC
P13 to P17
SEG19 to SEG23
D11 to D15
P00 to P05
SEG24 to SEG29
INT0 to INT5
D00 to D05
P06
21 to 25
26 to 31
32
G
G
G
G
Bits 11 to 15 pins of external data bus
General purpose I/O port pins
SEG output pins for LCDC
External interrupt input pins
Bits 00 to 05 pins of external data bus
General purpose I/O port pin
SEG output pins for LCDC
SEG30
D06
Bit 06 pin of external data bus
General purpose I/O port pin
SEG output pin for LCDC
P07
SEG31
33
ATG
External trigger input pin at using of A/D converter
Bit 07 pin of external data bus
General purpose I/O port pin
External interrupt input pin
D07
P70
34
35
INT6
I
I
RX0
RX0 input pin of CAN0
P71
General purpose I/O port pin
TX0 output pin of CAN0
TX0
(Continued)
5
MB91245/S Series
I/O circuit
type*
Pin no.
Pin name
Function
General purpose I/O port pin
P72
INT7
36
I
External interrupt input pin
RX1
RX1 input pin of CAN1
P73
General purpose I/O port pin
37
I
TX1
TX1 output pin of CAN1
38
39
DVCC
⎯
⎯
Power supply input pins for SMC
GND pins for SMC
DVSS
PB0
General purpose I/O port pin
40
41
42
43
44
45
46
47
48
49
50
51
H
H
H
H
H
H
H
H
H
H
H
H
PWM1P0
PB1
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1M0
PB2
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2P0
PB3
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2M0
PB4
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1P1
PB5
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1M1
PB6
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2P1
PB7
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2M1
PC0
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1P2
PC1
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1M2
PC2
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2P2
PC3
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2M2
DVCC
PWM output pin of stepping motor controller
Power supply input pins for SMC
GND pins for SMC
52
53
⎯
⎯
DVSS
(Continued)
6
MB91245/S Series
I/O circuit
type*
Pin no.
Pin name
P97 to P90
Function
General-purpose I/O port pins : Valid when analog input is pro-
hibited
54 to 61
E
E
Analog input pins of A/D converter : Valid when ADER register is
set to analog input
AN31 to AN24
P87 to P80
General-purpose I/O port pins : Valid when analog input is pro-
hibited
62 to 69
Analog input pins of A/D converter : Valid when ADER register is
set to analog input
AN23 to AN16
70
71
72
AVCC
AVRH
⎯
⎯
⎯
Analog power supply input pin for A/D converter
Analog base voltage input pin for A/D converter
AVSS/AVRL
Analog GND/analog base low voltage input pin for A/D converter
General-purpose I/O port pins : Valid when analog input is pro-
hibited
P60 to P67
AN0 to AN7
PF0 to PF7
AN8 to AN15
73 to 80
81 to 88
E
E
Analog input pins of A/D converter : Valid when ADER register is
set to analog input
General-purpose I/O port pins : Valid when analog input is pro-
hibited
Analog input pins of A/D converter : Valid when ADER register is
set to analog input
89
90
DVCC
DVSS
⎯
⎯
Power supply input pins for SMC
GND pins for SMC
PA0
General purpose I/O port pin
91
92
93
94
95
96
97
98
H
H
H
H
H
H
H
H
PWM1P3
PA1
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1M3
PA2
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2P3
PA3
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2M3
PE0
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1P4
PE1
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM1M4
PE2
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2P4
PE3
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2M4
PWM output pin of stepping motor controller
(Continued)
7
MB91245/S Series
I/O circuit
type*
Pin no.
Pin name
Function
General purpose I/O port pin
PE4
PWM1P5
PE5
99
H
H
H
H
PWM output pin of stepping motor controller
General purpose I/O port pin
100
101
102
PWM1M5
PE6
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2P5
PE7
PWM output pin of stepping motor controller
General purpose I/O port pin
PWM2M5
DVCC
PWM output pin of stepping motor controller
Power supply input pins for SMC
GND pins for SMC
103
104
⎯
⎯
DVSS
Mode pin 2 : Used to set basic operating mode and required to
be connected to VCC or VSS
105
106
MOD2
MOD1
D
D
Mode pin 1 : Used to set basic operating mode and required to
be connected to VCC or VSS
Mode pin 0 : Used to set basic operating mode and required to
be connected to VCC or VSS
107
108
MOD0
INIT
D
C
External reset input pin
General-purpose I/O port pin : Valid when UART0 data input is
prohibited
P40
109
I
UART0 serial data input pin, requiring output by ports to be
stopped while UART0 is performing input operation, except
when executed intentionally, as this input is always in use
SIN0
General-purpose I/O port pin : Valid when UART0 data output is
prohibited
P41
SOT0
P42
110
111
I
I
UART0 serial data output pin : Valid when UART0 data output is
permitted
General-purpose I/O port pin : Valid when clock output of
UART0 is prohibited
UART0 clock input and output pin for serial communication :
Valid when clock output of UART0 is permitted
SCK0
P43
General-purpose I/O port pin : Valid when LIN-UART0 data
input is prohibited
112
113
I
I
LIN-UART0 serial data input pin, requiring output by ports to be
stopped while LIN-UART0 is performing input operation, except
when executed intentionally, as this input is always in use
SIN3
General-purpose I/O port pin : Valid when LIN-UART0 data
output is prohibited
P44
LIN-UART0 serial data output pin : Valid when data output of
LIN-UART0 is permitted
SOT3
(Continued)
8
MB91245/S Series
I/O circuit
type*
Pin no.
Pin name
Function
General-purpose I/O port pin : Valid when clock output of
LIN-UART0 is prohibited
P45
114
I
LIN-UART0 clock input and output pin for serial communication :
Valid when clock output of LIN-UART0 is permitted
SCK3
P50
General-purpose I/O port pin
Serial data input pin of LIN-UART1 : LIN-UART1, requiring output
by ports to be stopped while LIN-UART1 is performing input
operation, except when executed intentionally, as this input is
always in use
SIN4
115
I
CK0
CS0
External clock input pin of free-run timer 0
Output pin of chip select 0 : Valid when external bus mode is
selected
P51
General-purpose I/O port pin
LIN-UART1 serial data output pin : Valid when data output of
LIN-UART1 is permitted
SOT4
116
117
I
I
Output pin of chip select 1 : Valid when output of chip select 1 is
permitted
CS1
P52
General-purpose I/O port pin
LIN-UART1 clock input and output pin for serial communication :
Valid when clock output of LIN-UART1 is permitted
SCK4
Output pin of chip select 2 : Valid when output of chip select 2 is
permitted
CS2
P53
General-purpose I/O port pin
Serial data input pin of LIN-UART2 : LIN-UART2, requiring output
by ports to be stopped while LIN-UART2 is performing input
operation, except when executed intentionally, as this input is
always in use
SIN5
118
I
CK1
CS3
External clock input pin of free-run timer 1
Output of chip select 3 : Valid when output of chip select 3 is
permitted
P54
General-purpose I/O port pin
Serial data output pin of LIN-UART2 : Valid when data output of
LIN-UART2 is permitted
SOT5
119
120
I
I
Read strobe output pin of external bus : Valid when external bus
mode is selected
RD
P55
General-purpose I/O port pin
LIN-UART2 clock input and output pin for serial communication :
Valid when clock output of LIN-UART2 is permitted
SCK5
Write strobe output pin of external bus : Valid when WR0 output
is permitted in external bus mode
WR0
(Continued)
9
MB91245/S Series
I/O circuit
type*
Pin no.
Pin name
Function
General-purpose I/O port pin
P56
OUT0
Output compare output pin
121
I
J
I
Write strobe output pin of external bus : Valid when WR1 output
is permitted in external bus mode
WR1
P57
General-purpose I/O port pin
Output compare output pin
OUT1
122
123
External ready input pin : Valid when external ready input is
permitted
RDY
P46
General-purpose I/O port pin
Sound generator pin
SGA
External address strobe output pin : Valid when address strobe
output is permitted
AS
P47
General-purpose I/O port pin
Sound generator pin
SGO
124
125
I
I
System clock output pin : Valid when system clock output is
permitted and outputs the same clock as the operating
frequency of external bus (Output is stopped in STOP mode)
SYSCLK
PG0
General-purpose I/O port pin
Output of PPG timer 0 : Valid when output of PPG timer 0 is
permitted
PPG0
126
127
128
129
VCC
VSS
⎯
⎯
A
Power supply pins
GND pins
X1
Main clock (oscillation) output pin
Main clock (oscillation) input pin
General-purpose I/O port pin
Output pin for reload timer
X0
A
PG1
TOT0
130
131
132
I
I
I
Output pin of PPG timer 2 : Valid when output of PPG timer 2 is
permitted
PPG2
PG2
General-purpose I/O port pin
Output pin for reload timer
TOT1
Output pin of PPG timer 4 : Valid when output of PPG timer 4 is
permitted
PPG4
PG3
General-purpose I/O port pin
Output pin for reload timer
TOT2
Output pin of PPG timer 6 : Valid when output of PPG timer 6 is
permitted
PPG6
(Continued)
10
MB91245/S Series
(Continued)
I/O circuit
type*
Pin no.
Pin name
Function
PD0
General-purpose I/O port pin
TIN0
Event input pin for reload timer
Trigger input pin of input capture 0 : This sets input capture to
trigger input and is enabled when input port is set up. When set
as input capture input, it requires output by ports to be stopped,
except when executed intentionally, as this input is always
used.
133
K
IN0
Input pin of pulse width counter 0 of PWC0 : Valid when input of
pulse width counter 0 of PWC0 is permitted
PWC0
PD1
General-purpose I/O port pin
Event input pin for reload timer
TIN1
Trigger input pin of input capture 1 : This sets input capture to
trigger input and is enabled when input port is set up. When set
as input capture input, it requires output by ports to be stopped,
except when executed intentionally, as this input is always
used.
134
K
IN1
PD2
General-purpose I/O port pin
Event input pin for reload timer
TIN2
Trigger input pin of input capture 2 : This sets input capture to
trigger input and is enabled when input port is set up. When set
as input capture input, it requires output by ports to be stopped,
except when executed intentionally, as this input is always
used.
135
136
K
K
IN2
PD3
IN3
General-purpose I/O port pin
Trigger input pin of input capture 3 : This sets input capture to
trigger input and is enabled when input port is set up. When set
as input capture input, it requires output by ports to be stopped,
except when executed intentionally, as this input is always
used.
PD4 to PD7
General-purpose I/O port pin
COM0 to COM3
Output pin of COM0 to COM3 of LCDC
137 to 140
141 to 144
F
F
PPG1, PPG3,
PPG5, PPG7
Output pin of PPG timer 1, 3, 5 and 7 : Valid when output of PPG
timer 1, 3, 5 and 7 is permitted
P20 to P23
SEG00 to SEG03
A00 to A03
General purpose I/O port pins
SEG output pins for LCDC
Bits 00 to 03 pins of external address bus
* : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
11
MB91245/S Series
■ I/O CIRCUIT TYPE
Group
Circuit Type
Remarks
For high speed (source oscillation of
main clock)
X1
X0
• Oscillation circuit
• Feedback resistance X0 :
approx. 1 MΩ
Clock input
A
Standby control
For low speed (source oscillation of
sub clock)
X1A
X0A
• Oscillation circuit
• Feedback resistance X0A :
approx. 7 MΩ
Clock input
B
Standby control
• CMOS hysteresis input
• Pull-up resistor provided
• No standby control
P-ch
P-ch
N-ch
C
R
Digital input
(Continued)
12
MB91245/S Series
Group
Circuit Type
MASK ROM product
Remarks
• MASK ROM product
Hysteresis input
Pull-down resistor provided only for
MOD2 & MOD1
R
Hysteresis input
N-ch
N-ch
• Flash memory product
Hysteresis input
High-voltage control for Flash test
provided
Flash memory product
D
N-ch
N-ch
Control
N-ch
R
Mode input
Diffused resistor
• CMOS output (4 mA)
P-ch
• Hysteresis (Automotive level) input
(Standby control provided)
• Analog input
(Analog input is valid when the
corresponding ADER bit is set to 1.)
Digital output
Digital output
N-ch
E
R
Digital input
Standby control
Analog input
• CMOS output (4 mA)
• LCDC output
• Hysteresis (Automotive level) input
(Standby control provided)
P-ch
N-ch
F
R
R
LCDC output
Hysteresis input
Standby control
(Continued)
13
MB91245/S Series
Group
Circuit Type
Remarks
• CMOS output (4 mA)
• LCDC output
• Hysteresis (Automotive level) input
(Standby control provided)
• Hysteresis (CMOS level) input
(Standby control provided)
P-ch
N-ch
R
R
G
LCDC output
Hysteresis input
(Automotive level)
R
Hysteresis input
(CMOS level)
Standby control
• CMOS output
P-ch
N-ch
High current output for PWM (30 mA)
• Hysteresis (Automotive level) input
(Standby control provided)
Digital output
Digital output
H
R
Digital input
Standby control
• CMOS output (4 mA)
P-ch
N-ch
• Hysteresis (Automotive level) input
(Standby control provided)
Digital output
Digital output
I
R
Digital input
Standby control
(Continued)
14
MB91245/S Series
(Continued)
Group
Circuit Type
Remarks
• CMOS output (4 mA)
P-ch
N-ch
• Hysteresis (Automotive level) input
(Standby control provided)
• Hysteresis (CMOS level) input
(Standby control provided)
R
R
J
Hysteresis input
(Automotive level)
Hysteresis input
(CMOS level)
Standby control
• Hysteresis (Automotive level) input
(Standby control provided)
P-ch
N-ch
K
R
Digital input
Standby control
15
MB91245/S Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC, if a voltage greater than VCC pin or less than VSS pin is applied to input and
output pin, or if an above-rating voltage is applied between VCC and VSS. When latch-up occurs, it may significantly
increase the power supply current, and may cause thermal destruction of an element. When you use a CMOS
IC, be very careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by performing a pull-up or
pull-down with a resistance of 2 kΩ or more. An unused I/O pin should be set to the output status and left open.
When set to the input status, it should be handled in the same way as an input pin.
• About power supply pins
If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential
are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the
pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal
operation of strobe signals caused by the rise in the ground level, and to conform to the total output current
rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC
and VSS near this device.
This device incorporates a regulator. When using the device with 5V power supply, apply that power supply to
the VCC pin and always connect a 1 µF or greater capacitor to the VCC3C for the regulator.
Example of power supply connection
5 V
5 V
VCC
AVCC
AVRH
AVSS
VSS
VCC3C
1 µF
GND
16
MB91245/S Series
• Crystal oscillator circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the PC board such
that X0/X1 pins, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to the
ground are placed as near one another as possible. When routing the X0 and X1 signals, they should be shielded
for use on the board. Caution must be taken especially when using a pin next to the X0.
It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by
ground plane because stable operation can be expected with such a layout.
In addition, a sub clock is required even when a dual clock product is used as a single clock product.
When using MB91F248S/248S/247S, connect the X0A pin to GND and leave the X1A pin open.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Mode pins (MOD0 to MOD2)
These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to test
mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS pins is
as short as possible and the connection impedance is now.
• Operation at start-up
Always use the INIT pin to perform a setting initialization reset (INIT) after power-on. Immediately after power-
on, hold the low level input to the INIT pin for the stabilization wait time required for the oscillator circuit, to take
the oscillation stabilization wait time for the oscillator circuit.
For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.
• Source oscillation input upon power-on
When power-on, always input the clock for the duration of the oscillation stabilization delay time.
• Treatment of power supply pins on A/D converter
Connect to ensure “AVCC = AVRH = VCC and AVSS = VSS” even if the A/D converter is not in use.
• Power-on sequence for power supply analog input of A/D converter
Always supply power to the A/D converter (AVCC and AVRH) and apply analog input (AN0 to AN 31) after turning
on the digital power supply (VCC). Also, turn off the power supply for the A/D converter and analog input before
turning off the digital power supply (VCC). In so doing, the power supply must be turn on and off so that AVRH
does not exceed AVCC. Even when using a pin shared with analog input as an input port, ensure that the input
voltage does not exceed AVCC (There is no problem in turning on or off the analog and digital power supplies at
the same time).
• Handling of power supply for high-current output buffer pin (DVCC, DVSS)
Always apply power to high-current output buffer pins (DVCC) after turning on the digital power supply (VCC). In
addition, turn off the power supply for the high-current output buffer pins before turning off the digital power
supply (VCC).
Apply the same power as for high-current output buffer pins even when using such pins as general-purpose
ports. (There is no problem in turning on or off the power supply for the high-current output buffer pins and the
digital power supply at the same time.)
AlwaysusetheGNDpin(DVSS)forthehigh-currentoutputbufferpinatthesamepotentialasthedigitalGND(VSS).
17
MB91245/S Series
• About switching from main clock mode to sub clock mode or stop mode
Always stop the main clock after switching the main clock mode to the sub clock mode or stop mode. Also secure
theoscillationstabilizationwaittimewhenreturningfromthesubclockmodeorstopmodetothemainclockmode.
• About Flash write
Note that Flash write is not possible in the sub mode.
18
MB91245/S Series
■ BLOCK DIAGRAM
FR 60Lite
CPU core
32
32
DMAC
5 channels
Bit search
32
ROM 256 Kbytes/
128 Kbytes/
Flash 256 Kbytes
Bus
converter
RAM
16 Kbytes/8 Kbytes
32
adapters
16
C-CAN
2 channels
RX0, RX1
TX0, TX1
X0, X1
X0A, X1A*
MOD0 to MOD2
INIT
Clock
control
16
Port I/F
PORT
Interrupt
controller
Reload timer
3 channels
TIN0 to TIN2
TOT0 to TOT2
external interrupt
8 channels
INT0 to INT7
PWC timer
1 channel
SIN0
SOT0
SCK0
PWC0
UART
1 channel
4 channels (when set to
16 bits) 8/16-bit PPG timer
PPG0 to PPG7
U-TIMER 1 channel
ICU2
ICU3
ICU
4 channels
IN0 to IN3
Real Time Clock
ICU0
ICU1
CPU Detect Reset
OCU
2 channels
OCU0
OCU1
OUT0, OUT1
CK0, CK1
FRT
2 channels
FRT0
FRT1
PWM1P0 to PWM1P5
PWM1M0 to PWM1M5
PWM2P0 to PWM2P5
PWM2M0 to PWM2M5
6 channels
Stepper Motor
Controller
SGA
SGO
Sound
Generator
ATG
AVCC/AVSS
AVRH
8/10-bit
32 channels input
A/D converter
AN0 to AN31
SIN3 to SIN5
SOT3 to SOT5
SCK3 to SCK5
LIN-UART
3 channels
LCD controller
32 SEG × 4 COM
COM0 to COM3
SEG00 to SEG31
* : The sub clock is not supported in single clock products.
19
MB91245/S Series
■ MEMORY SPACE
• Memory space
The FR family has of 4 Gbytes logical address space (232 addresses) linearly accessible to the CPU space.
• Direct addressing area
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during on instruction.
The direct area varies depending on the size of data to be accessed as follows.
→ Byte data access
→ Halfword data access : 000H to 1FFH
→ Word data access : 000H to 3FFH
: 000H to 0FFH
20
MB91245/S Series
■ MEMORY MAP
MB91V245A
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
0000 0000
H
H
Direct
addressing area
I/O
I/O
I/O
0000 0400
I/O
I/O
I/O
Refer to “■ I/O MAP”.
0001 0000
0002 0000
H
H
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
0002 01B4
H
Access prohibited
Internal RAM 32 KB
Access prohibited
Internal RAM 32 KB
Access prohibited
Internal RAM 32 KB
0003 8000
0004 0000
H
H
Access prohibited
Access prohibited
Access prohibited
0005 0000
0008 0000
H
H
Emulation
Emulation
SRAM area
SRAM area
External area
0010 0000
H
Access prohibited
External area
FFFF FFFF
H
21
MB91245/S Series
MB91F248/S
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
0000 0000
H
H
Direct
addressing area
I/O
I/O
I/O
0000 0400
I/O
I/O
I/O
Refer to “■ I/O MAP”.
0001 0000
0002 0000
H
H
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
Access prohibited
I/O (C-CAN)
0002 01B4
H
Access prohibited
Internal RAM 16 KB
Access prohibited
Internal RAM 16 KB
Access prohibited
Internal RAM 16 KB
0003 C000
H
0004 0000
0005 0000
000C 0000
H
Access prohibited
H
Access prohibited
Access prohibited
H
Flash memory
area
256 Kbytes
Flash memory
area
256 Kbytes
External area
0010 0000
H
Access prohibited
External area
FFFF FFFF
H
MB91248/S
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
0000 0000H
0000 0400H
Direct
addressing area
I/O
I/O
I/O
I/O
I/O
I/O
Refer to “■ I/O MAP”.
0001 0000H
0002 0000H
Access prohibited
Access prohibited
Access prohibited
I/O (C-CAN)
I/O (C-CAN)
I/O (C-CAN)
0002 01B4H
0003 C000H
0004 0000H
Access prohibited
Internal RAM 16 KB
Access prohibited
Internal RAM 16 KB
Access prohibited
Internal RAM 16 KB
Access prohibited
External area
Access prohibited
Access prohibited
0005 0000H
000C 0000H
MASK ROM
area
256 Kbytes
MASK ROM
area
256 Kbytes
0010 0000H
FFFF FFFFH
Access prohibited
External area
Note : Each mode is set depending on the mode vector fetch after INIT is negated (For mode settings, refer to
“■ MODE SETTINGS”).
22
MB91245/S Series
MB91247/S
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
0000 0000H
Direct
I/O
I/O
I/O
addressing area
0000 0400H
I/O
I/O
I/O
Refer to “■ I/O MAP”.
0001 0000H
0002 0000H
Access prohibited
Access prohibited
Access prohibited
I/O (C-CAN)
I/O (C-CAN)
I/O (C-CAN)
0002 01B4H
0003 E000H
0004 0000H
Access prohibited
Access prohibited
Internal RAM 8 KB
Access prohibited
Internal RAM 8 KB
Internal RAM 8 KB
Access prohibited
Access prohibited
Access prohibited
0005 0000H
000E 0000H
MASK ROM
area
MASK ROM
area
External area
128 Kbytes
128 Kbytes
0010 0000H
FFFF FFFFH
Access prohibited
External area
Note : Each mode is set depending on the mode vector fetch after INIT is negated (For mode settings, refer to
“■ MODE SETTINGS”).
23
MB91245/S Series
■ MODE SETTINGS
The FR family, sets the operation mode using mode pins (MOD2 to MOD0) and mode data.
• Mode pins
The mode pins (MOD2 to MOD0) specify how the mode vector fetch and reset vector fetch is performed.
Other settings than these in the table are prohibited.
Mode pin
Mode name
Reset vector access area
MOD2
MOD1
MOD0
0
0
0
0
0
1
Internal ROM mode vector
External ROM mode vector
Internal
External
• Mode data
Data written to the internal mode register (MODR) by mode vector fetch is called mode data.
After an operating mode has been set in the mode register the device operates in that operating mode.
The mode data is set by all reset sources. User programs cannot set data to the mode register.
Detailed description of mode data
bit
31
0
30
0
29
0
28
0
27
0
26
1
25
1
24
1
Operating mode
setting bits
Bit 31 to bit 24 are reserved.
Always set the value to “00000111B”. Normal operation is not guaranteed when a value other than “00000111B”
is set.
Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8H.
Place the data in the most significant byte from bit 31 to bit 24 as the FR family uses the big endian system
for byte endian.
bit
31
24 23
16 15
8 7
0
Incorrect
Correct
0x000FFFF8
H
XXXXXXXX
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
XXXXXXXX
0x000FFFF8
H
Reset vector
0x000FFFFC
H
24
MB91245/S Series
■ I/O MAP
The following table shows the correspondence between the memory space area and each register of the pe-
ripheral resource.
[How to read the map]
Register
Address
Block
+ 0
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+ 1
+ 2
+ 3
T-unit
Port data register
000000H
Read/Write attribute, Access unit
(B : byte, H : halfword, W : word)
Initial value after reset
Register name (First-column register at address 4n; second-column
register at 4n + 1, etc.)
Location of left-most register (When using word access, the register in
column 1 is in the MSB side of the data.)
Note :
Initial values of register bits are represented as follows :
“ 1 ” : Initial value “1”
“ 0 ” : Initial value “0”
“ X ” : Initial value “undefined”
“ - ” : No physical register present at this location
Access by any undescribed data access attribute is prohibited.
25
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
PDR0 [R/W] B, H
XXXXXXXX
PDR1 [R/W] B, H
XXXXXXXX
PDR2 [R/W] B, H
00000000
PDR3 [R/W] B, H
XXXX0000
00000000H
00000004H
00000008H
0000000CH
00000010H
PDR4 [R/W] B, H
XXXXXXXX
PDR5 [R/W] B, H
XXXXXXXX
PDR6 [R/W] B, H
XXXXXXXX
PDR7 [R/W] B, H
----XXXX
PDR8 [R/W] B, H
XXXXXXXX
PDR9 [R/W] B, H
XXXXXXXX
PDRA [R/W] B, H
----XXXX
PDRB [R/W] B, H
XXXXXXXX
Port Data
Register
PDRC [R/W] B, H
----XXXX
PDRD [R/W] B, H
0000XXXX
PDRE [R/W] B, H
XXXXXXXX
PDRF [R/W] B, H
XXXXXXXX
PDRG [R/W] B, H
----XXXX
⎯
00000014H
to
0000003CH
⎯
Reserved
External
Interrupt Control
(INT0 to INT7)
EIRR0 [R/W] B, H, W ENIR0 [R/W] B, H, W
ELVR0 [R/W] B, H, W
00000000 00000000
00000040H
00000000
00000000
DICR [R/W] B, H, W
-------0
HRCL [R/W] B
0--11111
Delay Interrupt
Module
00000044H
00000048H
0000004CH
00000050H
00000054H
00000058H
0000005CH
00000060H
00000064H
⎯
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
Reload Timer 0
Reload Timer 1
Reload Timer 2
TMCSR0 [R/W] B, H, W
----0000 00000000
⎯
00001000
TMRLR1 [W] H, W
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
TMCSR1 [R/W] B, H, W
----0000 00000000
⎯
TMRLR2 [W] H, W
XXXXXXXX XXXXXXXX
TMR2 [R] H, W
XXXXXXXX XXXXXXXX
TMCSR2 [R/W] B, H, W
----0000 00000000
⎯
SSR [R/W] B, H, W SIDR [R/W] B, H, W SCR [R/W] B, H, W SMR [R/W] B, H, W
UART0
00001000
XXXXXXXX
00000100
00--0-0-
UTIM [R] H (UTIMR [W] H)
00000000 00000000
DRCL [W] B
--------
UTIMC [R/W] B
0--00001
U-TIMER0
00000068H
to
0000008CH
⎯
Reserved
SGDBL [R/W] B
-------0
SGCR [R/W] B, H, W
0-----00 000--000
00000090H
00000094H
⎯
Sound
Generator
SGAR [R/W] B, H, W SGFR [R/W] B, H, W SGTR [R/W] B, H, W SGDR [R/W] B, H, W
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
26
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
LCDCMR [R/W]
B, H, W
LCR0 [R/W]
B, H, W
00010000
LCR1 [R/W]
B, H, W
00000000
00000098H
⎯
----0000
VRAM0 [R/W]
B, H, W
XXXXXXXX
VRAM1 [R/W]
B, H, W
XXXXXXXX
VRAM2 [R/W]
B, H, W
XXXXXXXX
VRAM3 [R/W]
B, H, W
XXXXXXXX
0000009CH
000000A0H
000000A4H
000000A8H
VRAM4 [R/W]
B, H, W
XXXXXXXX
VRAM5 [R/W]
B, H, W
XXXXXXXX
VRAM6 [R/W]
B, H, W
XXXXXXXX
VRAM7 [R/W]
B, H, W
XXXXXXXX
LCD
Controller
Driver
VRAM8 [R/W]
B, H, W
XXXXXXXX
VRAM9 [R/W]
B, H, W
XXXXXXXX
VRAM10 [R/W]
B, H, W
XXXXXXXX
VRAM11 [R/W]
B, H, W
XXXXXXXX
VRAM12 [R/W]
B, H, W
VRAM13 [R/W]
B, H, W
VRAM14 [R/W]
B, H, W
VRAM15 [R/W]
B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
000000A8H
to
000000AFH
⎯
Reserved
RDR3/TDR3 [R/W]
B, H, W
SCR3 [R/W] B, H, W SMR3 [R/W] B, H, W SSR3 [R/W] B, H, W
000000B0H
000000B4H
000000B8H
000000BCH
000000C0H
000000C4H
00000000
00000000
00001000
--------
LIN-UART0
ESCR3 [R/W]
B, H, W
ECCR3 [R/W]
B, H, W
BGR13 [R/W]
B, H, W
BGR03 [R/W]
B, H, W
XXXXXXXX
00000X00
000000XX
XXXXXXXX
RDR4/TDR4 [R/W]
B, H, W
SCR4 [R/W] B, H, W SMR4 [R/W] B, H, W SSR4 [R/W] B, H, W
00000000
00000000
00001000
--------
LIN-UART1
ESCR4 [R/W]
B, H, W
ECCR4 [R/W]
B, H, W
BGR14 [R/W]
B, H, W
BGR04 [R/W]
B, H, W
XXXXXXXX
00000X00
000000XX
XXXXXXXX
RDR5/TDR5 [R/W]
B, H, W
SCR5 [R/W] B, H, W SMR5 [R/W] B, H, W SSR5 [R/W] B, H, W
00000000
00000000
00001000
--------
LIN-UART2
Reserved
ESCR5 [R/W]
B, H, W
ECCR5 [R/W]
B, H, W
BGR15 [R/W]
B, H, W
BGR05 [R/W]
B, H, W
00000X00
000000XX
XXXXXXXX
XXXXXXXX
000000C8H
to
000000D0H
⎯
TCCS0 [R/W]
B, H, W
00000000
TCDT0 [R/W] H, W
00000000 00000000
16-bit Free
Run Timer0
000000D4H
000000D8H
⎯
⎯
TCCS1 [R/W]
B, H, W
00000000
TCDT1 [R/W] H, W
00000000 00000000
16-bit Free
Run Timer1
(Continued)
27
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
000000DCH
to
000000E0H
⎯
Reserved
IPCP1 [R] H, W
000000E4H
IPCP0 [R] H, W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
16-bit Input
Capture 0, 1
ICS01 [R/W] B, H, W
00000000
000000E8H
000000ECH
000000F0H
⎯
IPCP3 [R] H, W
XXXXXXXX XXXXXXXX
IPCP2 [R] H, W
XXXXXXXX XXXXXXXX
16-bit Input
Capture 2, 3
ICS23 [R/W] B, H, W
00000000
⎯
000000F4H
to
00000104H
⎯
⎯
⎯
⎯
Reserved
OCCP1 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP0 [R/W] H, W
XXXXXXXX XXXXXXXX
00000108H
0000010CH
00000110H
16-bit Output
Compare
OCS01 [R/W] B, H, W
11101100 00001100
⎯
00000114H
to
0000012CH
Reserved
16-bit PWC
Reserved
PWCSR0 [R/W] B, H, W
0000000X 00000000
PWCR0 [R] H, W
00000000 00000000
00000130H
00000134H
PDIVR0 [R/W]
00000138H
⎯
B, H, W
-----000
⎯
0000013CH
to
00000140H
⎯
WTDBL [R/W] B
-------0
WTCR [R/W] B, H
00000000 000-00-0
00000144H
00000148H
0000014CH
00000150H
⎯
⎯
WTBR [R/W] B
---XXXXX XXXXXXXX XXXXXXXX
Real Time
Clock
WTHR [R/W] B, H
---XXXXX
WTMR [R/W] B, H
--XXXXXX
WTSR [R/W] B
--XXXXXX
⎯
ADERH [R/W] B, H, W
00000000 00000000
ADERL [R/W] B, H, W
00000000 00000000
A/D Converter
ADCS1 [R/W]
B, H, W
00000000
ADCS0 [R/W]
B, H, W
00000000
ADCR1 [R]
B, H, W
------XX
ADCR0 [R]
B, H, W
XXXXXXXX
00000154H
(Continued)
28
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
ADCT1 [R/W]
B, H, W
00010000
ADCT0 [R/W]
B, H, W
00101100
ADSCH [R/W]
B, H, W
ADECH [R/W]
00000158H
B, H, W
---00000
A/D Converter
---00000
CUCR [R/W] B, H, W
CUTD [R/W] B, H, W
10000000 00000000
0000015CH
00000160H
-------- ---0--00
Clock
Caliblator
CUTR1 [R] B, H, W
-------- 00000000
CUTR2 [R] B, H, W
00000000 00000000
PWC20 [R/W]
PWC10 [R/W]
B, H, W
00000164H
00000168H
0000016CH
00000170H
00000174H
00000178H
0000017CH
00000180H
00000184H
00000188H
0000018CH
00000190H
B, H, W
⎯
Reserved
XXXXXXXX
XXXXXXXX
PWS20 [R/W]
B, H, W
-0000000
PWS10 [R/W]
B, H, W
PWC0 [R/W] B
-0000--0
⎯
--000000
PWC21 [R/W]
B, H, W
XXXXXXXX
PWC11 [R/W]
B, H, W
XXXXXXXX
⎯
⎯
⎯
⎯
⎯
PWS21 [R/W]
B, H, W
-0000000
PWS11 [R/W]
B, H, W
PWC1 [R/W] B
-0000--0
⎯
--000000
PWC22 [R/W]
B, H, W
XXXXXXXX
PWC12 [R/W]
B, H, W
XXXXXXXX
PWS22 [R/W]
B, H, W
-0000000
PWS12 [R/W]
B, H, W
PWC2 [R/W] B
-0000--0
⎯
--000000
SteppingMotor
Controller
PWC23 [R/W]
B, H, W
XXXXXXXX
PWC13 [R/W]
B, H, W
XXXXXXXX
PWS23 [R/W]
B, H, W
-0000000
PWS13 [R/W]
B, H, W
PWC3 [R/W] B
-0000--0
⎯
--000000
PWC24 [R/W]
B, H, W
XXXXXXXX
PWC14 [R/W]
B, H, W
XXXXXXXX
PWS24 [R/W]
B, H, W
-0000000
PWS14 [R/W]
B, H, W
PWC4 [R/W] B
-0000--0
⎯
--000000
PWC25 [R/W]
B, H, W
XXXXXXXX
PWC15 [R/W]
B, H, W
XXXXXXXX
PWS25 [R/W]
B, H, W
-0000000
PWS15 [R/W]
B, H, W
PWC5 [R/W] B
-0000--0
⎯
--000000
(Continued)
29
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
00000194H
to
000001A4H
⎯
Reserved
CANPRE [R/W]
CAN
Prescaler
000001A8H
B, H, W
00000000
Reserved
⎯
000001ACH
000001B0H
⎯
Reserved
TRG [R/W] B, H, W
00000000
REVC [R/W] B, H, W
00000000
⎯
⎯
PRLH0 [R/W]
B, H, W
XXXXXXXX
PRLL0 [R/W]
B, H, W
XXXXXXXX
PRLH1 [R/W]
B, H, W
XXXXXXXX
PRLL1 [R/W]
B, H, W
XXXXXXXX
000001B4H
000001B8H
000001BCH
000001C0H
000001C4H
000001C8H
PPG0
PRLH2 [R/W]
B, H, W
XXXXXXXX
PRLL2 [R/W]
B, H, W
XXXXXXXX
PRLH3 [R/W]
B, H, W
XXXXXXXX
PRLL3 [R/W]
B, H, W
XXXXXXXX
PPGC0 [R/W]
B, H, W
0000000X
PPGC1 [R/W]
B, H, W
0000000X
PPGC2 [R/W]
B, H, W
0000000X
PPGC3 [R/W]
B, H, W
0000000X
PRLH4 [R/W]
B, H, W
XXXXXXXX
PRLL4 [R/W]
B, H, W
XXXXXXXX
PRLH5 [R/W]
B, H, W
XXXXXXXX
PRLL5 [R/W]
B, H, W
XXXXXXXX
PRLH6 [R/W]
B, H, W
XXXXXXXX
PRLL6 [R/W]
B, H, W
XXXXXXXX
PRLH7 [R/W]
B, H, W
XXXXXXXX
PRLL7 [R/W]
B, H, W
XXXXXXXX
PPG0
PPGC4 [R/W]
B, H, W
PPGC5 [R/W]
B, H, W
PPGC6 [R/W]
B, H, W
PPGC7 [R/W]
B, H, W
0000000X
0000000X
0000000X
0000000X
000001CCH
to
000001FCH
⎯
Reserved
DMACA0 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00000200H
00000204H
00000208H
0000020CH
00000210H
00000214H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMACA1 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMAC
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMACA2 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
(Continued)
30
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
DMACA3 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00000218H
0000021CH
00000220H
00000224H
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMACA4 [R/W] B, H, W *1
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMAC
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
00000228H
to
0000023CH
⎯
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
00000240H
00000244H
to
000003ECH
⎯
Reserved
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000003F0H
000003F4H
000003F8H
000003FCH
00000400H
00000404H
00000408H
0000040CH
00000410H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit Search
Module
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDR0 [R/W] B, H, W DDR1 [R/W] B, H, W DDR2 [R/W] B, H, W DDR3 [R/W] B, H, W
00000000 00000000 11111111 00001111
DDR4 [R/W] B, H, W DDR5 [R/W] B, H, W DDR6 [R/W] B, H, W DDR7 [R/W] B, H, W
00000000 00000000 00000000 ----0000
DDR8 [R/W] B, H, W DDR9 [R/W] B, H, W DDRA [R/W] B, H, W DDRB [R/W] B, H, W Port Direction
00000000
00000000
----0000
00000000
Register
DDRC [R/W] B, H, W DDRD [R/W] B, H, W DDRE [R/W] B, H, W DDRF [R/W] B, H, W
----0000
1111----
00000000
00000000
DDRG [R/W] B, H, W
----0000
⎯
00000414H
to
0000041CH
⎯
Reserved
PFR0 [R/W] B, H, W PFR1 [R/W] B, H, W PFR2 [R/W] B, H, W PFR3 [R/W] B, H, W
00000420H
00000424H
00000000
PFR4 [R/W] B, H, W PFR5 [R/W] B, H, W
00000000 00000000
00000000
00000000
00000000
Port Function
Register
PFR7 [R/W] B, H, W
----0000
⎯
(Continued)
31
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
PFRA [R/W] B, H, W PFRB [R/W] B, H, W
00000428H
0000042CH
00000430H
⎯
----0000
PFRC [R/W] B, H, W PFRD [R/W] B, H, W PFRE [R/W] B, H, W
00000000
Port Function
Register
⎯
----0000
00000000
00000000
PFRG [R/W] B, H, W
----0000
⎯
00000434H
to
0000043CH
⎯
Reserved
ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W
00000440H
00000444H
00000448H
0000044CH
00000450H
00000454H
00000458H
0000045CH
00000460H
00000464H
00000468H
0000046CH
---11111
ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W
---11111 ---11111 ---11111 ---11111
---11111
---11111
---11111
Interrupt
Control Unit
00000470H
to
0000047CH
⎯
Reserved
RSRR [R/W] B, H, W STCR [R/W] B, H, W TBCR [R/W] B, H, W CTBR [W] B, H, W
00000480H
00000484H
00000488H
10000000
00110011
00XXXX11
XXXXXXXX
CLKR [W] B, H, W WPR [R/W] B, H, W DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W Clock Control
00000000
XXXXXXXX
00000011
00000000
Unit
OSCCR [R/W] B
X000XXX0
⎯
⎯
(Continued)
32
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
0000048CH
00000490H
⎯
Clock Control
Unit
OSCR [R/W] B
000--001
⎯
00000494H
to
000004F8H
⎯
⎯
Reserved
PSCR [W] B
XXXXXXXX
PortInputLevel
Select Register
000004FCH
⎯
00000500H
to
0000053CH
Reserved
PILR0 [R/W] B, H, W PILR1 [R/W] B, H, W
00000540H
00000544H
⎯
00000000
00000000
PILR5 [R/W] B, H, W
0-------
⎯
⎯
PortInputLevel
Select Register
00000548H
to
00000550H
⎯
00000554H
to
00000578H
⎯
Reserved
LVRC [R/W] B, H, W
CPU Detection
of operation
0000057CH
Reserved
Reserved
Reserved
00011000
00000580H
to
000005FCH
⎯
⎯
⎯
Reserved
EPFR2 [R/W]
B, H, W
00000000
EPFR3 [R/W]
B, H, W
00000000
00000600H
⎯
Extended
Port Function
Register
EPFR4 [R/W]
B, H, W
00000000
EPFR5 [R/W]
B, H, W
00000000
00000604H
00000608H
0000060CH
⎯
⎯
EPFRD [R/W]
B, H, W
00000000
⎯
Extended
Port Function
Register
EPFRG [R/W]
B, H, W
00000610H
⎯
----0000
00000614H
to
0000063CH
Reserved
(Continued)
33
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
ASR0 [R/W] B, H, W
00000000 00000000
ACR0 [R/W] B, H, W
1111XX00 00000000
00000640H
00000644H
00000648H
0000064CH
ASR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ASR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ASR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
External Bus
Control Unit
00000650H
to
0000065CH
⎯
⎯
AWR0 [R/W] B, H, W
01110000 01011011
AWR1 [R/W] B, H, W
XXXX0000 XX0X1XXX
00000660H
00000664H
AWR2 [R/W] B, H, W
0XXX0000 XX0X1XXX
AWR3 [R/W] B, H, W
0XXX0000 0X0X1XXX
00000668H
to
0000067CH
Reserved
CSER [R/W] B, H, W
External Bus
Control Unit
00000680H
⎯
XXXX0001
00000684H
to
000007F8H
⎯
⎯
Reserved
Mode register
Reserved
000007FCH
⎯
MODR *2
⎯
00000800H
to
00000FFCH
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001000H
00001004H
00001008H
0000100CH
00001010H
00001014H
00001018H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
34
MB91245/S Series
Register
Address
Block
+ 0
+ 1
DMADA3 [R/W] W
+ 2
+ 3
0000101CH
00001020H
00001024H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00001028H
to
00006FFCH
⎯
Reserved
FLCR [R/W]
01XX1000
Flash I/F
(Only Mass
Production
Product)
00007000H
00007004H
⎯
⎯
FLWC [R/W]
00000011
00007008H
to
0000FFFCH
⎯
Reserved
00020000H
00020004H
00020008H
0002000CH
00020010H
00020014H
00020018H
0002001CH
00020020H
00020024H
CTRLR0
STATR0
BTR0
ERRCNT0
INTR0
TESTR0
⎯
BRPER0
IF1CREQ0
IF1MSK20
IF1ARB20
IF1MCTR0
IF1DTA10
IF1DTB10
IF1CMSK0
IF1MSK10
IF1ARB10
⎯
IF1DTA20
IF1DTB20
00020028H,
0002002CH
CAN0
⎯
00020030H
00020034H
Reserved (IF1 data A mirror, little endian byte ordering)
Reserved (IF1 data B mirror, little endian byte ordering)
00020038H,
0002003CH
⎯
00020040H
00020044H
00020048H
0002004CH
00020050H
00020054H
IF2CREQ0
IF2MSK20
IF2ARB20
IF2MCTR0
IF2DTA10
IF2DTB10
IF2CMSK0
IF2MSK10
IF2ARB10
⎯
IF2DTA20
IF2DTB20
(Continued)
35
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
00020058H,
0002005CH
⎯
00020060H
00020064H
Reserved (IF2 data A mirror, little endian byte ordering)
Reserved (IF2 data B mirror, little endian byte ordering)
00020068H,
0002007CH
⎯
00020080H
00020084H
TREQR20
TREQR10
Reserved ( > 32..128 Message buffer)
00020088H,
0002008CH
⎯
00020090H
00020094H
NEWDT20
NEWDT10
CAN0
Reserved ( > 32..128 Message buffer)
00020098H,
0002009CH
⎯
000200A0H
000200A4H
INTPEND20
INTPEND10
Reserved ( > 32..128 Message buffer)
000200A8H,
000200ACH
⎯
000200B0H
000200B4H
MESVAL20
MESVAL10
Reserved ( > 32..128 Message buffer)
000200B8H,
000200FCH
⎯
00020100H
00020104H
00020108H
0002010CH
00020110H
00020114H
00020118H
0002011CH
00020120H
00020124H
CTRLR1
STATR1
BTR1
ERRCNT1
INTR1
TESTR1
⎯
BRPER1
IF1CREQ1
IF1MSK21
IF1ARB21
IF1MCTR1
IF1DTA11
IF1DTB11
IF1CMSK1
IF1MSK11
IF1ARB11
⎯
CAN1
IF1DTA21
IF1DTB21
00020128H,
0002012CH
⎯
00020130H
00020134H
Reserved (IF1 data A mirror, little endian byte ordering)
Reserved (IF1 data B mirror, little endian byte ordering)
00020138H,
0002013CH
⎯
(Continued)
36
MB91245/S Series
(Continued)
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
00020140H
00020144H
00020148H
0002014CH
00020150H
00020154H
IF2CREQ1
IF2MSK21
IF2ARB21
IF2MCTR1
IF2DTA11
IF2DTB11
IF2CMSK1
IF2MSK11
IF2ARB11
⎯
IF2DTA21
IF2DTB21
00020158H,
0002015CH
⎯
00020160H
00020164H
Reserved (IF2 data A mirror, little endian byte ordering)
Reserved (IF2 data B mirror, little endian byte ordering)
00020168H,
0002017CH
⎯
00020180H
00020184H
TREQR21
TREQR11
Reserved ( > 32..128 Message buffer)
CAN1
00020188H,
0002018CH
⎯
00020190H
00020194H
NEWDT21
NEWDT11
Reserved ( > 32..128 Message buffer)
00020198H,
0002019CH
⎯
000201A0H
000201A4H
INTPND21
INTPND11
Reserved ( > 32..128 Message buffer)
000201A8H,
000201ACH
⎯
000201B0H
000201B4H
MESVAL21
MESVAL11
Reserved ( > 32..128 Message buffer)
000201B8H,
000201FCH
⎯
00038000H
to
003FFFFCH
F-bus RAM
32 Kbytes
⎯
⎯
⎯
0003C000H
to
003FFFFCH
F-bus RAM
16 Kbytes
0003E000H
to
003FFFFCH
F-bus RAM
8 Kbytes
*1 : The lower 16 bits (DTC [15 : 0]) of DMACA0 to DMACA4 cannot be accessed in bytes.
*2 : This register is set by a mode vector fetch and cannot be accessed by the user.
37
MB91245/S Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
User ROM
256 Kbytes
(Only Mass
000C0000H
to
000FFFFCH
⎯
ProductionProduct)
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
000E0000H
to
000FFFFCH
User ROM
128 Kbytes
(MB91247)
⎯
38
MB91245/S Series
■ VECTOR TABLE
Interrupt number
DMA
Interrupt
level
TBR default
address
Interrupt source
Offset
start
Hexa-
Decimal
source
decimal
Reset
0
1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Mode vector
System reserved
System reserved
System reserved
System reserved
System reserved
Coprocessor absent trap
Coprocessor error trap
INTE instruction
2
3
4
5
6
7
8
9
System reserved
System reserved
Step trace trap
10
11
12
13
14
NMI request (ICE)
Undefined instruction exception
15 (FH)
Fixed
NMI instruction
15
0F
3C0H
000FFFC0H
⎯
External interrupt 0
16
17
18
19
20
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
6
7
External interrupt 1
External interrupt 2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
9
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Reload timer 0 (Underflow)
Reload timer 1 (Underflow)
Reload timer 2 (Underflow)
UART0 (Reception completed/error)
UART0 (Transmission completed)
10
0
3
LIN-UART0 (Reception completed/
error, LIN Sync break, bus idle)
29
1D
ICR13
388H
000FFF88H
1
(Continued)
39
MB91245/S Series
Interrupt number
DMA
start
source
Interrupt
level
TBR default
address
Interrupt source
Offset
Hexa-
Decimal
decimal
LIN-UART0 (Transmission
completed)
30
31
32
33
34
1E
1F
20
21
22
ICR14
ICR15
ICR16
ICR17
ICR18
384H
380H
37CH
378H
374H
000FFF84H
000FFF80H
000FFF7CH
000FFF78H
000FFF74H
4
2
LIN-UART1 (Reception completed/
error, LIN Sync break, bus idle)
LIN-UART1 (Transmission
completed)
5
LIN-UART2 (Reception completed/
error, LIN Sync break, bus idle)
⎯
⎯
LIN-UART2 (Transmission
completed)
CAN0 Reception/Transmission com-
pleted
Node status transition
35
36
23
24
ICR19
ICR20
370H
36CH
000FFF70H
000FFF6CH
⎯
⎯
CAN1 Reception/Transmission com-
pleted
Node status transition
System reserved
37
38
39
40
41
42
43
25
26
27
28
29
2A
2B
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
368H
364H
360H
35CH
358H
354H
350H
000FFF68H
000FFF64H
000FFF60H
000FFF5CH
000FFF58H
000FFF54H
000FFF50H
⎯
⎯
⎯
⎯
⎯
⎯
14
System reserved
System reserved
PWC (Measurement completed)
PWC (Overflow)
DMAC transfer completed/error
A/D converter
Real-time clock
Hour/minute/second overflow,
corrected
44
2C
ICR28
34CH
000FFF4CH
⎯
System reserved
45
46
2D
2E
ICR29
ICR30
348H
344H
000FFF48H
000FFF44H
⎯
⎯
Main oscillation stabilization wait
timer
Timebase timer overflow
PPG0/1 underflow
PPG2/3 underflow
PPG4/5 underflow
PPG6/7 underflow
47
48
49
50
51
2F
30
31
32
33
ICR31
ICR32
ICR33
ICR34
ICR35
340H
33CH
338H
334H
330H
000FFF40H
000FFF3CH
000FFF38H
000FFF34H
000FFF30H
⎯
⎯
⎯
⎯
⎯
16-bit free-run timer 0
Overflow & OCU0 Compare match
clear
52
34
ICR36
32CH
000FFF2CH
⎯
(Continued)
40
MB91245/S Series
(Continued)
Interrupt source
Interrupt number
DMA
Interrupt
level
TBR default
address
Offset
start
Hexa-
Decimal
source
decimal
16-bit free-run timer 1 Overflow
ICU0 (Capture)
53
54
55
56
57
58
59
60
61
35
36
37
38
39
3A
3B
3C
3D
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
000FFF28H
000FFF24H
000FFF20H
000FFF1CH
000FFF18H
000FFF14H
000FFF10H
000FFF0CH
000FFF08H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ICU1 (Capture)
ICU2 (Capture)
ICU3 (Capture)
OCU0 (Match)
OCU1 (Match)
System reserved
System reserved
Sound generator setup count
completed
62
3E
ICR46
304H
000FFF04H
⎯
Delay interrupt source bit
63
64
65
3F
40
41
ICR47
⎯
300H
2FCH
2F8H
000FFF00H
000FFEFCH
000FFEF8H
⎯
⎯
⎯
System reserved (Used by REALOS)
System reserved (Used by REALOS)
⎯
66
to
79
42
to
4F
2F4H
to
2C0H
000FFEF4H
to
000FFEC0H
System reserved
⎯
⎯
⎯
⎯
80
to
255
50
to
FF
2BCH
to
000H
000FFEBCH
to
000FFC00H
Used by INT instruction
41
MB91245/S Series
■ TABLE OF PIN STATUS IN EACH MODE
• Single chip mode
Initial value
In stop state
HIZ = 0 HIZ = 1
Pin
name
In sleep
state
Function name
INIT = “L”
INIT = “H”
INIT
X0
INIT
X0
Input enabled Input enabled
Hi-Z or input Hi-Z or input
enabled
enabled
”H” output or ”H” output or
input enabled input enabled
X1
X1
Hi-Z or input Hi-Z or input
Input
enabled
Input
enabled
Input
enabled
X0A
X1A
X0A
X1A
enabled
enabled
”H” output or ”H” output or
input enabled input enabled
MOD0
MOD1
MOD2
P00
MOD0
MOD1
Input enabled Input enabled
MOD2
P00/SEG24/INT0/D00
P01/SEG25/INT1/D01
P02/SEG26/INT2/D02
P03/SEG27/INT3/D03
P04/SEG28/INT4/D04
P :
Immediately Operation or
P01
preceding
status held
F :
output held
during LCDC
output,
P02
P03
Operation or otherwise
output held output Hi-Z /
P04
during LCDC INT0 to INT5
output; INT0 input enabled
to INT5 input when PFR0
enabledwhen register is set
PFR0register to “0”
Output Hi-Z Output Hi-Z
input
input
P05
P05/SEG29/INT5/D05
enabled
enabled
P :
Immediately
preceding
status held
F :
is set to “0”
P06
P07
P06/SEG30/D06
P07/SEG31/ATG/D07
Normal
operation
performed
P :
P10
to
P17
P10 to P17/
SEG16 to SEG23/
D08 to D15
Immediately
Operation or
preceding
output held
status held
during LCDC
F :
Operation or
Otherwise
output held
output Hi-Z/
during LCDC
Input fixed to
output;
P20
to
P27
P20 to P27/
SEG00 to SEG07/
A00 to A07
output;
“L” output
“L” output
P30
to
P33
P30 to P33/
SEG08 to SEG11/
A08 to A11
“0”
Otherwise
Hi-Z
P34
to
P37
P34 to P37/
SEG12 to SEG15/
A12 to A15
Output Hi-Z Output Hi-Z
input
enabled
input
enabled
(Continued)
42
MB91245/S Series
Initial value
INIT = “L” INIT = “H”
In stop state
Pin
name
In sleep
state
Function name
HIZ = 0
HIZ = 1
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN3
P44/SOT3
P45/SCK3
P46/SGA/AS
P :
P47/SGO/SYSCLK
P50/SIN4/CK0/CS0
P51/SOT4/CS1
P52/SCK4/CS2
P53/SIN5/CK1/CS3
P54/SOT5/RD
P55/SCK5/WR0
P56/OUT0/WR1
P57/OUT1/RDY
Immediately
preceding
status held
F :
Outputheldor
Hi-Z
Output Hi-Z /
Input fixed to
“0”
P :
Immediately
preceding
status held
F :
Output Hi-Z Output Hi-Z
P60
to
P67
input
input
P60 to P67/AN0 to AN7
enabled
enabled
Normal
operation
performed
P :
Immediately
preceding
status held
F :
Output held,
INT6 input
enabled
Output Hi-Z /
INT6 input
enabledwhen
PFR7register
is set to “1”
P70
P71
P72
P70/RX0/INT6
P :
Immediately
preceding
status held,
F : Hi-Z
Output Hi-Z /
Input fixed to
“0”
P71/TX0
P :
Immediately
preceding
status held
F :
Output held,
INT7 input
enabled
Output Hi-Z /
INT7 input
enabledwhen
PFR7register
is set to “1”
P72/RX1/INT7
(Continued)
43
MB91245/S Series
(Continued)
Initial value
INIT = “L” INIT = “H”
In stop state
Pin
In sleep
state
Function name
name
HIZ = 0
HIZ = 1
P73
P73/TX0
P80
to
P80 to P87/AN16 to AN23
P87
P90
to
P97
P :
P :
P90 to P97/AN24 to AN31
Immediately
preceding
status held
F :
Normal
operation
performed
Immediately
preceding
status held
F :
Outputheldor
Hi-Z
Output Hi-Z Output Hi-Z
Output Hi-Z /
Input fixed to
“0”
PA0
to
PA3
input
input
PA0 to PA3/
PWMxxx to PWMxxx
enabled
enabled
PB0
to
PB7
PB0 to PB7/
PWMxxx to PWMxxx
PC0
to
PC3
PC0 to PC3/
PWMxxx to PWMxxx
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD0/TIN0/IN0/PWC0
PD1/TIN1/IN1
Input
enabled
Input
enabled
Input enabled
Hi-Z
PD2/TIN2/IN2
PD3/IN3
PD4/COM0/PPG1
PD5/COM1/PPG3
PD6/COM2/PPG5
P :
Input fixed to
“0”
Immediately
preceding
status held
LCDC :
“L” output
“L” output
Output or hold
PPG :
Output held
PD7
PD7/COM3/PPG7
P :
Immediately
preceding
status held
F :
Normal
operation
performed
PE0
to
PE7
PE0 to PE7/
PWMxxx to PWMxxx
P :
PF0
to
PF7
Immediately
preceding
status held
F :
Outputheldor
Hi-Z
PF0 to PF7/AN8 to AN15
Output Hi-Z Output Hi-Z
Output Hi-Z /
Input fixed to
“0”
Input
Input
enabled
enabled
PG0
PG1
PG2
PG3
PG0/ (WOT) /PPG0
PG1/TOT0/PPG2
PG2/TOT1/PPG4
PG3/TOT2/PPG6
44
MB91245/S Series
• External bus mode (8-bit)
Initial value
In stop mode
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 0
HIZ = 1
INIT
X0
INIT
X0
Input enabled
Input enabled
Hi-Z or input
enabled
Hi-Z or input
enabled
”H” output or
input enabled
”H” output or
input enabled
X1
X1
Hi-Z or input
enabled
Hi-Z or input
enabled
Input
enabled
Input
enabled
Input
enabled
X0A
X1A
X0A
X1A
”H” output or
input enabled
”H” output or
input enabled
MOD0
MOD1
MOD2
MOD0
MOD1
MOD2
Input enabled
Input enabled
P00/SEG24/
INT0
P00
P01
P02
P03
P04
P05
P :
P01/SEG25/
INT1
Immediately
preceding status held
F :
Operation or output
held during LCDC
output; INT0 to INT5
input enabled when
PFR0 register is set
to “0”
Operation or output
held during LCDC
output, otherwise
output Hi-Z / INT0 to
INT5 input enabled
when PFR0 register
is set to “0”
P02/SEG26/
INT2
P03/SEG27/
INT3
P :
Immediately
preceding status
held
P04/SEG28/
INT4
Output
Hi-Z input Hi-Z input
enabled
Output
F :
P05/SEG29/
INT5
Normal operation
performed
enabled
P06 P06/SEG30
P :
Immediatelypreceding
status held
F :
Operation or output
held during LCDC
output,
Operation or output
held during LCDC
output, otherwise
output Hi-Z / Input
fixed to “0”
P07/SEG31/
P07
ATG
otherwise Hi-Z
P10
to
P17
Output Hi-Z / Input
fixed to “0”
D08 to D15
A00 to A07
A08 to A11
Hi-Z
Hi-Z
P20
to
P27
Output Hi-Z / Input
fixed to “0”
“L” output “H” output F : Address output F : Address output
P30
to
P33
(Continued)
45
MB91245/S Series
Initial value
In stop mode
HIZ = 0
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 1
P34
to
P37
Output
A12 to A15 Hi-Z input “H” output F : Address output
enabled
F : Address output
P40
P41
P42
P43
P44
P45
P40/SIN0
P :
P :
P41/SOT0
Immediately preceding Immediatelypreceding
status held
F :
Normal operation
performed
Output
Hi-Z input
enabled
P42/SCK0
P43/SIN3
P44/SOT3
P45/SCK3
status held
F :
Output held or Hi-Z
P :
P :
Immediately preceding Immediatelypreceding
status held,
“H” output AS : “H” output,
F :
status held,
AS : “H” output,
F : Output held
P46/SGA/
AS
P46
P47
Normal operation
performed
P :
P :
Output Hi-Z /
Input fixed to “0”
Immediately preceding Immediatelypreceding
Output
Hi-Z input
enabled
status held,
CLK : CLK output,
F :
status held,
CLK : “H” or “L” output,
F : Output held
P47/SGO/
SYSCLK
CLK
output
Normal operation
performed
P50/SIN4/
CK0/CS0
P50
P51
P52
P53
P54
P55
P51/SOT4/
CS1
Bus control :
“H” output
P :
Bus control :
“H” output
P :
P52/SCK4/
CS2
Immediately preceding Immediatelypreceding
“H” output
status held
F :
status held
F :
P53/SIN5/
CK1/CS3
Normal operation
performed
Output held or Hi-Z
P54/SOT5/
RD
P55/SCK5/
WR0
(Continued)
46
MB91245/S Series
Initial value
In stop mode
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 0
HIZ = 1
P :
P :
Immediatelypreceding Immediatelypreceding
status held
F :
Normal operation
performed; “H”
output when EPFR is set to “0”
set to “0”
status held
F :
Output held; “H”
output when EPFR is
P56
P57
P56/OUT0
“H” output
Output
Hi-Z input
enabled
Output Hi-Z /
Input fixed to “0”
P :
P :
Immediatelypreceding Immediatelypreceding
status held
F :
P57/OUT1/
RDY
status held
F :
RDY input
Normal status,
RDY input
Output held,
RDY input
P :
P60
to
P67
Immediatelypreceding
status held
F :
P60 to P77/
AN0 to AN7
Output Hi-Z /
Input fixed to “0”
Output held or Hi-Z
P :
Output Hi-Z /
INT6 input
enabled when
PFR7registeris
set to “1”
Immediatelypreceding
status held
F :
Output held,
INT6 input enabled
P70/RX0/
INT6
P70
P71
P72
P :
Immediately
preceding status held
F :
Normal operation
performed
OutputHi-Z OutputHi-Z
input
input
enabled
enabled
P :
Immediatelypreceding Output Hi-Z /
P71/TX0
status held,
F : Hi-Z
Input fixed to “0”
P :
Output Hi-Z /
INT7 input
enabled when
PFR7registeris
set to “1”
Immediatelypreceding
status held
F :
Output held,
INT7 input enabled
P72/RX1/
INT7
(Continued)
47
MB91245/S Series
(Continued)
Initial value
In stop mode
HIZ = 0
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 1
P80
to
P87
P80 to P87/
AN16 to AN23
P90
to
P97
P90 to P97/
AN24 to AN31
P :
Immediately
P :
Immediately
PA0 PA0 to PA3/ OutputHi-Z OutputHi-Z preceding status preceding status held
Output Hi-Z / Input
fixed to “0”
to
PWMxxx to
PWMxxx
input
input
held
F :
PA3
enabled
enabled F :
Normal operation
Normal operation performed
performed
PB0 PB0 to PB7/
to
PWMxxx to
PWMxxx
PB7
PC0 PC0 to PC3/
to
PC3
PWMxxx to
PWMxxx
PD0/TIN0/
IN0/PWC0
PD0
Input
enabled
Input
enabled
PD1
PD2
PD3
PD1/TIN1
PD2/TIN2
PD3/IN3
Input enabled
Hi-Z
PD4/COM0/
PPG1
PD4
PD5
PD6
PD7
Input fixed to “0”
P :
PD5/COM1/
PPG3
Immediatelypreceding
status held
LCDC :
Output or hold
PPG : Output held
“L” output
“L” output
PD6/COM2/
PPG5
PD7/COM3/
PPG7
P :
PE0 PE0 to PE7/
Immediately
preceding status
held
to
PE7
PWMxxx to
PWMxxx
PF0
to
PF7
F :
PF0 to PF7/
AN8 to AN15
Normal operation
performed
P :
OutputHi-Z OutputHi-Z
Immediately
preceding status held
F :
PG0/ (WOT) /
PPG0
Output Hi-Z / Input
fixed to “0”
PG0
PG1
PG2
PG3
Input
Input
enabled
enabled
PG1/TOT0/
PPG2
Output held or Hi-Z
PG2/TOT1/
PPG4
PG3/TOT2/
PPG6
48
MB91245/S Series
• External bus mode (16-bit)
Initial value
In stop mode
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 0
HIZ = 1
INIT
X0
INIT
X0
Input enabled
Input enabled
Hi-Z or input
enabled
Hi-Z or input
enabled
”H” output or input
enabled
”H” output or input
enabled
X1
X1
Hi-Z or input
enabled
Hi-Z or input
enabled
Input
enabled
Input
enabled
Input
enabled
X0A
X1A
X0A
X1A
”H” output or input
enabled
”H” output or input
enabled
MOD0
MOD1
MOD2
P00
MOD0
MOD1
MOD2
D00
Input enabled
Input enabled
P01
D01
P02
D02
P03
D03
P04
D04
Output
Output
Hi-Z input Hi-Z input
Hi-Z
Hi-Z
P05
D05
enabled
enabled
P06
D06
P07
D07
P10
to
P17
D08 to D15
A00 to A07
A08 to A11
A12 to A15
P20
to
P27
Output Hi-Z
Input fixed to “0”
“L” output
P30
to
P33
“H” output F : Address output F : Address output
P34
to
P37
P40
P41
P42
P43
P44
P45
P40/SIN0
P41/SOT0
P42/SCK0
P43/SIN3
P44/SOT3
P45/SCK3
P :
P :
Output
Hi-Z input
enabled
Immediately
Immediately
Output
Hi-Z input held
enabled F :
preceding status preceding status
held
F :
Normal operation Output held or Hi-Z
performed
(Continued)
49
MB91245/S Series
Initial value
In stop mode
HIZ = 0
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 1
P :
P :
Immediatelypreceding Immediatelypreceding
status held,
status held,
P46 P46/SGA/AS
“H” output AS : “H” output,
F :
AS : “H” output,
F : Output held
Normal operation
performed
P :
P :
Immediatelypreceding Immediatelypreceding
status held,
CLK : CLK output,
F :
Normal operation
performed
status held,
CLK : “H” or “L” output,
F : Output held
P47/SGO/
P47
CLK
output
Output
Hi-Z input
enabled
SYSCLK
Output Hi-Z
Input fixed to “0”
P50/SIN4/
P50
Bus control :
“H” output
P :
Immediatelypreceding Immediatelypreceding
status held
F :
Bus control :
“H” output
P :
CK0/CS0
P51/SOT4/
P51
CS1
“H” output
status held
F :
Output held or Hi-Z
P52/SCK4/
P52
CS2
Normal operation
performed
P53/SIN5/
P53
CK1/CS3
P54/SOT5/
Bus control :
“H” output
P :
Immediatelypreceding Immediatelypreceding
status held
F :
Bus control :
“H” output
P :
P54
RD
P55/SCK5/
P55
WR0
“H” output
status held
F :
Output held or Hi-Z
P56/OUT0/
Output
Hi-Z input
enabled
P56
Normal operation
performed
Output Hi-Z /
Input fixed to “0”
WR1
P :
P :
Immediatelypreceding Immediatelypreceding
P57/OUT1/
status held
F :
Normal status,
RDY input
status held
F : Output held,
RDY input
P57
RDY input
Output
RDY
P :
P :
Immediately
preceding status held status held
F :
Normal operation
performed
Immediatelypreceding
P60
Output
P60 to P77/
to
Output Hi-Z /
Input fixed to “0”
Hi-Z input Hi-Z input
AN0 to AN7
P67
F :
enabled
enabled
Output held or Hi-Z
(Continued)
50
MB91245/S Series
Initial value
In stop mode
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 0
HIZ = 1
P :
Output Hi-Z /
INT6 input
enabled when
PFR7registeris
set to “1”
Immediatelypreceding
status held
F :
Output held,
INT6 input enabled
P70/RX0/
INT6
P70
P71
P72
P :
Immediately
P :
OutputHi-Z OutputHi-Z
preceding status held Immediatelypreceding Output Hi-Z /
F :
Normal operation
performed
P71/TX0
input
input
status held,
F : Hi-Z
Input fixed to “0”
enabled
enabled
P :
Output Hi-Z /
INT7 input
enabled when
PFR7registeris
set to “1”
Immediatelypreceding
status held
F :
Output held,
INT7 input enabled
P72/RX1/
INT7
P80 P80 to P87/
to
P87
AN16 to
AN23
P90 P90 to P97/
to
P97
AN24 to
AN31
P :
P :
Immediately
preceding status held
F :
Normal operation
performed
Immediately
preceding status held
F :
Normal operation
performed
PA0 PA0 to PA3/ OutputHi-Z OutputHi-Z
Output Hi-Z/
Input fixed to “0”
to
PA3
PWMxxx to
PWMxxx
input
enabled
input
enabled
PB0 PB0 to PB7/
to
PB7
PWMxxx to
PWMxxx
PC0 PC0 to PC3/
to
PC3
PWMxxx to
PWMxxx
PD0/TIN0/
IN0/PWC0
PD0
Input
enabled
Input
enabled
PD1
PD2
PD3
PD1/TIN1
PD2/TIN2
PD3/IN3
Input enabled
Hi-Z
Input fixed to “0”
(Continued)
51
MB91245/S Series
(Continued)
Initial value
In stop mode
HIZ = 0
Pin
name
Function
name
In sleep mode
INIT = “L” INIT = “H”
HIZ = 1
PD4/COM0/
PPG1
PD4
PD5
PD6
PD7
P :
PD5/COM1/
PPG3
Immediatelypreceding
status held
LCDC :
Output or hold
PPG : Output held
“L” output
“L” output
Input fixed to “0”
PD6/COM2/
PPG5
PD7/COM3/
PPG7
P :
PE0 PE0 to PE7/
Immediately
preceding status
held
to
PE7
PWMxxx to
PWMxxx
PF0
to
PF7
F :
PF0 to PF7/
AN8 to AN15
Normal operation
performed
P :
OutputHi-Z OutputHi-Z
Immediately
preceding status held
F :
PG0/ (WOT) /
PPG0
Output Hi-Z / Input
fixed to “0”
PG0
PG1
PG2
PG3
Input
Input
enabled
enabled
PG1/TOT0/
PPG2
Output held or Hi-Z
PG2/TOT1/
PPG4
PG3/TOT2/
PPG6
52
MB91245/S Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VSS + 6.0
VSS + 6.0
VSS + 6.0
VSS + 6.0
VCC + 0.3
VCC + 0.3
15
VCC
AVCC
VAVRH
DVCC
VI
VSS − 0.3
V
V
VSS − 0.3
AVCC = VCC*2
AVCC ≥ VAVRH
DVCC = VCC*2
Power supply voltage*1
VSS − 0.3
V
VSS − 0.3
V
Input voltage*1
Output voltage*1
VSS − 0.3
V
VO
VSS − 0.3
⎯
V
IOL1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
*5
*6
*5
*6
*5
*6
*5
*6
*5
*6
*5
*6
*5
*6
*5
*6
“L” level maximum output
current*3
IOL2
⎯
40
IOLAV1
IOLAV2
ΣIOL1
⎯
4
“L” level average output
current*4
⎯
30
⎯
120
“L” level total maximum
output current
ΣIOL2
⎯
330
ΣIOLAV1
ΣIOLAV2
IOH1*3
IOH2*3
IOHAV1*4
IOHAV2*4
ΣIOH1
ΣIOH2
ΣIOHAV1*7
ΣIOHAV2*7
PD
⎯
50
“L” level total average
output current
⎯
240
⎯
−15
“H” level maximum output
current
⎯
−40
⎯
−4
“H” level average output
current
⎯
−30
⎯
−120
−330
−50
“H” level total maximum
output current
⎯
⎯
“H” level total average
output current
⎯
−240
660
Power consumption
Operating temperature
Storage temperature
⎯
MASK ROM product
(in single chip operation)
−40
−40
+105
+105
°C
°C
Flash memory product
(in single chip operation)
TA
MASK ROM/Flash memory product
(in external bus operation)
−40
−55
⎯
+85
+150
2
°C
°C
Tstg
IIHH
+B input standard
(Maximum clamp current)
mA
Exclusive of dedicated input pins*8
+B input standard
(Total maximum clamp
current)
ΣIIHH
⎯
20
mA
(Continued)
53
MB91245/S Series
(Continued)
*1 : The parameter is base on VSS = AVSS = DVSS = 0.0 V.
*2 : Caution must be taken that AVCC and DVCC do not exceed VCC upon power-on and under other circumstances.
*3 : The maximum output current defines the peak current value of each of the corresponding pins.
*4 : The average output current defines the average value of the current (100 ms) which passes through each of
the corresponding pins. The average value represents a value calculated by multiplying the operating current
by the operating rate.
*5 : Output other than PA0 to PA3 pins, PB0 to PB7 pins, PC0 to PC3 pins, and PE0 to PE7 pins
*6 : (PA0 to PA3 pins, PE0 to PE7 pins) + (PB0 to PB7 pins, PC0 to PC3 pins)
The SMC pins are divided into two groups (12 pins each) and the value is calculated as the total current per
group.
*7 : The total average output current defines the average value of the current (100 ms) which passes through all
the corresponding pins. The average value represents a value calculated by multiplying the operating current
by the operating rate.
*8 : +B input standard defines the current value for each of the corresponding pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
54
MB91245/S Series
2. Recommended Operating Conditions
Rating
(VSS = DVSS = AVSS = 0.0 V)
Parameter
Symbol
Unit
Remarks
Min
Max
Recommended guaranteed operating range
(MB91F248, MB91248)
Guaranteed operating range*1
(MB91F248, MB91248)
4.5
5.5
V
V
VCC
AVCC
DVCC
Power supply
voltage
3.5
2.0
5.5
5.5
Guaranteed operating range for holding
stop operation status*2
V
(MB91F248, MB91248)
Smoothing
capacitor*3
Use a ceramic capacitor or a capacitor with
similar frequency characteristics.
CS
1
µF
°C
°C
°C
MASK ROM product
(in single chip operation)
−40
−40
−40
+105
+105
+85
Operating
temperature
Flash memory product
(in single chip operation)
TA
MASK ROM/Flash memory product
(in external bus operation)
*1 : Exclusive of A/D operation
*2 : Internal voltage held in RAM : 1.8 V (Min) /3.6 V (Max)
*3 : For how to connect the smoothing capacitor CS, refer to the figure below.
• C Pin Connection Diagram
C
VSS
DVSS
AVSS
CS
< + B input (12 V to 16 V) conditions>
• Do not connect +B potential directly to a microcontroller pin.
• Always connect a resistor between the microcontroller pin and +B signal to limit the current.
lIHH = 2 mA per pin (Max.) [In the steady state and transient state between power-on and power-off, etc.]
It can be connected to any general-purpose input port except the output pin for LCDC.
• The protection diode in the microcontroller turns the potential upon +B input between the limiting resistor and
microcontroller pin into “VCC + protection diode ON voltage”. Configure the circuit so that these are not
interfered and the potential is not exceeded.
55
MB91245/S Series
Recommended example circuit
MB91245/S series
lIHH
Protection diode
+B Input (12 V to 16 V)
Current limiting resistor
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
56
MB91245/S Series
3. DC Specifications
Sym-
(TA : Recommended operating conditions; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V)
Value
Parameter
Pin name
Condition
Unit
Remarks
bol
Min
Typ
Max
Automotive level
input pins*1
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
P00 to P07,
P10 to P17, P57
CMOS hysteresis
input pins*2
MOD pins*3
“H” level
input
voltage
VIH
VIHM
VIHX
⎯
⎯
⎯
0.7 VCC
VCC − 0.3
0.8 VCC
⎯
⎯
⎯
VCC + 0.3
VCC + 0.3
⎯
V
V
V
⎯
X0, X1, X0A, X1A,
INIT
Automotive level
input pins*1
VILS
⎯
⎯
VSS − 0.3
⎯
0.5 VCC
V
P00-P07,
P10-P17, P57
CMOS hysteresis
input pins*2
MOD pins*3
“L” level
input
voltage
VIL
VILM
VILX
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
⎯
⎯
0.3 VCC
Vss + 0.3
0.2 VCC
V
V
V
⎯
X0, X1, X0A, X1A,
INIT
Flash memory
product
⎯
55
85
mA
Operating frequency :
FCP = 32 MHz in main
mode
ICC
⎯
⎯
55
85
mA MASK ROM product
mA In Flash-Write mode
100
150
Operating frequency :
FCP = 32 kHz, TA = +25 °C
in sub mode
Power
ICCL
⎯
290
450
µA
supply
VCC
current*4
TA = +25 °C, Vcc = 5V in
stop mode (oscillation
stopped)
ICCH
ICTS
IIL
⎯
⎯
−5
95
390
⎯
150
500
+5
µA
TA = +25 °C, Vcc = 5V in
stop mode (RTC in use)
µA At 4 MHz
µA
Input
leak
current
VCC = DVCC =
All input pins
AVCC = 5.5 V
VSS < VI < VCC
OtherthanVcc, VSS,
DVcc, DVSS, AVcc,
AVSS, PA0 to PA3,
PB0 to PB7,
PC0 to PC3,
PE0 to PE7
Input
capacity 1
CIN1
⎯
⎯
5
15
pF
pF
PA0 to PA3,
PB0 to PB7,
PC0 to PC3,
PE0 to PE7
Input
capacity 2
CIN2
⎯
⎯
⎯
15
50
45
Pull-up
resistance
RUP INIT
25
100
kΩ
(Continued)
57
MB91245/S Series
(Continued)
(TA : Recommended operating conditions; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V)
Value
Typ
Sym-
bol
Parameter
Pull-down
Pin name
Condition
Unit Remarks
Min
Max
MASK ROM
kΩ products
only
RDOWN MOD1, MOD2
⎯
25
50
100
resistance
Other than
PA0 to PA3,
VOH1 PB0 to PB7,
PC0 to PC3,
Output “H”
voltage 1
Vcc = 4.5 V
IOH = −4.0 mA
VCC −
0.5
⎯
⎯
⎯
V
PE0 to PE7
PA0 to PA3,
Output “H”
voltage 2
PB0 to PB7,
PC0 to PC3,
PE0 to PE7
Vcc = 4.5 V
IOH = −30.0 mA
VCC −
0.5
VOH2
⎯
⎯
⎯
⎯
V
Other than
PA0 to PA3,
VOL1 PB0 to PB7,
PC0 to PC3,
Output “L”
voltage 1
Vcc = 4.5 V
IOL = 4.0 mA
⎯
⎯
0
0.4
0.55
90
V
PE0 to PE7
PA0 to PA3,
PB0 to PB7,
PC0 to PC3,
PE0 to PE7
Output “L”
voltage 2
Vcc = 4.5 V
VOL2
V
IOL = 30.0 mA
PWM1Pn,
PWM1Mn,
∆VOH2 PWM2Pn,
High current output
Drive capacity
Phase-to-phase
deviation 1
Vcc = 4.5 V
IOH = 30.0 mA
Maximum
mV *5
PWM2Mn,
n = 0 to 5
deviation of VOH2
High current
output
Drive capacity
Phase-to-phase
deviation 2
PWM1Pn,
PWM1Mn,
∆VOL2 PWM2Pn,
Vcc = 4.5 V
IOL = 30.0 mA
Maximum
0
⎯
90
mV *5
PWM2Mn,
n = 0 to 5
deviation of VOL2
COM0 to COM3
Output impedance
COMm
(m = 0 to 3)
RVCOM
⎯
⎯
⎯
⎯
⎯
2.5
30
kΩ
kΩ
SEG00 to SEG31
Output impedance
SEGn
(n = 00 to 31)
RVSEG
15
COMm
(m = 0 to 3) ,
SEGn,
LCDC leak current
ILCDC
TA = +25 °C
−0.5
⎯
+0.5
µA
(n = 00 to 31)
*1 : All input pins except X0, X1, X0A, X1A, MOD0, MOD1, MOD2 and INIT pins
*2 : Can be selected by the input level select register (PILR).
*3 : MOD0, MOD1 and MOD2
*4 : They represent current values used when supplying power to the external clock from pin X1.
*5 : DefinedbythemaximumdeviationofVOH2/VOL2 ofeachpin, whenPWM1P0, PWM1M0, PWM2P0andPWM2M0
in ch.0 are simultaneously turned on. The same applies to other channels.
58
MB91245/S Series
4. Flash Memory Write/Erase Characteristics
Value
Parameter
Condition
Unit
Remarks
Min
Typ
Max
TA = +25 °C,
Vcc = 5.0 V
Exclusive of internal write time
prior to erase
Sector erase time
Chip erase time
⎯
1
5
15
s
s
TA = +25 °C,
Vcc = 5.0 V
Exclusive of internal write time
prior to erase
⎯
⎯
⎯
TA = +25 °C,
Vcc = 5.0 V
Exclusive of overhead time at
system level
Halfword write time
16
3600
µs
TA = +25 °C,
Vcc = 5.0 V
Exclusive of overhead time at
system level
Chip write time
⎯
10000
10
2.1
⎯
⎯
⎯
⎯
s
Erase/write cycle
⎯
cycle
year
Flash memory data
retain time
TA = +85 °C
(average)
⎯
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
59
MB91245/S Series
5. AC Specifications
(1) Clock timing
(TA : Recommended operating conditions; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V)
Value
Typ
4
Sym-
bol
Pin
Con-
dition
Parameter
Unit
Remarks
name
Min
⎯
Max
⎯
FC
X0, X1
MHz
kHz
Frequency of source
oscillation clock
Fca X0A, X1A
⎯
32
⎯
Source oscillation clock
Cycle time
tCYL
X0, X1
⎯
250
⎯
ns
⎯
The duty ratio normally
ns ranges from 40% to
60%.
PWH ,
PWL
Input clock pulse width
X0
100
⎯
⎯
fCPB
fCPT
0.0312
0.0312
⎯
⎯
32
16
MHz CPU based (CLKB)
External bus based
(CLKT)
Frequency of internal
operating clock
MHz
⎯
⎯
⎯
⎯
Peripheral based
(CLKP)
fCPP
tCPB
tCPT
0.0312
31.25
62.5
⎯
⎯
⎯
32
MHz
32000
32000
ns CPU based (CLKB)
External bus based
(CLKT)
Internal operating clock
cycle
ns
Peripheral based
(CLKP)
tCPP
31.25
⎯
⎯
32000
5
ns
Input clock
Rise/fall time
tcr
tcf
When external clock is
used
X0
⎯
ns
⎯
⎯
When main oscillation
MHz is at 4 MHz and PLL
multiplied by 8 is used
Frequency of internal
base clock
FCP
⎯
⎯
⎯
⎯
32
When main oscillation
ns is at 4 MHz and PLL
multiplied by 8 is used
Internal base clock
Cycle time
tCP
⎯
31.25
⎯
• X0/X1 Clock Timing
tCYL
0.8 VCC
0.2 VCC
X0
PWH
PWL
tcf
tcr
60
MB91245/S Series
• Operations
Oscillation should be performed as described below :
[Source oscillation] : X0/X1 : 4 MHz, PLL : multiplied by 8, Internal frequency : 32 MHz
: X0A/X1A : 32 kHz, PLL : no multiplied, Internal frequency : 32 kHz
Note that the PLL oscillation stabilization wait time should be set to 500 µs or more.
Example oscillation circuit
X0
X1
R
C1
C2
AC specifications are defined by the following measurement standard voltage values :
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.5 VCC
0.8 V
61
MB91245/S Series
(2) Reset input
(TA : Recommended operating conditions; Vcc = 5.0 V 10%, VSS = DVSS = AVSS = 0.0 V)
Value
Sym-
bol
Con-
dition
Parameter
Pin name
Unit
Remarks
Min
Max
Flash memory
product
500
⎯
ns
ns
MASK ROM
product
10 tCP
⎯
⎯
INIT input time
tINTL
INIT
⎯
Oscillation time of
oscillator* +
10 tcp + 12 µs
ms In stop mode
* : The oscillation time of the oscillator refers to the time when the amplitude has reached 90%. The oscillation time
of the crystal oscillator ranges from several ms to tens of ms. The oscillation time of the ceramic oscillator ranges
from several hundreds to several ms, while that of the external clock is 0 ms.
tINTL
INIT
0.2 VCC
0.2 VCC
• In stop mode
t
INTL
INIT
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operation clock
10 tcp + 12 µs
Oscillation
time of
oscillator
Oscillation stabilization wait time
Instruction executed
Internal reset
62
MB91245/S Series
[External reset input specifications (INIT) and internal reset signal cancellation timing]
• When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the
internal reset signal to transmit all reset signals to the internal logic.
(Max 8 µs at 32 MHz)
• The following chart shows how to set the timing for instruction execution start (start of application operation)
after external reset input.
Time from external reset input to instruction start = Max 256 tcp + 61 tcp
• Timing Chart
INIT
Min
Internal reset input timing
10 tcp
Internal reset
61 tcp
Max 256 tcp
Internal reset cancellation timing
[Pin state in external bus mode]
In the external bus mode, it is not guaranteed to hold the RAM value upon external reset (INIT = “0”) input.
In the external bus mode, the value of the internal bus is output to each pin during the time from the internal
reset input to its cancellation as well as the RAM value is not guaranteed to be held.
• Timing Chart (Pin State for External Bus Mode : 1)
INIT
Min
10 tcp
Internal reset
61 tcp
Max 256 tcp
Pin state of
external bus
Value immediately
before reset
Hi-Z
Initial value at reset
63
MB91245/S Series
It can be avoided by the following external reset input to continue Hi-Z.
• Timing Chart (Pin State for External Bus Mode : 2)
INIT
256 tcp
Internal reset
61 tcp
Max 256 tcp
Hi-Z
Pin state of
external bus
Initial value at reset
64
MB91245/S Series
(3) Power-on Conditions
(TA : Recommended operating conditions; VSS = 0.0 V)
Value
Condi-
tion
Parameter
Symbol Pin name
Unit
Remarks
Min
Max
Power supply rising
time
tR
0.05
30
ms
V
Power supply start
voltage
VOFF
VON
tOFF
⎯
3.5
50
0.2
⎯
Vcc
⎯
Power supply peak
voltage
V
Power supply cut-off
time
Due to repetitive
operation
⎯
ms
tR
4.5 V
Vcc
0.2 V
0.2 V
0.2 V
tOFF
Power supply drop time, power supply voltages and external reset input to retain RAM data in MB91245/S
Satisfy the following reset input standard to retain the RAM data used in the single chip mode.
Vcc (V)
Voltage drop time
External reset input standard (INIT)
4.0 V → 3.5 V dropped
Min 256 tcp
Min 256 tcp
4 V
4 V
Vcc
3.5 V
3.5 V
INIT
256 tcp
To retain RAM data, enter 256 tcp of INIT or more before dropping VCC to 3.5 V or lower.
65
MB91245/S Series
(4) Clock Output Timing
(VCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V)
Value
Parameter
Cycle time
Symbol Pin name Condition
Unit
Remarks
Min
Max
tCYC
tCHCL
tCLCH
SYSCLK
SYSCLK
SYSCLK
tCPT
⎯
ns
ns
ns
*1
SYSCLK↑→SYSCLK↓
SYSCLK↓→SYSCLK↑
⎯
tCYC / 2 − 10 tCYC / 2 + 10
tCYC / 2 − 10 tCYC / 2 + 10
*2
*3
t
CYC
t
CHCL
tCLCH
V
OH
VOH
SYSCLK
VOL
*1 : tCYC is the frequency of one clock cycle including the gear cycle.
*2 : The ratings are based on conditions with “gear cycle × 1”.
When the gear cycle is set to 1/2, 1/4 or 1/8, perform calculation by substituting 1/2, 1/4 or 1/8 for “n” in the
following formula, respectively.
( 1 / 2 × 1 / n ) × tCYC − 10
*3 : This is the value for the gear cycle × 1.
66
MB91245/S Series
(5) Normal Bus Access : Read/Write Operation
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min
Max
AWRxL :
W02 = 0
tCSLCH
3
⎯
ns
CS0 to CS3 setup
CS0 to CS3 hold
SYSCLK
CS0 to CS3
AWRxL :
W02 = 1
tCSDLCH
tCHCSH
tASCH
−8
3
⎯
tCYC / 2 + 25
⎯
ns
ns
ns
SYSCLK
A00 to A15
3
WR0, WR1
A00 to A15
Address setup
Address hold
tASWL
tASRL
tCHAX
tWHAX
tRHAX
tAVDV
3
3
⎯
ns
RD
A00 to A15
⎯
ns
SYSCLK
A00 to A15
3
tCYC / 2 + 25
ns
WR0, WR1
A00 to A15
3
⎯
⎯
ns
RD
A00 to A15
3
ns
Valid address →
valid data input time
A00 to A15
D00 to D15
3 / 2 × tCYC +
⎯
ns *1, *2
45
WR0, WR1 delay time
WR0, WR1 delay time
tCHWL
tCHWH
⎯
⎯
8
8
ns
ns
SYSCLK
WR0, WR1
⎯
WR0, WR1 minimum
pulse width
tWLWH
tWHDX
WR0, WR1
D00 to D15
tCYC − 5
⎯
⎯
ns
ns
WR0, WR1↑→
data hold time
3
RD delay time
RD delay time
tCHRL
tCHRH
⎯
⎯
6
6
ns
ns
SYSCLK
RD
RD ↓ →
tRLDV
tDSRH
tRHDX
⎯
20
0
tCYC − 30
ns *1
ns
valid data input time
RD
D00 to D15
Data setup → RD ↑ time
⎯
⎯
RD ↑ →
data hold time
ns
RD minimum pulse width
AS setup
tRLRH
tASLCH
tCHASH
RD
tCYC − 5
⎯
⎯
ns
ns
ns
3
3
SYSCLK
AS
AS hold
tCYC / 2 + 25
*1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded
cycles) to the rated value.
*2 : The ratings are based on conditions with “gear cycle × 1”. If the gear cycle is set to 1/2 to 1/16, perform
calculation by substituting the corresponding value for “n” in the following formula.
Formula : 3/ (2n) × tCYC + 45
67
MB91245/S Series
t
CYC
VOH
V
OH
V
OH
VOH
SYSCLK
t
ASLCH
tCHASH
V
OH
AS
V
OL
t
tCCSSDLCLCHH
t
CHCSH
V
OH
V
OL
CS0 to CS3
t
ASCH
t
CHAX
V
OH
V
V
OH
OL
A00 to A15
VOL
t
CHRL
tCHRH
t
RLRH
RD
V
OL
t
RHAX
t
ASRL
t
RLDV
t
DSRH
t
RHDX
t
AVDV
V
OH
V
OH
OL
D00 to D15
WR0, WR1
D00 to D15
VOL
V
t
CHWH
t
CHWL
t
WLWH
V
OH
V
OL
t
ASWL
t
t
WHAX
WHDX
V
V
OH
OL
V
V
OH
OL
68
MB91245/S Series
(6) Ready Input Timing
Parameter
(VCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V)
Value
Symbol
Pin name
Condition
Unit
Remarks
Min
Max
RDY setup time
→SYSCLK↓
SYSCLK
RDY
tRDYS
tRDYH
10
⎯
ns
ns
⎯
SYSCLK↑→
RDY hold time
SYSCLK
RDY
0
⎯
tcyc
VoH
VoH
SYSCLK
VoL
VoL
tRDYS
tRDYH
tRDYS
VoL
tRDYH
VoH
VoH
With RDY
wait
VoL
Without RDY
wait
VoH
VoH
VoL
VoL
69
MB91245/S Series
(7) UART Timing
(TA : Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V)
Value
Parameter
Serial clock
Symbol Pin name Condition
Unit
Remarks
Min
Max
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
SCK0
8 tCP
⎯
ns
ns
ns
ns
ns
ns
Cycle time
SCK↓→
SOT delay time
SCK0, SOT0
−80
100
60
+80
⎯
For internal shift clock
mode output pin,
CL = 80 pF+1⋅TTL
⎯
Valid SIN→
SCK↑
SCK0, SIN0
SCK↑→
Valid SIN hold time
⎯
Serial clock
“H” pulse width
4 tCP
4 tCP
⎯
⎯
SCK0
Serial clock
“L” pulse width
⎯
For external shift clock
SCK↓→
SOT delay time
SCK0, SOT0
SCK0, SIN0
⎯
150
⎯
ns mode output pin,
CL = 80 pF+1⋅TTL
Valid SIN→
SCK↑
60
ns
ns
SCK↑→
Valid SIN hold time
60
⎯
Notes : • The above ratings are the values for clock synchronous mode.
• CL is a load capacitance connected to pins during testing.
70
MB91245/S Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
tIVSH
tSHIX
0.8 Vcc
0.5 Vcc
0.8 Vcc
0.5 Vcc
SIN
• External Shift clock Mode
tSLSH
tSHSL
0.8 Vcc
0.8 Vcc
SCK
SOT
0.6 Vcc
tSLOV
0.6 Vcc
2.4 V
0.8 V
tIVSH
tSHIX
0.8 Vcc
0.5 Vcc
0.8 Vcc
0.5 Vcc
SIN
71
MB91245/S Series
(8) Timer Input Timing
(TA : Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min
Max
tTIWH
tTIWL
TIN0 to TIN2, PWC
IN0 to IN3
Input pulse width
⎯
4 tCP
⎯
ns
• Timer Input Timing
tTIWL
tTIWH
0.8 Vcc
0.8 Vcc
TINx
INx
0.5 Vcc
0.5 Vcc
(9) External Interrupt Timing
(TA : Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min
Max
Input pulse width
tINTH, INTL
INT0 to INT7
⎯
3 tCP
⎯
ns
• External interrupt input timing
tINTH
tINTL
0.8 Vcc
0.8 Vcc
0.5 Vcc
0.5 Vcc
INTx
Note : For INTx level detection time required to recover from the stop mode, add the stabilization time for the internal
step-down circuit (12 µs).
72
MB91245/S Series
6. A/D Converter Electrical Characteristics
(1) Electrical Characteristics
(TA : Recommended operating conditions; VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V)
Value
Sym-
Parameter
Resolution
Pin name
Unit
Remarks
bol
Min
Typ
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
3.0
2.5
LSB
LSB
Non-linearity error
⎯
⎯
Differential linearity
error
⎯
⎯
⎯
⎯
1.9
LSB
V
AVSS
AVSS
AVSS
Zero transition voltage
VOT
VFST
AN0 to AN31
AN0 to AN31
− 1.5 LSB + 0.5 LSB + 2.5 LSB
AVRH AVRH AVRH
− 3.5 LSB − 1.5 LSB + 0.5 LSB
1 LSB =
(AVRH − AVSS) / 1024
Full-scale transition
voltage
V
Sampling time
tSMP
tCMP
tCNV
⎯
⎯
⎯
1.375
1.375
2.750
⎯
⎯
⎯
⎯
⎯
⎯
µs *1
µs *2
µs *3
Compare time
A/D conversion time
Analog port input
current
IAIN
AN0 to AN31
⎯
⎯
10
µA VAVSS ≤ VAIN ≤ VAVCC
Analog input voltage
Standard voltage
VAIN
AVR +
IA
AN0 to AN31
AVRH
0
4.0
⎯
⎯
⎯
⎯
⎯
⎯
AVRH
AVcc
4.7
V
V
2.4
⎯
mA
Power supply
current*4
AVCC
IAH
5
µA *5
IR
AVRH
AVRH
500
⎯
900
5
µA VAVRH = 5.0 V
µA *5
Standard voltage
supply current
IRH
Variation between
channels
⎯
AN0 to AN31
⎯
⎯
5
LSB
*1 : When FCP is 32 MHz : tSMP = (Rext + Rin) × Cin × 7 = ST × CLKP cycle = 2 channels × 31.25 ns = 1.375 µs
*2 : When FCP is 32 MHz : tCMP = CKIN × 11 = CT × CLKP cycle × 11 = 4 h × 31.25 ns × 11 = 1.375 µs
*3 : This represents the conversion time per channel when tSMP and tCMP are selected while FCP is 32 MHz.
*4 : The current values are targeted temporary ratings.
*5 : This defines the power supply current when the A/D converter is not in operation and the CPU is stopped (at
“Vcc = AVcc = AVRH = 5.0 V”)
Notes : • As AVRH becomes smaller, the error becomes greater.
• Use the output impedance rS of the external circuit for analog input under the following conditions :
Output impedance rS of the external circuit = 5 kΩ (Max)
• If the output impedance of the external circuit is too high, the sampling time of the analog voltage may
not be sufficient.
When placing a DC blocking capacitor between the external circuit and input pin, set the capacitance
to the value calculated by multiplying CSH by several thousands as a guideline in order to minimize
the impact from dividing voltage capacitance with CSH.
73
MB91245/S Series
• Analog Input Equivalent Circuit
Circuit in microcontroller
Input pin AN0
RSH
CSH
rs
Comparator
Input pin AN7
Vs
S/H circuit
Analog channel selector
External circuit
<Recommended parameter values and tentative guideline for each element>
rS = 5 kΩ or less
RSH = approx. 2.5 kΩ
CSH = approx. 10 pF
Note : These element parameters should be regarded as tentative values used only for
design purposes. They are not guaranteed values.
74
MB91245/S Series
(2) Term Definitions
• Resolution
Level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, the analog voltage can be resolved into 210 = 1024.
• Total error
Difference between actual and theoretical values, which is a total value derived from an offset error, gain error,
non-linearity error and noise.
• Linearity error
Deviation between the value along a straight line connecting the zero transition point (“00 0000 0000”←→
“00 0000 0001”) of a device and the full-scale transition point (“11 1111 1110”←→“11 1111 1111”) compared
with the actual conversion values obtained.
• Differential linearity error
Deviation of input voltage, which is required for changing output code by1 LSB, from an ideal value.
75
MB91245/S Series
• 10-bit A/D Converter- Conversion Characteristics
11 1111 1111
B
11 1111 1110
11 1111 1101
11 1111 1100
B
B
B
.
.
.
.
.
1 LSB x N + VOT
Digital
output
.
.
.
.
.
.
.
.
Linearity error
00 0000 0011
00 0000 0010
B
B
00 0000 0001
00 0000 0000
B
B
V
NT
V
(N + 1)T
VFST
V
OT
Analog input
VFST− VOT
1022
1 LSB
=
=
=
VNT− (1 LSB × N + VOT)
Linearity error
[LSB]
1 LSB
V (N + 1) T − VNT
Differential linearity error
−1
[LSB]
1 LSB
N
: A/D converter digital output value.
VOT : Voltage at which digital output transits from 000H to 001H.
VFST : Voltage at which digital output transits from 3FEH to 3FFH.
VNT : A voltage at which digital output transits from (N − 1) to N.
76
MB91245/S Series
■ EXAMPLE CHARACTERISTICS
(1) Power supply current (at main RUN)
(2) Power supply current (at sub RUN)
ICC - VCC
ICCL - VCC
TA = + 25 °C
TA = + 25 °C
100
90
80
70
60
50
40
30
20
10
0
500
450
400
350
300
250
200
150
100
50
0
3.5
3.5
4
4.5
5
5.5
4
4.5
5
5.5
VCC (V)
VCC (V)
(3) Power supply current
(4) Power supply current
(at stop : when oscillation stops)
(at stop : when using RTC 4 MHz)
ICCH - VCC
ICTS - VCC
TA = + 25 °C
TA = + 25 °C
150
500
140
130
120
110
100
90
80
70
60
50
450
400
350
300
250
200
150
100
50
40
30
20
10
0
3.5
0
3.5
4
4.5
5
5.5
4
4.5
5
5.5
VCC (V)
VCC (V)
(Continued)
77
MB91245/S Series
(5) A/D power supply current
(6) A/D reference voltage supply current
IA - VCC
IR - VCC
VCC = AVCC = AVRH TA = + 25 °C
1000
VCC = AVCC = AVRH TA = + 25 °C
5
4.5
4
900
800
700
600
500
400
300
200
100
0
3.5
3
2.5
2
1.5
1
0.5
0
3.5
4
4.5
5
5.5
3.5
4
4.5
5
5.5
VCC (V)
VCC (V)
(7) “H” level input voltage/“L” level input voltage (8) “H” level input voltage/“L” level input voltage
(Automotive input)
(CMOS hysteresis input)
VIN - VCC
VIN - VCC
TA = + 25 °C
TA = + 25 °C
5
4.5
4
5
4.5
4
VIHS
3.5
3
3.5
VIH
3
VILS
2.5
2
2.5
2
VIL
1.5
1
1.5
1
0.5
0
0.5
0
3.5
4
4.5
VCC (V)
5
5.5
3.5
4
4.5
VCC (V)
5
5.5
(Continued)
78
MB91245/S Series
(Continued)
(9) “H” level output voltage
(10) “H” level output voltage
VOH2 - IOH
VOH1 - IOH
VCC = DVCC = 5.0 V TA = + 25 °C
VCC = DVCC = 5.0 V TA = + 25 °C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
−10
−20
−30
−40
0
−1
−2
−3
−4
−5
IOH (mA)
IOH (mA)
(11) “L” level output voltage
(12) “L” level output voltage
VOL1 - IOL
VCC = DVCC = 5.0 V TA = + 25 °C
VOL2 - IOL
VCC = DVCC = 5.0 V TA = + 25 °C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
0
10
20
30
40
IOL (mA)
I
OL (mA)
79
MB91245/S Series
■ ORDERING INFORMATION
Part number
Package
Remarks
401-pin ceramic PGA
(PGA-401C-A02)
MB91V245ACR-ES
Evaluation product
144-pin plastic LQFP
(FPT-144P-M08)
MB91F248PFV-GSE1
MB91F248SPFV-GSE1
MB91247PFV-GSE1
MB91247SPFV-GSE1
MB91248PFV-GSE1
MB91248SPFV-GSE1
Dual clock product
Single clock product
Dual clock product
Single clock product
Dual clock product
Single clock product
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
80
MB91245/S Series
■ PACKAGE DIMENSION
144-pin plastic LQFP
Lead pitch
0.50 mm
20.0 × 20.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
1.20g
Code
(Reference)
(FPT-144P-M08)
P-LFQFP144-20×20-0.50
144-pin plastic LQFP
(FPT-144P-M08)
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00 0.20(.866 .008)SQ
* 20.00 0.10(.787 .004)SQ
0.145 0.055
(.006 .002)
108
73
109
72
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 –+..000048
0.10 0.10
(.004 .004)
(Stand off)
0˚~8˚
INDEX
144
37
0.25(.010)
0.50 0.20
(.020 .008)
"A"
0.60 0.15
(.024 .006)
1
36
LEAD No.
0.50(.020)
0.22 0.05
(.009 .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003 FUJITSU LIMITED F144019S-c-4-6
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
81
MB91245/S Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited
Business Promotion Dept.
F0610
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