MB91307B_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-16309-3E

32-Bit Microcontroller

CMOS

FR65E Series

MB91307B

■ DESCRIPTION

The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety

of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability,

high-speed CPU processing. External bus access is assumed in order to support the expanded address space

accessible by the 32-bit CPU, and a 1 KB cache memory plus large 128 KB RAM are provided for high-speed

execution of CPU instructions.

This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX

and printer control that demand high-capability CPU processing power.

The MB91307B is a FR65E series product based on the FR30/40 series CPU with enhanced bus access for

higher speed operation.

■ FEATURES

FR CPU

• 32-bit RISC, load/store architecture, 5-stage pipeline

• Operating frequency 66MHz [with PLL: base frequency 16.5 MHz]

• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle

(Continued)

■ PACKAGE

120-pin, plastic LQFP

(FPT-120P-M21)

Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent rights to use these components

in an I²C system provided that the system conforms to the I²C Standard Specification as defined by Philips.

MB91307B

• Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.

• Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/

store instructions

• Easier assembler notation: register interlock function

• Built-in multiplier/instruction level support

Signed 32-bit multiplication: 5 cycles

Signed 16-bit multiplication: 3 cycles

• Interrupt (PC, PS removal): 6 cycles, 16 priority levels

• Harvard architecture for simultaneous execution of program access and data access

• CPU hold 4-word queue allows advanced instruction fetch function

• 4 GB expanded memory space enables linear access

• Instruction compatible with FR30/40 family

Bus Interface

• Operating frequency: Max 33 MHz

• 8- or 16-bit data output

• Built-in pre-fetch buffer

• Unused data/address pins can be used as general-0purpose input/output ports

• Fully independent 8-area chip select outputs, can be set in minimum 64 KB units

• Interface support for many memory types

SRAM, ROM/Flash

Page mode flash ROM, page mode ROM interface

Burst mode flash ROM (select burst length 1, 2, 4, 8)

• Basic bus cycle: 2 cycles

• Programmable by area with automatic wait cycle generation to enable wait insert

• RDY input for external wait cycles

• DMA supports fly-by transfer with independent I/O wait control

Built-in RAM

• 128 KB built-in RAM capacity

• Accepts writing of data and instruction codes, enabling use as instruction RAM

Instruction cache

• 1 KB capacity

• 2-way set associative

• 4-words (16 bytes) per set

• Lock function enables permanent program storage

• Areas not used for instruction cache can be used for RAM

DMAC (DMA controller)

• 5-channel (3-channel external-to-external)

• 3 transfer sources (external pin, internal peripheral, software)

• Addressing mode with 32-bit full address indication (increment, decrement, fixed)

• Transfer mode (demand transfer / burst transfer / step transfer / block transfer)

• Fly-by transfer support (3 channels between external I/O and external memory)

• Transfer data size selection 8/16/32-bit

Bit search module (using REALOS)

• Searches words from MSB for first bit position of a 1/0 change

Reload timer (includes 1 channel for REALOS)

• 16-bit timer: 3 channels

• Internal clock multiplier choice of x2, x8, x32

(Continued)

2

MB91307B

(Continued)

UART

• Full duplex double buffer

• 3-channel

• Parity/no parity selection

• Asynchronous (start-stop synchronized), CLK-synchronized communications selection

• Built-in exclusive baud rate timer

• External clock can be used as transfer clock

• Variety of error detection functions (parity, frame, overrun)

I²C interface

• Master/slave sending and receiving

• Clock synchronization function

• Transfer direction detection function

• Bus error detection function

• Arbitration function

• Slave address/general call address detection function

• Start condition repeat generator and detection function

• 10-bit/7-bit slave address

• Operates in standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)

Interrupt controller

• Total of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0

• Interrupt from internal peripheral devices

• Programmable priority settings (16 levels) enabled, except for non-maskable interrupt

• Can be used for wake-up from stop mode

A/D converter

• 10-bit resolution, 4-channel

• Sequential comparator type, conversion time approx. 5.4 µs

• Conversion modes: single conversion mode, continuous conversion mode

• Startup source: software / external trigger / timer output signal

Other interval timers

• 16-bit timer with 3 channels (U-timer)

• Watchdog timer

I/O port

• Maximum 69 ports

Other features

• Built-in oscillator circuit for clock source, PLL multiplier selection enabled

• INIT reset pin

• Also included: watchdog timer reset, software reset

• Power-saving modes: stop mode, sleep mode supported

• Gear functions

• Built-in time base timer

• Packages: LQFP-120 (FPT-120P-M21) : MB91307B

: MB91V307R(Evaluation product)

• CMOS technology

: 0.25 µm

• Supply voltage : 3.3 V ± 0.3 V (built-in regulator 3.3 V → 2.5 V)

3

MB91307B

■ PIN ASSIGNMENT

(TOP VIEW)

PA3/CS3

PA4/CS4

PA5/CS5

C

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

PI5/SC1

PI4/SO1

PI3/SI1

PI2/SC0

PI1/SO0

PI0/SI0

PA6/CS6

PA7/CS7

P80/RDY

P81/BGRNT

P82/BRQ

RD

UUB/WR0

P85/ULB/WR1

NMI

VCC

PJ7/INT7/ATG

PJ6/INT6/TIN2

PJ5/INT5/TIN1

PJ4/INT4/TIN0

PJ3/INT3

PJ2/INT2

PJ1/INT1

PJ0/INT0

AN3

AN2

AN1

AN0

AVSS/AVRL

AVRH

HST

VSS

INIT

P90/SYSCLK

P91

P92/MCLK

P93

P94/LBA/AS

P95/BAA

P96

AVCC

8

7

6

5

4

3

2

1

A24/P70

A23/P67

A22/P66

A21/P65

A20/P64

A19/P63

A18/P62

A17/P61

P97/WE

P20/D16

P21/D17

P22/D18

P23/D19

P24/D20

P25/D21

(FPT-120P-M21)

* : “L” level output after initialization and reset

4

MB91307B

■ PIN DESCRIPTIONS

I/O

circuit type

Pin no.

Pin name

Description

External data bus bits 16-23

Valid only in external bus 16-bit mode.

D16 to D23

P20 to P27

85 to 92

C

These pins can be used as ports in external bus 8-bit mode

External data bus bits 24-31

93 to 100 D24 to D31

102 to 109 A00 to A07

111 to 118 A08 to A15

C

F

External address output bits 0-7

External address output bits 8-15

A16 to A23

120, 1 to 7

External address output bits 16-23

F

P60 to P67

These pins can be used as ports according to setting

External data bus output bit 24

A24

8

P70

This pin can be used as a port according to setting

Power supply pin. Analog power supply for A/D converter

A/D converter reference voltage supply

9

AV^CC

AVRH

10

11

AV^SS/AVRL

Power supply pin. Analog power supply for A/D converter

A/D converter reference voltage supply. Analog input pin.

12 to 15 AN0 to AN3

D

I

INT0-INT3: External interrupt input. When the corresponding external

interrupt is enabled, this input is in use at all times, so that output from

other functions must be stopped unless used intentionally

INT0 to INT3

16 to 19

PJ0 to PJ3

PJ0-PJ3: General purpose input/output port

TIN0-TIN2: Reload timer input. When the corresponding timer input is

enabled, this input is in use at all times, so that output from other

functions must be stopped unless used intentionally.

TIN0 to TIN2

20 to 22

I

INT4-INT6: External interrupt input. When the corresponding external

interrupt is enabled, this input is in use at all times, so that output from

other functions must be stopped unless used intentionally.

INT4 to INT6

PJ4 to PJ6

ATG

PJ4-PJ6: General purpose input/output port

ATG: A/D converter external trigger input. When selected as an A/D start

source, this input is in use at all times, so that output from other functions

must be stopped unless used intentionally.

23

INT7: External interrupt input. When the corresponding external interrupt

is enabled, this input is in use at all times, so that output from other

functions must be stopped unless used intentionally.

INT7

PJ7

PJ7: General purpose input/output port

SI0: UART0 data input. When the UART0 channel is in input operation,

this input is in use at all times, so that output from other functions must

be stopped unless used intentionally.

SI0

25

F

PI0

PI0: General purpose input/output port.

SO0: UART0 data output. This function is valid when the UART0 data

output function setting is disabled.

SO0

26

PI1: General purpose input/output port. This function is valid when the

UART0 data output function setting is disabled.

PI1

(Continued)

5

MB91307B

I/O

circuit type

Pin no.

Pin name

SC0

Description

SC0: UART0 clock output. The clock output is valid when the UART0

clock output function setting is enabled.

27

F

C

PI2: General purpose input/output port. This function is valid when the

UART0 clock output function is disabled.

PI2

SI1: UART1 data input. When UART1 is set for input operation, this input

is in use at all times, so that output from other functions must be stopped

unless used intentionally.

SI1

28

29

30

31

32

33

35

PI3

PI3: General purpose input/output port.

SO1: UART1 data output. This function is enabled when the UART1 data

output function setting is enabled.

SO1

PI4: General purpose input/output port. This function is valid when the

UART1 data output function setting is disabled.

PI4

SC1

PI5

SC1: UART1 clock input/output. The clock output is enabled when the

UART1 clock output function setting is enabled.

PI5: General purpose input/output port. This function is valid when the

UART1 clock output function setting is disabled.

SI2: UART2 data input. When UART2 is set for input operation, this input

is in use at all times, so that output from other functions must be stopped

unless used intentionally.

SI2

PH0

SO2

PH0: General purpose input/output port.

SO2: UART2 data output. This function is enabled when the UART2 data

output function setting is enabled.

PH1: General purpose input/output port This function is enabled when

the UART2 data output function setting is disabled.

PH1

SC2

SC2: UART2 clock input/output. The clock output is enabled when the

UART2 clock output function setting is enabled.

PH2: General purpose input/output port This function is enabled when

the UART2 clock output function is disabled.

PH2

TOT0: Timer output port. This function is valid when the timer output

setting is enabled.

TOT0

PH3

PH3: General purpose input/output port.This pin outputs an L level signal

at reset.

TOT1: Timer output port. This function is valid when the timer output

setting is enabled.

TOT1

PH4

36

37

C

PH4: General purpose input/output port.This pin outputs an L level signal

at reset.

TOT2: Timer output port. This function is valid when the timer output is

enabled.

TOT2

PH5

PH5: General purpose input/output port.

(Continued)

6

MB91307B

I/O

circuit type

Pin no.

Pin name

Description

SDA: I²C bus input/output port. This function is valid when I²C operation

is enabled. When the I²C bus is in use, the port output must be set to

Hi-Z level. When the I²C bus is in use, this is an open drain pin.

SDA

PH6

38

Q

F

PH6: General purpose input/output port.

SCL: I²C bus input/output port. This function is valid when I²C operation

is enabled. When the I²C bus is in use, the port output must be set to

Hi-Z level. When the I²C bus is in use, this is an open drain pin.

SCL

39

40

PH7

PH7: General purpose input/output port.

DREQ2: DMA external transfer request input. When selected as a DMA

startup source, this input is in use at all times, so that output from other

functions must be stopped unless used intentionally.

DREQ2

PG0

PG0: General purpose input/output port.

DACK2: DMA external transfer request acknowledge output. This

function is valid when the DMA transfer request acknowledge output

setting is enabled.

DACK2

41

42

F

PG1: General purpose input/output port. This function is valid when the

DMA transfer request acknowledge output setting is enabled.

PG1

DEOP2: DMA external transfer end output. This function is valid when

the DMA external transfer end output setting is enabled.

DEOP2

DSTP2

DSTP2: DMA external transfer stop input. This function is valid when the

DMA external transfer stop input setting is enabled.

PG2: General purpose input/output port. This function is valid when the

DMA external transfer end output selection and the DMA external

transfer stop input selection are disabled.

PG2

Mode pins 2-0. The setting of these two pins determines the basic

operating mode. They should be connected to V^ccor Vss.

43 to 45 MD2 to MD0

G

F

DREQ0: DMA external transfer request input. When selected as a DMA

startup source, this input is in use at all times, so that output from other

functions must be stopped unless used intentionally.

DREQ0

46

PB0

PB0: General purpose input/output port.

DACK0: DMA external transfer request acknowledge output. This

function is valid when the DMA transfer request acknowledge output

setting is enabled.

DACK0

47

F

PB1: General purpose input/output port. This function is enabled when

the DMA transfer request acknowledge output setting is disabled.

PB1

DEOP2: DMA external transfer end output. This function is valid when

the DMA external transfer end output setting is enabled.

DEOP0

DSTP0: DMA external transfer stop input. This function is valid when the

DMA external transfer stop input setting is enabled.

DSTP0

48

PB2: General purpose input/output port. This function is valid when the

DMA external transfer end output selection and the DMA external

transfer stop input selection are disabled.

PB2

(Continued)

7

MB91307B

I/O

circuit type

Pin no.

Pin name

Description

DREQ1: DMA external transfer request input. When selected as a DMA

startup source, this input is in use at all times, so that output from other

functions must be stopped unless used intentionally.

DREQ1

PB3

49

F

PB3: General purpose input/output port.

DACK1: DMA external transfer request acknowledge output. This

function is valid when the DMA transfer request acknowledge output

setting is enabled.

DACK1

50

51

PB4: General purpose input/output port. This function is enabled when

the DNA transfer request acknowledge output setting is disabled.

PB4

DEOP1: DMA external transfer end output. This function is valid when

the DMA external transfer end output setting is enabled.

DEOP1

DSTP1

DSTP1: DMA external transfer stop input. This function is valid when the

DMA external transfer stop input setting is enabled.

F

PB5: General purpose input/output port. This function is valid when the

DMA external transfer end output selection and the DMA external

transfer stop input selection are disabled.

PB5

53

54

X1

X0

Clock (oscillator) output

Clock (oscillator) input

A

F

IOWR: Write strobe output for DMA fly-by transfer. This function is valid

when the DMA fly-by transfer write strobe output setting is enabled.

IOWR

PB6

IORD

PB7

CS0

PA1

CS1

PA1

CS2

PA2

CS3

PA3

56

57

58

59

60

61

PB6: General purpose input/output port. This function is valid when the

DMA fly-by transfer write strobe output setting is disabled.

IORD: Read strobe output for DMA fly-by transfer. This function is valid

when the DMA fly-by transfer read strobe output setting is enabled.

F

PB7: General purpose input/output port. This function is valid when the

DMA fly-by transfer read strobe output setting is disabled.

CS0: Chip select output. This function is valid when the chip select 0

output setting is enabled.

PA1: General purpose input/output port. This function is valid when the

chip select 0 output setting is disabled.

CS1: Chip select output. This function is valid when the chip select 1

output setting is enabled.

PA1: General purpose input/output port. This function is valid when the

chip select 1 output setting is disabled.

CS2: Chip select output. This function is valid when the chip select 2

output setting is enabled.

PA2: General purpose input/output port. This function is valid when the

chip select 2 output setting is disabled.

CS3: Chip select output. This function is valid when the chip select 3

output setting is enabled.

PA3: General purpose input/output port. This function is valid when the

chip select 3 output setting is disabled.

(Continued)

8

MB91307B

I/O

circuit type

Pin no.

Pin name

CS4

PA4

CS5

PA5

C

Description

CS4: Chip select output. This function is valid when the chip select 4

output setting is enabled.

62

F

PA4: General purpose input/output port. This function is valid when the

chip select 4 output setting is disabled.

CS5: Chip select output. This function is valid when the chip select 5

output setting is enabled.

63

64

65

PA5: General purpose input/output port. This function is valid when the

chip select 5 output setting is disabled.

C: Bypass capacitor pin for internal capacitor. See “HANDLING DEVIC-

ES”

CS6: Chip select output. This function is valid when the chip select 6

output setting is enabled.

CS6

PA6

CS7

PA7

RDY

P80

F

C

PA6: General purpose input/output port. This function is valid when the

chip select 6 output setting is disabled.

CS7: Chip select output. This function is valid when the chip select 7

output setting is enabled.

66

67

PA7: General purpose input/output port. This function is valid when the

chip select 7 output setting is disabled.

RDY: External ready signal input. This function is valid when the external

ready input setting is enabled.

P80: General purpose input/output port. This function is valid when the

external ready input setting is disabled.

BGRNT: External bus open acknowledge output. This pin outputs an L

level signal when the external bus is open. This function is valid when the

output setting is enabled.

BGRNT

P81

68

69

F

P

P81: General purpose input/output port. This function is valid when the

output setting is disabled.

BRQ: External bus open request input. The input value is “1” when the

external bus is open. This function is valid when the input setting is

enabled.

BRQ

P82: General purpose input/output port. This function is valid when the

input setting is disabled.

P82

RD

70

71

M

F

External bus read strobe output.

External bus write strobe output.

WR0

UUB

UUB: Is the upper side of the 16-bit SRAM input/output mask enable

signal. It is valid when the external bus is set to SRAM use. (WE/P97

function as the write strobe.)

External bus write strobe output.

WR1

ULB

ULB: Is the lower side of the 16-bit SRAM input/output mask enable

signal. It is valid when the external bus is set to SRAM use. (WE/P97

function as the write strobe.)

72

F

P85: General purpose input/output port. This function is valid when the

enable output setting is disabled.

P85

(Continued)

9

MB91307B

(Continued)

I/O

circuit type

Pin no.

Pin name

Description

73

74

76

NMI

HST

INIT

H

B

NMI request input

Hardware standby input

External reset input

SYSCLK: System clock output. This function is valid when the system

clock output setting is enabled. The clock signal output is at the same fre-

quency as the external bus operating frequency. Clock output halts in the

stop mode or the hardware standby mode.

SYSCLK

77

F

P90: General purpose input/output port. This function is enabled when the

system clock output setting is disabled.

P90

P91

MCLK

P92

P93

AS

P91: General purpose input/output port. This function is enabled when the

SDRAM clock enable output setting is disabled.

78

79

80

F

MCLK: Memory clock output. Clock output halts in the sleep mode, the

stop mode or the hardware standby mode.

P92: General purpose input/output port. This function is enabled when the

clock output setting is disabled.

P93: General purpose input/output port. This function is enabled when the

SDRAM clock re-input setting is disabled.

AS: Address strobe output. This function is valid when the address strobe

output setting is disabled.

LBA: Burst flash ROM address load output. This function is valid when the

address load output setting is enabled.

81

82

LBA

P94

BAA

F

P94: General purpose input/output port. This function is valid when the

address load output and address strobe output settings are disabled.

BAA: Burst flash ROM address advance output. This function is valid

when the address advance output setting is enabled.

P95: General purpose input/output port. This function is valid when the

address advance output and column address strobe output settings are

disabled.

P95

P96: General purpose input/output port. This function is enabled when the

column address strobe output setting is disabled.

83

84

P96

WE

P97

F

WE: Write strobe output for 16-bit SRAM. This function is enabled when

the write strobe output setting is enabled.

P97: General purpose input/output port. This function is enabled when the

write strobe output setting is prohibited.

9

AV^CC

AVRH

A/D converter power supply

A/D converter power supply (GND)

10

11

AV^SS/AVRL

24, 55,

110

V^CC

Power supply pins

34, 52,

75, 101

VSS

Power supply pins (GND)

10

MB91307B

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillator feedback resistance

approx. 1 MΩ

X1

clock input

X0

A

STANDBY

CONTROL

• CMOS hysteresis input

with pull-up resistance (25 kΩ)

B

digital input

• CMOS level input/output

with standby control

digital output

C

digital input

STANDBY CONTROL

• Analog input

with switch

D

analog input

CONTROL

(Continued)

11

MB91307B

Type

Circuit

Remarks

• CMOS level output

CMOS level hysteresis input

with standby control

digital output

F

digital input

STANDBY CONTROL

• CMOS level input

without standby control

G

digital input

• CMOS level hysteresis input

without standby control

H

digital input

• CMOS level input

• CMOS level hysteresis input

without standby control

digital output

I

digital input

• CMOS level input

digital output

M

(Continued)

12

MB91307B

(Continued)

Type

Circuit

Remarks

• CMOS level input/output

with standby control

withpull-downresistance (25kΩ)

digital output

P

CONTROL

digital input

STANDBY CONTROL

• Open drain output

CMOS level hysteresis input

with standby control

Open drain control

digital output

Q

digital input

STANDBY CONTROL

13

MB91307B

■ HANDLING DEVICES

❍MB91307 Series

• Preventing Latchup

When CMOS integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins

(other than medium- and high-withstand voltage pins), or to voltages lower than Vss, as well as when voltages

in excess of rated levels are applied between Vcc and Vss, a phenomenon known as latchup can occur. When a

latchup condition occurs, supply current can increase dramatically and may destroy semiconductor elements.

In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.

• Treatment of unused input pins

If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected

to pull-up or pull-down resistance.

• Power supply pins

Devices are designed to prevent problems such as latchup when multiple Vcc and Vss supply pins are used, by

providing internal connections between pins having the same potential. However, in order to reduce unwanted

radiation, prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output

current ratings, all such pins should always be connected externally to power supplies and ground. Also, care

must be given to connecting the Vcc and Vss pins of this device to a current source with as little impedance as

possible.

In addition, it is recommended that a bypass capacitor of 1.0 µF be connected between V^ccand Vss as close to

the pins as possible.

• Crystal oscillators

Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards

should be designed so that the X0 and X1 pins, and oscillators (or crystal oscillators), as well as bypass capacitors

connected to ground, are placed as close together as possible.

The use of printed circuit board architecture in which the X0 and X1 pins are surrounded by ground contributes

to stable operation and is strongly recommended.

• Treatment of NC pins

Any pins marked “NC” (not connected) must be left open.

• Mode pins (MD0-MD2)

These pins should be used in direct connection to Vcc or Vss. To prevent noise from causing the device to

erroneously switch into test mode, the printed circuit board design should allow the shortest possible pattern

length between mode pins and Vcc or Vss, and the connection should have as little impedance as possible.

• Operation at startup

Immediately after a power-on startup, always apply a reset initialization (INIT) at the INIT pin. Also, in order to

assure a wait period for the oscillator circuits to stabilize immediately after startup, be sure that the “L” level input

to the INIT pin continues for the required stabilization wait interval. (The INIT cycle for the INIT pin includes only

the minimum setting for the stabilization wait period.)

• Base oscillator input at startup

At power-on startup, always input a clock signal until the oscillator stabilization wait period is ended.

14

MB91307B

• Hardware standby at power-on startup

If a power-on startup is followed immediately by a hardware standby request, the reset initialization of settings

(INIT) from the INIT pin has priority. However in case of transition from the reset initialization (INIT) to hardware

standby, theoscillatorstabilizationwaitperiodisinitializedtomaximumduration, andafterreleaseofthehardware

standby request the maximum setting is applied to the oscillator stabilization wait period.

• Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

• Remarks for the external clock operation

When selecting the external clock, active X0 pin generally. Also simultaneously the opposite phase clock to X0

must be supplied to X1 pin. When using the clock along with STOP (oscillation stopped) mode, the X1 pin stops

when “H” is input in STOP mode. To prevent one output from competing against another, in this case, the stop

mode must not be used.

X0

X1

MB91307B

Using external clock (normal)

Note : Stop mode (oscillation stop mode) cannot be used.

Refer to the Data Sheet for maximum input frequency.

• Built-in DC-DC regulator

This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately

0.1 µF connected to the C pin for the regulator.

Note that the A/D converter requires a separate 3.3 V power supply.

3.3 V

VCC

C

AVCC

0.1 µF

AVRH

AVSS/AVRL

VSS

GND

15

MB91307B

• Precautions for use of stop mode

The built-in regulator in this device stops operating when the device is in stop mode. In such cases as when

increased leak current (ICCH) in stop mode, or abnormal operation or power fluctuation due to noise while in

operating mode cause the regulator to stop, the internal 2.5 V power supply can ball below the voltage at which

operation is assured. Therefore it is necessary when using the internal regulator and stop mode to assure that

the external power supply does not fall below 3.3 V. And even if this should occur, the internal regulator can be

set to restart when a reset is applied. (In this case the oscillator stabilization wait period should also be set to L

level.)

Sample use of Stop Mode with 3.3 V power supply

3.3 V

VCC

2.4 kΩ

C

7.6 kΩ

0.1 µF

VSS

GND

• Low-power consumption modes

• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the

TBCR, or time-base counter control register) and be sure to use the following sequence:

(LDI

STB

#value_of_standby, R0)

#_STCR, R12)

R0, @R12

; Write to standby control register (STCR)

; Read STCR for synchronous standby

; Read STCR again for dummy read

; NOP x 5 for timing adjustment

LDUB @R12, R0

NOP

Set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler

triggers the microcontroller to return from the standby mode.

• If you use the monitor debugger, follow the precautions below:

Do not set a breakpoint within the above array of instructions.

Do not single-step the above array of instructions.

• Executing instructions on RAM

If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005_FFFF8H to

0005_FFFF^H. (Instruction code prohibited area)

16

MB91307B

• Notes on the PS register

Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt

handler to break or the PS flag to update its display setting when the debugger is being used. As the

microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs

operations before and after the EIT as specified in either case.

• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS

instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data

event or emulator menu:

(1) D0 and D1 flags are updated earlier.

(2) The EIT handler (user interrupt/NMI or emulator) is executed.

(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as those in (1) above.

• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed

to enable interruptions when a user interrupt or NMI trigger event has occurred.

(1) The PS register is updated earlier.

(2) The EIT handler (user interrupt/NMI or emulator) is executed.

(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as that in (1) above.

• Notes on I-BUS Memory

Do not access data in the instruction cache control register or the instruction cache RAM immediately before

the RETI instruction.

❍Unique to the evaluation chip MB91V307R

• Simultaneous occurrences of a software break and a user interrupt/NMI

When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause

the following phenomena:

• The debugger stops pointing to a location other than the programmed breakpoints.

• The halted program is not re-executed correctly.

If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has

been used, avoid setting any break at the relevant location.

• Single-stepping the RETI instruction

If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly

after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being

executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant

interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.

• A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to

access to the area containing the address of a system stack pointer.

17

MB91307B

■ BLOCK DIAGRAM

FR65E

CPU Core

32

Instruction cache

1 KB

32

Bit search

RAM 128 KB

Bus Converter

DMAC 5 ch

32

External

memory

interface

32 to 16

Adapter

16

Clock control

UART

3 ch

U-TIMER

3 ch

I²C

1 ch

Interrupt

controller

External

interrupt

Reload

A/D

4 ch

timer 3-ch

Port

18

MB91307B

■ CPU AND CONTROL BLOCK

Internal Architecture

The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set

intended for built-in applications.

1. Features

• Uses of RISC Architecture

Basic instruction set: 1 instruction to 1 cycle.

• 32-bit architecture

General-purpose registers: 32-bits × 16 registers

• 4 GB linear memory space

• Built-in multipliers

32-bit × 32-bit multiplication: 5 cycles

16-bit × 16-bit multiplication: 3 cycles

• Enhanced interrupt processing

High-speed response (6 cycles)

Multiple interrupt support

Level masking functions (16 levels)

• Enhanced I/O operating instructions

Memory-to-memory transfer instructions

Bit processing instructions

• High code efficiency

Basic instruction length: 16 bits

• Low power consumption

Sleep mode, stop mode

• Gear function

19

MB91307B

2. Internal Architecture

The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction

bus (I-BUS) is connected to an on-chip instruction cache. a 32-bit ←→16-bit bus converter is connected to the

bus (F-BUS) to provide an interface between the CPU and peripheral resources. The Harvard ←→ Princeton

bus converter is connected to the both the I-BUS and D-BUS as an interface between the CPU and bus controller.

FRex CPU

D bus

I bus

32

I address

I data

Instruction

cache

32

Harvard

D address

D data

Princeton

bus

converter

32

F address

F data

RAM

32 bit

16 bit

Bus converter

16

R-bus

X-bus

Bus controller

Peripherals resource

Internal Architecture

20

MB91307B

3. Programming Model

• Basic Programming Model

32 bits

[Default values]

XXXX XXXXH

R0

R1

General-purpose register

R12

R13

AC

FP

SP

R14

R15

XXXX XXXXH

0000 0000H

PC

Program counter

Program status

PS

ILM

SCR

CCR

TBR

RP

Table base register

Return pointer

SSP

USP

System stack pointer

User stack pointer

MDH

MDL

Multiplier result registers

21

MB91307B

4. Registers

•General Purpose Register

32 bits

[Default values]

XXXX XXXXH

R0

R1

R12

R13

AC

XXXX XXXXH

0000 0000H

FP

SP

R14

R15

Registers R 0 to R 15 are general-purpose registers. These registers can be used as accumulators for compu-

tation operations, or as pointers for memory access.

Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular

applications.

R13: Virtual accumulator

R14: Frame pointer

R15: Stack pointer

Default values at reset are undefined for R0 to R14. The value for R15 is 00000000^H(SSP value).

•PS (Program Status Register)

This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.

All bits not defined in the diagram are reserved bits with read value “0” at all times. Write access to these bits

is not enabled.

31

20

16

10

0

Bit position→

8 7

ILM

SCR

CCR

PS Register

•CCR (Condition Code Register)

7

6

5

4

I

3

2

1

0

[Default value]

- - 00XXXXB

S

N

Z

V

C

CCR Register

S : Stack flag, cleared to “0” at reset.

: Interrupt flag, cleared to “0” at reset.

I

N : Negative flag, default value at reset undefined.

Z : Zero flag, default value at reset undefined.

V : Overflow flag, default value at reset undefined.

C : Carry flag, default value at reset undefined.

22

MB91307B

•SCR (System Condition code Register)

10

9

8

T

[Default value]

XX0^B

D1 D0

SCR Register

Stepwise division flags

These flags store interim data during execution of stepwise division.

Step trace trap flag

Indicates whether the step trace trap is enabled or disabled.

The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution

of user programs.

•ILM(Interrupt Level Mask Register)

20

19

18

17

16

[Defaultvalue]

01111B

ILM4 ILM3 ILM2 ILM1 ILM0

ILM Register

This register stores interrupt level mask values, for use in level masking.

The register is initialized to value 15 (01111^B) at reset.

•PC (Program Counte Registerr)

31

0

[Default value]

XXXXXXXX^H

PC

PC Register

The program counter indicates the address of the instruction that is executing.

The default value at reset is undefined.

•TBR (Table Base Register)

31

0

[Defaultvalue]

000FFC00^H

TBR

TBR Register

The table base register stores the starting address of the vector table used in EIT processing.

The default value at reset is 000FFC00^H.

23

MB91307B

•RP (Return Pointer)

31

0

[Default value]

XXXXXXXXH

RP

RP Register

The return register stores the address for return from subroutines.

During execution of a CALL instruction, the PC value is transferred to this RP register.

During execution of a RET instruction, the contents of the RP register are transferred to this PC register.

The default value at reset is undefined.

•SSP (System Stack Pointer)

31

0

[Defaultvalue]

00000000^H

SSP

SSP Register

The SSP register is the system stack pointer.

When the S flag is “0,” this register functions as the R15 register.

The SSP register can also be explicitly specified.

This register is also used as a stack pointer to indicate the stack to which the PS and PC are removed when an

EIT occurs.

The default value at reset is 00000000^H.

•USP (User Stack Pointer)

31

0

[Defaultvalue]

XXXXXXXXH

USP

USP Register

The USP register is the user stack pointer.

When the S flag is “1,” this register functions as the R15 register.

The USP register can also be explicitly specified.

The default value at reset is undefined.

This register cannot be used with RETI instructions.

•Multiply & Divide registers

31

0

MDH

MDL

Multiply & Divide Registers

The multiply and divide registers are each 32 bits in length.

The default value at reset is undefined.

24

MB91307B

■ SETTING MODE

In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating

mode.

1. Mode Pins

ThethreepinsMD2, MD1, MD0areusedinmodevectorfetchinstructions, andalsotomakesettingsintestmode.

Mode pin

Reset vector access

Mode name

Remarks

area

MD2 MD1 MD0

0

1

External ROM mode vector

Outside

Bus width is set by mode register.

2. Mode Register (MODR)

The mode data fetch instruction writes data to the address “0000_07FDH” called the mode data.

The area “0000_07FD^H” is the mode register (MODR). When a setting is made to this register, the device will

operate the mode corresponding to that setting.

The mode register can only be set by a reset source at the INIT level. It is not possible to write to this register

from a user program.

No data exists at the FR family mode register address (0000_07FFH).

< Detailed register description >

MODR

Default

7

6

0

5

0

4

0

3

0

2

1

0

Address

XXXXXXXX

0

ROMA WTH1 WTH0

0000 07FD^H

Operating mode setting bits

[bit7-3] Reserved bits

These bits should always be set to “00000.” If set to any other value, stable operation is not assured.

[bit2] ROMA (Internal RAM enable bit)

This bit indicates whether internal RAM is enabled.

ROMA

Function

Remarks

0

External ROM mode

The built-in RAM area functions as external area.

The built-in RAM area is enabled.

The 128 KB built-in RAM can be used.

1

Internal RAM mode

[bit1, 0] WTH1, WTH0 (Bus width indicator bits)

In external bus mode, these bits determine the bus width setting.

In external bus mode, the value of these bits sets the BW1, 0 bits in the AMD0 register (CS0 area).

WTH1

WTH0

Bus width

0

1

0

1

0

1

8-bit

16-bit

Setting prohibited

25

MB91307B

■ MEMORY SPACE

1. Memory Space

The FR family has 4 GB (2³²addresses) of logical address space with linear access from the CPU.

•Direct Addressing Areas

The following areas of address space are used for I/O operations.

These areas are called direct addressing areas, in which the address of an operand can be specified directly

during an instruction.

The direct areas differ according to the size of the data accessed, as follows.

→ byte data access

: 0-0FF^H

→ half word data access : 0-1FFH

→ word data access

: 0-3FFH

2. Memory Map

The following diagram illustrates memory space in the FR family.

Internal ROM

External ROM

external bus mode

Single chip mode

0000 0000H

0000 0400H

0000 0000H

0000 0400H

Direct addressing

area

I/O

See I/O map

0001 0000H

Access

prohibited

0004 0000H

0006 0000H

0004 0000H

0006 0000H

Internal RAM

128 KB

Internal RAM

128 KB

External area

Access

prohibited

0010 0000H

Access

prohibited

External area

FFFF FFFFH

: This model does not support single chip mode

26

MB91307B

•Use of Built-in RAM

The MB91307B provides 128 KB of built-in RAM. To enable use of this RAM, the mode register must be set to

internal ROM external bus mode (ROMA=1).

Precautions for use of this model

• The reset vector is fixed at 000F_FFFC^H.

• For the MB91307B, the 128Kbyte RAM area is from 0004_0000^Hto 0005_FFFFH. The area from 0006_0000H

to 000F_FFFFH is access prohibited.

• In order to use RAM the mode register must be set to internal ROM external bus mode.

• In internal ROM external bus mode the built-in RAM area can be used, but the vector area 000F_FFXX^His an

internal area and cannot be accessed externally. Please refer to the following explanation.

• When placing instruction code in RAM, nothing should be placed in the last 8 bytes of the area 0005_FFFF8h

to 0005_FFFF^H. (This is an instruction code prohibited area.)

After mode setting

After reset release

Internal ROM external bus mode

0000 0000H

0000 0400H

Direct addressing

area

I/O

Refer to I/O map

0001 0000H

Access

prohibited

Access

prohibited

0004 0000H

0006 0000H

Internal RAM

128 KB

External area

Access

prohibited

0010 0000H

External area

FFFF FFFFH

The shaded sections indicate internal areas

After mode register setting the vector area is an internal area. Therefore before writing to the mode register

it is necessary to rewrite the TBR register so that the vector area is changed to an external area.

27

MB91307B

■ USER PROGRAM INITIALIZATION

The following sequence describes an example using built-in RAM.

1. Hardware Setting Conditions

MB91307B

Normal setting

External

ROM

CS0

A19-1

1) Assume that 1 MB of external ROM is placed beginning at 0010_0000H. Place the program at this location

in the linker. (The following description can apply to other addresses than this one as well.)

2) Connect addresses A19 to A1 (1 MB) to ROM, other addresses will use CS0.

3) Set the mode pins (MD2, MD1, MD0) to external vectors.

4) Write the reset vector to 001F_FFFCH. Likewise write the mode vector to 001F_FFF8H.

2. Immediately After Reset Release

0000_0000H

MB91307B

0004_0000H

External

CS0

ROM

External

ROM

FFFF_FFFFH

1 MB of ROM can be

viewed again on the

address map.

After reset release, the CPU will attempt to load a mode vector from 000F_FFF8^H, a reset vector from

000F_FFFCH, however because this will be an external vector, the CPU will have to go externally. However

1)

the CS0 default value causes 1 MB of external ROM to be repeated in external space, so that the mode

vector and the reset vector itself will load the contents written at 001F_FFF8H and 001F_FFFCH in external

ROM.

2) The branch destination is set in the linker to an address in the area 001X_XXXXH, so that subsequent pro-

gram execution will be in this area.

28

MB91307B

3. User Program Initialization Steps

0000_0000H

MB91307B

0004_0000H

0010_0000H

External

ROM

CS0

External

ROM

001F_FFFFH

FFFF_FFFFH

1 MB of ROM space

matches 1 MB of the

address map.

1) Set the TBR register so that the interrupt table is 001F_FFXXH, then perform initialization. This process also

includes a chip select setting, and at the same time the CS0 address is set to be valid at 001X_XXXXH. The

CS0 decoding result is the same before and after the setting, so that the CPU can continue to run programs

on external ROM.

2) If necessary, initialize the contents of RAM.

3) Now initialization is complete, and the application program can be executed.

29

MB91307B

■ I/O MAP

This map shows the correlation between areas of memory space and individual registers in peripheral resources.

[How to read the map]

Register

Address

Block

+0

+1

+2

+3

PDR0 [R/W] PDR1 [R/W] PDR2 [R/W] PDR3 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

T-unit

Port Data Register

000000^H

Read/write attributes

Register default value after reset

Register name

(1-column registers at address 4n, 2-column registers at address 4n + 2…)

Left most register address

(for word access, the first column of the register contains the MSB end of the data)

Note: Default register bit values are indicated as follows:

“1” : Default value “1”

“0” : Default value “0”

“X” : Default value “X”

“-“ : No physical register at this location

30

MB91307B

Register

Address

000000^H

000004^H

000008^H

00000CH

000010^H

Block

+0

+1

+2

+3

PDR2 [R/W]

XXXXXXXX

PDR6 [R/W] PDR7 [R/W]

XXXXXXXX -------X

PDR8 [R/W] PDR9 [R/W] PDRA [R/W] PDRB [R/W]

--X--XXX XXXXXXX- XXXXXXXX XXXXXXXX

T-unit

Port Data Register

PDRG [R/W] PDRH [R/W] PDRI [R/W]

PDRJ [R/W]

XXXXXXXX

-----XXX

XXX00XXX

---XXXXX

R-bus

000018^H

to

Port Data Register

00001CH

000020^H

to

Reserved

00003CH

EIRR [R/W]

00000000

ENIR [R/W]

00000000

ELVR [R/W]

000040^H

000044^H

000048^H

00004C^H

000050^H

000054^H

000058H

00005C^H

000060^H

000064^H

000068H

Ext int

00000000

DICR [R/W] HRCL [R/W]

-------0 0--11111

TMRLR [W]

DLYI/I-unit

TMR [R]

XXXXXXXX XXXXXXXX

TMCSR [R/W]

XXXXXXXX XXXXXXXX

Reload Timer 0

Reload Timer 1

Reload Timer 2

----0000 00000000

TMR [R]

TMRLR [W]

XXXXXXXX XXXXXXXX

TMCSR [R/W]

----0000 00000000

TMR [R]

TMRLR [W]

XXXXXXXX XXXXXXXX

TMCSR [R/W]

----0000 00000000

SSR [R/W]

00001-00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

DRCL [W]

--------

SMR [R/W]

00--0-0-

UART0

U-TIMER 0

UART1

UTIM [R] (UTIMR [W] )

00000000 00000000

UTIMC [R/W]

0--00001

SSR [R/W]

00001-00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

SMR [R/W]

00--0-0-

(Continued)

31

MB91307B

Register

Address

Block

+0

+1

+2

+3

UTIM [R] (UTIMR [W] )

00000000 00000000

DRCL [W]

--------

UTIMC [R/W]

0--00001

SMR [R/W]

00--0-0-

00006C^H

000070H

000074^H

000078^H

00007CH

000080^H

000084^H

000088^H

00008C^H

000090^H

000094^H

000098H

00009C^H

0000A0^H

0000A4H

0000A8^H

0000AC^H

0000B0^H

U-TIMER 1

UART2

SSR [R/W]

00001-00

SIDR [R/W]

XXXXXXXX

SCR [R/W]

00000100

DRCL [W]

--------

UTIM [R] (UTIMR [W] )

00000000 00000000

UTIMC [R/W]

0--00001

[R/W]

U-TIMER 2

ADCR

[R]

ADCS

A/D Converter

sequential comparator

------XX XXXXXXXX

00000000 00000000

Reserved

IBCR [R/W]

00000000

IBSR [R/W]

00000000

ITBA [R/W]

------00 00000000

ITMK [R/W]

ISMK [R/W]

01111111

ICCR [R/W]

0-011111

ISBA [R/W]

00000000

IDBL [R/W]

-------0

I²C interface

00----11 11111111

IDAR [R/W]

00000000

Reserved

(Continued)

32

MB91307B

Register

Address

000200^H

000204H

000208H

00020C^H

000210^H

000214^H

000218^H

00021C^H

000220^H

000224^H

000228^H

Block

+0

+1

DMACA0 [R/W]

+2

+3

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

DMACA1 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

DMACA2 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

DMAC

00000000 00000000 00000000 00000000

DMACA3 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

DMACA4 [R/W]

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W]

00000000 00000000 00000000 00000000

00022C^H

to

00023CH

Reserved

DMAC

DMACR [R/W]

000240H

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

000244H

to

Reserved

000274H

000278^H

00027C^H

Reserved

000280H

to

Reserved

0002FCH

(Continued)

33

MB91307B

Register

Address

Block

+0

+1

+2

+3

000300^H

000304^H

Reserved

ISIZE [R/W]

------00

Instruction Cache

000308H

to

0003E0H

Reserved

Instruction Cache

Reserved

ICHRC [R/W]

0 - 000000

0003E4^H

0003E8H

to

0003ECH

BSD0 [W]

0003F0^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSD1 [R/W]

0003F4^H

0003F8^H

0003FC^H

000400^H

000404^H

000408^H

00040C^H

000410H

000414^H

000418^H

00041C^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSDC [W]

Bit Search Module

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDRG [R/W] DDRH [R/W] DDRI [R/W] DDRJ [R/W]

----000

00011000

--000000

00000000

R-bus

Port Direction Register

PFRG [R/W] PFRH [R/W]

----0000 0000000-

PFRI [R/W]

--00-00-

R-bus

Port Function Register

000420^H

to

Reserved

00043CH

(Continued)

34

MB91307B

(Continued)

Register

Address

Block

+0

ICR00 [R/W] ICR01 [R/W] ICR02 [R/W] ICR03 [R/W]

---11111 ---11111 ---11111 ---11111

ICR04 [R/W] ICR05 [R/W] ICR06 [R/W] ICR07 [R/W]

---11111 ---11111 ---11111 ---11111

ICR08 [R/W] ICR09 [R/W] ICR10 [R/W] ICR11 [R/W]

---11111 ---11111 ---11111 ---11111

ICR12 [R/W] ICR13 [R/W] ICR14 [R/W] ICR15 [R/W]

---11111 ---11111 ---11111 ---11111

ICR16 [R/W] ICR17 [R/W] ICR18 [R/W] ICR19 [R/W]

---11111 ---11111 ---11111 ---11111

ICR20 [R/W] ICR21 [R/W] ICR22 [R/W] ICR23 [R/W]

---11111 ---11111 ---11111 ---11111

ICR24 [R/W] ICR25 [R/W] ICR26 [R/W] ICR27 [R/W]

---11111 ---11111 ---11111 ---11111

ICR28 [R/W] ICR29 [R/W] ICR30 [R/W] ICR31 [R/W]

---11111 ---11111 ---11111 ---11111

ICR32 [R/W] ICR33 [R/W] ICR34 [R/W] ICR35 [R/W]

---11111 ---11111 ---11111 ---11111

ICR36 [R/W] ICR37 [R/W] ICR38 [R/W] ICR39 [R/W]

---11111 ---11111 ---11111 ---11111

ICR40 [R/W] ICR41 [R/W] ICR42 [R/W] ICR43 [R/W]

---11111 ---11111 ---11111 ---11111

ICR44 [R/W] ICR45 [R/W] ICR46 [R/W] ICR47 [R/W]

+1

+2

+3

000440^H

000444^H

000448H

00044CH

000450^H

000454^H

000458^H

00045C^H

000460^H

000464^H

000468^H

00046C^H

Interrupt Control unit

---11111

000470^H

to

00047CH

RSRR [R/W] STCR [R/W] TBCR [R/W]

10000000 *²00110011 *²00XXXX00 *¹XXXXXXXX

CTBR [W]

000480^H

000484^H

CLKR [R/W] WPR [W] DIVR0 [R/W] DIVR1 [R/W]

Clock Control unit

Reserved

00000000 *¹XXXXXXXX 00000011 *¹00000000 *¹

000488H

to

0005FC^H

*1: These registers have different default values at reset level. The value shown is the INIT level value.

*2: These registers have different default values at reset level. The value shown is the INIT level value from the INIT

pin.

35

MB91307B

Register

Address

Block

+0

+1

+2

+3

DDR2 [R/W]

00000000

000600H

000604H

DDR6 [R/W] DDR7 [R/W]

00000000 00000000

DDR8 [R/W] DDR9 [R/W] DDRA [R/W] DDRB [R/W]

--0--000 00000000 00000000 00000000

T-unit

Port Direction Register

000608^H

00060C^H

000610^H

000614^H

PFR6 [R/W] PFR7 [R/W]

11111111 -------1

PFR8 [R/W] PFR9 [R/W] PFRA [R/W] PFRB1 [R/W]

000618^H

00061C^H

000620^H

000624^H

--1--0--

PFRB2 [R/W]

00------

1111111-

0-001101

00000000

T-unit

Port Function Register

000628^H

to

Reserved

00063FH

ASR0 [R/W]

ACR0 [R/W]

000640^H

000644^H

000648^H

00064C^H

000650^H

000654^H

00000000 00000000

ASR1 [R/W]

1111XX00 00000000

ACR1 [R/W]

XXXXXXXX XXXXXXXX

ASR2 [R/W]

XXXXXXXX XXXXXXXX

ACR2 [R/W]

XXXXXXXX XXXXXXXX

ASR3 [R/W]

XXXXXXXX XXXXXXXX

ACR3 [R/W]

T-unit

XXXXXXXX XXXXXXXX

ASR4 [R/W]

XXXXXXXX XXXXXXXX

ACR4 [R/W]

XXXXXXXX XXXXXXXX

ASR5 [R/W]

XXXXXXXX XXXXXXXX

ACR5 [R/W]

XXXXXXXX XXXXXXXX

(Continued)

36

MB91307B

Register

Address

000658H

00065C^H

000660^H

000664^H

000668^H

00066C^H

000670^H

000674^H

000678^H

00067C^H

000680^H

000684^H

Block

+0

ASR6 [R/W]

+1

+2

ACR6 [R/W]

+3

XXXXXXXX XXXXXXXX

ASR7 [R/W]

XXXXXXXX XXXXXXXX

ACR7 [R/W]

XXXXXXXX XXXXXXXX

AWR0 [R/W]

XXXXXXXX XXXXXXXX

AWR1 [R/W]

011111111 11111111

AWR2 [R/W]

XXXXXXXX XXXXXXXX

AWR3 [R/W]

XXXXXXXX XXXXXXXX

AWR4 [R/W]

XXXXXXXX XXXXXXXX

AWR5 [R/W]

XXXXXXXX XXXXXXXX

AWR6 [R/W]

XXXXXXXX XXXXXXXX

AWR7 [R/W]

XXXXXXXX XXXXXXXX

T-unit

IOWR0 [R/W] IOWR1 [R/W] IOWR2 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX

CSER [R/W] CSHR [R/W]

TCR [R/W]

00000000

000000001

11111111

000684^H

to

0007F8H

Reserved

0007FCH

000800H

to

000AFCH

ESTS0 [R/W] ESTS1 [R/W] ESTS2 [R]

X0000000 XXXXXXXX 1XXXXXXX

ECTL0 [R/W] ECTL1 [R/W] ECTL2 [W] ECTL3 [R/W]

0X000000 00000000 000X0000 00X00X11

000B00^H

000B04^H

DSU

(Continued)

37

MB91307B

Register

Address

Block

+0

+1

ECNT1 [W]

+2

+3

ECNT0 [W]

000B08H

EUSA [W]

XXX00000

EDTC [W]

0000XXXX

XXXXXXXX XXXXXXXX

EWPT [R]

000B0C^H

000B10^H

00000000 00000000

EDTR0 [W]

EDTR1 [W]

XXXXXXXX XXXXXXXX

000B14^H

to

000B1CH

EIA0 [W]

000B20^H

000B24^H

000B28^H

000B2C^H

000B30^H

000B34^H

000B38^H

000B3C^H

000B40^H

000B44^H

000B48^H

000B4C^H

000B50^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA2 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA3 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA4 [W]

DSU

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA5 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA6 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA7 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTA [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTM [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPCR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued)

38

MB91307B

(Continued)

Register

Address

Block

+0

+1

EPSR [R/W]

+2

+3

000B54^H

000B58^H

000B5CH

000B60H

000B64^H

000B68^H

000B6C^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM0/EODM0 [W]

DSU

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM1/EODM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOD1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70^H

to

Reserved

000FFCH

DMASA0 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA0 [R/W]

001000^H

001004^H

001008^H

00100C^H

001010^H

001014H

001018^H

00101C^H

001020^H

001024H

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA1 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA1 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA2 [R/W]

DMAC

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA2 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA3 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA3 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA4 [R/W]

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA4 [R/W]

DMAC

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

39

MB91307B

■ INTERRUPT SOURCES AND INTERRUPT VECTORS

Interrupt number

Interrupt source

Interrupt level Offset TBR default address RN

Decimal

0

Hex

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

Reset

3FC^H

3F8H

3F4^H

3F0^H

3ECH

3E8^H

3E4^H

3E0H

3DC^H

3D8H

3D4^H

3D0H

3CCH

3C8^H

3C4H

3C0H

3BCH

3B8H

3B4^H

3B0H

3ACH

3A8^H

3A4H

3A0H

39CH

398^H

394H

390H

38C^H

388H

384H

380^H

37CH

378H

000FFFFCH

000FFFF8H

000FFFF4H

000FFFF0H

000FFFECH

000FFFE8H

000FFFE4H

000FFFE0H

000FFFDCH

000FFFD8H

000FFFD4H

000FFFD0H

000FFFCCH

000FFFC8H

000FFFC4H

000FFFC0H

000FFFBCH

000FFFB8H

000FFFB4H

000FFFB0H

000FFFACH

000FFFA8H

000FFFA4H

000FFFA0H

000FFF9CH

000FFF98H

000FFF94H

000FFF90H

000FFF8CH

000FFF88H

000FFF84H

000FFF80H

000FFF7CH

000FFF78H

Mode vector

1

System reserved

2

System reserved

3

System reserved

4

System reserved

5

System reserved

6

Coprocessor absent trap

Coprocessor error trap

INTE instruction

7

8

9

Instruction break exception

Operand break trap

Step trace trap

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

NMI request (tool)

Undefined instruction exception

NMI requ

15 (F^H)

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

Reload timer 0

6

7

11

12

13

14

8

9

Reload timer 1

Reload timer 2

10

0

UART0(RX completed)

UART1(RX completed)

UART2(RX completed)

UART0(TX completed)

UART1(TX completed)

UART2(TX completed)

DMAC0(end, error)

1

2

3

4

5

(Continued)

40

MB91307B

Interrupt number

Interrupt source

DMAC1(end, error)

Interrupt level Offset TBR default address RN

Decimal

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Hex

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

374^H

370H

36C^H

368^H

364H

360H

35C^H

358H

354^H

350H

34C^H

348H

344H

340^H

33CH

338H

334^H

330H

32C^H

328H

324H

320^H

31CH

318H

314H

310^H

30CH

308H

304^H

300H

2FCH

2F8^H

2F4H

2F0H

2EC^H

000FFF74H

000FFF70H

000FFF6CH

000FFF68H

000FFF64H

000FFF60H

000FFF5CH

000FFF58H

000FFF54H

000FFF50H

000FFF4CH

000FFF48H

000FFF44H

000FFF40H

000FFF3CH

000FFF38H

000FFF34H

000FFF30H

000FFF2CH

000FFF28H

000FFF24H

000FFF20H

000FFF1CH

000FFF18H

000FFF14H

000FFF10H

000FFF0CH

000FFF08H

000FFF04H

000FFF00H

000FFEFCH

000FFEF8H

000FFEF4H

000FFEF0H

000FFEECH

DMAC2(end, error)

DMAC3(end, error)

DMAC4(end, error)

A/D

15

I²C

System reserved

U-TIMER0

U-TIMER1

U-TIMER2

Time base timer overflow

System reserved

Delay interrupt source bit

System reserved (REALOS use)

System reserved

(Continued)

41

MB91307B

(Continued)

Interrupt number

Interrupt source

Interrupt level Offset TBR default address RN

Decimal

69

Hex

45

System reserved

2E8^H

2E4H

2E0^H

2DC^H

2D8H

2D4^H

2D0^H

2CCH

2C8^H

2C4H

2C0^H

000FFEE8H

000FFEE4H

000FFEE0H

000FFEDCH

000FFED8H

000FFED4H

000FFED0H

000FFECCH

000FFEC8H

000FFEC4H

000FFEC0H

70

46

71

47

72

48

73

49

74

4A

4B

4C

4D

4E

4F

75

76

77

78

79

80

to

50

to

2BCH

to

000FFEBCH

to

Used by INT instructions

255

FF

000H

000FFC00H

42

MB91307B

■ PERIPHERAL RESOURCES

1. Interrupt Controller

(1) Overview

The interrupt controller receives and processes arbitration of interrupts.

•Hardware Configuration

This module is configured from the following elements.

• ICR register

• Interrupt priority determination circuit

• Interrupt level and interrupt number (vector) generator

• Hold request removal request generator

•Principal Functions

This module primarily provides the following functions.

• NMI request / interrupt request detection

• Order of priority determination (according to level and number)

• Notification (to CPU) of interrupt level of source according to determination

• Notification (to CPU) of interrupt number of source according to determination

• Instruction (to CPU) to recover from stop mode when an interrupt other than NMI/interrupt level “11111” is

generated

• Generation of hold request removal requests to the bus master

43

MB91307B

(2) Register List

bit 7

6

5

4

3

2

1

0

Address:

ICR4

ICR3

ICR2

ICR1

ICR0

00000440H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

Address:

ICR4

R

ICR3

R/W

ICR2

R/W

ICR1

R/W

ICR0

R/W

00000441H

Address:

00000442H

Address:

00000443H

Address:

00000444H

Address:

00000445H

Address:

00000446H

Address:

00000447H

Address:

00000448H

Address:

00000449H

Address:

0000044AH

Address:

0000044BH

Address:

0000044CH

Address:

0000044DH

Address:

0000044EH

Address:

0000044FH

Address:

00000450H

Address:

00000451H

Address:

00000452H

Address:

00000453H

Address:

00000454H

Address:

00000455H

Address:

00000456H

Address:

00000457H

Address:

00000458H

Address:

00000459H

Address:

0000045AH

Address:

0000045BH

Address:

0000045CH

Address:

0000045DH

Address:

0000045EH

Address:

0000045FH

(Continued)

44

MB91307B

(Continued)

bit 7

6

5

4

3

2

1

0

Address:

ICR4

ICR3

ICR2

ICR1

ICR0

00000460H

00000461H

00000462H

00000463H

00000464H

00000465H

00000466H

00000467H

00000468H

00000469H

0000046AH

0000046BH

0000046CH

0000046DH

0000046EH

0000046FH

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

ICR4

R

ICR3

R/W

ICR2

R/W

ICR1

R/W

ICR0

R/W

Address:

MHALTI

R/W

LVL4

R

LVL3

R/W

LVL2

R/W

LVL1

R/W

LVL0

R/W

00000045H

HRCL

45

MB91307B

(3) Block Diagram

(“1” when LEVEL ≠ 11111)

WAKEUP

UNMI

Determine order of priority

LEVEL4

MHALTI

0

5

NMI

processing

HLDREQ

hold

request

LEVEL

determination

LEVEL,

VECTOR

generation

ICR00

RI00

VCT5

0

6

VECTOR

determination

ICR47

RI47

(DLYIRQ)

R-BUS

46

MB91307B

2. External Interrupt - NMI Control Block

(1) Overview

The External Interrupt - control block controls external interrupt requests input at the NMI and INT0-7 pins.

The request level can be selected from “H,” “L,” “rising edge,” or “falling edge” detection (except for NMI).

(2) Register List

• External interrupt enable register (ENIR)

bit

7

6

5

4

3

2

1

0

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

• External interrupt source register (EIRR)

bit

15

14

13

12

11

10

9

8

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

• Request level setting register (ELVR)

bit

15

14

13

12

11

10

9

8

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

bit

7

6

5

4

3

2

1

0

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

(3) Block Diagram

R BUS

8

9

8

Interrupt enable register

Source F/F

Interrupt

request

9

INT0

NMI

7

Gate

Edge detection circuit

Interrupt source register

Interrupt level setting register

47

MB91307B

3. REALOS Related Hardware

REALOS related hardware is used by the REALOS operating system. Therefore, when REALOS is in use, these

resources cannot be used by user programs.

1) Delay Interrupt Module

(1) Overview

The delay interrupt module is a module that generates interrupts for task switching. This module can be used

with software instructions to generate and cancel interrupts to the CPU.

(2) Register List

bit

7

6

5

4

3

2

1

0

Address :

DLYI

[R/W]

00000044H

DICR

(3) Block Diagram

R-bus

DLYI

Interrupt request

48

MB91307B

2) Bit Search Module

(1) Overview

Searches data written to input registers for “0” or “1” or change points, and outputs the value of the detected bits.

(2) Register List

31

0

Address :

0 detection data register

1 detection data register

Change point detection register

Detection results register

BSD0

BSD1

BSDC

BSRR

000003F0H

000003F4H

000003F8H

000003FCH

(3) Block Diagram

D-BUS

Input latch

Detection

mode

Address

decoder

1 detection data capture

Bit search circuit

Search results

49

MB91307B

4. 16-bit Reload Timer

(1) Overview

The 16-bit timer is configured from a 16-bit down-counter, 16-bit reload register, prescaler for internal count clock

generation, and a control register.

For the input clock signal, a selection of three internal clock signals (machine clock multiplied by 2, 8, or 32) or

external clock is provided.

The output pin (TOUT) produces a toggle output waveform at every underflow in reload mode, and a square

wave indicating counting in progress in one-shot mode.

The input pin (TIN) can be used for event input in external event count mode, and trigger input or gate input in

internal clock mode.

The external event count function can be used in reload mode or as a frequency multiplier in external clock mode.

There are three built-in 16-bit reload timer channels on this device.

Channels 0 1and 1 can be used to start DMA transfer from an interrupt signal.

(2) Register List

• Control status register (TMCSR)

15

14

6

13

12

11

10

9

8

CSL1

CSL0

MOD2 MOD1

7

5

4

3

2

1

0

MOD0

OUTL

RELD

INTE

UF

CNTE

TRG

• 16-bit timer register (TMR)

15

0

• 16-bit reload register (TMRLR)

15

50

MB91307B

(3) Block Diagram

16

8

16-bit reload register

R

|

B

U

S

Reload

RELD

OUTE

OUTL

INTE

UF

16-bit down counter

16

2

OUT

CTL.

GATE

2

IRQ

CSL1

Clock selector

CNTE

TRG

CSL0

Re-trigger

2

Port (TIN)

Port (TOT)

IN CTL.

EXCK

3

Prescaler

clear

φ

2¹2³2⁵

MOD2

MOD1

MOD0

Internal clock

3

51

MB91307B

5. U-TIMER (16 bit timer for UART baud rate generation)

(1) Overview

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set

using the combination of chip operating frequency and U-TIMER reload value.

The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event.

This device features a 3-channel built-in U-TIMER. By connecting two U-TIMER channels used as interval timers

in a cascade connection, it is possible to count intervals up to a maximum of 2³²× φ.

The available case connections are channel 0 to channel 1, and channel 1 to channel 2.

(2) Register List

15

8

7

0

UTIM

UTIMR

(R)

(W)

UTIMC

(R/W)

(3) Block Diagram

15

0

UTIMR (reload register)

Load

UTIM (timer)

Clock

Underflow

control

φ

MUX

(Peripheral clock)

Channel 0 only

f.f.

To UART

Under flow U-TIMER 1

52

MB91307B

6. UART

(1) Overview

The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing

the following features. This device features a 3-channel built-in UART.

• Full duplex double buffer

• Asynchronous (start-stop synchronized) or CLK synchronized transmission enabled

• Supports multi-processor mode

• Fully programmable baud rate

Built-in timer can be set to any desired baud rate (see U-TIMER description)

• Independent baud rate setting from external clock enabled.

• Error detection functions (parity, framing, overrun)

• Transfer signal NRZ encoded

• DMA transfer start from interrupt enabled

• DMAC interrupt source cleared by write operation to DRCL register.

(2) Register List

15

8

7

0

SCR

SSR

SMR

(R/W)

SIDR (R)/SODR (W)

DRCL

8 bit

(W)

8 bit

• Serial input register/Serial output registe (SIDR/SODR)

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

• Serial status register (SSR)

7

6

5

4

3

2

1

0

PE

ORE

FRE

RDRF TDRE

RIE

TIE

• Serial mode register (SMR)

7

6

5

4

3

1

0

MD1

MD0

CS0

SCKE

• Serial control register (SCR)

7

6

5

4

3

2

1

0

PEN

P

SBL

CL

A/D

REC

RXE

TXE

• DRCL register (DRCL)

7

6

5

4

3

2

1

0

53

MB91307B

(3) Block Diagram

Control signal

RX interrupt

(to CPU)

SC (clock)

TX clock

TX interrupt

(to CPU)

From U-TIMER

Clock select

circuit

RX clock

External clock

SC

RX control circuit

TX control circuit

SI (receiving data)

Start bit detect

circuit

Sent start

circuit

Receiving bit

counter

Sending bit

counter

Receiving parity

counter

Sending parity

counter

SO (Sending data)

Receiving status

decision circuit

Receiving shifter

Sending shifter

Receiving

end

Sending

start

SIDR

SODR

DMA receiving

error signal

(to DMAC)

R - BUS

MD1

MD0

PEN

P

PE

ORE

SBL

FRE

SMR

register

SCR

register

SSR

register

CL

RDRF

TDRE

CS0

A/D

REC

RXE

TXE

SCKE

SOE

RIE

TIE

Control signal

54

MB91307B

7. A/D Converter (Sequential comparison type)

(1) Overview

This A/D converter is a module that coverts analog input voltages to digital values, and provides the following

features.

• Minimum conversion time 5.4 µs/ch (at machine clock 33 MHz - CKLP)

• Built-in sample & hold circuit

• Resolution 10 bits (8-bit accuracy)

• Analog input: 4 channels by program selection

Single conversion mode: Conversion on 1 select channel

Scan conversion mode: Select continuous multiple channels. Up to 4 channels can be selected by program.

Continuous conversion mode: Continuous conversion on selected channel

Stop conversion mode: 1-channel conversion then pause and wait until the next start is applied

(enables synchronized conversion start)

• DMA transfer start from interrupt enabled

• Start sources can be selected from software, external trigger (falling edge), reload timer (rising edge).

(2) Register List

• Control status register (ADCS)

bit

15

14

13

12

11

10

9

8

BUSY

INT

INTE

PAUS

STS1

STS0

STRT

bit

7

6

5

4

3

2

1

0

MD1

MD0

ANS2

ANS1

ANS0

ANE2

ANE1

ANE0

• Data register (ADCR)

bit

15

14

13

12

11

10

9

8

bit

7

6

5

4

3

2

1

0

55

MB91307B

(3) Block Diagram

AVCC AVRH AVSS

Internal voltage

Sample & hold circuit

R

|

Sequential

B

U

S

Data register (ADCR)

AD control register

Channel decoder

Timing generator

Clock (CLKP)

Prescaler

ATG (External pin trigger)

Reload timer ch1 (Internal connection)

Precautions for Use:

When the A/D converter is started from an external trigger or internal timer, the ADCS register A/D start source

bits STS1, 0 are set, and at this time the input values for the external trigger and internal timer should be set to

the inactive side. If these values are set to the active side, abnormal operation may result.

When setting the STS 1, 0 bits, set ATG = “1” input, reload timer (channel 2) = “0” output.

Caution: If internal impedance is higher than the specified value, it may not be possible to obtain analog input

value sampling within the specified sampling time, so that proper results will not be obtained.

56

MB91307B

8. I²C Interface

(1) Overview

The I²C interface operates as a master/slave device on the I²C bus at serial I/O ports with IC bus support. The

following features are provided.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address/general call address detection function

• Transfer direction detection function

• Start condition repeat generation and detection function

• Bus error detection function

• 10-bit / 7-bit master/slave addressing

• Compatible with standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)

• Transfer end interrupt / bus error interrupt generation

(2) Register List

• Bus Control Register (IBCR)

15

14

13

12

11

10

9

8

Address : 000094H

Default value →

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bus Status Register (IBSR)

Address : 000095^H

Default value →

7

6

5

4

3

2

1

0

BB

RSC

AL

LRB

TRX

AAS

GCA

ADT

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• 10-Bit Slave Address Register

Address : 000096^H

15

14

13

12

11

10

9

8

TA9

TA8

R/W

0

R/W

0

Default value →

7

6

5

4

3

2

1

0

Address : 000097^H

TA7

TA6

TA5

TA4

TA3

TA2

TA1

TA0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default value →

(Continued)

57

MB91307B

(Continued)

• 10-Bit Slave Address Mask Register (ITMK)

15

14

13

12

11

10

9

8

Address : 000098H

ENTB

RAL

TM9

TM8

R/W

0

R

0

R/W

1

R/W

1

Default value →

7

6

5

4

3

2

1

0

Address : 000099^H

TM7

TM6

TM5

TM4

TM3

TM2

TM1

TM0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Default value →

• 7-Bit Slave Address Register (ISBA)

7

6

5

4

3

2

1

0

Address : 00009B^H

SA6

SA5

SA4

SA3

SA2

SA1

SA0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default value →

• 7-Bit Slave Address Mask Register (ISMK)

15

14

13

12

11

10

9

8

Address : 00009A^H

ENSB

SM6

SM5

SM4

SM3

SM2

SM1

SM0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Default value →

• Data Register (IDAR)

7

6

5

4

3

2

1

0

Address : 00009D^H

D7

D6

D5

D4

D3

D2

D1

D0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default value →

• Clock Control Register (ICCR)

15

14

13

12

11

10

9

8

Address : 00009E^H

TEST

EN

CS4

CS3

CS2

CS1

CS0

W

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Default value →

• Clock Disable Register (IDBL)

7

6

5

4

3

2

1

0

Address : 00009F^H

DBL

R/W

0

Default value →

58

MB91307B

(3) Block Diagram

ICCR

EN

I²C operation enabled

Clock enabled

IDBL

DBL

ICCR

Clock multiplier 2

CS4

CS3

CS2

CS1

CS0

Sync

2 3 4 5

32

Shift clock generator

Clock select 2 (1/12)

Shift clock

edge change

IBSR

BB

Bus busy

Repeat start

RSC

LRB

TRX

Start - stop

condition detector

Last Bit

Error

TX/RX

First Byte

ADT

AL

Arbitration lost detector

IBCR

BER

SCL

SDA

BEIE

INTE

INT

Interrupt request

IRQ

End

IBCR

SCC

Start

Master

MSS

ACK

Start - stop

condition generator

ACK OK

GC-ACK OK

GCAA

IDAR

IBSR

AAS

Slave

Global call

Slave address

compare

GCA

ENTB

ISMK

RAL

ITBA

ITMK

ISBA

ISMK

59

MB91307B

9. DMAC (DMA Controller)

(1) Overview

This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices.

DMA transfer controlled by this module increases system performance by enabling high speed transfer of many

types of data without going through the CPU.

•Hardware Configuration

This module is principally configured from the following units:

• Five independent DMA channels

• 5-channel independent access control circuit

• 32-bit address registers (reload enabled: 2 per channel)

• 16-bit transfer count registers (reload enabled: 2 per channel)

• 4-bit block count registers (1 per channel)

• External transfer request input pins: DREQ0,DREQ1,DREQ2 (ch0,1,2 only)

• External transfer request acknowledge output pins: DACK0,DACK1,DACK2 (ch0,1,2 only)

• DMA output completed pins: DEOP0,DEOP1,DEOP2 (ch0,1,2 only)

• Fly-by transfer (memory to I/O, memory to memory) (ch0,1,2 only)

• Two-cycle transfer

•Principal Functions

Data transfer using the DMAC module primarily involves the following functions:

• Supports independent data transfer on multiple channels (5 ch)

(1) Order of priority (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)

(2) The order can be reversed between ch.0-ch.1.

(3) DMAC startup sources

• Input from an external-only pin (edge detection/level detection, ch0,1,2 only)

• Request from a built-in peripheral (shared interrupt request, including external interrupts)

• Software request (register write)

(4) Transfer modes

• Demand transfer / burst transfer / step transfer / block transfer

• Addressing mode 32-bit full address designation (increment/decrement/fixed)

(address increment can be specified up to -255 to +255)

• Data type, byte / half-word / word length

• Single-shot / reload selection available

60

MB91307B

(2) Register Descriptions

(bit) 31

DMACA0 0000200H

24 23 16 15 08 07

00

ch.0 Control/status register A

DMACB0 0000204H

DMACA1 0000208H

DMACB1 000020CH

DMACA2 0000210H

DMACB2 0000214H

DMACA3 0000218H

DMACB3 000021CH

DMACA4 0000220H

DMACB4 0000224H

DMACR 0000240H

ch.0 Control/status register B

ch.1 Control/status register A

ch.1 Control/status register B

ch.2 Control/status register A

ch.2 Control/status register B

ch.3 Control/status register A

ch.3 Control/status register B

ch.4 Control/status register A

ch.4 Control/status register B

Overall control register

DMASA0 0001000H

DMADA0 0001004H

DMASA1 0001008H

DMADA1 000100CH

DMASA2 0001010H

DMADA2 0001014H

DMASA3 0001018H

DMADA3 000101CH

DMASA4 0001020H

DMADA4 0001024H

ch.0 Transfer source address register

ch.1 Transfer source address register

ch.2 Transfer source address register

ch.3 Transfer source address register

ch.4 Transfer source address register

61

MB91307B

(3) Block Diagram

Counter

Peripheral start request/stop

input

DMA start

source selection

circuit & request

acceptance

DMA transfer request to

bus controller

Buffer

Selector

External pin start request/stop

input

control

DTC two-stage register

DTCR

Counter

Buffer

DSS [3:0]

Priority

circuit

IRQ

[4:0]

To interrupt controller

Read/write

control

Selector

Read

Write

ERIR, EDIR

MCLREQ

BLK register

Peripheral interrupt clear

Status

transition

circuit

TYPE, MOD, WS

DDNO register

DDNO

To bus

controller

DMA controller

DDAD two-stage register

SDAM, SASZ [7:0] SADR

Write back

Access

address

DDAD two-stage register

DADM, DASZ [7:0] DADR

Write back

DMAC 5-channel Block Diagram

62

MB91307B

10. External Interface

(1) Overview

The external interface controller controls the interface between the LSI’s internal bus and external memory or I/

O devices.

This section describes the functions of the external interface.

(2) Features

• Up to 32 bit-length (4 Gbyte space) address output.

• Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings.

Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type)

Page mode ROM/flash memory (2/4/8 page size enabled)

Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.)

Address/data multiplexed bus (8 bit/16 bit width only)

Synchronous memory* (ASIC built-in memory etc.)

*: Does not connect to synchronous SRAM.

• 8 independent bank (chip select area) settings, each with corresponding ship select output available

Each area size can be set in multiples of 64 KB (from 64 KB to 2 GB per chip select area).

Each area can be set in any desired area of logic address space (boundaries limited by area size).

• The following functions can be independently set for each chip select area.

Chip select area enable/disable (no access to prohibited areas)

Access timing type for each area, etc.

Detailed access timing settings (individual access type settings for wait cycle, etc.)

Data bus width setting (8 bit/16 bit)

Byte ordering endian setting* (big or little).

*: CS0 area available with big endian only.

Write prohibited setting (read-only areas)

Internal cache loading enable/disable settings

Pre-fetch function enable/disable settings

Maximum burst length setting (1,2,4,8)

• Different detailed timing settings for each access timing type

Different settings can be used for each chip select area even for the same access timing type.

Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas)

Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas)

First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas)

Different idle, recovery cycles setup delay insertion etc. enabled

• Fly-by transfer with DMA enabled

Transfer between memory and I/O with 1 access

Memory wait cycle can be synchronized with I/O wait cycle during fly-by

Hold time can be obtained by delaying transfer access only

Specific idle/recovery cycles can be set for fly-by transfer

• External bus arbitration using BRQ and BGRNT enabled

• Pins not used in external interface can be set for use as general purpose I/O ports

63

MB91307B

(3) Block Diagram

Internal

address bus

Internaldata

bus

32

External data bus

switch

write buffer

read buffer

MUX

DATA BLOCK

ADDRESS BLOCK

+1 or +2

External address bus

address buffer

ASR

ASZ

CS0 CS7

comparator

RD

External pin control block

WR0, WR1

AS, BAA

All block control

BRQ

BGRNT

RDY

resisters &

controls

(4) I/O Pins

These are the external interface pins. (Some pins have dual functions.)

< Normal bus interface >

A24 to A0, D31 to D16

CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7

AS, SYSCLK, MCLK

RD

WE, WR0 (UUB) , WR1 (ULB)

RDY, BRQ, BGRNT

< Memory interface >

MCLK

LBA ( = AS) , BAA*

*: For burst ROM, Flash use

64

MB91307B

< DMA interface >

IOWR, IORD

DACK0, DACK1, DACK2

DREQ0, DREQ1, DREQ2

DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2

(5) Register List

Address 31

00000640^H

00000644^H

00000648^H

0000064C^H

00000650^H

00000654^H

00000658^H

0000065C^H

00000660^H

00000664^H

00000668^H

0000066C^H

24 23

16 15

08 07

ACR0

ACR1

ASR2

ACR3

ACR4

ACR5

ACR6

ACR7

AWR1

AWR3

AWR5

AWR7

00

ASR0

ASR1

ASR2

ASR3

ASR4

ASR5

ASR6

ASR7

AWR0

AWR2

AWR4

AWR6

00000670^HReserved Reserved Reserved Reserved

00000674^HReserved Reserved Reserved Reserved

00000678H

0000067CH Reserved Reserved Reserved Reserved

00000680H CSER CHER Reserved TCR

IOWR0

IOWR1

IOWR2

Reserved

00000684H Reserved Reserved Reserved Reserved

00000688^HReserved Reserved Reserved Reserved

0000068CH Reserved Reserved Reserved Reserved

• • •

000007F8^HReserved Reserved Reserved Reserved

000007FCH Reserved (MODR) Reserved Reserved

• • •

Reserved: This address is reserved, and should always be set to “0.”

MODR: Cannot be accessed from user programs.

65

MB91307B

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0 V)

Rating

Parameter

Supply voltage

Symbol

Unit

Remarks

Min

Max

V^CC

AV^CC

AVRH

V^I

VSS − 0.5

VSS − 0.3

−2.0

VSS + 4.0

VCC + 0.3

V

*1

*2

Analog supply voltage

Analog reference voltage

Input voltage

V

Analog pin input voltage

V^IA

AVCC + 0.3

VCC + 0.3

2.0

V

Output voltage

VO

V

Maximum clamp current

I^CLAMP

Σ| ICLAMP |

I^OL

mA

mW

°C

*6

*3

*4

Total maximum clamp current

L level maximum output current

L level average output current

L level maximum total output current

L level average total output current

H level maximum output current

H level average output current

H level maximum total output current

H level average total output current

Power consumption

20

10

IOLAV

ΣIOL

8

100

50

ΣI^OLAV

IOH

*5

*3

*4

−10

−4

IOHAV

ΣI^OH

ΣIOHAV

P^D

−50

−20

750

+70

+150

*5

Operating temperature

TA

0

Storage temperature

TSTG

°C

*1 : V^CCmust not be lower than VSS - 0.3 V.

*2 : AV^CCand AVRH shall never exceed VCC+0.3 V. Also AVRH shall never exceed AVCC.

*3 : Maximum output current determines the peak value of any one of the corresponding pins.

*4 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the

corresponding pins.

*5 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the

corresponding pins.

*6 : • Applicable to pins: P20 to P27, P60 to P67, P70, PJ0 to PJ7, PI0 to PI5, PH0 to PH7, PB0 to PB5,

PA0 to PA7, P80 to P82, P85, P90 to P97, AN0 to AN3

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied with a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the

microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

66

MB91307B

• Notethatifa+Bsignalisinputwhenthemicrocontrollerpowersupplyisoff(notfixedat0V), thepowersupplyis

provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits:

• Input/Output Equivalent circuits

Protective diode

VCC

P-ch

Limiting

resistance

+B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

2. Recommended Operating Conditions

(VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

3.0

3.6

V

In normal operation

Supply voltage

In stop mode with RAM

status maintained

3.0

3.6

Analog supply voltage

Analog reference voltage

Operating temperature

AVCC

AVRH

T^A

VSS − 0.3

AV^SS

0

VSS + 3.6

AVCC

V

+70

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

67

MB91307B

3. DC Characteristics

(VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Parameter

Symbol Pin name

Condition

Unit Remarks

Min

Typ

Max

V^IH

See note *

0.7 × VCC

VCC + 0.3

V

“H” level input

voltage

Input pins

other than *

Hysteresis

input

VHIS

0.8 × VCC

VSS

VCC + 0.3

V

0.25 ×

VCC

V^IL

See note *

V

“L” level input

voltage

Input pins

other than *

Hysteresis

input

V^ILS

VSS

0.2 × VCC

V

D16 to D31

A00 to A24

P60 to PJ7

“H” level output

voltage

VCC = 3.0 V

IOH = −4.0 mA

VOH

VCC − 0.5

VCC

V

D16 to D31

A00 to A24

P60 to PJ7

“L” level output

voltage

V^CC= 3.0 V

IOL = 8.0 mA

V^OL

VSS

0.4

Input leak

current

(Hi-Z output leak

current)

D16 to D31

A00 to A24

P60 to PJ7

V^CC= 3.6 V

0.45 V<VI<VCC

ILI

−5

+5

µA

kΩ

VCC = 3.6 V

VI = 0.45 V

Pull-up resistance

R^UP

INIT

12

25

100

Pull-down

resistance

VCC = 3.6 V

VI = 3.3 V

RDOWN

P82/BRQ

kΩ

(4x

fC = 16.5 MHz

VCC = 3.3 V

multiplied)

66 MHz

I^CC

150

mA

operation

Supply current

VCC

fC = 16.5 MHz

VCC = 3.3 V

ICCS

ICCH

50

mA Sleep mode

TA = 25 °C

VCC = 3.3 V

µA Stop mode

Other than:

VCC

Input capacitance

C^IN

VSS

10

pF

AVCC

AVSS

* : Pins without hysteresis input pins: D16 to D31, RDY, BRQ, INIT

68

MB91307B

4. AC Characteristics

(1) Clock Timing Standards

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Sym-

bol

name

Parameter

Condition

Unit

Remarks

PLL system*¹

(self oscillation 16.5MHz,

multiplied x4,maximum

internal operation 66MHz)

Min

Max

X0

X1

Clock frequency (1)

Clock cycle time

f^C

t^C

f^C

fC

t^C

12.5

16.5 MHz

X0

X1

60.6

33

ns

X0

X1

Self oscillation (x2

frequency input)

Clock frequency (2)

Clock frequency (3)

Clock cycle time

10

40

16

MHz

X0

X1

33

X0

X1

100

ns External clock

ns

P^WH

PWL

X0

X1

Input clock pulse width

Input clock rise, fall time

t^CR

tCF

X0

X1

8

ns

(tCR + tCF)

f^CP

fCPP

f^CPT

tCP

0.78*²

66

33

66

MHz CPU system

Internal operating clock frequency

Internal operating clock cycle time

MHz Peripheral system

MHz External bus system

15.2 1280*²ns CPU system

t^CPP

tCPT

30.3 1280*²ns Peripheral system

15.2 1280*²ns External bus system

*1 : When using the PLL, the clock frequency should be around 12.5 MHz to 16.5 MHz.

*2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillator

circuit PLL and a gear ratio of 1/16.

69

MB91307B

•Clock timing measurement conditions:

tC

0.8 VCC

0.2 VCC

Output pin

C = 50 pF

PWL

PWH

tCR

tCF

•Warranted operating range

VCC (V)

Warranted operating temperature:

(T^A= 0 °C to +70 °C)

f^CPPis represented by the shaded area

1.95

1.65

fCP / fCPP

(MHz)

0

0.78

33

Internal clock

66

• External/internal clock setting range

(MHz)

f^CP,

f^CPT

66

CPU system

fCPP

33

Peripheral, external bus systems

16.5

CPU: Divided ratio for peripherals

4 : 4

2 : 2

1 : 2

Notes :• When using the PLL, the external clock input should be around 16.5 MHz.

• Set PLL oscillator stabilization time > 300 µs.

• The internal clock gear setting should be within the values shown in (1) clock timing standards.

70

MB91307B

(2) Clock Output Timing

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Symbol

Conditions

Remarks

Parameter

Cycle time

Pin name

Unit

Min

Max

t^CYC

MCLK, SYSCLK

tCPT

ns *1

ns *2

MCLK↑→MCLK↓

SYSCLK↑→SYSCLK↓

t^CHCL

1/2 × tCYC − 3 1/2 × tCYC + 3

MCLK↓→MCLK↑

SYSCLK↓→SYSCLK↑

t^CLCL

MCLK, SYSCLK

ns *3

tCYC

tCHCL

tCLCH

VOH

MCLK, SYSCLK

VOL

*1 : t^CYCrepresents the frequency of one clock cycle including the gear period.

*2 : The values shown represent standards for × 1 gear period.

For gear period settings of 1/2, 1/4, 1/8, use the following formula replacing n with the value 1/2, 1/4, 1/8

respectively.

(1/2 × 1/n) × tCYC − 10

*3 : The values shown represent standards for × 1 gear period.

(3) Reset and Hardware Standby Input Standards

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

name

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Hardware standby input time

t^HSTL

HST

tCP × 5

ns

INIT input time

(power-on)

*

t^INTL

INIT

INIT input time

(other than power-on)

t^CP× 5

ns

tRSTL, tHSTL, tINTL

HST

INIT

0.2 VCC

* : INIT input time (at power-on)

FAR, Ceralock: φ × 2¹⁵or greater recommended

Crystal:

φ : Power on → X0/X1 period × 2

φ × 2²¹or greater recommended

71

MB91307B

(4) Normal Bus Access Read/Write Operation

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Condition

Remarks

Parameter

Symbol

Pin name

Unit

Min

3

Max

CS0 to CS7 setup

CS0 to CS7 hold

tCSLCH

tCSHCH

ns

MCLK, SYSCLK,

CS0 to CS7

3

tCYC/2 + 6

MCLK, SYSCLK,

A24 to A00

Address setup

Address hold

t^ASCH

tCHAX

t^AVDV

3

ns

MCLK, SYSCLK,

A24 to A00

tCYC/2 + 6

Valid address →

valid data input time

A24 to A00,

D31 to D16

3/2 × tCYC −

*

11

t^CHWL

t^CHWH

6

ns

MCLK, SYSCLK,

WR0 to WR1

WR0 to WR1 delay time

WR0 to WR1 minimum

pulse width

WR0 to WR1

tWLWH

tCYC − 3

ns

Data setup→WRx↑

tDSWH

tWHDX

t^CHRL

tCHRH

tRLDV

tCYC

ns

WR0 to WR1,

D31 to D16

WRx↑→data hold time

5

6

MCLK, SYSCLK,

RD

RD delay time

RD↓→valid data input time

t^CYC− 10

*

Data setup

→RD↑time

RD

D31 to D16

tDSRH

10

ns

RD↑→data hold time

RD minimum pulse width

AS setup

tRHDX

tRLRH

0

ns

RD

tCYC − 3

tASLCH

tASHCH

3

MCLK, SYSCLK,

AS

AS hold

* : To extend bus time by automatic wait insertion or RDY input, add to this value (t^CYC× number of extended cycles).

72

MB91307B

t

CYC

BA1

VOH

MCLK,

SYSCLK

tASLCH

tASHCH

VOH

AS

LBA

VOL

tCSLCH

VOL

tCSHCH

VOH

CS0 CS7

tASCH

tCHAX

VOH

VOL

VOH

VOL

A23 A00

tCHRL

tCHRH

tRLRH

RD

VOH

VOL

tRHDX

tRLDV

tDSRH

tAVDV

D31 D16

VOH

VOL

VOH

VOL

tCHWL

tCHWH

tWLWH

VOH

WR0 WR1

VOL

tWHDX

tDSWH

VOH

VOL

VOH

VOL

Write

D31 D16

73

MB91307B

(5) Ready Input Timing

Parameter

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Remarks

Symbol

Pin name

Condition

Unit

Min

Max

RDY setup time →MCLK↑,

SYSCLK↑

MCLK, SYSCLK,

RDY

t^RDYS

t^RDYH

10

ns

MCLK↑, SYSCLK↑

RDY hold time

MCLK, SYSCLK,

RDY

0

tCYC

VOH

MCLK,

VOL

SYSCLK

tRDYH

tCHASL

tRDYS

RDY

Wait applied

VOH

VOL

RDY

Wait not applied

VOH

VOL

74

MB91307B

(6) Hold Timing

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

3

Max

13.5

t^CHBGL

t^CHBGH

ns

MCLK, SYSCLK,

BGRNT

BGRNT delay time

3

Pin floating

→BGRNT↓time

tXHAL

tHAHV

tCYC − 10

tCYC + 10

ns

BGRNT

BGRNT↑→valid time

Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT changes.

tCYC

VOH

MCLK,

SYSCLK

BRQ

tCHBGH

tCHBGL

VOH

BGRNT

VOL

tHXAL

tHAHV

Pins

High-Z

75

MB91307B

(7) UART Timing

Parameter

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Symbol Pin name Condition

Unit Remarks

Min

Max

SC0 to SC2

Serial clock cycle time

t^SCYC

t^SLOV

8 t^CYCP

ns

SC0 to SC2

SO0 to SO2

SCLK↓ →SOUT delay time

−80

100

60

80

Internal

shift lock

mode

SC0 to SC2

SI0 to SI2

Valid SIN →SCLK↑

tIVSH

tSHIX

ns

SC0 to SC2

SI0 to SI2

SCLK↑ →valid SIN hold time

SC0 to SC2

Serial clock “H” pulse width

Serial clock “L” pulse width

tSHSL

tSLSH

4 t^CYCP

ns

4 tCYCP

SC0 to SC2

SO0 to SO2

External

shift lock

mode

SCLK↓ →SOUT delay time

Valid SIN→SCLK↑

t^SLOV

t^IVSH

t^SHIX

150

ns

SC0 to SC2

SI0 to SI2

60

SC0 to SC2

SI0 to SI2

SCLK↑→valid SIN hold time

Notes: • These AC standards are for operation in CLK synchronized mode.

• t^CYCPis the cycle time of the peripheral system clock.

• Internal Shift Clock Mode

tSCYC

VOH

SC0, SC1

SO0, SO1

VOL

tSLOV

VOL

VOH

VOL

tIVSH

tSHIX

VOH

VOL

VOH

VOL

SI0, SI1

• External Shift Clock Mode

SC0, SC1

tSLSH

tSHSL

VOH

VOL

tSLOV

VOH

VOL

SO0, SO1

SI0, SI1

tIVSH

tSHIX

VOH

VOL

VOH

VOL

76

MB91307B

(8) Timer Clock Input Timing

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

t^TIWH

tTIWL

Input pulse width

TIN0 to TIN2

2 tCYCP

ns

Note: t^CYCPis the cycle time of the peripheral system clock.

TIN0 to TIN2

tTIWL

tTIWH

(9) Trigger Input Timing

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Parameter

Symbol Pin name Condition

t^ATGXATG

Unit Remarks

Min

Max

A/D startup trigger input time

5 tCYCP

ns

Note: t^CYCPis the cycle time of the peripheral system clock.

tATGX, tINP, tPTG

ATG

77

MB91307B

(10) DMA Controller Timing

(V^CC= 3.0 V to 3.6 V , VSS = AVSS = 0 V, TA = 0 °C to +70 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

DREQ 0 to DRE2

DSTP 0 to DSTP2

DREQ input pulse width

DSTP input pulse width

t^DRWH

t^DSWH

tCLDL

5 t^CYC

5 tCYC

ns

6

MCLK, SYSCLK,

DACK0 to DACK2

DACK delay time

DEOP delay time

IORD delay time

IOWR delay time

ns

tCLDH

t^CLEL

MCLK, SYSCLK,

DEOP 0 to DEOP2

t^CLEH

t^CLIRL

t^CLIRH

t^CLIWL

t^CLIWH

MCLK, SYSCLK

78

MB91307B

tCYC

BA1

BA2

VOH

MCLK, SYSCLK

VOL

tCLDL

tCLDH

VOH

VOL

DACK0 DACK2

DEOP0 DEOP2

tCLEL

tCLEH

VOH

VOL

tCLIRL

tCLIRH

IORD

tCLIWL

tCLIWH

IOWR

tDRWH

VOH

DREQ0 DREQ2

VOL

tDSWH

VOH

DSTP0 DSTP2

VOL

79

MB91307B

5. A/D Converter Electrical Characteristics

(VCC = AVCC = +3.0 V to +3.6 V, VSS = AVSS = 0 V, AVRH = +3.0 V to +3.6 V, TA = 0 °C to +70 °C)

Value

Typ

10

Parameter

Symbol Pin name

Unit

Min

Max

10

Resolution

Total error

Linear error

BIT

LSB

µs

± 10

± 3.0

± 2.5

+ 10

Differential linear error

Zero transition error

Full scale transition error

Conversion time

V^OT

AN0 to AN3

− 10

+ 0.5

V^FST

AN0 to AN3 AVRH − 10 AVRH − 1.5 AVRH + 10

5.4 *¹

Analog port input current

Analog input voltage

Reference voltage

IAIN

AN0 to AN3

AVRH

0.1

10

µA

VAIN

AVss

AVRH

AVCC

V

I^A

IAH

IR

600

µA

Supply current

AVCC

10 *²

µA

Reference voltage supply current

Inter-channel variation

AVRH

I^RH

10 *²

5

µA

AN0 to AN3

LSB

*1 : At V^CC= AVCC = 3.0 V to 3.6 V, machine clock 33 MHz.

*2 : Current in CPU stop mode with A/D converter not operating (V^CC= AVCC = AVRH = 3.6 V)

Notes : • The relative error increases as AVRH is reduced.

• The output impedance on the external analog input circuit should be used as follows.

External circuit output impedance < 7 kΩ (provisional value)

If the output impedance on the external circuit is too great, the analog voltage sampling time may be insufficient.

80

MB91307B

Definition of A/D Converter Terms

• Resolution

Indicates the ability of the A/D converter to discriminate analog variation

• Linear error

Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s

zero transition point (00 0000 0000←→00 0000 0001) and full scale transition point (11 1111 1110←→11

1111 1111)

• Differential linear error

Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output

code.

[Linear Error]

[Differential linear error]

3FF

3FE

3FD

Actual variation

Theoretical

N − 1

N − 2

N − 1

N − 2

{1 LSB × (N − 1) + VTO}

VFST

Actual variation

(measured

value)

VNT

(measured

value)

004

003

002

001

V(N − 1)T

(measured

value)

Actual variation

VNT

(measured value)

Theoretical values

Actual variation

(measured value)

VTO

AVRL

AVRH

AVRL

AVRH

Analog input

[LSB]

V^NT− {1 LSB × (N − 1) + VOT}

Linear error in digital output N

=

1 LSB

V (^N+ 1) T − VNT

Differential linear error in digital output N =

−1

[LSB]

1 LSB

V^FST− VOT

1 LSB =

1 LSB” =

[V]

1022

AVRH − AVRL

[V]

(theoretical value)

1024

VOT : Voltage at which the digital output transitions from (000) H to (001) H.

V^FST: Voltage at which the digital output transitions from (3FE) H to (3FF) H.

V^NT: Voltage at which the digital output transitions from (N-1) to N.

81

MB91307B

• Total error

Expresses the difference between actual and theoretical values as error, including zero transition error, full-

scale error, and linearity error.

[Total error]

3FF

Actual variation

1.5 LSB

3FE

{1 LSB × (N − 1) + 0.5 LSB

3FD

VNT

(measured

value)

004

003

002

001

Actual variation

theoretical value

0.5 LSB

AVRL

AVRH

Analog input

V^NT− {1 LSB” × (N − 1) + 0.5 LSB”}

Total error in digital output N =

[LSB]

1 LSB”

VOT” (theoretical value) = AVRL + 0.5 LSB” [V]

V^FST” (theoretical value) = AVRH − 1.5 LSB” [V]

VNT : Voltage at which digital output transitions from (N-1) to N.

82

MB91307B

■ EXAMPLE CHARACTERISTICS

(1) Sample output voltage characteristics (TA = +25 °C)

Sample output H voltage (VOH) characteristics

Sample output L voltage (VOL) characteristics

3.6

3.4

3.2

3.0

2.8

0.4

0.3

0.2

0.1

0.0

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

Supplyvoltage(V)

(2) Sample input voltage characteristics (T^A= +25 °C)

Sample input H/L level characteristics (hysteresis)

Sample input H/L level characteristics (CMOS)

3.0

2.0

VIH

2.0

VIH

VIL

1.0

0.0

VIL

0.0

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

Supplyvoltage(V)

(3) Sample supply current characteristics

Sample supply current (ICC) characteristics

Sample supply current (I^CC) characteristics

(T^A= +25 °C, 66 MHz)

(V^CC= 3.3 V, 66 MHz)

200

150

100

50

200

150

100

50

0

0.0

3.0

3.2

3.4

3.6

0

25

70

Supply voltage (V)

Temperature ( °C)

(Continued)

83

MB91307B

(Continued)

Sample sleep current (ICCS) characteristics

(T^A= +25 °C, 33 MHz)

(V^CC= 3.3 V, 33 MHz)

50

40

30

20

50

40

30

20

3.0

3.2

3.4

3.6

0

25

70

Supply voltage (V)

Temperature ( °C)

Sample A/D supply current (IA) characteristics

Sample A/D reference current (IR) characteristics

(T^A= +25 °C, 33 MHz)

500

400

300

200

500

400

300

200

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

(4) Port resistance characteristics

Sample pull-up resistance characteristics

Sample pull-down resistance characteristics

(T^A= +25 °C)

30

25

20

15

30

25

20

15

3.0

3.2

3.4

3.6

3.0

3.2

3.4

3.6

Supply voltage (V)

84

MB91307B

■ ORDERING INFORMATION

Part number

Package

Remarks

120-pin, Plastic LQFP

(FPT-120P-M21)

MB91307BPFV

MB91V307RCR

Lead-free package

For development tool use

135-pin, Ceramic PGA

(PGA-135C-A02)

85

MB91307B

■ PACKAGE DIMENSION

120-pin, Plastic LQFP

(FPT-120P-M21)

18.00±0.20(.709±.008)SQ

16.00±0.10(.630±.004)SQ

90

61

91

60

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

INDEX

0~8°

"A"

120

31

0.10±0.05

(.004±.002)

(Stand off)

1

30

LEAD No.

0.145 ⁺–0⁰.^.0⁰3⁵

0.60±0.15

(.024±.006)

0.22±0.05

(.009±.002)

M

0.50(.020)

0.08(.003)

.006 ⁺^–.^.⁰⁰⁰⁰¹²

0.25(.010)

C

2001 FUJITSU LIMITED F120033S-c-3-3

Dimensions in mm (inches)

86

MB91307B

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0212

FUJITSU LIMITED Printed in Japan


型号：	MB91307B
厂家：	FUJITSU
描述：	32-Bit Microcontroller 32位微控制器微控制器
文件：	总87页 (文件大小：822K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB91307B [FUJITSU]

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