MB91350A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-16504-3E

32-Bit Proprietary Microcontroller

CMOS

FR60 MB91350A Series

MB91F355A/F356B/355A/354A/V350A

■ DESCRIPTION

The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC

CPU, incorporating a variety of I/O resources and bus control features for embedded control applications which

require high CPU performance for

This FR60 family is based on FR30 and FR40 families and enhanced is bus access. The FR60 family is a line of

single-chip oriented microcontrollers incorporating a wealth of peripheral resources.

The FR60 family is optimized for embedded control applications requiring high processing power of the CPU,

such as DVD player, navigation, high performance Fax machine, and printer controls.

■ FEATURES

1. FR CPU

• 32-bit RISC, load/store architecture with a five-stage pipeline

• Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz)

• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle

• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift

etc.

• Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store in-

structions

(Continued)

■ PACKAGE

176-pin plastic LQFP

(FPT-176P-M02)

I²C license

Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these components in an I²C system

provided that the system conforms to the I²C Standard Specification as defined by Philips.

MB91350A Series

• Register interlock functions: Facilitating coding in assemblers

• On-chip multiplier supported at the instruction level.

Signed 32-bit multiplication: 5 cycles.

Signed 16-bit multiplication: 3 cycles

• Interrupt (PC, PS save): 6 cycles, 16 priority levels

• Harvard architecture allowing program access and data access to be executed simultaneously

• FR family instruction compatible

2. Bus Interface

• Maximum operating frequency: 25 MHz

• Capable of up to 24-bit address full output (16 MB of space)

• 8,16-bit data output

• Built-in pre-fetch buffer

• Non-used data and address pin are usable as general I/O port.

• Capable of chip-select signal output for completely independent four areas settable in 64 KB minimum

• Support for various memory interfaces:

SRAM, ROM/Flash,

page mode Flash ROM, page mode ROM

• Basic bus cycle: 2 cycles

• Programmable automatic wait cycle generator capable of inserting wait cycles for each area

• RDY input for external wait cycles

• Support for fly-by transfer for DMA, which enables wait control of independent I/O

3. Mounted Memory

Memory

MB91V350A

No

MB91F355A

512 KB

16 KB

MB91F356B

256 KB

16 KB

MB91355A

512 KB

16 KB

MB91354A

384 KB

8 KB

ROM

RAM (stack)

16 KB

RAM (executable)

16 KB

8 KB

4. DMAC (DMA Controller)

• Capable of simultaneous operation of up to 5 channels (3 channels for external→external operation)

• Three transfer sources (external pin, internal peripheral, software) selectable by software. (Transfer can be

started from UART0/1/2.)

• Addressing using 32-bit full addressing mode (increment, decrement, fixed)

• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)

• Support for fly-by transfer (between external I/O and memory)

• Selectable transfer data size: 8, 16, or 32-bit

• Multi-byte transfer enabled (by software)

• DMAC descriptor in IO areas (200^Hto 240^H, 1000^Hto 1024^H)

5. Bit Search Module (for REALOS)

• Search for the position of the bit 1/0-changed first in 1 word from the MSB

6. Various Timers

• 4 channels of 16-bit reload timer (including 1 channel for REALOS):

Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch3)

• 16-bit free-running timer: 1 channel.

Output compare module: 8 channels. Input capture module: 4 channels

• 16-bit PPG timer 6 channels

7. UART

• UART Full duplex double buffer 5 channel

• Selectable parity On/Off

• Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable

(Continued)

2

MB91350A Series

(Continued)

• Internal timer for dedicated baud rate

• External clock can be used as transfer clock

• Assorted error detection functions (for parity, frame, and overrun errors)

• 115 Kbps support

8. SIO

• 3 channels for 8-bit data serial transfer

• Shift clock selectable from among internal three and external one

• Shift direction selectable (transfer from LSB or MSB) selectable

9. Interrupt Controller

• Total of 17 external interrupt lines (1 nonmaskable interrupt pin and 16 normal interrupt pins available for Wake

Up from STOP)

• interrupt from internal peripheral

• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt

10. D/A Converter

• 8-bit resolution. 3 channels

11. A/D Converter

• 10-bit resolution. 12 channels

• Casting time for serial/parallel conversion: 1.48 µs

• Conversion mode (single conversion mode, continuous conversion mode)

• Activation source (software, external trigger, peripheral interrupt)

12. Other Interval Timer/Counter

• 8/16-bit up/down counter

• 16-bit PPG timer 5 channels

• Watch dog timer

13. I²C Bus Interface (400 Kbps supported)

• 1channel master/slave sending and receiving

• Arbitration and clock synchronization

14. I/O Port

• 3 V I/O ports (16 ports shared for external interrupts support 5 V input.)

• Max 126 ports

15. Other Features

• Internal oscillator circuit as clock source, allowing PLL multiplication to be selected

• Provided with INIT as a reset pin (The CPU operates without oscillation stabilization wait interval when the

INIT pin is reset.)

• others, watch-dog timer reset, software reset enable

• Support for stop and sleep modes for low power consumption, capable of saving power during CPU operation

at 32 kHz.

• Gear function

• Built-in time base timer

• Package: LQFP-176 (lead pitch: 0.50 mm)

• CMOS technology(0.35 µm)

• Power supply voltage: 3.3 V

0.3 V

3

MB91350A Series

■ PIN ASSIGNMENT

(TOP VIEW)

PG5/SCK5

NMI

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

PM1/SO6/BIN0/TRG1

PM0/SI6/AIN0/TRG0

PN5/PPG5

PN4/PPG4

PN3/PPG3

PN2/PPG2

PN1/PPG1

PN0/PPG0

V^CC

X1A

V^SS

X0A

MD2

MD1

MD0

X0

V^CC

VSS

X1

PO7/OC7

PO6/OC6

PO5/OC5

PO4/OC4

PO3/OC3

PO2/OC2

PO1/OC1

PO0/OC0

PP3/TOT3

PP2/TOT2

PP1/TOT1

PP0/TOT0

V^CC

INIT

V^SS

VCC

PC0/DREQ2

PC1/DACK2

PC2/DSTP2/DEOP2

PB0/DREQ0

PB1/DACK0

PB2/DSTP0/DEOP0

PB3/DREQ1

PB4/DACK1

PB5/DSTP1/DEOP1

PB6/IOWR

PB7/IORD

PA0/CS0

PA1/CS1

PA2/CS2

PA3/CS3

V^SS

VSS

AVSS/AVRL

AVRH

AV^CC

AN11

AN10

AN9

VCC

AN8

P80/IN0/RDY

P81/IN1/BGRNT

P82/IN2/BRQ

P83/RD

AN7

AN6

AN5

AN4

P84/WR0

P85/IN3/WR1

P90/SYSCLK

P91

AN3

AN2

AN1

AN0

P92/MCLK

P93

DA2

DA1

P94/AS

DA0

V^SS

DA^VC

VCC

DAVS

(FPT-176P-M02)

4

MB91350A Series

■ PIN DESCRIPTION

Circuit

type

Pin no. Pin name

Description

D16 to D23

1 to 8

External data bus bit 16 to bit 23. Enabled in external bus mode.

Available as a port in external bus 8-bit mode.

C

P20 to P27

D24 to D31

9 to 16

external data bus bit 24 to bit 31. Enabled in external bus mode.

Usable as port at single chip mode.

C

P30 to P37

A00 to A07

19 to 26

Bits 0 to 7 of external address bus. Enabled in external bus mode.

Usable as port at single chip mode.

P40 to P47

A08 to A15

27 to 34

Bits 8 to 15 of external address bus. Enabled in external bus mode.

Usable as port at single chip mode.

P50 to P57

A16 to A20

Bits 16 to 20 of external address bus. Enabled in external bus mode.

37 to 41

C

Available as a port either in single chip mode or with no external address bus in

use.

P60 to P64

A21 to A23

Bits 21 to 23 of external address bus. Enabled in external bus mode.

42 to 44

Available as a port either in single chip mode or with no external address bus in

use.

P65 to P67

47 to 48 DA0, DA1

⎯

G

D/A converter output pin.

49

DA2

D/A converter output pin.

50 to 57 AN0 to AN7

Analog input pin.

AN8 to AN11

TOT0 to TOT3

58 to 61

67 to 70

G

Analog input pin.

Reload timer output port. This function is enabled when timer output is enabled.

D

General purpose input/output port. This function is enabled when the timer out-

put function is disabled.

PP0 to PP3

OC0

Output compare pin.

71

72

General purpose I/O. This function is available as a port when the output com-

pare output is not in use.

PO0

OC1

Output compare pin.

General purpose I/O. This function is available as a port when the output com-

pare output is not in use.

PO1

OC2

Output compare pin.

73

General purpose I/O. This function is available as a port when the output com-

pare output is not in use.

PO2

OC3 to OC7

PO3 to PO7

PPG0

Output compare pin.

74 to 78

81

General purpose I/O. This function is available as a port when the output com-

pare output is not in use.

PPG timer output pin.

General purpose I/O. This function is available as a port when the PPG timer out-

put is not in use.

PN0

(Continued)

5

MB91350A Series

Circuit

Pin no. Pin name

type

Description

PPG1

PPG timer output pin.

82

83

84

85

86

D

General purpose I/O. This function is available as a port when the PPG timer out-

put is not in use.

PN1

PPG2

PN2

PPG timer output pin.

General purpose I/O. This function is available as a port when the PPG timer out-

put is not in use.

PPG3

PN3

PPG timer output pin.

General purpose I/O. This function is available as a port when the PPG timer out-

put is not in use.

PPG4

PN4

PPG timer output pin.

General purpose I/O. This function is available as a port when the PPG timer out-

put is not in use.

PPG5

PN5

PPG timer output pin.

General purpose I/O. This function is available as a port when the PPG timer out-

put is not in use.

Data input for serial I/O6. Since this input is used as required when serial I/O 6 is

in input operation, the port output must remain off unless intentionally turned on.

SI6

8/16-bit up/down counter input. Since this input is used as required when en-

abled, the port output must remain off unless intentionally turned on.

AIN0

TRG0

PM0

87

88

89

D

External trigger input for PPG timer0. Since this input is used as required when

enabled, the port output must remain off unless intentionally turned on.

General purpose I/O. This function is available a port when the serial I/O, 8/16-

bit up/down counter, and PPG timer outputs are not in use.

Data output for serial I/O 6. This function is enabled when the serial I/O6 data out-

put is enabled.

SO6

8/16-bit up/down counter input. Since this input is used as required when en-

abled, the port output must remain off unless intentionally turned on.

BIN0

TRG1

PM1

External trigger input for PPG timer1. Since this input is used as required when

enabled, the port output must remain off unless intentionally turned on.

General purpose I/O. This function is available a port when the serial I/O, 8/16-

bit up/down counter, and PPG timer outputs are not in use.

Clock input/output for serial I/O 6. This function is enabled when serial I/O6 is us-

ing the external shift clock mode, or serial I/O5 clock output function is enabled.

SCK6

ZIN0

TRG2

PM2

8/16-bit up/down counter input. Since this input is used as required when en-

abled, the port output must remain off unless intentionally turned on.

External trigger input for PPG timer2. Since this input is used as required when

enabled, the port output must remain off unless intentionally turned on.

General purpose I/O. This function is available a port when the serial I/O, 8/16-

bit up/down counter, and PPG timer outputs are not in use.

(Continued)

6

MB91350A Series

Circuit

type

Pin no. Pin name

Description

Data input for serial I/O 7. Since this input is used as required when serial I/O 7

SI7

is in input operation, the port output must remain off unless intentionally turned

on.

8/16-bit up/down counter input. Since this input is used as required when en-

abled, the port output must remain off unless intentionally turned on.

AIN1

90

D

External trigger input for PPG timer 3. Since this input is used as required when

enabled, the port output must remain off unless intentionally turned on.

TRG3

PM3

SO7

General purpose I/O. This function is available a port when the serial I/O, 8/16-

bit up/down counter, and PPG timer outputs are not in use.

Data output for serial I/O 7. This function is enabled when the serial I/O 7 data

output is enabled.

8/16-bit up/down counter input. Since this input is used as required when en-

abled, the port output must remain off unless intentionally turned on.

BIN1

91

D

External trigger input for PPG timer 4. Since this input is used as required when

enabled, the port output must remain off unless intentionally turned on.

TRG4

General purpose I/O. This function is available a port when the serial I/O, 8/16-

bit up/down counter, and PPG timer outputs are not in use.

PM4

Clock input/output for serial I/O5. This function is enabled when serial I/O 7 is us-

ing the external shift clock mode, or serial I/O 5 clock output function is enabled.

SCK7

8/16-bit up/down counter input. Since this input is used as required when en-

abled, the port output must remain off unless intentionally turned on.

ZIN1

92

D

External trigger input for PPG timer 5. Since this input is used as required when

enabled, the port output must remain off unless intentionally turned on.

TRG5

General purpose I/O. This function is available a port when the serial I/O, 8/16-

bit up/down counter, and PPG timer outputs are not in use.

PM5

Clock input/output pin for I²C bus. This function is enabled when the I²C system

is enabled for operation in standard mode. The port output must remain off unless

intentionally turned on. (Open drain input)

SDA

94

F

General purpose input/output port. This function is available as a port when the

I²C system is disabled for operation. (Open drain input)

PL0

Clock input/output pin for I²C bus. This function is enabled when the I²C system

is enabled for operation in standard mode. The port output must remain off unless

intentionally turned on. (Open drain input)

SCL

95

F

E

General purpose input/output port. This function is available as a port when the

I²C system is disabled for operation. (Open drain input)

PL1

External interrupt input. Since this input is used as required when the correspond-

ing external interrupt is enabled, the port output must remain off unless intention-

ally turned on.

INT0 to

INT5

98 to 103

PK0 to PK5

General purpose input/output port.

(Continued)

7

MB91350A Series

Circuit

Pin no. Pin name

type

Description

External interrupt input. Since this input is used as required when the correspond-

ing external interrupt is enabled, the port output must remain off unless intention-

ally turned on.

INT6

104

105

E

External clock input pin for freerun timer. Since this input is used as required

when selected as the external clock input for the free running timer, the port out-

put must remain off unless intentionally turned on.

FRCK

PK6

General purpose input/output port.

External interrupt input. Since this input is used as required when the correspond-

ing external interrupt is enabled, the port output must remain off unless intention-

ally turned on.

INT7

External trigger input for A/D converter. Since this input is used as required when

selected as an A/D activation source, the port output must remain off unless in-

tentionally turned on.

ATG

PK7

General purpose input/output port.

External interrupt input. Since this input is used as required when the correspond-

ing external interrupt is enabled, the port output must remain off unless intention-

ally turned on.

INT8 to

INT15

106 to

113

E

D

PJ0 to PJ7

SI0

General purpose input/output port.

UART0 data input. Since this input is used as required when UART0 is in input

operation, the port output must remain off unless intentionally turned on.

116

117

PI0

General purpose input/output port.

UART0 data output. This function is enabled when the UART0 data output is en-

abled.

SO0

General purpose input/output port. This function is enabled when the data output

function of UART0 is disabled.

PI1

SCK0

PI2

UART0 clock input/output pin. This function is enabled either when clock output

enabled or when UART0 inputs the external clock signal.

118

119

120

D

General purpose input/output port. This function is enabled when UART0 is not

using the external clock signal with the UART0 clock output function disabled.

UART1 data input. Since this input is used as required when UART1 is in input

operation, the port output must remain off unless intentionally turned on.

SI1

PI3

General purpose input/output port.

UART1 data outpu. This function is enabled when the UART1 data output is en-

abled.

SO1

General purpose input/output port. This function is enabled when the data output

function of UART1 is disabled.

PI4

SCK1

PI5

UART1 clock input/output pin. This function is enabled either when clock output

enabled or when UART1 inputs the external clock signal.

121

D

General purpose input/output port. This function is enabled when UART1 is not

using the external clock signal with the UART1 clock output function disabled.

(Continued)

8

MB91350A Series

Circuit

type

Pin no. Pin name

Description

UART2 data input. Since this input is used as required when UART2 is in input

operation, the port output must remain off unless intentionally turned on.

SI2

122

D

PH0

General purpose input/output port.

UART2 data outpu. This function is enabled when the UART2 data output is en-

abled.

SO2

123

D

General purpose input/output port. This function is enabled when the data output

function of UART2 is disabled.

PH1

UART2 clock input/output pin. This function is enabled either when the UART2

clock output is enabled or when UART2 inputs the external clock signal.

SCK2

124

D

General purpose input/output port. This function is enabled when UART2 is not

using the external clock signal with the UART2 clock output function disabled.

PH2

UART3 data input. Since this input is used as required when UART3 is in input

operation, the port output must remain off unless intentionally turned on.

SI3

125

PH3

General purpose input/output port.

UART3 data outpu. This function is enabled when the UART3 data output is en-

abled.

SO3

126

General purpose input/output port. This function is enabled when the data output

function of UART3 is disabled.

PH4

UART0 clock input/output pin. This function is enabled either when the UART3

clock output is enabled or when UART3 inputs the external clock signal.

SCK3

127

D

General purpose input/output port. This function is enabled when UART3 is not

using the external clock signal with the UART3 clock output function disabled.

PH5

UART4 data input. Since this input is used as required when UART4 is in input

operation, the port output must remain off unless intentionally turned on.

SI4

128

PG0

General purpose input/output port.

UART4 data output. This function is enabled when the UART4 data output is en-

abled.

SO4

129

General purpose input/output port. This function is enabled when the data output

function of UART4 is disabled.

PG1

UART4 clock input/output pin. This function is enabled either when the UART4

clock output is enabled or when UART4 inputs the external clock signal.

SCK4

130

D

General purpose input/output port. This function is enabled when UART4 is not

using the external clock signal with the UART4 clock output function disabled.

PG2

Data input for serial I/O5. Since this input is used as required when serial I/O5 is

in input operation, the port output must remain off unless intentionally turned on.

SI5

131

PG3

General purpose input/output port.

Data output for serial I/O5. This function is enabled when the serial I/O5 data out-

put is enabled.

SO5

132

General purpose input/output port. This function is enabled when the I/O5 data

output function is disabled.

PG4

(Continued)

9

MB91350A Series

Circuit

Pin no. Pin name

type

Description

Clock innput/output for serial I/O5. This function is enabled when serial I/O5 is

using the external shift clock mode, or serial I/O5 clock output function is en-

abled.

SCK5

PG5

133

D

General purpose input/output port. This function is enabled when serial I/O5 is

not using the external shift clock mode with the serial I/O5 clock output function

disabled.

134

135

137

NMI

X1A

X0A

H

B

NMI (Non Maskable Interrupt) input

Output clock cycle time. Sub clock

Input clock cycle time. Sub clock

2 to 0Mode Pins. The levels applied to these pins set the basic operating mode.

Connect VCC or VSS.

H, J Input circuit configuration:

The production model (masked-ROM model) is type “H”.

The Flash ROM model is type “J”.

138 to

140

MD2 to

MD0

141

143

144

X0

X1

A

I

Input clock cycle time. Main clock

Output clock cycle time. Main clock

External reset input

INIT

External input for DMA transfer requests. Since this input is used as required

when selected as a DMA start source, the port output must remain off unless in-

tentionally turned on.

DREQ2

147

148

C

PC0

General purpose input/output port.

External acknowledge output for DMA transfer requests. This function is enabled

when the transfer request acceptance output for DMA is enabled.

DACK2

General purpose input/output port. This function is enabled when the transfer re-

quest acceptance output for DMA is enabled.

PC1

DEOP2

DSTP2

PC2

Completion output for DMA external transfer. This function is enabled when the

external transfer end output for DMA is enabled.

Stop input for DMA external transfer. This function is enabled when the external

transfer stop input for DMA is enabled.

149

C

General purpose input/output port. This function is enabled when the external

transfer end output and external transfer stop input for DMA are disabled.

External input for DMA transfer requests. Since this input is used as required

when selected as a DMA start source, the port output must remain off unless in-

tentionally turned on.

DREQ0

150

151

C

PB0

General purpose input/output port.

External acknowledge output for DMA transfer requests. This function is enabled

when the transfer request acceptance output for DMA is enabled.

DACK0

General purpose input/output port. This function is enabled when the transfer re-

quest acceptance output for DMA is disabled.

PB1

(Continued)

10

MB91350A Series

Circuit

type

Pin no. Pin name

Description

Completion output for DMA external transfer. This function is enabled when the

external transfer end output for DMA is enabled.

DEOP0

Stop input for DMA external transfer. This function is enabled when the external

transfer stop input for DMA is enabled.

152

DSTP0

PB2

C

General purpose input/output port. This function is enabled when the external

transfer end output and external transfer stop input for DMA are disabled.

External input for DMA transfer requests. Since this input is used as required

when selected as a DMA start source, the port output must remain off unless in-

tentionally turned on.

DREQ1

153

154

C

PB3

General purpose input/output port.

External acknowledge output for DMA transfer requests. This function is enabled

when the transfer request acceptance output for DMA is enabled.

DACK1

General purpose input/output port. This function is enabled when the external

transfer request acceptance output for DMA is disabled.

PB4

DEOP1

DSTP1

PB5

Completion output for DMA external transfer. This function is enabled when the

external transfer end output for DMA is enabled.

Stop input for DMA external transfer. This function is enabled when the external

transfer stop input for DMA is enabled.

155

156

C

General purpose input/output port. This function is enabled when the external

transfer end output and external transfer stop input for DMA are disabled.

Write strobe output for DMA fly-by transfer. This function is enabled when the

DMA fly-by transfer write strobe output is enabled.

IOWR

PB6

General purpose input/output port. This function is enabled when the DMA fly-by

transfer write strobe output is disabled.

Read storobe output for DMA fly-by transfer. This function is enabled when the

DMA fly-by transfer read strobe output is enabled.

IORD

PB7

157

158

159

C

General purpose input/output port. This function is enabled when the DMA fly-by

transfer read strobe output is disabled.

CS0

PA0

Chip select 0 output. Enable at external bus mode

General purpose input/output port. This is enabled at single chip mode.

Chip select 1 output. This function is enabled when the chip select 1 output is en-

abled.

CS1

PA1

CS2

PA2

General purpose input/output port. This function is enabled when the chip select

1 output is disabled.

Chip select 2 output. This function is enabled when the chip select 2 output is en-

abled.

160

C

General purpose input/output port. This function is enabled when the chip select

2 output is disabled.

(Continued)

11

MB91350A Series

Circuit

Pin no. Pin name

type

Description

Chip select 3 output. This function is enabled when the chip select 3 output is en-

abled.

CS3

PA3

RDY

IN0

161

164

C

D

General purpose input/output port. This function is enabled when the chip select

3 output is disabled.

External ready input. The pin has this function when external ready input is en-

abled.

Input capture input pin. Since this input is used as required when selected as an

input capture input, the port output must remain off unless intentionally turned on.

General purpose input/output port. This function is enabled when external ready

signal input is disabled.

P80

Acknowledge output for external bus release. Outputs “L” when the external bus

is released. The pin has this function when output is enabled.

BGRNT

IN1

Input capture input pin. Since this input is used as required when selected as an

input capture input, the port output must remain off unless intentionally turned on.

165

166

D

General purpose input/output port. This function is enabled when external bus re-

lease acknowledge output is disabled.

P81

External bus release request input. Input “1” to request release of the external

bus. The pin has this function when input is enabled.

BRQ

IN2

Input capture input pin. Since this input is used as required when selected as an

input capture input, the port output must remain off unless intentionally turned on.

General purpose input/output port. The pin has this function when the external

bus release request input is disabled.

P82

RD

P83

WR0

P84

External bus read strobe output. It is available in the external bus mode.

General purpose input/output port. This is enabled at single chip mode.

External bus write strobe output. It is available in the external bus mode.

General purpose input/output port. This is enabled at single chip mode.

167

168

D

External bus write strobe output. This function is enabled when WR1 output is en-

abled in external bus mode.

WR1

IN3

Input capture input pin. Since this input is used as required when selected as an

input capture input, the port output must remain off unless intentionally turned on.

169

D

General purpose input/output port. The pin has this function when the external

bus write-enable output is disabled.

P85

System clock output The pin has this function when system clock output is en-

abled. This outputs the same clock as the external bus operating frequency. (Out-

put halts in stop mode.)

SYSCLK

170

171

C

General purpose input/output port. The pin has this function when system clock

output is disabled.

P90

P91

General purpose input/output port.

(Continued)

12

MB91350A Series

(Continued)

Circuit

type

Pin no. Pin name

Description

Memory clock output. This function is enabled when the memory clock output is

enabled. This outputs the same clock as the external bus operating frequency.

(Output halts in sleep/stop mode.)

MCLK

172

C

General purpose input/output port. This function is enabled when the memory

clock output is disabled.

P92

173

174

P93

AS

C

General purpose input/output port.

Address strobe output. This function is enabled when address strobe output is

enabled.

General purpose input/output port. This function is enabled when address load

output is disabled.

P94

• Power supply and GND pins

Pin no.

Pin name

Description

17, 35, 65, 79, 93, 96,

114, 136, 145, 162, 175

V^SS

V^CC

GND pins. Apply equal potential to all of the pins.

18, 36, 66, 80, 97, 115,

142, 146, 163, 176

3.3 V power supply pin. Apply equal potential to all of the pins.

45

46

62

DA^VS

DA^VC

AV^CC

GND pin for D/A converter

Power supply pin for D/A converter

Analog power supply pin for A/D converter

Reference power supply pin for A/D converter

Analog GND pin for A/D converter

63

64

AVRH

AV^SS/AVRL

13

MB91350A Series

■ I/O CIRCUIT TYPE

Type

Circuit type

Remarks

• Oscillation feedback resistance:

approx. 1 MΩ

X1

X0

Clock input

A

Standby control

• Oscillation feedback resistance for

low speed (subclock oscillation):

approx. 7 MΩ

X1A

X0A

Clock input

B

C

D

Standby control

• CMOS level output

• CMOS level input

Pull-up control

Digital output

With standby control

With Pull-up control

Digital output

Digital input

Pull-up resistance = approx. 50 kΩ

(Typ)

Standby control

I^OL= 8 mA

• CMOS level output

• CMOS level hysteresis input

Pull-up control

Digital output

With standby control

With Pull-up control

Digital output

Digital input

Pull-up resistance = approx. 50 kΩ

(Typ)

Standby control

I^OL= 4 mA

(Continued)

14

MB91350A Series

Type

Circuit type

Remarks

• CMOS level output

• CMOS level hysteresis input

Digital output

E

With stand voltage of 5 V

Digital input

I^OL= 4 mA

• Nch open drain output

• CMOS level hysteresis input

Digital output

Digital input

with standby control

F

With stand voltage of 5 V

Standby control

I^OL= 15 mA

• Analog input with switch

G

Analog input

Control

• CMOS level hysteresis input

H

Digital input

• CMOS level hysteresis input

with pull-up resistor

Pull-up resistance = approx. 50 kΩ

(Typ)

I

Digital input

(Continued)

15

MB91350A Series

(Continued)

Type

Circuit type

Remarks

• CMOS level input

• Flash product only

J

Control signal

Mode input

Diffused resistor

16

MB91350A Series

■ HANDLING DEVICES

• Preventing Latchup

Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output

pin or if an above-rating voltage is applied between VCC and VSS. A latchup,if it occurs, significantly increases

the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very

careful not to exceed the maximum rating.

• Treatment of Unused Input Pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-

up or pull-down resistor.

• About power supply pins

In products with multiple V^CCor V^SSpins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to an external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand V^SSpins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between V^CCand V^SSnear

this device.

• About Crystal oscillator circuit

Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the circuit board so that

X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located

as close to the device as possible.

It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by

ground plane because stable operation can be expected with such a layout.

• Notes on Using External Clock

When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to

X0 must be supplied to X1 pin. However, in this case the stop mode(oscillator stop mode) must not be used.

(This is because the X1 pin stops at High level output in STOP mode.)

Using an external clock (normal)

X0

X1

Note: STOP mode (oscillation stop mode) cannot be used.

• Clock control block

Take the oscillation stabilization wait time during Low level input to the INIT pin.

17

MB91350A Series

• Notes on not using the sub clock

When no oscillator is connected to the X0A and X1A pins, pull down the X0A pin and open the X1A pin.

X0

OPEN

X1

MB91350A

• Treatment of NC and OPEN pins

Pins marked as NC and OPEN must be left open-circuit.

• Mode pins (MD0 to MD2)

These pins should be connected directly to V^CCor V^SS.

To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that

the distance between the mode pins and V^CCor V^SSis as short as possible and the connection impedance is low.

• Operation at start-up

The INIT pin must be at Low level when the power supply is turned on.

Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling time

required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INIT

via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)

• About oscillation input at power on

When turning the power on, maintain clock input until the device is released from the oscillation stabilization

wait state.

• Caution on Operations during PLL Clock Mode

Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the

microcontroller may continue to operate at the free-running frequency of the PLL’s internal self-oscillating oscil-

lator circuit. Performance of this operation, however, cannot be guaranteed.

• External bus setting

This model guarantees an external bus frequency of 25 MHz.

Setting the base clock frequency to 50 MHz with DIVR1 (external bus base clock division setting register)

initialized sets the external bus frequency also to 50 MHz. Before changing the base clock frequency, set the

external bus frequency not exceeding 25 MHz.

• MCLK and SYSCLK

MCLK and SYSCLK has a difference that MCLK stops in SLEEP/STOP mode but SYSCLK stops only in STOP

mode. Use either depending on each application.

Upon initialization, MCLK becomes invalid (PORT) and SYSCLK becomes valid. To use MCLK, set the port

function register (PFR) to select the use of that clock.

• Pull-up control

Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the “■ ELECTRICAL

CHARACTERISTICS 4. AC Characteristics (4) Normal Bus Access Read/Write Operation, (5) Multiplex Bus

Access Read/Write operation and (7) Hold Timing”.

Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby

mode.

18

MB91350A Series

• Sub clock select

Immediately after switching from main clock mode to subclock mode for the clock source, insert at least one

NOP instruction.

(ldi

stb

nop

#0x0b, r0)

#_CLKR, r12)

r0, @r12

// sub-clock mode

// Must insert NOP instruction

• Bit Search Module

The BSD0, BSD1, and BDSC registers are accessed only in words.

• D-bus memory

Do not allocate the code area in memory on the D-bus because no instruction fetch takes place to the D-bus.

Executing an instruction fetch to the D-bus area causes wrong data to be interpreted as code, possibly letting

the device to run out of control.

• Low Power Consumption Mode

To enter the sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing to it.

Precisely, use the following sequence.

Set the I flag, ILM, and ICR to, after returning from standby mode, branch to the interrupt handler having caused

the device to return.

(ldi

#value_of_standby, r0)

(ldi

#_STCR, r12)

stb

r0, @r12

@r12, r0

// set STOP/SLEEP bit

ldub

// Must read STCR

// after reading, go into standby

mode

ldub

@r12, r0

nop

// Must insert NOP *5

• Switch shared port function

To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR). Note,

however, that bus pins are switched depending on external bus settings.

• Pre-fetch

When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only.

Byte or halfword access results in wrong data read.

• I/O port access

Ports are accessed only in bytes.

• Built-in RAM

Immediately after a reset is canceled, the internal RAM allocation restricting function is still working, allowing

only 4 KB to be used for data and for program execution irrespective of the on-chip RAM capacity.

19

MB91350A Series

• Flash memory

In programming mode, Flash memory cannot be used as an interrupt vector table. A reset is possible.

• Notes on the PS register

As the PS register is processed by some instructions in advance, exception handling below may cause the

interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register

to be updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it

performs operations before and after the EIT as specified in either case.

1. The following operations are performed when the instruction followed by a DIVOU/DIVOS instruction results in:

(a) acceptance of a user interrupt or NMI, (b) single-stepping, or (c) a break at a data event or emulator menu.

• The D0 and D1 flags are updated in advance.

• An EIT handling routine (user interrupt, NMI, or emulator) is executed.

• Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are

updated to the same values as in (1).

2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed.

• The PS register is updated in advance.

• An EIT handling routine (user interrupt, NMI, or emulator) is executed.

• Upon returning from the EIT, the above instructions are executed and the PS register is updated to the

same value as in (1).

20

MB91350A Series

[Note on debugger]

• Step execution of RETI command

If an interrupt occurs frequently during single-stepping, the corresponding interrupt handling routine is executed

repeatedly. This will prevent the main routine and low-interrupt-level programs from being executed. (Whenever

RETI is single-stepped when interrupts by the timebase timer have been enabled, for example, the timebase

timer routine causes a break at the beginning.)

Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debug-

ging.

• Break function

If the address at which to cause a hardware break (including a event break) is set to the address currently

contained in the system stack pointer or in the area containing the stack pointer, the user program causes a

break after execution of one instruction.

To prevent this, do not set (word) access to the area containing the address in the system stack pointer as the

target of a hardware break (including an event break).

• Internal ROM area

Do not set an area of internal ROM as a DMAC transfer destination.

• Simultaneous occurrences of a software break (INTE instruction) and a user interrupt/NMI

When an INTE instruction and a user interrupt/NMI are accepted simultaneously, the emulator debugger reacts

as follows.

The emulator debugger stops while indicating a location in the user program, which is not a user-specified

breakpoint. (It stops with the beginning of the user interrupt/NMI handling routine indicated.)

The user program cannot be re-executed correctly.

To prevent this problem, follow the instructions below.

When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as

follows.

• The debugger stops pointing to a location other than the programmed breakpoints.

• The halted program is not re-executed correctly.

If this symptom occurs, use a hardware break in place of a hardware break. When using a monitor debugger,

do not set a break at the relevant location.

• A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data

event break to access to the area containing the address of a system stack pointer.

21

MB91350A Series

■ BLOCK DIAGRAM

FR CPU

DREQ0 to DREQ2

DACK0 to DACK2

DEOP0/DSTP0 to DEOP2/DSTP2

IOWR

32

DMAC 5 channels

Bit search

RAM (Stack)

ROM/Flash

IORD

A23 to A00

D31 to D16

Bus

Converter

RD

32

RAM (Executable)

32

WR1, WR0

External

memory

I/F

RDY

32 ↔ 16

Adapter

X0, X1

MD0 to MD2

INIT

BRQ

BGRNT

SYSCLK

Clock

control

X0A, X1A

Clock timer

16

PORT

PORT I/F

Interrupt

DMAC (DMA

Controller)

6 channels

PPG

TRG0 to TRG5

PPG0 to PPG5

16 channels

External interrupt

INT0 to INT15

NMI

4 channels

reload timer

TOT0 to TOT3

FRCK

SI0 to SI4

SO0 to SO4

5 channels

UART

SCK0 to SCK4

16-bit free-run

timer

5 channels

U-Timer

4 channels

input capture

IN0 to IN3

SI5 to SI7

SO5 to SO7

SCK5 to SCK7

3 channels

SIO

8 channels

output compare

OC0 to OC7

AN0 to AN11

ATG

AVRH, AVCC

AVSS/AVRL

12 channels

A/D

SDA

SCL

1 channel

I²C

DA0 to DA2

DAVC, DAVS

3 channels

D/A

2 channels

8/16-bit up/down

counter

AIN0, AIN1

BIN0, BIN1

ZIN0, ZIN1

MB91F355A

MB91F356B

MB91355A

512 KB

16 KB

MB91354A

384 KB

16 KB

ROM/Flash

512 KB (Flash) 256 KB (Flash)

RAM (Stack)

16 KB

8 KB

16 KB

8 KB

RAM (Executable)

8 KB

22

MB91350A Series

■ CPU AND CONTROL UNIT

Internal architecture

The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced

instructions for embedded controller applications.

1. Features

• RISC architecture employed. Basic instructions: Executed at 1 instruction per cycle

• General-purpose registers: 32-bit × 16 registers

• 4GB linear memory space

• Multiplier integrated.

32-bit x 32-bit multiplication: 5 cycles.

16-bit x 16-bit multiplication: 3 cycles

• Enhanced interrupt servicing.

Fast response speed (6 cycles).

Multiple interrupts supported.

Level masking (16 levels)

• Enhanced I/O manipulation instructions.

Memory-to-memory transfer instructions, Bit manipulation instructions

• High code efficiency. Basic instruction word length: 16-bit

• Low-power consumption. Sleep mode and stop mode

• Gear function

23

MB91350A Series

2. Internal architecture

The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated.

The 32-bit/16-bit bus converter is connected to a 32-bit bus (F-bus), providing an interface between the CPU

and peripheral resources. The Harvard-Princeton bus converter is connected to both of the I-bus and D-bus,

providing an interface between the CPU and the bus controller.

FR CPU

D-bus

I-bus

32

I address

External address

24

Harvard

32

I data

External data

16

D address

D data

32

Princeton

bus

converter

Data

RAM

Address

32

32-bit

Data

16-bit

bus converter

16

R-bus

F-bus

Peripherals resource

Internal I/O

bus controller

24

MB91350A Series

3. Programming model

• Basic programming model

32-bit

Initial Value:

XXXX XXXXH

R0

R1

GENERAL

PURPOSE

REGISTERS

R12

R13

R14

R15

AC

FP

SP

XXXX XXXXH

0000 0000H

Program counter

program status

PC

PS

⎯

ILM

⎯

SCR CCR

Table base register

TBR

Return pointer

RP

System stack pointer

SSP

User stack pointer

USP

Multiplication and division

result register

MDH

MDL

25

MB91350A Series

4. Register

General purpose registers

32-bit

Initial Value:

XXXX XXXXH

R0

R1

R12

R13

R14

R15

AC

FP

SP

XXXX XXXXH

0000 0000H

Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory

access pointers for CPU operations.

Of these 16 registers, the registers listed below are intended for special applications, for which some instructions

are enhanced.

R13 : Virtual accumulator

R14 : frame pointer

R15 : Stack pointer

The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 0000 0000^H(SSP value).

• PS (Program Status)

This register holds the program status and is divided into the ILM, SCR, and CCR.

The undefined bits in the following illustration are all reserved bits. Reading these bits always returns “0”. Writing

to them has no effect.

31

20

16

10

0

Bit position→

8 7

⎯

ILM

SCR

CCR

PS

26

MB91350A Series

• CCR (Condition Code Register )

Initial Value:

- - 00XXXX^B

7

6

5

4

I

3

2

Z

1

0

⎯

S

N

V

C

CCR

S

I

: Stack flag. Cleared to “0” by a reset.

: Interrupt enable flag. Cleared to “0” by a reset.

N

Z

V

C

: Negative flag. The initial value after a reset is indeterminate.

: Zero flag. The initial value after a reset is indeterminate.

: Overflow flag. The initial value after a reset is indeterminate.

: Carry flag. The initial value after a reset is indeterminate.

• SCR (System Condition code Register )

10

9

8

T

Initial Value:

XX0^B

D1 D0

SCR

Flag for step dividing

Stores intermediate data for stepwise multiplication operations.

Step trace trap flag

A flag specifying whether the step trace trap function is enabled or not.

Emulator use step trace trap function. The function cannot be used by the user program when using

the emulator.

• ILM

20

19

18

17

16

Initial Value:

01111^B

ILM4 ILM3 ILM2 ILM1 ILM0

ILM

This register stores the interrupt level mask value. The value in the ILM register is used as the level mask.

Initialized to “15” (01111^B) by a reset.

• PC (Program Counter)

31

0

Initial Value:

XXXXXXXX^H

PC

The program counter contains the address of the instruction currently being executed.

The initial value after a reset is indeterminate.

27

MB91350A Series

• TBR (Table Base Register)

31

0

Initial Value:

000FFC00^H

TBR

The table base register contains the start address of the vector table used for servicing EIT events.

The initial value after a reset is 000FFC00^H

• RP (Return Pointer)

31

0

Initial Value:

XXXXXXXX^H

RP

The return pointer contains the address to which to return from a subroutine.

When the CALL instruction is executed, the value in the PC is transferred to the RP.

When the RET instruction is executed, the value in the RP is transferred to the PC.

The initial value after a reset is indeterminate.

• SSP (System Stack Pointer)

31

0

Initial Value:

00000000^H

SSP

The SSP is the system stack pointer and functions as R15 when the S flag is “0”.

The SSP can be explicitly specified.

The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event

occurs.

The initial value after a reset is 00000000^H

• USP (User Stack Pointer)

31

0

Initial Value:

XXXXXXXX^H

USP

The USP is the user stack pointer and functions as R15 when the S flag is “1”.

The SSP can be explicitly specified.

The initial value after a reset is indeterminate.

This pointer cannot be used by the RETI instruction.

28

MB91350A Series

• Multiply & Divide registers

31

0

MDH

MDL

Multiplication and division result register

These registers hold the results of a multiplication or division. Each of them is 32-bit long.

The initial value after a reset is indeterminate.

29

MB91350A Series

■ MODE SETTINGS

The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.

1. Mode Pins

The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.

Mode Pins

Reset vector

access area

Mode name

Remarks

MD2 MD1 MD0

0

1

Internal ROM mode vector

External ROM mode vector

Internal

External

The bus width is specified by the mode register.

Values other than those listed in the table are prohibited.

2. Mode Register (MODR)

The data written to the mode register at 000F FFF8^Husing mode vector fetch is called mode data.

After an operation mode has been set in the mode register (MODR), the device operates in the operation mode.

The mode register is set by any reset source. User programs cannot write data to the mode register.

Note : Conventionally the FR family has nothing at addresses (0000 07FF^H) in the mode register.

MODR

Initial Value

7

0

6

0

5

0

4

0

3

0

2

1

0

000F FFF8^H

XXXXXXXX^B

ROMA WTH1 WTH0

Operation mode setting bits

[bit 7 to bit 3] Reserved bit

Be sure to set this bit to “00000”. Operation is not guaranteed when any value other than “00000” is set.

[bit 2] ROMA (internal ROM enable bit)

The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.

ROMA

function

Remarks

Internal F-bus RAM is valid; the area (80000^Hto 100000^H) of internal ROM is used

as an external area.

0

1

External ROM mode

Internal ROM mode Internal F-bus RAM and F-bus ROM become valid.

30

MB91350A Series

[bit 1, bit 0] WTH1, WTH0 (Bus width setting bits)

Used to set the bus width to be used in external bus mode.

When the operation mode is the external bus mode, this value is set in bits BW1 and BW0 in AMD0 (CS0 area).

WTH1

WTH0

function

8-bit bus width

16-bit bus width

⎯

Remarks

0

1

0

1

0

1

External bus mode

Setting disabled

single chip mode

31

MB91350A Series

■ MEMORY SPACE

1. Memory space

The FR family has 4 GB of logical address space (2³²addresses) available to the CPU by linear access.

• Direct Addressing Areas

The following address space areas are used as I/O areas.

These areas are called direct addressing areas, in which the address of an operand can be specified directly

during an instruction.

The size of directly addressable areas depends on the length of the data being accessed as shown below.

→ byte data access

→ half word data access : 000^Hto 1FF^H

→ word data access : 000^Hto 3FF^H

: 000^Hto 0FF^H

2. Memory Map

• Memory map of MB91F355A/MB91355A

Single chip mode

Internal ROM

External ROM

external bus mode

0000 0000H

Direct

addressing area

I/O

0000 0400H

Refer to “3. I/O Map”

I/O

0001 0000H

Access

disallowed

0003 E000H

Built-in RAM 8 KB

(Executable)

Built-in RAM 8 KB

(Executable)

Built-in RAM 8 KB

(Executable)

0004 0000H

Built-in RAM 16 KB

(Stack)

Built-in RAM 16 KB

(Stack)

0004 4000H

Access

disallowed

Access

disallowed

0005 0000H

External area

0008 0000H

Built-in RAM

512 KB

Built-in RAM

512 KB

External area

0010 0000H

Access

disallowed

External area

FFFF FFFFH

• Each mode is set depending on the mode vector fetch after INIT is negated.

• The MB91V350A uses the area of 512 KB of internal ROM as emulation RAM in the MB91355A memory map.

The internal RAM (Instruction) has been expanded from 8 KB to 16 KB.

• The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the

available area is updated, the instruction must be followed by at least 1 NOP instruction.

32

MB91350A Series

• Memory Map of MB91354A

Internal ROM

external bus mode

External ROM

external bus mode

Single chip mode

0000 0000H

0000 0400H

Direct

addressing area

I/O

Refer to “3. I/O Map”

0001 0000H

0003 E000H

Access

disallowed

Access

disallowed

Access

disallowed

Built-in RAM 8 KB

(Executable)

Built-in RAM 8 KB

(Executable)

Built-in RAM 8 KB

(Executable)

0004 0000H

0004 2000H

Built-in RAM 8 KB

(Stack)

Built-in RAM 8 KB

(Stack)

Built-in RAM 8 KB

(Stack)

Access

disallowed

Access

disallowed

0005 0000H

0008 0000H

000A 0000H

External area

Access

disallowed

External area

Built-in ROM

384 KB

Built-in ROM

384 KB

0010 0000H

FFFF FFFFH

Access

disallowed

External area

• Each mode is set depending on the mode vector fetch after INIT is negated.

• The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the

available area is updated, the instruction must be followed by at least 1 NOP instruction.

33

MB91350A Series

• Memory Map of MB91356B

Internal ROM

external bus mode

External ROM

external bus mode

Single chip mode

0000 0000H

Direct

addressing area

I/O

0000 0400H

Refer to “3. I/O Map”

I/O

0001 0000H

Access

disallowed

Access

disallowed

0003 E000H

Built-in RAM 8 KB

(Executable)

Built-in RAM 8 KB

(Executable)

Built-in RAM 8 KB

(Executable)

0004 0000H

Built-in RAM 16 KB

(Stack)

Built-in RAM 16 KB

(Stack)

0004 4000H

Access

disallowed

Access

disallowed

0005 0000H

External area

0008 0000H

Access

disallowed

000C 0000H

External area

Built-in ROM

256 KB

0010 0000H

Access

disallowed

External area

FFFF FFFFH

• Each mode is set depending on the mode vector fetch after INIT is negated.

• The available area of internal RAM is restricted immediately after a reset is canceled. When the setting of the

available area is updated, the instruction must be followed by at least 1 NOP instruction.

34

MB91350A Series

3. I/O Map

This shows the location of the various peripheral resource registers in the memory space.

(How to read the table)

Register

Address

Block diagram

+ 0

PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

+ 1

+ 2

+ 3

T-unit

Port Data Register

000000^H

Read/write attribute, Access unit

(B : Byte, H : Half Word, W : Word)

Initial value after a reset

Register name (First-column register at address 4n, second-column register at

address 4n + 2)

Location of left-most register (When using word access, the register in column

1 is in the MSB side of the data.)

Note : Initial values of register bits are represented as follows :

“1” : Initial value is “1”.

“0” : Initial Value: “0”.

“X” : Initial value is “X”.

“−” : No physical register at this location

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

PDR2 [R/W] B

XXXXXXXX

PDR3 [R/W] B

XXXXXXXX

000000^H

000004^H

000008^H

00000C^H

000010^H

000014^H

000018H

⎯

PDR4 [R/W] B

XXXXXXXX

PDR5 [R/W] B

XXXXXXXX

PDR6 [R/W] B

XXXXXXXX

⎯

T-unit

Port Data

Register

PDR8 [R/W] B

- - XXXXXX

PDR9 [R/W] B

- - - XXXXX

PDRA [R/W] B

- - - - XXXX

PDRB [R/W] B

XXXXXXXX

PDRC [R/W] B

- - - - - XXX

⎯

PDRG[R/W] B

- - XXXXXX

PDRH [R/W] B

- - XXXXXX

PDRI [R/W] B

- - XXXXXX

PDRJ [R/W] B

XXXXXXXX

PDRK [R/W] B

XXXXXXXX

PDRL [R/W] B

- - - - - - XX

PDRM [R/W] B

- - XXXXXX

PDRN [R/W] B

- - XXXXXX

R-bus

Port Data

Register

PDRO [R/W] B

XXXXXXXX

PDRP [R/W] B

- - - - XXXX

⎯

00001C^H

000020^H

⎯

Reserved

SIO 5*³

SMCS5 [R/W] B, H*³

00000010 - - - - 00 - -

SES5 [R/W] B*³

- - - - - - 00

SDR5 [R/W] B*³

XXXXXXXX

000024^H

(Continued)

35

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

SMCS6 [R/W] B, H

000028^H

SES6 [R/W] B

- - - - - - 00

SDR6 [R/W] B

XXXXXXXX

SIO 6

SIO 7

00000010 - - - - 00 - -

SMCS7 [R/W] B, H

SES7 [R/W] B

- - - - - - 00

SDR7 [R/W] B

XXXXXXXX

00002C^H

000030^H

000034^H

00000010 - - - - 00 - -

CDCR5 [R/W] B

0---1111

SIO Prescaler

5

⎯

⎯*¹

CDCR6 [R/W] B

0 - - - 1111

CDCR7 [R/W] B

0 - - - 1111

SIO Prescaler

6, 7

⎯*¹

SRCL5 [W] B

- - - - - - - -

SRCL6 [W] B

- - - - - - - -

SRCL7 [W] B

- - - - - - - -

000038^H

00003C^H

000040^H

⎯

SIO5 to SIO7

Reserved

⎯

EIRR0 [R/W] B, H, W ENIR0 [R/W] B, H, W

00000000 00000000

DICR [R/W] B, H, W HRCL [R/W] B, H, W

ELVR0 [R/W] B, H, W

Ext int

(INT0 to INT7)

00000000

000044^H

000048^H

00004C^H

000050^H

000054^H

000058^H

00005C^H

⎯

DLYI/I-unit

- - - - - - - 0

0 - - 11111

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

Reload Timer 0

TMCSR [R/W] B, H, W

- - - - 0000 00000000

⎯

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

Reload Timer 1

TMCSR [R/W] B, H, W

- - - - 0000 00000000

⎯

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

Reload Timer 2

UART0

TMCSR [R/W] B, H, W

- - - - 0000 00000000

⎯

SIDR/SODR [R/W]

SSR [R/W] B, H, W

00001000

SCR [R/W] B, H, W SMR [R/W] B, H, W

000060^H

000064^H

000068^H

00006C^H

000070^H

000074^H

B, H, W

XXXXXXXX

00000100

00 - - 0 - - -

UTIM [R] H (UTIMR [W] H)

00000000 00000000

DRCL [W] B

- - - - - - - -

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 0

SIDR/SODR [R/W]

SSR [R/W] B, H, W

00001000

SCR [R/W] B, H, W SMR [R/W] B, H, W

B, H, W

XXXXXXXX

UART1

00000100

00 - - 0 - - -

UTIM [R] H (UTIMR [W] H)

00000000 00000000

DRCL [W] B

- - - - - - - -

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 1

SIDR/SODR [R/W]

SSR [R/W] B, H, W

00001000

SCR [R/W] B, H, W SMR [R/W] B, H, W

B, H, W

XXXXXXXX

UART2

00000100

00 - - 0 - - -

UTIM [R] H (UTIMR [W] H)

00000000 00000000

DRCL [W] B

- - - - - - - -

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 2

(Continued)

36

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

ADCS2 [R/W]B, H, W ADCS1 [R/W]B, H, W

ADCT [R/W] H, W

XXXXXXXX_XXXXXXXX

000078^H

00007C^H

000080^H

000084^H

000088^H

X000XX00

000X0000

A/D

converter:

Successive

approxima-

tion

ADTH0 [R] B, H, W

XXXXXXXX

ADTL0 [R] B, H, W

000000XX

ADTH1 [R] B, H, W

ADTL1 [R] B, H, W

000000XX

XXXXXXXX

ADTH2 [R] B, H, W

XXXXXXXX

ADTL2 [R] B, H, W

000000XX

ADTH3 [R] B, H, W

XXXXXXXX

ADTL3 [R] B, H, W

000000XX

DACR2 [R/W] B, H, W DACR1 [R/W] B, H, W DACR0 [R/W] B, H, W

- - - - - - - 0 - - - - - - - 0 - - - - - - - 0

⎯

D/A

Converter

DADR2 [R/W] B, H, W DADR1 [R/W] B, H, W DADR0 [R/W] B, H, W

XXXXXXXX

00008C^H

000090^H

⎯

⎯*¹

Reserved

IBCR [R/W] B, H, W

00000000

IBSR [R] B, H, W

00000000

ITBA [R/W] B, H, W

- - - - - - 00 00000000

000094^H

000098^H

00009C^H

ITMK [R/W] B, H, W

00 - - - - 11 11111111

ISMK [R/W] B, H, W ISBA [R/W] B, H, W

I²C

interface

01111111

- 0000000

IDAR [R/W] B, H, W ICCR [R/W] B, H, W IDBL [R/W] B, H, W

⎯

00000000

⎯*¹

0 - 011111

- - - - - - - 0

⎯*¹

0000A0^H

0000A4^H

⎯

Reserved

⎯*¹

TMRLR [W] H, W

XXXXXXXX XXXXXXXX

TMR [R] H, W

XXXXXXXX XXXXXXXX

0000A8^H

0000AC^H

0000B0^H

0000B4^H

Reload

Timer 3

TMCSR [R/W] B, H, W

- - - - 0000 00000000

⎯

RCR1 [W] B, H, W

00000000

RCR0 [W] B, H, W

00000000

UDCR1 [R] B, H, W UDCR0 [R] B, H, W

00000000

8/16-bit

CCRH0 [R/W] B, H, W CCRL0 [R/W] B, H, W

00001000 00001000

CSR0 [R/W] B, H, W Up/Down

⎯

00000000

Counter

0, 1

CCRH1 [R/W] B, H, W CCRL1 [R/W] B, H, W

CSR1 [R/W] B, H, W

00000000

0000B8^H

0000BC^H

⎯

00001000

⎯

Reserved

UART3

SIDR/SODR [R/W]

B, H, W

SSR [R/W] B, H, W

00001000

SCR [R/W] B, H, W SMR [R/W] B, H, W

0000C0^H

0000C4^H

0000C8^H

00000100

00 - - 0 - - -

XXXXXXXX

UTIM [R] H (UTIMR [W] H)

00000000 00000000

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 3

⎯

SIDR/SODR [R/W]

SSR [R/W] B, H, W

00001000

SCR [R/W] B, H, W SMR [R/W] B, H, W

00000100 00 - - 0 - - -

B, H, W

XXXXXXXX

UART4

(Continued)

37

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

UTIM [R] H (UTIMR [W] H)

00000000 00000000

UTIMC [R/W] B

0 - - 00001

U-Timer/

UART 4

0000CC^H

0000D0^H

⎯

EIRR1 [R/W] B, H, W ENIR1 [R/W]B, H, W

00000000 00000000

ELVR1 [R/W] B, H, W

00000000

Ext int

(INT8-15)

16-bit

Free run

Timer

TCDT [R/W] H, W

00000000 00000000

TCCS [R/W] B, H, W

00000000

0000D4^H

⎯

IPCP1 [R] H, W

XXXXXXXX XXXXXXXX

IPCP0 [R] H, W

XXXXXXXX XXXXXXXX

0000D8^H

0000DC^H

0000E0^H

0000E4^H

0000E8^H

0000EC^H

0000F0^H

0000F4^H

IPCP3 [R] H, W

XXXXXXXX XXXXXXXX

IPCP2 [R] H, W

XXXXXXXX XXXXXXXX

16-bit ICU

ICS23 [R/W] B, H, W

00000000

ICS01 [R/W] B, H, W

00000000

⎯

OCCP1 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP0 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP3 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP2 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP5 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP4 [R/W] H, W

XXXXXXXX XXXXXXXX

16-bit

OCU

*3

OCCP7 [R/W] H, W

XXXXXXXX XXXXXXXX

OCCP6 [R/W] H, W

XXXXXXXX XXXXXXXX

OCS23 [R/W] B, H, W

1110110 00001100

OCS01 [R/W] B, H, W

1110110 00001100

OCS67 [R/W] B, H, W

1110110 00001100

OCS45 [R/W] B, H, W

1110110 00001100

0000F8^H

0000FC^H

⎯

Reserved

000100^H

to

000114^H

⎯

GCN10 [R/W] H

00110010_00010000

GCN20 [R/W] B

00000000

PPG

Control 0

000118^H

00011C^H

000120^H

⎯

Reserved

PTMR0 [R] H, W

11111111_11111111

PCSR0 [W] H, W

XXXXXXXX_XXXXXXXX

PPG0

PDUT0 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH0 [R/W] B, H, W PCNL0 [R/W] B, H, W

000124^H

000128^H

00012C^H

00000000

PTMR1 [R] H, W

11111111_11111111

PCSR1 [W] H, W

XXXXXXXX_XXXXXXXX

PPG1

PDUT1 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH1 [R/W] B, H, W PCNL1 [R/W] B, H, W

00000000

(Continued)

38

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

PTMR2 [R] H, W

11111111_11111111

PCSR2 [W] H, W

XXXXXXXX_XXXXXXXX

000130^H

000134^H

000138^H

00013C^H

000140^H

000144^H

000148^H

00014C^H

PPG2

PPG3

PPG4

PDUT2 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH2 [R/W] B, H, W PCNL2 [R/W] B, H, W

00000000 00000000

PTMR3 [R] H, W

11111111_11111111

PCSR3 [W] H, W

XXXXXXXX_XXXXXXXX

PDUT3 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH3 [R/W] B, H, W PCNL3[R/W] B, H, W

00000000

PTMR4 [R] H, W

11111111_11111111

PCSR4 [W] H, W

XXXXXXXX_XXXXXXXX

PDUT4 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH4 [R/W] B, H, W PCNL4 [R/W] B, H, W

00000000

PTMR5 [R] H, W

11111111_11111111

PCSR5 [W] H, W

XXXXXXXX_XXXXXXXX

PPG5

PDUT5 [W] H, W

XXXXXXXX_XXXXXXXX

PCNH5 [R/W] B, H, W PCNL5 [R/W] B, H, W

00000000

000150^H

to

0001FC^H

⎯

Reserved

DMACA0 [R/W] B, H, W*²

00000000 0000XXXX XXXXXXXX XXXXXXXX

000200^H

000204^H

000208^H

00020C^H

000210^H

000214^H

000218^H

00021C^H

000220^H

DMACB0 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMACA1 [R/W] B, H, W*²

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB1 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMACA2 [R/W] B, H, W*²

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB2 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMAC

DMACA3 [R/W] B, H, W*²

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB3 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

DMACA4 [R/W] B, H, W*²

00000000 0000XXXX XXXXXXXX XXXXXXXX

DMACB4 [R/W] B, H, W

00000000 00000000 XXXXXXXX XXXXXXXX

000224^H

000228^H

⎯

(Continued)

39

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

00022C^H

to

00023C^H

⎯

Reserved

DMAC

DMACR [R/W] B

0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

000240^H

000244^H

to

00027C^H

⎯

Reserved

FRLR [R/W] B, H, W

- - - - - - 01*³

F-bus RAM

capacity limit

000280^H

⎯

000284^H

to

00038C^H

⎯

Reserved

DRLR [R/W] B, H, W

- - - - - - 01*³

D-bus RAM

capacity limit

000390^H

000394^H

to

0003EC^H

⎯

Reserved

BSD0 [W]

0003F0^H

0003F4^H

0003F8^H

0003FC^H

000400^H

000404^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSD1 [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search

Module

BSDC [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

BSRR [R]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

DDRG[R/W] B

- - 000000

DDRH [R/W] B

- - 000000

DDRI [R/W] B

- - 000000

DDRJ [R/W] B

00000000

R-bus

Data

Direction

Register

DDRK [R/W] B

00000000

DDRL [R/W] B

- - - - - - 00

DDRM [R/W] B

- - 000000

DDRN [R/W] B

- - 000000

DDRO [R/W] B

00000000

DDRP [R/W] B

- - - - 0000

000408^H

00040C^H

000410^H

⎯

PFRG [R/W] B

- - 00 - 00 -

PFRH [R/W] B

- - 00 - 00 -

PFRI [R/W] B

- - 00 - 00 -

⎯

R-bus

PortFunction

Register

PFRL [R/W] B

- - - - - - 00

PFRM [R/W] B

- - 00 - 00 -

PFRN [R/W] B

- - 000000

000414^H

________

PFRO [R/W] B

00000000

PFRP [R/W] B

- - - - 0000

000418^H

00041C^H

Reserved

(Continued)

40

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

PCRG [R/W] B

- - 000000

PCRH [R/W] B

- - 000000

PCRI [R/W] B

- - 000000

000420^H

000424^H

000428^H

⎯

R-bus

PCRM [R/W] B

- - 000000

PCRN [R/W] B

- - 000000

Pull-up

Control

Register

⎯

PCRO [R/W] B

00000000

PCRP [R/W] B

- - - - 0000

⎯

00042C^H

to

00043C^H

⎯

Reserved

ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W

000440^H

000444^H

000448^H

00044C^H

000450^H

000454^H

000458^H

00045C^H

000460^H

000464^H

000468^H

00046C^H

- - - 11111

ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W

- - - 11111 - - - 11111 - - - 11111 - - - 11111

- - - 11111

Interrupt

Control unit

000470^H

to

00047C^H

⎯

RSRR [R/W] B, H, W STCR [R/W] B, H, W TBCR [R/W] B, H, W CTBR [W] B, H, W

000480^H

000484^H

000488^H

10000000

00110011

00XXXX00

XXXXXXXX

CLKR [R/W] B, H, W WPR [W] B, H, W DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W

Clock

Control unit

00000000

XXXXXXXX

00000011

00000000

OSCCR [R/W] B

XXXXXXX0

⎯

(Continued)

41

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

WPCR [R/W] B

00048C^H

⎯

Clock timer

00 - - - 000

Main oscillation

stabilization

timer

OSCR [R/W] B

000490^H

⎯

000 - - XX0

RSTOP0 [W] B

00000000

RSTOP1 [W] B

00000000

RSTOP2 [W] B

00000000

RSTOP3 [W] B

- - - - - 000

Peripheralstop

control

000494^H

000498^H

⎯

Reserved

00049C^H

to

0005FC^H

⎯

Reserved

DDR2 [R/W] B

00000000

DDR3 [R/W] B

00000000

000600^H

000604^H

000608^H

⎯

DDR4 [R/W] B

00000000

DDR5 [R/W] B

00000000

DDR6 [R/W] B

00000000

⎯

T-unit

Data Direction

Register

DDR8 [R/W] B

- - 000000

DDR9 [R/W] B

- - - 00000

DDRA [R/W] B

- - - - 0000

DDRB [R/W] B

00000000

DDRC [R/W] B

- - - - - 000

00060C^H

000610^H

000614^H

⎯

PFR6 [R/W] B

11111111

T-unit

Port Function

Register

PFR8 [R/W] B

- - 1 - - 0 - -

PFR9 [R/W] B

- - - 010 - 1

PFRA [R/W] B

- - - - 1111

PFRB1 [R/W] B

00000000

000618^H

00061C^H

000620^H

000624^H

000628^H

00062CH

PFRB2 [R/W] B

00 - - - - 00

PFRC [R/W] B

- - - 00000

⎯

PCR2 [R/W] B

00000000

PCR3 [R/W] B

00000000

⎯

PCR4 [R/W] B

00000000

PCR5 [R/W] B

00000000

PCR6 [R/W] B

00000000

⎯

T-unit

Pull-up Control

Register

PCR8 [R/W] B

--000000

PCR9 [R/W] B

00000000

PCRA [R/W] B

00000000

PCRB [R/W] B

00000000

PCRC [R/W] B

-----000

⎯

000630^H

to

00063C^H

⎯

Reserved

ASR0 [R/W] H, W

00000000 00000000

ACR0 [R/W] B, H, W

1111XX00 00000000

000640^H

000644^H

000648^H

ASR1 [R/W] H, W

00000000 00000000

ACR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

T-unit

ASR2 [R/W] H, W

00000000 00000000

ACR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

(Continued)

42

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

ASR3 [R/W] H, W

00000000 00000000

ACR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

00064C^H

000650^H

000654^H

000658^H

00065C^H

000660^H

000664^H

000668^H

00066C^H

ASR4 [R/W] H, W

00000000 00000000

ACR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR5 [R/W] H, W

00000000 00000000

ACR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR6 [R/W] H, W

00000000 00000000

ACR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

ASR7 [R/W] H, W

00000000 00000000

ACR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR0 [R/W] B, H, W

01111111 11111111

AWR1 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR2 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR3 [R/W] B, H, W

XXXXXXXX XXXXXXXX

T-unit

AWR4 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR5 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR6 [R/W] B, H, W

XXXXXXXX XXXXXXXX

AWR7 [R/W] B, H, W

XXXXXXXX XXXXXXXX

000670^H

000674^H

⎯

IOWR0 [R/W] B, H, W IOWR1 [R/W] B, H, W IOWR2 [R/W] B, H, W

000678^H

00067C^H

000680^H

⎯

XXXXXXXX

⎯

CSER [R/W] B, H, W

00000001

TCR [W] B, H, W

0000XXXX

⎯

000684^H

to

000AFC^H

Reserved

ESTS0 [R/W]

X0000000

ESTS1 [R/W]

XXXXXXXX

ESTS2 [R]

1XXXXXXX

000B00^H

000B04^H

000B08^H

⎯

DSU

(Evalua-

tion chip

only)

ECTL0 [R/W]

0X000000

ECTL1 [R/W]

00000000

ECTL2 [W]

000X0000

ECTL3 [R/W]

00X00X11

ECNT0 [W]

XXXXXXXX

ECNT1 [W]

XXXXXXXX

EUSA [W]

XXX00000

EDTC [W]

0000XXXX

(Continued)

43

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

EWPT [R]

000B0C^H

⎯

00000000 00000000

EDTR0 [W]

XXXXXXXX XXXXXXXX

EDTR1 [W]

XXXXXXXX XXXXXXXX

000B10^H

000B14^H

to

000B1C^H

⎯

EIA0 [W]

000B20^H

000B24^H

000B28^H

000B2C^H

000B30^H

000B34^H

000B38^H

000B3C^H

000B40^H

000B44^H

000B48^H

000B4C^H

000B50^H

000B54^H

000B58^H

000B5C^H

000B60^H

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA2 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA3 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA4 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA5 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA6 [W]

DSU

(Evaluation

chip only)

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIA7 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTA [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EDTM [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOA1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPCR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EPSR [R/W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EIAM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOAM0/EODM0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

(Continued)

44

MB91350A Series

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

EOAM1/EODM1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B64^H

000B68^H

000B6C^H

DSU

(Evaluation

chip only)

EOD0 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

EOD1 [W]

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70^H

to

000BFC^H

⎯

Reserved

Interrupt

Control unit

000C00^H

Register access disallowed

000C04^H

to

000C14^H

R-bus test

Reserved

000C18^H

to

000FFC^H

⎯

DMASA0 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001000^H

001004^H

001008^H

00100C^H

001010^H

001014^H

001018^H

00101C^H

001020^H

001024^H

DMADA0 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA1 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA1 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA2 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMAC

DMADA2 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA3 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA3 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMASA4 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMADA4 [R/W] W

XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

001028^H

to

001FFC^H

⎯

Reserved

(Continued)

45

MB91350A Series

(Continued)

Register

Block

diagram

Address

+ 0

+ 1

+ 2

+ 3

FLCR [R/W]

007000^H

⎯

0110X000

FLWC [R/W]

007004^H

⎯

Flash

00010011

memory

007008^H

00700C^H

007010^H

⎯

007014^H

to

0070FF^H

⎯

Reserved

*1 : Test register access barred

*2 : The lower 16-bit (DTC(15: 0)) of DMACA0 to DMACA4 cannot be accessed in byte.

*3 : The available area of internal RAM is restricted by the function described in 6-209 immediately after a reset is

canceled. When the setting of the available area is updated, the instruction must be followed by at least 1 NOP

instruction.

46

MB91350A Series

■ VECTOR TABLE

Interrupt

number

Interrupt

level

TBR default

address

Interrupt source

Offset

RN

10

16

Reset

0

1

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

⎯

3FC^H

3F8^H

3F4^H

3F0^H

3EC^H

3E8^H

3E4^H

3E0^H

3DC^H

3D8^H

3D4^H

3D0^H

3CC^H

3C8^H

3C4^H

000FFFFC^H

000FFFF8^H

000FFFF4^H

000FFFF0^H

000FFFEC^H

000FFFE8^H

000FFFE4^H

000FFFE0^H

000FFFDC^H

000FFFD8^H

000FFFD4^H

000FFFD0^H

000FFFCC^H

000FFFC8^H

000FFFC4^H

⎯

Mode vector

System reserved

Coprocessor absent trap

Coprocessor error trap

INTE instruction

2

3

4

5

6

7

8

9

Instruction break exception

Operand break trap

Step trace trap

10

11

12

13

14

NMI request (tool)

Undefined instruction exception

15 (F^H)

fixed15

NMI request

15

0F

3C0^H

000FFFC0^H

⎯

External interrupt 0

External interrupt 1

External interrupt 2

External interrupt 3

External interrupt 4

External interrupt 5

External interrupt 6

External interrupt 7

Reload timer 0

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

ICR16

3BC^H

3B8^H

3B4^H

3B0^H

3AC^H

3A8^H

3A4^H

3A0^H

39C^H

398^H

394^H

390^H

38C^H

388^H

384^H

380^H

37C^H

000FFFBC^H

000FFFB8^H

000FFFB4^H

000FFFB0^H

000FFFAC^H

000FFFA8^H

000FFFA4^H

000FFFA0^H

000FFF9C^H

000FFF98^H

000FFF94^H

000FFF90^H

000FFF8C^H

000FFF88^H

000FFF84^H

000FFF80^H

000FFF7C^H

6

7

11

⎯

8

Reload timer 1

9

Reload timer 2

10

0

UART(Reception completed)

UART0 (RX completed)

UART1 (RX completed)

UART2 (RX completed)

1

2

3

4

5

(Continued)

47

MB91350A Series

Interrupt

number

Interrupt

level

TBR default

address

Interrupt source

Offset

RN

10

33

34

35

36

37

38

39

40

41

42

43

44

45

16

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

DMAC0 (end, error)

DMAC1 (end, error)

DMAC2 (end, error)

DMAC3 (end, error)

DMAC4 (end, error)

A/D

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

378^H

374^H

370^H

36C^H

368^H

364^H

360^H

35C^H

358^H

354^H

350^H

34C^H

348^H

000FFF78^H

000FFF74^H

000FFF70^H

000FFF6C^H

000FFF68^H

000FFF64^H

000FFF60^H

000FFF5C^H

000FFF58^H

000FFF54^H

000FFF50^H

000FFF4C^H

000FFF48^H

⎯

15

⎯

12

13

14

⎯

I²C

UART4 (Reception completed)

SIO 5

SIO 6

SIO 7

UART3 (Reception completed)

UART3 (RX completed)

Reload timer 3/main oscillation stabilization

wait timer

46

2E

ICR30

344^H

000FFF44^H

⎯

Timebase timer overflow

External interrupt: FPINT(8-15)

Clock counter

47

48

49

50

51

52

53

54

55

56

2F

30

31

32

33

34

35

36

37

38

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

340^H

33C^H

338^H

334^H

330^H

32C^H

328^H

324^H

320^H

31C^H

000FFF40^H

000FFF3C^H

000FFF38^H

000FFF34^H

000FFF30^H

000FFF2C^H

000FFF28^H

000FFF24^H

000FFF20^H

000FFF1C^H

⎯

U/D Counter0

U/D Counter1

PPG 0/1

PPG 2/3

PPG 4/5

16-bit free-run timer

ICU2/3 (capture)

ICU1 (capture)/UART4 (transmission

complete)

57

39

ICR41

318^H

000FFF18^H

⎯

ICU0 (capture)

58

59

60

61

62

63

64

65

3A

3B

3C

3D

3E

3F

40

41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

⎯

314^H

310^H

30C^H

308^H

304^H

300^H

2FC^H

2F8^H

000FFF14^H

000FFF10^H

000FFF0C^H

000FFF08^H

000FFF04^H

000FFF00^H

000FFEFC^H

000FFEF8^H

⎯

OCU0/1 (match)

OCU2/3 (match)

OCU4/5 (match)

OCU6/7 (match)

Interrupt delay source bit

System reserved (Used by REALOS)

⎯

(Continued)

48

MB91350A Series

(Continued)

Interrupt

number

Interrupt

level

TBR default

address

Interrupt source

Offset

RN

10

66

67

68

69

70

71

72

73

74

75

76

77

78

79

16

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

System reserved

⎯

2F4^H

2F0^H

2EC^H

2E8^H

2E4^H

2E0^H

2DC^H

2D8^H

2D4^H

2D0^H

2CC^H

2C8^H

2C4^H

2C0^H

000FFEF4^H

000FFEF0^H

000FFEEC^H

000FFEE8^H

000FFEE4^H

000FFEE0^H

000FFEDC^H

000FFED8^H

000FFED4^H

000FFED0^H

000FFECC^H

000FFEC8^H

000FFEC4^H

000FFEC0^H

⎯

80

to

255

50

to

FF

2BC^H

to

000^H

000FFEBC^H

to

000FFC00^H

Used by INT instruction

⎯

49

MB91350A Series

■ PERIPHERAL RESOURCES

1. Interrupt controller

(1)Description

The interrupt controller manages interrupt reception and arbitration.

• Hardware configuration

This module consists of the following components:

• ICR register

• Interrupt priority determination circuit

• Interrupt level and interrupt number (vector) generator

• HOLD request cancellation request generator

• Main function

This module has the following major functions:

• Detect NMI and interrupt requests

• Prioritize interrupts (according to level and number)

• Notify interrupt level of selected interrupt request (to CPU)

• Notify interrupt number of selected interrupt request (to CPU)

• Request (to the CPU) to return from stop mode in response to an NMI or interrupt request with interrupt level

other than “11111”

• Hold request cancellation request issued to the bus master

(2)Register list

ICR register

7

6

5

4

3

2

1

0

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

⎯

ICR4 ICR3 ICR2 ICR1 ICR0

(Continued)

50

MB91350A Series

(Continued)

7

6

5

4

3

2

1

0

ICR16

ICR17

ICR18

ICR19

ICR20

ICR21

ICR22

ICR23

ICR24

ICR25

ICR26

ICR27

ICR28

ICR29

ICR30

ICR31

ICR32

ICR33

ICR34

ICR35

ICR36

ICR37

ICR38

ICR39

ICR40

ICR41

ICR42

ICR43

ICR44

ICR45

ICR46

ICR47

⎯

ICR4 ICR3 ICR2 ICR1 ICR0

Hold request cancel request resister (HRCL)

7

6

5

4

3

2

1

0

HRCL MHALT1

⎯

LVL4

LVL3

LVL2

LVL1

LVL0

51

MB91350A Series

(3)Block diagram

^{("1" when LEVEL}≠ ¹¹¹¹¹⁾

UNMI

WAKEUP

Determine order of priority

LEVEL4 to LEVEL0

MHALTI

5

NMI

HLDREQ

Cancel

NMI

LEVEL determination

LEVEL,

VECTOR

Genera-

tion

request

ICR00

RI00

VCT5 to VCT0

6

VECTOR

determination

R-bus

52

MB91350A Series

2. External interrupt/NMI control

(1)Description

The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to

INT15.

The level can be selected from “H”, “L”, rising edge, or falling edge (except for NMI).

(2)Register list

External interrupt enable register (ENIR)

7

6

5

4

3

2

1

0

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

External interrupt request register (EIRR)

15

14

13

12

11

10

9

8

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

Request level setting register (ELVR)

15

14

13

12

11

10

9

8

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

7

6

5

4

3

2

1

0

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

The above registers (for 8 channels) are available in two sets; there are a total of 16 channels.

(3)blockdiagram

R-bus

8

Interrupt enable register

17

8

17

Edge detection

circuit

INT0 to INT15

NMI

Request F/F

Interrupt

request

Gate

Interrupt source register

16

Interrupt level setting register

53

MB91350A Series

3. REALOS-related Hardware

REALOS-related hardware is used by the real-time OS. Therefore, REALOS-related hardware cannot be used

by user programs when REALOS is used.

• Delay interrupt module

(1)Description

The delayed interrupt module generates a task switching interrupt.

This module enables software to issue or cancel an interrupt request to the CPU.

(2)Register list

Delayed Interrupt Control Register (DICR)

7

6

5

4

3

2

1

0

⎯

DLY1

(3)Block diagram

R-bus

DLYI

Interrupt request

54

MB91350A Series

• Bit Search Module

(1)Description

The bit search module searches data written to an input register for “0”, “1”, or a change point and returns the

detected bit position.

(2)Register list

31

0

0 detection data register (BSD0)

1 detection data register (BSD1)

Data register for transition detection (BSDC)

Detection result register (BSRR)

(3)Block diagram

D-bus

Input latch

Detection

mode

Address decoder

Creating 1 detection data

Bit search circuit

Search results

55

MB91350A Series

4. 8/16-bit up/down counter

(1)Description

This block is the up/down counter consisting of 6 event input pins, an 8/16-bit up/down counter, an 8-bit reload/

compare register, and their control circuit.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 2 channels of 8/16-bit up/down

counter in this block.

This module has the following features.

• 8-bit count register enabling counting from (0)d to (255)d (enabling counting from (0)d to (65535)d in "16-bit

x 1 operation mode" ).

• Four different count modes available with selectable count clocks

Count mode

Timer mode

Up/down counter mode

Phase difference count mode (2 multiplication)

Phase difference count mode (4 multiplication)

• Capable of selecting a count clock signal in timer mode, from among the inputs from two internal clocks and

an internal circuit

Count clock

80 ns (12.5 MHz : 2-frequency division)

(When operating at 25 MHz )

320 ns (3.125 Hz : 8-frequency division)

• Capable of selecting the detection edge of the external pin input signal in up/down counter mode

Detection edge

Falling Edge detection

Rising Edge detection

Detection at rising edge, falling edge, or both edges

Edge detection disabled

• Phase difference count mode suitable for counting for an encoder such as a motor, capable of easily counting

the rotation angle and the number of revolutions at high precision by inputting the phase-A, phase-B, and

phase-Z outputs of the encoder

• ZIN pin available for two functions selectable (valid in all modes)

ZIN Pin

Counter clear function

Gate function

• Compare and reload functions available not only separately but also in combination for up/down counting at

an arbitrary width

Compare/reload function

Compare function (comparison interrupt request output)

Compare function (comparison interrupt request output and counter clear)

Reload function (underflow interrupt request output and reload)

Compare/reload function(Comparison interrupt request output and counter

clear; underflow interrupt request output and reload)

Compare/reload disabled

• Count direction flag used to identify the preceding count direction

• Capable of controlling the independent generations of interrupts at a compare match, reload (underflow),

overflow, or at a count direction change

56

MB91350A Series

(2)Register list

• Up/down count resister (UDCR)

Up/down count resister ch0 (UDCR0)

7

6

5

4

3

2

1

0

D07

D06

D05

D04

D03

D02

D01

D00

Up/down count resister ch1 (UDCR1)

15

14

13

12

11

10

9

8

D15

D14

D13

D12

D11

D10

D09

D08

• Reload compare resister (RCR)

Reload compare resister ch0 (RCR0)

7

6

5

4

3

2

1

0

D07

D06

D05

D04

D03

D02

D01

D00

Reload compare resister ch1 (RCR1)

15

14

13

12

11

10

9

8

D15

D14

D13

D12

D11

D10

D09

D08

• Counter status register (CSR)

Counter status register ch(0, 1) (CSR0, 1)

7

6

5

4

3

2

1

0

CST

CIT

UDI

CM

OVF

UD

• Counter control resister (CCRL)

Counter control resister ch(0, 1) (CCRL0, 1)

7

6

5

4

3

2

1

0

Reserved

CTU

UC

RLD

UD

CGS

CGE

• Counter control resister (CCRH)

Counter control resister ch0 (CCRH0)

15

14

CDC

13

12

11

10

9

8

M16

CFI

CLK

CM

CES

• Counter control resister ch1 (CCRH1)

15

14

13

12

11

10

9

8

CDC

CFI

CLK

CM

CES

Reserved

57

MB91350A Series

(3)Block diagram

Data bus

8 bit

To ch1

RCR0(Reload

CGE

CGS

M16

compare register ch0

Reload

control

CTU

Carry

Edge/level detection

ZIN0, ZIN1

UC

RLD

Counter clear

8 bit

UD

UDCR0(up/down

counter register ch0

CES

CM

CES

CM

UD

OVF

Count

Clock

Up/down

count

clock

AIN0, AIN1

BIN0, BIN1

UDI

CST

UD

select

UD

CDC

Prescaler

CIT

CFI

CLK

Interrupt output

58

MB91350A Series

5. 16-bit Reload Timer

(1)Description

The16-bittimerconsistsofa16-bitdowncounter, 16-bitreloadregister, internalclock, clockgenerationprescaler,

and control register.

The clock source can be selected from among three internal clocks (prepared by frequency dividing the machine

clock by 2/8/32, and also by 64/128 only for ch3) and an external event.

The interrupt can be used to initiate DMA transfer.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 4 channels of this timer.

(2)Register list

Control status register (TMCSR)

15

14

13

12

11

10

9

8

Reserved Reserved

⎯

CSL2

CSL1

CSL0

Reserved

(ch3 only)

7

6

5

4

3

2

1

0

⎯

OUTL

RELD

INTE

UF

CNTE

TRG

Reserved

16-bit timer register(TMR)

15

0

16-bit reload register(TMRLR)

15

59

MB91350A Series

(3)Block diagram

16-bit reload register (TMRLR)

16

7

Reload

16

16-bit timer register (TMR) UF

RELD

OUTL

INTE

UF

OUT

CTL.

Count enable

IRQ

R

|

b

u

s

CSL2

Re-trigger

CNTE

TRG

CSL1

Clock selector

CSL0

External timer output

(TOT0 to TOT3)

TOE0 to 3

Bit in PFRP

EXCK

3

IN CTL.

φ

Prescaler clear

2¹2³2⁵2⁶2⁷

(ch3 only)

Machine clock input

60

MB91350A Series

6. PPG (Programable Pulse Generator)

The PPG can efficiently output highly precise PWM waveforms.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 6 channels of PPG timer.

(1)Description

Each channel consists of a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare

register with duty ratio setting buffer, and pin control unit.

The count clocks for the 16-bit down counter can be selected from the following 4 types :(peripheral clock φ, φ/

4, φ/16, φ/64)

The counter is initialized to "FFFF^H" at a reset or counter borrow.

PPG outputs (PPG0 to PPG5) are provided for each channel.

(2)Register list

15

0

General control register 10 (GCN10)

General control register 20 (GCN20)

Timer register (PTMR0 to 5)

Cycle setting register (PCSR0 to 5)

Duty setting register (PDUT0)

(3)Block diagram (overall configuration for 1 channel)

TRG input

PPG timer ch0

16-bit reload timer ch0

PPG0

PPG1

PPG2

PPG3

16-bit reload timer ch1

General D/A control

ICR register 10

(resource select)

General D/A control

ICR register 20

TRG input

PPG timer ch1

TRG input

PPG timer ch2

4

External TRG0 to

TRG3

TRG input

PPG timer ch3

TRG input

PPG timer ch4

External TRG4

External TRG5

PPG4

PPG5

TRG input

PPG timer ch5

61

MB91350A Series

7. U-Timer (16-bit timer for UART baud rate generation)

(1) Description

The U-Timer is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set

depending on the combination of the chip operating frequency and U-Timer reload value.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5 channels of this timer.

(2) Register list

15

8 7

0

U-Timer Register (UTIM)

Reload Register (UTIMR)

U-Timer Control Register (UTIMC)

(3) Block diagram

15

0

UTIMR (reload register)

load

UTIM (U-timer)

clock

underflow

f.f.

φ

control

(Peripheral clock)

to UART

62

MB91350A Series

8. UART

(1) Description

The UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module

has the features listed below. The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 5

channels of UART.

• Full duplex double buffer

• Asynchronous (start-stop synchronized) or CLK synchronized transmission

• Supports multi-processor mode

• Completely programmable baud rate.

Arbitrary baud rate set by built-in timer (See the section for "U-Timer”.)

• Variable baud rate can be input from an external clock.

• Error detection functions(parity, framing, overrun)

• Transmission signal format is NRZ

• UART Ch0 to Ch2 can start DMA transfer using interrupts (Ch3 and Ch4 cannot start DMA transfer).

• Capable of clearing DMAC interrupt source by writing to DRCL register

(2)Register list

Serial input register/serial output register (SIDR/SODR)

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Serial status register(SSR)

7

6

5

4

3

2

1

0

PE

ORE

FRE

RDRF

TDRE

BDS

RIE

TIE

Serial mode register

7

6

5

4

3

2

1

0

MD1

MD0

⎯

CS0

⎯

Serial control register(SCR)

7

6

5

4

3

2

1

0

PEN

P

SBL

CL

A/D

REC

RXE

TXE

DECL register (DRCL)

7

6

5

4

3

2

1

0

⎯

63

MB91350A Series

(3) Block diagram

Control signal

RX interrupt

(to CPU)

SCK (clock)

Transmission clock

From U-Timer

Clock

TX interrupt

(to CPU)

selection

Reception clock

circuit

External clock

SCK

Reception control

Transmission

circuit

control circuit

SI (Receive data)

Start bit

detection circuit

Transmission

start circuit

Sending bit

Counter

Received bit

Counter

Received parity

Counter

Sending parity

Counter

SO (Send data)

Receive status

decision circuit

RX shifter

RX

TX shifter

Start

transmis-

sion

complete

SIDR

SODR

For DMA

receivederrorgenerating

signal (to DMAC)

R - bus

MD1

MD0

PEN

P

PE

ORE

FRE

RDRF

TDRE

BDS

RIE

SBL

CL

SMR

Register

SCR

Register

SSR

Register

CS0

A/D

REC

RXE

TXE

TIE

Control signal

64

MB91350A Series

9. Extended I/O Serial Interface (SIO)

(1) Description

This block is a serial I/O interface that allows data transfer using clock synchronization. It is composition of a

single 8-bit × 1 channel.

LSB-first or MSB-first transfer mode can be selected for data transfer.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 3 channels of this SIO.

The serial I/O interface operates in 2 modes:

• Internal shift clock mode: Transfer data in synchronization with the internal clock.

• External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK).

By manipulating the general-purpose port sharing the external pin (SCK) in this

mode, data can also be transferred by a CPU instruction.

(2) Register list

Serial mode control status register (SMCS)

15

14

13

12

11

10

9

8

SMD2 SMD1 SMD0

SIE

SIR

BUSY

STOP

STRT

7

6

5

4

3

2

1

0

⎯

MODE

BDS

⎯

SIO test resister(SES)

15

14

13

12

11

10

9

8

⎯

TST1

TST0

SDR (Serial Data Register)

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

SIO prescaler control register (CDCR)

15

14

13

12

11

10

9

8

MD

⎯

DIV3

DIV2

DIV1

DIV0

DMAC interrupt source clear register (SRCL)

7

6

5

4

3

2

1

0

⎯

65

MB91350A Series

(3)Block diagram

Initial Value

Internal data bus

(MSB fast) D0 to D7

Select transmitting direction

(MSB fast) D0 to D7

SI5 to SI7

Read

write

SDR (Serial Data Register)

SO5 to SO7

SCK5 to SCK7

Shift clock counter

Control circuit

Internal clock

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS

SCE

PFR

Register

Interrupt

request

Internal data bus

66

MB91350A Series

10. 16-bit free-run timer

(1)Description

The 16-bit free-running timer consists of a 16-bit up counter, control register, and status register. The count

values of this timer are used as the base timer for the output compares and input capture modules.

• Four count clock frequencies are available.

• An interrupt can be generated at a counter overflow.

• The counter can be initialized upon a match with compare register 0 of the output compare unit, depending

on the mode.

(2)Register list

Timer data register (upper) (TCDT)

15

14

13

12

11

10

9

8

T15

T14

T13

T12

T11

T10

T9

T8

Timer data register (lower) (TCDT)

7

6

5

4

3

2

1

0

T07

T06

T05

T04

T03

T02

T01

T00

Timer control status register (lower) (TCCS)

7

6

5

4

3

2

1

0

ECLK

IVF

IVFE

STOP MODE

CLR

CLK1

CLK0

(3)Block diagram

Interrupt

ECLK

IVF

IVFE

STOP MODE

CLR

CLK1

CLK0

φ

Divider

FRCK

Clock

select

Timer data register

(TCDT)

Clock

to internal circuit (T15 to T00)

Comparator 0

67

MB91350A Series

11. Input Capture

(1) Description

This module detects a rising or falling edge or both edges of an external input signal and stores the 16-bit free-

running timer value in a register.

This module stores the 16-bit free-running timer value in a register. In addition, the module can generate an

interrupt upon detection of an edge.

The input capture module consists of input capture data registers and a control register.

Each input capture unit has a corresponding external input pin.

• The detection edge of an external input can be selected from among 3 types.

Rising edge

Falling edge

Both edges

• An interrupt can be generated upon detection of a valid edge of an external input.

(2) Register list

Input capture data register (upper) (IPCP)

15

14

13

12

11

10

9

8

CP15

CP14

CP13

CP12

CP11

CP10

CP09

CP08

Input capture data register (lower) (IPCP)

7

6

5

4

3

2

1

0

CP07

CP06

CP05

CP04

CP03

CP02

CP01

CP00

Capture control register (ICS23)

7

6

5

4

3

2

1

0

ICP3

ICP2

ICE3

ICE2

EG31

EG30

EG21

EG20

Capture control register (ICS01)

7

6

5

4

3

2

1

0

ICP1

ICP0

ICE1

ICE0

EG11

EG10

EG01

EG00

68

MB91350A Series

(3) Block diagram

16-bit timer counter value

(T15 to T00)

IN0, IN2

Input pin

Input capture data register

ch (0, 2)

Edge

detection

EG11

EG31

EG10

EG30

EG01

EG21

EG00

EG20

16-bit timer counter value

(T15 to T00)

IN1, IN3

Input pin

Input capture data register

ch (1, 3)

Edge

detection

ICP1

ICP3

ICP0

ICP2

ICE1

ICE3

ICE0

ICE2

Interrupt

69

MB91350A Series

12. Output Compare

(1) Description

The output compare module consists of 16-bit compare registers, compare output latch, and control register.

When the 16-bit free-running timer value matches the compare register value, the output level is inverted and

an interrupt is issued.

The MB91F355A/MB91F356B/MB91355A/MB91354A/MB91V350A contain 8 channels of this block.

This module has the features listed below.

• Capable of using the 8 compare registers independently. Output pins and interrupt flags corresponding to the

compare registers

• A pair of compare registers can be used to control output pins. Using tow compare registers to invert output pins

• Capable of setting the initial value for each output pin.

• Interrupts can be generated upon a compare match.

• The ch0 compare register is used as the compare clear register for the 16-bit free-running timer.

(2)Register list

Output compare register(upper) (OCCP)

15

14

13

12

11

10

9

8

C15

C14

C13

C12

C11

C10

C09

C08

Output compare register(lower) (OCCP)

7

6

5

4

3

2

1

0

C07

C06

C05

C04

C03

C02

C01

C00

Output control register(upper) (OCS)

15

14

13

12

11

10

9

8

⎯

CMOD

⎯

OTD1

OTD0

Output control register(lower) (OCS)

7

6

5

4

3

2

1

0

ICP1

ICP0

ICE1

ICE0

⎯

CST1

CST0

70

MB91350A Series

(3) Block diagram

OTD1 OTD0

(Only ch0 is used as a free running timer

clear register.)

Output compare

register

Compare

Output latch

OTE0, OTE2,

OTE4, OTE6

Output

Compare circuit

OTE0 and OTE7 exist in PFRO.

There is in PFRO.

Output compare

register

CMOD

Compare

Output latch

OTE1, OTE3,

OTE5, OTE7

Output

Compare circuit

CST1

CST0

ICP1

ICP0

ICE1

ICE0

16-bit free-run timer

Interrupt output

71

MB91350A Series

13. I²C Interface

(1) Description

The I²C interface is a serial I/O port supporting the Inter-IC bus, operating as a master/slave device on the I²C

bus. It has the following features

• Master/slave sending and receiving

• Arbitration function

• Clock sync function

• Slave address and general call address detection function

• Ditecting function of transmitting direction

• Repeated start condition generation and detection function

• Bus error detection function

• 10-bit/7-bit slave address

• Slave address receive acknowledge control when in master mode

• Support for composite slave addresses

• Capable of interruption when a transmission or bus error occurs

• Standard mode (Max 100K bps)/High speed mode (Max 400K bps) supported

72

MB91350A Series

(2)Register list

Bus control register(IBCR)

15

14

13

12

11

10

9

8

BER BEIE SCC MSS ACK GCAA INTE INT

Bus status register(IBSR)

7

6

5

4

3

2

1

0

BB

RSC

AL

LRB TRX AAS GCA ADT

10-bit slave address resister (ITBA)

15

14

13

12

11

10

9

8

⎯

TA9

TA8

7

6

5

4

3

2

1

0

TA7

TA6

TA5

TA4

TA3

TA2

TA1

TA0

10-bit slave address mask resister(ITMK)

15

14

13

12

11

10

9

8

ENTB RAL

⎯

TM9 TM8

7

6

5

4

3

2

1

0

TM7

TM6

TM5

TM4

TM3

TM2

TM1

TM0

7-bit slave address resister (ISBA)

7

6

5

4

3

2

1

0

⎯

SA6 SA5 SA4 SA3 SA2 SA1 SA0

7-bit slave address mask resister (ISMK)

15 14 13

ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0

12

11

10

9

8

Data register (IDAR)

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Clock control register (ICCR)

15

14

13

12

11

10

9

8

TEST

⎯

EN

CS4

CS3

CS2

CS1

CS0

Clock disable register (IDBL)

7

6

5

4

3

2

1

0

⎯

DBL

73

MB91350A Series

(3) Block diagram

ICCR

EN

Operation enable

IDBL

DBL

CLKP

Clock enable

Clock divide 2

ICCR

CS4

CS3

CS2

CS1

CS0

Sync

2 3 4 5

32

Generating shift clock

Clock selector2 (1/12)

Shift clock edge

changing timing

IBSR

Bus busy

BB

Start

Start stop condition

detection

RSC

LRB

TRX

Last Bit

Error

Sending/

receiving

First Byte

ADT

AL

Arbitration lost detection

IBCR

BER

SCLI

SCLO

BEIE

INTE

INT

SDA

SDAO

Interrupt request

End

IRQ

IBCR

SCC

Start

Master

MSS

ACK

Start stop condition

generation

ACK enable

GCAA

IDAR

IBSR

AAS

Slave

Global call

Slave address

compare

GCA

ISMK

FNSB

ITMK

ENTB

RAL

ITBA

ITMK

ISBA

ISMK

74

MB91350A Series

14. A/D Converter

(1) Description

The A/D converter converts the analog input voltage into a digital value. It has the following features:

• Conversion time: 1.48 µs minimum per channel

• Employing serial/parallel conversion type for sample & hold circuit

• 10-bit resolution (switchable between 8 and 10 bits)

• Program selection of the analog input from among 12 channels

• Conversion mode

Single conversion mode : Convert 1 selected channel

Scan conversion mode : Scan up to 4 channels.

• Converted data is stored in the data buffer.

• An interrupt request to the CPU can be generated upon completion of A/D conversion. The interrupt can be

used to start DMA transfer.

• The startup source can be selected from among software, external trigger (falling edge), and reload timer ch2

(rising edge).

(2) Register list

15

8 7

0

Control status register (ADCS2/ADSC1)

Conversion time setting resister (ADCT)

Converted data register 0 (ADTH0/ADTL0)

Converted data register 1 (ADTH1/ADTL1)

Converted data register 2 (ADTH2/ADTL2)

Converted data register 3 (ADTH3/ADTL3)

ADCS2

ADCS1

ADTH0

ADTH1

ADTH2

ADTH3

ADTL0

ADTL1

ADTL2

ADTL3

75

MB91350A Series

(3) Block diagram

Analog input

AVCC, AVRH, AVSS/AVRL

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

ADT0

ADT1

ADT2

ADT3

M

P

X

M

P

X

10 bit

A/D

Converter

S/H

AN9

AN10

AN11

Control logic

Interrupt

16-bit reload timer ch2

External input

76

MB91350A Series

15. 8-bit D/A Converter

(1) Description

This block contains 2 channels of 8-bit D/A converters. The D/A converter register can be used to control the

independent output of each channel. The block has the following features.

• Power saving function

• 3.3 V Interface

(2) Register list

D/A data register 0 to 2(DADR0 to DADR2)

7

6

5

4

3

2

1

0

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

D/A control register 0 to 2 (DACR0 to DACR2)

7

6

5

4

3

2

1

0

⎯

DAE

(3) Block diagram

R-bus

D/A

D/A control

D/A

DAE0

STOP

DAE1

DAE2

PD

STOP

D/A

converter

D/A

converter

D/A

converter

D/A output 0

D/A output 1

D/A output 2

77

MB91350A Series

16. DMAC (DMA Controller)

(1) Description

This module realize direct memory access (DMA) transfer with the FR family device.

DMA transfer controlled by this module enables many types of data transfer to be performed at high speed

without CPU intervention, thereby improving system performance.

• Hardware configuration

This model consists mainly of the following components:

• Independent DMA channels × 5 channels

• 5 channels independent access control circuits

• 32-bit address register (Supports reloading: 2 per channel)

• 16-bit transfer count register (Supports reloading: 1 per channel)

• 4-bit block count register (1 per channel)

• External transfer request input pins: DREQ0, DREQ1, DREQ2 (ch0, ch1, ch2 only)

• External transfer request acceptance output pins: DACK0, DACK1, DACK2 (ch0, ch1,ch2 only)

• DMA end output pins: DEOP0, DEOP1, DEOP2 (ch0, ch1, ch2 only)

• (ch3 only) fly-by transfer (memory to I/O, I/O to memory)

• 2-cycle transfer

• Main function

This module has the following major functions for data transfer:

• Supports independent data transfer for multiple channels (5 channels)

(1) Priority order (ch0 > ch1 > ch2 > ch3 > ch4)

(2) Order can be reversed for ch0 and ch1

(3) DMAC activation triggers

• External dedicated pin input (edge detection/level detection: ch0 to ch2 only)

• Internal peripheral request (Interrupt request sharing, including external interrupts)

• Software request (register write)

(4) Transmission mode

• Demand transfer, burst transfer, step transfer, or block transfer

• Addressing mode: 32-bit full addressing (increment, decrement, or fixed)

(address increment can be in the range - 255 to + 255)

• Data length: Byte, halfword, or word

• Single-shot or reload operation selectable

78

MB91350A Series

(2) Register Description

31

16 15

0

Ch0 control/status

Ch1 control/status

Ch2 control/status

Ch3 control/status

Ch4 control/status

register A (DMACA0)

register B (DMACB0)

register A (DMACA1)

register B (DMACB1)

register A (DMACA2)

register B (DMACB2)

register A (DMACA3)

register B (DMACB3)

register A (DMACA4)

register B (DMACB4)

(DMACR)

Overall control register

Ch0 transfer source address register

(DMASA0)

(DMADA0)

Ch1 transfer source address register

Ch2 transfer source address register

Ch3 transfer source address register

Ch4 transfer source address register

(DMASA1)

(DMADA1)

(DMASA2)

(DMADA2)

(DMASA3)

(DMADA3)

(DMASA4)

(DMADA4)

79

MB91350A Series

(3) Block diagram

Counter

Buffer

Peripheral start request/

Stop input

DMA start

source select

circuit & request

acceptance

control

DMA transfer request

to bus controller

Selector

External pin start

request/stop input

DTC two-stage register

DTCR

Counter

Buffer

DSS [3:0]

Priority

circuit

IRQ

[4:0]

To interrupt controller

ERIR, EDIR

Read/write

control

Read

Write

Selector

MCLREQ

BLK register

Clear peripheral interrupt

Status

transition

circuit

TYPE, MOD, WS

DDNO register

DDNO

To

bus

con-

troller

DMA control

DSAD two-stage register ^{SADM, SASZ [7:0] SADR}

Write back

Access

Address

DADM, DASZ [7:0] DADR

DDAD two-stage register

Write back

5-channel DMAC block diagram

80

MB91350A Series

■ ELECTRICAL CHARACTERISTICS

1. Abusolute Maximum Rating

Rating

Parameter

Symbol

Unit

Remarks

*2

Min

Max

V^SS+ 4.0

V^CC+ 0.5

V^SS+ 5.5

AV^CC+ 0.5

V^CC+ 0.5

+ 2.0

Power supply voltage*¹

V^CC

DA^VC

AV^CC

AVRH

V^I

V^SS− 0.5

− 2.0

V

Analog power supply voltage*¹

Analog reference voltage*¹

Input voltage*¹

*3

*8

V

Input voltage (Nch open-drain) *¹

Analog pin input voltage*¹

Output voltage*¹

V^IND

V

V^IA

V

V^O

V

Maximum clamp current

Total maximum clamp current

“L” level maximum output current

I^CLAMP

Σ|I^CLAMP|

I^OL

mA

*7

*4

⎯

20

⎯

10

“H” level maximum output current

(Nch open-drain)

I^OLND

I^OLAV

⎯

20

8

mA

“L” level average output current

*5

“H” level average output current

(Nch open-drain)

I^OLAVND

15

“L” level total maximum output

current

ΣI^OL

⎯

100

50

mA

“L” level total average output

current

ΣI^OLAV

*6

“H” level maximum output current

“H” level average output current

I^OH

⎯

− 10

− 4

mA

*4

*5

I^OHAV

“H” level total maximum output

current

ΣI^OH

⎯

− 50

− 20

mA

“H” level total average output

current

ΣI^OHAV

*6

Power consumption

Operating temperature

Storage temperature

P^D

T^a

⎯

− 40

⎯

850

+ 85

+ 125

mW

°C

T^STG

°C

*1 : The parameter is based on V^SS= DA^VS= AV^SS= 0 V.

*2 : V^CCmust not be lower than V^SS- 0.3 V.

*3 : Be careful not to exceed "V^CC+ 0.3 V”, for example, when the power is turned on.

*4 : The maximum output current is the peak value for a single pin.

*5 : The average output current is the average current for a single pin over a period of 100 ms.

*6 : The total average output current is the average current for all pins over a period of 100 ms.

81

MB91350A Series

*7 : • Relevant pins: Port2, 3, 4, 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P, and AN (A/D input)

• Use within recommended operating conditions.

• Use at DC voltage (current).

• The + B signal should always be applied a limiting resistance placed between the + B signal and

the microcontroller.

• The value of the limiting resistance should be set so that when the + B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that, when the microcontroller drive current is low as in low power consumption mode, the + B input

potential can increase the potential at the V^CCpin via a protective diode, possibly affecting other devices.

• Note that, if the + B input exists when the microcontroller is off (not fixed at 0 V), power is supplied through

the pin, possibly causing the microcontroller to operate imperfectly.

• Note that, if the + B input exists when the power supply is turned on, power is supplied through the pin,

possibly resulting in a power-supply voltage at which a power-on reset does not work.

• Be careful not to let the + B input pin open.

• Note that the analog I/O pins (such as the LCD drive and comparator input pins) other than the A/D input pin

cannot input + B.

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

Vcc

Pch

Limiting

resistance

+ B input (0 V to 16 V)

Nch

R

*8: V^Ishould not exceed the specified ratings. However, if the maximum current to/from an input is limited by some

means with external components, the I^CLAMPrating supersedes the V^Irating.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

82

MB91350A Series

2. Recommended Operating Conditions

(V^SS= DA^VS= AV^SS= 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

3.6

V^CC

V

At normal operating

Power supply voltage

Analog power supply voltage

3.0

3.6

hold RAM status at stop

DA^VC

AV^CC

AVRH

Ta

V^SS− 0.3

AV^SS

V^SS+ 3.6

AV^CC

V

Analog reference voltage

Operating temperature

V

− 40

+ 85

°C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

83

MB91350A Series

3. DC Characteristics

Sym-

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Parameter

Conditions

Unit

Remarks

bol

Min

Typ

Max

Port 2, 3, 4,

5, 6, 9, A, B,

C

V^IH

⎯

V^CC× 0.65

⎯

V^CC− 0.3

V

Port 8, G, H,

I, M, N, O, P,

MD0, MD1,

MD2, INIT,

NMI

“H” level

input voltage

Hysteresis

input

V^IHS

⎯

V^CC× 0.8

⎯

V^CC− 0.3

V

Hysteresisinput

with stand

voltage of 5 V

V^IHST

Port J, K, L

⎯

V^CC× 0.8

⎯

5.25

V

Port 2, 3, 4,

5, 6, 9, A, B,

C

V^IL

V^SS

V^CC× 0.25

Port 8, G, H,

I, M, N, O, P,

MD0, MD1,

MD2, INIT,

NMI

“L” level

input voltage

V^ILS

⎯

V^SS

⎯

V^CC× 0.2

V^CC

V

Hysteresis input

Hysteresisinput

with stand

voltage of 5 V

V^ILST

Port J, K, L

V^SS

Port 2, 3, 4,

5, 6, 8, 9, A,

V^OHB, C, G, H, I,

J, K, M, N,

O, P

"H" level

output voltage

V^CC= 3.0 V

I^OH= − 4.0 mA

V^CC− 0.5

Port 2, 3, 4,

5, 6, 8, 9, A,

V^OL1B, C, G, H, I,

J, K, M, N,

V^CC= 3.0 V

I^OL= 4.0 mA

V^SS

− 5

25

⎯

50

0.4

+ 5

200

V

“L” level

output voltage

O, P

V^CC= 3.0 V

I^OL= 15.0 mA

V^OL2

Port L

Nch open-drain

Input leak

current

(High-Z

output Leak-

age current)

V^CC= 3.6 V

0<V^I<V^CC

I^LI

All input pin

µA

kΩ

Pull-up

resistance

setting pin V^CC= 3.6 V

INIT, Pull up V^I= 0.45 V

R^UP

(Continued)

84

MB91350A Series

(Continued)

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Sym-

bol

Parameter

Conditions

Unit

Remarks

Min

Typ

Max

Multiply by 4

CLKB : 50 MHz

f^C= 12.5 MHz

V^CC= 3.3 V

I^CC

⎯

160

220

mA CLKT : 25 MHz

When operating at

25 MHz

Sleep

f^C= 12.5 MHz

V^CC= 3.3 V

I^CCS

⎯

100

1

140

100

mA When operating at

25 MHz

Ta = + 25 °C

V^CC= 3.3 V

I^CCH

µA at stop

Power

supply

current

V^CC

Sub RUN

Ta = + 25 °C

f^C= 32.768 kHz

V^CC= 3.3 V

CLKB : 32.768 kHz

mA CLKT : 32.768 kHz

When operating at

32.768 kHz

I^CCL

⎯

0.3

3.0

Ta = + 25 °C

f^C= 32.768 kHz

V^CC= 3.3 V

Sub sleep

mA When operating at

32.768 kHz

I^CCLS

⎯

0.2

5

2.0

Ta = + 25 °C

f^C= 32.768 kHz

V^CC= 3.3 V

at watch mode

µA operating

I^CCT

120

(Main Off, STOP)

Other than

V^CC, V^SS,

AV^CC, AV^SS,

DA^VC, DA^VS

Input

capacitance

C^IH

⎯

5

15

pF

85

MB91350A Series

4. AC Characteristics

(1) Clock timing

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Sym-

bol

Parameter

Clock

Conditions

Unit

Remarks

Min

Typ

Max

X0

X1

Main PLL

f^C

10

⎯

12.5 MHz

frequency

(When operating at

max internal frequency

(50 MHz) = 12.5 MHz

self-oscillation with × 4

PLL)

⎯

X0

X1

Clock cycle time

t^C

80

10

⎯

100

25

ns

Main self-oscillation

Clock

frequency

X0

X1

f^C

⎯

MHz (frequency-halved

input)

f^CP

f^CPP

f^CPT

t^CP

2.94*

20

⎯

50

25

MHz CPU

When a minimum

value of 12.5 MHz

is input as the X0

clock frequency

and × 4 multiplica-

tion is set for the

PLL of the oscillator

circuit

Internal operating

clock frequency

⎯

MHz Peripheral

MHz External bus

ns CPU

25

340*

Internal operating

clock cycle time

t^CPP

t^CPT

40

ns Peripheral

ns External bus

40

Clock

frequency

X0A

X1A

f^C

t^C

⎯

30

28.6

40

32.768

35

kHz

SUB

self-oscillation

X0A

X1A

Clock cycle time

30.51 33.3

µs

Input clock palse

width

X0 P^WH/tc

X1 P^WL/tc

⎯

60

%

f^CP,

f^CPP,

f^CPT

Internal operating

clock frequency

⎯

2*

32

kHz

When a standard

value of 32.768 kHz

is input as the X0A

clock frequency

t^CP,

t^CPP,

t^CPT

Internal operating

clock cycle time

30.51

⎯

500*

µs

* : The values assume a gear cycle of 1/16.

86

MB91350A Series

• Conditions for measuring the clock timing ratings

tC

0.8 VCC

0.2 VCC

Output pin

C = 50 pF

PWL

PWH

tCR

tCF

• Operation Assurance Range

V^CC(V)

Operation Assurance Range (Ta = − 40°C to + 85°C)

f^CPPis represented by the shaded area.

3.6

3.0

fCP, fCPP

(MHz)

0

2.94

25

50

Internal clock

87

MB91350A Series

• External/internal clock setting range

Oscillation input clock f^C= 12.5 MHz

CPU (CLKB) :

(MHz)

f^CP

50

Peripheral

External bus(CLKT) :

fCPP,

fCPT

25

12.5

CPU :

4 : 4

2 : 2

1 : 2

Notes : • When the PLL is used, the external clock input must fall between 10.0 and 12.5 MHz.

• Set the PLL oscillation stabilization wait time longer than 454.5 µs. The internal clock gear setting should

not exceed the relevant value in the table in “(1) Clock timing ratings”.

88

MB91350A Series

(2)Clock output timing

Parameter

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Condi-

Symbol

Unit Remarks

tions

Min

Max

MCLK,

SYSCLK

Cycle time

t^CYC

t^CHCL

t^CLCH

t^CPT

⎯

ns *1

ns *2

ns *3

MCLK,

SYSCLK

SYSCLK ↑→ SYSCLK ↓

SYSCLK ↓→ SYSCLK ↑

⎯

t^CYC− 5

t^CYC+ 5

MCLK,

SYSCLK

*1 : t^CYCis the frequency of one clock cycle after gearing.

*2 : The following ratings are for the gear ratio set to × 1. For the ratings when the gear ratio is set to between 1/2,

1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation.

(1 / 2 × 1 / n ) × t^CYC− 10

*3 : The following rating are for the gear ratio set to × 1.

Note : t^CPTindicates the internal operating clock cycle time. See “(1) Clock timing”.

In the following AC ratings, MCLK is equivalent to SYSCLK.

t

CYC

t

CHCL

tCLCH

V

OH

VOH

MCLK

SYSCLK

V

OL

(3) Reset and hardware standby ratings

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Condi-

tions

Parameter

INIT input time

Symbol

Unit Remarks

Min

Max

t^C× 10

⎯

ns

(at power-on)

t^INTL

INIT

⎯

INIT input time

(other than at power-on)

t^C× 10

Note : t^Cindicates the clock cycle time. See “(1) Clock timing”.

tINTL

INIT

0.2 VCC

89

MB91350A Series

(4) Normal bus access read/write operation

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Remarks

Parameter

Symbol

Conditions

Unit

Min

3

Max

⎯

t^CSLCH

t^CSDLCH

t^CHCSH

AWRxL*³: W02 = 0

AWR0L : W02 = 1

ns

CS0 to CS3 setup

CS0 to CS3 hold

MCLK,

CS0 to CS3

− 3

3

⎯

t^CYC/2 + 6

MCLK,

A23 to A00

t^ASCH

t^ASWL

t^ASRL

t^CHAX

t^WHAX

t^RHAX

t^AVDV

3

⎯

ns

WR0, WR1,

A23 to A00

Address setup

Address hold

⎯

RD,

A23 to A00

3

⎯

t^CYC/2 + 6

⎯

MCLK,

A23 to A00

3

WR0, WR1,

A23 to A00

3

RD,

A23 to A00

3

⎯

Valid address →

Valid data input time

A23 to A00,

D31 to D16

*1

*2

⎯

3 / 2 × t^CYC− 15

WR0, WR1 delay time

t^CHWL

t^CHWH

⎯

6

ns

MCLK,

WR0, WR1

WR0, WR1 minimum

pulse width

t^WLWH

WR0, WR1

t^CYC− 5

⎯

ns

Data setup → WRx ↑

WRx ↑ → Data hold time

RD delay time

t^DSWH

t^WHDX

t^CHRL

t^CHRH

t^CYC

3

⎯

6

ns

WR0, WR1,

D31 to D16

⎯

MCLK,

RD

RD delay time

6

RD ↓ →

Valid data input time

t^RLDV

⎯

t^CYC− 10

ns *1

RD,

Data setup →RD ↑ Time

RD ↓ → Data hold time

RD minimum pulse width

AS setup

t^DSRH

t^RHDX

t^RLRH

D31 to D16

10

⎯

ns

0

RD

t^CYC− 5

⎯

t^ASLCH

t^CHASH

3

⎯

MCLK,

AS

AS hold

t^CYC/2 + 6

*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (t^CYC× the number of

cycles added for the delay) to this rating.

*2 : The following ratings are for the gear ratio set to × 1. For the ratings when the gear ratio is set to between 1/2 to

1/16, substitute 1/2 to 1/16 for n in the following equation.

Calculation expression: 3/(2n) × t^CYC− 15

*3 : AWRxL : Area Wait Register

Note : t^CYCindicates the cycle time. See “(2) Clock output timing”.

90

MB91350A Series

t

CYC

BA1

VOH

MCLK

tASLCH

tCHASH

VOH

AS

(LBA)

VOL

tCSLCH

tCHCSH

VOH

CS0 to CS3

VOL

tASCH

tCHAX

VOH

VOL

VOH

VOL

A23 to A00

tCHRH

tCHRL

tRLRH

RD

VOH

VOL

tASRL

tRHAX

tRHDX

tRLDV

tDSRH

tAVDV

D31 to D16

WR0, WR1

VOH

VOL

VOH

VOL

tCHWL

tCHWH

tWLWH

VOH

VOL

tASWL

tWHAX

tWHDX

tDSWH

VOH

VOL

VOH

VOL

D31 to D16

write

91

MB91350A Series

(5) Multiplex bus access read/write operation

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Condi-

tions

Parameter

Symbol

Unit Remarks

Min

Max

AD15 to AD0 Address

AUDI setup time

→ MCLK ↑

t^ASCH

3

⎯

ns

MCLK,

D31 to D16

MCLK ↑ →

AD15 to AD0 Address

AUDI Hold Time

t^CHAX

t^ASASH

t^ASHAX

3

12

t^CYC/2 + 6

ns

⎯

AD15 to AD0 Address

AUDI setup time → AS ↑

⎯

AS,

D31 to D16

AS ↑ →

AD15 to AD0 Address

AUDI Hold Time

t^CYC− 3

t^CYC+ 3

Notes : • This rating is not guaranteed when the CS→RD/WR, and setup delay setting by AWR: bit 1 is “0”.

• Beside This rating, normal bus interface ratings are applicable.

• t^CYCindicates the cycle time. See “(2) Clock output timing”.

t

CYC

BA1

VOH

MCLK

AS

VOH

VOL

tASASH

tASHAX

tCHAX

tASCH

VOH

VOL

VOH

VOL

D31 to D16

92

MB91350A Series

(6) Ready input timings

Parameter

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to +85°C)

Value

Symbol

Conditions

Unit Remarks

Min

Max

RDY setup time →

MCLK ↓

MCLK,

RDY

t^RDYS

t^RDYH

⎯

15

⎯

ns

MCLK ↑ →

RDY hold time

MCLK,

RDY

0

⎯

t

CYC

V

OH

V

OH

MCLK

V

OL

VOL

t

RDYS

t

RDYH

t

RDYS

t

RDYH

RDY

V

OH

VOH

with wait

V

OL

VOL

RDY

without wait

V

OH

VOH

V

OL

V

OL

93

MB91350A Series

(7) Hold timing

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

BRQ setup time

→ MCLK ↑

t^BRQS

t^BRQH

15

⎯

ns

MCLK,

BRQ

⎯

MCLK ↑ → BRQ

AUDI Hold Time

0

⎯

BGRNT delay time

t^CHBGL

t^CHBGH

t^CYC/2 − 6

t^CYC/2 + 6

ns

MCLK,

BGRNT

Pin floating →

BGRNT ↓ time

BGRNT,

⎯

t^XZBGL

t^BGHXV

t^CYC− 10

t^CYC+ 10

ns

D31 to D16,

A23 to A00,

CS3 to CS0*

BGRNT ↑ →

Pin valid time

* : These are applied to only the case that SREN bit of area select register (ACR) is set to “1”.

Notes : • It takes 1 cycle or more from when BRQ is captured until BGRNT changes.

• t^CYCindicates the cycle time. See “(2) Clock output timing”.

t

CYC

V

OH

V

OH

V

OH

V

OH

MCLK

BRQ

t

BRQS

t

BRQH

V

OL

V

OH

t

CHBGH

t

CHBGL

V

OH

BGRNT

V

OL

t

XZBGL

tBGHXV

D31 to D16,

A23 to A00,

CS3 to CS0 *

High-Z

* : These are applied to only the case that SREN bit of area select register (ACR) is set to “1”.

94

MB91350A Series

(8) UART, SIO timing

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

SCK0 to SCK7

8 t^CPP

⎯

ns

SCK ↓ →

BGRNT delay time

SCK0 to SCK7,

SO0 to SO7

− 80

100

60

+ 80

⎯

Internalshift

clock

mode

SCK0 to SCK7,

SI0 to SI7

Valid SI → SCK ↑

t^IVSH

ns

SCK ↑ → valid SIN hold

time

SCK0 to SCK7,

SI0 to SI7

tSHIX

⎯

Serial clock H Pulse Width

Serial clock L Pulse Width

t^SHSL

t^SLSH

SCK0 to SCK7

4 t^CPP

⎯

ns

SCK0 to SCK7,

SO0 to SO7

SCK ↓ → SO delay time

Valid SI → SCK ↑

t^SLOV

t^IVSH

tSHIX

External

shift clock

mode

⎯

60

150

⎯

ns

SCK0 to SCK7,

SI0 to SI7

SCK ↑ → valid SI hold

time

SCK0 to SCK7,

SI0 to SI7

⎯

Notes : • Above rating is for CLK synchronous mode.

• t^CPPindicates the peripheral clock cycle time. See “(1) Clock timing”.

• Internal shift clock mode

tSCYC

VOH

SCK0 to SCK7

VOL

tSLOV

VOH

VOL

SO0 to SO7

tIVSH

tSHIX

VOH

VOL

VOH

VOL

SI0 to SI7

• External shift clock mode

tSLSH

tSHSL

VOH

SCK0 to SCK7

SO0 to SO7

SI0 to SI7

VOL

tSLOV

VOH

VOL

tIVSH

tSHIX

VOH

VOL

VOH

VOL

95

MB91350A Series

(9) Free-run timer clock, PPG timer input timing

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

FRCK,

TRG0 to TRG5,

AIN0 to AIN1,

BIN0 to BIN1,

ZIN0 to ZIN1

t^TIWH

t^TIWL

Input pulse width

⎯

2 t^CPP

⎯

ns

Note : t^CPPindicates the peripheral clock cycle time. See “(1) Clock timing”.

tTIWL

tTIWH

(10) Trigger input timing

Parameter

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Symbol

Conditions

Unit Remarks

Min

Max

A/D activation trigger input

time

t^ATGX

t^INP

ATG

⎯

5 t^CPP

⎯

ns

input capture

input trigger

IN0 to IN3

5 t^CPP

⎯

Note : t^CPPindicates the peripheral clock cycle time. See “(1) Clock timing”.

t

ATGX, tINP

ATG,

IN0 to IN3

96

MB91350A Series

(11)DMA controller timing

• For edge detection (block/step transfer mode,burst transfer mode)

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

⎯

DREQ Input pulse width

t^DRWL

t^DSWH

DREQ 0 to DREQ2

DSTP 0 to DSTP2

2 t^CYC*

ns

⎯

* : t^CYCbecomes t^CPwhen f^CPTis greater than f^CP.

• For level detection (demand transfer mode)

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Condi-

tions

Parameter

Symbol

Unit Remarks

Min

15

Max

⎯

DREQ setup time

DREQ Hold Time

DSTP setup time

DSTP Hold Time

t^DRS

t^DRH

t^DSTPS

t^DSTPH

MCLK, DREQ 0 to DREQ2

MCLK, DSTP 0 to DSTP2

MCLK,DSTP 0 to DSTP2

ns

0.0

15

⎯

0.0

⎯

• Common operation mode

Parameter

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Value

Condi-

tions

Symbol

t^DALCH

Unit

Remarks

Min

3

Max

⎯

ns CS timing

ns FR30 compatible

ns CS timing

ns FR30 compatible

ns CS timing

ns FR30 compatible

ns CS timing

ns FR30 compatible

ns CS timing

ns FR30 compatible

ns CS timing

ns FR30 compatible

ns

AWRxL* :

W02 = 0

⎯

− 3

⎯

3

6

MCLK,

DACK 0 to

DACK2

⎯

AWR0L :

W02 = 1

DACK delay time

t^DADLCH

t^CHDAH

t^DELCH

6

t^CYC/2 + 6

⎯

6

⎯

AWR0L :

W02 = 0

⎯

− 3

⎯

12

6

MCLK,

DEOP 0 to

DEOP2

⎯

AWRxL* :

W02 = 1

DEOP delay time

t^DEDLCH

6

t^CYC/2 + 6

t^CHDEH

⎯

6

t^CHIRL

t^CHIRH

t^CHIWL

t^CHIWH

t^IRLIRH

t^IWLIWH

MCLK,

IORD

IORD delay time

IOWR delay time

6

ns

6

ns

MCLK,

IOWR

6

ns

IORD minimum pulse width

IOWR minimum pulse width

IORD

IOWR

⎯

ns

* : AWRxL: Area Wait Register.

Note : t^CYCindicates the cycle time. See “(2) Clock output timing”.

97

MB91350A Series

tCYC

VOH

MCLK

VOL

tDRWL

tDRS

tDRH

VOH

DREQ0 to DREQ2

VOL

tDSWH

tDSTPS

tDSTPH

VOH

DSTP0 to DSTP2

VOL

tCHIRL

tCHIWL

tCHIRH

tIRLIRH

VOH

IORD

VOL

tCHIWH

tIWLIWH

VOH

VOL

IOWR

RD,

WRn

Chip select

timing

tDALCH

tDADLCH

tCHDAH

VOH

DACK0 to DACK2

VOL

tDELCH

tDEDLCH

tCHDEH

VOH

DEOP0 to DEOP2

VOL

FR30 compatible

timing

tCHDAH

tDALCH

tDADLCH

VOH

VOL

DACK0 to DACK2

tCHDEH

tDELCH

tDEDLCH

VOL

DEOP0 to DEOP2

98

MB91350A Series

(12) I²C Timing

(V^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, Ta = − 40°C to + 85°C)

Fast-mode*⁴

Standard-mode

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

SCL clock frequency*⁴

f^SCL

0

100

0

400

kHz

Hold time (repeated) START condition

SDA↓→SCL↓

t^HDSTA

4.0

⎯

0.6

⎯

µs

“L” width of the SCL clock

“H” width of the SCL clock

t^LOW

t^HIGH

4.7

4.0

⎯

1.3

0.6

⎯

µs

Set-up time for a repeated START condition

SCL↑→SDA↓

t^SUSTA

t^HDDAT

t^SUDAT

t^SUSTO

t^BUS

4.7

0

⎯

3.45*²

⎯

0.6

0

⎯

0.9*³

⎯

µs

ns

µs

R = 1.0 kΩ,

C = 50 pF*¹

Data hold time

SCL↓→SDA↓↑

Data set-up time

SDA↓↑→SCL↑

250

4.0

4.7

100

0.6

1.3

Set-up time for STOP condition

SCL↑→SDA↑

⎯

Bus free time between a STOP and START

condition

⎯

*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (t^LOW) of the SCL signal.

*3 : A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement

t^SUDAT≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

SDA

tHDSTA

tBUS

tSUDAT

t^LOW

SCL

tHIGH

tHDSTA

tSUSTA

tHDDAT

tSUSTO

99

MB91350A Series

5. Electrical Characteristics for the A/D Converter

(V^CC= AV^CC= 3.0 V to 3.6 V, V^SS= DA^VS= AV^SS= 0 V, AVRH = 3.0 V to 3.6 V, Ta = − 40°C to + 85°C)

Value

Symbol

Parameter

Unit

Remarks

Min

⎯

Typ

⎯

Max

10

Resolution

⎯

bit

Total error*¹

− 5.0

− 3.5

− 2.5

⎯

+ 5.0

+ 3.5

+ 2.5

LSB

Nonlinear error*¹

Differential linear error*¹

⎯

AVcc = 3.3 V,

AVRH = 3.3 V

AN11

to AN0

Zero transition voltage*¹

⎯

LSB

AVRL − 2.0 AVRL + 1.0 AVRL + 6.0

AVRH − 5.5 AVRH + 1.5 AVRH + 3.0

AN11

to AN0

Full-transition voltage*¹

Conversion time

⎯

I^A

⎯

1.48*²

⎯

8

300

⎯

5

µs

mA

Analog power supply current

(analog + digital)

AV^CC

I^AH

⎯

µA At stop

AVRH = 3.0 V,

AVRL = 0.0 V

Reference power supply

current

(between AVRH and AVRL)

I^R

⎯

470

⎯

10

⎯

µA

AVRH

I^RH

⎯

µA At stop

AN11

to AN0

Analog input capacitance

Interchannel disparity

40

pF

AN11

to AN0

⎯

4

LSB

*1: Measured in the CPU sleep state

*2: When the peripheral resource clock frequency is 25.0 MHz, set the Conversion Time Setting Register (ADCT)

to a value equal to or greater than 5334^H.

Set each bit as follow :

Sampling time

: SAMP3 to SAMP0 ≥ 5^H

Conversion time a : CV03 to CV0 ≥ 3^H

Conversion time b : CV13 to CV0 ≥ 3^H

Conversion time c : CV23 to CV0 ≥ 4^H

100

MB91350A Series

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• Analog input circuit model

R

Comparator

Analog input

During Sampling : ON

C

R

C

MB91355A

MB91F355A

MB91F356B

0.18 kΩ (Max)

63.0 pF (Max)

39.0 pF (Max)

Note : The values are reference values.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

• The relationship between the external impedance and minimum sampling time

(External impedance = 0 kΩ to 100 kΩ)

(External impedance = 0 kΩ to 20 kΩ)

MB91F355A/MB91F356B

100

MB91F355A/MB91F356B

20

90

80

70

60

18

16

14

12

MB91355A

50

10

MB91355A

40

8

6

4

2

0

30

20

10

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [µs]

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• About errors

As |AVRH-AV^SS| becomes smaller, values of relative errors grow larger.

101

MB91350A Series

Definition of A/D Converter Terms

• Resolution

Analog variation that is recognized by an A/D converter.

• Linearity error

Zero transition point ( "0000000000” - “0000000001”) and full-scale transition point

Difference between the line connected (“1111111110” - “1111111111”) and actual conversion characteristics.

• Differential linear error

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

Linearity error

Actual conversion

characteristic

Differential linear error

3FFH

3FEH

3FDH

Actual conversion

characteristic

N + 1

{1 LSB' (N − 1) + VOT}

V^FST

Ideal characteristics

(measure-

N

ment value)

004H

003H

002H

001H

V^(N+1)T

(measurement

value)

V^NT

N − 1

N − 2

(measurement value)

Actual conversion

characteristic

Ideal characteristics

V^NT

(measurement value)

V^OT(measurement value)

Analog input

Actual conversion characteristic

AVSS

AVRH

AV^SS

AVRH

Analog input

V^NT− {1 LSB’ × (N − 1) + {V^OT}

Linear error in digital output N =

[LSB]

1 LSB’

V ^{(N + 1) T}− V^NT

Differential linear error in digital output N =

V^FST− V^OT

− 1 [LSB]

1 LSB’

1 LSB =

[V]

1022

V^OT: A voltage at which digital output transitions from (000)^Hto (001)^H.

V^FST: A voltage at which digital output transitions from (3FE)^Hto (3FF)^H.

V^NT: A voltage at which digital output transitions from (N - 1) to N.

102

MB91350A Series

• Total error

This error indicates the difference between actual and ideal values, including the zero transition error/full-scale

transition error/linearity error.

Total error

3FFH

1.5 LSB'

Actual conversion

characteristic

3FEH

3FDH

{1 LSB' (N − 1) + 0.5 LSB'}

004H

003H

002H

001H

V^NT

(measurement

value)

Actual

characteristics

Ideal characteristics

0.5 LSB'

AVSS

AVRH

Analog input

[V]

AVRH − AV^SS

1LS’ (Ideal value) 1 =

1024

V^NT− {1 LSB’ × (N − 1) × {0.5 LSB’}

Total error of digital output N =

1 LSB’

V^NT: A voltage at which digital output transitions from (N + 1) to (N).

V^OT’(Ideal value) = AV^SS+ {0.5 LSB’ [V]

V^FST’(Ideal value) = AVRH − 1.5 LSB’ [V]

103

MB91350A Series

6. Electrical Characteristics for the D/A Converter

(V^CC= DA^VC= 3.0 V = 3.6 V, V^SS= DA^VS= 0 V, Ta = − 40°C to + 85°C)

Value

Symbol

Parameter

Resolution

Unit

Remarks

Min Typ Max

⎯

− 2.0

− 1.0

⎯

8

bit

Nonlinear error

+ 2.0 LSB When the output is unloaded

+ 1.0 LSB When the output is unloaded

Differential linear error

⎯

0.6

3.0

⎯

µs

When load capacitance (C^L) = 20 pF

When load capacitance (C^L) = 100 pF

Convertion speed

⎯

DA0 to

DA2

Output high impedance

⎯

2.0

2.9

40

3.8

kΩ

µA

10 µs conversion when the output is

unloaded

⎯

Analog current

DA^VC

Input digital code

When fixed at 7A^Hor 85^H

I^ADA

⎯

460*

µA

I^ADAH

0.1

⎯

At power-down

* : This D/A converter varies in current consumption depending on each input digital code.

This rating indicates the current consumption when the digital code that maximizes current consumption is input.

104

MB91350A Series

■ FLASH MEMORY WRITE/ERASE CHARACTERISTICS

Value

Parameter

Condition

Unit

Remarks

Min

Typ

Max

Excludes 00^Hprogramming

prior erasure.

Sector erase time

Chip erase time

⎯

1

15

s

Ta = +25 °C,

V^CC= 3.3 V

Excludes 00^Hprogramming

prior erasure.

⎯

8

⎯

Half word (16-bit

width) writing time

Excludes system-level

overhead.

⎯

20

16

10,000

⎯

3,600

⎯

µs

Write/erase cycle

⎯

cycle

year

Flash data retention

time

Average

Ta = +85°C

⎯

*

*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85°C).

105

MB91350A Series

■ EXAMPLE CHARACTERISTICS

(1) “H” level output voltage

(2) “L” level output voltage

VOH - VCC

VOL1 - VCC

Ta = +25 °C

500

400

300

200

100

0

4

3

2

1

0

2.7

3.0

3.3

3.6

3.9

2.7

3.0

3.3

3.6

3.9

VCC [V]

(3) “L” level output voltage (Nch open-drain)

VOL2 - VCC

(4) Input leak current

ILI - VCC

Ta = +25 °C

6

4

500

400

300

200

100

0

2

0

−2

−4

−6

2.7

3.0

3.3

3.6

3.9

2.7

3.0

3.3

3.6

3.9

VCC [V]

(5) Pull-up resistance

RUP - VCC

Ta = +25 °C

200

160

120

80

40

0

2.7

3.0

3.3

3.6

3.9

VCC [V]

(Continued)

106

MB91350A Series

(6) Power supply current

(7) Power supply current

I

CC - VCC

Ta = +25 °C, fCP = 50 MHz,

CCP = fCPT = 25 MHz

ICC - fC

Ta = +25 °C, VCC = 3.3 V,

f

CP = 4 × fC (multiplied by 4)

f

300

250

200

150

100

50

300

250

200

150

100

50

0

2.7

3.0

3.3

3.6

3.9

1

10

100

V

CC [V]

f

C

[MHz]

(8) Power supply current at sleep

(9) Power supply current at sleep

I

CCS - VCC

Ta = +25 °C, fCP = 50 MHz,

CCP = fCPT = 25 MHz

ICCS - fC

Ta = +25 °C, VCC = 3.3 V,

f

CP = 4 × fC (multiplied by 4)

300

250

200

150

100

50

300

250

200

150

100

50

0

2.7

3.0

3.3

3.6

3.9

1

10

100

V

CC [V]

f

C

[MHz]

(10) Power supply current at stop

(11) Sub RUN power supply current

I

CCL - VCC

ICCH - VCC

Ta = +25 °C, fCP = 32 kHz,

Ta = +25 °C

100

80

60

40

20

0

f

CCP = fCPT = 32 kHz

500

400

300

200

100

0

−20

2.7

3.0

3.3

3.6

3.9

2.7

3.0

3.3

3.6

3.9

VCC [V]

V

CC [V]

(12) Sub sleep power supply current

(13) Watch mode power supply current

I

CCT - VCC

Ta = +25 °C, fCP = 32 kHz,

CCP = fCPT = 32 kHz

I

CCLS - VCC

Ta = +25 °C, fCP = 32 kHz,

f

CCP = fCPT = 32 kHz

f

500

400

300

200

100

0

100

80

60

40

20

0

−

20

2.7

3.0

3.3

3.6

3.9

3.0

3.3

3.6

3.9

V

CC [V]

V

CC [V]

(Continued)

107

MB91350A Series

(Continued)

(14) A/D converter power supply current

(15) A/D converter reference power supply voltage

IA - VCC

IR - VCC

Ta = +25 °C

1000

10

8

800

600

400

200

0

6

4

2

0

2.7

3.0

3.3

3.6

3.9

2.7

3.0

3.3

3.6

3.9

VCC [V]

(16) A/D converter power supply current at stop

(17) A/D converter reference power supply current at stop

IAH - VCC

IRH - VCC

Ta = +25 °C

20

10

0

10

0

−10

2.7

3.0

3.3

3.6

3.9

2.7

3.0

3.3

3.6

3.9

VCC [V]

(18) D/A converter power supply current

< per 1 channel >

(19) D/A converter power supply current at power down

IADA - VCC

IADAH - VCC

Ta = +25 °C

20

500

400

300

200

100

0

10

0

−10

2.7

3.0

3.3

3.6

3.9

2.7

3.0

3.3

3.6

3.9

VCC [V]

108

MB91350A Series

■ ORDERING INFORMATION

Part number

Package

Remarks

176-pin plastic LQFP

(FPT-176P-M02)

MB91F355APMT-002

MB91F356BPMT

MB91355APMT

Lead-free Package

176-pin plastic LQFP

(FPT-176P-M02)

Lead-free Package

176-pin plastic LQFP

(FPT-176P-M02)

176-pin plastic LQFP

(FPT-176P-M02)

MB91354APMT

109

MB91350A Series

■ PACKAGE DIMENSION

Note 1) * : Values do not include resin protrusion.

176-pin plastic LQFP

(FPT-176P-M02)

Resin protrusion is +0.25 (.010) Max (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

26.00±0.20(1.024±.008)SQ

* 24.00±0.10(.945±.004)SQ

0.145±0.055

(.006±.002)

132

89

133

88

0.08(.003)

Details of "A" part

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.10±0.10

(.004±.004)

(Stand off)

0˚~8˚

INDEX

0.25(.010)

0.50±0.20

176

45

(.020±.008)

"A"

0.60±0.15

(.024±.006)

1

44

LEAD No.

0.50(.020)

0.22±0.05

(.009±.002)

M

0.08(.003)

C

2003 FUJITSU LIMITED F176006S-c-4-6

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

110

MB91350A Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0505


型号：	MB91350A
厂家：	FUJITSU
描述：	32-Bit Proprietary Microcontroller 32位微控制器专用微控制器
文件：	总111页 (文件大小：1117K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB91350A [FUJITSU]

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