MB91F264BPFV-G-E1 [FUJITSU]
32-bit Proprietary Microcontroller CMOS; 32位微控制器的专有CMOS
| 型号： | MB91F264BPFV-G-E1 |
| 厂家： | 
FUJITSU |
| 描述： | 32-bit Proprietary Microcontroller CMOS |
| 文件： | 总60页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16507-1E
32-bit Proprietary Microcontroller
CMOS
FR60Lite MB91260B Series
MB91263B/MB91F264B
■ DESCRIPTION
The MB91260B series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications
which require high-speed processing.
The CPU is used the FR family and the compatibility of FR60Lite.
■ FEATURES
• FR60Lite CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method)
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
• Memory-to-memory transfer, bit handling, barrel shift instructions, etc : Instructions suitable for embedded
applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
(Continued)
■ PACKAGES
100-pin plastic QFP
100-pin plastic LQFP
(FTP-100P-M06)
(FTP-100P-M05)
MB91260B Series
(Continued)
• Register interlock function : Facilitates coding in assembler.
• Built-in multiplier with instruction-level support
• 32 bit multiplication with sign : 5 cycles
• 16 bit multiplication with sign : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• FR family instruction compatible
• Internal peripheral functions
• Capacity of internal ROM and ROM type
MASK ROM : 128 KB (MB91263B)
FLASH ROM : 256 KB (MB91F264B)
• Capacity of internal RAM : 8 KB
• A/D converter (sequential comparison type)
• Resolution : 10 bits : 2 ch × 2 units, 8 ch × 1 unit
• Conversion time : 1.2 µs (Minimum conversion time system clock at 33 MHz)
1.35 µs (Minimum conversion time system clock at 20 MHz)
• External interrupt input : 10 ch
• Bit search module (for REALOS)
Function for searching the MSB in each word for the first 1-to-0 inverted bit position
• UART (Full-duplex double buffer) : 3 ch
Selectable parity On/Off
Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
Internal timer for dedicated baud rate (U-Timer) on each channel
External clock can be used as transfer clock
Error detection function for parity, frame and overrun errors
• 8/16-bit PPG timer : 16 ch (at 8-bit) / 8 ch (at 16-bit)
• Reload timer : 3 ch (with cascade mode, without output of reload timer 0)
• Free-run timer : 1 ch
• PWC timer : 2 ch
• Input capture : 4 ch (interface with free-run timer)
• Output compare : 6 ch (interface with free-run timer)
• Waveform generator
Various waveforms which are generated by using output compare, 16-bit PPG timer 0 and 16-bit dead timer
• SUM of products macro (simple DSP)
RAM : instruction RAM
XRAM
YRAM
256 × 16-bit
64 × 16-bit
64 × 16-bit
Execution of 1 cycle product addition (16-bit × 16-bit + 40 bits)
Operation results are extracted rounded from 40 to 16 bits
• DMAC (DMA Controller) : 5 ch
Operation of transfer and activation by internal peripheral interrupts and software
• Watchdog timer
• Low Power Consumption Mode
Sleep/stop function
• Package : QFP-100, LQFP-100
• Technology : CMOS 0.35 µm
• Power supply : 1-power supply [Vcc = 4.0 V to 5.5 V]
2
MB91260B Series
■ PIN ASSIGNMENT
(TOP VIEW)
P23/SIN1
P24/SOT1
P25/SCK1
P26/INT6
P27/INT7
P50
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P02/PPG3
P01/PPG2
P00/PPG1
INIT
MD0
MD1
P51/TIN0
P52/TIN1
P53/TIN2
P54/INT0
P55/INT1
P56/INT2
P57/INT3
PG0/CKI/INT4
PG1/PPG0/INT5
PG2
MD2
NMI
9
P77/ADTG2
P76/ADTG1
P75/ADTG0
P74/PWI1
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
P73/PWI0
P72/DTTI
P71/TOT2
P70/TOT1
P63/INT9
P62/INT8
P61/IC3
P60/IC2
P37/IC1
P36/IC0
P35/RTO5
P34/RTO4
P33/RTO3
P32/RTO2
P31/RTO1
P30/RTO0
VCC
VSS
C
PG3/SIN2
PG4/SOT2
PG5/SCK2
P40
P41
P42
P43
P44
P45
P46
P47
(FPT-100-M06)
(Continued)
3
MB91260B Series
(Continued)
(TOP VIEW)
P25/SCK1
P26/INT6
P27/INT7
P50
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
INIT
MD0
MD1
MD2
P51/TIN0
P52/TIN1
P53/TIN2
P54/INT0
P55/INT1
P56/INT2
P57/INT3
PG0/CKI/INT4
PG1/PPG0/INT5
PG2
NMI
P77/ADTG2
P76/ADTG1
P75/ADTG0
P74/PWI1
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCC
P73/PWI0
P72/DTTI
P71/TOT2
P70/TOT1
P63/INT9
P62/INT8
P61/IC3
P60/IC2
P37/IC1
P36/IC0
P35/RTO5
P34/RTO4
P33/RTO3
P32/RTO2
VCC
VSS
C
PG3/SIN2
PG4/SOT2
PG5/SCK2
P40
P41
P42
P43
P44
(FPT-100-M05)
4
MB91260B Series
■ PIN DESCRIPTION
Pin no.
Pin Circuit
Description
name type
QFP LQFP
UART1 data input terminal.
SIN1
When use the terminal as data input of UART1, set the corresponding data
direction resister (DDR) to input.
1
99
D
General purpose input/output port.
This function is always valid.
P23
SOT1
P24
UART1 data output terminal.
This function becomes valid when data output of UART1 is set to enabled.
2
3
100
1
D
D
General purpose input/output port.
This function becomes valid when data output of UART1 is set to disabled.
UART1 clock input/output terminal.
This function becomes valid when clock input/output is set to enabled.
SCK1
P25
General purpose input/output port.
This function becomes valid when clock input/output is set to disabled.
External interrupt input terminal.
INT6
P26
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
4
2
E
General purpose input/output port.
This function is always valid.
External interrupt input terminal.
INT7
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
5
6
7
3
4
5
E
C
C
General purpose input/output port.
This function is always valid.
P27
P50
General purpose input/output port.
External trigger input terminal of reload timer 0.
When use the terminal as trigger input, set the corresponding data
direction resister (DDR) to input.
TIN0
P51
General purpose input/output port.
This function is always valid.
External trigger input terminal of reload timer 1.
When use the terminal as external trigger input, set the corresponding data
direction resister (DDR) to input.
TIN1
P52
8
6
C
General purpose input/output port.
This function is always valid.
(Continued)
5
MB91260B Series
Pin no.
Pin
name
Circuit
type
Description
QFP LQFP
External trigger input terminal of reload timer 2.
When use the terminal as external trigger input, set the corresponding data
direction resister (DDR) to input.
TIN2
P53
INT0
P54
INT1
P55
INT2
P56
INT3
P57
CKI
9
7
8
C
E
E
E
E
General purpose input/output port.
This function is always valid.
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
10
11
12
13
General purpose input/output port.
This function is always valid.
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
9
General purpose input/output port.
This function is always valid.
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
10
11
General purpose input/output port.
This function is always valid.
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
External clock input terminal for free-run timer.
When use the terminal as external clock input of free-run timer, set the
corresponding data direction resister (DDR) to input.
External interrupt input terminal.
When use the terminal as external interrupt input, set the corresponding data
direction resister (DDR) to input.
14
12
E
INT4
PG0
General purpose input/output port.
This function is always valid.
(Continued)
6
MB91260B Series
Pin no.
Pin Circuit
name type
Description
QFP LQFP
Output terminal of PPG timer 0.
This function becomes valid when output of PPG timer 0 is set to enabled.
PPG0
External interrupt input terminal.
15
13
INT5
E
When use the terminal as external input, output of PPG timer 0 is set to disabled,
and set the corresponding data direction resister (DDR) to input.
General purpose input/output port.
This function becomes valid when output of PPG temer 0 is set to disabled.
PG1
PG2
16
20
14
18
C
D
General purpose input/output port.
UART2 data input terminal.
When use the terminal as data input of UART2, set the corresponding data
direction resister (DDR) to input.
SIN2
General purpose input/output port.
This function is always valid.
PG3
SOT2
PG4
UART2 data output terminal.
This function becomes valid when data output of UART2 is set to enabled.
21
22
19
20
D
D
General purpose input/output port.
This function becomes valid when data output of UART2 is set to disabled.
UART2 clock input/output terminal.
This function becomes valid when clock input/output of UART2 is set to enabled.
SCK2
PG5
General purpose input/output port.
This function becomes valid when clock input/output of UART2 is set to disabled.
23
24
25
26
27
28
29
30
21
22
23
24
25
26
27
28
P40
P41
P42
P43
P44
P45
P46
P47
C
C
C
C
C
C
C
C
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
General purpose input/output port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR2 resister to
analog input.
AN11
PE1
31
29
G
General purpose input/output port.
This function becomes valid when set the corresponding AICR2 resister to port.
(Continued)
7
MB91260B Series
Pin no.
Pin Circuit
Description
name type
QFP LQFP
Analog input terminal of A/D converter.
AN10
PE0
AN9
PD1
AN8
PD0
AN7
PC7
AN6
PC6
AN5
PC5
AN4
PC4
AN3
PC3
This function becomes valid when set the corresponding AICR2 resister to
analog input.
32
38
39
41
42
43
44
45
30
36
37
39
40
41
42
43
G
G
G
G
G
G
G
G
General purpose input/output port.
This function becomes valid when set the corresponding AICR2 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR1 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR1 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR1 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR1 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
(Continued)
8
MB91260B Series
Pin no.
Pin
name
Circuit
type
Description
Analog input terminal of A/D converter.
QFP LQFP
AN2
PC2
AN1
PC1
AN0
PC0
This function becomes valid when set the corresponding AICR0 resister to
analog input.
46
47
48
44
45
46
G
G
G
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
Analog input terminal of A/D converter.
This function becomes valid when set the corresponding AICR0 resister to
analog input.
General purpose input/output port.
This function becomes valid when set the corresponding AICR0 resister to port.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
RTO0
P30
51
52
53
54
49
50
51
52
J
J
J
J
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
RTO1
P31
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
RTO2
P32
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
RTO3
P33
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
(Continued)
9
MB91260B Series
Pin no.
Pin Circuit
Description
name type
QFP LQFP
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
RTO4
P34
55
56
53
54
J
J
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator.
This function becomes valid when waveform generator output of multi-function
timer is set to enabled.
RTO5
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P35
IC0
Trigger input terminal of input capture 0.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
57
58
59
60
61
62
55
56
57
58
59
60
D
D
D
D
E
E
General purpose input/output port.
This function is always valid.
P36
IC1
Trigger input terminal of input capture 1.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
P37
IC2
Trigger input terminal of input capture 2.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
P60
IC3
Trigger input terminal of input capture 3.
When use the terminal as trigger input of input capture, set the corresponding data
direction resister (DDR) to input.
General purpose input/output port.
This function is always valid.
P61
INT8
P62
INT9
P63
External interrupt input terminal.
When use the terminal as external input, set the corresponding data direction
resister (DDR) to input.
General purpose input/output port.
This function is always valid.
External interrupt input terminal.
When use the terminal as external input, set the corresponding data direction
resister (DDR) to input.
General purpose input/output port.
This function is always valid.
(Continued)
10
MB91260B Series
Pin no.
Pin
name
Circuit
type
Description
Output terminal of reload timer 1.
QFP LQFP
TOT1
P70
This function becomes valid when reload timer output is set to enabled.
63
64
61
62
C
C
General purpose input/output port.
This function becomes valid when reload timer output is set to disabled.
Output terminal of reload timer 2.
This function becomes valid when reload timer output is set to enabled.
TOT2
P71
General purpose input/output port.
This function becomes valid when reload timer output is set to disabled.
Outputcontrol input terminal of waveform generator output terminal RTO0 to
RTO5 of multi-function timer.
This function becomes valid when DTTI input is set to enabled by waveform
generator of multi-function timer.
DTTI
65
63
D
General purpose input/output port.
This function is always valid.
P72
PWI0
P73
Pulse width counter input terminal of PWC timer 0.
This function becomes valid when pulse width counter input of PWC timer 0 is
set to enabled.
66
69
70
71
64
67
68
69
D
D
C
C
General purpose input/output port.
This function is always valid.
Pulse width counter input terminal of PWC timer 1.
This function becomes valid when pulse width counter input of PWC timer 1 is
set to enabled.
PWI1
P74
General purpose input/output port.
This function is always valid.
External trigger input terminal of A/D converter 0.
When use the external trigger as activation factor of A/D convertor, set the
corresponding data direction resister (DDR) to input.
ADTG0
P75
General purpose input/output port.
This function is always valid.
External trigger input terminal of A/D converter 1.
When use the external trigger as activation factor of A/D convertor, set the
corresponding data direction resister (DDR) to input.
ADTG1
P76
General purpose input/output port.
This function is always valid.
External trigger input terminal of A/D converter 2.
ADTG2
When use the external trigger as activation factor of A/D convertor, set the
corresponding data direction resister (DDR) to input.
72
73
70
71
C
H
General purpose input/output port.
This function is always valid.
P77
NMI
NMI (Non Maskable Interrupt) input terminal.
(Continued)
11
MB91260B Series
Pin no.
Pin Circuit
name type
Description
QFP LQFP
Mode terminal 2.
Set operating mode. Connect to VCC or VSS.
74
75
72
73
MD2
MD1
K
K
Mode terminal 1.
Set operating mode. Connect to VCC or VSS.
Mode terminal 0.
Set operating mode. Connect to VCC or VSS.
76
77
74
75
MD0
INIT
K
I
External reset input terminal.
Output terminal of PPG timer 1.
This function becomes valid when output of PPG timer 1 is set to enabled.
PPG1
78
79
80
81
82
83
84
76
77
78
79
80
81
82
C
C
C
C
C
C
C
General purpose input/output port.
This function becomes valid when output of PPG timer 1 is set to disabled.
P00
PPG2
P01
Output terminal of PPG timer 2.
This function becomes valid when output of PPG timer 2 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 2 is set to disabled.
Output terminal of PPG timer 3.
This function becomes valid when output of PPG timer 3 is set to enabled.
PPG3
P02
General purpose input/output port.
This function becomes valid when output of PPG timer 3 is set to disabled.
Output terminal of PPG timer 4.
This function becomes valid when output of PPG timer 4 is set to enabled.
PPG4
P03
General purpose input/output port.
This function becomes valid when output of PPG timer 4 is set to disabled.
Output terminal of PPG timer 5.
This function becomes valid when output of PPG timer 5 is set to enabled.
PPG5
P04
General purpose input/output port.
This function becomes valid when output of PPG timer 5 is set to disabled.
Output terminal of PPG timer 6.
This function becomes valid when output of PPG timer 6 is set to enabled.
PPG6
P05
General purpose input/output port.
This function becomes valid when output of PPG timer 6 is set to disabled.
Output terminal of PPG timer 7.
This function becomes valid when output of PPG timer 7 is set to enabled.
PPG7
P06
General purpose input/output port.
This function becomes valid when output of PPG timer 7 is set to disabled.
(Continued)
12
MB91260B Series
Pin no.
Pin
name
Circuit
type
Description
QFP LQFP
Output terminal of PPG timer 8.
This function becomes valid when output of PPG timer 8 is set to enabled.
PPG8
P07
85
86
87
88
89
90
91
83
84
85
86
87
88
89
C
C
C
C
C
C
C
General purpose input/output port.
This function becomes valid when output of PPG timer 8 is set to disabled.
Output terminal of PPG timer 9.
This function becomes valid when output of PPG timer 9 is set to enabled.
PPG9
P10
General purpose input/output port.
This function becomes valid when output of PPG timer 9 is set to disabled.
Output terminal of PPG timer 10.
This function becomes valid when output of PPG timer 10 is set to enabled.
PPG10
P11
General purpose input/output port.
This function becomes valid when output of PPG timer 10 is set to disabled.
Output terminal of PPG timer 11.
This function becomes valid when output of PPG timer 11 is set to enabled.
PPG11
P12
General purpose input/output port.
This function becomes valid when output of PPG timer 11 is set to disabled.
Output terminal of PPG timer 12.
This function becomes valid when output of PPG timer 12 is set to enabled.
PPG12
P13
General purpose input/output port.
This function becomes valid when output of PPG timer 12 is set to disabled.
Output terminal of PPG timer 13.
This function becomes valid when output of PPG timer 13 is set to enabled.
PPG13
P14
General purpose input/output port.
This function becomes valid when output of PPG timer 13 is set to disabled.
Output terminal of PPG timer 14.
This function becomes valid when output of PPG timer 14 is set to enabled.
PPG14
P15
General purpose input/output port.
This function becomes valid when output of PPG timer 14 is set to disabled.
94
95
92
93
X1
X0
A
A
Main clock oscillation output terminal.
Main clock oscillation input terminal.
Output terminal of PPG timer 15.
This function becomes valid when output of PPG timer 15 is set to enabled.
PPG15
96
97
94
95
C
C
General purpose input/output port.
This function becomes valid when output of PPG timer 15 is set to disabled.
P16
P17
General purpose input/output port.
UART0 data input terminal.
SIN0
P20
When use the terminal as data input of UART0, set the corresponding data
direction resister (DDR) to input.
98
96
D
General purpose input/output port.
This function is always valid.
(Continued)
13
MB91260B Series
(Continued)
Pin no.
Pin Circuit
Description
name type
QFP LQFP
UART0 data output terminal.
This function becomes valid when data output of UART0 is set to enabled.
SOT0
P21
99
97
98
D
D
General purpose input/output port.
This function becomes valid when data output of UART0 is set to disabled.
UART0 clock input/output terminal.
This function becomes valid when clock input/output of UART0 is set to enabled.
SCK0
P22
100
General purpose input/output port.
This function becomes valid when clock input/output of UART0 is set to disabled.
• Power supply and GND pins
Pin no.
Pin name
Description
QFP
LQFP
GND pins.
Apply equal potential to all of the pins.
18, 50, 68, 93
16, 48, 66, 91
Vss
Vcc
Power supply pin.
Apply equal potential to all of the pins.
17, 49, 67, 92
15, 47, 65, 90
35
33
36
40
37
19
34
33
31
34
38
35
17
32
AVcc
AVRH2
AVRH1
AVRH0
AVss
Analog power supply pin for A/D converter.
Analog reference power supply pin for A/D converter 2.
Analog reference power supply pin for A/D converter 1.
Analog reference power supply pin for A/D converter 0.
Analog GND pin for A/D converter.
C
Condencer connection pin for internal regulator.
Condencer connection pin for analog.
ACC
14
MB91260B Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
• Oscillation circuit
X1
• Oscillation feedback resistance :
approx. 1 MΩ
Clock input
A
X0
Standby control
• CMOS level output
• CMOS level input.
Pull-up control
• With standby control
• With Pull-up control
• Pull-up resistance value =
approx. 50 kΩ (Typ)
Digital output
Digital output
P-ch
P-ch
N-ch
C
R
• IOL = 4 mA
Digital input
Standby control
• CMOS level output
• CMOS level hysteresis input.
Pull-up control
Digital output
Digital output
• With standby control
• With Pull-up control
• Pull-up resistance value =
approx. 50 kΩ (Typ)
P-ch
P-ch
N-ch
D
R
• IOL = 4 mA
Digital input
Standby control
(Continued)
15
MB91260B Series
Type
Circuit type
Remarks
• CMOS level output
Pull-up control
Digital output
• CMOS level hysteresis input.
• Without standby control
• With Pull-up control
• Pull-up resistance value =
approx. 50 kΩ (Typ)
P-ch
P-ch
N-ch
E
Digital output
Digital input
R
• IOL = 4 mA
• Analog/CMOS level input/output pin
• CMOS level output
• CMOS level input.
Digital output
P-ch
(attached with standby control)
• Analog input
Digital output
(Analog input is enabled when AICR’s
corresponding bit is set to “1”.)
G
N-ch
R
Digital input
• IOL = 4 mA
Standby control
Analog input
• CMOS level hysteresis input.
• Without standby control
P-ch
N-ch
H
R
Digital input
(Continued)
16
MB91260B Series
(Continued)
Type
Circuit type
Remarks
• CMOS level hysteresis input.
P-ch
• With pull-up resistor
• Pull-up resistance value =
approx. 50 kΩ (Typ)
P-ch
N-ch
I
• Without standby control
R
Digital input
• CMOS level output
• CMOS level hysteresis input.
Digital output
Digital output
P-ch
• With standby control
• IOL = 12 mA
J
N-ch
R
Digital input
Standby control
• CMOS level input.
• Without standby control
P-ch
K
N-ch
R
Digital input
17
MB91260B Series
■ HANDLING DEVICES
• Preventing Latchup
Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output
pin or if an above-rating voltage is applied between VCC and VSS.
A latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an
element. When you use a CMOS IC, be very careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-
up or pull-down resistor.
• About power supply pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However you must connect the pins to external a same potential
power supply and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of
strobe signals caused by the rise in the ground level, and to conform to the total current rating.
The power pins should be connected to VCC and VSS of this device at the lowest possible impedance from the
current supply source.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near
this device.
• About Crystal oscillator circuit
Noise near the X0 and X1 pin may cause the device to malfunction.
Design the circuit board so that X0 and X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and XI pins surrounded by ground plane
because stable operation can be expected with such a layout.
• Mode pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS.
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low.
• Operation at start-up
Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up.
Also, in order to provide a delay while the oscillator circuit stabilize immediately after start-up, maintain the "L"
level input to the INIT pin for the required stabilization wait time.
(For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)
• About oscillation input at power on
When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.
18
MB91260B Series
• Caution operation during PLL clock mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this device, the device
may continue to operate at the free-run frequency of the PLL’s internal self-oscillating oscillator circuit.
Performance of this operation, however, cannot be guaranteed.
• External clock
When external clock is selected, the opposite phase clock to X0 pin must be supplied to X1 pin simultaneously.
If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So,
when STOP mode is specified, approximately 1 kΩ of resistance should be added externally to avoid the conclift
of output.
The following figure shows using an external clock.
X0
X1
MB91260B series
Using an external clock
• C pin
A bypass capacitor of approximately 0.1 µF should be connected the C pin for built-in regulator.
C
MB91260B series
0.1 µF
VSS
GND
• ACC pin
A capacitor of approximately 0.1 µF should be inserted between the ACC pin and the AVcc pin as this product
has built-in A/D convertor.
ACC
MB91260B series
0.1 µF
AVSS
19
MB91260B Series
• Clock control block
Take the oscillation stabilization wait time during Low level input to the INIT pin.
• Switch shared port function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR).
• Low Power Consumption Mode
(1) To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR:
or time-base counter control register) and be sure to use the following seaquence
(LDI
#value_of_standby, R0)
#_STCR, R12)
R0, @R12
: Value_of standby is write data to STCR.
: _STCR is address (481H) of STCR.
: Writing to standby control register (STCR)
: STCR read for synchronous standby
: Dummy re-read of STCR
(LDI
STB
LDUB
LDUB
NOP
NOP
NOP
NOP
NOP
@R12, R0
@R12, R0
: NOP × 5 for arrangement of timing
In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after
the standby returns.
(2) Please do not do the following when the monitor debugger is used.
• Break point setting for above instruction lines
• Step execution for above instruction lines
• Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
1. The following operations are performed when the instruction followed by a DIV0U/DIV0S instruction results
in: (a)acceptanceofauserinterruptorNMI, (b)stepexecution, or(c)abreakatadataeventoremulatormenu.
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger even has occurred.
(1) The PS register is updated in advance.
(2) An EIT handling routine (user interrupt, NMI) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).
20
MB91260B Series
• Watch dog timer
The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time.
The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from
being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on
operating programs until it resets the CPU.
As an exception, the watchdog timer defers a reset timing automatically under the condition in which the CPU
stops program execution.
21
MB91260B Series
■ NOTE ON DEBUGGER
• Step execution of RETI command
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed
repeatedly after step execution.
This will prevent the main routine and low-interrupt-level programs from being executed.
Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine
no longer needs debugging.
• Operand break
Do not apply a data event break to access to the area containing the address of a system stack pointer.
• Execution in an unused area of FLASH memory
Accidentally executing an instruction in an unused area of FLASH memory (with data placed at 0XFFFF) prevents
breaks from being accepted.
To prevent this, the code event address mask function of the debugger should be used to cause a break when
accessing an instruction in an unused area.
• Power-on debugging
All of the following three conditions must be satisfied when the power supply is turned off by power-on debugging.
(1) The time for the user power to fall from 0.9 VCC to 0.5 VCC is 25 µs or longer.
Note : In a dual-power system, VCC indicates the external I/O power supply voltage.
(2) CPU operating frequency must be higher than 1 MHz.
(3) During execution of user program
• Interrupt handler for NMI request (tool)
Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor
flag to be set only in response to a break request from the ICE is set, for example, by an adverse effect of noise
to the DSU pin while the ICE is not connected. Enable to use the ICE while adding this program.
Additional location
Next interrupt handler
Interrupt source
Interrupt number
Offset
: NMI request (tool)
: #13 (decimal) , 0DH (hexa decimal)
: 3C8H
Address TBR is default
: 000FFFC8H
Additional program
STM (R0, R1)
LDI
#B00H, R0;
#0, R1
: B00H is the address of DSU break factor register.
: Clear the break factor register.
LDI
STB
LDM
RETI
R1, @R0
(R0, R1)
22
MB91260B Series
■ BLOCK DIAGRAM
FR60 Lite CPU core
32
32
DMAC 5 ch
Bit search
SUM of products macro
Bus converter
ROM 128 KB/
FLASH 256 KB
RAM 8 KB
32
32 ↔ 16
Adapter
X0, X1
MD0 ~ MD2
INIT
Clock
control
16
Port I/F
PORT
Interrupt
controller
3 ch
TIN0 ~ TIN2
TOT1, TOT2
reload timer
10 ch
External interrupt
INT0 ~ INT9
NMI
2 ch
PWC timer
PWI0, PWI1
SIN0 ~ SIN2
SOT0 ~ SOT2
SCK0 ~ SCK2
3 ch
UART
8 ch
8/16 PPG timer
PPG0 ~ PPG15
3 ch
U timer
AVCC
Multi-function timer
Free-run timer 1 ch
ADTG0
AN0 ~ AN7
AVRH0
8 ch input
8/10 bit A/D-0
CKI
IC0 ~ IC3
Input capture 4 ch
ADTG1
AVRH1
AN8, AN9
2 ch input
8/10 bit A/D-1
Output compare 6 ch
RTO0 ~ RTO5
DTTI
ADTG2
AVRH2
AN10, AN11
2 ch input
8/10 bit A/D-2
Waveform generator
23
MB91260B Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the data size to be being accessed as follows.
→ byte data access
→ half word data access
→ word data access
: 000-0FFH
: 000-1FFH
: 000-3FFH
2. Memory Map
MB91F264B
MB91263B
Single chip mode
Single chip mode
0000 0000H
0000 0400H
0000 0000H
0000 0400H
Direct
addressing area
Direct
addressing area
I/O
I/O
I/O
I/O
Refer to I/O Map
Refer to I/O Map
0001 0000H
0003 E000H
0001 0000H
0003 E000H
Access
disallowed
Access
disallowed
Internal RAM
8 KB
Internal RAM
8 KB
0004 0000H
0004 0000H
Access
disallowed
Access
disallowed
000E 0000H
0010 0000H
000C 0000H
0010 0000H
Internal RAM
128 KB
Internal RAM
256 KB
Access
disallowed
Access
disallowed
FFFF FFFFH
FFFF FFFFH
Each mode is set depending on the mode vector fetched after the INIT signal is nagated.
(Refer to MODE SETTINGS for mode setting.)
24
MB91260B Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.
Mode Pins
Reset vector access
Mode name
Remarks
area
MD2 MD1 MD0
0
1
0
0
0
0
Internal ROM mode vector
Flash serial write mode
Internal
2. Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset source. User programs cannot set data to the mode register.
<Details of mode data description>
31
0
30
0
29
0
28
0
27
0
26
1
25
1
24
1
Operation mode setting bits
[bit31-24] Reserved bit
Be sure to set this bit to “00000111”.
Operation is not guaranteed when any value other than “00000111” is set.
3. Note
Mode data set in the mode vector must be placed as byte data at 0X000FFFF8.
Use the highest byte from bit 31 to bit 24 for placement as the FR family uses the big endian method for byte
endian.
15
16
8 7
0
31
24 23
Incorrect 0x000FFFF8
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
XXXXXXXX
Correct 0x000FFFF8
0x000FFFFC
Mode Data
XXXXXXXX
XXXXXXXX
Reset Vector
25
MB91260B Series
■ I/O MAP
This shows the location of the various peripheral resource registers in the memory space.
Register
Address
Block
+ 0
PDR0 [R/W]B PDR1 [R/W]B PDR2 [R/W]B PDR3 [R/W]B
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+ 1
+ 2
+ 3
000000H
Port data register
Read/write attribute, Access unit
(B : byte, H : half word, W : word)
Initial value after a reset
Register name (First-column register at address 4n; second-column
register at address 4n + 2)
Location of left-most register (When using word access, the register in
column 1 is in the MSB side of the data.)
Note : Initial values of register bits are represented as follows :
“ 1 ”
“ 0 ”
“ X ”
“ - ”
: Initial Value : “ 1 ”
: Initial Value : “ 0 ”
: Initial Value : “ undefined ”
: No physical register at this location
26
MB91260B Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
PDR0 [R/W] B
XXXXXXXX
PDR1 [R/W] B
XXXXXXXX
PDR2 [R/W] B
XXXXXXXX
PDR3 [R/W] B
XXXXXXXX
000000H
PDR4 [R/W] B
XXXXXXXX
PDR5 [R/W] B
XXXXXXXX
PDR6 [R/W] B
----XXXX
PDR7 [R/W] B
XXXXXXXX
000004H
000008H
00000CH
Port data register
PDRC [R/W] B
XXXXXXXX
PDRD [R/W] B
------XX
PDRE [R/W] B
------XX
PDRG [R/W] B
--XXXXXX
000010H
000014H
to
Reserved
00003CH
External interrupt
(INT0 to INT7)
EIRR0 [R/W] B, H, W
00000000
ENIR0 [R/W] B, H, W
00000000
ELVR0 [R/W] B, H, W
00000000 00000000
000040H
000044H
HRCL [R/W, R]
B, H, W
Delay interrupt/
Hold request
DICR [R/W] B, H, W
-------0
0--11111
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
000048H
00004CH
000050H
000054H
000058H
00005CH
Reload
timer 0
TMCSR0 [R/W, R] B, H, W
---00000 00000000
TMRLR1 [W] H, W
XXXXXXXX XXXXXXXX
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
Reload
timer 1
TMCSR1 [R/W, R] B, H, W
---00000 00000000
TMRLR2 [W] H, W
XXXXXXXX XXXXXXXX
TMR2 [R] H, W
XXXXXXXX XXXXXXXX
Reload
timer 2
TMCSR2 [R/W, R] B, H, W
---00000 00000000
SIDR0 [R]/SODR0[W]
SSR0 [R/W, R] B, H, W
00001000
SCR0 [R/W] B, H, W SMR0 [R/W, W] B, H, W
B, H, W
XXXXXXXX
000060H
000064H
000068H
00006CH
000070H
000074H
UART0
U-timer 0
UART1
00000100
00--0-0-
UTIM0 [R] H / UTIMR0 [W] H
00000000 00000000
DRCL0 [W] B
--------
UTIMC0 [R/W] B
0--00001
SIDR1 [R]/SODR1[W]
SSR1 [R/W, R] B, H, W
00001000
SCR1 [R/W] B, H, W SMR1 [R/W] B, H, W
B, H, W
XXXXXXXX
00000100
00--0-0-
UTIM1 [R] H / UTIMR1 [W] H
00000000 00000000
DRCL1 [W] B
--------
UTIMC1 [R/W] B
0--00001
U-timer 1
UART2
SIDR2 [R]/SODR2[W]
SSR2 [R/W, R] B, H, W
00001000
SCR2 [R/W] B, H, W SMR2 [R/W] B, H, W
B, H, W
XXXXXXXX
00000100
00--0-0-
UTIM2 [R] H / UTIMR2 [W] H
00000000 00000000
DRCL2 [W] B
--------
UTIMC2 [R/W] B
0--00001
U-timer 2
(Continued)
27
MB91260B Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
ADCH0 [R/W] B, H, W
XX000000
ADMD0 [R/W] B, H, W ADCD01 [R] B, H, W ADCD00 [R] B, H, W
000078H
00007CH
000080H
000084H
000088H
00008CH
A/D
converter 0/
AICR0
00001111
XXXXXXXX
XXXXXXXX
ADCS0 [R/W, W] B, H, W
00000X00
AICR0 [R/W] B, H, W
00000000
ADCH1 [R/W] B, H, W
XXXX0XX0
ADMD1 [R/W] B, H, W ADCD11 [R] B, H, W ADCD10 [R] B, H, W
A/D
converter 1/
AICR1
00001111
XXXXXXXX
XXXXXXXX
ADCS1 [R/W, W] B, H, W
00000X00
AICR1 [R/W] B, H, W
------00
ADCH2 [R/W] B, H, W
XXXX0XX0
ADMD2 [R/W] B, H, W ADCD21 [R] B, H, W ADCD20 [R] B, H, W
A/D
converter 2/
AICR2
00001111
XXXXXXXX
XXXXXXXX
ADCS2 [R/W, W] B, H, W
00000X00
AICR2 [R/W] B, H, W
------00
OCCPBH0, OCCPBL0[W]/
OCCPBH1, OCCPBL1[W]/
OCCPH0, OCCPL0[R] H, W
00000000 00000000
OCCPH1, OCCPL1 [R] H, W
00000000 00000000
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
OCCPBH2, OCCPBL2[W]/
OCCPH2, OCCPL2 [R] H, W
00000000 00000000
OCCPBH3, OCCPBL3[W]/
OCCPH3, OCCPL3 [R] H, W
00000000 00000000
OCCPBH4, OCCPBL4[W]/
OCCPH4, OCCPL4 [R] H, W
00000000 00000000
OCCPBH5, OCCPBL5[W]/
OCCPH5, OCCPL5 [R] H, W
00000000 00000000
OCU
OCSH3 [R/W]
B, H, W
X1100000
OCSL2 [R/W]
B, H, W
00001100
OCSH1 [R/W] B, H, W
OCSL0 [R/W] B, H, W
00001100
X1100000
OCMOD [R/W]
B, H, W
XX000000
OCSH5 [R/W] B, H, W
X1100000
OCSL4 [R/W] B, H, W
00001100
CPCLRBH, CPCLRBL[W]/
CPCLRH, CPCLRL[R] H, W
11111111 11111111
TCDTH, TCDTL [R/W] H, W
00000000 00000000
free-run
timer
ADTRGC [R/W]
B, H, W
XXXX0000
TCCSH [R/W] B, H, W
00000000
TCCSL [R/W] B, H, W
01000000
IPCPH0, IPCPL0 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH1, IPCPL1 [R] H, W
XXXXXXXX XXXXXXXX
0000ACH
0000B0H
IPCPH2, IPCPL2 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH3, IPCPL3 [R] H, W
XXXXXXXX XXXXXXXX
ICU
ICSL23 [R/W]
B, H, W
00000000
PICSH01 [W] B, H, W
PICSL01 [R/W] B, H, W ICSH23 [R] B, H, W
0000B4H
0000B8H
000000--
00000000
XXXXXX00
External interrupt
(INT8, INT9)
EIRR1 [R/W] B, H, W
------00
ENIR1 [R/W] B, H, W
------00
ELVR1 [R/W] B, H, W
-------- ----0000
(Continued)
28
MB91260B Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
TMRRH0, TMRRL0 [R/W] H, W
XXXXXXXX XXXXXXXX
TMRRH1, TMRRL1 [R/W] H, W
XXXXXXXX XXXXXXXX
0000BCH
0000C0H
0000C4H
0000C8H
0000CCH
0000D0H
TMRRH2, TMRRL2 [R/W] H, W
XXXXXXXX XXXXXXXX
Waveform
generator
DTCR0 [R/W] B, H, W DTCR1 [R/W] B, H, W DTCR2 [R/W] B, H, W
00000000
00000000
00000000
SIGCR1 [R/W] B, H, W
10000000
SIGCR2 [R/W] B, H, W
XXXXXXX1
ADCOMP0 [R/W] H, W
00000000 00000000
ADCOMP1 [R/W] H, W
00000000 00000000
A/D
COMP
ADCOMP2 [R/W] H, W
00000000 00000000
ADCOMPC [R/W] B, H, W
XXXXX000
0000D4H
to
0000DCH
Reserved
PWC
PWCSR0 [R/W, R] B, H, W
00000000 00000000
PWCR0 [R] H, W
00000000 00000000
0000E0H
0000E4H
0000E8H
PWCSR1 [R/W, R] B, H, W
00000000 00000000
PWCR1 [R] H, W
00000000 00000000
PDIVR0 [R/W] B, H, W
PDIVR1 [R/W] B, H, W
XXXXX000
XXXXX000
0000ECH
to
Reserved
000FCH
PRLH0 [R/W] B, H, W PRLL0 [R/W] B, H, W
PRLH1 [R/W] B, H, W
XXXXXXXX
PRLL1 [R/W] B, H, W
XXXXXXXX
000100H
000104H
000108H
00010CH
000110H
000114H
000118H
XXXXXXXX
PRLH2 [R/W] B, H, W PRLL2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
XXXXXXXX
PRLH3 [R/W] B, H, W
XXXXXXXX
PRLL3 [R/W] B, H, W
XXXXXXXX
PPGC0 [R/W] B, H, W PPGC1 [R/W] B, H, W PPGC2 [R/W] B, H, W
PPGC3 [R/W] B, H, W
0000000X
0000000X
PRLH4 [R/W] B, H, W PRLL4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
PRLH6 [R/W] B, H, W PRLL6 [R/W] B, H, W
XXXXXXXX XXXXXXXX
PPGC4 [R/W] B, H, W PPGC5 [R/W] B, H, W
0000000X 0000000X
PRLH8 [R/W] B, H, W PRLL8 [R/W] B, H, W
XXXXXXXX XXXXXXXX
0000000X
0000000X
PRLH5 [R/W] B, H, W
XXXXXXXX
PRLL5 [R/W] B, H, W
XXXXXXXX
PRLH7 [R/W] B, H, W
XXXXXXXX
PRLL7 [R/W] B, H, W
XXXXXXXX
PPG
PPGC6 [R/W] B, H,
W0000000X
PPGC7 [R/W] B, H, W
0000000X
PRLH9 [R/W] B, H, W
XXXXXXXX
PRLL9 [R/W] B, H, W
XXXXXXXX
PRLH11 [R/W]
B, H, W
XXXXXXXX
PRLH10 [R/W] B, H, W PRLL10 [R/W] B, H, W
PRLL11 [R/W] B, H, W
XXXXXXXX
00011CH
000120H
XXXXXXXX
XXXXXXXX
PPGC8 [R/W] B, H, W PPGC9 [R/W] B, H, W PPGC10 [R/W] B, H, W PPGC11 [R/W] B, H, W
0000000X 0000000X 0000000X 0000000X
(Continued)
29
MB91260B Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
PRLH12 [R/W] B, H, W PRLL12 [R/W] B, H, W PRLH13 [R/W] B, H, W PRLL13 [R/W] B, H, W
000124H
000128H
00012CH
000130H
000134H
XXXXXXXX
PRLH14 [R/W] B, H, W PRLL14 [R/W] B, H, W PRLH15 [R/W] B, H, W PRLL15 [R/W] B, H, W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PPGC12 [R/W] B, H, W PPGC13 [R/W] B, H, W PPGC14 [R/W] B, H, W PPGC15 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
PPG
0000000X
0000000X
0000000X
0000000X
TRG [R/W] B, H, W
00000000 00000000
GATEC [R/W] B, H, W
XXXXXX00
REVC [R/W] B, H, W
00000000 00000000
000138H
to
Reserved
0001FCH
DMACA0 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
DMACB0 [R/W] B, H, W
00000000 00000000 00000000 00000000
DMACA1 [R/W] B, H, W*1
00000000 00000000 00000000 00000000
DMACB1 [R/W] B, H, W
00000000 00000000 00000000 00000000
DMACA2 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
DMAC
DMACB2 [R/W] B, H, W
00000000 00000000 00000000 00000000
DMACA3 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
DMACB3 [R/W] B, H, W
00000000 00000000 00000000 00000000
DMACA4 [R/W] B, H, W *1
00000000 00000000 00000000 00000000
DMACB4 [R/W] B, H, W
00000000 00000000 00000000 00000000
000228H
to
00023CH
Reserved
DMAC
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
000240H
000244H
to
Reserved
000398H
(Continued)
30
MB91260B Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
00039CH
0003A0H
DSP-PC [R/W]
XXXXXXXX
DSP-CSR [R/W, R, W]
00000000
DSP-LY [R/W]
XXXXXXXX XXXXXXXX
DSP-OT0 [R]
XXXXXXXX XXXXXXXX
DSP-OT1 [R]
XXXXXXXX XXXXXXXX
0003A4H
DSP-OT2 [R]
XXXXXXXX XXXXXXXX
DSP-OT3 [R]
XXXXXXXX XXXXXXXX
Sum of
products
0003A8H
0003ACH
0003B0H
DSP-OT4 [R]
XXXXXXXX XXXXXXXX
DSP-OT5 [R]
XXXXXXXX XXXXXXXX
DSP-OT6 [R]
XXXXXXXX XXXXXXXX
DSP-OT7 [R]
XXXXXXXX XXXXXXXX
0003B4H
0003B8H
to
0003ECH
Reserved
Bit search
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F0H
0003F4H
0003F8H
0003FCH
000400H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDR0 [R/W] B
00000000
DDR1 [R/W] B
00000000
DDR2 [R/W] B
00000000
DDR3 [R/W] B
00000000
DDR4 [R/W] B
00000000
DDR5 [R/W] B
00000000
DDR6 [R/W] B
----0000
DDR7 [R/W] B
00000000
000404H
000408H
00040CH
Data
direction
register
DDRC [R/W] B
00000000
DDRD [R/W] B
------00
DDRE [R/W] B
------00
DDRG [R/W] B
--000000
000410H
000414H
to
Reserved
00041CH
PFR0 [R/W] B
00000000
PFR1 [R/W] B
-0000000
PFR2 [R/W] B
--00-00-
000420H
000424H
PFR7 [R/W] B
------00
Port
function
register
000428H
00042CH
PFRG [R/W] B
--00--0-
000430H
(Continued)
31
MB91260B Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
000434H
to
Reserved
00043CH
ICR00 [R/W, R] B, H, W ICR01 [R/W, R] B, H, W ICR02 [R/W, R] B, H, W ICR03 [R/W, R] B, H, W
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
----1111
ICR04 [R/W, R] B, H, W ICR05 [R/W, R] B, H, W ICR06 [R/W, R] B, H, W ICR07 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR08 [R/W, R] B, H, W ICR09 [R/W, R] B, H, W ICR10 [R/W, R] B, H, W ICR11 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR12 [R/W, R] B, H, W ICR13 [R/W, R] B, H, W ICR14 [R/W, R] B, H, W ICR15 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR16 [R/W, R] B, H, W ICR17 [R/W, R] B, H, W ICR18 [R/W, R] B, H, W ICR19 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR20 [R/W, R] B, H, W ICR21 [R/W, R] B, H, W ICR22 [R/W, R] B, H, W ICR23 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR24 [R/W, R] B, H, W ICR25 [R/W, R] B, H, W ICR26 [R/W, R] B, H, W ICR27 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR28 [R/W, R] B, H, W ICR29 [R/W, R] B, H, W ICR30 [R/W, R] B, H, W ICR31 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR32 [R/W, R] B, H, W ICR33 [R/W, R] B, H, W ICR34 [R/W, R] B, H, W ICR35 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR36 [R/W, R] B, H, W ICR37 [R/W, R] B, H, W ICR38 [R/W, R] B, H, W ICR39 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR40 [R/W, R] B, H, W ICR41 [R/W, R] B, H, W ICR42 [R/W, R] B, H, W ICR43 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR44 [R/W, R] B, H, W ICR45 [R/W, R] B, H, W ICR46 [R/W, R] B, H, W ICR47 [R/W, R] B, H, W
----1111
----1111
----1111
Interrupt
controller
----1111
----1111
----1111
----1111
000470H
to
Reserved
00047CH
RSRR [R/W] B, H, W
10000000
STCR [R/W] B, H, W
00110011
TBCR [R/W] B, H, W
00XXXX00
CTBR [W] B, H, W
XXXXXXXX
000480H
000484H
Clock
control
unit
CLKR [R/W] B, H, W
00000000
WPR [W] B, H, W
XXXXXXXX
DIVR0 [R/W] B, H, W
00000011
DIVR1 [R/W] B, H, W
00000000
000488H
to
Reserved
0005FCH
PCR0 [R/W] B
00000000
PCR1 [R/W] B
00000000
PCR2 [R/W] B
00000000
PCR3 [R/W] B
00------
000600H
000604H
PCR4 [R/W] B
00000000
PCR5 [R/W] B
00000000
PCR6 [R/W] B
----0000
PCR7 [R/W] B
00000000
Pull-up
Control
000608H
00060CH
(Continued)
32
MB91260B Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
PCRG [R/W] B
--000000
Pull-up
Control
000610H
000614H
to
Reserved
000FFCH
DMASA0 [R/W] W
00000000 00000000 00000000 00000000
001000H
001004H
001008H
00100CH
001010H
001014H
001018H
00101CH
001020H
001024H
DMADA0 [R/W] W
00000000 00000000 00000000 00000000
DMASA1 [R/W] W
00000000 00000000 00000000 00000000
DMADA1 [R/W] W
00000000 00000000 00000000 00000000
DMASA2 [R/W] W
00000000 00000000 00000000 00000000
DMAC
DMADA2 [R/W] W
00000000 00000000 00000000 00000000
DMASA3 [R/W] W
00000000 00000000 00000000 00000000
DMADA3 [R/W] W
00000000 00000000 00000000 00000000
DMASA4 [R/W] W
00000000 00000000 00000000 00000000
DMADA4 [R/W] W
00000000 00000000 00000000 00000000
001028H
to
006FFCH
Reserved
FLASH
FLCR [R/W]
0110X000
007000H
007004H
FLWC [R/W]
00000011*2
007008H
00700CH
007010H
007014H
to
Reserved
00BFFCH
(Continued)
33
MB91260B Series
(Continued)
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
00C000H
to
00C07CH
X-RAM (coefficient RAM) [R/W]
64 × 16 bit
00C080H
to
00C0FCH
Sum of
products
Y-RAM (variable RAM) [R/W]
64 × 16 bit
00C100H
to
00C2FCH
I-RAM (instruction RAM) [R/W]
256 × 16 bit
00C300H
to
Reserved
00FFFCH
*1 : The lower 16 bits (DTC[15: 0]) of DMACA0 to DMACA4 cannot be accessed in bytes.
*2 : The initial value of 1FLWC (7004H) is “00010011B” on EVA tool.
Writing “00000011B” on the evaluation model has no effect on its operation.
Notes : • Do not excute Read Modify Write instructions on registers having a write-only bit.
• Data is undefined in reseved or (-) area.
34
MB91260B Series
■ INTERRUPT VECTOR
Interrupt number
Interrupt
level
TBR default
address
Interrupt source
Offset
RN
10
0
16
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
Reset
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
000FFFC0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
Mode vector
1
System reserved
System reserved
System reserved
System reserved
System reserved
Coprocessor absent trap
Coprocessor error trap
INTE instruction
2
3
4
5
6
7
8
9
Instruction break exception
Operand break trap
Step trace trap
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NMI request (tool)
Undefined instruction exception
NMI request
15 (FH) fixed
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Reload timer 0
6
7
8
9
Reload timer 1
Reload timer 2
10
0
UART0(Reception completed)
UART0 (RX completed)
DTTI
3
DMAC0 (end, error)
DMAC1 (end, error)
DMAC2/3/4 (end, error)
(Continued)
35
MB91260B Series
Interrupt number
Interrupt
level
TBR default
address
Interrupt source
Offset
RN
10
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
16
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
UART1(Reception completed)
UART1 (RX completed)
UART2 (Reception completed)
UART2 (RX completed)
SUM of products macro
PPG0
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
378H
374H
370H
36CH
368H
364H
360H
35CH
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
000FFF78H
000FFF74H
000FFF70H
000FFF6CH
000FFF68H
000FFF64H
000FFF60H
000FFF5CH
000FFF58H
000FFF54H
000FFF50H
000FFF4CH
000FFF48H
000FFF44H
000FFF40H
000FFF3CH
000FFF38H
000FFF34H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
000FFF20H
000FFF1CH
000FFF18H
000FFF14H
000FFF10H
000FFF0CH
000FFF08H
000FFF04H
000FFF00H
000FFEFCH
000FFEF8H
1
4
2
5
PPG1
PPG2/3
PPG4/5/6/7
PPG8/9/10/11/12/13/14/15
External interrupt 8/9
Waveform0 (under flow)
Waveform1 (under flow)
Waveform2 (under flow)
Timebase timer overflow
Free-run timer (Compare clear)
Free-run timer (zero detection)
A/D0
A/D1
A/D2
PWC0 (measurment completed)
PWC1 (measurment completed)
PWC0 (overflow)
PWC1 (overflow)
ICU0 (capture)
ICU1 (capture)
ICU2/3 (capture)
OCU0/1 (match)
OCU2/3 (match)
OCU4/5 (match)
Delay interrupt source bit
System reserved (Used by REALOS)
System reserved (Used by REALOS)
(Continued)
36
MB91260B Series
(Continued)
Interrupt source
Interrupt number
Interrupt
level
TBR default
address
Offset
RN
10
66
67
68
69
70
71
72
73
74
75
76
77
78
79
16
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
000FFEF4H
000FFEF0H
000FFEECH
000FFEE8H
000FFEE4H
000FFEE0H
000FFEDCH
000FFED8H
000FFED4H
000FFED0H
000FFECCH
000FFEC8H
000FFEC4H
000FFEC0H
80
to
50
to
2BCH
to
000FFEBCH
to
Used by INT instruction
255
FF
000H
000FFC00H
37
MB91260B Series
■ PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows.
• Input enabled
• Indicates that the input function can be used.
• Input 0 fixed
• Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released.
• Output Hi-Z
• Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving.
• Output is maintained.
• Indicates the output in the output state existing immediately before this mode is established.
• If the device enters this mode with an internal output peripheral operating or while serving as an output port,
the output is performed by the internal peripheral or the port output is maintained, respectively.
• State existing immediately before is maintained.
• When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.
38
MB91260B Series
• List of pin status (single chip mode)
Pin no.
At initializing
INIT = L*1 INIT = H*2
At Stop mode
At sleep
Pin name Function
mode
QFP
LQFP
99
Hi-Z = 0
Hi-Z = 1
1
2
3
P23
P24
P25
SIN1
SOT1
SCK1
Retention
of the
Retention
of the
Output Hi-Z/
100
1
immediately immediately Input 0 fixed
prior state
prior state
Input
enabled
Input
enabled
Input
enabled
4, 5
2, 3
P26, P27 INT6, INT7
Retention
of the
Retention
of the
Output Hi-Z/
6 to 9
4 to 7 P50 to P53
Ports
immediately immediately Input 0 fixed
prior state
prior state
10
11
12
13
14
15
16
20
21
22
8
P54
P55
P56
P57
PG0
PG1
PG2
PG3
PG4
PG5
INT0
INT1
9
10
11
12
13
14
18
19
20
INT2
Input
enabled
Input
enabled
Input
enabled
INT3
CKI/INT4
PPG0/INT5
Ports
Output Hi-Z/ Output Hi-Z/
Input
Input
disabled
disabled
SIN2
SOT2
SCK2
Ports
23 to 30 21 to 28 P40 to P47
AN11,
AN10
Retention
of the
Retention
of the
31, 32 29, 30 PE1, PE0
Output Hi-Z/
immediately immediately Input 0 fixed
38, 39 36, 37 PD1, PD0 AN9, AN8
PC7 to
prior state
prior state
41 to 48 39 to 46
AN7 to AN0
PC0
RTO0 to
RTO5
51 to 56 49 to 54 P30 to P35
57, 58 55, 56 P36, P37
59, 60 57, 58 P60, P61
IC0, IC1
IC2, IC3
Input
enabled
Input
enabled
Input
enabled
61, 62 59, 60 P62, P63 INT8, INT9
(Continued)
39
MB91260B Series
(Continued)
P : Selection of general purpose port, F : Selection of specified function
Pin no.
At initializing
At Stop mode
Pin
name
At sleep
mode
Function
1
2
QFP LQFP
INIT =
Hi-Z = 0
Hi-Z = 1
L*
INIT = H*
TOT1,
TOT2
63, 64 61, 62 P70, P71
65
66
69
70
71
72
63
64
67
68
69
70
P72
P73
P74
P75
P76
P77
DTTI
PWI0
Retention
of the
Retention
of the
Output Hi-Z/ Output Hi-Z/
Output Hi-Z/
PWI1
input disabled input disabled immediately immediately Input 0 fixed
prior state
prior state
ADTG0
ADTG1
ADTG2
Input
enabled
Input
enabled
Input
enabled
73
71
NMI
NMI
Input enabled Input enabled
78
79
80
81
82
83
84
85
86
87
88
89
90
91
96
97
98
99
100
76
77
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
Ports
Retention
of the
Retention
of the
Output Hi-Z/
output Hi-Z/
Ouptut Hi-Z/
input disabled input disabled immediately immediately input 0 fixed
prior state prior state
SIN0
SOT0
SCK0
*1 : INIT = L : Indicates the pin status with INIT remaining at the “L” level.
*2 : INIT = H : Indicates the pin status existing immediately after INIT transition from “L” to “H” level.
40
MB91260B Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0 V)
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VSS + 6.0
VSS + 6.0
VSS + 6.0
VCC + 0.3
AVcc + 0.3
VCC + 0.3
10
Power supply voltage
Analog power supply voltage
Analog reference voltage
Input voltage
VCC
AVCC
AVRH
VI
VSS − 0.5
VSS − 0.5
VSS − 0.5
VSS − 0.3
VSS − 0.3
VSS − 0.3
V
V
V
V
V
V
*1
*1
Analog pin input voltage
Output voltage
VIA
VO
L level maximum output current
L level average output current
IOL
mA *2
mA *3
IOLAV
8
L level total maximum output
current
ΣIOL
100
50
mA
L level total average output
current
ΣIOLAV
mA *4
H level maximum output
current
IOH
− 10
− 4
mA *2
mA *3
mA
H level average output current
IOHAV
ΣIOH
H level total maximum output
current
− 50
H level total average output
current
ΣIOHAV
− 20
mA *4
600
600
360
FLASH product
Power consumption
PD
mW MASK product Ta ≤ + 85 °C
MASK product Ta ≤ + 105 °C *5
MASK product (at single chip
operating)
− 40
+ 105
°C
Operating temperature
Storage temperature
Ta
FLASH product (at single chip
operating)
− 40
− 55
+ 85
°C
Tstg
125
°C
*1 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on.
Be careful not to let AVCC exceed VCC, for example, when the power is turned on.
*2 : The maximum output current is the peak value for a single pin.
*3 : The average output current is the average current for a single pin over a period of 100 ms.
*4 : The total average output current is the average current for all pins over a period of 100 ms.
*5 : For use at Ta = +105 °C, lower the operating frequency to reduce power consumption.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
41
MB91260B Series
2. Recommended Operating Conditions
(Vss = AVss = 0 V)
Remarks
Value
Parameter
Symbol
Unit
Min
Max
Power supply voltage
VCC
AVCC
4.0
5.5
V
V
At normal operating
Analog power supply
voltage
VSS + 4.0
VSS + 5.5
AVRH0
AVSS
AVSS
AVSS
AVCC
AVCC
AVCC
V
V
V
For A/D converter 0
For A/D converter 1
For A/D converter 2
Analog reference voltage AVRH1
AVRH2
MASK product (at single chip
operation)
− 40
− 40
+ 105
+ 85
°C
°C
Operating temperature
Ta
FLASH product (at single chip
operation)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
42
MB91260B Series
3. DC Characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Value
Sym
Parameter
bol
Pin
Conditions
Unit Remarks
Min
Typ
Max
Other than hyster-
esis input pin
VIH
VIHS
VIL
0.8 × Vcc
Vcc
V
V
"H" level input
voltage
Hysteresis input
pin
Vcc − 0.4
Vss
Vcc
Other than hyster-
esis input pin
0.2 × Vcc
Vss + 0.4
V
Input Low
Voltage
Hysteresis input
pin
VILS
VOH
Vss
V
Other than port 30 VCC = 5.0 V,
to 35
Vcc − 0.5
Vcc − 0.7
V
IOH = 4.0 mA
"H" level output
voltage
VCC = 5.0 V,
IOH = 8.0 mA
VOH2 Port 30 to 35
V
Other than port 30 VCC = 5.0 V,
VOL
0.4
0.6
5
V
to 35
IOL = 4.0 mA
Output Low
Voltage
VCC = 5.0 V,
IOL = 12 mA
VOL2 Port 30 to 35
V
VCC = 5.0 V,
VSS ≤ VI ≤ VCC
Input leak current
ILI
− 5
µA
kΩ
INIT,
Pull-up pin
Pullup resistance RPULL
50
ICC
VCC
VCC = 5.0 V, 33 MHz
VCC = 5.0 V, 33 MHz
90
60
100
80
mA
Power supply
current
ICCS VCC
ICCH VCC
mA At SLEEP
VCC = 5.0 V,
Ta = + 25 °C
300
µA At STOP
Other than VCC,
CIN VSS, AVCC, AVSS,
AVRH0, 1, 2
Input
capacitance
10
pF
43
MB91260B Series
4. FLASH MEMORY write/erase characteristics
Value
Typ
Parameter
Conditions
Unit
Remarks
Min
Max
Ta = + 25 °C,
Vcc = 5.0 V
Not including time for internal
writing before deletion.
Sector erase time
Chip erase time
Byte write time
1
10
8
15
s
s
Ta = + 25 °C,
Vcc = 5.0 V
Not including time for internal
writing before deletion.
Ta = + 25 °C,
Vcc = 5.0 V
Not including system-level
overhead time.
3,600
µs
Ta = + 25 °C,
Vcc = 5.0 V
Not including system-level
overhead time.
Chip write time
2.1
s
Erase/write cycle
10,000
Cycle
44
MB91260B Series
5. AC Characteristics
(1) Clock Timing Ratings
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Value
Typ
Sym
Parameter
bol
Pin
Conditions
Unit
Remarks
Min
Max
X0
X1
For using the PLL within
the self-oscillation enabled
range, set the multiplier for
the internal clock not to let
the operating frequency
exceed 33 MHz.
Clock frequency
Clock cycle time
fC
3.6
12
MHz
X0
X1
tC
83.3
278
ns
fCP
fCPP
tCP
When 4.125 MHz is 2.06*
33
33
MHz CPU
Internaloperating
clock frequency
input as the X0
clock frequency and
2.06*
MHz Peripheral
ns CPU
30.3
30.3
485*
×8 multiplication is
set for the PLL of
the oscillator circuit.
Internaloperating
clock cycle time
tCPP
485*
ns Peripheral
* : The values assume a gear cycle of 1/16.
• Conditions for measuring the clock timing ratings
tC
0.8 VCC
0.2 VCC
Output pin
C = 50 pF
PWL
PWH
tCR
tCF
45
MB91260B Series
• Operation Assurance Range
VCC (V)
5.5
4.0
fCP / fCPP
(MHz)
0
0.25
33
Internal clock
• Internal clock setting range
(MHz)
33
CPU (CLKB) :
Peripheral (CLKP) :
16.5
Oscillation input clock fC = 4.192 MHz
4.125
(PLL multiplied by 8)
CPU : Divided ratio for
peripherals.
8 : 8
4 : 4
1 : 1
Notes : • Oscillation stabilization time of PLL > 600 µs
• The internal clock gear setting should be within the value shown in clock timing ratings table.
46
MB91260B Series
(2) Reset Input
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Value
Sym-
bol
Condi-
tions
Parameter
Pin
Unit Remarks
Max
Min
Init input time
(at power-on and STOP mode)
Oscillation time of
oscillator + tC × 10
ns
ns
tINTL
INIT
Init input time
(other than the above)
tC × 10
tINTL
INIT
0.2 VCC
47
MB91260B Series
(3) UART Timing
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Conditions
Unit Remarks
Min
Max
Serial clock cycle time
tSCYC
tSLOV
SCK0 to SCK2
8 tCYCP
ns
ns
SCK0 to SCK2,
SOT0 to SOT2
SCK ↓ → SOT delay time
− 80
100
60
80
Internalshift
clock mode
SCK0 to SCK2,
SIN0 to SIN2
Valid SIN → SCK ↑
tIVSH
ns
ns
SCK0 to SCK2,
SIN0 to SIN2
SCK ↑ → valid SIN hold time
tSHIX
Serial clock H pulse width
Serial clock L pulse width
tSHSL
SCK0 to SCK2
SCK0 to SCK2
4 tCYCP
4 tCYCP
ns
ns
tSLSH
SCK0 to SCK2,
SOT0 to SOT2
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
External
shift clock
mode
150
ns
ns
ns
SCK0 to SCK2,
SIN0 to SIN2
60
60
SCK0 to SCK2,
SIN0 to SIN2
SCK ↑ → valid SIN hold time
Notes : • There are the AC ratings for CLK synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
48
MB91260B Series
• Internal shift clock mode
tSCYC
VOH
SCK0 to SCK2
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT2
SIN0 to SIN2
tIVSH
tSHIX
VOH
VOL
VOH
VOL
• External shift clock mode
tSLSH
tSHSL
VOH
VOL
VOL
VOL
SCK0 to SCK2
SOT0 to SOT2
tSLOV
VOH
VOL
tIVSH
tSHIX
VOH
VOL
VOH
VOL
SIN0 to SIN2
49
MB91260B Series
(4) Free-run Timer Clock, PWC Input and Reload Timer Trigger Timing
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Conditions
Unit
Remarks
Min
Max
CKI
PWI0, PWI1
TIN0 to TIN2
tTIWH
tTIWL
Input pulse width
4 tCYCP
ns
Note : tCYCP indicates the peripheral clock cycle time.
tTIWL
tTIWH
50
MB91260B Series
(5) Trigger Input Timing
Parameter
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Value
Symbol
Pin
Conditions
Unit Remarks
Max
Min
Input capture
trigger input
tINP
IC0 to IC3
5 tCYCP
5 tCYCP
ns
ns
ADTG0 to
ADTG2
A/D activation trigger input
tATGX
Note : tCYCP indicates the peripheral clock cycle time.
tATGX, tINP
IC0 to IC3
ADTG0 to ADTG2
51
MB91260B Series
6. Electrical Characteristics for the A/D Converter
Sym-
(VCC = AVcc = 5.0 V, VSS = AVSS = 0 V)
Value
Typ
Parameter
Pin
Unit
Remarks
bol
Min
Max
10
Resolution
bit
Total error*1
− 4
4
LSB
LSB
Linearity error*
− 3.5
3.5
Differential linearity
error*1
− 3
3
LSB
At AVRHn*4 = 5.0 V
AN0 to
AN11
Zero transition voltage*1
VOT
AVss − 3.5 AVss + 0.5 AVss + 4.5 LSB
AN0 to
AN11
AVRH −
AVRH −
AVRH +
Full transition voltage*1
Conversion time
VFST
LSB
µS
5.5
1.5
2.5
1.2*2
Analog port
Input current
AN0 to
AN11
IAIN
10
µA
AN0 to
AN11
Analog input voltage
VAIN
AVss
AVss
AVRH
AVcc
V
V
Reference voltage
AVRHn
Analog power supply
current
(analog + digital)
IA
2
1
mA Per 1 unit
AVcc
IAH*3
100
µA Per 1 unit
Per 1 unit
mA AVRHn*4 = 5.0 V,
at AVss = 0 V
reference power supply
current
(between AVRH and
AVSS)
IR
AVRHn
per 1 unit
µA
IRH*3
100
4
at STOP
Analog input capacitance
Inter-channel disparity
10
pF
AN0 to
AN11
LSB
*1 : Measured in the CPU sleep state
*2 : Vcc = AVcc = 5.0 V, machine clock at 33 MHz
*3 : The current when the CPU is in stop mode and the A/D converter is not operating (at Vcc= AVcc = AVRHn = 5.0 V)
*4: AVRHn = AVRH0, AVRH1, AVRH2
Note : The above does not guarantee the inter-unit accuracy.
Set the output impedance of the external circuit ≤ 2 kΩ.
52
MB91260B Series
Definition of A/D Converter Terms
• Resolution : Analog variation that is recognized by an A/D converter.
• Linearity error : Zero transition point (00 0000 0000 ←→ 00 0000 0001) and full-scale transition point.
Difference between the line connected (11 1111 1110 ←→ 11 1111 1111) and actual conversion character-
istics.
• Differential linearity error : Deviation of input voltage, that is required for changing output code by 1 LSB, from
an ideal value.
• Total error : This error indicates the difference between actual and ideal values, including the zero transition
error/full-scale transition error/linearity error.
Total error
3FF
1.5 LSB'
Actual conversion
characteristics
3FE
3FD
{1 LSB' (N − 1) + 0.5 LSB'}
004
003
002
001
VNT
(measurement value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB'
AVSS
AVRH
Analog input
AVRH − AVSS
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1LSB’
(Ideal value)
=
[V] Total error of digital output N
=
1024
1 LSB’
VOT’
(Ideal value)
= AVSS + 0.5 LSB’ [V]
VFST’
(Ideal value)
= AVRH − 1.5 LSB’ [V] VNT : A voltage at which digital output transitions from (N + 1) to N.
(Continued)
53
MB91260B Series
(Continued)
Linearity error
Differential linear error
3FF
Actual conversion
Actual conversion
characteristics
characteristics
3FE
N + 1
{1 LSB (N − 1) + VOT}
Ideal
characteristics
3FD
VFST
(measurement
value)
N
004
VNT
(measurement value)
003
002
001
N − 1
N − 2
VFST
(measurement
value)
Actual conversion
characteristics
Ideal characteristics
VNT
(measurement value)
Actual conversion
characteristics
V0T (measurement Value)
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
VNT − { 1 LSB × (N − 1) + VOT }
Linearity error in digital output N
=
=
=
[LSB]
1 LSB
V (N + 1) T − VNT
Differential linearity error in digital output
N
− 1 [LSB]
1 LSB
VFST − VOT
1 LSB
[V]
1022
VOT : A voltage at which digital output transitions from 000H to 001H.
VFST : A voltage at which digital output transitions from 3FEH to 3FFH .
54
MB91260B Series
■ EXAMPLE CHARACTERISTICS
“L” Level Output Voltage vs.
Power Supply Voltage
“H” Level Output Voltage vs.
Power Supply Voltage
6
400
350
300
250
200
150
100
50
5
4
3
2
1
0
4.0
4.5
5.0
5.5
0
4.0
VCC (V)
4.5
5.0
5.5
VCC (V)
Pull-up Resistor vs. Power Supply Voltage
Power Supply Current vs. Power Supply Voltage
80
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VCC (V)
VCC (V)
Power Supply Current vs. Internal Operation Frequency (MB91263)
100
90
80
70
60
50
40
30
20
10
0
4.0 V
4.5 V
5.0 V
5.5 V
15
20
25
30
35
Internal operation frequency [MHz]
(Continued)
55
MB91260B Series
(Continued)
Power Supply Current (at sleep) vs.
Power Supply Voltageage
Power Supply Current (at stop) vs.
Power Supply Voltage
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VCC (V)
VCC (V)
A/D Conversion Block Per 1 Unit (33 MHz)
Reference Voltage Supplying Current vs.
Power Supply Voltage
A/D Conversion Block Per 1 Unit (33 MHz)
Analog Power Supply Current vs.
Power Supply Voltage
2
1.5
1
1.0
0.8
0.6
0.4
0.2
0.0
0.5
0
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VCC (V)
VCC (V)
56
MB91260B Series
■ ORDERING INFORMATION
Part number
MB91F264BPF-G
Package
Remarks
Lead-free Package
Lead-free Package
Lead-free Package
Lead-free Package
100-pin plastic QFP
(FPT-100P-M06)
MB91F264BPF-G-E1
MB91F264BPFV-G
100-pin plastic LQFP
(FPT-100P-M05)
MB91F264BPFV-G-E1
MB91263BPF-G-xxx-BND
MB91263BPF-G-xxx-BNDE1
MB91263BPFV-G-xxx-BND
MB91263BPFV-G-xxx-BNDE1
100-pin plastic QFP
(FPT-100P-M06)
100-pin plastic LQFP
(FPT-100P-M05)
57
MB91260B Series
■ PACKAGE DIMENSION
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100 - pin plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8˚
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
C
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches)
Note: The values in parentheses are reference values.
(Continued)
58
MB91260B Series
(Continued)
100-pin plastic LQFP
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
(FPT-100P-M05)
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
INDEX
0.10±0.10
(.004±.004)
(Stand off)
100
26
0˚~8˚
"A"
0.50±0.20
(.020±.008)
0.25(.010)
1
25
0.60±0.15
(.024±.006)
0.50(.020)
0.20±0.05
(.008±.002)
0.145±0.055
(.0057±.0022)
M
0.08(.003)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches)
Note: The values in parentheses are reference values.
59
MB91260B Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0401
FUJITSU LIMITED Printed in Japan
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