MB91F267NAPMC-GE1 [FUJITSU]
32-bit Proprietary Microcontrollers; 32位微控制器专用
| 型号： | MB91F267NAPMC-GE1 |
| 厂家： | 
FUJITSU |
| 描述： | 32-bit Proprietary Microcontrollers |
| 文件： | 总55页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16702-3E
32-bit Proprietary Microcontrollers
CMOS
FR60Lite MB91265A Series
MB91266A/MB91F267A/MB91F267NA/MB91V265A
■ DESCRIPTION
The MB91265A series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications
which require high-speed processing.
The CPU is used the FR family* and the compatibility of FR60Lite.
MB91F267NA loads the C-CAN (1 channel) .
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
• FR60Lite CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method)
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
• Memory-to-memory transfer, bit handling, barrel shift instructions, etc. : Instructions suitable for embedded
applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
• Register interlock function : Facilitates coding in assembler.
• Built-in multiplier with instruction-level support
• 32-bit multiplication with sign : 5 cycles
• 16-bit multiplication with sign : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction compatible with FR family
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2005-2007 FUJITSU LIMITED All rights reserved
MB91265A Series
(Continued)
• Internal peripheral functions
• Capacity of internal ROM and ROM type
MASK ROM : 64 Kbytes (MB91266A)
Flash ROM : 128 Kbytes (MB91F267A/MB91F267NA)
: 24 Kbytes (evaluation model*)
* : Evaluation model is MB91V265A.
• Capacity of internal RAM : 2 Kbytes (MASK product)/4 Kbytes (Flash memory product)
• A/D converter (sequential comparison type)
Resolution : 8/10 bits : 4 channels × 1 unit, 7 channels × 1 unit
Conversion time : 1.2 µs (Minimum conversion time system clock at 33 MHz)
1.35 µs (Minimum conversion time system clock at 20 MHz)
• External interrupt input : 8 channels
• Bit search module (for REALOS)
Function for searching the MSB (upper bit) in each word for the first 1-to-0 inverted bit position
• C-CAN 32MSB : 1 channel (loaded in MB91F267NA only)
• UART (Full-duplex double buffer) : 2 channels
Selectable parity On/Off
Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
Internal timer for dedicated baud rate (U-TIMER) on each channel
External clock can be used as transfer clock
Error detection function for parity, frame, and overrun errors
• 8/16-bit PPG timer : 8 channels (at 8-bit) / 4 channels (at 16-bit)
• Timing generator
• 16-bit reload timer : 3 channels (with cascade mode, without output of reload timer 0)
• 16-bit free-run timer : 3 channels
• 16-bit PWC timer : 1 channel
• Input capture : 4 channels (interface with free-run timer)
• Output compare : 6 channels (interface with free-run timer)
• Waveform generator
Various waveforms which are generated by using output compare, 16-bit PPG timer 0, and 16-bit dead timer
• SUM of products macro
RAM : instruction RAM (I-RAM) 256 × 16-bit
coefficient RAM (X-RAM) 64 × 16-bit
variable RAM (Y-RAM)
64 × 16-bit
Execution of 1 cycle MAC (16-bit × 16-bit + 40 bits)
Operation results are extracted rounded from 40 to 16 bits
• DMAC (DMA Controller) : 5 channels
Operation of transfer and activation by internal peripheral interrupts and software
• Watchdog timer
• Low-power consumption mode
Sleep/stop function
• Package : LQFP-64P
• Technology : CMOS 0.35 µm
• Power supply : 1-power supply (Vcc = 4.0 V to 5.5 V)
2
MB91265A Series
■ PIN ASSIGNMENT
(TOP VIEW)
AVSS
ACC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
X1
X0
MD0
MD1
MD2
PG1/PPG0
P27
P26/IC1
P25/IC0
P24/CKI
P23/DTTI
P22/PWI0
P21/ADTG2/IC3
P20/ADTG1/IC2
P17/PPG6/TX0*
SS
AN0/P50
AN1/P51
AN2/P52
AN3/P53
AN4/P54
AN5/P55
AN6/P56
AN7/P57
AN8/P44
AN9/P45
AN10/P46
NMI
9
10
11
12
13
14
15
16
C
VSS
(FPT-64P-M23)
* : C-CAN pin is loaded in only MB91F267NA.
3
MB91265A Series
■ PIN DESCRIPTION
I/O
Pin
Pin no.
Circuit
Description
name
AN0
P50
AN1
P51
AN2
P52
AN3
P53
AN4
P54
AN5
P55
AN6
P56
AN7
P57
AN8
P44
AN9
P45
type*1
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
3
G
G
G
G
G
G
G
G
G
G
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
4
5
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
6
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
7
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
8
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
9
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
10
11
12
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
(Continued)
4
MB91265A Series
I/O
Pin
name
Pin no.
Circuit
Description
Analog input terminal of A/D converter 2.
type*1
AN10
This function becomes valid when set the corresponding AICR2 register to analog
input.
13
14
G
H
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
P46
NMI
NMI (Non Maskable Interrupt) input terminal.
External interrupt input terminal.
INT4
PPG1
P00
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
Output terminal of PPG timer 1.
This function becomes valid when output of PPG timer 1 is set to enabled.
18
19
20
E
D
E
General purpose input/output port.
This function becomes valid when output of PPG timer 1 and external interrupt input
are set to disabled.
Output terminal of PPG timer 2.
This function becomes valid when output of PPG timer 2 is set to enabled.
PPG2
P01
General purpose input/output port.
This function becomes valid when output of PPG timer 2 is set to disabled.
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
INT5
PPG3
P02
Output terminal of PPG timer 3.
This function becomes valid when output of PPG timer 3 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 3 and external interrupt input
are set to disabled.
External trigger input terminal of reload timer 0.
TIN0
P03
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
21
22
23
D
D
D
General purpose input/output port.
This function becomes valid when external clock input of reload timer 0 is set to
disabled.
External trigger input terminal of reload timer 1.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
TIN1
P04
General purpose input/output port.
This function becomes valid when external clock input of reload timer 1 is set to
disabled.
External trigger input terminal of reload timer 2.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
TIN2
P05
General purpose input/output port.
This function becomes valid when external clock input of reload timer 2 is set to
disabled.
(Continued)
5
MB91265A Series
I/O
Pin
Circuit
Pin no.
Description
name
TOT1
P06
type*1
Output terminal of reload timer 1.
This function becomes valid when output of reload timer 1 is set to enabled.
24
D
D
D
General purpose input/output port.
This function becomes valid when output of reload timer 1 is set to disabled.
Output terminal of reload timer 2.
TOT2
P07
This function becomes valid when output of reload timer 2 is set to enabled.
25
26
General purpose input/output port.
This function becomes valid when output of reload timer 2 is set to disabled.
UART0 data output terminal.
SOT0
P10
This function becomes valid when data output of UART0 is set to enabled.
General purpose input/output port.
This function becomes valid when data output of UART0 is set to disabled.
UART0 data input terminal.
SIN0
Since this input is used as required while the UART0 input is enabled, the port output
must remain off unless intentionally used.
27
D
General purpose input/output port.
This function becomes valid when data input of UART0 is set to disabled.
P11
SCK0
P12
UART0 clock input/output terminal.
This function becomes valid when clock output of UART0 is set to enabled.
28
29
D
D
General purpose input/output port.
This function becomes valid when clock output of UART0 is set to disabled.
UART1 data output terminal.
This function becomes valid when data output of UART1 is set to enabled.
SOT1
P13
General purpose input/output port.
This function becomes valid when data output of UART1 is set to disabled.
UART1 data input terminal.
SIN1
Since this input is used as required while the UART1 input is enabled, the port output
must remain off unless intentionally used.
30
31
D
D
General purpose input/output port.
This function becomes valid when data input of UART1 is set to disabled.
P14
SCK1
P15
UART1 clock input/output terminal.
This function becomes valid when clock output of UART1 is set to enabled.
General purpose input/output port.
This function becomes valid when clock output of UART1 is set to disabled.
(Continued)
6
MB91265A Series
I/O
Pin
name
Circuit
Pin no.
Description
type*1
External interrupt input terminal.
INT6
PPG5
RX0
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
Output terminal of PPG timer 5.
This function becomes valid when output of PPG timer 5 is set to enabled.
32
E
RX0 input terminal of C-CAN0 (MB91F267NA only ) .
Since this input is used as required while the RX0 input is enabled, port output must
remain off unless intentionally used.
General purpose input/output port.
P16
This function becomes valid when output of PPG timer 5 and RX0 input*2 of C-CAN0
are set to disabled.
Output terminal of PPG timer 6.
This function becomes valid when output of PPG timer 6 is set to enabled.
PPG6
TX0
TX0 output terminal of C-CAN0 (only MB91F267NA) .
This function becomes valid when TX0 output of C-CAN0 is set to enabled.
33
D
General purpose input/output port.
P17
This function becomes valid when output of PPG timer 6 and TX0 output*2 of C-CAN0
are set to disabled.
External trigger input terminal of A/D converter 1.
ADTG1
Since this input is used as required while it selects as A/D activation trigger cause, the
port output must remain off unless intentionally used.
Trigger input terminal of input capture 2.
The port can serve as an input when set for input with the setting of the input capture
trigger input. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
34
IC2
D
General purpose input/output port.
P20
This function becomes valid when the setting of the external trigger input of A/D
converter 1 or the setting of the input capture trigger input is set to disabled.
External trigger input terminal of A/D converter 2.
ADTG2
Since this input is used as required while it selects as A/D activation trigger cause, the
port output must remain off unless intentionally used.
Trigger input terminal of input capture 3.
The port can serve as an input when set for input with the setting of the input capture
trigger input. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
35
IC3
D
General purpose input/output port.
P21
PWI0
P22
This function becomes valid when the setting of the external trigger input of A/D
converter 2 or the setting of the input capture trigger input is set to disabled.
Pulse width counter input of PWC timer 0
This function becomes valid when pulse width counter input of PWC timer 0 is set to
enabled.
36
D
General purpose input/output port.
This function becomes valid when pulse width counter input of PWC timer 0 is set to
disabled.
(Continued)
7
MB91265A Series
I/O
Pin
Circuit
Pin no.
Description
name
DTTI
P23
type*1
Control input signal of multi-function timer waveform generator output RTO0 to RTO5.
This function becomes valid when DTTI input is set to enabled.
37
D
D
General purpose input/output port.
This function becomes valid when input of DTTI is set to disabled.
External clock input terminal of free-run timer.
Since this input is used as required while the port is used for external clock input
terminal of free-run timer, the port output must remain off unless intentionally used.
CKI
P24
38
39
40
General purpose input/output port.
This function becomes valid when external clock input of free-run timer is set to
disabled.
Trigger input terminal of input capture 0.
The port can serve as an input when set for input with the setting of the trigger input of
input capture 0. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
IC0
P25
IC1
D
D
General purpose input/output port.
This function becomes valid when trigger input of input capture 0 is set to disabled.
Trigger input terminal of input capture 1.
The port can serve as an input when set for input with the setting of the trigger input of
input capture 1. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
General purpose input/output port.
This function becomes valid when trigger input of input capture 1 is set to disabled.
P26
P27
41
42
D
D
General purpose input/output port.
Output terminal of PPG timer 0.
This function becomes valid when output of PPG timer 0 is set to enabled.
PPG0
General purpose input/output port.
This function becomes valid when output of PPG timer 0 is set to disabled.
PG1
MD2
Mode terminal 2.
43
H, K Setting this pin determines the basic operation mode. Connect to VCC or VSS.
The circuit type of flash memory models is K.
Mode terminal 1.
44
45
MD1
MD0
H, K Setting this pin determines the basic operation mode. Connect to VCC or VSS.
The circuit type of flash memory models is K.
Mode terminal 0.
H
Setting this pin determines the basic operation mode. Connect to VCC or VSS.
46
47
X0
X1
A
A
Clock (oscillation) input terminal.
Clock (oscillation) output terminal.
Output terminal of PPG timer 4.
This function becomes valid when output of PPG timer 4 is set to enabled.
PPG4
P37
49
D
General purpose input/output port.
This function becomes valid when output of PPG timer 4 is set to disabled.
(Continued)
8
MB91265A Series
I/O
Pin
name
Circuit
Pin no.
Description
type*1
External interrupt input terminal.
INT7
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
50
E
Output terminal of PPG timer 7.
This function becomes valid when output of PPG timer 7 is set to enabled.
PPG7
General purpose input/output port.
This function becomes valid when output of PPG timer 7 is set to disabled.
P36
INIT
51
52
I
External reset input terminal.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
RTO5
P35
J
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
RTO4
P34
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
53
54
55
56
57
58
J
J
J
J
J
E
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
RTO3
P33
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
RTO2
P32
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
RTO1
P31
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
RTO0
P30
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
INT0
P40
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
(Continued)
9
MB91265A Series
(Continued)
I/O
Pin
Circuit
Pin no.
Description
name
INT1
P41
type*1
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
59
E
E
E
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
External interrupt input terminal.
INT2
P42
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
60
61
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
External interrupt input terminal.
INT3
P43
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
*1 : For the I/O circuit type, refer to “ ■ I/O CIRCUIT TYPE ”
*2 : C-CAN is set in only MB91F267NA.
• Power supply and GND pins
Pin no.
Pin name
Description
GND pins.
Apply equal potential to all of the pins.
16, 48
Vss
Power supply pin.
Apply equal potential to all of the pins.
17
Vcc
64
63
62
1
AVcc
AVRH2
AVRH1
AVss
C
Analog power supply pin for A/D converter.
Analog reference power supply pin for A/D converter 2.
Analog reference power supply pin for A/D converter 1.
Analog GND pin for A/D converter.
15
2
Condenser connection pin for internal regulator.
Condenser connection pin for analog.
ACC
10
MB91265A Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
Oscillation feedback resistance
for high speed (main clock oscillation) :
approx. 1 MΩ
X1
Clock input
A
X0
Standby control
• CMOS level output
• CMOS level hysteresis input
Pull-up control
• With standby control
• With Pull-up control
Digital output
Digital output
P-ch
P-ch
N-ch
• IOL = 4 mA
D
Digital input
Standby control
• CMOS level output
• CMOS level hysteresis input
Pull-up control
Digital output
• Without standby control
• With Pull-up control
P-ch
P-ch
N-ch
E
• IOL = 4 mA
Digital output
Digital input
(Continued)
11
MB91265A Series
Type
Circuit type
Remarks
• Analog/CMOS level hysteresis
input/output pin
• CMOS level output
• CMOS level hysteresis input
(attached with standby control)
• Analog input
Digital output
Digital output
P-ch
N-ch
G
(Analog input is enabled when AICR’s
corresponding bit is set to “1”.)
Digital input
• IOL = 4 mA
Standby control
Analog input
• CMOS level hysteresis input
• Without standby control
P-ch
N-ch
H
Digital input
• CMOS level hysteresis input
• With pull-up resistor
P-ch
P-ch
N-ch
• Without standby control
I
Digital input
(Continued)
12
MB91265A Series
(Continued)
Type
Circuit type
Remarks
• CMOS level output
• CMOS level hysteresis input
Digital output
Digital output
P-ch
N-ch
• With standby control
• IOL = 12 mA
J
Digital input
Standby control
Flash memory product only
• CMOS level input
N-ch
N-ch
N-ch
N-ch
• High voltage control for test of flash
K
Control signal
Mode input
N-ch
13
MB91265A Series
■ HANDLING DEVICES
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage greater than VCC pin or less than VSS pin is applied to an input or
output pin or if an above-rating voltage is applied between VCC and VSS pins.
A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of
an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating.
Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-
up or pull-down resistor.
About Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
About Crystal Oscillator Circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0
and X1 pins the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane
because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
About Mode Pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS pins.
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance
is low.
Operation at Start-up
Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up.
Also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after start-up,
hold the “L” level input to the INIT pin for the required stabilization wait time (For INIT via the INIT pin, the
oscillation stabilization wait time setting is initialized to the minimum value) .
14
MB91265A Series
Order of power turning ON/OFF
Use the following procedure for turning the power on or off.
Note that, even if the A/D converter is not used, keep the following pins connected with the level as described
below.
AVCC = VCC level
AVSS = VSS level
• When Powering ON : VCC→AVCC→AVRH
• When Powering OFF : AVRH→AVCC→VCC
About Oscillation Input at Power On
When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.
15
MB91265A Series
Caution for operation during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
External clock
When external clock is selected, the opposite phase clock to X0 pin must be supplied to X1 pin simultaneously.
If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So,
when STOP mode is specified, approximately 1 kΩ of resistance should be added externally to avoid the collision
of output.
The following figure shows using an external clock.
X0
X1
MB91265A series
Using an external clock
C pin
A bypass capacitor of approximately 0.1 µF should be connected the C pin for built-in regulator.
C
MB91265A series
0.1 µF
VSS
GND
ACC pin
A capacitor of approximately 0.1 µF should be inserted between the ACC pin and the AVSS pin as this product
has built-in A/D converter.
ACC
MB91265A series
0.1 µF
AVSS
16
MB91265A Series
Clock Control Block
Input the “L” signal to the INIT pin to assure the clock oscillation stabilization wait time.
Switch Shared Port Function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) .
Low Power Consumption Mode
To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR :
timebase counter control register) and be sure to use the following sequence
(LDI
(LDI
#value_of_standby, R0) : value_of_standby is write data to STCR.
#_STCR, R12)
R0, @R12
: _STCR is address (481H) of STCR.
: Writing to standby control register (STCR)
: STCR read for synchronous standby
: Dummy re-read of STCR
STB
LDUB
LDUB
NOP
NOP
NOP
NOP
NOP
@R12, R0
@R12, R0
: NOP × 5 for arrangement of timing
In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the
standby returns.
• Please do not do the following when the monitor debugger is used.
• Break point setting for above instruction lines
• Step execution for above instruction lines
17
MB91265A Series
Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event
or emulator menu :
1) The D0 and D1 flags are updated in advance.
2) An EIT handling routine (user interrupt or emulator) is executed.
3)UponreturningfromtheEIT,theDIVOU/DIVOSinstructionisexecuted,andtheD0andD1flagsareupdated
to the same values as in 1).
• The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to allow the interrupt.
1) The PS register is updated in advance.
2) An EIT handling routine (user interrupt) is executed.
3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the
same value as in 1).
Watchdog Timer
The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time.
The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from
being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on
operating programs until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.
For those conditions to which this exception applies, refer to “ ■ NOTE ON DEBUGGER”.
18
MB91265A Series
■ NOTE ON DEBUGGER
• Step execution of RETI command
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed
repeatedly after step execution.
This will prevent the main routine and low-interrupt-level programs from being executed.
Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine
no longer needs debugging.
• Operand break
Do not apply a data event break to access to the area containing the address of a system stack pointer.
• Execution in an unused area of flash memory
Accidentally executing an instruction in an unused area of flash memory (with data placed at 0xFFFF) prevents
breaks from being accepted.
To prevent this, the code event address mask function of the debugger should be used to cause a break when
accessing an instruction in an unused area.
• Power-on debugging
All of the following three conditions must be satisfied when the power supply is turned off by power-on debugging.
(1) The time for the user power to fall from 0.9 VCC to 0.5 VCC is 25 µs or longer.
Note : In a dual-power system, VCC indicates the external I/O power supply voltage.
(2) CPU operating frequency must be higher than 1 MHz.
(3) During execution of user program
• Interrupt handler for NMI request (tool)
Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor
flag to be set only in response to a break request from the ICE is set, for example, by an adverse effect of noise
to the DSU pin while the ICE is not connected. Enable to use the ICE while adding this program.
Additional location
Next interrupt handler
Interrupt source
Interrupt number
Offset
: NMI request (tool)
: #13 (decimal) , 0D (hexadecimal)
: 3C8H
Address TBR is default
: 000FFFC8H
Additional program
STM (R0, R1)
LDI
#B00H, R0;
#0, R1
: B00H is the address of DSU break factor register.
: Clear the break factor register.
LDI
STB
LDM
RETI
R1, @R0
(R0, R1)
19
MB91265A Series
■ BLOCK DIAGRAM
FR60 Lite CPU core
32
32
DMAC 5 channels
Bit search module
16-bit MAC
ROM 64 Kbytes/
Flash 128 Kbytes
Bus converter
RAM 2 Kbytes/
RAM 4 Kbytes
1 channel
C-CAN
TX0
RX0
32
(Built-in MB91F267NA only)
16-bit ↔ 32-bit
Adapter
X0, X1
MD0 to MD2
INIT
Clock
control
16
PORT
Port I/F
Interrupt
controller
3 channels
16-bit reload timer
TIN0 to TIN2
TOT1, TOT2
8 channels
INT0 to INT7
external interrupt
NMI
1 channel
16-bit PWC timer
PWI0
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
2 channels
UART
4 channels 16-bit/
8 channels 8-bit
PPG timer
PPG0 to PPG7
2 channels
U-TIMER
AVCC
ADTG1
AVRH1
Timing generator
4 channels input
8/10-bit A/D converter-1
AN0 to AN3
ADTG2
AVRH2
AN4 to AN10
Multi-function timer
16-bit free-run timer 3 channels
Input capture 4 channels
Output compare 6 channels
Waveform generator
7 channels input
8/10-bit A/D converter-2
CKI
IC0 to IC3
RTO0 to RTO5
DTTI
20
MB91265A Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the data size to be being accessed as follows.
→ byte data access
→ half word data access : 000H to 1FFH
→ word data access : 000H to 3FFH
: 000H to 0FFH
2. Memory Map
MB91F267A/MB91F267NA
Single chip mode
MB91266A
Single chip mode
0000 0000H
0000 0000H
0000 0400H
Direct
addressing area
Direct
addressing area
I/O
I/O
I/O
0000 0400H
I/O
Refer to ■ I/O MAP
Refer to ■ I/O MAP
0001 0000H
0001 0000H
Access
Access
disallowed
disallowed
0003 F000H
0003 F800H
Internal RAM
2 Kbytes
Internal RAM
4 Kbytes
0004 0000H
0004 0000H
Access
Access
disallowed
disallowed
000E 0000H
000F 0000H
0010 0000H
Internal ROM
128 Kbytes
Internal ROM
64 Kbytes
0010 0000H
Access
disallowed
Access
disallowed
FFFF FFFFH
FFFF FFFFH
21
MB91265A Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
• Mode Pins
The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.
Mode Pins
Reset vector
access area
Mode name
Remarks
MD2 MD1 MD0
0
0
0
0
0
1
Internal ROM mode vector
External ROM mode vector
Internal
External
Not supported by this model.
• Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset source. User programs cannot set data to the mode register.
Details of mode data description
bit
31
30
29
0
28
27
0
26
1
25
1
24
1
0
0
0
Operation mode setting bits
Bit31 to bit24 are all reserved bits.
Be sure to set this bit to “00000111”.
Operation is not guaranteed when any value other than “00000111” is set.
Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8H.
Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte
endian.
bit 31
24 23
16 15
8 7
0
Incorrect
Correct
0x000FFFF8H
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
XXXXXXXX
0x000FFFF8H
0x000FFFFCH
Mode Data
Reset Vector
22
MB91265A Series
■ I/O MAP
[How to read the table]
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
T-unit
Port data register
000000H
Read/write attribute Access unit
(B : byte, H : half word, W : word)
Initial value of register after reset
Register name (column 1 of the register is at address 4n, column 2 is
at address 4n + 1...)
Leftmost register address (For word-length access, column 1 of the
register becomes the MSB of the data.)
Note : Initial values of register bits are represented as follows :
“ 1 ” : Initial Value “ 1 ”
“ 0 ” : Initial Value “ 0 ”
“ X ” : Initial Value “ undefined”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
23
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
PDR0 [R/W] B, H, W
XXXXXXXX
PDR1 [R/W] B, H, W PDR2 [R/W] B, H, W PDR3 [R/W] B, H, W
000000H
000004H
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDR4 [R/W] B, H, W
-XXXXXXX
PDR5 [R/W] B, H, W
XXXXXXXX
⎯
⎯
Port data
register
000008H
00000CH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PDRG [R/W] B, H, W
------X-
000010H
⎯
⎯
⎯
000014H
to
00003CH
⎯
Reserved
EIRR0 [R/W] B, H, W ENIR0 [R/W] B, H, W
00000000 00000000
ELVR0 [R/W] B, H, W
00000000 00000000
External interrupt
(INT0 to INT7)
000040H
000044H
000048H
00004CH
000050H
000054H
000058H
00005CH
DICR [R/W] B, H, W HRCL [R/W, R] B, H, W
-------0 0--11111
Delay interrupt/
Hold request
⎯
⎯
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
Reload
timer 0
TMCSR0 [R/W, R] B, H, W
---00000 00000000
⎯
TMRLR1 [W] H, W
XXXXXXXX XXXXXXXX
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
Reload
timer 1
TMCSR1 [R/W, R] B, H, W
---00000 00000000
⎯
TMRLR2 [W] H, W
XXXXXXXX XXXXXXXX
TMR2 [R] H, W
XXXXXXXX XXXXXXXX
Reload
timer 2
TMCSR2 [R/W, R] B, H, W
---00000 00000000
⎯
SIDR0 [R]/SODR0[W]
SMR0 [R/W, W]
SSR0 [R/W, R] B, H, W
00001000
SCR0 [R/W] B, H, W
000060H
000064H
000068H
00006CH
B, H, W
XXXXXXXX
B, H, W
00--0-0-
UART0
U-TIMER 0
UART1
00000100
UTIM0 [R] H / UTIMR0 [W] H
00000000 00000000
DRCL0 [W] B
--------
UTIMC0 [R/W] B
0--00001
SIDR1 [R]/SODR1[W]
SSR1 [R/W, R] B, H, W
00001000
SCR1 [R/W] B, H, W SMR1 [R/W] B, H, W
B, H, W
XXXXXXXX
00000100
00--0-0-
UTIM1 [R] H / UTIMR1 [W] H
00000000 00000000
DRCL1 [W] B
--------
UTIMC1 [R/W] B
0--00001
U-TIMER 1
000070H
to
00007CH
⎯
⎯
⎯
⎯
Reserved
(Continued)
24
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
ADCH1 [R/W] B, H, W ADMD1 [R/W] B, H, W ADCD11 [R] B, H, W
ADCD10 [R] B, H, W
XXXXXXXX
000080H
000084H
000088H
00008CH
A/D
converter 1/
AICR1
XXXX0XX0
00001111
XXXXXXXX
ADCS1 [R/W, W] B, H, W
00000X00
AICR1 [R/W] B, H, W
----0000
⎯
⎯
ADCH2 [R/W] B, H, W ADMD2 [R/W] B, H, W ADCD21 [R] B, H, W
ADCD20 [R] B, H, W
XXXXXXXX
A/D
converter 2/
AICR2
XXXX0XX0
00001111
XXXXXXXX
ADCS2 [R/W, W] B, H, W
00000X00
AICR2 [R/W] B, H, W
-0000000
⎯
⎯
OCCPBH0, OCCPBL0[W] /
OCCPBH1, OCCPBL1[W] /
000090H
000094H
000098H
OCCPH0, OCCPL0[R] H, W
00000000 00000000
OCCPH1, OCCPL1 [R] H, W
00000000 00000000
OCCPBH2, OCCPBL2[W] /
OCCPH2, OCCPL2 [R] H, W
00000000 00000000
OCCPBH3, OCCPBL3[W] /
OCCPH3, OCCPL3 [R] H, W
00000000 00000000
16-bit
output
compare
OCCPBH4, OCCPBL4[W] /
OCCPH4, OCCPL4 [R] H, W
00000000 00000000
OCCPBH5, OCCPBL5[W] /
OCCPH5, OCCPL5 [R] H, W
00000000 00000000
OCSH1 [R/W] B, H, W
X1100000
OCSL0 [R/W] B, H, W OCSH3 [R/W] B, H, W OCSL2 [R/W] B, H, W
00009CH
0000A0H
00001100
OCSL4 [R/W] B, H, W OCMOD [R/W] B, H, W
00001100 XX000000
X1100000
00001100
OCSH5 [R/W] B, H, W
X1100000
⎯
CPCLRBH0, CPCLRBL0[W]/
CPCLRH0, CPCLRL0[R] H, W
11111111 11111111
TCDTH0, TCDTL0 [R/W] H, W
00000000 00000000
0000A4H
16-bit
free-run
timer 0
TCCSH0 [R/W] B, H, W TCCSL0 [R/W] B, H, W
ADTRGC [R/W] B, H, W
XXXX0000
0000A8H
0000ACH
0000B0H
⎯
00000000
01000000
IPCPH0, IPCPL0 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH1, IPCPL1 [R] H, W
XXXXXXXX XXXXXXXX
16-bit
input
capture
IPCPH2, IPCPL2 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH3, IPCPL3 [R] H, W
XXXXXXXX XXXXXXXX
PICSH01 [W] B, H, W PICSL01 [R/W] B, H, W ICSH23 [R] B, H, W
ICSL23 [R/W]B, H, W
00000000
0000B4H
0000B8H
0000BCH
00000000
00000000
XXXXXX00
⎯
⎯
⎯
⎯
Reserved
TMRRH0, TMRRL0 [R/W] H, W
XXXXXXXX XXXXXXXX
TMRRH1, TMRRL1 [R/W] H, W
XXXXXXXX XXXXXXXX
TMRRH2, TMRRL2 [R/W] H, W
XXXXXXXX XXXXXXXX
0000C0H
0000C4H
0000C8H
⎯
⎯
⎯
Waveform
generator
DTCR0 [R/W] B, H, W
00000000
DTCR1 [R/W] B, H, W DTCR2 [R/W] B, H, W
00000000
00000000
SIGCR1 [R/W] B, H, W
00000000
SIGCR2 [R/W] B, H, W
XXXXXXX1
⎯
⎯
(Continued)
25
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
ADCOMP1 [R/W] H, W
00000000 00000000
+ 3
0000CCH
0000D0H
⎯
A/D COMP
ADCOMPC2 [R/W]
ADCOMPC1 [R/W]
B, H, W
ADCOMP2 [R/W] H, W
00000000 00000000
B, H, W
XX0000XX
XXXXX00X
0000D4H
0000D8H
0000DCH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Reserved
PWCSR0 [R/W, R] B, H, W
00000000 00000000
PWCR0 [R] H, W
00000000 00000000
0000E0H
0000E4H
0000E8H
16-bit PWC
timer
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PDIVR0 [R/W] B, H, W
XXXXX000
0000ECH
0000F0H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Reserved
000F4H
to
000FCH
⎯
⎯
⎯
⎯
PRLH0 [R/W] B, H, W PRLL0 [R/W] B, H, W PRLH1 [R/W] B, H, W PRLL1 [R/W] B, H, W
000100H
000104H
000108H
00010CH
000110H
000114H
XXXXXXXX
PRLH2 [R/W] B, H, W PRLL2 [R/W] B, H, W PRLH3 [R/W] B, H, W PRLL3 [R/W] B, H, W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PPGC0 [R/W] B, H, W PPGC1 [R/W] B, H, W PPGC2 [R/W] B, H, W PPGC3 [R/W] B, H, W
00000000 00000000 00000000 00000000
PRLH4 [R/W] B, H, W PRLL4 [R/W] B, H, W PRLH5 [R/W] B, H, W PRLL5 [R/W] B, H, W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PRLH6 [R/W] B, H, W PRLL6 [R/W] B, H, W PRLH7 [R/W] B, H, W PRLL7 [R/W] B, H, W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
PPGC4 [R/W] B, H, W PPGC5 [R/W] B, H, W PPGC6 [R/W] B, H, W PPGC7 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
8/16-bit
PPG timer
0 to 7
00000000
00000000
00000000
00000000
000118H
to
00012CH
⎯
⎯
⎯
⎯
Reserved
TRG [R/W] B, H, W
-------- 00000000
GATEC [R/W] B, H, W
XXXXXX00
000130H
000134H
⎯
⎯
8/16-bit
PPG timer
0 to 7
REVC [R/W] B, H, W
-------- 00000000
⎯
⎯
000138H
to
000140H
⎯
⎯
⎯
Reserved
(Continued)
26
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
TTCR0 [R/W] B, H, W
00000000
TSTPR0 [R] B, H, W
00000000
000144H
000148H
⎯
⎯
COMP0 [R/W] B, H, W
00000000
COMP2 [R/W] B, H, W COMP4 [R/W] B, H, W COMP6 [R/W] B, H, W
Timing
generator
00000000
00000000
00000000
00014CH
000150H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
CPCLRBH1, CPCLRBL1 [W] /
CPCLRH1, CPCLRL1 [R] H, W
11111111 11111111
TCDTH1, TCDTL1 [R/W] H, W
00000000 00000000
000154H
000158H
00015CH
16-bit
free-run
timer 1
TCCSH1 [R/W] B, H, W TCCSL1 [R/W] B, H, W
⎯
⎯
00000000
01000000
CPCLRBH2, CPCLRBL2 [W] /
CPCLRH2, CPCLRL2 [R] H, W
11111111 11111111
TCDTH2, TCDTL2 [R/W] H, W
00000000 00000000
16-bit
free-run
timer 2
TCCSH2 [R/W] B, H, W TCCSL2 [R/W] B, H, W
000160H
000164H
000168H
⎯
⎯
⎯
⎯
00000000
01000000
⎯
⎯
Reserved
FSR2 [R/W] B, H, W
00000000
FSR1 [R/W] B, H, W
----0000
FSR0 [R/W] B, H, W
00000000
FRT
selector
⎯
00016CH
to
0001A4H
⎯
Reserved
CANPRE [R, R/W] B, H, W
00000000
C-CAN*1
prescaler
0001A8H
⎯
⎯
⎯
0001ACH
to
0001FCH
⎯
Reserved
DMACA0 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMACA1 [R/W] B, H, W*2
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMACA2 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMAC
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMACA3 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMACA4 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
(Continued)
27
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
000228H
to
00023CH
⎯
Reserved
DMAC
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
000240H
000244H
to
⎯
00024CH
000250H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Reserved
000254H
to
000398H
⎯
00039CH
DSP-PC [R/W]
XXXXXXXX
DSP-CSR [R/W, R, W]
00000000
DSP-LY [R/W]
XXXXXXXX XXXXXXXX
0003A0H
DSP-OT0 [R]
XXXXXXXX XXXXXXXX
DSP-OT1 [R]
XXXXXXXX XXXXXXXX
0003A4H
DSP-OT2 [R]
XXXXXXXX XXXXXXXX
DSP-OT3 [R]
XXXXXXXX XXXXXXXX
0003A8H
0003ACH
0003B0H
16 bit MAC
⎯
⎯
⎯
⎯
DSP-OT4 [R]
XXXXXXXX XXXXXXXX
DSP-OT5 [R]
XXXXXXXX XXXXXXXX
DSP-OT6[R]
XXXXXXXX XXXXXXXX
DSP-OT7 [R]
XXXXXXXX XXXXXXXX
0003B4H
0003B8H
⎯
⎯
⎯
⎯
0003BCH
to
⎯
Reserved
0003ECH
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F0H
0003F4H
0003F8H
0003FCH
000400H
000404H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit search
module
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDR0 [R/W] B, H, W
00000000
DDR1 [R/W] B, H, W
00000000
DDR2 [R/W] B, H, W
00000000
DDR3 [R/W] B, H, W
00000000
DDR4 [R/W] B, H, W
-0000000
DDR5 [R/W] B, H, W
00000000
⎯
⎯
Data
direction
register
000408H
00040CH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DDRG [R/W] B, H, W
------0-
000410H
⎯
⎯
⎯
(Continued)
28
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
000414H
to
00041CH
⎯
Reserved
PFR0 [R/W] B, H, W
00------
PFR1 [R/W] B, H, W
0-0-00-0
000420H
⎯
⎯
000424H
000428H
00042CH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Port
function
register
⎯
⎯
PTFR0 [R/W] B, H, W
00000000
000430H
⎯
⎯
⎯
000434H
to
00043CH
⎯
Reserved
ICR00 [R/W, R] B, H, W ICR01 [R/W, R] B, H, W ICR02 [R/W, R] B, H, W ICR03 [R/W, R] B, H, W
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
----1111
ICR04 [R/W, R] B, H, W ICR05 [R/W, R] B, H, W ICR06 [R/W, R] B, H, W ICR07 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR08 [R/W, R] B, H, W ICR09 [R/W, R] B, H, W ICR10 [R/W, R] B, H, W ICR11 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR12 [R/W, R] B, H, W ICR13 [R/W, R] B, H, W ICR14 [R/W, R] B, H, W ICR15 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR16 [R/W, R] B, H, W ICR17 [R/W, R] B, H, W ICR18 [R/W, R] B, H, W ICR19 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR20 [R/W, R] B, H, W ICR21 [R/W, R] B, H, W ICR22 [R/W, R] B, H, W ICR23 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR24 [R/W, R] B, H, W ICR25 [R/W, R] B, H, W ICR26 [R/W, R] B, H, W ICR27 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR28 [R/W, R] B, H, W ICR29 [R/W, R] B, H, W ICR30 [R/W, R] B, H, W ICR31 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR32 [R/W, R] B, H, W ICR33 [R/W, R] B, H, W ICR34 [R/W, R] B, H, W ICR35 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR36 [R/W, R] B, H, W ICR37 [R/W, R] B, H, W ICR38 [R/W, R] B, H, W ICR39 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR40 [R/W, R] B, H, W ICR41 [R/W, R] B, H, W ICR42 [R/W, R] B, H, W ICR43 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
ICR44 [R/W, R] B, H, W ICR45 [R/W, R] B, H, W ICR46 [R/W, R] B, H, W ICR47 [R/W, R] B, H, W
----1111 ----1111 ----1111 ----1111
----1111
----1111
----1111
Interrupt
control
unit
000470H
to
00047CH
⎯
Reserved
(Continued)
29
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
RSRR [R/W] B, H, W STCR [R/W] B, H, W
TBCR [R/W] B, H, W
00XXXX00
CTBR [W] B, H, W
XXXXXXXX
000480H
000484H
10000000
00110011
CLKR [R/W] B, H, W
00000000
WPR [W] B, H, W
XXXXXXXX
DIVR0 [R/W] B, H, W
00000011
DIVR1 [R/W] B, H, W
00000000
Clock control
000488H
00048CH
000490H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
000494H
to
⎯
Reserved
0005FCH
PCR0 [R/W] B, H, W
00000000
PCR1 [R/W] B, H, W
00000000
PCR2 [R/W] B, H, W
00000000
PCR3 [R/W] B, H, W
00------
000600H
000604H
PCR4 [R/W] B, H, W
----0000
⎯
⎯
⎯
Pull-up
000608H
00060CH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Control Unit
PCRG [R/W] B, H, W
------0-
000610H
⎯
⎯
⎯
000614H
to
⎯
00063CH
Reserved
000640H
to
⎯
000FFCH
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001000H
001004H
001008H
00100CH
001010H
001014H
001018H
00101CH
001020H
001024H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
30
MB91265A Series
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
001028H
to
006FFCH
⎯
Reserved
FLCR [R/W] B
01101000
007000H
007004H
⎯
⎯
⎯
⎯
⎯
FLWC [R/W] B
00000011
⎯
Flash
007008H
00700CH
007010H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
007014H
to
00BFFCH
⎯
Reserved
16 bit MAC
Reserved
00C000H
to
00C07CH
X-RAM (coefficient RAM) [R/W]
64 × 16-bit
00C080H
to
00C0FCH
Y-RAM (variable RAM) [R/W]
64 × 16-bit
00C100H
to
00C2FCH
I-RAM (instruction RAM) [R/W]
256 × 16-bit
00C300H
to
00FFFCH
⎯
CTRLR0 [R, R/W]
00000000 00000001
STATR0 [R, R/W]
00000000 00000000
020000H
020004H
020008H
02000CH
020010H
020014H
020018H
02001CH
020020H
020024H
ERRCNT0 [R]
00000000 00000000
BTR0 [R, R/W]
00100011 00000001
INTR0 [R]
00000000 00000000
TESTR0 [R, R/W]
00000000 X0000000
BRPER0 [R, R/W]
00000000 00000000
⎯
⎯
IF1CREQ0 [R, R/W]
00000000 00000000
IF1CMSK0 [R, R/W]
00000000 00000000
C-CAN*1
IF1MSK20 [R, R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
IF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
IF1MCTR0 [R, R/W]
00000000 00000000
⎯
⎯
IF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
(Continued)
31
MB91265A Series
(Continued)
Register
Address
Block
+ 0
+ 1
+ 2
+ 3
020030H
020040H
Reserved (IF1 data mirror, little endian byte ordering)
IF2CREQ0 [R, R/W]
IF2CMSK0 [R, R/W]
00000000 00000000
00000000 00000000
IF2MSK20 [R, R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
020044H
020048H
02004CH
020050H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
IF2MCTR0 [R, R/W]
00000000 00000000
⎯
⎯
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
020054H
020060H
020080H
020084H
020090H
020094H
0200A0H
0200A4H
0200B0H
0200B4H
C-CAN*1
Reserved (IF2 data mirror, little endian byte ordering)
TREQR20 [R]
00000000 00000000
TREQR10 [R]
00000000 00000000
Reserved (>32..128 Message buffer)
NEWDT20 [R]
00000000 00000000
NEWDT10 [R]
00000000 00000000
Reserved (>32..128 Message buffer)
INTPND20 [R]
00000000 00000000
INTPND10 [R]
00000000 00000000
Reserved (>32..128 Message buffer)
MESVAL20 [R]
00000000 00000000
MESVAL10 [R]
00000000 00000000
Reserved (>32..128 Message buffer)
*1 : C-CAN is loaded in only MB91F267NA.
*2 : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes.
Notes : • The initial value of FLWC (7004H) is “00010011B” on EVA tool. Writing “00000011B” on the evaluation
model has no effect on its operation.
• Do not execute Read Modify Write instructions on registers having a write-only bit.
• Data is undefined in reserved or (-) area.
32
MB91265A Series
■ INTERRUPT VECTOR
Interrupt number
Interrupt
level
TBR default
address
Interrupt source
Offset
Hexa-
Decimal
decimal
Reset
0
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
⎯
⎯
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
38CH
388H
384H
380H
37CH
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
000FFFC0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
000FFF94H
000FFF90H
000FFF8CH
000FFF88H
000FFF84H
000FFF80H
000FFF7CH
Mode vector
1
System reserved
2
⎯
System reserved
3
⎯
System reserved
4
⎯
System reserved
5
⎯
System reserved
6
⎯
Coprocessor absent trap
Coprocessor error trap
INTE instruction
7
⎯
8
⎯
9
⎯
System reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
⎯
System reserved
⎯
Step trace trap
⎯
NMI request (tool)
Undefined instruction exception
NMI request
⎯
⎯
15 (FH) fixed
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6/C-CAN wake up*
External interrupt 7
Reload timer 0
Reload timer 1
Reload timer 2
UART0(Reception completed)
UART0 (RX completed)
DTTI
DMAC0 (end, error)
DMAC1 (end, error)
DMAC2/DMAC3/DMAC4 (end, error)
(Continued)
33
MB91265A Series
Interrupt number
Interrupt
level
TBR default
address
Interrupt source
Offset
Hexa-
Decimal
decimal
UART1(Reception completed)
UART1 (RX completed)
C-CAN0*
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
⎯
378H
374H
370H
36CH
368H
364H
360H
35CH
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
000FFF78H
000FFF74H
000FFF70H
000FFF6CH
000FFF68H
000FFF64H
000FFF60H
000FFF5CH
000FFF58H
000FFF54H
000FFF50H
000FFF4CH
000FFF48H
000FFF44H
000FFF40H
000FFF3CH
000FFF38H
000FFF34H
000FFF30H
000FFF2CH
000FFF28H
000FFF24H
000FFF20H
000FFF1CH
000FFF18H
000FFF14H
000FFF10H
000FFF0CH
000FFF08H
000FFF04H
000FFF00H
000FFEFCH
000FFEF8H
System reserved
16-bit MAC
PPG0/PPG1
PPG2/PPG3
PPG4/PPG5/PPG6/PPG7
System reserved
Waveform0/1/2 (underflow)
Free-run timer 1 (compare clear)
Free-run timer 1 (zero detection)
Free-run timer 2 (compare clear)
Free-run timer 2 (zero detection)
Timebase timer overflow
Free-run timer 0 (compare clear)
Free-run timer 0 (zero detection)
System reserved
A/D converter 1
A/D converter 2
PWC0 (measurement completed)
System reserved
PWC0 (overflow)
System reserved
ICU0 (capture)
ICU1 (capture)
ICU2/3 (capture)
OCU0/1 (match)
OCU2/3 (match)
OCU4/5 (match)
Delay interrupt source bit
System reserved (Used by REALOS)
System reserved (Used by REALOS)
⎯
(Continued)
34
MB91265A Series
(Continued)
Interrupt number
Interrupt
level
TBR default
address
Interrupt source
Offset
Hexa-
Decimal
decimal
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
System reserved
66
67
68
69
70
71
72
73
74
75
76
77
78
79
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
2C8H
2C4H
2C0H
000FFEF4H
000FFEF0H
000FFEECH
000FFEE8H
000FFEE4H
000FFEE0H
000FFEDCH
000FFED8H
000FFED4H
000FFED0H
000FFECCH
000FFEC8H
000FFEC4H
000FFEC0H
80
to
255
50
to
FF
2BCH
to
000H
000FFEBCH
to
000FFC00H
Used by INT instruction
⎯
* : C-CAN interrupt is only loaded in MB91F267NA.
35
MB91265A Series
■ PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows.
• Input enabled
Indicates that the input function can be used.
• Input 0 fixed
Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released.
• Output Hi-Z
• Output is maintained.
Indicates the output in the output state existing immediately before this mode is established.
If the device enters this mode with an internal output peripheral operating or while serving as an output port,
the output is performed by the internal peripheral or the port output is maintained, respectively.
• State existing immediately before is maintained.
When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.
• List of pin status (single chip mode)
At initializing
INIT = L*1 INIT = H*2
Output Hi-Z/ Output Hi-Z/
At Stop mode
At sleep
mode
Pin no. Pin name
Function
Hi-Z = 0
Hi-Z = 1
3 to 10 P50 to P57 AN0 to AN7
11 to 13 P44 to P46 AN8 to AN10
Retention of
the immedi-
ately prior
state
Retention
of the
Output Hi-Z/
Input
Input
immediately Input 0 fixed
prior state
disabled
enabled
Input
enabled
Input
enabled
14
18
NMI
P00
NMI
Input
enabled
Input
enabled
Input
enabled
PPG1/INT4
Retention
of the
immediately
prior state
Retention
of the
immediately Input 0 fixed
prior state
Output Hi-Z/
19
P01
PPG2
20
P02
PPG3/INT5
Input enabled Input enabled Input enabled
21 to 23 P03 to P05 TIN0 to TIN2
24, 25 P06, P07 TOT1, TOT2
Output Hi-Z/ Output Hi-Z/
Input
disabled
Input
enabled
26
27
28
29
30
31
P10
P11
P12
P13
P14
P15
SOT0
SIN0
Retention
of the
immediately
prior state
Retention
of the
immediately Input 0 fixed
prior state
Output Hi-Z/
SCK0
SOT1
SIN1
SCK1
PPG5/INT6/
RX0*3
32
P16
Input enabled Input enabled Input enabled
(Continued)
36
MB91265A Series
(Continued)
At initializing
INIT = L*1 INIT = H*2
At Stop mode
At sleep
mode
Pin no. Pin name
Function
Hi-Z = 0
Hi-Z = 1
33
34
35
36
37
38
39
40
41
42
49
50
P17
P20
P21
P22
P23
P24
P25
P26
P27
PG1
P37
P36
PPG6/TX0*3
ADTG1/IC2
ADTG2/IC3
PWI0
Retention
of the
immediately
prior state
Retention
of the
immediately Input 0 fixed
prior state
DTTI
Output Hi-Z/
CKI
IC0
Output Hi-Z/ Output Hi-Z/
IC1
Input
Input
General port
PPG0
disabled
enabled
PPG4
PPG7/INT7
Input enabled Input enabled Input enabled
Retention
of the
immediately
prior state
Retention
of the
immediately Input 0 fixed
prior state
RTO5 to
RTO0
Output Hi-Z/
52 to 57 P35 to P30
58 to 61 P40 to P43 INT0 to INT3
Input enabled Input enabled Input enabled
*1 : INIT = L : Indicates the pin status with INIT remaining at the “L” level.
*2 : INIT = H : Indicates the pin status existing immediately after INIT transition from “L” to “H” level.
*3 : C-CAN terminal is only loaded in MB91F267NA.
37
MB91265A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VSS + 6.0
VSS + 6.0
VSS + 6.0
VCC + 0.3
AVcc + 0.3
VCC + 0.3
10
Power supply voltage*1
VCC
AVCC
AVRHn*6
VI
VSS − 0.5
VSS − 0.5
VSS − 0.5
VSS − 0.3
VSS − 0.3
VSS − 0.3
⎯
V
V
V
V
V
V
Analog power supply voltage*1
Analog reference voltage*1
Input voltage*1
Analog pin input voltage*1
Output voltage*1
*2
*2
VIA
VO
“L” level maximum output current
“L” level average output current
“L” level total maximum output current
“L” level total average output current
“H” level maximum output current
“H” level average output current
“H” level total maximum output current
“H” level total average output current
Power consumption
IOL
mA *3
mA *4
mA
IOLAV
ΣIOL
ΣIOLAV
IOH
⎯
8
⎯
60
⎯
30
mA *5
mA *3
mA *4
mA
⎯
− 10
IOHAV
ΣIOH
ΣIOHAV
PD
⎯
− 4
⎯
− 30
⎯
− 12
mA *5
mW
⎯
600
Operating temperature
Ta
− 40
+ 105
+ 125
°C At single chip operating
°C
Storage temperature
Tstg
− 55
*1 : The parameter is based on VSS = AVSS = 0 V.
*2 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on.
Be careful not to let AVCC exceed VCC, for example, when the power is turned on.
*3 : The maximum output current is the peak value for a single pin.
*4 : The average output current is the average current for a single pin over a period of 100 ms.
*5 : The total average output current is the average current for all pins over a period of 100 ms.
*6 : AVRHn = AVRH1, AVRH2
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB91265A Series
2. Recommended Operating Conditions
(Vss = AVss = 0 V)
Value
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage
VCC
4.0
5.5
V
V
At normal operating
Analog power supply
voltage
AVCC
VSS + 4.0
VSS + 5.5
AVRH1
AVRH2
Ta
AVSS
AVSS
− 40
AVCC
AVCC
+ 105
V
V
For A/D converter 1
For A/D converter 2
Analog reference voltage
Operating temperature
°C At single chip operating
Note : Upon power up, it takes approx. 100 µs for stabilization of internal power supply after the VCC power supply
is stabilized. Keep applying “L” to INIT signal during that period.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
39
MB91265A Series
3. DC Characteristics
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Conditions
Unit Remarks
Min
Typ
Max
"H" level input
voltage
Hysteresis
input pin
VIHS
VILS
VOH
VOH2
VOL
⎯
⎯
Vcc × 0.8
⎯
Vcc + 0.3
V
V
"L" level input
voltage
Hysteresis
input pin
Vss − 0.3
Vcc − 0.5
Vcc − 0.7
⎯
⎯
⎯
⎯
⎯
⎯
⎯
50
Vss × 0.2
⎯
Other than
P30 to P35
VCC = 5.0 V,
IOH = 4.0 mA
V
"H" level output
voltage
VCC = 5.0 V,
IOH = 8.0 mA
P30 to P35
⎯
V
Other than
P30 to P35
VCC = 5.0 V,
IOL = 4.0 mA
0.4
V
"L" level output
voltage
VCC = 5.0 V,
IOL = 12 mA
VOL2
ILI
P30 to P35
⎯
0.6
V
Input leak
current
VCC = 5.0 V,
VSS < VI < VCC
⎯
− 5
+ 5
µA
kΩ
Pull-up
resistance
INIT,
Pull-up pin
RPULL
⎯
⎯
⎯
ICC
VCC
VCC
VCC = 5.0 V, 33 MHz
VCC = 5.0 V, 33 MHz
⎯
⎯
90
60
100
80
mA
Power supply
current
ICCS
mA At SLEEP
VCC = 5.0 V,
Ta = + 25 °C
ICCH
VCC
⎯
300
⎯
µA At STOP
Other than VCC,
VSS, AVCC, AVSS,
AVRH1, AVRH2
Input
capacitance
CIN
⎯
⎯
5
15
pF
4. Flash Memory Write/Erase Characteristics
Value
Typ
Parameter
Conditions
Unit
Remarks
Min
Max
Sector erase time
(4 Kbytes sector)
Ta = + 25 °C,
Vcc = 5.0 V
Not including time for internal
writing before deletion.
⎯
0.2
0.5
s
Ta = + 25 °C,
Vcc = 5.0 V
Not including system-level
overhead time.
Byte write time
⎯
10000
20
32
⎯
⎯
3600
⎯
µs
Erase/write cycle
⎯
cycle
year
Flash memory data
retention time
Average
Ta = + 85 °C
⎯
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
40
MB91265A Series
5. AC Characteristics
(1) Clock Timing Ratings
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Value
Typ
Parameter
Symbol Pin
Conditions
Unit
Remarks
Min
Max
X0
X1
For using the PLL
within the self-oscilla-
tion enabled range,
set the multiplier for
the internal clock not
to let the operating
frequency exceed
33 MHz.
Clock frequency
fC
3.6*2
⎯
12
MHz
⎯
X0
X1
Clock cycle time
tC
83.3
⎯
278*2
ns
The standard of the
Input clock pulse
width
PWH
PWL
X0
⎯
⎯
100
⎯
⎯
⎯
ns duty ratio is 40 % to
60 %.
Input clock
rising, falling time
tCF
tCR
X0
⎯
5
ns At external clock
fCP
fCPP
tCP
When 4.125 MHz is 2.06*1
⎯
⎯
⎯
33
33
485*1
MHz CPU
Internal operating
clock frequency
⎯
input as the X0 clock
frequency and ×8
multiplication is set
2.06*1
MHz Peripheral
ns CPU
30.3
Internal operating
clock cycle time
⎯
for the PLL of the
oscillator circuit.
tCPP
30.3
⎯
485*1
ns Peripheral
*1 : The values assume a gear cycle of 1/16.
*2 : When the PLL is used, the lower-limit frequency of the input clock to the X0 and X1 pins determines depending
on the PLL multiplication.
At × 1 multiplication : more than 8 MHz
At × 2 to × 8 multiplication : more than 4 MHz
• Conditions for measuring the clock timing ratings
t
C
0.8 VCC
0.2 VCC
Output pin
C = 50 pF
P
WL
P
WH
t
CR
t
CF
41
MB91265A Series
• Operation Assurance Range
VCC (V)
5.5
4.0
fCP , fCPP
(MHz)
0
0.25
33
Internal clock
• Internal clock setting range
(MHz)
33
CPU (CLKB) :
Peripheral (CLKP) :
16.5
Oscillation input clock fC = 4.192 MHz
4.125
(PLL multiplied by 8)
8 : 8
4 : 4
1 : 1
CPU : Divided ratio for peripherals.
Notes : • Oscillation stabilization time of PLL > 600 µs
• The internal clock gear setting should be within the value shown in clock timing ratings table.
42
MB91265A Series
(2) Reset Input Ratings
Parameter
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Value
Sym-
bol
Condi-
tions
Pin
Unit Remarks
Max
Min
INIT input time
(at power-on and STOP mode)
Oscillation time of
oscillator + tC × 10
⎯
⎯
ns
ns
*
tINTL
INIT
⎯
INIT input time
(other than the above)
tC × 10
* : After the power is stable, L level is kept inputting to INIT for the duration of approximately 100 µs until the internal
power is stabilized.
t
INTL
INIT
0.2 VCC
43
MB91265A Series
(3) UART Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Value
Parameter
Symbol
tSCYC
tSLOV
tIVSH
tSHIX
Pin
Conditions
Unit
Min
Max
Serial clock cycle time
SCK0, SCK1
8 tCYCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
− 80
100
60
+ 80
⎯
Internal shift
clock mode
SCK0, SCK1,
SIN0, SIN1
Valid SIN → SCK ↑
ns
ns
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → valid SIN hold time
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0, SCK1
SCK0, SCK1
4 tCYCP
4 tCYCP
⎯
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
⎯
60
60
150
⎯
ns
ns
ns
External shift
clock mode
SCK0, SCK1,
SIN0, SIN1
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → valid SIN hold time
⎯
Notes : • The above ratings are the values for clock synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
44
MB91265A Series
• Internal shift clock mode
tSCYC
VOH
SCK0, SCK1
VOL
VOL
tSLOV
VOH
VOL
SOT0, SOT1
SIN0, SIN1
tIVSH
tSHIX
VOH
VOL
VOH
VOL
• External shift clock mode
tSLSH
tSHSL
VOH
VOL
VOL
VOL
SCK0, SCK1
SOT0, SOT1
tSLOV
VOH
VOL
tIVSH
tSHIX
VOH
VOL
VOH
VOL
SIN0, SIN1
45
MB91265A Series
(4) Free-run Timer Clock, PWC Input, and Reload Timer Trigger Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Conditions
Unit
Min
Max
tTIWH
tTIWL
CKI, PWI0,
TIN0 to TIN2
Input pulse width
⎯
4 tCYCP
⎯
ns
Note : tCYCP indicates the peripheral clock cycle time.
VOH
VOH
CKI, PWI0,
TIN0 to TIN2
tTIWH
VOL
VOL
tTIWL
(5) Trigger Input Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Value
Unit
Parameter
Input capture
Symbol
Pin
Conditions
Min
Max
tIC
IC0 to IC3
⎯
⎯
5 tCYCP
⎯
ns
ns
trigger input
ADTG1,
ADTG2
A/D activation trigger input
tADTG
5 tCYCP
⎯
Note : tCYCP indicates the peripheral clock cycle time.
tADTG, tIC
IC0 to IC3
ADTG1, ADTG2
V
OL
VOL
46
MB91265A Series
6. Electrical Characteristics for the A/D Converter
Sym-
(VCC = AVcc = 5.0 V, VSS = AVSS = 0 V)
Value
Typ
⎯
Parameter
Pin
Unit
Remarks
bol
Min
Max
10
Resolution
Total error*1
Linearity error*1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
bit
− 4
⎯
+ 4
LSB
LSB
− 3.5
⎯
+ 3.5
Differential linearity
error*1
⎯
⎯
− 3
⎯
+ 3
LSB
V
At AVRHn*4 = 5.0 V
AVss −
3.5LSB
AVss +
0.5LSB
AVss +
4.5LSB
Zero transition voltage*1
VOT AN0 to AN10
VFST AN0 to AN10
AVRH −
5.5LSB
1.2*2
AVRH −
1.5LSB
AVRH +
2.5LSB
Full transition voltage*1
Conversion time
V
⎯
⎯
⎯
⎯
⎯
µs
µA
Analog port
Input current
IAIN AN0 to AN10
⎯
10
Analog input voltage
Reference voltage
VAIN AN0 to AN10
AVss
AVss
⎯
⎯
⎯
2
AVRH
AVcc
⎯
V
V
⎯
AVRHn*4
AVcc
Analog power supply
current
(analog + digital)
IA
mA Per 1 unit
IAH*3
⎯
⎯
100
µA Per 1 unit
Per 1 unit
Reference power supply
current
(between AVRH and
AVSS)
IR
⎯
1
⎯
mA AVRHn*4 = 5.0 V,
at AVSS = 0 V
AVRHn*4
Per 1 unit
µA
IRH*3
⎯
⎯
100
at STOP
Analog input capacitance
Inter-channel disparity
⎯
⎯
⎯
⎯
⎯
10
⎯
pF
AN0 to AN10
⎯
4
LSB
*1 : Measured in the CPU sleep state
*2 : Vcc = AVcc = 5.0 V, machine clock at 33 MHz
*3:ThecurrentwhentheCPUisinstopmode and the A/D converter is not operating (at Vcc= AVcc = AVRHn = 5.0V)
*4: AVRHn = AVRH1, AVRH2
Note : The above does not guarantee the inter-unit accuracy.
Set the output impedance of the external circuit ≤ 2 kΩ.
47
MB91265A Series
Definition of A/D Converter Terms
• Resolution : Analog variation that is recognized by an A/D converter.
• Linearity error : Zero transition point (00 0000 0000 ←→ 00 0000 0001) and full-scale transition point.
Difference between the line connected (11 1111 1110 ←→ 11 1111 1111) and actual conversion character-
istics.
• Differential linearity error : Deviation of input voltage, that is required for changing output code by 1 LSB, from
an ideal value.
• Total error : This error indicates the difference between actual and ideal values, including the zero transition
error/full-scale transition error/linearity error.
Total error
3FFH
1.5 LSB'
Actual conversion
characteristics
3FEH
3FDH
{1 LSB' (N − 1) + 0.5 LSB'}
004H
003H
002H
001H
VNT
(measurement value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB'
AVSS
AVRH
Analog input
AVRH − AVSS
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1LSB’
(Ideal value)
=
[V] Total error of digital output N
=
1024
1 LSB’
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N + 1) to N.
VOT’ (Ideal value) = AVSS + 0.5LSB’ [V]
VFST’ (Ideal value) = AVRH − 1.5 LSB’ [V]
(Continued)
48
MB91265A Series
(Continued)
Linearity error
Differential linearity error
3FFH
3FEH
3FDH
Actual conversion
Actual conversion
characteristics
characteristics
N + 1H
{1 LSB (N − 1) + VOT}
Ideal
characteristics
VFST
(measurement
value)
NH
004H
003H
002H
001H
VNT
(measurement value)
N − 1H
N − 2H
VFST
(measurement
value)
Actual conversion
characteristics
Ideal characteristics
VNT
(measurement value)
Actual conversion
characteristics
VOT (measurement value)
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
VNT − { 1 LSB × (N − 1) + VOT }
Linearity error in digital output N
=
=
=
[LSB]
1 LSB
V (N + 1) T − VNT
Differential linearity error in digital output N
− 1 [LSB]
1 LSB
VFST − VOT
1 LSB
[V]
1022
N : A/D converter digital output value
VOT : A voltage at which digital output transits from 000H to 001H.
VFST : A voltage at which digital output transits from 3FEH to 3FFH .
49
MB91265A Series
■ EXAMPLE CHARACTERISTICS
“L” Level Output Voltage vs.
Power Supply Voltage
“H” Level Output Voltage vs.
Power Supply Voltage
6
400
350
300
250
200
150
100
50
5
4
3
2
1
0
4.0
4.5
5.0
5.5
0
4.0
VCC (V)
4.5
5.0
5.5
VCC (V)
Pull-up Resistor vs. Power Supply Voltage
Power Supply Current vs. Power Supply Voltage
80
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VCC (V)
VCC (V)
Power Supply Current vs. Internal Operating Clock Frequency (MB91266A)
100
90
80
70
Power Supply Voltage
60
50
40
30
20
10
0
4.0 V
4.5 V
5.0 V
5.5 V
15
20
25
30
35
Internal Operating Clock Frequency [MHz]
(Continued)
50
MB91265A Series
(Continued)
Power Supply Current (at sleep) vs.
Power Supply Voltage
Power Supply Current (at stop) vs.
Power Supply Voltage
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VCC (V)
VCC (V)
A/D Conversion Block Per 1 Unit (33 MHz)
Reference Power Supply Current vs.
Power Supply Voltage
A/D Conversion Block Per 1 Unit (33 MHz)
Analog Power Supply Current vs.
Power Supply Voltage
2
1.5
1
1.0
0.8
0.6
0.4
0.2
0.0
0.5
0
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VCC (V)
VCC (V)
51
MB91265A Series
■ ORDERING INFORMATION
Part number
MB91266APMC-G-XXX
MB91266APMC-GS-XXX
MB91266APMC-G-XXXE1
MB91266APMC-GS-XXXE1
MB91F267APMC-G
Package
Remarks
Lead-free Package
Lead-free Package
MB91F267APMC-GS
64-pin plastic LQFP
(FPT-64P-M23)
MB91F267APMC-GE1
MB91F267APMC-GSE1
MB91F267NAPMC-G
MB91F267NAPMC-GS
Lead-free Package
Lead-free Package
Package loaded C-CAN
Package loaded C-CAN
Lead-free Package,
Package loaded C-CAN
MB91F267NAPMC-GE1
MB91F267NAPMC-GSE1
MB91V265ACR-ES
Lead-free Package,
Package loaded C-CAN
401-pin ceramic PGA
(PGA-401C-A02)
52
MB91265A Series
■ PACKAGE DIMENSION
64-pin plastic LQFP
Lead pitch
0.65 mm
12.0 × 12.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
P-LFQFP64-12×12-0.65
Code
(Reference)
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00 0.20(.551 .008)SQ
*12.00 0.10(.472 .004)SQ
0.145 0.055
(.0057 .0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
0.25(.010)
INDEX
0~8˚
64
17
0.50 0.20
(.020 .008)
0.10 0.10
(.004 .004)
(Stand off)
"A"
1
16
0.60 0.15
(.024 .006)
0.65(.026)
0.32 0.05
(.013 .002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2003 FUJITSU LIMITED F64034S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
53
MB91265A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Changed the name of the series as follows:
MB91265 Series → MB91265A Series
⎯
⎯
Added the following part numbers:
MB91V265A : evaluation product
⎯
⎯
8
■ PIN DESCRIPTION
Changed the description of the function of the X0 pin as follows:
Clock (oscillation) output terminal.
→ Clock (oscillation) input terminal.
Changed the description of the function of the X1 pin as follows:
Clock (oscillation) input terminal.
→ Clock (oscillation) output terminal.
Removed the X0A pin and the X1A pin from the description of the
crystal oscillator circuit.
14 ■ HANDLING DEVICES
■ ELECTRICAL CHARACTERISTICS
47 6. Electrical Characteristics for
the A/D Converter
Changed the units of the zero transition voltage and the full
transition voltage as follows:
LSB → V
Added the following part numbers:
MB91V265ACR-ES
52 ■ ORDERING INFORMATION
The vertical lines marked in the left side of the page show the changes.
54
MB91265A Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
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Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
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Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
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and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
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reaction control in nuclear facility, aircraft flight control, air traffic
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satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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of those products from Japan.
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registered trademarks of their respective owners.
Edited
Business Promotion Dept.
F0701
相关型号：
MB91F267PFM-G
RISC Microcontroller, 32-Bit, FLASH, FR CPU, 33MHz, CMOS, PQFP64, PLASTIC, LQFP-64
FUJITSU
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RISC Microcontroller, 32-Bit, FLASH, FR CPU, 33MHz, CMOS, PQFP64, LEAD FREE, PLASTIC, LQFP-64
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