MB93461-40PB-GE1 [FUJITSU]
FR450 Series VLIW Embedded Microprocessor; FR450系列VLIW嵌入式微处理器
| 型号： | MB93461-40PB-GE1 |
| 厂家： | 
FUJITSU |
| 描述： | FR450 Series VLIW Embedded Microprocessor |
| 文件： | 总68页 (文件大小：964K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-08201-1E
Family
FR450 Series
VLIW Embedded Microprocessor
MB93461
■ DESCRIPTION
MB93461 realizes excellent performance in the field by combining advanced general processing and media
processing for Digital AV equipments such as Television, Advanced Projector, IP TV Phone, Portable Media Player,
etc.
The processor core embedded in MB93461 can combine maximum two instructions out of integer operation
instruction, media instruction, and branch instruction and can issue them in units of VLIW (Very Long Instruction
Word) instruction per cycle. Moreover, peripheral resource modules including MMU (Memory Management
Unit) , SDRAM controller (SDRAMC) , interrupt controller (IRC) , DMA controller (DMAC) , asynchronous transfer
module (UART) , TIMER/COUNTER, general-purpose input/output (GPIO) , video display controller (VDC) , video
capture controller (VCC) , audio interface, serial interface (I2C*) , USB interface (Full Speed Host/Function) ,
Memory Stick interface, and SD-IO interface are embedded in MB93461.
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
■ PACKAGES
420-ball plastic BGA
400-ball plastic PFBGA
(BGA-420P-M25)
(BGA-400P-M04)
MB93461
■ FEATURES
FR450 CPU Core
• 2-way VLIW Processor Core
• Core Frequency : 400 MHz/360 MHz
• MMU is embedded
• Peak Performance (Core Frequency : 400 MHz)
800 MIPS (Integer operation performance) ,
3200 MOPS + 400 MIPS (Media operation performance, 4MAC + Integer)
• 64 32-bit registers (32GR + 32FR)
Cache
• Instruction cache 32 KB (2way) , line size 32 Byte
• Data cache 32 KB (2way) , line size 32 Byte
• Non-blocking cache (Data Cache)
• 64-byte store buffer (Data Cache)
SDRAM interface
• SDRAM compliant with PC133 standard can be connected, Variable 32-bit/16-bit data bus and 4 CS
Local bus interface
• 32-bit address/32-bit, 16-bit, or 8-bit data
• Directly connecting SRAM/ROM, etc. is possible
JTAG
• Boundary scan function compliant with IEEE1149.1 is supported
AV peripheral resource
• Video Display Controller (VDC)
Scan method : progressive/interlace
Horizontal resolution : 320 to 1920 pixels, Vertical resolution : 240 to 1200 pixels
OSD display : Max 1920x1200 pixels , 255/15 colors + transparent
• Video Capture Controller ( VCC )
Scan method : progressive/interlace
Horizontal resolution : 320 to 1920 pixels, Vertical resolution : 240 to 1200 pixels
Reduce Scaler
• Audio output
3-line serial (SPD-IF, I2S, MSB-Justified) , PCM highway, and Digital volume are supported
• Audio input
3-line serial (I2S, MSB-Justified) and PCM highway are supported
• Serial interface (I2C, 2 channels)
Standard transfer (100 Kbps) and high-speed transfer (400 Kbps) are supported
• USB interface
USB 2.0 FS Host/Function
• MS1.4 Interface
• SD-IO interface
• AV-DMAC (8 channels)
• GPIO (32-bit)
(Continued)
2
MB93461
(Continued)
General-purpose peripheral resource
• Interrupt Controller (IRC)
• DMAC (8 channels)
• UART (2 channels)
• Timer (3 channels)
• GPIO (22-bit)
Recommended operation condition and external shape
• Power supply voltage and current
Externally 3.3 V 0.15 V, Internally 1.4 V 0.07 V (at 400 MHz) , Internally 1.3 V 0.065 V (at 360 MHz)
• Operating temperature range from 0 °C to + 70 °C
■ PRODUCT LINEUP
These specifications have indicated four kinds of following products.
1) MB93461PB-GE1
2) MB93461-40PB-GE1
3) MB93461BGL-GE1
4) MB93461-40BGL-GE1
Part number
MB93461PB-GE1 MB93461-40PB-GE1 MB93461BGL-GE1 MB93461-40BGL-GE1
Core Frequency
360 MHz
400 MHz
360 MHz
400 MHz
Voltage external/
internal
3.3 V 0.15 V/
1.3 V 0.065 V
3.3 V 0.15 V/
1.4 V 0.07 V
3.3 V 0.15 V/
1.3 V 0.065 V
3.3 V 0.15 V/
1.4 V 0.07 V
Ta
0 °C to + 70 °C
Package (code)
BGA420 (BGA-420P-M25)
19 °C/W (0 m/s)
PFBGA400 (BGA-400P-M04)
Thermal
resistance
Rth (ja)
42 °C/W (0 m/s)
Remarks
Lead-free Solder ball
3
MB93461
■ PIN ASSIGNMENT
1. BGA420
64 pins from K10 to U17 are for thermal. Connect them to VSS.
INDEX
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
101 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 75
102 193 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 169 74
103 194 277 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 255 168 73
104 195 278 353 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 333 254 167 72
A
B
2
3
4
5
6
7
8
9
C
D
E
105 196 279 354
106 197 280 355
107 198 281 356
108 199 282 357
403 332 253 166 71
402 331 252 165 70
401 330 251 164 69
400 329 250 163 68
399 328 249 162 67
398 327 248 161 66
397 326 247 160 65
396 325 246 159 64
395 324 245 158 63
394 323 244 157 62
393 322 243 156 61
392 321 242 155 60
391 320 241 154 59
390 319 240 153 58
389 318 239 152 57
388 317 238 151 56
F
G
H
J
10 109 200 283 358
11 110 201 284 359
12 111 202 285 360
13 112 203 286 361
14 113 204 287 362
15 114 205 288 363
16 115 206 289 364
17 116 207 290 365
18 117 208 291 366
19 118 209 292 367
20 119 210 293 368
21 120 211 294 369
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
22 121 212 295 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 316 237 150 55
23 122 213 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 236 149 54
24 123 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 148 53
25 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 52
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
(BGA-420P-M25)
4
MB93461
Pin No.
1
Position Pin name
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Position Pin name
Pin No.
73
Position Pin name
A1
B1
N.C.
N.C.
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AE26
AD26
AC26
AB26
AA26
Y26
VSS
DA[0]
DA[1]
DA[4]
DA[9]
DBA[1]
DDQM[3]
DDQ[17]
DDQ[22]
DDQ[25]
DDQ[30]
N.C.
D26
C26
B26
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
N.C.
N.C.
2
74
3
C1
N.C.
75
N.C.
4
D1
N.C.
76
N.C.
5
E1
HPWREN
VCG[0]
VCG[5]
VSS
77
N.C.
6
F1
78
N.C.
7
G1
79
N.C.
8
H1
80
A[23]
9
J1
VCR[1]
VCR[6]
VCB[1]
VCB[6]
VDR[0]
VDR[1]
VDR[6]
VDG[1]
VDG[6]
VDB[1]
VDB[6]
ENABLE
VDE
81
A[26]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
K1
82
VSS
L1
83
BSTREQ#
BSTACK#
BS#
M1
84
N1
N.C.
85
P1
N.C.
86
CS#[1]
CS#[6]
PP[00]
PP[01]
PP[04]
PP[09]
PP[12]
PP[17]
PP[13]
SDCMD
VSS
R1
N.C.
87
T1
N.C.
88
U1
N.C.
89
V1
N.C.
90
W1
Y1
TRST#
VSS
91
92
AA1
AB1
AC1
AD1
AE1
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
PRST#
CMODE[3]
VDD
93
VSS
W26
V26
94
A8
N.C.
95
A7
N.C.
U26
D[2]
96
A6
N.C.
T26
D[7]
97
A5
VDD
N.C.
R26
D[10]
98
A4
N.C.
N.C.
P26
D[15]
99
A3
N.C.
N.C.
N26
D[16]
100
101
102
103
104
105
106
107
108
A2
N.C.
N.C.
M26
D[19]
B2
N.C.
VDD
L26
D[24]
C2
N.C.
DDQ[2]
DDQ[7]
DDQ[9]
DDQ[14]
DCAS#
DCS#[2]
K26
D[27]
D2
N.C.
J26
BE[0]
BCLKO
A[5]
E2
VDD
H26
F2
VDD
G26
G2
VCG[4]
VCVSYNC
VCR[0]
(Continued)
F26
A[8]
H2
E26
A[13]
J2
5
MB93461
Pin No.
109
Position Pin name
Pin No.
143
Position Pin name
Pin No.
177
Position Pin name
K2
L2
VCR[5]
VCB[0]
AE21
AE22
DDQ[26]
DDQ[31]
B18
B17
A[31]
WE#
110
144
178
TEST-
MODE
111
M2
VCB[5]
145
AE23
179
B16
CS#[0]
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
N2
P2
VCB[7]
VDR[2]
VDR[7]
VDG[2]
VDG[7]
VDB[2]
VDB[7]
TOPFIELD
DISABLE
VDE
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
AE24
AE25
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
N.C.
N.C.
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
B15
B14
B13
B12
B11
B10
B9
CS#[5]
CPUHOLD
PP[02]
PP[05]
PP[10]
PP[15]
PP[20]
PP[16]
SDDAT[0]
SDCKI
USCKI
UDM
R2
N.C.
T2
N.C.
U2
TMS
ED
V2
W2
VDE
Y2
CMODE[2]
CLKIN
D[1]
B8
AA2
AB2
AC2
AD2
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
B7
B6
N.C.
D[6]
B5
N.C.
R25
P25
N25
M25
L25
D[9]
B4
N.C.
D[14]
D[17]
D[20]
D[25]
D[28]
BE[1]
BE[3]
A[6]
B3
N.C.
N.C.
C3
D3
E3
N.C.
SDA[1]
VSS
VDE
VSS
DDQ[1]
DDQ[6]
DDQ[8]
DDQ[13]
DWE#
DCS#[1]
DCLKFB
DRAS#
DA[2]
K25
J25
F3
VDE
G3
H3
J3
VCG[3]
VCHSYNC
VDD
H25
G25
F25
A[9]
K3
VCR[4]
VCR[7]
VCB[4]
VSS
E25
D25
C25
B25
B24
B23
B22
B21
A[14]
A[16]
N.C.
L3
M3
N3
P3
N.C.
VDR[3]
VDG[0]
VDG[3]
VDB[0]
VDB[3]
DA[5]
N.C.
R3
T3
DA[10]
DA[11]
DDQ[16]
N.C.
A[22]
A[25]
U3
V3
VDCLK-
OUT
141
142
AE19
AE20
DDQ[18]
DDQ[23]
175
176
B20
B19
A[30]
IBW
209
210
W3
Y3
VDD
(Continued)
6
MB93461
Pin No.
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
Position Pin name
Pin No.
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
Position Pin name
Pin No.
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
Position Pin name
AA3
AB3
FSCKI
LRCKI
SDO
N24
M24
L24
K24
J24
H24
G24
F24
E24
D24
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
D[18]
D[21]
H4
J4
VCG[7]
VDE
AC3
D[26]
K4
VCR[3]
VDE
AD3
N.C.
D[29]
L4
AD4
SDA[0]
SCL[1]
DDQ[0]
DDQ[5]
VDD
BE[2]
A[2]
M4
VCB[3]
VDE
AD5
N4
AD6
A[7]
P4
VDR[4]
VSS
AD7
A[10]
R4
AD8
A[15]
T4
VDG[4]
VSS
AD9
DDQ[12]
DDQ[15]
DCS#[0]
VSS
A[17]
U4
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AC24
AB24
AA24
N.C.
V4
VDB[4]
VDHSYNC
VSS
A[19]
W4
A[21]
Y4
DCS#[3]
DA[3]
A[24]
AA4
AB4
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
SDI
A[29]
BCKO
VDE
DA[6]
BREQ#
VDE
DBA[0]
DA[12]
VSS
SCL[0]
VDE
RD#
BGNT#
CS#[4]
CS#[7]
PP[03]
PP[06]
PP[11]
PP[18]
PP[21]
SDCLK
SDDAT[1]
DDQ[4]
VDE
DDQ[19]
DDQ[24]
DDQ[27]
VSS
DDQ[11]
VDE
DDQM[1]
DCLK
VSS
TDC
N.C.
TDO
VSS
TDI
C8
DA[7]
VSS
ERST#
C7
RAM-
BOOT#
239
Y24
274
C6
VDE
309
AC17
DCKE
240
241
242
243
244
W24
V24
U24
T24
R24
CMODE[1]
VSS
275
276
277
278
279
C5
C4
D4
E4
F4
VDD
UDP
VDE
310
311
312
313
314
AC18
AC19
AC20
AC21
AC22
VDE
DDQ[20]
VSS
D[0]
D[5]
UDM1
VSS
DDQ[28]
VDE
D[8]
MTEST-
MODE
245
P24
D[13]
280
G4
VCG[2]
315
AC23
(Continued)
7
MB93461
Pin No.
316
Position Pin name
Pin No.
349
Position Pin name
Pin No.
382
Position Pin name
AB23
AA23
Y23
TCK
HRST#
VSS
D8
D7
D6
D5
E5
SDWP
SDDAT[2]
SDCD
AB17
AB18
AB19
AB20
AB21
DDQM[2]
VDD
317
350
383
318
351
384
DDQ[21]
VDE
319
W23
V23
CMODE[0]
VSS
352
VSS
385
320
353
UDP1
386
DDQ[29]
HOVR-
CUR#
321
U23
RSTOUT#
354
F5
387
AB22
VDD
322
323
T23
R23
D[4]
355
356
G5
H5
VCG[1]
VCG[6]
388
389
AA22
Y22
ECV
VDE
ECLK
VCD-
CLKIN
324
P23
D[12]
357
J5
390
W22
VDD
325
326
327
328
329
330
331
332
333
334
N23
M23
L23
K23
J23
VSS
D[22]
VSS
D[30]
VSS
A[3]
358
359
360
361
362
363
364
365
366
367
K5
L5
VCR[2]
VSS
391*
392
393
394
395
396
397
398
399
400
V22
U22
T22
R22
P22
N22
M22
L22
K22
J22
VDD
VDE
D[3]
M5
N5
P5
R5
T5
U5
V5
W5
VCB[2]
VSS
VSS
D[11]
VDE
D[23]
VDE
D[31]
VDE
VDR[5]
VDE
H23
G23
F23
E23
D23
VSS
A[11]
VSS
A[18]
VDG[5]
VDE
VDB[5]
VDVSYNC
VDP-
CLKIN
335
D22
A[20]
368
Y5
401
H22
A[4]
336
337
338
339
340
341
342
343
344
345
346
347
348
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
VDE
A[28]
ERR#
VDD
369
370
371
372
373
374
375
376
377
378*
379
380
381
AA5
AB5
BCKI
LRCKO
VSS
402
403
404
405
406
407
408
409
410
411
412
413
414
G22
F22
E22
E21
E20
E19
E18
E17
E16
E15
E14
E13
E12
VDE
A[12]
VDD
VSS
A[27]
VDD
VSS
DIR
AB6
AB7
DDQ[3]
VSS
RDY#
VDE
AB8
AB9
DDQ[10]
VSS
CS#[3]
VDE
AB10
AB11
AB12
AB13
AB14
AB15
AB16
DDQM[0]
VDD
VSS
VSS
CS#[2]
VSS
VDE
PP[07]
VSS
VDD
VDE
PP[19]
VSS
DA[8]
VDE
PP[08]
(Continued)
8
MB93461
(Continued)
Pin No.
Position Pin name
415
416
417
418
419
E11
E10
E9
VDE
PP[14]
VDD
E8
MSDIRP
SDDAT[3]
E7
SDMSSE-
LECT
420
E6
* : Pin No. 378 and 391 are the analog power supply pins of PLL.
9
MB93461
2. PFBGA400
81 pins from L11 to W19 are for thermal. Connect them to VSS.
(TOP VIEW)
INDEX
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 14 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
1
2
3
4
5
6
7
8
9
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
113 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 84
114 217 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 190 83
115 218 313 400 399 398 397 396 395 394 393 392 391 390 389 388 397 386 385 384 383 382 381 380 379 288 189 82
C
D
E
116 219 314
117 220 315
118 221 316
119 222 317
120 223 318
378 287 188 81
377 286 187 80
376 285 186 79
375 284 185 78
374 283 184 77
373 282 183 76
372 281 182 75
371 280 181 74
370 279 180 73
369 278 179 72
368 277 178 71
367 276 177 70
366 275 176 69
365 274 175 68
364 273 174 67
363 272 173 66
362 271 172 65
361 270 171 64
360 269 170 63
359 268 169 62
358 267 168 61
F
G
H
J
K
10 121 224 319
11 122 225 320
12 123 226 321
13 124 227 322
14 125 228 323
15 126 229 324
16 127 230 325
17 128 231 326
18 129 232 327
19 130 233 328
20 131 234 329
21 132 235 330
22 133 236 331
23 134 237 332
24 135 238 333
25 136 239 334
L
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
26 137 240 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 266 167 60
27 138 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 166 59
28 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 58
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
(BGA-400P-M04)
10
MB93461
Pin No.
Position Pin name
Pin No.
35
Position Pin name
Pin No.
69
Position Pin name
1
2
3
4
5
6
7
A1
B1
C1
D1
E1
F1
G1
N.C.
N.C.
AJ7
AJ8
VDE
DDQ[10]
DDQ[14]
DWE#
DCS#[0]
DCLK
U29
T29
R29
P29
N29
M29
L29
D[12]
D[16]
VDE
36
70
UDP1
37
AJ9
71
HPWREN
VDD
38
AJ10
AJ11
AJ12
AJ13
72
D[22]
D[26]
D[28]
BE[0]
39
73
VCG[3]
VCG[7]
40
74
41*
VDD
75
VCD-
CLKIN
8
H1
42
AJ14
DA[0]
76
K29
VDE
9
J1
K1
L1
VCR[1]
VCR[5]
VCR[7]
VCB[3]
VSS
43
44
45
46
47
48
49
50
51
52
53
54
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
VSS
DA[6]
77
78
79
80
81
82
83
84
85
86
87
88
J29
H29
G29
F29
E29
D29
C29
B29
A29
A28
A27
A26
A[3]
A[7]
10
11
12
13
14
15
16
17
18
19
20
DA[10]
DBA[1]
DDQM[2]
VDE
A[9]
M1
N1
P1
R1
T1
U1
V1
W1
Y1
A[13]
VDD
A[18]
N.C.
N.C.
N.C.
N.C.
A[20]
VSS
VDR[0]
VDR[4]
VDG[0]
VDG[2]
VDG[6]
VDE
DDQ[19]
DDQ[23]
DDQ[25]
DDQ[29]
VDE
VDB[4]
TDC
VDCLK-
OUT
21
AA1
55
AJ27
N.C.
89
A25
A[26]
22
23
24
25
26
27
28
29
30
31
32
33
34
AB1
AC1
AD1
AE1
AF1
AG1
AH1
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
TOPFIELD
VDE
56
57
58
59
60
61
62
63
64
65
66
67
68
AJ28
AJ29
AH29
AG29
AF29
AE29
AD29
AC29
AB29
AA29
Y29
N.C.
N.C.
90
91
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A[30]
BREQ#
VDD
BCKI
N.C.
92
BCKO
N.C.
TCK
93
DIR
ECV
94
BS#
N.C.
VSS
95
CS#[0]
CS#[4]
VDE
N.C.
VDE
96
N.C.
CMODE[1]
VSS
97
N.C.
98
PP[01]
VDE
SDA[1]
VDD
VDE
99
D[2]
100
101
102
PP[07]
PP[11]
DDQ[1]
DDQ[5]
W29
D[6]
V29
D[8]
PP[15]
(Continued)
11
MB93461
Pin No.
Position Pin name
Pin No.
Position Pin name
Pin No.
Position Pin name
RAM-
AD28
103
A11
PP[17]
136
AE2
LRCKI
169
BOOT#
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
A10
A9
A8
A7
A6
A5
A4
A3
A2
B2
C2
D2
E2
F2
G2
H2
J2
VDD
SDWP
SDDAT[1]
SDCKI
VDD
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
AF2
AG2
SDO
N.C.
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
AC28
AB28*
AA28
Y28
W28
V28
U28
T28
CMODE[0]
VDD
VDD
D[1]
AH2
N.C.
AH3
SDA[0]
VSS
AH4
D[5]
UDM
AH5
DDQ[0]
DDQ[4]
VSS
VDE
D[11]
D[15]
VSS
N.C.
AH6
N.C.
AH7
N.C.
AH8
DDQ[9]
DDQ[13]
DDQ[15]
DDQM[1]
VDD
R28
P28
N28
M28
L28
N.C.
AH9
D[21]
D[25]
D[27]
D[31]
VSS
VDE
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
VDD
VDE
VCG[2]
VCG[6]
VSS
VSS
K28
J28
DRAS#
DA[3]
A[2]
H28
G28
F28
A[6]
VCR[0]
VCR[4]
VDE
DA[5]
A[8]
K2
L2
DA[9]
A[12]
VSS
VDE
E28
D28
C28
B28
B27
B26
B25
B24
M2
N2
P2
R2
T2
U2
V2
VCB[2]
VCB[6]
VCB[7]
VDR[3]
VDR[7]
VDG[1]
VDG[5]
DCKE
VSS
A[17]
N.C.
DDQ[18]
DDQ[22]
VDE
N.C.
A[19]
A[23]
A[25]
A[29]
DDQ[28]
VSS
TEST-
MODE
130
W2
VSS
163
AH26
196
B23
ERR#
131
132
133
Y2
VDB[3]
VDB[7]
164
165
166
AH27
AH28
AG28
N.C.
N.C.
TDO
197
198
199
B22
B21
B20
VSS
BSTACK#
WE#
AA2
AB2
ENABLE
VDP-
CLKIN
134
135
AC2
AD2
167
168
AF28
AE28
TRST#
ED
200
201
B19
B18
BGNT#
SDI
CS#[3]
(Continued)
12
MB93461
Pin No.
202
203
204
205
206
207
208
209
210
211
212
Position Pin name
Pin No.
236
237
238
239
240
241
242
243
244
245
246
Position Pin name
Pin No.
270
271
272
273
274
275
276
277
278
279
280
Position Pin name
B17
B16
B15
B14
B13
B12
B11
B10
B9
VSS
PP[00]
VSS
AB3
AC3
AD3
AE3
AF3
AG3
AG4
AG5
AG6
AG7
AG8
VDVSYNC
VSS
AB27
AA27
Y27
W27
V27
U27
T27
CMODE[3]
CLKIN
D[0]
FSCKI
VDE
PP[06]
PP[10]
PP[12]
PP[14]
VSS
D[4]
LRCKO
VDE
VSS
D[10]
D[14]
D[18]
D[20]
D[24]
VDE
SCL[1]
VDE
R27
P27
N27
M27
SDCLK
SDDAT[0]
VSS
DDQ[3]
DDQ[7]
DDQ[8]
B8
B7
SDMSSE-
LECT
213
B6
247
AG9
DDQ[12]
281
L27
D[30]
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
B5
B4
B3
C3
D3
E3
F3
G3
H3
J3
VSS
VDE
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
VDE
DDQM[0]
DCS#[2]
DCLKFB
DCS#[3]
DA[2]
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
K27
J27
BE[2]
BE[3]
A[5]
N.C.
H27
G27
F27
E27
D27
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
N.C.
VDE
VSS
A[11]
A[15]
A[16]
N.C.
VSS
VCG[1]
VCG[5]
VCVSYNC
VDD
DA[4]
DA[8]
VSS
A[22]
A[24]
A[28]
VDD
DA[12]
DDQ[16]
DDQ[17]
DDQ[21]
VSS
K3
L3
VCR[3]
VSS
M3
N3
P3
R3
T3
VCB[1]
VCB[5]
VSS
BSTREQ#
A[31]
RD#
DDQ[27]
DDQ[31]
VDD
VDR[2]
VDR[6]
VDE
CS#[2]
MTEST-
MODE
231
U3
VDE
265
AG27
299
C17
CS#[6]
232
233
234
235
V3
W3
Y3
VDG[4]
VDB[0]
VDB[2]
VDB[6]
266
267
268
269
AF27
AE27
AD27
AC27
TMS
ERST#
VSS
300
301
302
303
C16
C15
C14
C13
CPUHOLD
PP[03]
PP[05]
AA3
VDD
PP[09]
(Continued)
13
MB93461
(Continued)
Pin No.
304
305
306
307
308
309
310
311
312
313
Position Pin name
Pin No.
338
339
340
341
342
343
344
345
346
347
Position Pin name
Pin No.
372
373
374
375
376
377
378
379
380
381
Position Pin name
C12
C11
C10
C9
VDE
PP[19]
PP[21]
PP[16]
SDCMD
SDDAT[3]
SDCD
VDD
AF7
AF8
DDQ[6]
VDD
L26
K26
J26
D[29]
BE[1]
BCLKO
A[4]
AF9
DDQ[11]
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
H26
G26
F26
E26
D26
D25
D24
C8
DCAS#
DCS#[1]
VSS
VSS
C7
A[10]
A[14]
A[21]
VDE
C6
C5
VSS
C4
UDP
DA[1]
VDE
D4
UDM1
A[27]
HOVR-
CUR#
314
E4
348
AF17
DA[7]
382
D23
VSS
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
F4
G4
H4
J4
VCG[0]
VCG[4]
VCHSYNC
VDE
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AE26
AD26
AC26
AB26
AA26
Y26
DBA[0]
DA[11]
DDQM[3]
VDD
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
IBW
VDE
RDY#
VSS
K4
VCR[2]
VCR[6]
VCB[0]
VCB[4]
VDE
DDQ[20]
DDQ[24]
DDQ[26]
DDQ[30]
TDI
CS#[1]
CS#[5]
CS#[7]
PP[02]
PP[04]
PP[08]
VSS
L4
M4
N4
P4
R4
T4
VDR[1]
VDR[5]
VSS
HRST#
ECLK
U4
V4
PRST#
CMODE[2]
VSS
PP[18]
PP[20]
PP[13]
MSDIRP
SDDAT[2]
VDE
VDG[3]
VDG[7]
VDB[1]
VDB[5]
VDHSYNC
VDD
W4
Y4
RSTOUT#
D[3]
D8
AA4
AB4
AC4
W26
D7
V26
D[7]
D6
U26
D[9]
D5
USCKI
VDCDIS-
ABLE
333
AD4
367
T26
D[13]
334
335
336
337
AE4
AF4
AF5
AF6
VSS
SCL[0]
VSS
368
369
370
371
R26
P26
N26
M26
D[17]
D[19]
D[23]
VSS
DDQ[2]
* : Pin No. 41 and 171 are the analog power supply pins of PLL.
14
MB93461
■ PIN DESCRIPTION
1. Format
Pin No.
Pin name
Direction
Type
BS
Description
Pin name : Indicates name of external pin
If several signals share the same pin, the names are separated by a slash (/) .
“# ” in a signal line name indicates “active low.”
Direction : Indicates I/O of signal with reference to LSI chip
Input : Indicates pin for input signal to LSI chip
Output : Indicates pin for output signal from LSI chip
Input/output : Indicates pin for bidirectional signal
Type : Indicates pin input/output circuit type
Each symbol has the following meaning :
Symbol
Description
Solid Drive
SD
Type of output pin. Normal output. The pin never becomes high impedance.
Tri-State
TS
PU
PD
OD
Type of output or input/output pin. The pin may become high impedance.
Pull-up
Type of input pin or input/output pin. A pull-up resistor is built into the circuit.
Pull-down
Type of input pin or input/output pin. A pull-down resistor is built into the circuit.
Open-drain
Type of output pin. The pin may become high impedance.
Note : Explains outline of function and relationship with other pins.
BS : Indicates whether the target of boundary-scan or not.
15
MB93461
2. Local Bus Interface
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Bus Request
261
264
91
BREQ#
BGNT#
Input
⎯
Yes This signal inputs a bus release request from
the bus master device.
Bus Grant
200
Output
SD
Yes This signal indicates that the local bus is
released.
177
175
260
337
406
81
174
259
80
173
258
335
257
334
255
168
254
167
72
403
332
253
166
71
295
90
195
292
381
89
194
291
193
290
379
87
A[31]
A[30]
A[29]
A[28]
A[27]
A[26]
A[25]
A[24]
A[23]
A[22]
A[21]
A[20]
A[19]
A[18]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
192
82
Address
189
288
287
378
80
187
286
377
79
186
78
185
284
375
77
Input/
output
A word address is output.
When the local bus is released, this pin
TS
Yes
becomes input.
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
252
165
70
401
330
251
184
(Continued)
16
MB93461
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
399
328
249
162
67
248
161
66
397
326
247
160
65
246
159
64
182
281
372
74
181
73
180
279
370
72
179
278
369
277
368
70
177
276
367
69
176
275
366
68
365
67
174
273
364
66
D[31]
D[30]
D[29]
D[28]
D[27]
D[26]
D[25]
D[24]
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
Data
This is the data bus; D[31] is MSB.
When connecting a 16-bit slave device to this
signal, connect it to D[31 : 16] (higher) .
Input/
TS
Yes When connecting a 8-bit slave device to this
signal, connect it to D[31 : 24] (higher) .
If all of the CS# that allowed to assert are con-
figured to 8-bit or 16-bit (by LCR0-7.BW) ,
D[15 : 00] are not driven.
63
output
158
245
324
395
62
157
244
61
156
243
322
393
60
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
155
242
173
272
D[1]
D[0]
(Continued)
17
MB93461
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Byte Enable
This specifies byte lanes for data transfer.
The correspondence between this signal and
the data bus when accessing the 32-bit slave
device is shown below (The CS area can be
set only to the big endian (LCRx.LE = 0) .) :
BE[0] → D [31 : 24]
BE[1] → D [23 : 16]
BE[2] → D [15 : 08]
BE[3] → D [07 : 00]
BE[0 : 1] is used to access a 16-bit slave de-
vice; the correspondence between this signal
and the data bus is shown below :
1) The CS area set to big endian (LCRx.LE
= 0)
BE[0] → D [31 : 24] (higher byte)
BE[1] → D [23 : 16] (lower byte)
2) The CS area set to little endian (LCRx.LE
= 1)
BE[0] → D [23 : 16] (higher byte)
BE[1] → D [31 : 24] (lower byte)
BE[2] is used to access halfword address.
BE[2] → A[1]
68
75
BE[0]/BE#[0]
BE[1]/BE#[1]
BE[2]/BE#[2]
BE[3]/BE#[3]
163
250
164
373
282
283
Input/
TS
Yes
output
BE[0] is used to access a 8-bit slave device;
the correspondence between this signal and
the data bus is shown below :
BE[0] → D [31 : 24]
BE[2 : 3] is used to access byte address.
BE[2] → A[1]
BE[3] → A[0]
These pins become input when the bus is re-
leased. To access this LSI as the slave de-
vice when this bus is released, it must be
treated as a 32-bit slave device.
BE[0] must be pulled-down/pulled-up accord-
ing to BE/#BE polarity (When RSTOUT# is
asserted, the value of BE[0] is reflected in
LGCR.BED) .
Bus Cycle Start
This is asserted for only 1 CLKIN cycle at the
Yes beginning of a bus cycle to indicate the start
of the bus cycle.
Input/
TS
85
94
BS#
RD#
output
This pin is input when the bus is released.
Read
This pin is asserted during the second or later
Yes CLKIN cycles of read local bus cycles.
This pin becomes high impedance when the
local bus is released.
263
296
Output
TS
(Continued)
18
MB93461
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Write Enable
This pin is asserted during a write cycles. It
can be used as a strobe pulse for write data.
This pin becomes high impedance when the
bus is released.
178
199
WE#
Output
TS
Yes
Direction
Indicates transfer direction of D[31 : 00] pins
L : input (read) , H : output (write)
This pin becomes input when the bus is re-
leased. This LSI determines whether the lo-
cal bus cycles that performed by external
devices are reads or writes, based on the
DIR signal.
Input/
output
409
93
DIR
TS
Yes
This pin becomes “L” when bus is idle.
Ready
This pin is in the input state while the bus is
not released; the bus cycle completion no-
tice is “input” from the slave device to this
pin.
This pin becomes output while this LSI is op-
erating as the slave bus when the bus re-
leased; it notifies the bus master device of
the bus cycle completion.
Input/
output
340
385
RDY#
TS
Yes
When RSTOUT# is asserted, the value of
RDY# is reflected in LCR0.RC.
Error
This is sampled at the end of the bus cycle;
the error notice is input from the slave de-
vice to this pin.
338
196
ERR#
Input
⎯
Yes
Yes
This pin is ignored when the bus is released.
Chip Select
This signal selects slave device under con-
trol of MB93461.
The corresponding address is determined
from the settings of the programmable ad-
dress decoder built into MB93461.
Connect the boot ROM to the CS#[0] pin.
342
411
86
201
298
387
95
CS#[3]
CS#[2]
CS#[1]
CS#[0]
Output
SD
179
Chip Select/Interrupt Request 7-4
This signal is used as chip select or interrupt
request. Chip select selects slave device
under control of this LSI. This signal works
as IRQ#[7 : 4] after power-on reset and
need to set LGCR.CSE to use as CS#.
When use as CS#, the corresponding ad-
dress is determined from the setting of the
programmable address decoder built into
this LSI.
266
87
180
265
389
299
388
96
CS#[7]/IRQ#[7]
CS#[6]/IRQ#[6]
CS#[5]/IRQ#[5]
CS#[4]/IRQ#[4]
Input/
output
TS/
PU
Yes
(Continued)
19
MB93461
(Continued)
Pin No.
Pin name
Direction Type BS
Description
BGA PFBGA
Initial Bus Width
This pin is used to specify the data bus width of
the boot ROM to be connected to the CS#[0] pin.
176
383
IBW
Input
⎯
Yes The data bus width specified for this signal can
be changed later via software.
16 bits : Input low level
32 bits : Input high level
Input/
output
Burst Request
This pin is used to request burst transfer.
83
84
294
198
BSTREQ#
BSTACK#
TS
TS
Yes
Input/
output
Burst Acknowledge
Yes
This pin is used to enable burst transfer.
Bus Clock Out
This clock is supplied to the device connected
with the local bus.
69
374
BCLKO
Output
SD
Yes
Output stops during power-on reset.
20
MB93461
3. SDRAM Interface
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Chip Select
224
36
133
222
252
250
343
39
DCS#[3]
DCS#[2]
DCS#[1]
DCS#[0]
This signal is output based on the setting of the
programmable address decoder incorporated
in this LSI.
DCS#[2] and DCS#[3] are only used for con-
necting the 168-pin registered DIMM.
Output
Output
SD
SD
Yes
Yes
42
227
46
349
DBA[1]
DBA[0]
Bank Address
The bank address is output.
228
139
138
41
380
307
226
137
40
257
350
45
154
255
348
44
153
254
152
253
346
42
DA[12]
DA[11]
DA[10]
DA[9]
DA[8]
DA[7]
DA[6]
DA[5]
DA[4]
DA[3]
DA[2]
DA[1]
DA[0]
Multiplexed Address
The address multiplexed for SDRAM is output.
Output
SD
Yes
225
136
39
38
Row Address Strobe
Row Address Strobe signal to SDRAM.
135
35
151
342
38
DRAS#
DCAS#
DWE#
DCKE
Output
Output
Output
Output
SD
SD
SD
SD
Yes
Yes
Yes
Yes
Column Address Strobe
Column Address Strobe signal to SDRAM.
Write Enable
Write Enable signal to SDRAM.
132
309
Clock Enable
Clock Enable signal to SDRAM.
156
Data Mask
These pins (signal) are combined with other
signals to specify the byte lane to be written.
At read, all the bits are driven Low.
The correspondence between this signal and
the data bus when connecting 32-bit SDRAM is
shown below :
376
303
382
43
249
148
47
DDQM[0]
DDQM[1]
DDQM[2]
DDQM[3]
DDQM[0] → DDQ[31 : 24]
Output
SD
Yes
DDQM[1] → DDQ[23 : 16]
351
DDQM[2] → DDQ[15 : 08]
DDQM[3] → DDQ[07 : 00]
The correspondence between this signal and
the data bus when connecting 16-bit SDRAM is
shown below :
DDQM[0] → DDQ[31 : 24]
DDQM[1] → DDQ[23 : 16]
(Continued)
21
MB93461
(Continued)
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
144
47
263
356
52
161
262
355
51
354
50
159
260
353
49
158
259
258
147
37
146
247
340
36
145
246
245
338
34
143
244
337
33
DDQ[31]
DDQ[30]
DDQ[29]
DDQ[28]
DDQ[27]
DDQ[26]
DDQ[25]
DDQ[24]
DDQ[23]
DDQ[22]
DDQ[21]
DDQ[20]
DDQ[19]
DDQ[18]
DDQ[17]
DDQ[16]
DDQ[15]
DDQ[14]
DDQ[13]
DDQ[12]
DDQ[11]
DDQ[10]
DDQ[9]
386
313
232
143
46
231
142
45
384
311
230
141
44
140
221
34
Data
This signal is connected to the SDRAM data
bus; DDQ[31] is MSB.
Input/
TS
When connecting 16-bit SDRAM, connect it to
DDQ[31 : 16]
Yes
output
When the bus width is set to 16 bits by
DCFG.BW, DDQ[15 : 00] is fixed to the high-im-
pedance state.
131
220
301
374
33
130
32
DDQ[8]
DDQ[7]
DDQ[6]
DDQ[5]
DDQ[4]
DDQ[3]
DDQ[2]
DDQ[1]
129
218
299
372
31
128
217
142
DDQ[0]
SDRAM Clock
This is the output of the clock signal supplied to
SDRAM.
The output is halted while the PLL is halted.
The output is also halted during a power-on re-
set.
304
134
40
DCLK
Output
Input
SD
Yes
Feedback for SDRAM Clock
Yes To adjust the DCLK phase, feedback input to
the PLL built into this LSI chip.
251
DCLKFB
⎯
22
MB93461
4. General-purpose Peripheral Resource
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
88
89
182
267
203
98
390
301
IRQ#[0]/PP[00]
IRQ#[1]/PP[01]
IRQ#[2]/PP[02]
IRQ#[3]/PP[03]
Interrupt Request 0 to 3/GPIO 0 to 3
Yes These pins are used as the interrupt input
and as a general-purpose I/O port (GPIO) .
Input/
output
TS
Timer ch 0 Output/Timer ch 0 Gate/GPIO 4
Yes This pin is used as the timer ch 0 pin and as
a general-purpose I/O port (GPIO) .
TOUT[0]/
GATE[0]/PP[04]
Input/
output
90
391
302
TS
TS
Timer ch 1 Output/Timer ch 1 Gate/GPIO 5
Yes This pin is used as the timer ch 1 pin and as
a general-purpose I/O port (GPIO) .
TOUT[1]/
GATE[1]/PP[05]
Input/
output
183
UART ch 0 Receive Data/GPIO 6
Input/
output
This pin is used as the UART ch 0 receive
data and as a general-purpose I/O port
(GPIO) .
268
345
414
91
205
100
392
303
206
101
207
396
RXD[0]/PP[06]
TXD[0]/PP[07]
CTS#[0]/PP[08]
RTS#[0]/PP[09]
RXD[1]/PP[10]
TXD[1]/PP[11]
DREQ#[0]/PP[12]
DACK#[0]/PP[13]
TS
TS
TS
TS
TS
TS
TS
TS
Yes
UART ch 0 Transmit Data/GPIO 7
This pin is used as the UART ch 0 transmit
data and as a general-purpose I/O port
(GPIO) .
Input/
output
Yes
UART ch 0 Clear To Send Signal/GPIO 8
This pin is used as the UART ch 0 CTS sig-
nal and as a general-purpose I/O port
(GPIO) .
Input/
output
Yes
UART ch 0 Request To Send Signal/GPIO 9
This pin is used as the UART ch 0 RTS sig-
nal and as a general-purpose I/O port
(GPIO) .
Input/
output
Yes
UART ch 1 Receive Data/GPIO 10
This pin is used as the UART ch 1 receive
data and as a general-purpose I/O port
(GPIO) .
Input/
output
184
269
92
Yes
UART ch 1 Transmit Data/GPIO 11
This pin is used as the UART ch 1 transmit
data and as a general-purpose I/O port
(GPIO) .
Input/
output
Yes
DMAC ch 0 Transfer Request/GPIO 12
This pin is used as the UART ch 0 transfer
request and as a general-purpose I/O port
(GPIO) .
Input/
output
Yes
DMAC ch 0 Acknowledge/GPIO 13
This pin is used as the DMAC ch 0 transfer
acknowledge signal and as a general-pur-
Input/
output
94
Yes
pose I/O port (GPIO) .
(Continued)
23
MB93461
(Continued)
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
DMAC ch 0 Transfer Done/DMAC ch4
Transfer Request/GPIO 14
DONE#[0]/
DREQ#[4]/PP[14] output
Input/
TS
This pin is used as the DMAC ch 0 transfer
end signal, as the DMAC ch 4 transfer re-
quest, and as a general-purpose I/O port
(GPIO) .
416
208
Yes
DMAC ch 1 Transfer Request/GPIO 15
This pin is used as the DMAC ch 1 transfer
request and as a general-purpose I/O port
(GPIO) .
Input/
DREQ#[1]/PP[15]
output
185
187
102
307
TS
TS
Yes
Yes
DMAC ch 1 Acknowledge/GPIO 16
This pin is used as the DMAC ch 1 transfer
acknowledge signal and as a general-pur-
pose I/O port (GPIO) .
Input/
DACK#[1]/PP[16]
output
DMAC ch 1 Transfer Done/DMAC ch 5
Transfer Request/GPIO 17
This pin is used as the DMAC ch 1 transfer
end signal, as the DMAC ch 5 transfer re-
quest, and as a general-purpose I/O port
(GPIO) .
DONE#[1]/
Input/
93
103
DREQ#[5]/
output
TS
Yes
PP[17]
DMAC ch 2 Transfer Request/GPIO 18
This pin is used as the DMAC ch 2 transfer
request and as a general-purpose I/O port
(GPIO) .
Input/
DREQ#[2]/PP[18]
output
270
347
394
305
TS
TS
Yes
Yes
DMAC ch 3 Transfer Request/GPIO 19
This pin is used as the DMAC ch 3 transfer
request and as a general-purpose I/O port
(GPIO) .
Input/
DREQ#[3]/PP[19]
output
DMAC ch 2 Transfer Acknowledge/DMAC
ch 6 Transfer Request/GPIO 20
This pin is used as the DMAC ch 2 transfer
acknowledge signal, as the DMAC ch 6
transfer request, and as a general-purpose
I/O port (GPIO) .
DACK#[2]/
Input/
186
271
395
306
DREQ#[6]/
output
TS
TS
Yes
Yes
PP[20]
DMAC ch 3 Transfer Acknowledge/DMAC
ch 7 Transfer Request/GPIO 21
This pin is used as the DMAC ch 3 transfer
acknowledge signal, as the DMAC ch 7
transfer request, and as a general-purpose
I/O port (GPIO) .
DACK#[3]/
Input/
DREQ#[7]/
output
PP[21]
24
MB93461
5. ICE Interface
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
ESB Reset
For the printed circuit board using the ICE,
connect the connector intended for the ICE to
this pin; for the printed circuit board not using
the ICE, open this pin.
238
267
ERST#
Input
PD
Yes
Hard Reset
This is the reset input dedicated to the ICE.
This pin function is equivalent to reset by the
debugger hardware reset command. Reset
by this pin will not reset debug related set-
tings, so this pin can be used for debugging
the reset sequence, etc.
317
358
HRST#
Input
⎯
Yes
When using this pin, connect the reset switch
signal to this pin; when not using this pin, fix it
to the High level.
ESB Command Valid
Command valid signal for ICE interface.
For the printed circuit board using the ICE,
connect the connector intended for the ICE to
this pin; for the printed circuit board not using
the ICE, open this pin.
388
151
389
60
ECV
ED
Input
PU
Yes
Yes
Yes
ESB Data
Data I/O signal for ICE interface.
For the printed circuit board using the ICE,
connect the connector intended for the ICE to
this pin; for the printed circuit board not using
the ICE, open this pin.
Input/
output
TS/
PD
168
359
ESB Clock
Clock signal (output) for ICE interface.
For the printed circuit board using the ICE,
connect the connector intended for the ICE to
this pin; for the printed circuit board not using
the ICE, open this pin.
ECLK
Output
TS
25
MB93461
6. Reset-related Pin
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Power-on Reset
This is the level trigger initialization signal.
Apply the L level to this pin for 16 CLKIN clock
cycles or more. This pin is used to cause a
power-on reset; it initializes all registers and
sequencers except cache and GR/FR.
57
360
PRST#
Input
⎯
Yes
Reset Output
This signal is asserted during a power-on re-
set.
The power-on reset operation is prolonged in
the LSI until the oscillation stabilization wait
time for the internal PLL has elapsed. Conse-
quently, use this signal to detect that the pow-
er-on reset operation has been completed in
the LSI.
321
363
RSTOUT#
Output
SD
Yes
When HRST# is asserted with the ICE used,
this signal (RSTOUT#) is asserted as in the
power-on reset.
RAM Boot
A software reset can be caused by applying a
Low level to this pin.
When this signal and the PRST# pin are as-
serted simultaneously, the power-on reset op-
eration is preferred.
At a power-on reset, the level input to this pin
is reflected in the SA bit of the register HSR0,
and then the reset vector address is deter-
mined as shown below based on the SA bit.
Low level : 0x00000000
239
169
RAMBOOT#
Input
⎯
Yes
High level : 0xFF000000
7. CPU Status
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
CPU Hold
181
300
CPUHOLD
Output
SD
Yes
Signal indicating that CPU stops in hold state.
26
MB93461
8. Clock
Pin No.
BGA PFBGA
Pin name
Direction Type
BS
Description
Clock Input
External clock are input to this pin.
154
271
CLKIN
Input
Input
⎯
⎯
Yes
58
270
361
63
CMODE[3]
CMODE[2]
CMODE[1]
CMODE[0]
Clock Mode
Determines operating frequency of each sec-
tion in LSI.
153
240
319
Yes
170
9. Pin Related to JTAG
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Test Data Input
237
236
357
166
TDI
Input
PU
TS
No
This is the test data input pin. This signal is
sampled on the rising edge of TCK.
Test Data Output
This is the test data output pin. This drives
active when the ATP controller is the Shift-IR
or Shift-DR state. This signal changes on the
falling edge of TCK.
TDO
Output
No
Test Mode Select
150
316
266
59
TMS
TCK
Input
Input
PU
PU
No
No
This is the test mode select pin. This signal is
sampled on the rising edge of TCK.
Test Clock
This is the test clock pin.
Test Reset
This is the TAP controller asynchronous re-
set. This pin initializes the TAP controller.
When not using the JTAG function on the
printed circuit board, input the same signal as
PRST# to this pin.
55
167
TRST#
Input
PU
No
10. Test
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Test Mode Input
Fix it at Low level on the printed circuit board.
145
234
315
163
54
TESTMODE
TDC
Input
Input
Input
⎯
⎯
⎯
Yes
No
Test Input
Fix it at Low level on the printed circuit board.
UlTEST MODE Input
Fix it at Low level on the printed circuit board.
265
MTESTMODE
Yes
27
MB93461
11. VDC Pin
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
R component output/Cr compo-
nent output/GPIO
These pins are display video data
output pins. In the RGB mode, the
114
15
127
230
325
15
126
229
324
14
VDR[7]/VDCR[7]/AVPP[23]
VDR[6]/VDCR[6]/AVPP[22]
VDR[5]/VDCR[5]/AVPP[21]
VDR[4]/VDCR[4]/AVPP[20]
VDR[3]/VDCR[3]/AVPP[19] output
VDR[2]/VDCR[2]/AVPP[18]
VDR[1]/VDCR[1]/AVPP[17]
VDR[0]/VDCR[0]/AVPP[16]
362
287
204
113
14
Input/
TS
Yes red component is output. In the
24-bit YC mode, Cr component is
output. These pins are shared by
GPIO unit and set as GPIO input
setting after reset.
13
G Component output/Y compo-
nent output/YC multiplexed output
These pins are display video data
output pins. In the RGB mode, the
Yes green component is output. Also,
in the 16-bit or 24-bit YC mode,
the Y component is output. When
8-bit YC mode is selected, multi-
plexed pixel data is output.
116
17
328
18
129
232
327
17
VDG[7]/VDY[7]/VDX[7]
VDG[6]/VDY[6]/VDX[6]
VDG[5]/VDY[5]/VDX[5]
VDG[4]/VDY[4]/VDX[4]
VDG[3]/VDY[3]/VDX[3]
VDG[2]/VDY[2]/VDX[2]
VDG[1]/VDY[1]/VDX[1]
VDG[0]/VDY[0]/VDX[0]
364
289
206
115
16
Output
TS
128
16
205
VDB[7]/VDCX[7]/VDCB[7]/
AVPP[39]
VDB[6]/VDCX[6]/VDCB[6]/
AVPP[38]
VDB[5]/VDCX[5]/VDCB[5]/
AVPP[37]
VDB[4]/VDCX[4]/VDCB[4]/
AVPP[36]
VDB[3]/VDCX[3]/VDCB[3]/
AVPP[35]
VDB[2]/VDCX[2]/VDCB[2]/
AVPP[34]
VDB[1]/VDCX[1]/VDCB[1]/
AVPP[33]
VDB[0]/VDCX[0]/VDCB[0]/
AVPP[32]
B Component output/C compo-
nent output/Cb component output/
GPIO
118
19
132
235
330
20
131
234
329
233
These pins are display video data
output pins. In the RGB mode, the
blue component is output. In the
Yes 16-bit YC mode, the Cb compo-
nent and the Cr component are
time-shared and output. More-
over, in the 24-bit YC mode, Cb
component is output. These pins
are shared by GPIO unit and set
as GPIO input setting after reset.
366
291
208
117
18
Input/
output
TS
207
Horizontal synchronous signal
output
292
367
331
236
VDHSYNC/VDHSYNC#
VDVSYNC/VDVSYNC#
Output
Output
TS
TS
Yes This pin is for display synchronous
signal output. Its polarity is pro-
grammable.
Vertical synchronous signal out-
put
Yes This pin is for display synchronous
signal output. Its polarity is pro-
grammable.
(Continued)
28
MB93461
(Continued)
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Vertical pixel clock input
This pin inputs a basic clock to
generate display pixel clock out-
put.
368
209
20
134
21
VDPCLKIN
Input
Output
Output
⎯
TS
TS
Yes
Display pixel clock output
Yes Pixel data is output in synchroni-
zation with this signal.
VDCLKOUT
Pixel output enable
This signal shows that effective
pixel data is output. Its polarity is
133
ENABLE/ENABLE#
Yes
programmable.
Top field
This pin shows that the top field is
Yes
119
120
22
TOPFIELD/TOPFIELD#
Output
Input
TS
displayed. Its polarity is program-
mable.
Video output disable
When this signal is asserted,
VDR[7 : 0]/VDCR[7 : 0], VDG[7 :
0]/VDY[7 : 0], VDB[7 : 0]/VDCX[7 :
Yes 0]/VDCB[7 : 0], VDHSYNC, VD-
VSYNC, and VDCLKOUT go in to
the high-impedance state. Howev-
er, ordinary operation continues
inside.
333
DISABLE
⎯
29
MB93461
12. VCC Pin
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
R component input/Cr component
input/GPIO
These pins are capture video data
input pins. In the RGB mode, the
201
10
11
320
10
121
224
319
9
VCR[7]/VCCR[7]/AVPP[15]
VCR[6]/VCCR[6]/AVPP[14]
VCR[5]/VCCR[5]/AVPP[13]
VCR[4]/VCCR[4]/AVPP[12]
VCR[3]/VCCR[3]/AVPP[11] output
VCR[2]/VCCR[2]/AVPP[10]
VCR[1]/VCCR[1]/AVPP[9]
109
200
283
358
9
Input/
TS
Yes red component is input. In the 24-
bit YC mode, Cr component is in-
put. These pins are shared by
GPIO unit and set as GPIO input
setting after reset.
108
120
VCR[0]/VCCR[0]/AVPP[8]
G Component input/Y component
input/YC multiplexed input
281
356
7
106
197
280
355
6
7
VCG[7]/VCY[7]/VCX[7]
VCG[6]/VCY[6]/VCX[6]
VCG[5]/VCY[5]/VCX[5]
VCG[4]/VCY[4]/VCX[4]
VCG[3]/VCY[3]/VCX[3]
VCG[2]/VCY[2]/VCX[2]
VCG[1]/VCY[1]/VCX[1]
VCG[0]/VCY[0]/VCX[0]
118
221
316
6
117
220
315
These pins are capture video data
input pins. In the RGB mode, the
Yes green component is input. Also, in
the 24-bit YC mode, the Y compo-
nent is input. When 8-bit YC mode
is selected, multiplexed pixel data
is output.
Input
⎯
VCB[7]/VCCX[7]/VCCB[7]/
AVPP[31]
VCB[6]/VCCX[6]/VCCB[6]/
AVPP[30]
VCB[5]/VCCX[5]/VCCB[5]/
AVPP[29]
B component input/C component
input/Cb component input/GPIO
These pins are capture video data
input pins. In the RGB mode, the
blue component is input. Also, in
112
12
125
124
227
322
12
123
226
321
111
202
285
360
11
VCB[4]/VCCX[4]/VCCB[4]/
AVPP[28]
VCB[3]/VCCX[3]/VCCB[3]/
AVPP[27]
VCB[2]/VCCX[2]/VCCB[2]/
AVPP[26]
Input/
output
the 16-bit YC mode, Cb compo-
nent and Cr component are time-
TS
Yes
shared and input. Moreover, in the
24-bit YC mode, Cb component is
input. These pins are shared by
GPIO unit and set as GPIO input
setting after reset.
110
VCB[1]/VCCX[1]/VCCB[1]/
AVPP[25]
VCB[0]/VCCX[0]/VCCB[0]/
AVPP[24]
Horizontal synchronous signal in-
put
198
317
VCHSYNC/VCHSYNC#
Input
⎯
Yes This pin is a capture synchronous
signal input pin. Its polarity is pro-
grammable.
Vertical synchronous signal input
This pin is a capture synchronous
signal input pin. Its polarity is pro-
grammable.
107
357
222
8
VCVSYNC/VCVSYNC#
VCDCLKIN
Input
Input
⎯
⎯
Yes
Capture pixel clock input
This pin is a sampling clock for
capture. The edge to use is pro-
Yes
grammable.
30
MB93461
13. Audio Pin
Pin No.
Pin name
Direction Type
BS
Description
Audio data output
BGA PFBGA
213
370
137
240
SDO/DX
Output
Output
TS
SD
Yes
Audio serial data is output.
LR clock output/CH0 synchronous signal
LR clock is output when it is I2S and MSB-Jus-
tified output. Moreover, if it is output that sup-
ports PCM highway, CH0 synchronous signal
FS0 is output.
LRCKO/FS0
Yes
Bit clock output
This pin is for bit clock output for audio input/
output. Input/output that supports PCM high-
way always operates in the master mode,
therefore, MCLK output by MB93461 is used
for input as well.
295
294
212
25
BCKO/MCLK
SDI/DR
Output
Input
SD
⎯
Yes
Yes
Yes
Audio data input
This pin is for audio serial data input.
135
136
LR clock input/CH1 synchronous signal out-
put
In the case of I2S and MSB-Justified input, it
becomes LR clock input. Moreover, in the
case of input/output that supports PCM high-
way, CH1 synchronous signal FS1 is output.
Input/
output
LRCKI/FS1
TS
Bit clock input
369
211
24
BCKI
Input
Input
⎯
⎯
Yes
Yes
This pin is for the input of bit clock used for I2S
and MSB-justified audio input.
Basic clock input for audio output
This pin is for the input of basic clocks (256fS/
384fS/512fS/756fS) to generate bit clock of
MSB-justified or I2S audio output, LR clock
and MCLK, FS0 and FS1 at supporting PCM
highway.
238
FSCKI
31
MB93461
14. USB/USB-Host
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
USB D+ signal
Input/
TS
276
191
190
353
278
312
109
400
3
UDP
No
This pin is for differential signal (+) of USB
output
function.
USB D− signal
Input/
TS
UDM
USCKI
UDP1
UDM1
No
Yes
No
This pin is for differential signal (−) of USB
output
function.
USB clock input
This pin inputs 48 MHz clock that is required
by USB interface.
Input
⎯
TS
TS
USB D+ signal
Input/
output
This pin is for differential signal (+) of USB
host.
USB D- signal
This pin is for differential signal (−) of USB
host.
Input/
output
313
No
USB Over Current Detection
This signal is asserted when over current oc-
curs in the down stream. It is read to the Over
Current Indicator of HcRhstatus. Over-Cur-
rent mode is set by No Over Current Protec-
tion of HcRh Descriptor A and Over
CurrentProtection Mode. In the Individual
over-current mode, it is read into Port Over
Current Indicator of HcRh Port Status. This
pin must be pulled up on the printed circuit
board if not used.
354
314
HOVRCUR#
Input
⎯
Yes
Yes
USB Port Power Enable
Global power to the USB port is controlled by
this signal. When No Power Switching is set,
this signal is always active.
5
4
HPWREN
Output
SD
15. I2C Pin
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
I2C clock
216
297
242
335
SCL[1]
SCL[0]
Input/out-
OD
These pins are used for a clock signal of the
I2C bus. SCL[0] corresponds to I2C ch 0;
SCL[1] corresponds to I2C ch 1.
No
put
I2C data
126
215
31
140
SDA[1]
SDA[0]
Input/out-
OD
These pins are used for data signals for the
I2C bus. SDA[0] corresponds to I2C ch 0;
SDA[1] corresponds to I2C ch 1.
No
put
32
MB93461
16. SD/MS Pin
Pin No.
Pin name
Direction Type
BS
Description
BGA PFBGA
Clock input for the SD/Memory Stick
If both of SD and MS are not used, set
this pin to the “H” level on the printed cir-
cuit board.
SDCKI/
MSCKI
189
349
418
351
107
105
397
310
Input
⎯
⎯
⎯
⎯
Yes
Data direction output of SDDAT[0]/MS-
DIO[0]
Yes If both of SD and MS are not used, set
this pin to the “H” level on the printed cir-
cuit board.
SDWP/
MSDIRS
Input/
output
Data direction output of SDDAT[3 : 1]/
MSDIO[3 : 1]
If both of SD and MS are not used, set
this pin open on the printed circuit board.
Input/
output
MSDIRP
Yes
SD/Memory Stick insertion/extraction
detection signal
Yes If both of SD and MS are not used, set
this pin to the “H” level on the printed cir-
cuit board.
SDCD/MSCD
Input
SD command I/O/Memory Stick bus
state signal
Yes If both of SD and MS are not used, set
this pin to the “H” level on the printed cir-
cuit board.
Input/
output
95
308
210
211
SDCMD/MSBS
SDCLK/MSCLK
SD
SD
TS
Transfer clock output for SD/Memory
Stick
If both of SD and MS are not used, set
this pin open on the printed circuit board.
272
188
Output
Yes
Data signal for SD/Memory Stick (at seri-
al)
Yes If both of SD and MS are not used, set
this pin to the “H” level on the printed cir-
cuit board.
Input/
output
SDDAT[0]/MSDIO[0]
Data signal for SD/Memory Stick (at par-
allel)
Yes If both of SD and MS are not used, set
this pin to the “H” level on the printed cir-
cuit board.
419
350
273
309
398
106
SDDAT[3]/MSDIO[3]
SDDAT[2]/MSDIO[2]
SDDAT[1]/MSDIO[1]
Input/
output
TS
SD/Memory Stick selection signal input
If both of SD and MS are not used, set
this pin to the “H” level on the printed cir-
420
213
SDMSSELECT
Input
⎯
Yes
cuit board.
Note : Customers are advised to consult with our sales representatives, if you use SD or MS.
33
MB93461
■ PIN STATE
H
L
: Indicates high level
: Indicates low level
HiZ : Indicates high-impedance state
X
A
: Indicates either high level or low level
: Indicates output of clock
Note:Initialvalue:Indicatespinstateimmediatelyafterpower-onreset. Themeaningofeachsymbolisgivenbelow:
Core sleep
mode
Bus sleep PLL operation
PLL stop
mode
Pin Name
Initial state
mode
mode
BREQ#
BGNT#
A[31 : 2]
D[31 : 0]
⎯
H
⎯
⎯
⎯
⎯
Operation
Operation
Operation
Operation
Operation
Operation
Operation
⎯
H
H
H
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
⎯
X
X
X
HiZ
HiZ
HiZ
BE[0 : 3]/BE#[0 : 3]
BS# , RD# , WE#
DIR
X
X
X
H
H
H
X
X
X
RDY#
HiZ
HiZ
HiZ
ERR#
⎯
⎯
⎯
CS#[3 : 0]
H
Operation
Operation
⎯
H
H
H
CS#[7 : 4]/IRQ#[7 : 4]
IBW
HiZ
⎯
H or HiZ
H or HiZ
H or HiZ
⎯
⎯
⎯
BSTREQ#
HiZ
HiZ
L
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
⎯
H
H
H
BSTACK#
HiZ
HiZ
HiZ
BCLKO
Operation
L
L
DCS#[3 : 0]
DBA[1 : 0]
H
L
L
L
L
X
X
X
DA[12 : 0]
X
X
X
X
DRAS# , DCAS#
DWE#
H
L
L
H
L
H
H
L
H
DCKE
H
L
L
DDQM[0 : 3]
DDQ[31 : 0]
DCLK
H
H
H
H
HiZ
L
HiZ
HiZ
HiZ
Operation
⎯
Operation
⎯
L
DCLKFB
⎯
⎯
IRQ#[3 : 0]/PP[03 : 00]
TOUT[0]/GATE[0]/PP[04]
TOUT[1]/GATE[1]/PP[05]
HiZ
HiZ
HiZ
Operation
Operation
Operation
Operation
Operation
Operation
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
(Continued)
34
MB93461
Core sleep
mode
Bus sleep PLL operation
PLL stop
mode
Pin Name
RXD[0]/PP[06]
Initial state
mode
Operation
Operation
Operation
Operation
Operation
Operation
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
⎯
mode
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
⎯
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
⎯
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Operation
⎯
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
X or HiZ
⎯
TXD[0]/PP[07]
CTS#[0]/PP[08]
RTS#[0]/PP[09]
RXD[1]/PP[10]
TXD[1]/PP[11]
DREQ#[0]/PP[12]
DACK#[0]/PP[13]
DONE#[0]/DREQ#[4]/PP[14]
DREQ#[1]/PP[15]
DACK#[1]/PP[16]
DONE#[1]/DREQ#[5]/PP[17]
DREQ#[2]/PP[18]
DREQ#[3]/PP[19]
DACK#[2]/DREQ#[6]/PP[20]
DACK#[3]/DREQ#[7]/PP[21]
ERST# , HRST#
ECV
⎯
⎯
⎯
⎯
⎯
ED
HiZ
L
HiZ
HiZ
HiZ
HiZ
ECLK
L
L
L
L
PRST#
⎯
⎯
⎯
⎯
⎯
RSTOUT#
L
Operation
⎯
Operation
⎯
Operation
⎯
Operation
⎯
RAMBOOT#
⎯
CPUHOLD
L
X
X
X
X
CLKIN
⎯
⎯
⎯
⎯
⎯
CMODE[3 : 0]
TDI
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TDO
HiZ
⎯
HiZ
HiZ
HiZ
HiZ
TMS , TCK , TRST#
⎯
⎯
⎯
⎯
TESTMODE , TDC ,
MTESTMODE
⎯
⎯
⎯
⎯
⎯
VDR[7 : 0]/VDCR[7 : 0]
/AVPP[23 : 16]
⎯
⎯
Operation
Operation
X or HiZ
X
X or HiZ
X
X or HiZ
VDG[7 : 0]/VDY[7 : 0]/VDX[7 : 0]
X
(Continued)
35
MB93461
Core sleep
mode
Bus sleep PLL operation
PLL stop
mode
Pin Name
Initial state
mode
mode
VDB[7 : 0]/VDCX[7 : 0]/
VDCB[7 : 0]/AVPP[39 : 32]
⎯
Operation
X or HiZ
X or HiZ
X or HiZ
VDHSYNC/VDHSYNC#
VDVSYNC/VDVSYNC#
VDPCLKIN
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Operation
Operation
⎯
X
X
X
X
X
X
⎯
⎯
⎯
VDCLKOUT
Operation
Operation
Operation
⎯
Operation
Operation
Operation
ENABLE/ENABLE#
TOPFIELD/TOPFIELD#
DISABLE
X
X
X
X
X
X
⎯
⎯
⎯
VCR[7 : 0]/VCCR[7 : 0]/
AVPP[15 : 8]
⎯
⎯
⎯
Operation
⎯
X or HiZ
⎯
X or HiZ
⎯
X or HiZ
⎯
VCG[7 : 0]/VCY[7 : 0]/VCX[7 : 0]
VCB[7 : 0]/VCCX[7 : 0]/
VCCB[7 : 0]/AVPP[31 : 24]
Operation
X or HiZ
X or HiZ
X or HiZ
VCHSYNC/VCHSYNC#
VCVSYNC/VCVSYNC#
VCDCLKIN
SDO/DX
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Operation
Operation
Operation
⎯
X
Operation
Operation
⎯
X
Operation
Operation
⎯
X
LRCKO/FS0
BCKO/MCLK
SDI/DR
Operation
Operation
⎯
LRCKI/FS1
BCKI
Operation
⎯
X or HiZ
⎯
X or HiZ
⎯
X or HiZ
⎯
FSCKI
⎯
⎯
⎯
⎯
UDP
Operation
Operation
⎯
HiZ
HiZ
HiZ
UDM
HiZ
HiZ
HiZ
USCKI
⎯
⎯
⎯
UDP1
Operation
Operation
⎯
HiZ
HiZ
HiZ
UDM1
HiZ
HiZ
HiZ
HOVRCUR#
HPWREN
SCL[1 : 0]
SDA[1 : 0]
SDCKI/MSCKI
SDWP/MSDIRS
MSDIRP
⎯
⎯
⎯
Operation
HiZ
X
X
X
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
⎯
⎯
⎯
⎯
Operation
Operation
X or HiZ
X
X or HiZ
X
X or HiZ
X
(Continued)
36
MB93461
(Continued)
Pin Name
Core sleep
mode
Bus sleep
mode
PLL operation
PLL stop
mode
Initial state
mode
SDCD/MSCD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SDCMD/MSBS
Operation
Operation
Operation
Operation
⎯
X or HiZ
Operation
X or HiZ
X or HiZ
⎯
X or HiZ
Operation
X or HiZ
X or HiZ
⎯
X or HiZ
Operation
X or HiZ
X or HiZ
⎯
SDCLK/MSCLK
SDDAT[0]/MSDIO[0]
SDDAT[3 : 1]/MSDIO[3 : 1]
SDMSSELECT
37
MB93461
■ HANDLING DEVICES
• Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VDE or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VDE pin and VSS pin.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, care must also be taken in not allowing the analog power-supply voltage (VDD) to exceed
the digital power-supply voltage.
• Handling unused pins
Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ.
Unused bi-directional pins should be set to the output state and can be left open, or the input state with the
above described connection.
When not using USB/USB-Host pin, fix both UDP1 and UDM1 to the opposite level for each other.
• Power supply pins
In products with multiple VDE, VDD, or VSS pins, the pins of a same potential are internally connected in the
device to avoid abnormal operations including latch-up. However you must connect the pins to an external power
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total current rating.
Make sure to connect VDE, VDD, and VSS pins via the lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VDE, VDD, and VSS pins near the
device.
• Pull-up/down resistors
The MB93461 does not support internal pull-up/down resistors (except PU/PD Pin Type) . Use external compo-
nents where needed.
• N.C. Pin
The N.C. (internally connected) pin must be opened for use.
38
MB93461
■ BLOCK DIAGRAM
FR-V Digital - AV Peripherals
32-bit
FR450
core
(CPU,
cache)
Audio
output
(I2S)
Audio
input
(I2S)
MS 1.4/
SD-IO
Video
display
cntl
External
memory
controller
Video
capture
cntl
SDR-
SDRAM
DSU
Bus
bridge
High bandwidth system interconnect
High bandwidth system interconnect
DMAC
Bus bridge
I2C
× 2
USB 2.0 USB 2.0
Local bus
interface
GPIO
DMAC
function
(FS)
host
(FS)
32-bit
Low bandwidth peripheral bus
Local bus
IRC
GPIO
FR450 SoC
Platform
Timer UART
FR450 core block diagram
Pipeline control
Instruction fetch
I
I
M
M
I-cache
32 KB
2-way
1RW
Static branch
prediction
64
GR
32w × 32b
5R/3W
Integer 0 slot
Integer 1 slot
64
64
MMU
32
Integer-unit
64
FR
32w × 32b
5R/3W
Media 0 slot
Media 1 slot
D-cache
32 KB
2-way
1RW
Media-unit
Cache-unit
39
MB93461
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Min
Max
Power supply voltage (External)
Power supply voltage (Internal)
Input voltage
VDE
VDD
VI
VSS − 0.5
VSS − 0.5
VSS − 0.5
−55
VSS + 4.0
VSS + 1.8
V
V
VDE + 0.5 ( ≤ 4.0)
+ 125
V
Storage temperature
TSTG
°C
Note : VSS = 0 V
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
40
MB93461
2. Recommended Operating Conditions
[VSS = 0 V]
Value
Typ
3.3
3.3
1.3
1.4
⎯
Parameter
Symbol
360 MHz
Unit
Max
Min
3.15
3.15
1.235
1.33
−0.3
2.0
3.45
3.45
V
V
Power supply voltage (External)
Power supply voltage (Internal)
VDE
400 MHz
360 MHz
400 MHz
VIL
1.365
1.47
V
VDDI
V
“L” level input voltage
“H” level input voltage
Operating temperature
0.8
V
VIH
⎯
VDE + 0.3
70
V
Ta
0
25
°C
USB
[VSS = 0 V]
Value
Parameter
Symbol
Unit
Min
2.0
⎯
Typ
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Max
⎯
“H” level input voltage
VIHU
VILU
V
V
“L” level input voltage
0.8
Differential input sensitivity
Differential common mode range
“H” level output voltage
VDIU
0.2
0.8
2.8
0.0
1.3
⎯
V
VCMU
VOHU
VOLU
2.5
V
3.45
0.3
V
“L” level output voltage
V
Output signal crossover voltage
VCRSU
Rpu *1
Rpd *2
VTERM
2.0
V
1.425
14.25
3.15
1.575
15.75
3.45
kΩ
kΩ
V
Bus pull-up/down resistor on upstream port
Termination voltage on upstream port pull-up
*1 : If USB function is used , it is necessary to attach “Rpu” outside to D+ or D−.
*2 : If USB host is used , it is necessary to attach “Rpd” outside to D+ and D−.
Notes : Board Wiring
• For connecting the power supply and ground (GND) , use multiple VDD and VSS pins. The system board
based on the MB93461 must be a multi-layer board containing power supply (VDD) and GND (VSS) layers for
stable power supply.
• Insert sufficient decoupling capacitors (condensers) near the MB93461. Changes to the output levels of many
of the output pins on the MB93461 (in particular, those with large load capacitance) may cause variation in
power supply.
• For those systems which run at a high frequency, low-inductance capacitors and mutual wiring are recom-
mended. Inductance can be lowered by shortening the distance between the processor and decoupling ca-
pacitor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
41
MB93461
3. DC Characteristics
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
Value
Parameter
Symbol
Condition
Unit
Min
Typ
Max
“L” level input
voltage
VIL
VIH
VOL
VOH
ILI
⎯
⎯
0
⎯
0.8
V
V
“H” level input
voltage
2.0
⎯
⎯
⎯
⎯
⎯
VDE
0.2
VDE
5
“L” level output
voltage
IOL = 100 µA
0
VDE − 0.2
−5
V
“H” level output
voltage
IOH = −100 µA
VIN = 0 or VDE
VOUT = 0 or VDE
V
Input leakage
current
µA
µA
Tri-state output
leakage current
ILZ
−5
5
CMODE = 0x3, CLKIN = 60 MHz,
(Dhrystone2.1 + DMA transfer)
No Load
360
MHz
0
0
40
44
80
88
mA
mA
Power supply
current (VDE)
IDE
CMODE = 0x3, CLKIN = 66MHz,
(Dhrystone2.1 + DMA transfer)
No Load
400
MHz
360 CMODE = 0x3, CLKIN = 60 MHz,
MHz (Dhrystone2.1 + DMA transfer)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
196
245
70
420
520
⎯
mA
mA
mA
mA
mA
mA
mA
mA
Power supply
current (VDD)
IDD
400 CMODE = 0x3, CLKIN = 66 MHz,
MHz (Dhrystone2.1 + DMA transfer)
360 Core sleep mode,
MHz CLKIN = 60 MHz
ICORESLEEP
IBUSSLEEP
IPLLON
400 Core sleep mode,
MHz CLKIN = 66 MHz
87
⎯
360 Bus sleep mode,
MHz CLKIN = 60 MHz
32.4
40.6
18.2
22.4
⎯
At sleep power
supply current
400 Bus sleep mode,
MHz CLKIN = 66 MHz
⎯
360 PLL On mode,
MHz CLKIN = 60 MHz
⎯
400 PLL On mode,
MHz CLKIN = 66 MHz
⎯
IPLLOFF
CPIN
PLL Stop mode, CLKIN = 0 MHz
VDE = VI = 0, f = 1 MHz
⎯
⎯
5
⎯
mA
pF
Capacity of pins
⎯
16
42
MB93461
USB
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
Value
Parameter
Symbol
Conditions
Unit
Min
0
Typ
⎯
Max
0.4
VDE
⎯
“L” level output voltage
“H” level output voltage
“L” level output current
“H” level output current
Output short-circuit current
VOL
VOH
IOL
IOL = 20 mA
V
IOH = −20 mA
VOL = 0.4 V
VOH = VDE − 0.4 V
⎯
VDE − 0.5
20
⎯
V
⎯
mA
mA
mA
IOH
IOS
−20
⎯
⎯
⎯
⎯
300
I2C
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
Value
Parameter
Symbol
Conditions
Unit
Min
−0.5
Typ
⎯
Max
0.3 × VDE
VDE
“L” level input voltage
“H” level input voltage
“L” level output voltage 1
Schmitt trigger hysteresis
Data line leakage
VIL
VIH
VOL1
VHYS
II
⎯
⎯
V
V
0.7 × VDE
0
⎯
IOL = 3 mA
⎯
0.4
V
⎯
⎯
0.05 × VDE
−10
⎯
⎯
V
⎯
10
µA
43
MB93461
4. AC Characteristics
(1) Local Bus Interface
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Item
Parameter
Unit
Min
Max
27*
⎯
Min
Max
23.5*
⎯
CLKIN period (TCLKIN)
⎯
15*
6.0
6.0
⎯
15*
6.0
6.0
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN high time
CLKIN low time
CLKIN rise time
CLKIN fall time
BGNT#
⎯
CLKIN
input
⎯
⎯
⎯
⎯
⎯
1.0
1.0
6.5
6.5
⎯
1.0
1.0
6.5
6.5
⎯
⎯
⎯
Output valid delay time CLKIN rise
Output valid delay time CLKIN rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
A [31 : 2]
D [31 : 0]
BE/BE# [0 : 3]
BS#
Output hold time
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
CLKIN rise
6.5
⎯
6.5
⎯
6.5
⎯
6.5
⎯
6.5
⎯
6.5
⎯
RD#
WE#
Output valid delay time CLKIN rise
Output valid delay time CLKIN fall
Output valid delay time CLKIN rise
6.5
7.0
6.5
⎯
6.5
7.0
6.5
⎯
Local-bus
I/F output
DIR
Output hold time
Output valid delay time CLKIN rise
Output hold time CLKIN rise
CLKIN rise
6.5
⎯
6.5
⎯
RDY#
CS# [3 : 0]
Output valid delay time CLKIN rise
Output valid delay time CLKIN rise
6.5
6.5
⎯
6.5
6.5
⎯
CS# [7 : 4]/
IRQ# [7 : 4]
Output hold time
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
CLKIN rise
6.5
⎯
6.5
⎯
BSTREQ#
BSTACK#
6.5
⎯
6.5
⎯
* : Refer to “5. Clock Setting” for details.
(Continued)
44
MB93461
(Continued)
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360MHz
400MHz
Reference
Signal
Item
Parameter
Unit
Min
Max
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Min
Max
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BREQ#
A [31 : 2]
D [31 : 0]
BE/BE# [0 : 3]
BS#
DIR
Local-bus
I/F input
RDY#
ERR#
CS# [7 : 4]/
IRQ# [7 : 4]
IBW
BSTREQ#
BSTACK#
Notes : • Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point
is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less.
The external output load capacitance is 30 pF.
• Maximum frequency of CLKIN varies depending on the setting of CMODE [0] to [3] pins. Please refer to
“ 5. Clock Setting.”
45
MB93461
Setup Hold
Valid
Valid
Hold
Hold
CLKIN
Input pin
Output pin
Input-and-output pin
WE#
46
MB93461
(2) SDRAM Interface
Item
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Parameter
Unit
Min
Max
20*
⎯
Min
Max
17.5*
⎯
DCLKFB period (TDCLKFB)
DCLKFB high time
DCLKFB low time
DCLKFB rise time
DCLKFB fall time
⎯
⎯
⎯
⎯
⎯
7.5*
2.5
2.5
⎯
7.5*
2.5
2.5
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DCLKFB
input
⎯
⎯
1.0
1.0
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
⎯
1.0
1.0
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
⎯
⎯
⎯
DCS# [3 : 0] Output valid delay time DCLKFB rise
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
DBA [1 : 0]
DA [12 : 0]
DRAS#
DCAS#
DWE#
Output valid delay time DCLKFB rise
Output valid delay time DCLKFB rise
Output valid delay time DCLKFB rise
Output valid delay time DCLKFB rise
Output valid delay time DCLKFB rise
Output valid delay time DCLKFB rise
SDRAM
I/F output
DCKE
DDQM [0 : 3] Output valid delay time DCLKFB rise
Output valid delay time DCLKFB rise
DDQ [31 : 0]
Output hold time
Input setup time
Input hold time
DCLKFB rise
DCLKFB rise
DCLKFB rise
⎯
⎯
SDRAM
I/F input
DDQ [31 : 0]
⎯
⎯
* : This value is decided by CMODE.
Notes : • Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is
1.5V, theinputlevelis0.4Vto2.4V, andtheinputrisetimeandfalltimeare1.5nsorlessunlessotherwise
noted.
The external output load capacitance is 30 pF unless otherwise noted.
• The frequency of the input to DCLKFB and the output from DCLK is decided by the input frequency to
CLKIN, and setup of a CMODE [3 : 0] pins. Refer to “5. Clock Setting” for details.
Setup Hold
Valid
Hold
DCLKFB
Output pin
Input-and-
output pin
47
MB93461
• This LSI outputs DCLK which is supplied to SDRAM as a clock. PLL is built into this LSI. Adjust the phase
of DCLK so that the CLK pin of SDRAM and the internal phase in this LSI may be nearly equal. Therefore,
when connecting, adjust the delay time of the feedback path from DCLK to DCLKFB, so that the phase
of the clock input to DCLKFB which is the feedback signal to PLL and the phase of the clock (wave shape
on the reception edge of DCLK) input to CLK of SDRAM may be nearly equal.
48
MB93461
(3) General-purpose Peripheral Resource
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Item
Parameter
Unit
Min
Max
10.0
⎯
Min
Max
10.0
⎯
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
IRQ# [3 : 0]/
PP [03 : 00]
TOUT[0]/
GATE[0]/
PP[04]
10.0
10.0
2.0
2.0
2.0
⎯
10.0
⎯
2.0
2.0
2.0
⎯
10.0
⎯
ns
ns
ns
TOUT[1]/
GATE[1]/
PP[05]
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
10.0
⎯
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
10.0
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RXD[0]/
PP[06]
10.0
⎯
10.0
⎯
TXD[0]/PP[07]
Output hold time
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
CLKIN rise
10.0
⎯
10.0
⎯
CTS# [0]/
PP[08]
10.0
⎯
10.0
⎯
RST# [0]/
PP[09]
10.0
⎯
10.0
⎯
Resources RXD[1]/
output
PP[10]
10.0
⎯
10.0
⎯
TXD[1]/PP[11]
Output hold time
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
CLKIN rise
10.0
⎯
10.0
⎯
DREQ# [0]/
PP[12]
10.0
⎯
10.0
⎯
DACK# [0]/
PP[13]
DONE# [0]/
DREQ# [4]/
PP[14]
10.0
10.0
2.0
⎯
2.0
⎯
ns
2.0
2.0
2.0
2.0
2.0
10.0
⎯
2.0
2.0
2.0
2.0
2.0
10.0
⎯
ns
ns
ns
ns
ns
DREQ# [1]/
PP[15]
10.0
⎯
10.0
⎯
DACK# [1]/
PP[16]
DONE# [1]/
DREQ# [5]/
PP[17]
10.0
10.0
2.0
⎯
2.0
⎯
ns
(Continued)
49
MB93461
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Item
Parameter
Unit
Min
Max
10.0
⎯
Min
Max
10.0
⎯
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
Output hold time CLKIN rise
Output valid delay time CLKIN rise
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
DREQ#[2]/
PP[18]
10.0
⎯
10.0
⎯
DREQ#[3]/
PP[19]
Resources
output
DACK#[2]/
DREQ#[6]/
PP[20]
10.0
10.0
2.0
2.0
2.0
⎯
10.0
⎯
2.0
2.0
2.0
⎯
10.0
⎯
ns
ns
ns
DACK#[3]/
DREQ#[7]/
PP[21]
Output hold time
CLKIN rise
Input setup time
Input hold time
Input setup time
CLKIN rise
CLKIN rise
CLKIN rise
4.0
1.5
4.0
⎯
⎯
⎯
4.0
1.5
4.0
⎯
⎯
⎯
ns
ns
ns
IRQ#[3 : 0]/
PP [03 : 00]
TOUT[0]/
GATE[0]/
PP[04]
Input hold time
Input setup time
Input hold time
CLKIN rise
CLKIN rise
CLKIN rise
1.5
4.0
1.5
⎯
⎯
⎯
1.5
4.0
1.5
⎯
⎯
⎯
ns
ns
ns
TOUT[1]/
GATE[1]/
PP[05]
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
4.0
1.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RXD[0]/
PP[06]
TXD[0]/PP[07]
Resources
input
CTS#[0]/
PP[08]
RST#[0]/
PP[09]
RXD[1]/
PP[10]
TXD[1]/PP[11]
DREQ#[0]/
PP[12]
DACK#[0]/
PP[13]
(Continued)
50
MB93461
(Continued)
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Item
Parameter
Unit
Min
Max
Min
Max
DONE#[0]/
DREQ#[4]/
PP[14]
Input setup time
Input hold time
CLKIN rise
CLKIN rise
4.0
1.5
⎯
4.0
1.5
⎯
ns
ns
⎯
⎯
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
4.0
1.5
4.0
1.5
4.0
⎯
⎯
⎯
⎯
⎯
4.0
1.5
4.0
1.5
4.0
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
ns
ns
DREQ#[1]/
PP[15]
DACK#[1]/
PP[16]
DONE#[1]/
DREQ#[5]/
PP[17]
Input hold time
CLKIN rise
1.5
⎯
1.5
⎯
ns
Resources
input
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
CLKIN rise
4.0
1.5
4.0
1.5
4.0
⎯
⎯
⎯
⎯
⎯
4.0
1.5
4.0
1.5
4.0
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
ns
ns
DREQ#[2]/
PP[18]
DREQ#[3]/
PP[19]
DACK#[2]/
DREQ#[6]/
PP[20]
Input hold time
Input setup time
Input hold time
CLKIN rise
CLKIN rise
CLKIN rise
1.5
4.0
1.5
⎯
⎯
⎯
1.5
4.0
1.5
⎯
⎯
⎯
ns
ns
ns
DACK#[3]/
DREQ#[7]/
PP[21]
Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5
V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less.
The external output load capacitance is 30 pF unless otherwise noted.
Setup Hold
Hold
Valid
CLKIN
Input pin
Output pin
Input-and-
output pin
51
MB93461
(4) ICE Interface
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Item
Parameter
Unit
Min
Max
⎯
Min
Max
⎯
ECLK output period
ECLK output high time
⎯
30
13.0
13.0
⎯
30
13.0
13.0
⎯
ns
ns
⎯
⎯
⎯
ECLK output ECLK output low time
ECLK output rise time
⎯
⎯
⎯
ns
⎯
2.0
2.0
8.0
⎯
2.0
2.0
8.0
⎯
ns
ECLK output fall time
⎯
⎯
⎯
ns
Output valid delay time
Output hold time
Input setup time
Input hold time
ECLK rise
ECLK rise
ECLK rise
ECLK rise
⎯
⎯
⎯
ns
ICE output
ED
0.0
5.0
0.0
16
0.0
5.0
0.0
16
ns
⎯
⎯
ns
ERST#
⎯
⎯
ns
HRST# Low pulse width
⎯
⎯
TCLKIN*
ns
ICE input
Input setup time
ECV
ECLK rise
ECLK rise
ECLK rise
ECLK rise
5.0
0.0
5.0
0.0
⎯
5.0
0.0
5.0
0.0
⎯
Input hold time
⎯
⎯
ns
Input setup time
ED
⎯
⎯
ns
Input hold time
⎯
⎯
ns
* : Unit of TCLKIN is CLKIN period. Please refer to “4. (1) Local Bus Interface”.
Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is
1.5 V, and the input level is 0.4 V to 2.4 V. The input rise time and fall time are 1.5 ns or less. The external
output load capacitance is 30 pF unless otherwise noted.
Setup Hold
Hold
Valid
ECLK
Input pin
Input-and
-output pin
52
MB93461
(5) Reset-related Pin
Item
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Parameter
Unit
Min Max
Min Max
Reset output
Reset input
Boot input
RSTOUT#
PRST#
RAMBOOT# Low pulse width
Output valid delay time CLKIN rise
0
8.0
⎯
0
8.0
⎯
ns
Low pulse width
⎯
⎯
16
16
16
16
TCLKIN*
TCLKIN*
⎯
⎯
* : Unit of TCLKIN is CLKIN period. Please refer to “4. (1) Local Bus Interface”.
(6) CPU Status
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
Min Max
8.0
400 MHz
Min Max
8.0
Reference
Signal
Item
Parameter
Unit
CPU output
CPUHOLD
Output valid delay time CLKIN rise
0
0
ns
(7) Clock
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Item
Parameter
Unit
Min Max
Min Max
Input setup time
Input hold time
⎯
⎯
Must be fixed to “H” or “L”
Must be fixed to “H” or “L”
⎯
⎯
Clock mode input CMODE[3 : 0]
(8) Test
[360 MHz : VDE = 3.3 V 0.15, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz
400 MHz
Reference
Signal
Item
Parameter
Unit
Min Max
Min Max
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
⎯
⎯
⎯
⎯
⎯
⎯
Must be fixed to “L”
Must be fixed to “L”
Must be fixed to “L”
Must be fixed to “L”
Must be fixed to “L”
Must be fixed to “L”
⎯
⎯
⎯
⎯
⎯
⎯
TESTMODE
Test mode input TDC
MTESTMODE
53
MB93461
(9) Video Display Controller (VDC)
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz/400 MHz
Reference
Item
Parameter
Unit
Signal
Min
12.5
4
Max
125
⎯
VDPCLKIN period
⎯
ns
ns
ns
ns
ns
VDC clock
input
VDPCLKIN high time
VDPCLKIN low time
⎯
⎯
4
⎯
Output valid delay time VDCLKOUT fall
−2
−2
3
VDR [7 : 0]/VDCR [7 : 0]
Output hold time
VDCLKOUT fall
⎯
VDG [7 : 0]/VDY [7 : 0]/
VDX[7 : 0]
Output valid delay time VDCLKOUT fall
Output valid delay time VDCLKOUT fall
−2
3
ns
−2
−2
3
ns
ns
VDB [7 : 0]/VDCX[7 : 0]/
VDCB [7 : 0]
Output hold time
VDCLKOUT fall
⎯
VDC
I/F output
VDHSYNC/
VDHSYNC#
Output valid delay time VDCLKOUT fall
−2
3
ns
VDVSYNC/
VDVSYNC#
Output valid delay time VDCLKOUT fall
Output valid delay time VDCLKOUT fall
Output valid delay time VDCLKOUT fall
Output valid delay time VDPCLKIN rise
−2
−2
−2
3
3
3
ns
ns
ns
ENABLE/ENABLE#
TOPFIELD/
TOPFIELD#
VDCLKOUT*
7
11
⎯
⎯
ns
ns
ns
Input setup time
Input hold time
VDPCLKIN rise
VDPCLKIN rise
2.5
1.5
VDC
I/F input
DISABLE
* : The falling edge of VDCLKOUT is synchronous with respect to the rising edge of VDPCLKIN.
Note : Eachparameterisvalidwithinthespecifiedrangesoftemperatureandsupplyvoltageunlessotherwisenoted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is
1.5 V, and the input level is 0.4 V to 2.4 V.
The external output load capacitance is 15 pF.
54
MB93461
(10) Video Capture Controller (VCC)
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz/400 MHz
Reference
Item
Parameter
Unit
Signal
Min
12.5
4
Max
125
⎯
VCDCLKIN period
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCC clock
input
VCDCLKIN high time
VCDCLKIN low time
⎯
⎯
4
⎯
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
Input setup time
Input hold time
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
VCDCLKIN edge*
2.5
1.5
2.5
1.5
2.5
1.5
2.5
1.5
2.5
1.5
⎯
VCR [7 : 0]/VCCR [7 : 0]
⎯
⎯
VCG[7 : 0]/VCY[7 : 0]/
VCX[7 : 0]
⎯
⎯
VCC
I/F input
VCB[7 : 0]/VCCX[7 : 0]/
VCCB[7 : 0]
⎯
⎯
VCHSYNC/
VCHSYNC#
⎯
⎯
VCVSYNC/
VCVSYNC#
⎯
*: The reference signal of VCC interface is decided by the setting of register in the VCC unit.
RCC.ES = 0 : falling edge of VCDCLKIN
RCC.ES = 1 : rising edge of VCDCLKIN
Please refer to MB93461 LSI specification.
Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is
1.5 V, and the input level is 1.0 V to 2.0 V.
The external output load capacitance is 30 pF.
55
MB93461
(11) Audio
Item
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz/400 MHz
Reference
Parameter
Unit
Signal
Min
25
10.5
10.5
100
42
42
3
Max
⎯
⎯
⎯
⎯
⎯
⎯
11
11
11
11
⎯
⎯
⎯
⎯
FSCKI period
⎯
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FSCKI high time
FSCKI low time
BCKI period
BCKI high time
BCKI low time
SDO*
⎯
Audio clock
input
⎯
⎯
⎯
Output valid delay time
FSCKI rise
FSCKI rise
FSCKI rise
FSCKI rise
BCKI rise
BCKI rise
BCKI rise
BCKI rise
LRCKO*
Output valid delay time
Output valid delay time
Output valid delay time
Input setup time
3
Audio
I/F output
BCKO*
3
LRCKI
3
15
15
15
15
SDI
Input hold time
Audio
I/F input
Input setup time
LRCKI
Input hold time
* : LRCKO and SDO signals are generated with respect to the falling edge of BCKO (duty 50%) .
Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is
1.5 V, and the input level is 0.4 V to 2.4 V.
The external output load capacitance is 30 pF.
56
MB93461
(12) USB Interface
Item
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz/400 MHz
Reference
Parameter
Unit
Signal
Min
20
8
Max
USCKI period
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
ns
ns
%
USB clock input USCKI high time
USCKI low time
⎯
8
⎯
D+/D− rise time
TFR
TFF
4
20
D+/D− fall time
4
20
USB driver
Differential rise and fall time matching
Driver output resistance
90
28
111.11
44
Ω
Notes : • Frequency of USCKI is set to 48 MHz in order to carry out operation based on the standard of USB 2.0 FS.
Furthermore, it is necessary to put in a clock with a frequency accuracy of 2500 ppm.
• In order to fulfill the standard of USB 2.0 FS, it is necessary to add 25 Ω to 30 Ω in-series resistance
outside.
D+
90%
90%
10%
10%
D-
T
FF
T
FR
57
MB93461
(13) I2C
Item
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz/400 MHz
Reference
Signal
Parameter
Unit
Min
23*
23*
23*
23*
Max
250
300
250
300
Output fall time
⎯
⎯
⎯
⎯
ns
ns
ns
ns
SCL[1 : 0]
I2C
I/F output
Output rise time
Output fall time
Output rise time
SDA[1 : 0]
* : 20 + 0.1 × C (C = Capacitance of one bus line in pF)
Notes : • Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
• Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is
1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less.
• The external output load capacitance is 30 pF.
(14) GPIO
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz/400 MHz
Reference
Signal
Item
GPIO
Parameter
Unit
Min
⎯
Max
⎯
Output valid delay time
⎯
⎯
⎯
⎯
ns
ns
ns
ns
AVPP[39 : 8]
AVPP[39 : 8]
I/F output
Output hold time
Input setup time
Input hold time
⎯
⎯
⎯
⎯
GPIO
I/F input
⎯
⎯
Notes : • AVPP[39 : 8] is an asynchronous pin.
• Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise
noted.
Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is
1.5 V, and the input level is 0.4 V to 2.4 V.
The external output load capacitance is 30 pF.
(15) Memory Stick Interface
Note : Customers are advised to consult with our sales representatives , if you use MS.
(16) SD-IO Interface
Note : Customers are advised to consult with our sales representatives , if you use SD.
58
MB93461
(17) Power Sequence
Item
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
[400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 °C to + 70 °C]
360 MHz/400 MHz
Reference
Parameter
Unit
Signal
Min
Max
VDE rise time
Power-on VDD rise time
TRE
⎯
⎯
⎯
⎯
30
ms
ms
ms
TRD
⎯
15
Delay time from VDE rise to VDD rise
TDRED
−100
100
Note : Power-off Sequence is not defined.
• Power-on Sequence
VDE-Min
V
DE
TDRED
TRE
VDD-Min
V
DD
TRD
59
MB93461
5. Clock Setting
In this LSI, the clock signal inputted into CLKIN is multiplied by internal PLL, and it has distributed to each part
in LSI.
The multiplication rate for each clock is decided using the CMODE [3 : 0] pins. Depending on this setup, the
maximum frequency of CLKIN may be restricted.
The maximum frequency that can be inputted into CLKIN and the frequency of each part of LSI are shown below.
CLKIN input
CMODE
[0] to [3]
Period
(TCLKIN)
[ns]
Internal operating clock of this LSI
360
MHz
or
Freq.
[MHz]
CLKIN
Freq.
Ratio
400
MHz
External
Core
bus
3 2 1 0
SDRAM
Core
DSU
Min Max Min Max
15.0 18.0 55.6 66.7
15.0 15.5 64.5 66.7
15.0 20.0 50.0 66.7
15.0 17.5 57.1 66.7
16.7 20.0 50.0 60.0
15.0 17.5 57.1 66.7
16.7 20.0 50.0 60.0
15.0 17.5 57.1 66.7
15.0 18.0 55.6 66.7
15.0 15.5 64.5 66.7
bus
360
MHz
0 0 0 0 Ratio
0 0 0 1 Ratio
0 0 1 0 Ratio
0 0 1 1 Ratio
0 1 0 0 Ratio
×1
×1
×1
×1
×1
×1
×1
×1
×1
×2
×2
×2
×1
×0.5
400
MHz
360
MHz
×1
×1
×1
×1
×1
×1
×2
×1
×3
×6
×6
×2
×0.25
×0.5
400
MHz
360
MHz
400
MHz
360
MHz
×0.5
400
MHz
360
MHz
×0.16
400
MHz
0 1 0 1
0 1 1 0
0 1 1 1
Reserved
Reserved
Reserved
360
MHz
15.0 18.0 55.6 66.7
1 0 0 0 Ratio
×1
×1
×1
×1
×2
×0.16
400
15.0 15.5 64.5 66.7
MHz
(Continued)
60
MB93461
(Continued)
CLKIN input
CMODE
[0] to [3]
Period
(TCLKIN)
[ns]
Internal operating clock of this LSI
360
MHz
or
Freq.
[MHz]
CLKIN
Freq.
Ratio
400
MHz
External
Core
bus
3 2 1 0
SDRAM
Core
DSU
Min Max Min Max
15.0 18.0 55.6 66.7
15.0 15.5 64.5 66.7
bus
360
MHz
1 0 0 1 Ratio
×1
×1
×1
×2
×2
×4
×0.33
400
MHz
1 0 1 0
1 0 1 1
Reserved
Reserved
360
MHz
15.0 18.0 55.6 66.7
15.0 15.5 64.5 66.7
1 1 0 0 Ratio
×1
×1
×2
×4
×0.33
×0.75
400
MHz
1 1 0 1
Reserved
360
MHz
25.0 27.0 37.0 40.0
22.5 23.5 42.6 44.4
15.0 20.0 50.0 66.7
15.0 17.5 57.1 66.7
1 1 1 0 Ratio
×1
×1
×1
×1
×3
×3
×9
400
MHz
360
MHz
1 1 1 1 Ratio
×1.5
×1.5
×4.5 ×0.375
400
MHz
Notes : • “×” indicates the frequency ratio for the external input clock.
• By default, the operating frequency of the resource bus clock is the same as that of the external bus.
• When CLKC.p0 is set to “1”, the operating frequency of the resource bus clock is half that of the external
bus. However, the frequency of the resource bus clock is fixed to 1/2 operating frequency of the external
bus when CMODE = F regardless of the setting of CLKC.p0.
• As the setting of CMODE = 5, 6, 7, A, B, D that is the hatched part in the table is not confirmed for
operation guarantee, do not set them.
61
MB93461
■ CONNECTION WITH MEMORY
1. Connection with ROM or SRAM
An example of connection between this processor and ROM or SRAM, etc. is shown below.
Example : Four SRAMs (each of “256 K × 8 bits”) are connected to the 32-bit bus (The polarity of BE/BE# is
positive logic) .
MB93461
A [19:2]
D [31:24]
DIR
A [17:0]
I/O [7:0]
OE#
SRAM (1)
WE#
WE#
CS1#
CS2
CS# [n]
BE [0]/BE# [0]
A [17:0]
I/O [7:0]
OE#
D [23:16]
SRAM (2)
WE#
CS1#
CS2
BE [1]/BE# [1]
D [15:8]
A [17:0]
I/O [7:0]
OE#
SRAM (3)
WE#
CS1#
CS2
BE [2]/BE# [2]
D [7:0]
A [17:0]
I/O [7:0]
OE#
SRAM (4)
WE#
CS1#
CS2
BE [3]/BE# [3]
RDY#
62
MB93461
2. Connection with SDRAM
SDRAM can be connected directly to DCS# [0] or DCS# [1].
An example in which two SDRAMs (each of “1 M × 4 banks × 16 bits”) are connected to the 32-bit bus is shown
below.
MB93461
DBA [1:0]
DA [11:0]
DCS# [0]
DRAS#
BA [1:0]
A [11:0]
CS#
RAS#
CAS#
WE#
DCAS#
SDRAM (1)
DWE#
DDQM [0:1]
DDQ [31:16]
DCKE
DQMU, L
DQ [15:0]
CKE
DCLK
CLK
DCLKFB
BA [1:0]
A [11:0]
CS#
RAS#
CAS#
WE#
SDRAM (2)
DDQM [2:3]
DDQ [15:0]
DQMU, L
DQ [15:0]
CKE
CLK
Note : This LSI outputs DCLK which is supplied to SDRAM as a clock. PLL is built into this LSI. Adjust the phase
of DCLK so that the CLK pin of SDRAM and the internal phase in this LSI may be nearly equal. Therefore,
when connecting, adjust the delay time of the feedback path from DCLK to DCLKFB, so that the phase of
the clock input to DCLKFB which is the feedback signal to PLL and the phase of the clock (wave shape on
the reception edge of DCLK) input to CLK of SDRAM may be nearly equal.
63
MB93461
Example : Connecting Registered-DIMM to DCS#[3 : 2]
DCS#[2] and DCS#[3] are only used for connecting the 168-pin registered DIMM. Connect the 168-pin registered
DIMM as follows. The DIMM must be “registered”. In the registered DIMM, it is assumed that the module
connected to DCS#[2] or DCS#[3] is used after DCS#, DBA, DA, DRAS#, DCAS#, DWE#, DDQM, and DCKE
are latched once at the rising of DCLK signal. When using DCS#[2] or DCS#[3], the bus width must be set to
the 32-bit mode.
168-pin
MB93461
Registered-DIMM
BA [1:0]
A [12:0]
S0#
DBA [1:0]
DA [12:0]
DCS# [2]
S2#
DCS# [3]
DRAS#
RAS#
CAS#
WE#
DCAS#
DWE#
DDQM [0:1]
DQMB [4:5]
DQMB [6:7]
DQMB [0:1]
DQMB [2:3]
DQ [47:32]
DQ [63:48]
DQ [15:0]
DDQM [2:3]
DDQ [31:16]
DDQ [15:0]
DQ [31:16]
DCKE
DCLK
CKE
CLK
DCLKFB
64
MB93461
■ CONNECTION WITH PERIPHERAL DEVICE
1. Connection with MB93441 (PCI Bridge Chip)
An example of connection between this processor and peripheral device is shown below.
Clock Gen.
MB93441
MB93461
CLKIN
BREQ#
BGNT#
CLKIN
BREQ#
BGNT#
D[31:00]
A[27:2]
BE[0:3]
DIR
D[31:00]
A[27:2]
BE[0:3]
DIR
BS#
BS#
RDY#
RDY#
DREQ#[n] (n : 0 to 7)
DREQ#
CSC#
CSR#
IRQ#
Correspondence is arbitrary.
CS#[n] (n : Arbitrary except 0)
IRQ[n]/PP[n] (n : 0 to 3)
Correspondence is arbitrary.
Correspondence is arbitrary.
BSTREQ#
BSTACK#
BSTREQ#
BSTACK#
PRST#
BW16
PRST#
Reset Gen.
65
MB93461
2. Connection with MB93443 (IDE/PC-Card Host Controller)
An example of connection between this processor and peripheral device is shown below.
Clock Gen.
MB93443
MB93461
CLKIN
CLKIN
D[31:00]
A[15:2]
BE[0:3]
DIR
D[31:00]
A[15:2]
BE[0:3]
DIR
BS#
BS#
RDY#
RDY#
DREQ#[n] (n : 0 to 7)
DREQ#
CSC#
CSR#
IRQ#
Correspondence is arbitrary.
CS#[n] (n : Arbitrary except 0)
IRQ[n]/PP[n] (n : 0 to 3)
Correspondence is arbitrary.
Correspondence is arbitrary.
BSTREQ#
BSTACK#
BSTREQ#
BSTACK#
PRST#
BW16
PRST#
Reset Gen.
66
MB93461
■ PACKAGE DIMENSIONS
420-ball plastic BGA
(BGA-420P-M25)
27.00±0.20(1.063±.008)
+0.70 .945–+..000228
24.00–0.05
25.00(.984)BSC
0.50(.020)
4-C2.0
(4-C.079 )
BSC
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
4X10.00
(4X.394)
0.50(.020)
BSC
27.00±0.20
(1.063±.008)
+0.70
25.00(.984)
BSC
24.00
–0.05
+.028
–.002
.945
1.00(.039)
BSC
8
7
6
5
4
3
2
1
AF AE AD AC AB AA Y WV U T R P N M L K J H G F E D C B A
3-R0.5
(3-R.020)
B
A
1 PIN INDEX
ø0.63±0.15(.025±.006)
M
0.30(.012)
0.10(.004)
C
C
A B
0.35(.014)
0.15(.006)
C
C
M
0.25(.010)
C
0.56±0.06
(.022±.002)
0.50±0.10
2.23±0.21
(.088±.008)
1.17±0.05
C
SEATING PLANE
(.020±.004) (.046±.002)
Dimensions in mm (inches).
C
Note: The values in parentheses are reference values.
2005 FUJITSU LIMITED BGA420025Sc-1-2
400-ball plastic PFBGA
(BGA-400P-M04)
15.00±0.10(.591±.004)
14.00(.551)REF
0.20(.008)
S B
B
0.50(.020)
TYP
29
28
27
26
25
24
23
22
21
20
19
A
18
16
14
12
10
8
17
15
13
11
9
14.00(.551)
REF
15.00±0.10
(.591±.004)
0.50(.020)
TYP
7
6
5
4
3
2
1
AJ
AG AE AC AA
AH AF AD AB
W
U
R
N
L
J
G
E
C
A
Y
V
T
P
M
K
H
F
D
B
0.20(.008)
S A
(INDEX AREA)
INDEX
481-ø0.30±0.10
(481-ø.012±.004)
M
ø0.05(.002)
S
A
B
S
0.25±0.10
1.15±0.20
0.15(.006)
S
(.010±.004)
(Stand off)
(.045±.008)
(Seated height)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2004 FUJITSU LIMITED B400004S-c-1-1
67
MB93461
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0504
© 2005 FUJITSU LIMITED Printed in Japan
相关型号：
©2020 ICPDF网 联系我们和版权申明