MB95F128NBPFV [FUJITSU]
暂无描述;型号: | MB95F128NBPFV |
厂家: | FUJITSU |
描述: | 暂无描述 微控制器 |
文件: | 总67页 (文件大小:776K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12616-1E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95120 series
MB95F128D/F128E/FV100D-101/FV100D-102
■ DESCRIPTION
The MB95120 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
• Timer
• 8/16-bit compound timer × 2 channels
• 16-bit reload timer
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
• Timebase timer
• Watch prescaler
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved
MB95120 Series
(Continued)
• LIN-UART
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• UART/SIO
• Full duplex double buffer
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• I2C*
• Built-in wake-up function
• External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected
• LCD controller (LCDC)
• 40 SEG × 4 COM (Max 160 pixels)
• With blinking function
• Built-in division resistance for LCD drive/booster : selected by mask option
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
• I/O port
• The number of maximum ports : Max 87
• Port configuration
• General-purpose I/O ports (N-ch open drain) : 2 ports
• General-purpose I/O ports (CMOS)
• Programmable input voltage levels of port
• CMOS input level / hysteresis input level
• Dual operation Flash memory
: 85 ports
• Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
• Flash memory security function
Protects the content of Flash memory (Flash memory product only)
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
2
MB95120 Series
■ PRODUCT LINEUP
Part number*1
MB95F128D
MB95F128E
Parameter
Type
Flash memory product
ROM capacity
RAM capacity
Reset output
Clock system
60 Kbytes
2 Kbytes
No
Dual clock
Low voltage
detection reset
No
Number of basic instructions
Instruction bit length
Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
CPU functions
Data bit length
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time : 0.6 µs (at machine clock frequency 16.25 MHz)
General-purpose I/O port (N-ch open drain)
General-purpose I/O port (CMOS)
Programmable input voltage levels of port
CMOS input level / hysteresis input level
: 2 ports
: 85 ports
Ports (Max 87 ports)
Timebase timer
Watchdog timer
Wild register
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Reset generated cycle
At main oscillation clock 10 MHz
At sub oscillation clock 32.768 kHz
: Min 105 ms
: Min 250 ms
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
I2C
Start condition repeated generation and detection functions
Built-in wake-up function
Data transfer capable in UART/SIO
Full duplex double buffer
Variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected
UART/SIO
LIN-UART
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set
Full duplex double buffer
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave
8/10-bit A/D converter
(12 channels)
8-bit or 10-bit resolution can be selected
(Continued)
3
MB95120 Series
(Continued)
Part number*1
MB95F128D
MB95F128E
Parameter
COM output
SEG output
LCD drive power supply (bias) pin
40 SEG × 4 COM
Duty LCD mode
: 4 (Max)
: 40 (Max)
: 4
: 160 pixels can be displayed
LCD controller
(LCDC)
With blinking function
Division resistance for LCD drive/booster : selected by mask option
Built-in internal division resistance :
selected by mask option
Built-in booster circuit :
selected by mask option
Two clock modes and two counter operating modes can be selected
Square wave form output
Count clock : 7 internal clocks and external clock can be selected
Counter operating mode : reload mode or one-shot mode can be selected
16-bit reload timer
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer ×
1 channel”
Built-in timer function, PWC function, PWM function, capture function and square
wave form output
8/16-bit compound
timer (2 channels)
Count clock : 7 internal clocks and external clock can be selected
PWM mode or one-shot mode can be selected
Counter operating clock : Eight selectable clock sources
Support for external trigger start
16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”
Counter operating clock : Eight selectable clock sources
8/16-bit PPG
(2 channels)
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63 (Capable of counting for 1 minute when selecting
clock source 1 second and setting counter value to 60)
Watch counter
Watch prescaler
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(12 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected)
Can be used to recover from standby modes
3
Supports automatic programming, Embedded AlgorithmTM
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
*
Flash memory
Standby mode
Erase can be performed on each block
Block protection with external programming voltage
Dual operation Flash memory
Flash Security Feature for protecting the content of the Flash
Sleep, stop, watch, and timebase timer
*1 : MASK ROM products are currently under consideration.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of evaluation product in MB95120 series is MB95FV100D-101 (internal division resistance
included) or MB95FV100D-102 (LCD booster circuit included) . When using it, the MCU board (MB2146-
301A or MB2146-302A) is required.
4
MB95120 Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown as follows.
Oscillation stabilization wait time
Remarks
(214−2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F128D/F128E
Package
MB95FV100D-101/102
FPT-100P-M20
FPT-100P-M06
BGA-224P-M08
: Available
: Unavailable
5
MB95120 Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95120 series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95120 series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
Flash memory and mask ROM products, do not use these values in the program.
The functions corresponding to certain bits in single-byte registers may not be supported on Flash memory
products. However, reading or writing to these bits will not cause malfunction of the hardware. Also, as the
evaluation and Flash memory products are designed to have identical software operation, no particular
precautions are required.
• Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory product, carefully
check the difference in the amount of memory from the model to be actually used when developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage are different between the Evaluation and Flash memory products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
6
MB95120 Series
■ PIN ASSIGNMENT
(TOP VIEW)
100999897969594939291908988878685848382818079787776
V
SS
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PC5/SEG13
PC6/SEG14
PC7/SEG15
PD0/SEG16
PD1/SEG17
PD2/SEG18
PD3/SEG19
PD4/SEG20
PD5/SEG21
PD6/SEG22
PD7/SEG23
PE0/SEG24
PE1/SEG25
PE2/SEG26
PE3/SEG27
PE4/SEG28/INT10
PE5/SEG29/INT11
PE6/SEG30/INT12
PE7/SEG31/INT13
P60/SEG32/PPG10
P61/SEG33/PPG11
MOD
PG0
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
P10/UI0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P50/SCL0
P51/SDA0
P52/PPG1
AVR
X0
X1
VSS
AVCC
26272829303132333435363738394041424344454647484950
(FPT-100P-M20)
Note : The P90 to P95 are not used as a general-purpose ports in the MB95F128E.
(Continued)
7
MB95120 Series
(Continued)
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P91/V2
P90/V3
PC4/SEG12
VCC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCC
VSS
PG0
PC5/SEG13
PC6/SEG14
PC7/SEG15
PD0/SEG16
PD1/SEG17
PD2/SEG18
PD3/SEG19
PD4/SEG20
PD5/SEG21
PD6/SEG22
PD7/SEG23
PE0/SEG24
PE1/SEG25
PE2/SEG26
PE3/SEG27
PE4/SEG28/INT10
PE5/SEG29/INT11
PE6/SEG30/INT12
PE7/SEG31/INT13
P60/SEG32/PPG10
P61/SEG33/PPG11
MOD
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
P10/UI0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P50/SCL0
P51/SDA0
P52/PPG1
AVR
X0
X1
VSS
X1A
X0A
RST
AVCC
AVSS
P30/AN00
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(FPT-100P-M06)
Note : The P90 to P95 are not used as a general-purpose ports in the MB95F128E.
8
MB95120 Series
■ PIN DESCRIPTION
Pin no.
I/O
Pin name
circuit
Function
LQFP *1
QFP *2
type*3
1
2
4
5
VSS
⎯
Power supply pin (GND)
PG0
H
General-purpose I/O port
3
6
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
4
7
5
8
General-purpose I/O port
6
9
C
The pins are shared with external interrupt input. Large
current port.
7
10
11
12
13
8
9
10
General-purpose I/O port
The pin is shared with UART/SIO ch.0 data input.
11
12
13
14
15
16
P10/UI0
P11/UO0
P12/UCK0
G
H
General-purpose I/O port
The pin is shared with UART/SIO ch.0 data output.
General-purpose I/O port
The pin is shared with UART/SIO ch.0 clock I/O.
General-purpose I/O port
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0)
and A/D converter trigger input (ADTG).
P13/TRG0/
ADTG
14
17
General-purpose I/O port
The pin is shared with 16-bit PPG ch.0 output.
15
18
P14/PPG0
16
17
18
19
20
21
P20/PPG00
P21/PPG01
P22/TO00
General-purpose I/O port
The pins are shared with 8/16-bit PPG ch.0 output.
General-purpose I/O port
The pins are shared with 8/16-bit compound timer ch.0
output.
H
19
22
P23/TO01
General-purpose I/O port
20
23
P24/EC0
The pin is shared with 8/16-bit compound timer ch.0 clock
input.
General-purpose I/O port
21
22
23
24
25
26
P50/SCL0
P51/SDA0
P52/PPG1
The pin is shared with I2C ch.0 clock I/O.
I
General-purpose I/O port
The pin is shared with I2C ch.0 data I/O.
General-purpose I/O port
The pin is shared with 16-bit PPG ch.1 output.
H
24
25
27
28
AVR
AVCC
⎯
⎯
A/D converter reference input pin
A/D converter power supply pin
(Continued)
9
MB95120 Series
Pin no.
I/O
Pin name
circuit
Function
LQFP *1
QFP *2
type*3
26
27
28
29
30
31
32
33
34
35
36
37
38
29
30
31
32
33
34
35
36
37
38
39
40
41
AVSS
⎯
A/D converter power supply pin (GND)
P30/AN00
P31/AN01
P32/AN02
P33/AN03
P34/AN04
P35/AN05
P36/AN06
P37/AN07
P40/AN08
P41/AN09
P42/AN10
P43/AN11
General-purpose I/O port
The pins are shared with A/D converter analog input.
J
General-purpose I/O port
The pins are shared with A/D converter analog input.
J
General-purpose I/O port
The pin is shared with 16-bit PPG ch.1 trigger input.
39
40
41
42
43
44
P53/TRG1
P70/TO0
P71/TI0
H
H
General-purpose I/O port
The pin is shared with 16-bit reload timer ch.0 output.
General-purpose I/O port
The pin is shared with 16-bit reload timer ch.0 input.
General-purpose I/O port
The pin is shared with LIN-UART data input (SIN) and
LCDC SEG output (SEG39) .
P67/SEG39/
SIN
42
43
44
45
45
46
47
48
N
General-purpose I/O port
The pin is shared with LIN-UART data output (SOT) and
LCDC SEG output (SEG38) .
P66/SEG38/
SOT
General-purpose I/O port
The pin is shared with LIN-UART clock I/O (SCK) and LCDC
SEG output (SEG37) .
P65/SEG37/
SCK
M
General-purpose I/O port
The pin is shared with 8/16-bit compound timer ch.1 clock
input (EC1) and LCDC SEG output (SEG36) .
P64/SEG36/
EC1
P63/SEG35/
TO11
General-purpose I/O port
46
47
49
50
The pins are shared with 8/16-bit compound timer ch.1
output (TO10, TO11) and LCDC SEG output (SEG34,
SEG35) .
P62/SEG34/
TO10
48
49
50
51
51
52
53
54
RST
X0A
X1A
VSS
B'
A
Reset pin
Sub clock oscillation pins (32 kHz)
⎯
Power supply pin (GND)
(Continued)
10
MB95120 Series
Pin no.
I/O
circuit
Pin name
Function
LQFP *1
QFP *2
type*3
52
53
54
55
56
57
X1
X0
A
B
Main clock oscillation pins
MOD
An operating mode designation pin
P61/SEG33/
PPG11
55
56
57
58
59
60
58
59
60
61
62
63
General-purpose I/O port
The pins are shared with 8/16-bit PPG ch.1 output (PPG10,
PPG11) and LCDC SEG output (SEG32, SEG33) .
M
P60/SEG32/
PPG10
PE7/SEG31/
INT13
PE6/SEG30/
INT12
General-purpose I/O port
The pins are shared with external interrupt input (INT10 to
INT13) and LCDC SEG output (SEG28 to SEG31) .
Q
PE5/SEG29/
INT11
PE4/SEG28/
INT10
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
PE3/SEG27
PE2/SEG26
PE1/SEG25
PE0/SEG24
PD7/SEG23
PD6/SEG22
PD5/SEG21
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
PC7/SEG15
PC6/SEG14
PC5/SEG13
VCC
General-purpose I/O port
The pins are shared with LCDC SEG output.
M
M
General-purpose I/O port
The pins are shared with LCDC SEG output.
General-purpose I/O port
The pins are shared with LCDC SEG output.
M
⎯
Power supply pin
(Continued)
11
MB95120 Series
(Continued)
Pin no.
I/O
Pin name
circuit
Function
LQFP *1
QFP *2
type*3
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
PC4/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG09
PC0/SEG08
PB7/SEG07
PB6/SEG06
PB5/SEG05
PB4/SEG04
PB3/SEG03
PB2/SEG02
PB1/SEG01
PB0/SEG00
PA3/COM3
PA2/COM2
PA1/COM1
PA0/COM0
P95*4/C1
General-purpose I/O port
The pins are shared with LCDC SEG output.
M
General-purpose I/O port
The pins are shared with LCDC SEG output.
M
General-purpose I/O port
The pins are shared with LCDC COM output.
M
S
General-purpose I/O port
P94*4/C0
P93*4/V0
P92*4/V1
P91*4/V2
General-purpose I/O port
The pins are shared with power supply pins for LCDC
drive.
R
2
P90*4/V3
3
VCC
⎯
Power supply pin
*1 : FPT-100P-M20
*2 : FPT-100P-M06
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
*4 : The P90 to P95 are not used as a general-purpose ports in the MB95F128E.
12
MB95120 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
X1 (X1A)
Clock input
N-ch
X0 (X0A)
A
Feedback resistance : approx. 24 MΩ
(Evaluation product : approx.10 MΩ)
Damping resistance : approx.144 kΩ
(Evaluation product : non-damping
resistance )
Standby control
• Only for input
• Hysteresis input
B
Mode input
Hysteresis input
Reset input
B’
• CMOS output
• Hysteresis input
P-ch
Digital output
Digital output
N-ch
C
Hysteresis input
Standby control
External interrupt
enable
• CMOS output
• CMOS input
• Hysteresis input
• With pull-up control
R
P-ch
Pull-up control
P-ch
N-ch
Digital output
Digital output
G
CMOS input
Hysteresis input
Standby control
• CMOS output
• Hysteresis input
• With pull-up control
R
P-ch
Pull-up control
P-ch
N-ch
Digital output
Digital output
H
Hysteresis input
Standby control
(Continued)
13
MB95120 Series
Type
Circuit
Remarks
• N-ch open drain output
• CMOS input
• Hysteresis input
Digital output
N-ch
I
CMOS input
Hysteresis input
Standby control
• CMOS output
• Hysteresis input
• Analog input
• With pull-up control
R
Pull-up control
P-ch
P-ch
N-ch
Digital output
Digital output
J
Analog input
A/D control
Hysteresis input
Standby control
• CMOS output
• LCD output
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
M
LCD output
LCD control
Hysteresis input
Standby control
• CMOS output
• LCD output
• CMOS input
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
N
LCD output
CMOS input
Hysteresis input
LCD control
Standby control
(Continued)
14
MB95120 Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• LCD output
• Hysteresis input
P-ch
Digital output
Digital output
N-ch
Q
LCD output
LCD control
Hysteresis input
Standby control
External
interrupt control
• CMOS output
P-ch
N-ch
• LCD power supply
• Hysteresis input
Digital output
Digital output
R
LCD internal division
resistance I/O
LCD control
Hysteresis input
Standby control
• CMOS output
P-ch
N-ch
• LCD power supply
• Hysteresis input
Digital output
Digital output
S
LCD booster I/O
Hysteresis input
Standby control
15
MB95120 Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC , AVR) and analog input voltage from exceeding
the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power-supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
■ PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent
damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is unused output pin, make it open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 µF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near
this device.
16
MB95120 Series
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pin to VCC or VSS pins and to provide a low-impedance connection.
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN11 pins.
17
MB95120 Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
FPT-100P-M20
TEF110-95F128HSPFV
FPT-100P-M06
TEF110-95F128HSPF
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
• MB95F128D/F128E (60 Kbytes)
Flash memory
CPU address
Programmer address*
71000H
1000H
SA1 (4 Kbytes)
1FFFH
2000H
71FFFH
72000H
SA2 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA5 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer
18
MB95120 Series
■ BLOCK DIAGRAM
F2 MC-8FX CPU
RST
Reset control
ROM
RAM
X0/X1
Clock control
X0A/X1A
Interrupt control
Wild register
Watch prescaler
Watch counter
PG0
P60/SEG32/PPG10
P61/SEG33/PPG11
P00/INT00 to P07/INT07
External interrupt ch.0 to ch.7
8/16-bit PPG ch.1
P10/UI0
P11/UO0
P12/UCK0
P62/SEG34/TO10
P63/SEG35/TO11
P64/SEG36/EC1
UART/SIO
8/16-bit compound
timer ch.1
P13/TRG0/ADTG
16-bit PPG ch.0
P65/SEG37/SCK
P66/SEG38/SOT
P67/SEG39/SIN
P14/PPG0
LIN-UART
P20/PPG00
P21/PPG01
8/16-bit PPG ch.0
P70/TO0
P71/TI0
16-bit reload timer
P22/TO00
P23/TO01
P24/EC0
8/16-bit compound
timer ch.0
P90/V3 to P93/V0
P94/C0, P95/C1
P30/AN00 to P37/AN07
PA0/COM0 to PA3/COM3
PB0/SEG00 to PB7/SEG07
PC0/SEG08 to PC7/SEG15
PD0/SEG16 to PD7/SEG23
PE0/SEG24 to PE3/SEG27
PE4/SEG28/INT10
P40/AN08 to P43/AN11
8/10-bit A/D
converter
AVCC
AVSS
AVR
LCDC
P50/SCL0
P51/SDA0
I2C
PE5/SEG29/INT11
PE6/SEG30/INT12
P52/PPG1
External interrupt ch.8 to ch.11
PE7/SEG31/INT13
16-bit PPG ch.1
P53/TRG1
Port
Port
Other pins
MOD, VCC
19
MB95120 Series
■ CPU CORE
1. Memory space
Memory space of the MB95120 series is 64 Kbytes and consists of I/O area, data area, and program area. The
memoryspaceincludesspecial-purposeareassuchasthegeneral-purpose registersandvectortable. Memory
map of the MB95120 series is shown below.
• Memory Map
MB95F128D
MB95F128E
MB95FV100D-101
MB95FV100D-102
0000H
0000H
I/O
I/O
0080H
0100H
0200H
0080H
0100H
0200H
RAM 2 Kbytes
Register
RAM 3.75 Kbytes
Register
0880H
0F80H
Access
prohibited
0F80H
Extended I/O
Extended I/O
1000H
1000H
Flash memory
60 Kbytes
Flash memory
60 Kbytes
FFFFH
FFFFH
20
MB95120 Series
2. Register
The MB95120 series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register for index modification
: A 16-bit pointer to point to a memory address.
: A 16-bit register to indicate a stack area.
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16-bit
FFFDH
0000H
0000H
0000H
0000H
0000H
0030H
: Program counter
: Accumulator
PC
A
T
: Temporary accumulator
: Index register
IX
EP
SP
PS
: Extra pointer
: Stack pointer
: Program status
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the program status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R4
R3
R2
R1
R0 DP2 DP1 DP0
H
I
IL1
IL0
N
Z
PS
C
V
RP
DP
CCR
21
MB95120 Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
OP code lower
"0" "0" "0" "0" "0" "0" "0" "1"
R4 R3 R2 R1 R0 b2
b1
b0
Generated address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
0000H to 007FH (without mapping)
0080H to 00FFH (without mapping)
0100H to 017FH
XXXB (no effect to mapping)
0000H to 007FH
000B (initial value)
001B
010B
011B
100B
101B
110B
111B
0180H to 01FFH
0200H to 027FH
0080H to 00FFH
0280H to 02FFH
0300H to 037FH
0380H to 03FFH
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
I flag
Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
:
:
:
IL1, IL0
IL1
0
IL0
0
Interrupt level
Priority
0
1
2
3
High
0
1
1
0
Low = no interruption
1
1
N flag
Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
:
:
:
Z flag
V flag
Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag
Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
:
22
MB95120 Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains
8-register. Up to a total of 32 banks can be used on the MB95120 series. The bank currently in use is indicated
by the register bank pointer (RP).8-register. Up to a total of 32 banks can be used on the MB95120 series. The
bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates
the general-purpose register 0 (R0) to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R1
R0
R1
R0
R1
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
1FFH
Bank 31
107H
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
Bank 0
Memory area
23
MB95120 Series
■ I/O MAP
Register
abbreviation
Address
Register name
R/W
Initial value
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
0010H
0011H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
PDR0
DDR0
PDR1
DDR1
⎯
Port 0 data register
Port 0 direction register
Port 1 data register
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
⎯
Port 1 direction register
(Disabled)
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
⎯
Oscillation stabilization wait time setting register
PLL control register
R/W
R/W
R/W
R/W
R
11111111B
00000000B
1010X011B
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
⎯
System clock control register
Standby control register
Reset source register
Timebase timer control register
Watch prescaler control register
Watchdog timer control register
(Disabled)
R/W
R/W
R/W
⎯
PDR2
DDR2
PDR3
DDR3
PDR4
DDR4
PDR5
DDR5
PDR6
DDR6
PDR7
DDR7
Port 2 data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port 2 direction register
Port 3 data register
Port 3 direction register
Port 4 data register
Port 4 direction register
Port 5 data register
Port 5 direction register
Port 6 data register
Port 6 direction register
Port 7 data register
Port 7 direction register
001AH,
001BH
⎯
(Disabled)
⎯
⎯
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
Port 9 direction register
Port A data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
(Continued)
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
24
MB95120 Series
Register
abbreviation
Address
Register name
R/W
Initial value
0024H
0025H
0026H
0027H
PDRD
DDRD
PDRE
DDRE
Port D data register
Port D direction register
Port E data register
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
Port E direction register
0028H,
0029H
⎯
(Disabled)
⎯
⎯
002AH
002BH
002CH
002DH
002EH
002FH
0030H
0031H
0032H
PDRG
DDRG
⎯
Port G data register
Port G direction register
(Disabled)
R/W
R/W
⎯
00000000B
00000000B
⎯
PUL1
PUL2
PUL3
PUL4
PUL5
PUL7
Port 1 pull-up register
Port 2 pull-up register
Port 3 pull-up register
Port 4 pull-up register
Port 5 pull-up register
Port 7 pull-up register
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0033H,
0034H
⎯
(Disabled)
⎯
⎯
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
003EH
003FH
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
Port G pull-up register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 01 control status register 1 ch.0
8/16-bit compound timer 00 control status register 1 ch.0
8/16-bit compound timer 11 control status register 1 ch.1
8/16-bit compound timer 10 control status register 1 ch.1
8/16-bit PPG1 control register ch.0
PC00
8/16-bit PPG0 control register ch.0
PC11
8/16-bit PPG1 control register ch.1
PC10
8/16-bit PPG0 control register ch.1
TMCSRH0
TMCSRL0
16-bit reload timer control status register (upper byte) ch.0 R/W
16-bit reload timer control status register (lower byte) ch.0
R/W
0040H,
0041H
⎯
(Disabled)
⎯
⎯
0042H
0043H
0044H
0045H
PCNTH0
PCNTL0
PCNTH1
PCNTL1
16-bit PPG status control register (upper byte) ch.0
16-bit PPG status control register (lower byte) ch.0
16-bit PPG status control register (upper byte) ch.1
16-bit PPG status control register (lower byte) ch.1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
0046H,
0047H
⎯
(Disabled)
⎯
⎯
0048H
0049H
EIC00
EIC10
External interrupt circuit control register ch.0/ch.1
External interrupt circuit control register ch.2/ch.3
R/W
R/W
00000000B
00000000B
(Continued)
25
MB95120 Series
Register
Address
Register name
R/W Initial value
abbreviation
004AH
004BH
004CH
004DH
EIC20
EIC30
EIC01
EIC11
External interrupt circuit control register ch.4/ch.5
External interrupt circuit control register ch.6/ch.7
External interrupt circuit control register ch.8/ch.9
External interrupt circuit control register ch.10/ch.11
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
004EH,
004FH
⎯
(Disabled)
⎯
⎯
0050H
0051H
0052H
0053H
0054H
0055H
0056H
0057H
0058H
0059H
005AH
SCR
SMR
LIN-UART serial control register
LIN-UART serial mode register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000B
00000000B
00001000B
00000000B
00000100B
000000XXB
00000000B
00100000B
00000001B
00000000B
00000000B
SSR
LIN-UART serial status register
RDR/TDR
ESCR
ECCR
SMC10
SMC20
SSR0
LIN-UART reception/transmission data register
LIN-UART extended status control register
LIN-UART extended communication control register
UART/SIO serial mode control register 1 ch.0
UART/SIO serial mode control register 2 ch.0
UART/SIO serial status register ch.0
TDR0
UART/SIO serial output data register ch.0
UART/SIO serial input data register ch.0
RDR0
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
0060H
0061H
0062H
0063H
0064H
0065H
IBCR00
IBCR10
IBSR0
IDDR0
IAAR0
ICCR0
I2C bus control register 0 ch.0
I2C bus control register 1 ch.0
I2C bus status register ch.0
I2C data register ch.0
I2C address register ch.0
I2C clock control register ch.0
R/W
R/W
R
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
R/W
R/W
R/W
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
006DH
006EH
006FH
0070H
0071H
0072H
ADC1
ADC2
ADDH
ADDL
WCSR
⎯
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register (upper byte)
8/10-bit A/D converter data register (lower byte)
Watch counter status register
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
00000000B
⎯
(Disabled)
FSR
Flash memory status register
R/W
000X0000B
(Continued)
26
MB95120 Series
Register
abbreviation
Address
Register name
R/W Initial value
0073H
0074H
0075H
0076H
0077H
SWRE0
SWRE1
⎯
Flash memory sector writing control register 0
Flash memory sector writing control register 1
(Disabled)
R/W
R/W
⎯
00000000B
00000000B
⎯
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W
R/W
00000000B
00000000B
Register bank pointer (RP) ,
Mirror of direct bank pointer (DP)
0078H
⎯
⎯
⎯
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
Interrupt level setting register 0
Interrupt level setting register 1
R/W
R/W
R/W
R/W
R/W
R/W
⎯
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
⎯
ILR2
Interrupt level setting register 2
ILR3
Interrupt level setting register 3
ILR4
Interrupt level setting register 4
ILR5
Interrupt level setting register 5
⎯
(Disabled)
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register address setting register (upper byte) ch.0
Wild register address setting register (lower byte) ch.0
Wild register data setting register ch.0
Wild register address setting register (upper byte) ch.1
Wild register address setting register (lower byte) ch.1
Wild register data setting register ch.1
Wild register address setting register (upper byte) ch.2
Wild register address setting register (lower byte) ch.2
Wild register data setting register ch.2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit compound timer 01 control status register 0 ch.0
8/16-bit compound timer 00 control status register 0 ch.0
8/16-bit compound timer 01 data register ch.0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 00 data register ch.0
8/16-bit compound timer 00/01 timer mode control register
ch.0
0F96H
TMCR0
R/W
00000000B
0F97H
0F98H
0F99H
0F9AH
T11CR0
T10CR0
T11DR
T10DR
8/16-bit compound timer 11 control status register 0 ch.1
8/16-bit compound timer 10 control status register 0 ch.1
8/16-bit compound timer 11 data register ch.1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
8/16-bit compound timer 10 data register ch.1
00000000B
(Continued)
27
MB95120 Series
Register
Address
Register name
R/W Initial value
abbreviation
8/16-bit compound timer 10/11 timer mode control register
ch.1
0F9BH
TMCR1
R/W
00000000B
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
0FA4H
0FA5H
PPS01
PPS00
PDS01
PDS00
PPS11
PPS10
PDS11
PDS10
PPGS
8/16-bit PPG1 cycle setting buffer register ch.0
8/16-bit PPG0 cycle setting buffer register ch.0
8/16-bit PPG1 duty setting buffer register ch.0
8/16-bit PPG0 duty setting buffer register ch.0
8/16-bit PPG1 cycle setting buffer register ch.1
8/16-bit PPG0 cycle setting buffer register ch.1
8/16-bit PPG1 duty setting buffer register ch.1
8/16-bit PPG0 duty setting buffer register ch.1
8/16-bit PPG start register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
REVC
8/16-bit PPG output inversion register
TMRH0/
TMRLRH0
0FA6H
0FA7H
16-bit reload timer/reload register (upper byte) ch.0
16-bit reload timer/reload register (lower byte) ch.0
(Disabled)
R/W
R/W
⎯
00000000B
00000000B
⎯
TMRL0/
TMRLRL0
0FA8H,
0FA9H
⎯
0FAAH
0FABH
0FACH
0FADH
0FAEH
0FAFH
0FB0H
0FB1H
0FB2H
0FB3H
0FB4H
0FB5H
PDCRH0
PDCRL0
PCSRH0
PCSRL0
PDUTH0
PDUTL0
PDCRH1
PDCRL1
PCSRH1
PCSRL1
PDUTH1
PDUTL1
16-bit PPG down counter register (upper byte) ch.0
16-bit PPG down counter register (lower byte) ch.0
16-bit PPG cycle setting buffer register (upper byte) ch.0
16-bit PPG cycle setting buffer register (lower byte) ch.0
16-bit PPG duty setting buffer register (upper byte) ch.0
16-bit PPG duty setting buffer register (lower byte) ch.0
16-bit PPG down counter register (upper byte) ch.1
16-bit PPG down counter register (lower byte) ch.1
16-bit PPG cycle setting buffer register (upper byte) ch.1
16-bit PPG cycle setting buffer register (lower byte) ch.1
16-bit PPG duty setting buffer register (upper byte) ch.1
16-bit PPG duty setting buffer register (lower byte) ch.1
R
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
R
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
0FB6H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
0FBDH
BGR1
BGR0
LIN-UART baud rate generator register 1
LIN-UART baud rate generator register 0
R/W
R/W
00000000B
00000000B
UART/SIO dedicated baud rate generator
prescaler select register ch.0
0FBEH
PSSR0
R/W
00000000B
(Continued)
28
MB95120 Series
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
0FBFH
BRSR0
R/W
00000000B
0FC0H,
0FC1H
⎯
(Disabled)
⎯
⎯
0FC2H
0FC3H
0FC4H
0FC5H
0FC6H
0FC7H
0FC8H
0FC9H
0FCAH
0FCBH
0FCCH
AIDRH
AIDRL
A/D input disable register (upper byte)
A/D input disable register (lower byte)
LCDC control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00010000B
00110000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
LCDCC
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
LCDCE6
LCDCB1
LCDCB2
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
LCDC enable register 6
LCDC blinking setting register 1
LCDC blinking setting register 2
0FCDH
to
LCDRAM
LCDC display RAM
R/W
00000000B
0FE0H
0FE1H,
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
0FEFH
ILSR
Input level select register
R/W
R/W
00000000B
01000000B
WICR
Interrupt pin select circuit control register
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
W
: Read only
: Write only
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
29
MB95120 Series
■ INTERRUPT SOURCE TABLE
Vector table address
Same level
priority order
(atsimultaneous
occurrence)
Interrupt
request
number
Bit name of
interrupt level
setting register
Interrupt source
Upper
FFFAH
FFF8H
FFF6H
FFF4H
Lower
FFFBH
FFF9H
FFF7H
FFF5H
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
UART/SIO ch.0
High
IRQ0
IRQ1
IRQ2
IRQ3
L00 [1 : 0]
L01 [1 : 0]
L02 [1 : 0]
L03 [1 : 0]
IRQ4
IRQ5
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFF3H
FFF1H
FFEFH
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
L04 [1 : 0]
L05 [1 : 0]
L06 [1 : 0]
L07 [1 : 0]
L08 [1 : 0]
L09 [1 : 0]
L10 [1 : 0]
L11 [1 : 0]
L12 [1 : 0]
L13 [1 : 0]
L14 [1 : 0]
L15 [1 : 0]
L16 [1 : 0]
L17 [1 : 0]
L18 [1 : 0]
L19 [1 : 0]
L20 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
8/16-bit compound timer ch.0 (Upper)
LIN-UART (reception)
LIN-UART (transmission)
8/16-bit PPG ch.1 (Lower)
8/16-bit PPG ch.1 (Upper)
16-bit reload timer ch.0
8/16-bit PPG ch.0 (Upper)
8/16-bit PPG ch.0 (Lower)
8/16-bit compound timer ch.1 (Upper)
16-bit PPG ch.0
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
I2C ch.0
16-bit PPG ch.1
8/10-bit A/D converter
Timebase timer
Watch prescaler/watch counter
External interrupt ch.8
External interrupt ch.9
External interrupt ch.10
External interrupt ch.11
8/16-bit compound timer ch.1 (Lower)
Flash memory
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
IRQ22
IRQ23
FFCEH
FFCCH
FFCFH
FFCDH
L22 [1 : 0]
L23 [1 : 0]
Low
30
MB95120 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Vcc
AVcc
Vss − 0.3
Vss − 0.3
VSS − 0.3
Vss + 4.0
Vss + 4.0
VSS + 4.0
*2
*2
Power supply voltage*1
V
AVR
Products with LCD internal division
resistance*3
V0 to V3
V0
V1
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
Vss − 0.3
Vss − 0.3
Vss − 0.3
− 2.0
VSS + 2.0
VSS + 2.0
VSS + 4.0
VSS + 6.0
VSS + 6.0
Vss + 4.0
Vss + 6.0
Vss + 4.0
+ 2.0
Powersupplyvoltagefor
LCD
V
V2
Products with booster circuit* 3
V3
C0, C1
VI1
Other than P50, P51*4
Input voltage*1
V
V
VI2
P50, P51
*4
Output voltage*1
VO
Maximum clamp current
ICLAMP
mA Applicable to pins*5
Total maximum clamp
current
Σ|ICLAMP|
⎯
⎯
20
mA Applicable to pins*5
IOL1
IOL2
15
15
Other than P00 to P07
“L” level maximum
output current
mA
P00 to P07
Other than P00 to P07
Average output current =
IOLAV1
4
operating current × operating ratio
(1 pin)
mA
“L” level average
current
⎯
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOLAV2
12
“L” level total maximum
output current
ΣIOL
⎯
⎯
100
50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“L” level total average
output current
ΣIOLAV
IOH1
IOH2
− 15
− 15
Other than P00 to P07
“H” level maximum
output current
⎯
mA
P00 to P07
(Continued)
31
MB95120 Series
(Continued)
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOHAV1
− 4
“H” level average
current
⎯
mA
mA
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
IOHAV2
− 8
“H” level total maximum
output current
ΣIOH
⎯
⎯
− 100
− 50
Total average output current =
“H” level total average
output current
ΣIOHAV
mA operating current × operating ratio
(Total of pins)
Power consumption
Operating temperature
Storage temperature
Pd
TA
⎯
320
+ 85
+ 150
mW
°C
− 40
− 55
Tstg
°C
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V.
*3 : V0 to V3 should not exceed VCC + 0.3 V.
*4 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI1 rating.
*5 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+B signal input.
32
MB95120 Series
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
Vcc
Limiting
P-ch
resistance
+ B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
33
MB95120 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Parameter
Symbol Pin name Condition
Unit
Remarks
Min
Max
At normal operation,
1.8*
3.3
Flash memory product,
TA = −10 °C to +85 °C
At normal operation,
Flash memory product,
TA = −40 °C to +85 °C
2.0*
3.3
Power supply
voltage
VCC,
AVCC
⎯
⎯
V
Evaluation product
TA = +5 °C to +35 °C
2.6
1.5
3.6
3.3
Holds condition in stop mode,
Flash memory product
The range of liquid crystal power
supply: without up-conversion
(The optimal value depends on
liquid crystal display elements
used.)
V0
to
V3
Power supply
voltage for LCD
⎯
⎯
VSS
VCC
V
A/D converter
reference
input voltage
AVR
TA
⎯
⎯
⎯
⎯
1.8
AVCC
V
Operating
temperature
− 40
+ 85
°C
* : The values vary with the operating frequency, machine clock or analog guarantee range.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
34
MB95120 Series
3. DC Characteristics
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Typ
Condi-
tions
Parameter
Symbol
Pin name
Unit
Remarks
Min
Max
P10 (selectable at UI0) ,
P67 (selectable at SIN)
VIH1
VIH2
⎯
⎯
0.7 VCC
⎯
⎯
VCC + 0.3
V
V
When selecting
CMOS input level
(Hysteresis input)
P50, P51
0.7 VCC
VSS + 5.5
(selectable at I2C)
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
P90 to P95,
“H” level input
voltage
VIHS1
⎯
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
PA0 to PA3,
PB0 to PB7,
PC0 to PC7,
PD0 to PD7,
PE0 to PE7
VIHS2
VIHM
P50, P51
⎯
⎯
0.8 VCC
0.8 VCC
⎯
⎯
VSS + 5.5
VCC + 0.3
V
V
RST, MOD
Hysteresis input
P10 (selectable at UI0) ,
P50, P51
When selecting
CMOS input level
(Hysteresis input)
“L” level input
voltage
VIL
⎯
VSS − 0.3
⎯
0.3 VCC
V
(selectable at I2C)
P67 (selectable at SIN)
P00 to P07
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
P50 to P53,
P60 to P67,
P70, P71,
P90 to P95,
PA0 to PA3,
PB0 to PB7,
PC0 to PC7,
PD0 to PD7,
PE0 to PE7
VILS
⎯
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
“L” level input
voltage
VILM
RST, MOD
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.2 VCC
V
V
Hysteresis input
Open-drain
output
application
voltage
VD1
P50, P51
VSS + 5.5
(Continued)
35
MB95120 Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
2.4
2.4
Typ
Max
⎯
Output pin other
than P00 to P07
VOH1
VOH2
IOH = − 4.0 mA
IOH = − 8.0 mA
⎯
V
V
“H” level output
voltage
P00 to P07
⎯
⎯
Output pin other
than P00 to
P07, RST
VOL1
IOL = 4.0 mA
IOL = 12 mA
⎯
⎯
⎯
⎯
0.4
0.4
V
V
“L” level output
voltage
VOL2
P00 to P07
Input leakage
current (Hi-Z
output leakage
current)
Port other than 0.0 V < VI <
When the pull-up
prohibition setting
ILI
− 5
⎯
⎯
+ 5
µA
µA
P50, P51
VCC
Open-drain
output leakage
current
0.0 V < VI <
VSS + 5.5 V
ILIOD
P50, P51
⎯
5
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
P52, P53,
When the pull-up
permission setting
Pull-up resistor
RPULL
VI = 0.0 V
f = 1 MHz
25
50
5
100
15
kΩ
P70, P71
Other than
AVCC, AVSS,
AVR, VCC, VSS
Input
capacitance
CIN
⎯
pF
(Continued)
36
MB95120 Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
At other than
Flash memory
writing and
erasing
⎯
11.0
14.0
mA
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
At Flash
mA memory writing
and erasing
⎯
⎯
⎯
⎯
30.0
17.6
38.1
4.5
35.0
22.4
44.9
6.0
ICC
At other than
Flash memory
writing and
erasing
mA
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
At Flash
mA memory writing
and erasing
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
mA
mA
µA
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
VCC
⎯
⎯
⎯
⎯
⎯
⎯
7.2
25
7
9.6
35
Power supply
current*
(External clock
operation)
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2)
ICCL
ICCLS
ICCT
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2)
15
µA
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
2
10
µA
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
10
16.0
14
mA
ICCMPLL
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
22.4
mA
(Continued)
37
MB95120 Series
(Continued)
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
ICCSPLL
⎯
190
250
µA
VCC
(External clock
operation)
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
ICTS
ICCH
IA
⎯
⎯
⎯
0.4
1
0.5
5
mA
µA
Power supply
current*
Sub stop mode
TA = + 25 °C
FCH = 16 MHz
At operating of A/D
conversion
1.3
2.2
mA
AVCC
FCH = 16 MHz
At stopping of A/D
conversion
IAH
⎯
1
5
µA
TA = + 25 °C
Products with
LCD internal
division
LCD internal
division
resistance
RLCD
⎯
Between V3 and VSS
⎯
⎯
300
⎯
kΩ
µA
resistance only
V0 to V3,
LCD leakage
current
ILCDL COM0 to COM3
SEG00 to SEG39
⎯
⎯
1
VV3
VV2
V3
V2
V1 = 1.5 V
V1 = 1.5 V
4.3
2.9
4.5
3.0
4.7
3.1
V
V
Output voltage
for LCD boost
Reference
voltage for
LCD boost
Products with
booster circuit
only
VV1
V1
IIN = 0.0 µA
1.4
8.5
⎯
1.5
9.8
⎯
1.7
11
5
V
Reference
voltage input
impedance
RRIN V1
⎯
kΩ
kΩ
kΩ
µA
COM0 to
COM3 output
impedance
RVCOM COM0 to COM3
V1 to V3 = 3.6 V
SEG00 to
SEG39 output RVSEG SEG00 to SEG39
impedance
⎯
⎯
⎯
⎯
7
V0 to V3,
LCD leak
ILCDL COM0 to COM3
current
− 1
⎯
+ 1
SEG00 to SEG39
* : The power-supply current is determined by the external clock.
• Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
38
MB95120 Series
4. AC Characteristics
(1) Clock Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Condi-
tions
Parameter
Pin name
Unit
16.25 MHz
Remarks
Min
Typ
Max
When using main
oscillation circuit
1.00
⎯
1.00
3.00
3.00
3.00
3.00
⎯
⎯
⎯
⎯
⎯
32.50 MHz When using external clock
10.00 MHz Main PLL multiplied by 1
8.13 MHz Main PLL multiplied by 2
6.50 MHz Main PLL multiplied by 2.5
4.06 MHz Main PLL multiplied by 4
When using sub
FCH
X0, X1
Clock frequency
⎯
⎯
32.768
32.768
⎯
kHz
kHz
ns
oscillation circuit
FCL
X0A, X1A
X0, X1
When using sub PLL
VCC = 2.3 V to 3.3 V
⎯
⎯
When using main
oscillation circuit
61.5
30.8
⎯
⎯
⎯
1000
1000
⎯
tHCYL
Clock cycle time
ns When using external clock
When using sub
µs
tLCYL X0A, X1A
30.5
oscillation circuit
tWH1
tWL1
X0
61.5
⎯
⎯
15.2
⎯
⎯
⎯
5
ns
When using external clock
Duty ratio is about 30% to
70%.
Input clock pulse width
tWH2
X0A
tWL2
µs
Input clock rise time and
fall time
tCR
X0, X0A
tCF
⎯
ns When using external clock
39
MB95120 Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Main Clock Input Port External Connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
C2
FCH
C1
• Input wave form for using external clock (sub clock)
tLCYL
tWH2
tWL2
tCR
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of Sub clock Input Port External Connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0A
X1A
X0A
X1A
Open
FCL
C2
FCL
C1
40
MB95120 Series
(2) Source Clock/Machine Clock
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Typ
Sym-
Pin
Parameter
Unit
Remarks
bol name
Min
Max
When using main clock
Min : FCH = 16.25 MHz,
PLL multiplied by 1
61.5
⎯
⎯
2000
ns
Source clock cycle time*1
(Clock before setting
division)
Max : FCH = 1 MHz, divided by 2
tSCLK
⎯
When using sub clock
Min : FCL = 32 kHz,
PLL multiplied by 4
7.6
61.0
µs
Max : FCL = 32 kHz, divided by 2
FSP
⎯
⎯
0.50
⎯
⎯
16.25 MHz When using main clock
131.072 kHz When using sub clock
When using main clock
Source clock frequency
FSPL
16.384
61.5
7.6
⎯
⎯
32000
ns Min : FSP = 16.25 MHz, no division
Machine clock cycle time*2
(Minimum instruction
execution time)
Max : FSP = 0.5 MHz, divided by 16
tMCLK
⎯
When using sub clock
976.5
µs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
1.024
⎯
⎯
16.250 MHz When using main clock
131.072 kHz When using sub clock
Machine clock frequency
⎯
FMPL
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Outline of clock generation block
F
CH
Divided by 2
(main oscillation)
Main PLL
× 1
× 2
× 2.5
× 4
Division
circuit
× 1
SCLK
(source clock)
MCLK
(machine clock)
× 1/4
× 1/8
F
CL
Divided by 2
× 1/16
(sub oscillation)
Clock mode select bit
(SYCC: SCS1, SCS0)
Sub PLL
× 2
× 3
× 4
41
MB95120 Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95F128D/F128E
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
2.7
3.6
2.3
1.8
1.8
0.5 MHz 3 MHz 5 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• Operating voltage - Operating frequency (TA = − 40 °C to + 85 °C)
• MB95F128D/F128E
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.3
2.7
3.3
2.3
2.0
2.0
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
42
MB95120 Series
• Operating voltage - Operating frequency (TA = + 5 °C to + 35 °C)
• MB95FV100D-101/102
FRAM, Main clock mode and main PLL
mode operation guarantee range
Sub PLL, Sub clock mode and watch
mode operation guarantee range
3.6
3.6
3.3
2.6
2.6
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
43
MB95120 Series
• Main PLL operation frequency
[MHz]
16.25
16
15
× 4
12
10
× 2.5
× 1
× 2
7.5
6
5
3
[MHz]
10
0
3
4 4.062
5
6.4 6.5
8
8.125
Machine clock frequency (FMP)
44
MB95120 Series
(3) External Reset
Parameter
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns At normal operating
RST “L” level pulse
width
Oscillation time of oscillator*2
At stop mode, sub clock mode,
µs
tRSTL
⎯
+ 2 tMCLK
sub sleep mode, and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of µs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
2 tMCLK
Oscillation time
of oscillator
Oscillation stabilization wait time
Execute instruction
Internal reset
45
MB95120 Series
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Power supply rising time
Power supply cutoff time
tR
⎯
⎯
⎯
36
ms
ms
Waiting time until
power-on
tOFF
1
⎯
t
R
tOFF
1.5 V
0.2 V
0.2 V
0.2 V
V
CC
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
Hold Condition in stop mode
VSS
46
MB95120 Series
(5) Peripheral Input Timing
Parameter
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Pin name
Unit
Min
Max
Peripheral input “H” pulse
width
tILIH
tIHIL
2 tMCLK*
⎯
ns
ns
INT00 to INT07,
INT10 to INT13,
EC0, EC1, TI0, TRG0/ADTG, TRG1
Peripheral input “L” pulse
width
2 tMCLK*
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
tIHIL
INT00 to INT07,
INT10 to INT13, EC0, EC1,
TI0, TRG0/ADTG, TRG1
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
47
MB95120 Series
(6) UART/SIO, Serial I/O Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
UCK ↓ → UO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
UCK0
UCK0, UO0
UCK0, UI0
UCK0, UI0
UCK0
4 tMCLK*
− 190
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1TTL.
+190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
4 tMCLK*
4 tMCLK*
0
UCK ↑ → valid UI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK ↓ → UO time
⎯
⎯
UCK0
⎯
External clock
operation output pin :
CL = 80 pF + 1TTL.
UCK0, UO0
UCK0, UI0
UCK0, UI0
190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
UCK ↑ → valid UI hold time
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK0
0.8 V
0.8 V
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
UCK0
tSLSH
tSHSL
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
48
MB95120 Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
5 tMCLK*3
−95
Max
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
tSLOVI SCK, SOT
+95
tIVSHI
tSHIXI
tSLSH
tSHSL
SCK, SIN
SCK, SIN
SCK
tMCLK*3 + 190
⎯
SCK ↑ → valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSLOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSHE SCK, SIN operationoutputpin:
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SCK fall time
tSHIXE SCK, SIN
tMCLK*3 + 95
⎯
tF
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
49
MB95120 Series
• Internal shift clock mode
SCK
t
SCYC
2.4 V
0.8 V
0.8 V
t
SLOVI
2.4 V
0.8 V
SOT
SIN
t
IVSHI
tSHIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
SCK
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
SLOVE
0.2 VCC
t
R
t
F
t
2.4 V
0.8 V
SOT
SIN
tSHIXE
tIVSHE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
50
MB95120 Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
5 tMCLK*3
−95
Max
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
SCK
SCK, SOT
SCK, SIN
SCK, SIN
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
+95
tMCLK*3 + 190
⎯
SCK ↓ → valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSHOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSLE
tSLIXE
tF
SCK, SIN operation output pin :
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SCK fall time
SCK, SIN
tMCLK*3 + 95
⎯
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
51
MB95120 Series
• Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
t
SHOVI
2.4 V
0.8 V
SOT
t
IVSLI
t
SLIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
SIN
• External shift clock mode
tSHSL
tSLSH
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
0.2 VCC
tF
t
R
tSHOVE
2.4 V
0.8 V
SOT
SIN
tSLIXE
t
IVSLE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
52
MB95120 Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
−95
+95
⎯
Internal clock
SCK, SIN operation output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SOT → SCK ↓ delay time
tSLIXI
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
tSOVLI
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tSLIXI
tIVSLI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
53
MB95120 Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK, SOT
−95
+95
⎯
Internal clock
SCK, SIN operating output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SOT → SCK ↑ delay time
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
t
SCYC
2.4 V
2.4 V
SCK
0.8 V
t
SOVHI
t
SLOVI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
t
IVSHI
tSHIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
54
MB95120 Series
(8) I2C Timing
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin
name
Parameter
Symbol
Conditions Standard-mode
Fast-mode
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL0
0
100
0
400
kHz
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
SCL0
SDA0
tHD;STA
4.0
⎯
0.6
⎯
µs
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
SCL0
SCL0
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
SCL0
SDA0
tSU;STA
4.7
0
⎯
3.45*2
⎯
0.6
0
⎯
0.9*3
⎯
µs
µs
µs
µs
µs
R = 1.7 kΩ,
C = 50 pF*1
SCL0
SDA0
Data hold time SCL ↓ → SDA ↓ ↑
tHD;DAT
SCL0
SDA0
Data setup time SDA ↓ ↑ → SCL ↑ tSU;DAT
0.25
4.0
4.7
0.1
0.6
1.3
Stop condition setup time SCL ↑ →
SDA ↑
SCL0
SDA0
tSU;STO
⎯
⎯
Bus free time between stop
tBUF
SCL0
SDA0
⎯
⎯
condition and start condition
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
tWAKEUP
SDA0
SCL0
t
HD;STA
t
HD;DAT
t
HIGH
tBUF
t
LOW
t
SU;STO
t
HD;STA
t
SU;DAT
SCL
tSU;STA
f
55
MB95120 Series
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value*2
Sym- Pin
bol name
Condi-
tions
Parameter
Unit
Remarks
Min
Max
SCL clock
“L” width
(2 + nm / 2) tMCLK − 20
tLOW SCL0
⎯
ns Master mode
SCL clock
“H” width
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
tHIGH SCL0
ns Master mode
Master mode
Maximum value is
applied when m,
ns n = 1, 8.
Start condition
hold time
SCL0
tHD;STA
(−1 + nm / 2) tMCLK − 20
(−1 + nm) tMCLK + 20
SDA0
Otherwise, the
minimum value is
applied.
Stop condition
setup time
SCL0
tSU;STO
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode
SDA0
Start condition
setup time
SCL0
tSU;STA
SDA0
Bus free time
between stop
condition and
start condition
SCL0
tBUF
(2 nm + 4) tMCLK − 20
3 tMCLK − 20
⎯
⎯
ns
SDA0
SCL0
SDA0
Data hold time tHD;DAT
ns Master mode
Master mode
R = 1.7 kΩ,
C = 50 pF*1
When assuming
that “L” of SCL is
not extended, the
minimum value is
Data setup
tSU;DAT
SCL0
SDA0
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns applied to first bit
time
of continuous
data.
Otherwise,
the maximum
value is applied.
Minimum value is
appliedtointerrupt
at 9th SCL↓.
Maximum value is
appliedtointerrupt
at 8th SCL↓.
Setup time
between
clearing
interrupt and
SCL rising
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
tSU;INT SCL0
ns
SCL clock “L”
width
4 tMCLK − 20
4 tMCLK − 20
tLOW SCL0
tHIGH SCL0
⎯
⎯
ns At reception
ns At reception
SCL clock “H”
width
Undetected when
ns 1 tMCLK is used at
reception
Start condition
detection
SCL0
tHD;STA
2 tMCLK − 20
⎯
SDA0
(Continued)
56
MB95120 Series
(Continued)
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value*2
Sym- Pin
bol name
Condi-
tions
Parameter
Unit
Remarks
Min
Max
Undetected when
ns 1 tMCLK is used at
reception
Stop condition
detection
SCL0
tSU;STO
2 tMCLK − 20
⎯
SDA0
Undetected when
ns 1 tMCLK is used at
reception
Restart condition
detection condition
SCL0
tSU;STA
2 tMCLK − 20
⎯
SDA0
SCL0
tBUF
Bus free time
2 tMCLK − 20
2 tMCLK − 20
tLOW − 3 tMCLK − 20
0
⎯
⎯
⎯
⎯
⎯
ns At reception
SDA0
SCL0
tHD;DAT
At slave transmission
mode
Data hold time
Data setup time
Data hold time
Data setup time
ns
SDA0
R = 1.7 kΩ,
C = 50 pF*1
SCL0
tSU;DAT
At slave transmission
mode
ns
SDA0
SCL0
tHD;DAT
ns At reception
ns At reception
SDA0
SCL0
tSU;DAT
tMCLK − 20
SDA0
Oscillation
stabilization
wait time +
2 tMCLK − 20
SDA↓→SCL↑
(at wakeup function)
tWAKE- SCL0
⎯
ns
UP
SDA0
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) .
• n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) .
• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
• Fast-mode :
: 0.9 MHz < tMCLK ≤ 10 MHz
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
(m, n) = (1, 22) , (5, 4)
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
57
MB95120 Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVcc = Vcc = 1.8 V to 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Typ
⎯
Parameter
Resolution
Symbol
Unit
Remarks
Min
⎯
Max
10
bit
Total error
− 3.0
− 2.5
− 1.9
⎯
+ 3.0
+ 2.5
+ 1.9
LSB
LSB
LSB
⎯
Linearity error
⎯
Differential linear error
⎯
2.7 V ≤ AVcc ≤
AVss − 1.5 LSB AVss + 0.5 LSB AVss + 2.5 LSB
AVss − 0.5 LSB AVss + 1.5 LSB AVss + 3.5 LSB
AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB
AVR − 2.5 LSB AVR − 0.5 LSB AVR + 1.5 LSB
V
V
3.3 V
Zero transition voltage
VOT
VFST
⎯
1.8 V ≤ AVcc <
2.7 V
2.7 V ≤ AVcc ≤
3.3 V
V
Full-scale transition
voltage
1.8 V ≤ AVcc <
2.7 V
V
2.7 V ≤ AVcc ≤
0.6
20
⎯
⎯
140
140
µs
µs
3.3 V
Compare time
Sampling time
1.8 V ≤ AVcc <
2.7 V
2.7 V ≤ AVcc ≤
3.3 V,
At external
0.4
30
⎯
⎯
µs
∞
∞
impedance < 1.8 kΩ
⎯
1.8 V ≤ AVcc <
2.7 V,
µs At external
impedance <
14.8 kΩ
Analog input current
Analog input voltage
Reference voltage
IAIN
VAIN
⎯
−0.3
AVss
⎯
⎯
⎯
+0.3
AVR
AVcc
µA
V
AVss + 1.8
V
AVR pin
AVR pin,
IR
⎯
⎯
400
600
5
µA During A/D
Reference voltage
supply current
operation
AVR pin,
µA
IRH
⎯
At stop mode
58
MB95120 Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
R
C
2.7 V ≤ AVcc ≤ 3.6 V 1.7 kΩ (Max)
1.8 V ≤ AVcc < 2.7 V 84 kΩ (Max)
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
AVCC ≥ 2.7 V
AVCC ≥ 2.7 V
100
20
90
80
70
60
18
16
14
12
10
8
AVCC ≥ 1.8 V
50
40
30
20
10
0
6
4
2
0
0
5
10 15 20 25 30 35 40
0
1
2
3
4
Minimum sampling time [µs]
Minimum sampling time [µs]
• About errors
As |AVR − AVSS| becomes smaller, values of relative errors grow larger.
59
MB95120 Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
V
FST
3FF
H
3FFH
3FE
H
3FE
H
Actual conversion
characteristic
1.5 LSB
3FD
H
3FD
H
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
H
H
H
H
004
003
002
001
H
H
H
H
V
NT
V
OT
Actual conversion
characteristic
1 LSB
0.5 LSB
Ideal characteristics
AVSS
AVSS
AVR
AVR
Analog input
Analog input
Total error of
digital output N
AVR − AVSS
1024
VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
1 LSB =
(V)
[LSB]
1 LSB
N
: A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) to N.
(Continued)
60
MB95120 Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
004
003
002
001
H
H
H
H
characteristics
Actual conversion
characteristic
3FF
3FE
3FD
H
H
H
Actual conversion
characteristic
Ideal
characteristics
VFST
(measurement
value)
Actual conversion
characteristic
Actual conversion
characteristic
3FC
H
VOT (measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error
Differential linear error
Actual conversion
characteristic
Ideal characteristics
3FF
3FE
3FD
H
N+1
N
H
H
Actual conversion
characteristic
{1 LSB × N + VOT
}
H
V
(N+1)T
VFST
H
H
H
(measurement
value)
V
NT
004
003
002
001
H
H
H
H
N-1
N-2
V
NT
Actual conversion
characteristic
Actual conversion
characteristic
Ideal characteristics
VOT (measurement value)
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linear error in
digital output N
VNT − {1 LSB × N + VOT}
V (N + 1) T − VNT
Differential linear error
in digital output N
=
=
− 1
1 LSB
1 LSB
N
: A/D Converter digital output value
VNT : A voltage at which digital output transits from (N − 1) to N.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
61
MB95120 Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2*1
3.0*2
s
s
Excludes 00H programming prior erasure.
Excludes 00H programming prior erasure.
Sector erase time
(16 Kbytes sector)
⎯
0.5*1
12.0*2
Byte programming time
Program/erase cycle
⎯
32
3600
µs Excludes system-level overhead.
cycle
10000
⎯
⎯
Power supply voltage at
program/erase
2.7
⎯
⎯
3.3
V
Flash memory data retention
time
20*3
⎯
year Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
62
MB95120 Series
■ MASK OPTION
Part number
Specifying procedure
Clock mode select
• Single-system clock mode
• Dual-system clock mode
MB95F128D
MB95F128E MB95FV100D-101 MB95FV100D-102
No.
Setting disabled
Setting disabled
Setting disabled
Changing by the switch on
MCU board
1
2
3
4
5
Dual-system clock mode
LCDC Booster circuit select
• Internal division resistance
• Booster circuit
internal
Booster
division
circuit
internal
division
resistance
Booster
circuit
resistance
Low voltage detection reset*
• With low voltage detection reset
• Without low voltage detection reset
No
No
No
No
Clock supervisor*
• With clock supervisor
• Without clock supervisor
Fixed to oscillation
stabilization wait time of
(214−2) /FCH
Oscillation stabilization
wait time
Fixed to oscillation stabilization wait
time of (214−2) /FCH
* : Low voltage detection reset and clock supervisor are options of 5-V products.
63
MB95120 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB95F128DPMC
MB95F128EPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB95F128DPF
MB95F128EPF
100-pin plastic QFP
(FPT-100P-M06)
MB2146-301A
(MB95FV100D-101PBT)
Included LCDC internal
division resistance
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
MB2146-302A
(MB95FV100D-102PBT)
(
)
Included LCDC booster
64
MB95120 Series
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Gullwing
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*
14.00 0.10(.551 .004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
–
0.10 .059 +.008
–.004
INDEX
(Mounting height)
0.10 0.10
(.004 .004)
(Stand off)
100
26
0˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60 0.15
(.024 .006)
1
25
0.50(.020)
0.20 0.05
(.008 .002)
0.145 0.055
(.0057 .0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 FUJITSU LIMITED F100031S-c-2-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
65
MB95120 Series
(Continued)
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90 0.40(.941 .016)
*
20.00 0.20(.787 .008)
80
51
81
50
0.10(.004)
17.90 0.40
(.705 .016)
*
14.00 0.20
(.551 .008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 –+00..2305
.118 +–..000184
(Mounting height)
0~8˚
1
30
0.65(.026)
0.32 0.05
(.013 .002)
0.17 0.06
(.007 .002)
M
0.13(.005)
0.25 0.20
(.010 .008)
(Stand off)
0.80 0.20
(.031 .008)
"A"
0.88 0.15
(.035 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
66
MB95120 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
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function and schematic diagrams, shall not be construed as license
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Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
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Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
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over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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Edited
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F0701
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