MB95F166D [FUJITSU]
8-bit Microcontroller; 8位微控制器型号: | MB95F166D |
厂家: | FUJITSU |
描述: | 8-bit Microcontroller |
文件: | 总68页 (文件大小:404K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12618-2E
8-bit Microcontroller
CMOS
F2MC-8FX MB95160 Series
MB95F166D/166D/FV100D-101
■ DESCRIPTION
The MB95160 series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
• Timer
• 8/16-bit compound timer × 2 channels
Can be used to interval timer, PWC timer, PWM timer and input capture.
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 1 channel
• Timebase timer × 1 channel
• Watch prescaler × 1 channel
• LIN-UART × 1 channel
• LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.3
MB95160 Series
(Continued)
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
•
• I2C × 1 channel
Built-in wake-up function
• External interrupt × 8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 8 channels
8-bit or 10-bit resolution can be selected.
• LCD controller (LCDC)
• 32 SEG × 4 COM (Max 128 pixels) (Built-in internal division resistance product)
• With blinking function
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
• I/O port
• The number of maximum ports : Max 53
• Port configuration
- General-purpose I/O ports (N-ch open drain) : 2 ports
- General-purpose I/O ports (CMOS)
• Programmable input voltage levels of port
CMOS input level/hysteresis input level
: 51 ports
• Flash memory security function (Flash memory device only)
Protects the content of Flash memory
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MB95160 Series
■ PRODUCT LINEUP
Part number
Parameter
MB95F166D
MB95166D
Type
Flash memory product
Mask ROM product
ROM capacity
RAM capacity
Reset output
Clock system
32 Kbytes
1 Kbyte
No
Dual clock
Low voltage
detection reset
No
Number of basic instructions
Instruction bit length
Instruction length
: 136
: 8 bits
: 1 to 3 bytes
Data bit length
: 1, 8, and 16 bits
CPU functions
Minimum instruction execution time : 61.5 ns (at machine clock frequency
16.25 MHz)
Interrupt processing time
: 0.6 μs (at machine clock frequency
16.25 MHz)
General-purpose I/O port (N-ch open drain) : 2 ports
General-purpose I/O port (CMOS)
Programmable input voltage levels of port.
CMOS input level/hysteresis input level.
: 51 ports
Ports (Max 53 ports)
Timebase timer
(1 channel)
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Reset generated cycle
Watchdog timer
Wild register
At main oscillation clock 10 MHz
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
: Min 105 ms
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
I2C
(1 channel)
Data transfer capable in UART/SIO
Full duplex double buffer,
UART/SIO
(1 channel)
variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock synchronous (SIO) or clock asynchronous (UART) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Capable of serial data transfer synchronous or asynchronous to clock signal.
LIN functions available as the LIN master or LIN slave.
LIN-UART
(1 channel)
(Continued)
DS07-12618-2E
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MB95160 Series
(Continued)
Part number
Parameter
MB95F166D
MB95166D
8/10-bit
A/D converter
(8 channels)
8-bit or 10-bit resolution can be selected.
COM output
: 4 (Max)
SEG output
LCD drive power supply (bias) pin
: 32 (Max)
: 4
32 SEG × 4 COM : 128 pixels can be displayed. (Built-in internal division resistance
LCD controller
(LCDC)
product)
Duty LCD mode
Operable in LCD standby mode
Built-in internal division resistance
With blinking function
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer ×
1 channel”.
Built-in timer function, PWC function, PWM function, capture function, and square
wave form output
8/16-bit compound
timer (2 channels)
Count clock : 7 internal clocks and external clock can be selected.
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sources
Support for external trigger start
16-bit PPG
(1 channel)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”.
Counter operating clock : Eight selectable clock sources
8/16-bit PPG
(2 channels)
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when
selecting clock source 1 second and setting counter value to 60)
Watch counter
Watch prescaler
(1 channel)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Min) : 10000 times
Data retention time : 20 years
Flash memory
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch, and timebase timer
* : For details of option, refer to “■ MASK OPTION”.
Note : Part number of the evaluation product in MB95160 series is MB95FV100D-101 (internal division resistance
included) . When using it, the MCU board (MB2146-301A) is required.
4
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MB95160 Series
■ OSCILLATION STABILIZATION WAIT TIME
For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value
of main clock oscillation stabilization wait time from among the following four values.
Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabili-
zation wait time at the maximum value.
Select of oscillation stabilization wait time
Remarks
(22 − 2) /FCH
(212 − 2) /FCH
(213 − 2) /FCH
(214 − 2) /FCH
0.5 μs (at main oscillation clock 4 MHz)
Approx. 1.02 ms (at main oscillation clock 4 MHz)
Approx. 2.05 ms (at main oscillation clock 4 MHz)
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F166D
MB95FV100D-101
MB95166D
Package
FPT-64P-M23
FPT-64P-M24
BGA-224P-M08
: Available
: Unavailable
DS07-12618-2E
5
MB95160 Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The evaluation product has not only the functions of the MB95160 series but also those of other products to
support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95160 series are therefore access-barred. Read/write access to these
access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in
unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
Flash memory products and Mask ROM products, do not use these values in the program.
The functions corresponding to certain bits in single-byte registers may not be supported on some Flash memory
products and Mask ROM products. However, reading or writing to these bits will not cause malfunction of the
hardware. Also, as the evaluation, Flash memory products and Mask ROM products are designed to have
identical software operation, no particular precautions are required.
• Difference of Memory Spaces
If the amount of memory on the evaluation product is different from that of the Flash memory products and Mask
ROM products, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS”
and “■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage is different among the evaluation, Flash memory products and Mask ROM products.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”
• Difference MOD pins
A pull-down resistor is provided for the MOD pin of the Mask ROM product.
6
DS07-12618-2E
MB95160 Series
■ PIN ASSIGNMENT
(TOP VIEW)
AVCC
AVR
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P60/SEG16/PPG10
PC7/SEG15
PC6/SEG14
PC5/SEG13
PC4/SEG12
PC3/SEG11
PC2/SEG10
PC1/SEG09
PC0/SEG08
PB7/SEG07
PB6/SEG06
PB5/SEG05
PB4/SEG04
PB3/SEG03
PB2/SEG02
PB1/SEG01
2
P14/PPG0
P13/ADTG/TRG0
P12/UCK0
P11/UO0
3
4
5
6
P10/UI0
7
P24/SDA0/EC0
P23/SCL0/TO01
P22/TO00
P21/PPG01
P20/PPG00
MOD
8
LQFP-64
9
10
11
12
13
14
15
16
X0
X1
V
SS
(FPT-64P-M23,FPT-64P-M24)
DS07-12618-2E
7
MB95160 Series
■ PIN DESCRIPTION
I/O circuit
type*
Pin no.
Pin name
Function
A/D converter power supply pin.
1
2
AVCC
AVR
⎯
⎯
A/D converter reference input pin.
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 output.
3
P14/PPG0
General-purpose I/O port.
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and
A/D trigger input (ADTG) .
P13/TRG0/
ADTG
4
H
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 clock I/O.
5
6
7
P12/UCK0
P11/UO0
P10/UI0
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data output.
General-purpose I/O port.
The pin is shared with UART/SIO ch.0 data input.
G
I
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 clock input
(EC0) and I2C ch.0 data I/O (SDA0) .
P24/EC0/
SDA0
8
9
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 output (TO01)
and I2C ch.0 clock I/O (SCL0) .
P23/TO01/
SCL0
General-purpose I/O port.
The pin is shared with 8/16-bit compound timer ch.0 output.
10
11
12
P22/TO00
P21/PPG01
P20/PPG00
General-purpose I/O port.
The pin is shared with 8/16-bit PPG ch.0 output.
H
General-purpose I/O port.
The pin is shared with 8/16-bit PPG ch.0 output.
13
14
15
16
17
18
19
20
21
22
23
24
25
MOD
X0
B
A
Operating mode designation pin.
Main clock oscillation pins.
X1
VSS
⎯
⎯
H
Power supply pin (GND).
Power supply pin.
VCC
PG0
General-purpose I/O port.
X1A
A
Sub clock oscillation pins (32 kHz).
Reset pin.
X0A
RST
B’
P90/V3
P91/V2
P92/V1
P93/V0
General-purpose I/O ports.
The pins are shared with power supply pin for LCDC drive.
R
(Continued)
8
DS07-12618-2E
MB95160 Series
I/Ocircuit
type*
Pin no.
Pin name
Function
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
P94
S
General-purpose I/O ports.
General-purpose I/O ports.
P95
PA0/COM0
PA1/COM1
PA2/COM2
PA3/COM3
PB0/SEG00
PB1/SEG01
PB2/SEG02
PB3/SEG03
PB4/SEG04
PB5/SEG05
PB6/SEG06
PB7/SEG07
PC0/SEG08
PC1/SEG09
PC2/SEG10
PC3/SEG11
PC4/SEG12
PC5/SEG13
PC6/SEG14
PC7/SEG15
M
The pins are shared with LCDC COM output (COM0 to COM3).
General-purpose I/O ports.
The pins are shared with LCDC SEG output (SEG00 to SEG07).
M
General-purpose I/O ports.
The pins are shared with LCDC SEG output (SEG08 to SEG15).
M
P60/SEG16/
PPG10
48
49
General-purpose I/O ports.
The pins are shared with LCDC SEG output (SEG16, SEG17) and
8/16-bit PPG ch.1 output (PPG10, PPG11) .
P61/SEG17/
PPG11
M
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG18) and 8/16-bit
compound timer ch.1 output (TO10) .
P62/SEG18/
TO10
50
(Continued)
DS07-12618-2E
9
MB95160 Series
(Continued)
I/Ocircuit
type*
Pin no.
Pin name
Function
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG19) and 8/16-bit
compound timer ch.1 output (TO11) .
P63/SEG19/
TO11
51
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG20) and 8/16-bit
compound timer ch.1 clock input (EC1) .
P64/SEG20/
EC1
52
53
54
55
M
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG21) and LIN-UART
clock I/O (SCK) .
P65/SEG21/
SCK
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG22) and LIN-UART
data output (SOT) .
P66/SEG22/
SOT
General-purpose I/O port.
The pin is shared with LCDC SEG output (SEG23) and LIN-UART
data input (SIN) .
P67/SEG23/
SIN
N
P07/INT07/
AN07/SEG24
56
57
58
59
60
61
62
P06/INT06/
AN06/SEG25
P05/INT05/
AN05/SEG26
P04/INT04/
AN04/SEG27
General-purpose I/O port.
The pins are shared with external interrupt input (INT00 to INT07) ,
A/D analog input (AN00 to AN07) and LCDC SEG output (SEG24 to
SEG31) .
F
P03/INT03/
AN03/SEG28
P02/INT02/
AN02/SEG29
P01/INT01/
AN01/SEG30
P00/INT00/
AN00/SEG31
63
64
AVSS
⎯
Power supply pin (GND) of A/D converter
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
10
DS07-12618-2E
MB95160 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
- Feedback resistance : approx. 24 MΩ
(Evaluation product : approx. 10 MΩ)
- Dumping resistance : approx.144 kΩ
(Evaluation product : without dumping
resistance)
X1 (X1A)
X0 (X0A)
Clock input
N-ch
Standby control
B
• Only for input
• Hysteresis input only for Mask ROM prod-
uct
Mode input
R
• Pull-down resistor only for MODE pin of
Mask ROM product
B’
F
Hysteresis input
Reset input
• CMOS output
• LCD output
• Hysteresis input
• Analog input
P-ch
N-ch
Digital output
Digital output
Analog input
LCD output
Hysteresis input
A/D control
LCD control
Standby control
External interrupt
control
G
• CMOS output
• CMOS input
• Hysteresis input
• With pull-up control
R
P-ch
Pull-up control
Digital output
P-ch
N-ch
Digital output
CMOS input
Hysteresis input
Standby control
(Continued)
DS07-12618-2E
11
MB95160 Series
Type
Circuit
Remarks
H
• CMOS output
R
P-ch
• Hysteresis input
• With pull-up control
Pull-up control
Digital output
P-ch
N-ch
Digital output
Hysteresis input
Standby control
Standby control
I
• N-ch open drain output
• CMOS input
Digital output
• Hysteresis input
N-ch
CMOS input
Hysteresis input
M
• CMOS output
• LCD output
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
LCD output
LCD control
Hysteresis input
Standby control
N
• CMOS output
• LCD output
• CMOS input
• Hysteresis input
P-ch
N-ch
Digital output
Digital output
LCD output
CMOS input
Hysteresis input
LCD control
Standby control
R
• CMOS output
P-ch
N-ch
• LCD power supply
• Hysteresis input
Digital output
Digital output
LCD built-in division
resistance I/O
Standby control
LCD control
Hysteresis input
(Continued)
12
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MB95160 Series
(Continued)
Type
Circuit
Remarks
S
• CMOS output
• Hysteresis input
P-ch
Digital output
Digital output
N-ch
Hysteresis input
Standby control
DS07-12618-2E
13
MB95160 Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
• Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent dam-
age. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins. If there is unused output pin, make it to open.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS pins
near this device.
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pin to VCC or VSS and to provide a low-impedance connection.
14
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MB95160 Series
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN07 pins.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
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15
MB95160 Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
Parallel programmers
FPT-64P-M23
TEF110-95F168HPMC
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
FPT-64P-M24
TEF110-95F168HPMC1
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
Flash memory
32 Kbytes
CPU address
8000H
Programmer address*
18000H
FFFFH
1FFFFH
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in
Flash memory.
• Programming Method
1) Set the type code of the parallel programmer to “17222”.
2) Load program data to programmer addresses 18000H to 1FFFFH.
3) Programmed by parallel programmer
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MB95160 Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
RST
Reset control
ROM
RAM
X0, X1
Clock control
X0A, X1A
Interrupt control
Wild register
Watch prescaler
Watch counter
PG0
P00/INT00 to
P07/INT07
External interrupt
P60/SEG16/PPG10
P61/SEG17/PPG11
8/16-bit PPG ch.1
8/16-bit
P10/UI0
P11/UO0
P12/UCK0
UART/SIO
P62/SEG18/TO10
P63/SEG19/TO11
P64/SEG20/EC1
compound timer ch.1
P13/TRG0/ADTG
16-bit PPG
P14/PPG0
P65/SEG21/SCK
P66/SEG22/SOT
P67/SEG23/SIN
LIN-UART
P20/PPG00
P21/PPG01
8/16-bit PPG ch.0
P90/V3 to P93/V0
P22/TO00
P23/TO01/SCL0
P24/EC0/SDA0
8/16-bit
compound timer ch.0
PA0/COM0 to PA3/COM3
PB0/SEG00 to PB7/SEG07
PC0/SEG08 to PC7/SEG15
(P00/SEG31 to P07/SEG24)
LCDC
I2C
(P00/AN00 to
P07/AN07)
8/10-bit
A/D converter
AVCC
AVSS
AVR
P94, P95
Port
Port
Other pins
MOD, VSS, VCC
DS07-12618-2E
17
MB95160 Series
■ CPU CORE
1. Memory space
Memory space of the MB95160 series is 64 Kbytes and consists of I/O area, data area, and program area. The
memory space includes special-purpose areas such as the general-purpose registers and vector table.
• Memory Map
MB95F166D
MB95FV100D-101
I/O
MB95166D
0000H
0000H
0000H
I/O
I/O
0080H
0100H
0200H
0080H
0100H
0080H
0100H
RAM 3.75 Kbytes
Register
RAM 1 Kbyte
RAM 1 Kbyte
Register
Register
0200H
0480H
0200H
0480H
Access
Access
prohibited
prohibited
0F80H
1000H
0F80H
1000H
0F80H
1000H
Exterded I/O
Extended I/O
Extended I/O
Access
Access
prohibited
prohibited
8000H
8000H
Flash memory
60 Kbytes
Flash memory
32 Kbytes
Mask ROM
32 Kbytes
FFFFH
FFFFH
FFFFH
18
DS07-12618-2E
MB95160 Series
2. Register
The MB95160 series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
Extra pointer (EP)
Stack pointer (SP)
Program status (PS)
: A 16-bit register for index modification.
: A 16-bit pointer to point to a memory address.
: A 16-bit register to indicate a stack area.
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register.
Initial Value
16-bit
FFFDH
0000H
0000H
0000H
0000H
0000H
0030H
: Program counter
: Accumulator
PC
AH
TH
AL
TL
: Temporary accumulator
: Index register
IX
: Extra pointer
EP
SP
PS
: Stack pointer
: Program status
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) .
• Structure of the Program Status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
R4
R3
R2
R1
R0 DP2 DP1 DP0
H
I
IL1
IL0
N
Z
PS
C
V
RP
DP
CCR
DS07-12618-2E
19
MB95160 Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
OP code lower
"0" "0" "0" "0" "0" "0" "0" "1"
R4 R3 R2 R1 R0 b2
b1
b0
Generated address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
0000H to 007FH (without mapping)
0080H to 00FFH (without mapping)
0100H to 017FH
XXXB (no effect to mapping)
0000H to 007FH
000B (initial value)
001B
010B
011B
100B
101B
110B
111B
0180H to 01FFH
0200H to 027FH
0080H to 00FFH
0280H to 02FFH
0300H to 037FH
0380H to 03FFH
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
I flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
0
IL0
0
Interrupt level
Priority
0
1
2
High
0
1
1
0
1
1
3
Low (no interruption)
N flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
Z flag : Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
V flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
20
DS07-12618-2E
MB95160 Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains
8-register. Up to a total of 32 banks can be used on the MB95160 series. The bank currently in use is specified
by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0)
to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R1
R0
R1
R0
R1
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
R2
R3
R4
R5
R6
R7
1FFH
Bank 31
107H
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
Bank 0
Memory area
DS07-12618-2E
21
MB95160 Series
■ I/O MAP
Register
abbreviation
Address
Register name
R/W
Initial value
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
PDR0
DDR0
PDR1
DDR1
⎯
Port 0 data register
Port 0 direction register
Port 1 data register
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
⎯
Port 1 direction register
(Disabled)
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
⎯
Oscillation stabilization wait time setting register
PLL control register
R/W
R/W
R/W
R/W
11111111B
00000000B
1010X011B
00000000B
System clock control register
Standby control register
Reset factor register
R/W XXXXXXXXB
Timebase timer control register
Watch prescaler control register
Watchdog timer control register
(Disabled)
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
⎯
PDR2
DDR2
Port 2 data register
R/W
R/W
00000000B
00000000B
Port 2 direction register
0010H
to
0015H
⎯
(Disabled)
⎯
⎯
0016H
0017H
PDR6
DDR6
Port 6 data register
R/W
R/W
00000000B
00000000B
Port 6 direction register
0018H
to
001BH
⎯
(Disabled)
⎯
⎯
001CH
001DH
001EH
001FH
0020H
0021H
0022H
0023H
PDR9
DDR9
PDRA
DDRA
PDRB
DDRB
PDRC
DDRC
Port 9 data register
Port 9 direction register
Port A data register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Port A direction register
Port B data register
Port B direction register
Port C data register
Port C direction register
0024H
to
0029H
⎯
(Disabled)
⎯
⎯
(Continued)
22
DS07-12618-2E
MB95160 Series
Register
abbreviation
Address
Register name
R/W Initial value
002AH
002BH
002CH
002DH
002EH
PDRG
DDRG
⎯
Port G data register
Port G direction register
(Disabled)
R/W
R/W
⎯
00000000B
00000000B
⎯
PUL1
PUL2
Port 1 pull-up register
Port 2 pull-up register
R/W
R/W
00000000B
00000000B
002FH
to
0034H
⎯
(Disabled)
⎯
⎯
0035H
0036H
0037H
0038H
0039H
003AH
003BH
003CH
003DH
PULG
T01CR1
T00CR1
T11CR1
T10CR1
PC01
Port G pull-up control register
8/16-bit compound timer 01 control status register 1 ch.0
8/16-bit compound timer 00 control status register 1 ch.0
8/16-bit compound timer 11 control status register 1 ch.1
8/16-bit compound timer 10 control status register 1 ch.1
8/16-bit PPG1 control register ch.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
PC00
8/16-bit PPG0 control register ch.0
PC11
8/16-bit PPG1 control register ch.1
PC10
8/16-bit PPG0 control register ch.1
003EH
to
0041H
⎯
(Disabled)
⎯
⎯
0042H
0043H
PCNTH0
PCNTL0
16-bit PPG status control register (upper byte) ch.0
16-bit PPG status control register (lower byte) ch.0
R/W
R/W
00000000B
00000000B
0044H
to
0047H
⎯
(Disabled)
⎯
⎯
0048H
0049H
004AH
004BH
EIC00
EIC10
EIC20
EIC30
External interrupt circuit control register ch.0/ch.1
External interrupt circuit control register ch.2/ch.3
External interrupt circuit control register ch.4/ch.5
External interrupt circuit control register ch.6/ch.7
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
004CH
to
004FH
⎯
(Disabled)
⎯
⎯
0050H
0051H
0052H
0053H
0054H
SCR
SMR
LIN-UART serial control register
LIN-UART serial mode register
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00001000B
00000000B
SSR
LIN-UART serial status register
RDR/TDR
ESCR
LIN-UART reception/transmission data register
LIN-UART extended status control register
00000100B
(Continued)
DS07-12618-2E
23
MB95160 Series
Register
Address
Register name
R/W Initial value
abbreviation
0055H
0056H
0057H
0058H
0059H
005AH
ECCR
SMC10
SMC20
SSR0
LIN-UART extended communication control register
UART/SIO serial mode control register 1 ch.0
UART/SIO serial mode control register 2 ch.0
UART/SIO serial status register ch.0
R/W
R/W
R/W
R/W
R/W
R
000000XXB
00000000B
00100000B
00000001B
00000000B
00000000B
TDR0
UART/SIO serial output data register ch. 0
UART/SIO serial input data register ch.0
RDR0
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
0060H
0061H
0062H
0063H
0064H
0065H
IBCR00
IBCR10
IBSR0
IDDR0
IAAR0
ICCR0
I2C bus control register 0 ch.0
I2C bus control register 1 ch.0
I2C bus status register ch.0
I2C data register ch.0
R/W
R/W
R
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
R/W
R/W
R/W
I2C address register ch.0
I2C clock control register ch.0
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
WCSR
⎯
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register (upper byte)
8/10-bit A/D converter data register (lower byte)
Watch counter status register
(Disabled)
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00000000B
00000000B
00000000B
00000000B
⎯
FSR*
⎯
Flash memory status register
(Disabled)
R/W
⎯
000X0000B
⎯
⎯
(Disabled)
⎯
⎯
⎯
(Disabled)
⎯
⎯
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
R/W
R/W
00000000B
00000000B
Register bank pointer (RP) ,
Mirror of direct bank pointer (DP)
0078H
⎯
⎯
⎯
0079H
007AH
007BH
007CH
ILR0
ILR1
ILR2
ILR3
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
(Continued)
24
DS07-12618-2E
MB95160 Series
Register
abbreviation
Address
Register name
R/W
Initial value
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR4
Interrupt level setting register 4
Interrupt level setting register 5
R/W
R/W
⎯
11111111B
11111111B
⎯
ILR5
⎯
(Disabled)
WRARH0
WRARL0
WRDR0
WRARH1
WRARL1
WRDR1
WRARH2
WRARL2
WRDR2
Wild register address setting register (upper byte) ch.0
Wild register address setting register (lower byte) ch.0
Wild register data setting register ch.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
Wild register address setting register (upper byte) ch.1
Wild register address setting register (lower byte) ch.1
Wild register data setting register ch.1
Wild register address setting register (upper byte) ch.2
Wild register address setting register (lower byte) ch.2
Wild register data setting register ch.2
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
0F93H
0F94H
0F95H
T01CR0
T00CR0
T01DR
T00DR
8/16-bit compound timer 01 control status register 0 ch.0
8/16-bit compound timer 00 control status register 0 ch.0
8/16-bit compound timer 01 data register ch.0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 00 data register ch.0
8/16-bit compound timer 00/01 timer mode control
register ch.0
0F96H
TMCR0
R/W
00000000B
0F97H
0F98H
0F99H
0F9AH
T11CR0
T10CR0
T11DR
T10DR
8/16-bit compound timer 11 control status register 0 ch.1
8/16-bit compound timer 10 control status register 0 ch.1
8/16-bit compound timer 11 data register ch.1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
00000000B
8/16-bit compound timer 10 data register ch.1
8/16-bit compound timer 10/11 timer mode control
register ch.1
0F9BH
TMCR1
R/W
00000000B
0F9CH
0F9DH
0F9EH
0F9FH
0FA0H
0FA1H
0FA2H
0FA3H
0FA4H
PPS01
PPS00
PDS01
PDS00
PPS11
PPS10
PDS11
PDS10
PPGS
8/16-bit PPG1 cycle setting buffer register ch.0
8/16-bit PPG0 cycle setting buffer register ch.0
8/16-bit PPG1 duty setting buffer register ch.0
8/16-bit PPG0 duty setting buffer register ch.0
8/16-bit PPG1 cycle setting buffer register ch.1
8/16-bit PPG0 cycle setting buffer register ch.1
8/16-bit PPG1 duty setting buffer register ch.1
8/16-bit PPG0 duty setting buffer register ch.1
8/16-bit PPG start register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
11111111B
00000000B
(Continued)
DS07-12618-2E
25
MB95160 Series
Register
Address
Register name
R/W Initialvalue
abbreviation
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
to
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
0FABH
0FACH
0FADH
0FAEH
0FAFH
PDCRH0
PDCRL0
PCSRH0
PCSRL0
PDUTH0
PDUTL0
16-bit PPG down counter register (upper byte) ch.0
16-bit PPG down counter register (lower byte) ch.0
16-bit PPG cycle setting buffer register (upper byte) ch.0
16-bit PPG cycle setting buffer register (lower byte) ch.0
16-bit PPG duty setting buffer register (upper byte) ch.0
16-bit PPG duty setting buffer register (lower byte) ch.0
R
00000000B
00000000B
11111111B
11111111B
11111111B
11111111B
R
R/W
R/W
R/W
R/W
0FB0H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
0FBDH
BGR1
BGR0
LIN-UART baud rate generator register 1
LIN-UART baud rate generator register 0
R/W
R/W
00000000B
00000000B
UART/SIO dedicated baud rate generator prescaler selecting
register ch.0
0FBEH
PSSR0
BRSR0
R/W
00000000B
00000000B
0FBFH
UART/SIO dedicated baud rate generator setting register ch.0 R/W
0FC0H
to
0FC2H
⎯
(Disabled)
⎯
⎯
0FC3H
0FC4H
0FC5H
0FC6H
0FC7H
0FC8H
0FC9H
0FCAH
0FCBH
0FCCH
AIDRL
LCDCC
LCDCE1
LCDCE2
LCDCE3
LCDCE4
LCDCE5
⎯
A/D input disable register (lower byte)
LCDC control register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
00000000B
00010000B
00110000B
00000000B
00000000B
00000000B
00000000B
⎯
LCDC enable register 1
LCDC enable register 2
LCDC enable register 3
LCDC enable register 4
LCDC enable register 5
(Disabled)
LCDCB1
LCDCB2
LCDC blinking setting register 1
LCDC blinking setting register 2
R/W
R/W
00000000B
00000000B
0FCDH
to
LCDRAM
LCDC display RAM
R/W
00000000B
0FDCH
0FDDH
to
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
(Continued)
26
DS07-12618-2E
MB95160 Series
(Continued)
Register
abbreviation
Address
Register name
R/W
Initial value
0FE4H
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
0FEFH
ILSR
Input level selecting register
Interrupt pin control register
R/W
R/W
00000000B
01000000B
WICR
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
• R/W access symbols
R/W : Readable/Writable
R
: Read only
: Write only
W
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
* : Only for Flash product
DS07-12618-2E
27
MB95160 Series
■ INTERRUPT SOURCE TABLE
Vector table address
Same level
priority order
(atsimultaneous
occurrence)
Interrupt
request
number
Bit name of
interrupt level
setting register
Interrupt source
Upper
FFFAH
FFF8H
FFF6H
FFF4H
Lower
FFFBH
FFF9H
FFF7H
FFF5H
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
UART/SIO ch.0
High
IRQ0
IRQ1
IRQ2
IRQ3
L00 [1 : 0]
L01 [1 : 0]
L02 [1 : 0]
L03 [1 : 0]
IRQ4
IRQ5
FFF2H
FFF0H
FFEEH
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFD0H
FFCEH
FFCCH
FFF3H
FFF1H
FFEFH
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
FFD1H
FFCFH
FFCDH
L04 [1 : 0]
L05 [1 : 0]
L06 [1 : 0]
L07 [1 : 0]
L08 [1 : 0]
L09 [1 : 0]
L10 [1 : 0]
L11 [1 : 0]
L12 [1 : 0]
L13 [1 : 0]
L14 [1 : 0]
L15 [1 : 0]
L16 [1 : 0]
L17 [1 : 0]
L18 [1 : 0]
L19 [1 : 0]
L20 [1 : 0]
L21 [1 : 0]
L22 [1 : 0]
L23 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
8/16-bit compound timer ch.0 (Upper)
LIN-UART (reception)
LIN-UART (transmission)
8/16-bit PPG ch.1 (Lower)
8/16-bit PPG ch.1 (Upper)
(Unused)
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23
8/16-bit PPG ch.0 (Upper)
8/16-bit PPG ch.0 (Lower)
8/16-bit compound timer ch.1 (Upper)
16-bit PPG ch.0
I2C ch.0
(Unused)
8/10-bit A/D converter
Timebase timer
Watch prescaler/Watch counter
(Unused)
8/16-bit compound timer ch.1 (Lower)
Flash memory
Low
28
DS07-12618-2E
MB95160 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC,
AVCC
Vss − 0.3
Vss − 0.3
VSS − 0.3
Vss + 4.0
Vss + 4.0
VSS + 4.0
*2
*2
*3
Power supply voltage*1
V
V
AVR
Powersupplyvoltagefor
LCD
V0 to V3
Vss − 0.3
Vss − 0.3
Vss − 0.3
− 2.0
Vss + 6.0
Vss + 4.0
Vss + 4.0
+ 2.0
V
V
V
P23, P24*4
Input voltage*1
VI
Other than P23, P24*4
Output voltage*1
VO
*4
Maximum clamp current
ICLAMP
mA Applicable to pins*5
Total maximum clamp
current
Σ|ICLAMP|
⎯
⎯
20
15
mA Applicable to pins*5
“L” level maximum
output current
IOL
mA Applicable to pins*5
Applicable to pins*5
“L” level average
current
Average output current =
IOLAV
⎯
4
mA
operating current × operating ratio
(1 pin)
“L” level total maximum
output current
ΣIOL
ΣIOLAV
IOH
⎯
⎯
⎯
100
50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“L” level total average
output current
“H” level maximum
output current
− 15
mA Applicable to pins*5
Applicable to pins*5
“H” level average
current
Average output current =
mA
IOHAV
⎯
− 4
operating current × operating ratio
(1 pin)
“H” level total maximum
output current
ΣIOH
⎯
⎯
− 100
− 50
mA
Total average output current =
mA operating current × operating ratio
(Total of pins)
“H” level total average
output current
ΣIOHAV
Power consumption
Operating temperature
Storage temperature
Pd
TA
⎯
320
+ 85
+ 150
mW
°C
− 40
− 55
Tstg
°C
*1 : The parameter is based on VSS = 0.0 V.
*2 : Apply equal potential to AVCC and VCC. AVR should not exceed AVCC + 0.3 V.
(Continued)
DS07-12618-2E
29
MB95160 Series
(Continued)
*3 : V0 to V3 should not exceed VCC + 0.3 V.
*4 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*5 : Applicable to pins :
P00 to P07, P10 to P14, P20 to P22,P60 to P67, P90 to P95, PA0 to PA3, PB0 to PB7, PC0 to PC7
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+ B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
Vcc
Limiting
P-ch
resistance
+ B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
DS07-12618-2E
MB95160 Series
2. Recommended Operating Conditions
(Vss = 0.0 V)
Value
Typ
Parameter
Symbol Conditions
Unit
Remarks
Min
Max
At normal operating,
TA = − 10 °C to + 85 °C
1.8*
⎯
⎯
⎯
⎯
3.3
At normal operating,
TA = − 40 °C to + 85 °C
2.0*
2.6
1.5
3.3
3.6
3.3
Power supply
voltage
VCC,
AVCC
V
MB95FV100D-101,
TA = + 5 °C to + 35 °C
Retain status of stop mode
operation
⎯
The optimal value depends
on liquid crystal display
elements used.
Power supply
voltage for LCD
V0 to V3
VSS
⎯
VCC
V
A/D converter
reference input
voltage
AVR
TA
1.8
⎯
⎯
AVCC
V
Operating
temperature
− 40
+ 85
°C
* : The values vary with the operating frequency, machine clock or analog guarantee range.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
DS07-12618-2E
31
MB95160 Series
3. DC Characteristics
Sym-
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Pin name
Conditions
Unit
Remarks
bol
Min
Typ
Max
When selecting
CMOS input level
VIH1 P10, P67
VIH2 P23, P24
⎯
⎯
0.7 VCC
0.7 VCC
⎯
VCC + 0.3
VSS + 6.0
V
V
⎯
P00 to P07,
P10 to P14,
P20 to P22,
P60 to P67,
P90 to P95,
VIHS1
⎯
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
PA0 to PA3,
PB0 to PB7,
PC0 to PC7
“H” level input
voltage
VIHS2 P23, P24
⎯
⎯
0.8 VCC
0.7 VCC
⎯
⎯
VSS + 5.5
VCC + 0.3
V
V
CMOS input
(Flash Memory
product)
VIHM RST, MOD
Hysteresis input
(Mask ROM
product)
0.8 VCC
⎯
⎯
VCC + 0.3
V
V
P10,P23,
VIL
When selecting
CMOS input level
⎯
⎯
VSS − 0.3
0.3 VCC
P24,P67
P00 to P07,
P10 to P14,
P20 to P24,
P60 to P67,
P90 to P95,
VILS
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
PA0 to PA3,
PB0 to PB7,
PC0 to PC7
“L” level input
voltage
Hysteresis input
(Mask ROM
product)
VSS − 0.3
VSS − 0.3
⎯
⎯
0.2 VCC
0.3 VCC
V
V
VILM RST, MOD
⎯
CMOS input
(Flash Memory
product)
Output pins
VOH other than
P23, P24
“H” level
output voltage
IOH = 4.0 mA
IOL = 4.0 mA
2.4
⎯
⎯
⎯
V
V
“L” level output
voltage
Output pins
VOL
⎯
0.4
other than RST
Input leakage
current (Hi-Z
output leakage
current)
Ports other than
P23, P24
When the pull-up
prohibition setting
ILI
0.0 V < VI < VCC
− 5
⎯
+ 5
μA
(Continued)
32
DS07-12618-2E
MB95160 Series
(Vcc = 3.3 V,Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min Typ Max
Open-drain
output leakage ILIOD P23, P24
current
0.0 V < VI <
VSS + 5.5 V
⎯
⎯
5
μA
kΩ
P10 to P14,
Pull-up resistor RPULL
P20 to P22
When the pull-up
permission setting
VI = 0.0 V
VI = Vcc
25
25
50
50
100
100
Pull-down re-
RMOD MOD
sistor
kΩ Mask ROM product
Other than AVCC,
CIN AVSS, AVR,
Input
capacitance
f = 1 MHz
⎯
⎯
5
15
pF
VCC, VSS
MB95F166D
At other than Flash
memory writing
and erasing
11.0 14.0 mA
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
MB95F166D
⎯
⎯
30.0 35.0 mA At Flash memory
writing and erasing
7.3 10.0 mA MB95166D
ICC
MB95F166D
At other than Flash
17.6 22.4 mA
⎯
memory writing
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
and erasing
MB95F166D
38.1 44.9 mA At Flash memory
writing and erasing
⎯
⎯
VCC
Power supply
current*
11.7 16.0 mA MB95166D
(External clock
operation)
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯
⎯
⎯
⎯
4.5
7.2
25
7
6.0
9.6
35
mA
mA
μA
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2)
ICCL
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2)
ICCLS
15
μA
(Continued)
DS07-12618-2E
33
MB95160 Series
(Continued)
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min Typ Max
Flashmemory
product
FCL = 32 kHz
⎯
⎯
⎯
⎯
⎯
⎯
2
1
10
5
μA
μA
Watch mode
Main stop mode
TA = + 25 °C
ICCT
MASK ROM
product
Flashmemory
product
FCH = 4 MHz
10
6.7
14
10
mA
mA
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
MASK ROM
product
ICCMPLL
Flashmemory
product
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
16.0 22.4 mA
10.8 16.0 mA
VCC
MASK ROM
product
(External clock
operation)
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
Power supply
current*
ICCSPLL
⎯
190
250 μA
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
ICTS
ICCH
IA
⎯
⎯
⎯
0.4
1
0.5 mA
Sub stop mode
TA = + 25 °C
5
μA
FCH = 16 MHz
At operating of A/D
conversion
1.3
2.2 mA
AVCC
FCH = 16 MHz
At stopping of A/D
conversion
IAH
⎯
1
5
μA
TA = + 25 °C
LCD internal
division resistance
RLCD
⎯
Between V3 and VSS
⎯
⎯
⎯
300
⎯
⎯
5
kΩ
kΩ
kΩ
COM0 to COM3
output impedance
RVCOM COM0 to COM3
RVSEG SEG00 to SEG31
V1 to V3 = 5.0 V
SEG00 to SEG31
output impedance
⎯
7
V0 to V3,
LCD leak current
ILCDL COM0 to COM3
SEG00 to SEG31
⎯
− 1
⎯
+ 1 μA
* : • The power-supply current is determined by the external clock.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
34
DS07-12618-2E
MB95160 Series
4. AC Characteristics
(1) Clock Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
Parameter
Pin name Conditions
Unit
Remarks
bol
Min
Typ
Max
When using main
oscillation circuit
1.00
⎯
16.25 MHz
1.00
3.00
3.00
3.00
3.00
⎯
⎯
⎯
⎯
⎯
32.50 MHz When using external clock
10.00 MHz Main PLL multiplied by 1
8.13 MHz Main PLL multiplied by 2
6.50 MHz Main PLL multiplied by 2.5
4.06 MHz Main PLL multiplied by 4
When using sub
FCH
X0, X1
Clock frequency
⎯
⎯
32.768
32.768
⎯
⎯
⎯
kHz
oscillation circuit
FCL
X0A, X1A
kHz When using sub PLL
⎯
When using oscillation
circuit
61.5
30.8
⎯
1000
1000
⎯
ns
tHCYL
X0, X1
Clock cycle time
⎯
ns When using external clock
When using sub clock,
μs
tLCYL X0A, X1A
30.5
When using external clock
tWH1
tWL1
X0
X0A
61.5
⎯
⎯
15.2
⎯
⎯
⎯
5
ns
When using external clock
Duty ratio is about 30% to
70%.
Input clock pulse
width
tWH2
tWL2
μs
Input clock rise time
and fall time
tCR
tCF
X0, X0A
⎯
ns When using external clock
DS07-12618-2E
35
MB95160 Series
• Input wave form at external clock use (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Main Clock Input Port External Connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
C2
FCH
C1
• Input wave form at external clock use (sub clock)
tLCYL
tWH2
tWL2
tCR
tCF
0.8 VCC 0.8 VCC
X0A
0.1 VCC
0.1 VCC
0.1 VCC
• Figure of Sub clock Input Port External Connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0A
X1A
X0A
X1A
Open
FCL
C2
FCL
C1
36
DS07-12618-2E
MB95160 Series
(2) Source Clock/Machine Clock
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Typ
Sym- Condi-
Parameter
Unit
Remarks
bol
tions
Min
Max
When using main clock
Min : FCH = 8.125 MHz,
PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
When using sub clock
61.5
⎯
2000
ns
Source clock
cycle time*1
(Clock before
setting division)
tSCLK
7.6
⎯
61.0
μs Min : FCL = 32 kHz, PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
FSP
0.50
⎯
⎯
16.25
MHz When using main clock
Source clock
frequency
FSPL
16.384
131.072 kHz When using sub clock
⎯
When using main clock
Machine clock
cycle time*2
(Minimum
instruction
execution time)
61.5
7.6
⎯
⎯
32000
976.5
ns Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
tMCLK
When using sub clock
μs Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
1.024
⎯
⎯
16.250 MHz When using main clock
131.072 kHz When using sub clock
Machine clock
frequency
FMPL
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS07-12618-2E
37
MB95160 Series
• Outline of clock generation block
F
CH
Divided by 2
(main oscillation)
Main PLL
× 1
× 2
× 2.5
Division
circuit
× 1
× 1/4
× 1/8
× 1/16
× 4
SCLK
( source clock )
MCLK
( machine clock )
F
CL
Divided by 2
(sub oscillation)
Clock mode select bit
( SYCC : SCS1, SCS0 )
Sub PLL
× 2
× 3
× 4
38
DS07-12618-2E
MB95160 Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95166D
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
3.6
2.7
2.3
1.8
1.8
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz 5 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Source clock frequency (FSP)
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
• MB95F166D
Sub PLL operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
Sub clock mode and watch mode
operation guarantee range
3.3
3.3
2.7
1.8
2.3
1.8
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz 5 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSP)
DS07-12618-2E
39
MB95160 Series
• Operating voltage - Operating frequency (When TA = − 10 °C to + 85 °C)
• MB95166D
Sub PLL operation guarantee range
Sub clock mode and watch mode
operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
3.6
3.6
2.7
2.3
1.8
1.8
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
PLL operation guarantee range
Source clock frequency (FSP)
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
• MB95F166D
Sub PLL operation guarantee range
Main clock mode and main PLL mode
operation guarantee range
Sub clock mode and watch mode
operation guarantee range
3.3
3.3
2.7
2.0
2.3
2.0
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSP)
40
DS07-12618-2E
MB95160 Series
• Operating voltage - Operating frequency (When TA = + 5 °C to + 35 °C)
• MB95FV100D-101
Main clock mode and main PLL mode
operation guarantee range
Sub PLL , Sub clock mode and
watch mode operation guarantee range
3.6
3.3
2.6
3.6
2.6
0.5 MHz
3 MHz
10 MHz
16.25 MHz
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
PLL operation guarantee range
Source clock frequency (FSP)
Main clock operation guarantee range
Source clock frequency (FSP)
DS07-12618-2E
41
MB95160 Series
• Main PLL operation frequency
[MHz]
16.25
16
15
× 4
12
10
× 2.5
× 1
× 2
7.5
6
5
3
[MHz]
10
0
3
4
5
6.4
6.5
8
4.062
8.125
Machine clock frequency (FMP)
42
DS07-12618-2E
MB95160 Series
(3) External Reset
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin
name
Condi-
tions
Parameter
Symbol
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns At normal operating
At stop mode, sub
RST “L” level
pulse width
Oscillationtimeofoscillator*2
clock mode,
sub sleep mode,
tRSTL
RST
⎯
⎯
μs
+ 100
and watch mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of
μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
2 tMCLK
Oscillation time
of oscillator
Oscillation stabilization wait time
Execute instruction
Internal reset
DS07-12618-2E
43
MB95160 Series
(4) Power-on Reset
(Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Power supply
rising time
tR
⎯
36
ms
ms
VCC
⎯
Power supply
cutoff time
Waiting time until
power-on
tOFF
1
⎯
t
R
tOFF
1.5 V
0.2 V
0.2 V
0.2 V
V
CC
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
Limiting the slope of rising within
20 mV/ms is recommended.
1.5 V
Hold condition in stop mode
VSS
44
DS07-12618-2E
MB95160 Series
(5) Peripheral Input Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Peripheral input
“H” pulse width
tILIH
tIHIL
2 tMCLK*
⎯
ns
ns
INT00 to INT07,
EC0, EC1, TRG0/ADTG
⎯
Peripheral input
“L” pulse width
2 tMCLK*
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
tIHIL
INT00 to INT07,
EC0, EC1,
0.8 VCC 0.8 VCC
TRG0/ADTG
0.2 VCC
0.2 VCC
DS07-12618-2E
45
MB95160 Series
(6) UART/SIO, Serial I/O Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
UCK ↓ → UO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
UCK0
UCK0, UO0
UCK0, UI0
UCK0, UI0
UCK0
4 tMCLK*
− 190
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation
output pin : CL = 80 pF
+ 1TTL.
+ 190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
4 tMCLK*
4 tMCLK*
⎯
UCK ↑ → valid UI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
UCK ↓ → UO time
⎯
⎯
External clock
operation
output pin : CL = 80 pF
+ 1TTL.
UCK0
⎯
UCK0, UO0
UCK0, UI0
UCK0, UI0
190
⎯
Valid UI → UCK ↑
2 tMCLK*
2 tMCLK*
UCK ↑ → valid UI hold time
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK0
0.8 V
0.8 V
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
UCK0
tSLSH
tSHSL
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
46
DS07-12618-2E
MB95160 Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(Vcc = 3.3 V, Vss = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
5 tMCLK*3
−95
Max
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
tSLOVI SCK, SOT
+ 95
tIVSHI
tSHIXI
tSLSH
tSHSL
SCK, SIN
SCK, SIN
SCK
tMCLK*3 + 190
⎯
SCK ↑ → valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
0
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
⎯
SCK
⎯
tSLOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSHE SCK, SIN operation output pin :
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SCK fall time
tSHIXE SCK, SIN
tMCLK*3 + 95
⎯
tF
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
DS07-12618-2E
47
MB95160 Series
• Internal shift clock mode
SCK
t
SCYC
2.4 V
0.8 V
0.8 V
t
SLOVI
2.4 V
0.8 V
SOT
SIN
t
IVSHI
tSHIXI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
SCK
t
SHSL
t
SLSH
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t
R
t
F
t
SLOVE
2.4 V
0.8 V
SOT
SIN
t
IVSHE
t
SHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
48
DS07-12618-2E
MB95160 Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 3.3 V, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
5 tMCLK*3
−95
Max
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
SCK
SCK, SOT
SCK, SIN
SCK, SIN
SCK
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
+ 95
tMCLK*3 + 190
⎯
SCK ↓ → valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
0
⎯
3 tMCLK*3 − tR
tMCLK*3 + 95
⎯
⎯
SCK
⎯
tSHOVE SCK, SOT
2 tMCLK*3 + 95
External clock
tIVSLE
tSLIXE
tF
SCK, SIN operation output pin :
190
⎯
⎯
10
10
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SCK fall time
SCK, SIN
tMCLK*3 + 95
⎯
SCK
SCK
SCK rise time
tR
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of
the serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
DS07-12618-2E
49
MB95160 Series
• Internal shift clock mode
SCK
t
SCYC
2.4 V
2.4 V
0.8 V
t
SHOVI
2.4 V
0.8 V
SOT
SIN
t
SLIXI
t
IVSLI
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
SCK
t
SHSL
tSLSH
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
t
F
t
R
t
SHOVE
2.4 V
0.8 V
SOT
SIN
t
IVSLE
t
SLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
50
DS07-12618-2E
MB95160 Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
5 tMCLK*3
−95
Max
⎯
Serial clock cycle time
tSCYC
tSHOVI
tIVSLI
SCK
ns
ns
ns
ns
ns
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
SCK, SOT
+ 95
⎯
Internal clock
SCK, SIN operation output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↓ → valid SIN hold time
SOT → SCK ↓ delay time
tSLIXI
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
tSOVLI
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of
the serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
t
SCYC
2.4 V
SCK
0.8 V
0.8 V
t
SHOVI
t
SOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tSLIXI
tIVSLI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
DS07-12618-2E
51
MB95160 Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 3.3 V, VSS = 0.0 V, TA = −40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Min
Max
⎯
Serial clock cycle time
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCK
5 tMCLK*3
ns
ns
ns
ns
ns
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
SCK, SOT
−95
+ 95
⎯
Internal clock
SCK, SIN operation output pin : tMCLK*3 + 190
CL = 80 pF + 1 TTL.
SCK ↑ → valid SIN hold time
SOT → SCK ↑ delay time
SCK, SIN
SCK, SOT
0
⎯
4 tMCLK*3
⎯
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
t
SCYC
2.4 V
2.4 V
SCK
0.8 V
t
SOVHI
t
SLOVI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
t
SHIXI
t
IVSHI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
52
DS07-12618-2E
MB95160 Series
(8) I2C Timing
(VCC = 3.3 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Conditions Standard-mode
Pin
name
Parameter
Symbol
Fast-mode
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
SCL0
0
100
0
400
kHz
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
SCL0
SDA0
tHD;STA
4.0
⎯
0.6
⎯
μs
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
SCL0
SCL0
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
μs
μs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
SCL0
SDA0
tSU;STA
tHD;DAT
4.7
0
⎯
3.45*2
⎯
0.6
0
⎯
0.9*3
⎯
μs
μs
μs
μs
μs
R = 1.7 kΩ,
C = 50 pF*1
SCL0
SDA0
Data hold time SCL ↓ → SDA ↓ ↑
SCL0
SDA0
Data setup time SDA ↓ ↑ → SCL ↑ tSU;DAT
0.25*4
4.0
0.1*4
0.6
1.3
Stop condition setup time SCL ↑ →
SDA ↑
SCL0
SDA0
tSU;STO
⎯
⎯
Bus free time between stop
tBUF
SCL0
SDA0
4.7
⎯
⎯
condition and start condition
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
*4 : Refer to “ • Note of SDA and SCL set-up time”.
• Note of SDA and SCL set-up time
0.7 VCC
SDA0
Input data set-up time
SCL0
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on
the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be
satisfied.
DS07-12618-2E
53
MB95160 Series
t
WAKEUP
SDA0
SCL0
t
HD;STA
t
HD;DAT
t
HIGH
t
BUF
t
LOW
t
SU;STO
t
HD;STA
tSU;DAT
t
SU;STA
54
DS07-12618-2E
MB95160 Series
(VCC = 3.3 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value*2
Sym- Pin
bol name
Condi-
tions
Parameter
Unit
Remarks
Min
Max
SCL clock
“L” width
(2 + nm / 2) tMCLK − 20
tLOW SCL0
tHIGH SCL0
⎯
ns Master mode
SCL clock
“H” width
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
ns Master mode
Master mode
Maximum value is
applied when m,
ns n = 1, 8.
Start condition
hold time
SCL0
tHD;STA
(−1 + nm / 2) tMCLK − 20
(−1 + nm) tMCLK + 20
SDA0
Otherwise, the
minimum value is
applied.
Stop condition
setup time
SCL0
tSU;STO
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode
(1 + nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20 ns Master mode
SDA0
Start condition
setup time
SCL0
tSU;STA
SDA0
Bus free time
between stop
condition and
start condition
SCL0
tBUF
(2 nm + 4) tMCLK − 20
3 tMCLK − 20
⎯
⎯
ns
SDA0
SCL0
SDA0
Data hold time tHD;DAT
ns Master mode
Master mode
R = 1.7 kΩ,
C = 50 pF*1
When assuming
that “L” of SCL is
not extended, the
minimum value is
Data setup
tSU;DAT
SCL0
SDA0
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns applied to first bit
time
of continuous
data.
Otherwise,
the maximum
value is applied.
Minimum value is
appliedtointerrupt
at 9th SCL↓.
Maximum value is
appliedtointerrupt
at 8th SCL↓.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL0
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20 ns
SCL clock “L”
width
4 tMCLK − 20
4 tMCLK − 20
tLOW SCL0
tHIGH SCL0
⎯
⎯
ns At reception
ns At reception
SCL clock “H”
width
Undetected when
ns 1 tMCLK is used at
reception
Start condition
detection
SCL0
tHD;STA
2 tMCLK − 20
⎯
SDA0
(Continued)
DS07-12618-2E
55
MB95160 Series
(Continued)
(VCC = 3.3 V 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value*2
Sym-
bol
Pin
name
Condi-
tions
Parameter
Unit
Remarks
Min
Max
Undetected when 1
ns tMCLK is used at
reception
Stop condition
detection
SCL0
SDA0
2 tMCLK − 20
tSU;STO
⎯
Undetected when 1
ns tMCLK is used at
reception
Restart condition
detection condition
SCL0
SDA0
2 tMCLK − 20
tSU;STA
⎯
SCL0
SDA0
Bus free time
tBUF
2 tMCLK − 20
2 tMCLK − 20
tLOW − 3 tMCLK − 20
0
⎯
⎯
⎯
⎯
⎯
ns At reception
SCL0
SDA0
At slave transmission
mode
Data hold time
Data setup time
Data hold time
Data setup time
tHD;DAT
tSU;DAT
tHD;DAT
tSU;DAT
ns
R = 1.7 kΩ,
C = 50 pF*1
SCL0
SDA0
At slave transmission
mode
ns
SCL0
SDA0
ns At reception
ns At reception
SCL0
SDA0
tMCLK − 20
Oscillation
stabilization
wait time +
2 tMCLK − 20
SDA ↓ → SCL ↑
(at wakeup function)
SCL0
SDA0
tWAKEUP
⎯
ns
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) .
• n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) .
• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
• Fast-mode :
: 0.9 MHz < tMCLK ≤ 10 MHz
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
(m, n) = (1, 22) , (5, 4)
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 4 MHz
: 3.3 MHz < tMCLK ≤ 8 MHz
: 3.3 MHz < tMCLK ≤ 10 MHz
56
DS07-12618-2E
MB95160 Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVCC = VCC = 1.8 V to 3.3 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym- Condi-
Parameter
Unit
Remarks
bol
tions
Min
⎯
Typ
⎯
Max
10
Resolution
Total error
bit
− 3.0
− 2.5
⎯
+ 3.0
+ 2.5
LSB
LSB
⎯
Linearity error
⎯
Differential
linear error
− 1.9
⎯
+ 1.9
LSB
AVSS − 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB
AVSS − 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB
AVR − 3.5 LSB AVR − 1.5 LSB AVR + 0.5 LSB
V
V
V
2.7 V ≤ AVCC ≤ 3.3 V
1.8 V ≤ AVCC < 2.7 V
2.7 V ≤ AVCC ≤ 3.3 V
Zero transition
voltage
VOT
VFST
⎯
Full-scale
transition
voltage
AVR − 2.5 LSB AVR − 0.5 LSB AVR + 1.5 LSB
V
1.8 V ≤ AVCC < 2.7 V
0.6
20
⎯
⎯
140
140
μs 2.7 V ≤ AVcc ≤ 3.3 V
μs 1.8 V ≤ AVcc < 2.7 V
Compare time
2.7 V ≤ AVcc ≤ 3.3 V,
μs At external
⎯
0.4
30
⎯
⎯
∞
∞
impedance < 1.8 kΩ
Sampling time
⎯
1.8 V ≤ AVcc < 2.7 V,
μs At external
impedance < 14.8 kΩ
Analog input
current
IAIN
VAIN
⎯
−0.3
AVSS
⎯
⎯
+0.3
AVR
AVCC
600
5
μA
Analog input
voltage
V
Reference
voltage
AVSS + 1.8
⎯
⎯
V
AVR pin
AVR pin,
During A/D operation
IR
400
⎯
μA
μA
Reference
voltage supply
current
AVR pin,
At stop mode
IRH
⎯
DS07-12618-2E
57
MB95160 Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
R
C
2.7 V ≤ VCC ≤ 3.6 V
1.8 V ≤ VCC < 2.7 V
1.7 kΩ (Max)
84 kΩ (Max)
14.5 pF (Max)
25.2 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
AVcc ≥ 2.7 V
AVcc ≥ 2.7 V
100
90
80
70
60
20
18
16
14
12
10
8
AVcc ≥ 1.8 V
50
40
30
20
10
0
6
4
2
0
0
5
10 15 20 25 30 35 40
0
1
2
3
4
Minimum sampling time [μs]
Minimum sampling time [μs]
• About errors
As |VCC − VSS| becomes smaller, values of relative errors grow larger.
58
DS07-12618-2E
MB95160 Series
(3) Definition of A/D Converter Terms
• Resolution
The analog quantity to be monitored by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FEH
3FDH
3FFH
3FEH
3FDH
Actual conversion
characteristic
1.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
004H
003H
002H
001H
VNT
VOT
Actual conversion
characteristic
1 LSB
0.5 LSB
Ideal characteristics
VSS
VSS
VCC
VCC
Analog input
Analog input
Total error of
digital output N
VCC − Vss
1024
VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
1 LSB =
(V)
[LSB]
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) H to NH
(Continued)
DS07-12618-2E
59
MB95160 Series
(Continued)
Full-scale transition error
Zero transition error
Ideal characteristics
004H
003H
002H
001H
Actual conversion
characteristic
3FFH
3FEH
3FDH
3FCH
Actual conversion
characteristic
Ideal
characteristics
VFST
(measurement
value)
Actual conversion
characteristic
Actual conversion
characteristic
VOT (measurement value)
VSS
VCC
VSS
VCC
Analog input
Analog input
Linearity error
Differential linear error
Actual conversion
characteristic
Ideal characteristics
3FFH
3FEH
3FDH
(N+1)H
NH
Actual conversion
characteristic
{1 LSB × N + VOT}
V (N+1)T
VFST
(measurement
value)
VNT
004H
003H
002H
001H
(N-1)H
(N-2)H
VNT
Actual conversion
characteristic
Actual conversion
characteristic
Ideal characteristics
VOT (measurement value)
VSS
VCC
VSS
VCC
Analog input
Analog input
Linearity error in
digital output N
VNT − {1 LSB × N + VOT}
V (N + 1) T − VNT
Differential linear error
in digital output N
=
=
− 1
1 LSB
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1) H to NH
VOT (Ideal value) = VSS + 0.5 LSB [V]
VFST (Ideal value) = VCC − 1.5 LSB [V]
60
DS07-12618-2E
MB95160 Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
⎯
Typ
1*1
32
Max
15*2
Chip erase time
s
Excludes 00H programming prior erasure.
Byte programming time
Erase/program cycle
⎯
3600*2
μs Excludes system-level overhead.
cycle
10000
⎯
⎯
Power supply voltage at erase/
program
2.7
⎯
⎯
3.3
V
Flash memory data retention
time
20*3
⎯
year Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 3.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 2.7 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
DS07-12618-2E
61
MB95160 Series
■ MASK OPTION
Part number
MB95F166D
MB95FV100D-101
Setting disabled
MB95166D
No.
Specifying when
ordering MASK
Specifying procedure
Setting disabled
Clock mode select
• Single-system clock mode
• Dual-system clock mode
Changing by the
switch on
Dual-system clock
mode
Dual-system clock
mode
1
2
3
MCU board
Low voltage detection reset*
• With low voltage detection reset
• Without low voltage detection
reset
No
No
No
No
No
Clock supervisor*
• With clock supervisor
• Without clock supervisor
No
Selection of oscillation stabiliza-
tion wait time
Selectable:
Fixed to oscillation sta- Fixed to oscillation sta- 1 : (22 − 2) / FCH
bilization wait time of bilization wait time of 2 : (212 − 2) / FCH
4
• Selectable the initial value of
main clock oscillation stabilization (214 − 2) /FCH
(214 − 2) /FCH
3 : (213 − 2) / FCH
4 : (214 − 2) / FCH
wait time
* : Low voltage detection reset and clock supervisor are options of 5-V products.
62
DS07-12618-2E
MB95160 Series
■ ORDERING INFORMATION
Part number
Package
64-pin plastic LQFP
(FPT-64P-M23)
MB95F166DPMC/MB95166DPMC
MB95F166DPMC1/MB95166DPMC1
64-pin plastic LQFP
(FPT-64P-M24)
MCU board
224-ball plastic PFBGA
MB2146-301A
(MB95FV100D-101PBT)
(
)
(BGA-224P-M08)
DS07-12618-2E
63
MB95160 Series
■ PACKAGE DIMENSIONS
64-pin plastic LQFP
Lead pitch
0.65 mm
12.0 × 12.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
P-LFQFP64-12×12-0.65
Code
(Reference)
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
0.145±0.055
(.0057±.0022)
48
33
49
32
0.10(.004)
Details of "A" part
1.50 +0.20
–
0.10
.004
(Mounting height)
.059 +.008
–
0.25(.010)
INDEX
0~8˚
64
17
0.50±0.20
0.10±0.10
(.020±.008)
(.004±.004)
(Stand off)
"A"
1
16
0.60±0.15
(.024±.006)
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
64
DS07-12618-2E
MB95160 Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Gullwing
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.32 g
Code
(Reference)
(FPT-64P-M24)
P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*
10.00±0.10(.394±.004)SQ
0.145±0.055
(.006±.002)
48
33
49
32
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
64
17
"A"
0.25(.010)
0.50±0.20
(.020±.008)
1
16
LEAD No.
0.60±0.15
(.024±.006)
0.50(.020)
0.20±0.05
(.008±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2
2005 FUJITSU LIMITED F64036S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-12618-2E
65
MB95160 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
Added the part number;
(MB95166D)
⎯
⎯
■ FEATURE
Changed as follows.
2
(• Flash memory security function →
• Flash memory security function (Flash memory device only) )
3, 4
3
■ PRODUCT LINEUP
Added the row of MB95166D.
Changed the Reset output.
(Yes → No)
■ OSCILLATION STABILIZATION
Changed the “■ OSCILLATION STABILIZATION WAIT TIME”
WAIT TIME
5
6
■ PACKAGES AND CORRESPOND- Added the row of MB95166D.
ING PRODUCTS
■ DIFFERENCES AMONG PROD-
UCTS AND NOTES ON SELECTING
PRODUCTS
• Changed the Notes on Using Evaluation Products
• Changed the Difference of Memory Spaces
• Changed the Operating voltage
• Added the Difference MOD pins
11
13
14
17
23
■ I/O CIRCUIT TYPE
Changed the Type B
Changed the Type S ( • LCD power supply was deleted)
Added the item of “• Serial Communication”.
Added the MB95166D in “• Memory Map”.
Changed the Address 0073H, 0074H.
■ HANDLING DEVICES
■ CPU CORE
■ I/O MAP
■ ELECTRICAL CHARACTERISTICS Changed the Remarks of “Power supply voltage for LCD”
28
1. Absolute Maximum Ratings
(Products with LCD internal division resistance*3 → *3)
Changed the row of Symbol VIHM and VILM.
Added the row of Pull-down resistor (RMOD).
Changed the Power supply current.
31
32
3. DC Characteristics
32, 33
4. AC Characteristics
(2) Source Clock/Machine Clock
• Changed the Operating voltage - Operating frequency
(When TA = −10 °C to +85 °C)
38, 39
(• Added the graph of MB95166D )
61
62
■ MASK OPTION
Added the row of MB95166D.
■ ORDERING INFORMATION
Changed the part numbers.
(MB95F166DPMC → MB95F166DPMC/MB95166DPMC)
(MB95F166DPMC1 → MB95F166DPMC1/MB95166DPMC1)
The vertical lines marked in the left side of the page show the changes.
66
DS07-12618-2E
MB95160 Series
MEMO
DS07-12618-2E
67
MB95160 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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