MB95F562H [FUJITSU]
8-bit Microcontrollers;
| 型号： | MB95F562H |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Microcontrollers 微控制器 |
| 文件： | 总84页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS702-00003-1v0-E
8-bit Microcontrollers
CMOS
New-8FX MB95560H/570H/580H Series
MB95F562H/F562K/F563H/F563K/F564H/F564K
MB95F572H/F572K/F573H/F573K/F574H/F574K
MB95F582H/F582K/F583H/F583K/F584H/F584K
■ DESCRIPTION
MB95560H/570H/580H is a series of general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers of these series contain a variety of peripheral resources.
■ FEATURES
• New-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Clock
• Selectable main clock source
Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (4 MHz 2%)
The main CR clock frequency becomes 8 MHz when the PLL multiplier is 2.
The main CR clock frequency becomes 10 MHz when the PLL multiplier is 2.5.
The main CR clock frequency becomes 12 MHz when the PLL multiplier is 3.
The main CR clock frequency becomes 16 MHz when the PLL multiplier is 4.
• Selectable subclock source
Sub-oscillation clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
• Timer
• 8/16-bit composite timer × 2 channels
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
• LIN-UART (available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/
F583K/F584H/F584K)
• Full duplex double buffer
• Capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer
(Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.12
MB95560H/570H/580H Series
(Continued)
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected.
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F562H/F563H/F564H (maximum no. of I/O ports: 16)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 1
: 15
• MB95F562K/F563K/F564K (maximum no. of I/O ports: 17)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 2
: 15
• MB95F572H/F573H/F574H (maximum no. of I/O ports: 4)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 1
: 3
• MB95F572K/F573K/F574K (maximum no. of I/O ports: 5)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 2
: 3
• MB95F582H/F583H/F584H (maximum no. of I/O ports: 12)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 1
: 11
• MB95F582K/F583K/F584K (maximum no. of I/O ports: 13)
General-purpose I/O ports (N-ch open drain)
General-purpose I/O ports (CMOS I/O)
: 2
: 11
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Low-voltage detection reset circuit (available only on MB95F562K/F563K/F564K/F572K/F573K/F574K/
F582K/F583K/F584K)
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Dual operation Flash memory
• The erase/write operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
• Protects the content of the Flash memory
2
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PRODUCT LINE-UP
• MB95560H Series
Part number
MB95F562H
MB95F563H
MB95F564H
MB95F562K
MB95F563K
MB95F564K
Parameter
Type
Flash memory product
It supervises the main clock oscillation.
Clock
supervisor
counter
Flash memory
capacity
RAM capacity
8 Kbyte
12 Kbyte
496 bytes
No
20 Kbyte
496 bytes
8 Kbyte
12 Kbyte
496 bytes
Yes
20 Kbyte
240 bytes
240 bytes
496 bytes
Low-voltage
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
CPU functions
• Data bit length
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 16
• I/O ports (Max) : 17
General-
purpose I/O
• CMOS I/O
: 15
• CMOS I/O
: 15
• N-ch open drain: 1
• N-ch open drain: 2
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
-
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
LIN-UART
• Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is en-
abled.
• The LIN function can be used as a LIN master or a LIN slave.
6 channels
8-bit or 10-bit resolution can be selected.
2 channels
8/10-bit A/D
converter
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit
composite timer
6 channels
External
interrupt
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
• It supports serial writing (asynchronous mode).
On-chip debug
(Continued)
DS702-00003-1v0-E
3
MB95560H/570H/580H Series
(Continued)
Part number
MB95F562H
MB95F563H
MB95F564H
MB95F562K
MB95F563K
MB95F564K
Parameter
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
5 years
20 years
10 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
LCC-32P-M19
Package
FPT-20P-M09
FPT-20P-M10
4
DS702-00003-1v0-E
MB95560H/570H/580H Series
• MB95570H Series
Part number
MB95F572H
MB95F573H
MB95F574H
MB95F572K
MB95F573K
MB95F574K
Parameter
Type
Flash memory product
It supervises the main clock oscillation.
Clock
supervisor
counter
Flash memory
capacity
RAM capacity
8 Kbyte
12 Kbyte
496 bytes
No
20 Kbyte
496 bytes
8 Kbyte
12 Kbyte
496 bytes
Yes
20 Kbyte
240 bytes
240 bytes
496 bytes
Low-voltage
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
CPU functions
• Data bit length
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 4
• I/O ports (Max) : 5
General-
purpose I/O
• CMOS I/O
: 3
• CMOS I/O
: 3
• N-ch open drain: 1
• N-ch open drain: 2
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
-
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
LIN-UART
It can be used to replace 3 bytes of data.
No LIN-UART
2 channels
8-bit or 10-bit resolution can be selected.
1 channel
8/10-bit A/D
converter
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit
composite timer
2 channels
External
interrupt
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
• It can be used to wake up the device from standby modes.
• 1-wire serial control
• It supports serial writing (asynchronous mode).
On-chip debug
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
5 years
20 years
10 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
Package
FPT-8P-M08
DS702-00003-1v0-E
5
MB95560H/570H/580H Series
• MB95580H Series
Part number
MB95F582H
MB95F583H
MB95F584H
MB95F582K
MB95F583K
MB95F584K
Parameter
Type
Flash memory product
It supervises the main clock oscillation.
Clock
supervisor
counter
Flash memory
capacity
RAM capacity
8 Kbyte
12 Kbyte
496 bytes
No
20 Kbyte
496 bytes
8 Kbyte
12 Kbyte
496 bytes
Yes
20 Kbyte
240 bytes
240 bytes
496 bytes
Low-voltage
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
• Instruction bit length
• Instruction length
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8 and 16 bits
CPU functions
• Data bit length
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 12
• I/O ports (Max) : 13
General-
purpose I/O
• CMOS I/O
: 11
• CMOS I/O
: 11
• N-ch open drain: 1
• N-ch open drain: 2
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
-
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
LIN-UART
• Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is en-
abled.
• The LIN function can be used as a LIN master or a LIN slave.
5 channels
8-bit or 10-bit resolution can be selected.
1 channel
8/10-bit A/D
converter
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
• It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
8/16-bit
composite timer
6 channels
External
interrupt
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
• It can be used to wake up the device from standby modes.
• 1-wire serial control
• It supports serial writing (asynchronous mode).
On-chip debug
(Continued)
6
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Part number
MB95F582H
MB95F583H
MB95F584H
MB95F582K
MB95F583K
MB95F584K
Parameter
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
5 years
20 years
10 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
LCC-32P-M19
Package
FPT-16P-M08
FPT-16P-M23
DS702-00003-1v0-E
7
MB95560H/570H/580H Series
■ PACKAGES AND CORRESPONDING PRODUCTS
• MB95560H Series
Part number
MB95F562H
MB95F562K
MB95F563H
MB95F563K
MB95F564H
MB95F564K
Package
LCC-32P-M19
FPT-20P-M09
FPT-20P-M10
FPT-16P-M08
FPT-16P-M23
FPT-8P-M08
O
O
O
X
X
X
O
O
O
X
X
X
O
O
O
X
X
X
O
O
O
X
X
X
O
O
O
X
X
X
O
O
O
X
X
X
• MB95570H Series
Part number
MB95F572H
MB95F572K
MB95F573H
MB95F573K
MB95F574H
MB95F574K
Package
LCC-32P-M19
FPT-20P-M09
FPT-20P-M10
FPT-16P-M08
FPT-16P-M23
FPT-8P-M08
X
X
X
X
X
O
X
X
X
X
X
O
X
X
X
X
X
O
X
X
X
X
X
O
X
X
X
X
X
O
X
X
X
X
X
O
• MB95580H Series
Part number
MB95F582H
MB95F582K
MB95F583H
MB95F583K
MB95F584H
MB95F584K
Package
LCC-32P-M19
FPT-20P-M09
FPT-20P-M10
FPT-16P-M08
FPT-16P-M23
FPT-8P-M08
O
X
X
O
O
X
O
X
X
O
O
X
O
X
X
O
O
X
O
X
X
O
O
X
O
X
X
O
O
X
O
X
X
O
O
X
O: Available
X: Unavailable
8
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For
details of the connection method, refer to “CHAPTER 21 EXAMPLE OF SERIAL PROGRAMMING
CONNECTION” in the hardware manual of the MB95560H/570H/580H Series.
DS702-00003-1v0-E
9
MB95560H/570H/580H Series
■ PIN ASSIGNMENT
X1/PF1
X0/PF0
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
P07/INT07
(TOP VIEW)
P12/EC0/DBG
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
X1A/PG2
X0A/PG1
Vcc
LCC-32P-M19
(MB95560H Series)
C
RST/PF2
* The number of usable pins is 20. 17
X0/PF0
X1/PF1
Vss
1
2
20
19
18
17
16
15
14
13
12
11
P12/EC0/DBG
(TOP VIEW)
P07/INT07
3
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
X1A/PG2
X0A/PG1
Vcc
4
5
FPT-20P-M09
FPT-20P-M10
(MB95560H Series)
6
C
7
RST/PF2
TO10/P62
TO11/P63
8
9
P00/AN00
10
P64/EC1
(Continued)
10
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
X1/PF1
X0/PF0
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
P07/INT07
(TOP VIEW)
P12/EC0/DBG
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
X1A/PG2
X0A/PG1
Vcc
LCC-32P-M19
(MB95580H Series)
C
RST/PF2
* The number of usable pins is 16. 17
X0/PF0
X1/PF1
Vss
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P12/EC0/DBG
(TOP VIEW)
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P01/AN01
X1A/PG2
X0A/PG1
Vcc
FPT-16P-M08
FPT-16P-M23
(MB95580H Series)
RST/PF2
C
P02/INT02/AN02/SCK
(TOP VIEW)
Vss
Vcc
1
2
3
4
8
7
6
5
P12/EC0/DBG
P06/INT06/TO01
P05/AN05/TO00
P04/INT04/AN04/EC0
FPT-8P-M08
(MB95570H Series)
C
RST/PF2
DS702-00003-1v0-E
11
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 32 pins)
I/O
circuit
type*
Pin no.
Pin name
Function
PF1
X1
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
1
B
PF0
X0
2
3
4
B
⎯
C
Main clock input oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
VSS
PG2
X1A
PG1
X0A
VCC
C
5
C
6
7
⎯
⎯
Capacitor connection pin
General-purpose I/O port
PF2
8
9
A
E
E
Reset pin
RST
Dedicated reset pin in MB95F562H/F563H/F564H
General-purpose I/O port
High-current pin
P63
TO11
P62
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
High-current pin
10
TO10
NC
8/16-bit composite timer ch. 1 output pin
11
12
13
14
⎯
⎯
⎯
⎯
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
NC
NC
NC
General-purpose I/O port
High-current pin
P00
AN00
P64
15
16
17
D
E
D
A/D converter analog input pin
General-purpose I/O port
High-current pin
EC1
P01
8/16-bit composite timer ch. 1 clock input pin
General-purpose I/O port
High-current pin
AN01
P02
A/D converter analog input pin
General-purpose I/O port
High-current pin
INT02
AN02
SCK
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
18
D
(Continued)
12
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
I/O
circuit
type*
Pin no.
Pin name
Function
General-purpose I/O port
High-current pin
P03
INT03
AN03
SOT
P04
External interrupt input pin
19
20
D
D
A/D converter analog input pin
LIN-UART data output pin
General-purpose I/O port
INT04
AN04
SIN
External interrupt input pin
A/D converter analog input pin
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
High-current pin
P05
INT05
AN05
TO00
External interrupt input pin
21
22
D
E
A/D converter analog input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
P06
INT06
TO01
P12
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
23
24
EC0
F
E
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
DBG
General-purpose I/O port
High-current pin
P07
INT07
NC
NC
NC
NC
NC
NC
NC
NC
External interrupt input pin
25
26
27
28
29
30
31
32
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00003-1v0-E
13
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 20 pins)
I/O
circuit
type*
Pin no.
Pin name
Function
PF0
X0
General-purpose I/O port
1
B
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
PF1
X1
2
3
4
B
—
C
VSS
PG2
X1A
PG1
X0A
VCC
C
5
C
6
7
—
—
Capacitor connection pin
General-purpose I/O port
PF2
8
A
E
E
E
D
D
Reset pin
RST
Dedicated reset pin in MB95F562H/F563H/F564H
General-purpose I/O port
High-current pin
P62
TO10
P63
9
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
High-current pin
10
11
12
13
TO11
P64
8/16-bit composite timer ch. 1 output pin
General-purpose I/O port
High-current pin
EC1
P00
8/16-bit composite timer ch. 1 clock input pin
General-purpose I/O port
High-current pin
AN00
P01
A/D converter analog input pin
General-purpose I/O port
High-current pin
AN01
P02
A/D converter analog input pin
General-purpose I/O port
High-current pin
INT02
AN02
SCK
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
14
15
D
D
General-purpose I/O port
High-current pin
P03
INT03
AN03
SOT
External interrupt input pin
A/D converter analog input pin
LIN-UART data output pin
(Continued)
14
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
I/O
circuit
type*
Pin no.
Pin name
Function
P04
INT04
AN04
SIN
General-purpose I/O port
External interrupt input pin
16
D
A/D converter analog input pin
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
High-current pin
P05
INT05
AN05
TO00
External interrupt input pin
17
18
D
E
A/D converter analog input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
P06
INT06
TO01
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
P07
19
20
E
F
INT07
P12
External interrupt input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
EC0
DBG
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00003-1v0-E
15
MB95560H/570H/580H Series
s
■ PIN FUNCTIONS (MB95570H Series, 8 pins)
I/O
circuit
type*
Pin no.
Pin name
Function
1
2
3
VSS
VCC
C
—
—
—
Power supply pin (GND)
Power supply pin
Capacitor connection pin
General-purpose I/O port
Reset pin
PF2
4
A
RST
Dedicated reset pin in MB95F572H/F573H/F574H
P04
INT04
AN04
EC0
General-purpose I/O port
External interrupt input pin
5
D
A/D converter analog input pin
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
High-current pin
P05
6
D
AN05
TO00
A/D converter analog input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
P06
7
8
E
F
INT06
TO01
P12
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
EC0
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
DBG
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
16
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 32 pins)
I/O
circuit
type*
Pin no.
Pin name
Function
PF1
X1
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
1
B
PF0
X0
2
3
4
B
⎯
C
Main clock input oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
VSS
PG2
X1A
PG1
X0A
VCC
C
5
C
6
7
⎯
⎯
Capacitor connection pin
General-purpose I/O port
PF2
8
A
Reset pin
RST
Dedicated reset pin in MB95F582H/F583H/F584H
9
NC
NC
NC
NC
NC
NC
NC
NC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
10
11
12
13
14
15
16
General-purpose I/O port
High-current pin
P01
AN01
P02
17
D
A/D converter analog input pin
General-purpose I/O port
High-current pin
INT02
AN02
SCK
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
18
D
General-purpose I/O port
High-current pin
P03
INT03
AN03
SOT
External interrupt input pin
A/D converter analog input pin
LIN-UART data output pin
19
D
(Continued)
DS702-00003-1v0-E
17
MB95560H/570H/580H Series
(Continued)
I/O
circuit
type*
Pin no.
Pin name
Function
P04
INT04
AN04
SIN
General-purpose I/O port
External interrupt input pin
20
D
A/D converter analog input pin
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
High-current pin
P05
INT05
AN05
TO00
External interrupt input pin
21
22
D
E
A/D converter analog input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
P06
INT06
TO01
P12
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
23
24
EC0
F
E
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
DBG
General-purpose I/O port
High-current pin
P07
INT07
NC
NC
NC
NC
NC
NC
NC
NC
External interrupt input pin
25
26
27
28
29
30
31
32
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
It is an internally connected pin. Always leave it unconnected.
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
18
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 16 pins)
I/O
circuit
type*
Pin no.
Pin name
Function
PF0
X0
General-purpose I/O port
1
B
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
PF1
X1
2
3
4
B
—
C
VSS
PG2
X1A
PG1
X0A
VCC
5
6
C
—
PF2
General-purpose I/O port
7
8
A
Reset pin
RST
C
Dedicated reset pin in MB95F582H/F583H/F584H
—
Capacitor connection pin
General-purpose I/O port
High-current pin
P02
INT02
AN02
SCK
External interrupt input pin
A/D converter analog input pin
LIN-UART clock I/O pin
9
D
D
D
General-purpose I/O port
High-current pin
P01
AN01
P03
10
11
A/D converter analog input pin
General-purpose I/O port
High-current pin
INT03
AN03
SOT
P04
External interrupt input pin
A/D converter analog input pin
LIN-UART data output pin
General-purpose I/O port
INT04
AN04
SIN
External interrupt input pin
12
D
A/D converter analog input pin
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
(Continued)
DS702-00003-1v0-E
19
MB95560H/570H/580H Series
(Continued)
I/O
circuit
type*
Pin no.
Pin name
Function
General-purpose I/O port
High-current pin
P05
INT05
AN05
TO00
External interrupt input pin
13
D
E
A/D converter analog input pin
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
High-current pin
P06
14
INT06
TO01
External interrupt input pin
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
High-current pin
P07
15
16
E
F
INT07
P12
External interrupt input pin
General-purpose I/O port
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
EC0
DBG
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
20
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• N-ch open drain output
• Hysteresis input
• Reset output
Reset input / Hysteresis input
Reset output / Digital output
N-ch
B
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
Port select
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
Clock input
X1
X0
Standby control / Port select
Port select
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
C
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx.10 MΩ
Port select
R
Pull-up control
P-ch
N-ch
P-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• Pull-up control available
Standby control
Hysteresis input
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
P-ch
Digital output
Digital output
N-ch
Standby control
Hysteresis input
(Continued)
DS702-00003-1v0-E
21
MB95560H/570H/580H Series
(Continued)
Type
Circuit
Remarks
• CMOS output
• Hysteresis input
• Pull-up control available
• Analog input
D
Pull-up control
R
P-ch
N-ch
Digital output
Digital output
P-ch
Analog input
A/D control
Standby control
Hysteresis input
E
• CMOS output
• Hysteresis input
• Pull-up control available
Pull-up control
R
P-ch
N-ch
Digital output
Digital output
P-ch
Standby control
Hysteresis input
F
• N-ch open drain output
• Hysteresis input
Standby control
Hysteresis input
Digital output
N-ch
22
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of "■ ELECTRICAL
CHARACTERISTICS" is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the
RST/PF2 pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the
general purpose I/O function can be selected by the RSTEN bit in the SYSC register.
DS702-00003-1v0-E
23
MB95560H/570H/580H Series
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set
to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and
the VSS pin when designing the layout of a printed circuit board.
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
24
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95560H Series)
New-8FX CPU
Dual operation Flash with
security function
PF2*1/RST*2
Reset with LVD
(8/12/20 Kbyte)
PF1/X1*2
PF0/X0*2
PG2/X1A*2
PG1/X0A*2
Oscillator
circuit
CR
oscillator
RAM (240/496 bytes)
Interrupt controller
Clock control
(P05*3/TO00)
8/16-bit composite timer ch. 0
8/10-bit A/D converter
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
(P12*1/DBG)
On-chip debug
Wild register
(P00*3/AN00 to P05*3/AN05)
P02*3/INT02 to P07*3/INT07
External interrupt
(P62*3/TO10)
(P63*3/TO11)
P64*3/EC1
(P02*3/SCK)
(P03*3/SOT)
(P04/SIN)
8/16-bit composite timer ch. 1
LIN-UART
C
Port
Port
Vcc
*1: PF2 and P12 are N-ch open drain pins.
*2: Software option
Vss
*3: P00 to P03, P05 to P07 and P62 to P64 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00003-1v0-E
25
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95570H Series)
New-8FX CPU
Dual operation Flash with
security function
PF2*1/RST*2
Reset with LVD
CR oscillator
(8/12/20 Kbyte)
RAM (240/496 bytes)
Interrupt controller
Clock control
On-chip debug
Wild register
(P05*3/TO00)
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
8/16-bit composite timer ch. 0
8/10-bit A/D converter
(P12*1/DBG)
P05*3/AN05, (P04/AN04)
P04/INT04, P06*3/INT06
C
External interrupt
Port
Port
Vcc
*1: PF2 and P12 are N-ch open drain pins.
*2: Software option
Vss
*3: P05 and P06 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
26
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95580H Series)
New-8FX CPU
Dual operation Flash with
security function
PF2*1/RST*2
Reset with LVD
(8/12/20 Kbyte)
PF1/X1*2
PF0/X0*2
PG2/X1A*2
PG1/X0A*2
Oscillator
circuit
CR
oscillator
RAM (240/496 bytes)
Interrupt controller
Clock control
(P05*3/TO00)
8/16-bit composite timer ch. 0
8/10-bit A/D converter
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
(P12*1/DBG)
On-chip debug
Wild register
(P01*3/AN01 to P05*3/AN05)
P02*3/INT02 to P07*3/INT07
External interrupt
(P02*3/SCK)
(P03*3/SOT)
(P04/SIN)
LIN-UART
C
Port
Port
Vcc
*1: PF2 and P12 are N-ch open drain pins.
*2: Software option
Vss
*3: P01 to P03 and P05 to P07 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00003-1v0-E
27
MB95560H/570H/580H Series
■ CPU CORE
• Memory Space
The memory space of the MB95560H/570H/580H Series is 64 Kbyte in size, and consists of an I/O area, a
data area, and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95560H/570H/580H Series are
shown below.
• Memory Maps
MB95F562H/F562K/F572H/
MB95F563H/F563K/F573H/
F573K/F583H/F583K
MB95F564H/F564K/F574H/
F572K/F582H/F582K
F574K/F584H/F584K
0000
H
0000
H
0000
H
I/O
I/O
I/O
0080
0090
0100
H
H
0080
0090
0100
H
H
0080
0090
0100
H
H
Access prohibited
RAM 240 bytes
Access prohibited
RAM 496 bytes
Access prohibited
RAM 496 bytes
H
H
H
H
Register
Register
Register
0180
0200
H
H
0200
H
H
Access prohibited
0280
0280
Access prohibited
Extension I/O
Access prohibited
Extension I/O
0F80
H
0F80
H
H
0F80
H
H
Extension I/O
1000
H
1000
1000
Access prohibited
Flash 4 Kbyte
Access prohibited
Access prohibited
B000
H
H
B000
C000
H
H
B000
H
Flash 4 Kbyte
C000
Access prohibited
Access prohibited
Flash 4 Kbyte
Flash 20 Kbyte
E000
H
H
F000
H
H
Flash 8 Kbyte
FFFF
FFFF
FFFF
H
28
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95560H Series)
Register
Address
Register name
R/W Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
PDR0
DDR0
PDR1
DDR1
—
Port 0 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
—
—
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
SYCC2
STBC2
Oscillation stabilization wait time setting register
PLL control register
R/W 11111111B
R/W 00000000B
R/W XXX11011B
R/W 00000000B
R/W XXXXXXXXB
R/W 00000000B
R/W 00000000B
R/W 00XX0000B
R/W XXXX0011B
R/W 00000000B
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Standby control register 2
000FH
to
—
(Disabled)
—
—
0015H
0016H
0017H
PDR6
DDR6
Port 6 data register
R/W 00000000B
R/W 00000000B
Port 6 direction register
0018H
to
—
(Disabled)
—
—
0027H
0028H
0029H
002AH
002BH
002CH
PDRF
DDRF
PDRG
DDRG
PUL0
Port F data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port F direction register
Port G data register
Port G direction register
Port 0 pull-up register
002DH
to
—
(Disabled)
—
—
0032H
0033H
0034H
0035H
0036H
0037H
0038H
0039H
PUL6
—
Port 6 pull-up register
R/W 00000000B
(Disabled)
—
—
PULG
Port G pull-up register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
T01CR1
T00CR1
T11CR1
T10CR1
8/16-bit composite timer 01 status control register 1
8/16-bit composite timer 00 status control register 1
8/16-bit composite timer 11 status control register 1
8/16-bit composite timer 10 status control register 1
003AH
to
—
(Disabled)
—
—
0048H
(Continued)
DS702-00003-1v0-E
29
MB95560H/570H/580H Series
Register
abbreviation
Address
Register name
R/W Initial value
0049H
004AH
004BH
EIC10
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W 00000000B
R/W 00000000B
R/W 00000000B
EIC20
EIC30
004CH,
004DH
—
(Disabled)
—
—
004EH
004FH
0050H
0051H
0052H
0053H
0054H
0055H
LVDR
—
LVDR reset voltage selection ID register
(Disabled)
R/W 00000000B
—
—
SCR
SMR
SSR
LIN-UART serial control register
LIN-UART serial mode register
LIN-UART serial status register
R/W 00000000B
R/W 00000000B
R/W 00001000B
R/W 00000000B
R/W 00000100B
R/W 000000XXB
RDR/TDR LIN-UART receive/transmit data register
ESCR
ECCR
LIN-UART extended status control register
LIN-UART extended communication control register
0056H
to
—
(Disabled)
—
—
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
—
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
(Disabled)
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
—
—
FSR2
FSR
Flash memory status register 2
R/W 00000000B
R/W 000X0000B
R/W 00000000B
Flash memory status register
SWRE0
FSR3
FSR4
WREN
WROR
Flash memory sector write control register 0
Flash memory status register 3
R
000XXXXXB
Flash memory status register 4
R/W 00000000B
R/W 00000000B
R/W 00000000B
Wild register address compare enable register
Wild register data test setting register
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
—
—
—
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
ILR0
ILR1
ILR2
ILR3
ILR4
ILR5
—
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
(Disabled)
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
R/W 11111111B
—
—
WRARH0 Wild register address setting register (upper) ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
(Continued)
WRARL0
WRDR0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
30
DS702-00003-1v0-E
MB95560H/570H/580H Series
Register
abbreviation
Address
Register name
R/W Initial value
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
WRARH1 Wild register address setting register (upper) ch. 1
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
WRARL1
WRDR1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
WRARH2 Wild register address setting register (upper) ch. 2
WRARL2
WRDR2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
0F89H
to
—
(Disabled)
—
—
0F91H
0F92H
0F93H
0F94H
0F95H
0F96H
0F97H
0F98H
0F99H
0F9AH
0F9BH
T01CR0
T00CR0
T01DR
T00DR
TMCR0
T11CR0
T10CR0
T11DR
T10DR
TMCR1
8/16-bit composite timer 01 status control register 0
8/16-bit composite timer 00 status control register 0
8/16-bit composite timer 01 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 00 data register
8/16-bit composite timer 00/01 timer mode control register
8/16-bit composite timer 11 status control register 0
8/16-bit composite timer 10 status control register 0
8/16-bit composite timer 11 data register
8/16-bit composite timer 10 data register
8/16-bit composite timer 10/11 timer mode control register
0F9CH
to
—
(Disabled)
—
—
0FBBH
0FBCH
0FBDH
BGR1
BGR0
LIN-UART baud rate generator register 1
LIN-UART baud rate generator register 0
R/W 00000000B
R/W 00000000B
0FBEH
to
0FC2H
—
AIDRL
—
(Disabled)
A/D input disable register (Lower)
(Disabled)
—
—
0FC3H
R/W 00000000B
0FC4H
to
—
—
0FE3H
0FE4H
0FE5H
0FE6H
0FE7H
0FE8H
0FE9H
0FEAH
CRTH
CRTL
—
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
(Disabled)
R/W 000XXXXXB
R/W 000XXXXXB
—
—
CRTDA
SYSC
CMCR
CMDR
Main CR clock temperature dependent adjustment register
System configuration register
R/W 00011111B
R/W 11000011B
R/W 00000000B
R/W 00000000B
(Continued)
Clock monitoring control register
Clock monitoring data register
DS702-00003-1v0-E
31
MB95560H/570H/580H Series
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
0FEBH
0FECH
WDTH
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
R/W XXXXXXXXB
R/W XXXXXXXXB
WDTL
0FEDH
to
—
(Disabled)
—
—
0FFFH
• R/W access symbols
R/W : Readable / Writable
: Read only
R
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
32
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95570H Series)
Register
Address
Register name
R/W Initial value
abbreviation
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
PDR0
DDR0
PDR1
DDR1
—
Port 0 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
—
—
WATR
PLLC
SYCC
STBC
RSRR
TBTC
WPCR
WDTC
SYCC2
STBC2
Oscillation stabilization wait time setting register
PLL control register
R/W 11111111B
R/W 00000000B
R/W XXX11011B
R/W 00000000B
R/W XXXXXXXXB
R/W 00000000B
R/W 00000000B
R/W 00XX0000B
R/W XXXX0011B
R/W 00000000B
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Standby control register 2
000FH
to
—
(Disabled)
—
—
0027H
0028H
0029H
PDRF
DDRF
Port F data register
R/W 00000000B
R/W 00000000B
Port F direction register
002AH,
002BH
—
(Disabled)
—
—
002CH
PUL0
Port 0 pull-up register
R/W 00000000B
002DH
to
—
(Disabled)
—
—
0032H
0033H
PUL6
—
Port 6 pull-up register
(Disabled)
R/W 00000000B
0034H,
0035H
—
—
0036H
0037H
T01CR1
T00CR1
8/16-bit composite timer 01 status control register 1
8/16-bit composite timer 00 status control register 1
R/W 00000000B
R/W 00000000B
0038H
to
—
(Disabled)
—
—
0049H
004AH
004BH
EIC20
EIC30
External interrupt circuit control register ch. 4
External interrupt circuit control register ch. 6
R/W 00000000B
R/W 00000000B
004CH,
004DH
—
(Disabled)
—
—
004EH
LVDR
LVDR reset voltage selection ID register
R/W 00000000B
004FH
to
—
(Disabled)
—
—
006BH
(Continued)
DS702-00003-1v0-E
33
MB95560H/570H/580H Series
Register
Address
Register name
R/W Initial value
abbreviation
ADC1
ADC2
ADDH
ADDL
—
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
(Disabled)
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
—
—
FSR2
Flash memory status register 2
R/W 00000000B
R/W 000X0000B
R/W 00000000B
FSR
Flash memory status register
SWRE0
FSR3
Flash memory sector write control register 0
Flash memory status register 3
R
000XXXXXB
FSR4
Flash memory status register 4
R/W 00000000B
R/W 00000000B
R/W 00000000B
WREN
WROR
Wild register address compare enable register
Wild register data test setting register
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
—
—
—
0079H
007AH
ILR0
ILR1
Interrupt level setting register 0
Interrupt level setting register 1
R/W 11111111B
R/W 11111111B
007BH,
007CH
—
(Disabled)
—
—
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR4
ILR5
—
Interrupt level setting register 4
Interrupt level setting register 5
(Disabled)
R/W 11111111B
R/W 11111111B
—
—
WRARH0 Wild register address setting register (upper) ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
WRARL0
WRDR0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
WRARH1 Wild register address setting register (upper) ch. 1
WRARL1
WRDR1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
WRARH2 Wild register address setting register (upper) ch. 2
WRARL2
WRDR2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
0F89H
to
—
(Disabled)
—
—
0F91H
0F92H
0F93H
0F94H
0F95H
0F96H
T01CR0
T00CR0
T01DR
T00DR
TMCR0
8/16-bit composite timer 01 status control register 0
8/16-bit composite timer 00 status control register 0
8/16-bit composite timer 01 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 00 data register
8/16-bit composite timer 00/01 timer mode control register
0F97H
to
—
(Disabled)
—
—
0FC2H
(Continued)
34
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Register
Address
Register name
A/D input disable register (lower)
R/W Initial value
abbreviation
0FC3H
AIDRL
—
R/W 00000000B
0FC4H
to
(Disabled)
—
—
0FE3H
0FE4H
0FE5H
0FE6H
0FE7H
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
CRTH
CRTL
—
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
(Disabled)
R/W 000XXXXXB
R/W 000XXXXXB
—
—
CRTDA
SYSC
CMCR
CMDR
WDTH
WDTL
Main CR clock temperature dependent adjustment register
System configuration register
R/W 00011111B
R/W 11000011B
R/W 00000000B
R/W 00000000B
R/W XXXXXXXXB
R/W XXXXXXXXB
Clock monitoring control register
Clock monitoring data register
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
0FEDH
to
—
(Disabled)
—
—
0FFFH
• R/W access symbols
R/W : Readable / Writable
: Read only
R
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS702-00003-1v0-E
35
MB95560H/570H/580H Series
■ I/O MAP (MB95580H Series)
Register
Address
Register name
R/W Initial value
abbreviation
PDR0
DDR0
PDR1
DDR1
—
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
Port 0 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port 0 direction register
Port 1 data register
Port 1 direction register
(Disabled)
—
—
WATR
PLLC
Oscillation stabilization wait time setting register
PLL control register
R/W 11111111B
R/W 00000000B
R/W XXX11011B
R/W 00000000B
R/W XXXXXXXXB
R/W 00000000B
R/W 00000000B
R/W 00XX0000B
R/W XXXX0011B
R/W 00000000B
SYCC
STBC
RSRR
TBTC
System clock control register
Standby control register
Reset source register
Time-base timer control register
Watch prescaler control register
Watchdog timer control register
System clock control register 2
Standby control register 2
WPCR
WDTC
SYCC2
STBC2
000FH
to
—
(Disabled)
—
—
0027H
0028H
0029H
002AH
002BH
002CH
PDRF
DDRF
PDRG
DDRG
PUL0
Port F data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
Port F direction register
Port G data register
Port G direction register
Port 0 pull-up register
002DH
to
—
(Disabled)
—
—
0032H
0033H
0034H
0035H
0036H
0037H
PUL6
—
Port 6 pull-up register
R/W 00000000B
(Disabled)
—
—
PULG
T01CR1
T00CR1
Port G pull-up register
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 01 status control register 1
8/16-bit composite timer 00 status control register 1
0038H
to
—
(Disabled)
—
—
0048H
0049H
004AH
004BH
EIC10
EIC20
EIC30
External interrupt circuit control register ch. 2/ch. 3
External interrupt circuit control register ch. 4/ch. 5
External interrupt circuit control register ch. 6/ch. 7
R/W 00000000B
R/W 00000000B
R/W 00000000B
004CH,
004DH
—
(Disabled)
—
—
004EH
004FH
LVDR
—
LVDR reset voltage selection ID register
(Disabled)
R/W 00000000B
—
—
(Continued)
36
DS702-00003-1v0-E
MB95560H/570H/580H Series
Register
Address
Register name
LIN-UART serial control register
R/W Initial value
abbreviation
0050H
0051H
0052H
0053H
0054H
0055H
SCR
SMR
SSR
R/W 00000000B
R/W 00000000B
R/W 00001000B
R/W 00000000B
R/W 00000100B
R/W 000000XXB
LIN-UART serial mode register
LIN-UART serial status register
RDR/TDR LIN-UART receive/transmit data register
ESCR
ECCR
LIN-UART extended status control register
LIN-UART extended communication control register
0056H
to
—
(Disabled)
—
—
006BH
006CH
006DH
006EH
006FH
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
ADC1
ADC2
ADDH
ADDL
—
8/10-bit A/D converter control register 1
8/10-bit A/D converter control register 2
8/10-bit A/D converter data register upper
8/10-bit A/D converter data register lower
(Disabled)
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
—
—
FSR2
FSR
Flash memory status register 2
R/W 00000000B
R/W 000X0000B
R/W 00000000B
Flash memory status register
SWRE0
FSR3
FSR4
WREN
WROR
Flash memory sector write control register 0
Flash memory status register 3
R
000XXXXXB
Flash memory status register 4
R/W 00000000B
R/W 00000000B
R/W 00000000B
Wild register address compare enable register
Wild register data test setting register
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
0078H
—
⎯
—
0079H
007AH
007BH
007CH
007DH
007EH
007FH
0F80H
0F81H
0F82H
0F83H
0F84H
0F85H
0F86H
0F87H
0F88H
ILR0
ILR1
ILR2
—
Interrupt level setting register 0
Interrupt level setting register 1
Interrupt level setting register 2
(Disabled)
R/W 11111111B
R/W 11111111B
R/W 11111111B
—
—
ILR4
ILR5
—
Interrupt level setting register 4
Interrupt level setting register 5
(Disabled)
R/W 11111111B
R/W 11111111B
—
—
WRARH0 Wild register address setting register (upper) ch. 0
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
(Continued)
WRARL0
WRDR0
Wild register address setting register (lower) ch. 0
Wild register data setting register ch. 0
WRARH1 Wild register address setting register (upper) ch. 1
WRARL1
WRDR1
Wild register address setting register (lower) ch. 1
Wild register data setting register ch. 1
WRARH2 Wild register address setting register (upper) ch. 2
WRARL2
WRDR2
Wild register address setting register (lower) ch. 2
Wild register data setting register ch. 2
DS702-00003-1v0-E
37
MB95560H/570H/580H Series
(Continued)
Register
abbreviation
Address
Register name
R/W Initial value
0F89H
to
—
(Disabled)
—
—
0F91H
0F92H
0F93H
0F94H
0F95H
0F96H
T01CR0
T00CR0
T01DR
T00DR
TMCR0
8/16-bit composite timer 01 status control register 0
8/16-bit composite timer 00 status control register 0
8/16-bit composite timer 01 data register
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
R/W 00000000B
8/16-bit composite timer 00 data register
8/16-bit composite timer 00/01 timer mode control register
0F97H
to
—
(Disabled)
—
—
0FBBH
0FBCH
0FBDH
BGR1
BGR0
LIN-UART baud rate generator register 1
LIN-UART baud rate generator register 0
R/W 00000000B
R/W 00000000B
0FBEH
to
0FC2H
—
AIDRL
—
(Disabled)
A/D input disable register (Lower)
(Disabled)
—
—
0FC3H
R/W 00000000B
0FC4H
to
—
—
0FE3H
0FE4H
0FE5H
0FE6H
0FE7H
0FE8H
0FE9H
0FEAH
0FEBH
0FECH
CRTH
CRTL
—
Main CR clock trimming register (upper)
Main CR clock trimming register (lower)
(Disabled)
R/W 000XXXXXB
R/W 000XXXXXB
—
—
CRTDA
SYSC
CMCR
CMDR
WDTH
WDTL
Main CR clock temperature dependent adjustment
System configuration register
R/W 00011111B
R/W 11000011B
R/W 00000000B
R/W 00000000B
R/W XXXXXXXXB
R/W XXXXXXXXB
Clock monitoring control register
Clock monitoring data register
Watchdog timer selection ID register (upper)
Watchdog timer selection ID register (lower)
0FEDH
to
—
(Disabled)
—
—
0FFFH
• R/W access symbols
R/W : Readable / Writable
: Read only
R
• Initial value symbols
0
1
X
: The initial value of this bit is “0”.
: The initial value of this bit is “1”.
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
38
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95560H Series)
Vector table address
Priority order of
Bit name of interruptsources
interrupt level of the same level
Interrupt
request
number
Interrupt source
Upper
Lower
setting register
(occurring
simultaneously)
External interrupt ch. 4
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
IRQ00
IRQ01
FFFAH
FFF8H
FFFBH
FFF9H
L00 [1:0]
L01 [1:0]
High
IRQ02
IRQ03
FFF6H
FFF4H
FFF7H
FFF5H
L02 [1:0]
L03 [1:0]
IRQ04
IRQ05
FFF2H
FFF0H
FFF3H
FFF1H
L04 [1:0]
L05 [1:0]
8/16-bit composite timer ch. 0
(lower)
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
IRQ08
IRQ09
IRQ10
IRQ11
IRQ12
IRQ13
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
L07 [1:0]
L08 [1:0]
L09 [1:0]
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
LIN-UART (transmission)
—
—
—
—
—
8/16-bit composite timer ch. 1
(upper)
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFD0H
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
FFD1H
L15 [1:0]
L16 [1:0]
L17 [1:0]
L18 [1:0]
L19 [1:0]
L20 [1:0]
L21 [1:0]
—
—
8/10-bit A/D converter
Time-base timer
Watch prescaler
—
8/16-bit composite timer ch. 1
(lower)
IRQ22
IRQ23
FFCEH
FFCCH
FFCFH
FFCDH
L22 [1:0]
L23 [1:0]
Flash memory
Low
DS702-00003-1v0-E
39
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95570H Series)
Vector table address
Interrupt
Priority order of
Bit name of interruptsources
interrupt level of the same level
Interrupt source
request
number
Upper
Lower
setting register
(occurring
simultaneously)
External interrupt ch. 4
IRQ00
IRQ01
FFFAH
FFF8H
FFFBH
FFF9H
L00 [1:0]
L01 [1:0]
High
—
—
IRQ02
IRQ03
FFF6H
FFF4H
FFF7H
FFF5H
L02 [1:0]
L03 [1:0]
External interrupt ch. 6
—
—
—
IRQ04
IRQ05
FFF2H
FFF0H
FFF3H
FFF1H
L04 [1:0]
L05 [1:0]
8/16-bit composite timer ch. 0
(lower)
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
—
IRQ07
IRQ08
IRQ09
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFD0H
FFCEH
FFCCH
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
FFD1H
FFCFH
FFCDH
L07 [1:0]
L08 [1:0]
L09 [1:0]
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
L14 [1:0]
L15 [1:0]
L16 [1:0]
L17 [1:0]
L18 [1:0]
L19 [1:0]
L20 [1:0]
L21 [1:0]
L22 [1:0]
L23 [1:0]
—
—
—
—
—
—
—
—
—
—
8/10-bit A/D converter
Time-base timer
Watch prescaler
—
—
Flash memory
Low
40
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95580H Series)
Vector table address
Priority order of
Bit name of interruptsources
interrupt level of the same level
Interrupt
request
number
Interrupt source
Upper
Lower
setting register
(occurring
simultaneously)
External interrupt ch. 4
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
IRQ00
IRQ01
FFFAH
FFF8H
FFFBH
FFF9H
L00 [1:0]
L01 [1:0]
High
IRQ02
IRQ03
FFF6H
FFF4H
FFF7H
FFF5H
L02 [1:0]
L03 [1:0]
IRQ04
IRQ05
FFF2H
FFF0H
FFF3H
FFF1H
L04 [1:0]
L05 [1:0]
8/16-bit composite timer ch. 0
(lower)
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
IRQ08
IRQ09
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23
FFECH
FFEAH
FFE8H
FFE6H
FFE4H
FFE2H
FFE0H
FFDEH
FFDCH
FFDAH
FFD8H
FFD6H
FFD4H
FFD2H
FFD0H
FFCEH
FFCCH
FFEDH
FFEBH
FFE9H
FFE7H
FFE5H
FFE3H
FFE1H
FFDFH
FFDDH
FFDBH
FFD9H
FFD7H
FFD5H
FFD3H
FFD1H
FFCFH
FFCDH
L07 [1:0]
L08 [1:0]
L09 [1:0]
L10 [1:0]
L11 [1:0]
L12 [1:0]
L13 [1:0]
L14 [1:0]
L15 [1:0]
L16 [1:0]
L17 [1:0]
L18 [1:0]
L19 [1:0]
L20 [1:0]
L21 [1:0]
L22 [1:0]
L23 [1:0]
LIN-UART (transmission)
—
—
—
—
—
—
—
—
—
8/10-bit A/D converter
Time-base timer
Watch prescaler
—
—
Flash memory
Low
DS702-00003-1v0-E
41
MB95560H/570H/580H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VSS + 6
VSS + 6
VSS + 6
+ 2
Power supply voltage*1
Input voltage*1
VCC
VI
VSS − 0.3
VSS − 0.3
VSS − 0.3
− 2
V
V
V
*2
*2
Output voltage*1
VO
Maximum clamp current
ICLAMP
mA Applicable to specific pins*3
Total maximum clamp
current
Σ|ICLAMP|
—
—
20
mA Applicable to specific pins*3
IOL1
15
15
Other than P05, P06, P62 and P63*4
“L” level maximum
output current
mA
IOL2
P05, P06, P62 and P63*4
Other than P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
IOLAV1
4
“L” level average current
—
mA
P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
IOLAV2
12
“L” level total maximum
output current
ΣIOL
—
—
48
50
mA
Total average output current=
mA operating current × operating ratio
(Total number of pins)
“L” level total average
output current
ΣIOLAV
IOH1
− 15
− 15
Other than P05, P06, P62 and P63*4
P05, P06, P62 and P63*4
“H” level maximum
output current
—
mA
IOH2
Other than P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
IOHAV1
− 4
− 8
“H” level average
current
—
mA
IOHAV2
“H” level total maximum
output current
ΣIOH
—
—
48
mA
Total average output current=
mA operating current × operating ratio
(Total number of pins)
“H” level total average
output current
ΣIOHAV
− 50
Power consumption
Operating temperature
Storage temperature
Pd
TA
—
320
+ 85
mW
− 40
− 55
°C
Tstg
+ 150
°C
(Continued)
42
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
*1: The parameter is based on VSS = 0.0 V.
*2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
*3: Applicable to the following pins: P00 to P07, P62 to P64, PF0, PF1, PG1, PG2 (P00, and P62 to P64 are
only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. P01, P02, P03, P07, PF0. PF1, PG1
and PG2 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/
F583K/F584H/F584K.)
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• Thevalueofthelimitingresistorshouldbesettoavalueatwhichthecurrenttobeinputtothemicrocontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the
current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin,
affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
*4: P62 and P63 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS702-00003-1v0-E
43
MB95560H/570H/580H Series
2. Recommended Operating Conditions
Value
(VSS = 0.0 V)
Parameter Symbol
Unit
Remarks
Min
2.4*1*2
2.3
Max
5.5*1
5.5
In normal operation
Other than on-chip debug
mode
Hold condition in stop mode
In normal operation
Power supply
VCC
V
voltage
2.9
5.5
On-chip debug mode
2.3
5.5
Hold condition in stop mode
Smoothing
CS
0.022
1
µF *3
Other than on-chip debug mode
capacitor
− 40
+ 5
+ 85
+ 35
Operating
TA
°C
temperature
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/EC0/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact
their representatives beforehand.
44
DS702-00003-1v0-E
MB95560H/570H/580H Series
3. DC Characteristics
Parameter Symbol
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Typ*1 Max*2
Pin name
Condition
Unit
Remarks
Min
VIH
P04
—
0.7 VCC
—
VCC + 0.3
V
Hysteresis input
P00*3 to P03*4,
P05 to P07*4,
P12,
"H" level
input voltage
VIHS
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
P62 to P64*3,
PF0*4, PF1*4,
PG1*4, PG2*4
VIHM
VIL
PF2
P04
—
—
0.8 VCC
—
—
VCC + 0.3
V
V
Hysteresis input
Hysteresis input
VSS − 0.3
0.3 VCC
P00*3 to P03*4,
P05 to P07*4,
P12,
“L” level
input voltage
VILS
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
Hysteresis input
P62 to P64*3,
PF0*4, PF1*4,
PG1*4, PG2*4
VILM
VD
PF2
—
—
VSS − 0.3
VSS − 0.3
—
—
0.2 VCC
V
V
Open-drain
output
application
voltage
P12, PF2
Vss + 5.5
P04, PF0*4,
PF1*4, PG1*4,
PG2*4
P00*3 to P03*4,
P05 to P07*4,
P62 to P64*3
VOH1
VOH2
VOL1
IOH = −4 mA
IOH = −8 mA
IOL = 4 mA
VCC − 0.5
VCC − 0.5
—
—
—
—
—
—
V
V
V
“H” level
output
voltage
P04, P12
PF0 to PF2*4,
PG1*4, PG2*4
0.4
“L” level
output
voltage
P00*3 to P03*4,
P05 to P07*4,
P12,
VOL2
IOL = 12 mA
—
—
—
0.4
V
P62 to P64*3
Input leak
current (Hi-Z
output leak
current)
When pull-up
ILI
All input pins
0.0 V < VI < VCC
− 5
+ 5
µA resistance is
disabled
P00*3 to P07*4,
When pull-up
kΩ resistance is
enabled
Pull-up
resistance
RPULL P62 to P64*3,
PG1*4, PG2*4*5
VI = 0 V
25
—
50
5
100
15
Input
capacitance
Other than VCC
and VSS
CIN
f = 1 MHz
pF
(Continued)
DS702-00003-1v0-E
45
MB95560H/570H/580H Series
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Typ*1 Max*2
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Except during
—
3.6
5.8
mA Flash memory
writing and erasing
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
During Flash
—
—
7.5
4.1
13.8 mA memory writing
and erasing
9.1
mA At A/D conversion
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
ICCS
—
1.3
3
mA
VCC
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = + 25°C
(External clock
operation)
ICCL
—
49
145
10
µA
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = + 25°C
*6
ICCLS
—
—
6
µA
µA
Powersupply
current*5
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25°C
*6
ICCT
5
9
FCRH = 4 MHz
ICCMCR
FMP = 4 MHz
Main CR clock mode
—
—
1.1
4.6
mA
µA
VCC
Sub-CR clock mode
(divided by 2)
ICCSCR
58.1 230
TA = + 25°C
FCH = 32 MHz
Time-base timer
mode
ICCTS
—
—
330
4
370
15
µA
VCC
TA = + 25°C
(External clock
operation)
Main stop mode
for a single
external clock
product
Substop mode
TA = + 25°C
ICCH
µA
(Continued)
46
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Typ*1 Max*2
Parameter Symbol
Pin name
Condition
Unit
Remarks
Min
Current
consumption for
low-voltage
ILVD
—
4
7
µA
detection circuit only
Current
Powersupply
ICRH
consumption for the
main CR oscillator
—
—
240
320
µA
µA
VCC
current*5
Current
consumption for the
sub-CR oscillator
oscillating at
100 kHz
ICRL
7
20
*1: VCC = 5.0 V, TA = + 25°C
*2: VCC = 5.5 V, TA = + 25°C
*3: P00, P62, P63 and P64 are available only on MB95F562H/F562K/F563H/F563K/F564H/F564K.
*4: P01, P02, P03, P07, PF0, PF1, PG1 and PG2 are available only on MB95F562H/F562K/F563H/F563K/
F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.
*5: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock / Machine Clock" for FMP and FMPL.
*6: In sub-CR clock mode, the power supply current value will become the sum of adding ICRL to ICCLS or ICCT. In
addition, when the sub-CR clock mode is selected with FMPL being 50 kHz, the current consumption will
increase accordingly.
DS702-00003-1v0-E
47
MB95560H/570H/580H Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Typ
Parameter Symbol Pin name Condition
Unit
Remarks
Min
Max
16.25 MHz
12 MHz
32.5 MHz
When the main oscillation
circuit is used
X0, X1
—
1
—
FCH
X0
X1 : open
1
1
—
—
When the main external clock
is used
X0, X1
*
Operating conditions
3.92
4
4.08 MHz • The main CR clock is used.
• 0°C < TA < +70°C
Operating conditions
• The main CR clock is used.
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
3.8
4
4.2 MHz
Operating conditions
8.16 MHz • PLL multiplier: 2
• 0°C < TA < +70°C
7.84
7.6
8
Operating conditions
• PLL multiplier: 2
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
8
8.4 MHz
Operating conditions
10.2 MHz • PLL multiplier: 2.5
• 0°C < TA < +70°C
9.8
10
10
12
12
16
16
FCRH
⎯
—
Operating conditions
Clock
• PLL multiplier: 2.5
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
frequency
9.5
10.5 MHz
Operating conditions
12.24 MHz • PLL multiplier: 3
• 0°C < TA < +70°C
11.76
11.4
15.68
15.2
Operating conditions
• PLL multiplier: 3
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
12.6 MHz
Operating conditions
16.32 MHz • PLL multiplier: 4
• 0°C < TA < +70°C
Operating conditions
• PLL multiplier: 4
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
16.8 MHz
When the sub-oscillation
circuit is used
When the sub-external clock is
used
When the sub-CR clock is
used
—
—
50
32.768
32.768
100
—
—
kHz
kHz
FCL
X0A, X1A
—
—
FCRL
⎯
150 kHz
(Continued)
48
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Typ
Parameter Symbol Pin name Condition
Unit
Remarks
Min
Max
When the main oscillation
circuit is used
X0, X1
—
61.5
—
1000 ns
tHCYL
Clock cycle
time
X0
X1 : open 83.4
—
—
1000 ns
1000 ns
When an external clock is
used
X0, X1
X0A, X1A
X0
*
30.8
—
tLCYL
—
30.5
—
—
—
—
—
µs When the subclock is used
ns
X1 : open 33.4
tWH1
tWL1
When an external clock is
ns
Input clock
pulse width
X0, X1
*
14.4
used, the duty ratio should
tWH2
tWL2
range between 40% and 60%.
X0A
X0
—
X1 : open
*
—
15.2
—
—
5
µs
ns
ns
Input clock rise
time and fall
time
—
tCR
tCF
When an external clock is
used
X0, X1
—
—
5
When the main CR clock is
used
tCRHWK
tCRLWK
—
—
—
—
—
—
—
—
50
30
µs
µs
CR oscillation
start time
When the sub-CR clock is
used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
DS702-00003-1v0-E
49
MB95560H/570H/580H Series
• Input waveform generated when an external clock (main clock) is used
t
HCYL
t
WH1
t
WL1
tCR
t
CF
X0, X1
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or When an external clock is used When an external clock
a ceramic oscillator is used (X1 is open) is used
X0
X1
X0
X1
X0
X1
Open
FCH
FCH
FCH
• Input waveform generated when an external clock (subclock) is used
t
LCYL
tWH2
t
WL2
tCR
t
CF
X0A
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
When an external clock
is used
X0A X1A
X0A X1A
Open
F
CL
FCL
50
DS702-00003-1v0-E
MB95560H/570H/580H Series
(2) Source Clock / Machine Clock
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Pin
name
Parameter Symbol
Unit
Remarks
Min
Typ
Max
When the main external clock is used
61.5
—
2000
ns Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
When the main CR clock is used
ns Min: FCRH = 4 MHz, multiplied by 4
Max: FCRH = 4 MHz, divided by 4
62.5
—
1000
Source clock
tSCLK
—
cycle time*1
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
—
61
20
—
—
µs
When the sub-CR clock is used
µs
FCRL = 100 kHz, divided by 2
0.5
—
—
4
16.25 MHz When the main oscillation clock is used
FSP
—
—
MHz When the main CR clock is used
Source clock
frequency
—
—
—
—
16.384
kHz When the sub-oscillation clock is used
FSPL
When the sub-CR clock is used
kHz
—
50
—
FCRL = 100 kHz, divided by 2
When the main oscillation clock is used
ns Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
61.5
—
32000
When the main CR clock is used
ns Min: FSP = 4 MHz, no division
Max: FSP = 4 MHz, divided by 4
Machine clock
cycle time*2
(minimum
instruction
execution
time)
250
61
—
—
—
1000
976.5
320
tMCLK
When the sub-oscillation clock is used
µs Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
When the sub-CR clock is used
µs Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
20
0.031
0.25
—
—
—
16.25 MHz When the main oscillation clock is used
16 MHz When the main CR clock is used
FMP
Machine clock
frequency
1.024
16.384 kHz When the sub-oscillation clock is used
FMPL
When the sub-CR clock is used
FCRL = 100 kHz
3.125
—
50
kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio
select bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the
division ratio set by the machine clock division ratio select bits (SYCC:DIV1, DIV0). In addition, a source
clock can be selected from the following.
• Main clock divided by 2
• PLL multiplication of main clock (Select a multiplier from 2, 2.5, 3 and 4.)
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS702-00003-1v0-E
51
MB95560H/570H/580H Series
• Schematic diagram of the clock generation block
FCH
Divided by 2
(Main oscillation clock)
FMPLL
(Main CR PLL)
Division circuit
SCLK
(Source clock)
×
×
×
1
1/4
1/8
FCRH
MCLK
(Main CR clock)
(Machine clock)
× 1/16
FCL
Divided by 2
Divided by 2
(Sub-oscillation clock)
Machine clock divide ratio select bits
(SYCC:DIV1, DIV0)
FCRL
(Sub-CR clock)
Clock mode select bits
(SYCC2: RCS1, RCS0)
• Operating voltage - Operating frequency (When TA = − 40°C to + 85°C)
MB95560H/570H/580H (without the on-chip debug function)
5.5
5.0
A/D converter operation range
4.0
3.5
3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL
)
• Operating voltage - Operating frequency (When TA = − 40°C to + 85°C)
MB95560H/570H/580H (with the on-chip debug function)
5.5
5.0
A/D converter operation range
4.0
3.5
3.0
2.9
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
52
DS702-00003-1v0-E
MB95560H/570H/580H Series
(3) External Reset
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Parameter Symbol
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns In normal operation
In stop mode, subclock mode,
µs subsleep mode, watch mode, and
power-on
RST “L” level
tRSTL
Oscillation time of the
—
—
pulse width
oscillator*2 + 200
200
µs In time-base timer mode
*1: See “(2) Source Clock / Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
t
RSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
200 μs
Oscillation
time of
oscillator
Oscillation stabilization wait time
Internal reset
Execute instruction
DS702-00003-1v0-E
53
MB95560H/570H/580H Series
(4) Power-on Reset
(VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Max
Parameter
Symbol
Condition
Unit
Remarks
Min
—
1
Power supply rising time
Power supply cutoff time
tR
—
—
50
—
ms
tOFF
ms Wait time until power-on
t
R
tOFF
2.5 V
0.2 V
0.2 V
0.2 V
VCC
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as
shown below.
VCC
Set the slope of rising to
a value below 30 mV/ms.
2.3 V
Hold condition in stop mode
V
SS
54
DS702-00003-1v0-E
MB95560H/570H/580H Series
(5) Peripheral Input Timing
Parameter
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Symbol
Pin name
Unit
Min
2 tMCLK
2 tMCLK
Max
—
*1
*1
Peripheral input “H” pulse width
Peripheral input “L” pulse width
tILIH
tIHIL
ns
ns
INT02 to INT07*2,*3, EC0*2, EC1*4
—
t
ILIH
t
IHIL
0.8 VCC 0.8 VCC
INT02 to INT07*2, *3
EC0*2, EC1*4
,
0.2 VCC
0.2 VCC
*1: See “(2) Source Clock / Machine Clock” for tMCLK.
*2: INT04, INT06 and EC0 are available on all products.
*3: INT02, INT03, INT05 and INT07 are available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/
F582H/F582K/F583H/F583K/F584H/F584K.
*4: EC1 is available only on MB95F562H/F562K/F563H/F563K/F564H/F564K.
DS702-00003-1v0-E
55
MB95560H/570H/580H Series
(6) LIN-UART Timing (available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/
F583H/F583K/F584H/F584K)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Parameter
Symbol Pin name
Condition
Unit
Min
5 tMCLK*3
− 50
Max
—
Serial clock cycle time
SCK ↓→ SOT delay time
Valid SIN → SCK ↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
tF
SCK
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin:
CL = 80 pF + 1 TTL
SCK, SOT
SCK, SIN
SCK, SIN
SCK
+ 50
—
tMCLK*3 + 80
SCK ↑→ valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓→ SOT delay time
Valid SIN → SCK ↑
0
—
3 tMCLK*3 − tR
tMCLK*3 + 10
—
—
SCK
—
SCK, SOT
2 tMCLK*3 + 60 ns
External clock
SCK, SIN operation output pin:
30
—
—
10
10
ns
ns
ns
ns
CL = 80 pF + 1 TTL
SCK ↑→ valid SIN hold time
SCK fall time
SCK, SIN
tMCLK*3 + 30
SCK
SCK
—
SCK rise time
tR
—
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
56
DS702-00003-1v0-E
MB95560H/570H/580H Series
• Internal shift clock mode
tSCYC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
t
SLOVI
0.8 VCC
0.2 VCC
SOT
tIVSHI
tSHIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSLSH
t
SHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
t
R
tF
t
SLOVE
0.8 VCC
SOT
SIN
0.2 VCC
t
IVSHE
t
SHIXE
0.7 VCC 0.7 VCC
0.3 VCC 0.3 VCC
DS702-00003-1v0-E
57
MB95560H/570H/580H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0)
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Parameter
Symbol Pin name
Condition
Unit
Min
5 tMCLK*3
− 50
Max
—
Serial clock cycle time
SCK ↑→ SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
SCK
ns
ns
ns
ns
ns
ns
Internal clock
operation output pin:
CL = 80 pF + 1 TTL
SCK, SOT
SCK, SIN
SCK, SIN
SCK
+ 50
—
tMCLK*3 + 80
SCK ↓→ valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑→ SOT delay time
Valid SIN → SCK ↓
0
—
3 tMCLK*3 − tR
tMCLK*3 + 10
—
—
SCK
—
tSHOVE SCK, SOT
2 tMCLK*3 + 60 ns
External clock
tIVSLE
tSLIXE
tF
SCK, SIN operation output pin:
30
—
—
10
10
ns
ns
ns
ns
CL = 80 pF + 1 TTL
SCK ↓→ valid SIN hold time
SCK fall time
SCK, SIN
tMCLK*3 + 30
SCK
SCK
—
SCK rise time
tR
—
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
58
DS702-00003-1v0-E
MB95560H/570H/580H Series
• Internal shift clock mode
tSCYC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
t
SHOVI
0.8 VCC
0.2 VCC
SOT
tIVSLI
tSLIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSHSL
t
SLSH
0.8 VCC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
0.2 VCC
t
F
t
R
tSHOVE
0.8 VCC
SOT
SIN
0.2 VCC
t
IVSLE
t
SLIXE
0.7 VCC 0.7 VCC
0.3 VCC 0.3 VCC
DS702-00003-1v0-E
59
MB95560H/570H/580H Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1)
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Parameter
Symbol Pin name
Condition
Unit
Min
5 tMCLK*3
− 50
Max
—
Serial clock cycle time
SCK ↑→ SOT delay time
Valid SIN → SCK ↓
tSCYC
tSHOVI
tIVSLI
SCK
ns
ns
ns
ns
ns
SCK, SOT
+ 50
—
Internal clock
SCK, SIN operation output pin: tMCLK*3 + 80
CL = 80 pF + 1 TTL
SCK ↓→ valid SIN hold time
SOT → SCK ↓ delay time
tSLIXI
SCK, SIN
SCK, SOT
0
—
tSOVLI
3 tMCLK*3 − 70
—
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
t
SCYC
0.8 VCC
SCK
SOT
SIN
0.2 VCC
0.2 VCC
tSHOVI
t
SOVLI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIVSLI
t
SLIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
60
DS702-00003-1v0-E
MB95560H/570H/580H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1)
(VCC = 5.0 V 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Parameter
Symbol Pin name
Condition
Unit
Min
5 tMCLK*3
− 50
Max
—
Serial clock cycle time
SCK ↓→ SOT delay time
Valid SIN → SCK ↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
SCK
ns
ns
ns
ns
ns
SCK, SOT
+ 50
—
Internal clock
SCK, SIN operating output pin: tMCLK*3 + 80
CL = 80 pF + 1 TTL
SCK ↑→ valid SIN hold time
SOT → SCK ↑ delay time
SCK, SIN
SCK, SOT
0
—
3 tMCLK*3 − 70
—
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
t
SCYC
0.8 VCC
0.8 VCC
SCK
SOT
SIN
0.2 VCC
t
SOVHI
t
SLOVI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t
IVSHI
t
SHIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
DS702-00003-1v0-E
61
MB95560H/570H/580H Series
(7) Low-voltage Detection
(VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
2.52
2.61
2.89
3.08
2.43
2.52
2.80
2.99
—
Typ
2.7
2.8
3.1
3.3
2.6
2.7
3
Max
2.88
2.99
3.31
3.52
2.77
2.88
3.20
3.41
100
2.3
Release voltage*
VDL+
V
At power supply rise
At power supply fall
Detection voltage*
VDL−
V
3.2
—
Hysteresis width
VHYS
Voff
mV
V
Power supply start voltage
Power supply end voltage
—
—
Von
4.9
—
—
V
Power supply voltage
change time
(at power supply rise)
Slope of power supply that the reset
µs release signal generates within the
rating (VDL+)
tr
tf
650
650
—
—
—
—
Power supply voltage
change time
(at power supply fall)
Slope of power supply that the reset
µs detection signal generates within the
rating (VDL-)
Reset release delay time
Reset detection delay time
td1
td2
—
—
—
—
30
30
µs
µs
LVD threshold voltage
transition stabilization time
tstb
10
—
—
µs
*: The release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID
register (LVDR) in the low-voltage detection reset circuit. For details of the LVDR register, refer to
“CHAPTER 18 LOW-VOLTAGE DETECTION RESET CIRCUIT” in the hardware manual of the MB95560H/
570H/580H Series.
62
DS702-00003-1v0-E
MB95560H/570H/580H Series
VCC
Von
Voff
time
tf
tr
V
V
DL+
V
HYS
DL-
Internal reset signal
time
td2
td1
DS702-00003-1v0-E
63
MB95560H/570H/580H Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Typ
—
Parameter
Resolution
Symbol
Unit
Remarks
Min
—
Max
10
bit
Total error
− 3
—
+ 3
LSB
LSB
—
Linearity error
− 2.5
—
+ 2.5
Differential linear
error
− 1.9
—
+ 1.9
LSB
V
Zero transition
voltage
VOT
VSS − 7.2 LSB VSS + 0.5 LSB VSS + 8.2 LSB
VCC − 6.2 LSB VCC − 1.5 LSB VCC + 9.2 LSB
Full-scale transition
voltage
VFST
—
V
Compare time
3
—
—
10
µs 2.7 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V,
µs with external
Sampling time
—
0.517
∞
impedance < 3.3 kΩ
Analog input current
Analog input voltage
IAIN
− 0.3
—
—
+ 0.3
µA
V
VAIN
VSS
VCC
64
DS702-00003-1v0-E
MB95560H/570H/580H Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 5.5 V
3.3 kΩ (Max)
15.7 kΩ (Max)
14.89 pF (Max)
14.89 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
[External impedance = 0 kΩ to 20 kΩ]
100000
80000
60000
40000
20000
0
20000
15000
10000
5000
0
0
2
4
6
8
10
12
0
0.5
1
1.5
2
2.5
Minimum sampling time [μs]
Minimum sampling time [μs]
Minimum sampling time with VCC > 2.7 V
Minimum sampling time with VCC > 2.4 V
• A/D conversion error
As |VCC − VSS| decreases, the A/D conversion error increases proportionately.
DS702-00003-1v0-E
65
MB95560H/570H/580H Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
3FFH
3FEH
3FDH
3FFH
3FEH
3FDH
VFST
Actual conversion
characteristic
2 LSB
{1 LSB × (N-1) + 0.5 LSB}
004H
003H
002H
001H
004H
003H
002H
001H
VOT
VNT
Actual conversion
characteristic
1 LSB
Ideal characteristic
0.5 LSB
VSS
Analog input
VCC - VSS
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
1 LSB
Total error of
digital output N
1 LSB =
(V)
=
[LSB]
1024
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
66
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Zero transition error
Full-scale transition error
Ideal characteristic
004H
003H
002H
001H
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
Actual conversion
Ideal
characteristic
3FDH
3FCH
characteristic
Actual conversion
characteristic
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
Linearity error
Differential linearity error
Ideal characteristic
Actual conversion
characteristic
3FFH
3FEH
3FDH
(N+1)H
NH
Actual conversion
characteristic
{1 LSB × N + VOT}
V(N+1)T
VFST
(measurement
value)
VNT
004H
003H
002H
001H
VNT
(N-1)H
(N-2)H
Actual conversion
characteristic
Ideal
Actual conversion
characteristic
characteristic
VOT (measurement value)
Analog input
VSS
VCC
VSS
Analog input
VCC
V(N+1)T - VNT
VNT - {1 LSB × N + VOT}
1 LSB
Differential linear error
of digital output N
Linearity error
of digital output N
=
- 1
=
1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
DS702-00003-1v0-E
67
MB95560H/570H/580H Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
The time of writing 00H prior to
erasure is excluded.
—
0.3*1
1.6
s
s
Sector erase time
(16 Kbyte sector)
The time of writing 00H prior to
erasure is excluded.
—
0.6*1
3.1
Byte writing time
—
17
—
272
—
µs System-level overhead is excluded.
cycle
Program/erase cycle
100000
Power supply voltage at
program/erase
2.4
—
—
5.5
—
V
Flash memory data retention
time
5*2
year Average TA = + 85°C
*1: VCC = 5.5 V, TA = + 25°C, 0 cycle
*2: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being + 85°C).
68
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
ICC − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
F
F
MP = 16 MHz
MP = 10 MHz
15
10
5
15
10
5
0
0
−50
0
+50
+100
+150
2
3
4
5
6
7
TA[°C]
V
CC[V]
ICCS − VCC
ICCS − TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
Main sleep mode with the external clock operating
10
10
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
F
F
MP = 16 MHz
MP = 10 MHz
8
6
4
2
0
8
6
4
2
0
−50
0
+50
+100
+150
2
3
4
5
6
7
TA[°C]
VCC[V]
ICCL − VCC
ICCL − TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
Subclock mode with the external clock operating
100
100
75
50
25
0
75
50
25
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
TA[°C]
(Continued)
DS702-00003-1v0-E
69
MB95560H/570H/580H Series
ICCLS − VCC
ICCLS − TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
Subsleep mode with the external clock operating
80
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
−50
0
+50
+100
+150
2
3
4
5
6
7
TA[°C]
VCC[V]
ICCT − VCC
ICCT − TA
TA = +25°C, FMPL = 16 kHz (divided by 2)
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
Watch mode with the external clock operating
20
20
16
12
8
16
12
8
4
4
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
TA[°C]
ICTS − VCC
ICTS − TA
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
VCC = 5.5 V, FMP = 10, 16 kHz (divided by 2)
Time-base timer mode with the external clock
Time-base timer mode with the external clock
operating
operating
1.4
1.4
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
F
F
MP = 16 MHz
MP = 10 MHz
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−50
0
+50
[°C]
+100
+150
2
3
4
5
6
7
T
A
VCC[V]
(Continued)
70
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
ICCH − VCC
ICCH − TA
TA = +25°C, FMPL = (stop)
VCC = 5.5 V, FMPL = (stop)
Substop mode with the external clock stopping
Substop mode with the external clock stopping
20
20
15
10
5
15
10
5
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
TA[°C]
ICCMCR − VCC
ICCMCR − TA
TA = +25°C, FMP = 4 MHz (no division)
VCC = 5.5 V, FMP = 4 MHz (no division)
Main clock mode with the main CR clock operating
Main clock mode with the main CR clock operating
20
20
15
10
5
15
10
5
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
TA[°C]
ICCSCR − VCC
ICCSCR − TA
TA = +25°C, FMPL = 50 kHz (divided by 2)
VCC = 5.5 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
Subclock mode with the sub-CR clock operating
200
200
150
100
50
150
100
50
0
0
2
3
4
5
6
7
−50
0
+50
+100
+150
VCC[V]
TA[°C]
DS702-00003-1v0-E
71
MB95560H/570H/580H Series
• Input voltage characteristics
VIHI − VCC and VILI − VCC
VIHS − VCC and VILS − VCC
TA = +25°C
TA = +25°C
5
5
4
3
2
1
0
VIHI
VILI
V
V
IHS
ILS
4
3
2
1
0
2
3
4
5
6
7
2
3
4
5
6
7
VCC[V]
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25°C
5
4
3
2
1
0
V
V
IHM
ILM
2
3
4
5
6
7
VCC[V]
72
DS702-00003-1v0-E
MB95560H/570H/580H Series
• Output voltage characteristics
(VCC − VOH1) − IOH
(VCC − VOH2) − IOH
TA = +25°C
TA = +25°C
1.0
1.0
0.8
0.6
0.4
0.2
0.0
0.8
0.6
0.4
0.2
0.0
0
−2
−4
−6
−8
−10
0
−2
−4
−6
−8
−10
IOH [mA]
IOH [mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VOL1 − IOL
TA = +25°C
VOL2 − IOL
TA = +25°C
1.0
0.8
0.6
0.4
0.2
0.0
0.6
0.4
0.2
0.0
0
2
4
6
8
10
0
2
4
6
8
10
IOL [mA]
IOL [mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
V
V
V
V
V
V
CC = 2.4 V
CC = 2.7 V
CC = 3.5 V
CC = 4.5 V
CC = 5.0 V
CC = 5.5 V
DS702-00003-1v0-E
73
MB95560H/570H/580H Series
• Pull-up characteristics
RPULL − VCC
TA = +25°C
250
200
150
100
50
0
2
3
4
5
6
VCC[V]
74
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ MASK OPTIONS
MB95F562H
MB95F563H
MB95F564H
MB95F572H
MB95F573H
MB95F574H
MB95F582H
MB95F583H
MB95F584H
MB95F562K
MB95F563K
MB95F564K
MB95F572K
MB95F573K
MB95F574K
MB95F582K
MB95F583K
MB95F584K
Part Number
No.
Selectable/Fixed
Fixed
1
2
Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset
Reset With dedicated reset input Without dedicated reset input
DS702-00003-1v0-E
75
MB95560H/570H/580H Series
■ ORDERING INFORMATION
Part Number
Package
MB95F562HWQN-G-JNE1
MB95F562HWQN-G-JNERE1
MB95F562KWQN-G-JNE1
MB95F562KWQN-G-JNERE1
MB95F563HWQN-G-JNE1
MB95F563HWQN-G-JNERE1
MB95F563KWQN-G-JNE1
MB95F563KWQN-G-JNERE1
MB95F564HWQN-G-JNE1
MB95F564HWQN-G-JNERE1
MB95F564KWQN-G-JNE1
MB95F564KWQN-G-JNERE1
32-pin plastic QFN
(LCC-32P-M19)
MB95F562HPF-G-JNE2
MB95F562KPF-G-JNE2
MB95F563HPF-G-JNE2
MB95F563KPF-G-JNE2
MB95F564HPF-G-JNE2
MB95F564KPF-G-JNE2
20-pin plastic SOP
(FPT-20P-M09)
MB95F562HPFT-G-JNE2
MB95F562KPFT-G-JNE2
MB95F563HPFT-G-JNE2
MB95F563KPFT-G-JNE2
MB95F564HPFT-G-JNE2
MB95F564KPFT-G-JNE2
20-pin plastic TSSOP
(FPT-20P-M10)
MB95F582HWQN-G-JNE1
MB95F582HWQN-G-JNERE1
MB95F582KWQN-G-JNE1
MB95F582KWQN-G-JNERE1
MB95F583HWQN-G-JNE1
MB95F583HWQN-G-JNERE1
MB95F583KWQN-G-JNE1
MB95F583KWQN-G-JNERE1
MB95F584HWQN-G-JNE1
MB95F584HWQN-G-JNERE1
MB95F584KWQN-G-JNE1
MB95F584KWQN-G-JNERE1
32-pin plastic QFN
(LCC-32P-M19)
MB95F582HPFT-G-JNE2
MB95F582KPFT-G-JNE2
MB95F583HPFT-G-JNE2
MB95F583KPFT-G-JNE2
MB95F584HPFT-G-JNE2
MB95F584KPFT-G-JNE2
16-pin plastic TSSOP
(FPT-16P-M08)
MB95F582HPF-G-JNE2
MB95F582KPF-G-JNE2
MB95F583HPF-G-JNE2
MB95F583KPF-G-JNE2
MB95F584HPF-G-JNE2
MB95F584KPF-G-JNE2
16-pin plastic SOP
(FPT-16P-M23)
MB95F572HPF-G-JNE2
MB95F572KPF-G-JNE2
MB95F573HPF-G-JNE2
MB95F573KPF-G-JNE2
MB95F574HPF-G-JNE2
MB95F574KPF-G-JNE2
8-pin plastic SOP
(FPT-8P-M08)
76
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PACKAGE DIMENSION
32-pin plastic QFN
Lead pitch
0.50 mm
5.00 mm × 5.00 mm
Plastic mold
Package width ×
package length
Sealing method
Mounting height
Weight
0.80 mm MAX
0.06 g
(LCC-32P-M19)
32-pin plastic QFN
(LCC-32P-M19)
3.50 0.10
(.138 .004)
5.00 0.10
(.197 .004)
3.50 0.10
(.138 .004)
5.00 0.10
(.197 .004)
+0.05
0.25 –0.07
+.002
INDEX AREA
(.010
)
–.003
(3-R0.20)
((3-R.008))
0.40 0.05
(.016 .002)
1PIN CORNER
0.50(.020)
(TYP)
(C0.30(C.012))
0.75 0.05
(.030 .002)
+0.03
0.02 –0.02
+.001
(0.20(.008))
(.001
)
–.001
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00003-1v0-E
77
MB95560H/570H/580H Series
20-pin plastic SOP
Lead pitch
Package width
1.27 mm
7.50 mm × 12.70 mm
Gullwing
×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
Sealing method
Mounting height
2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP
(FPT-20P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
0.25 +–00..0027
#12.70 0.10(.500 .004)
.010 –+..000013
20
11
BTM E-MARK
+0.40
#7.50 0.10
(.295 .004)
10.2 –0.20
.402 +–..000186
INDEX
Details of "A" part
+0.13
2.52 –0.17
(Mounting height)
.099 –+..000075
"A"
1
10
0.40 –+00..0059
.016 –+..000024
0~8°
1.27(.050)
M
0.25(.010)
0.80–+00..3407
.031–+..001129
0.20 0.10
(.008 .004)
(Stand off)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
78
DS702-00003-1v0-E
MB95560H/570H/580H Series
20-pin plastic TSSOP
Lead pitch
0.65 mm
4.40 mm × 6.50 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.20 mm MAX
0.08 g
(FPT-20P-M10)
20-pin plastic TSSOP
(FPT-20P-M10)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#6.50 0.10(.256 .004)
0.14 +–00..0045
.006 –+..000022
20
11
BTM E-MARK
#4.40 0.10
6.40 0.20
(.173 .004) (.252 .008)
INDEX
Details of "A" part
1.20(.047)
(Mounting height)
MAX
1
10
LEAD No.
"A"
0.65(.026)
0.24 0.04
(.009 .002)
0~8°
0.10 0.05
(.004 .002)
0.60 0.15
(.024 .006)
(Stand off)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F20031S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00003-1v0-E
79
MB95560H/570H/580H Series
16-pin plastic TSSOP
Lead pitch
Package width
0.65 mm
4.40 mm × 4.96 mm
Gullwing
×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.20 mm Max
0.06 g
(FPT-16P-M08)
16-pin plastic TSSOP
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) * : These dimensions do not include resin protrusion.
(FPT-16P-M08)
*4.96 0.10(.195 .004)
0.145 0.045
(.0057 .0018)
16
9
*4.40 0.10
6.40 0.20
(.173 .004) (.252 .008)
INDEX
Details of "A" part
1.10 +–00..1150
(Mounting height)
+0.04
.043
–0.06
1
8
LEAD No.
"A"
0.65(.026)
0.24 0.08
(.009 .003)
M
0.13(.005)
0~8°
0.10 0.05
(.004 .002)
(Stand off)
0.60 0.15
(.024 .006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2007-2010 FUJITSU SEMICONDUCTOR LIMITED F16021S-c-1-5
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
80
DS702-00003-1v0-E
MB95560H/570H/580H Series
16-pin plastic SOP
Lead pitch
1.27 mm
3.90 mm × 9.96 mm
Gullwing
Package width
package length
×
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.75 mm MAX
0.12 g
(FPT-16P-M23)
16-pin plastic SOP
(FPT-16P-M23)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
0.60 +–00..1250
#9.96 0.10(.392 .004)
+0.08
.024
–0.06
16
9
8
2
8
2
BTM E-MARK
(1.04 (.041))
INDEX
#3.90 0.10 6.00 0.20
(.236 .008)
(.154 .004)
0.40 0.10
(.016 .004)
0.40 0.10
(.016 .004)
1
8
+0.11
–0.04
0.40
1.27(.050)
M
0.25(.010)
0.65 0.10 (.026 .004)
+.004
–.002
(.016
)
1.45 0.20(.057 .008)
7
2
1.60 +–00..2155
+0.06
.063
–0.10
0.15 +–00..0150 .006
+0.04
–0.02
0.10(.004)
7
2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF16-23Sc-1-1
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00003-1v0-E
81
MB95560H/570H/580H Series
(Continued)
8-pin plastic SOP
Lead pitch
Package width
1.27 mm
5.30 mm × 5.24 mm
Gullwing
×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
Sealing method
Mounting height
2.10 mm Max
(FPT-8P-M08)
8-pin plastic SOP
(FPT-8P-M08)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#5.24 0.10
(.206 .004)
8
5
"A"
BTM E-MARK
+0.45
7.80 –0.10
+.018
.307 –.004
#5.30 0.10
(.209 .004)
INDEX
Details of "A" part
2.10(.083)
MAX
(Mounting height)
1
4
0.20 0.05
(.008 .002)
1.27(.050)
0.43 0.05
(.017 .002)
0~8°
0.10 –+00..0155
0.75 –+00..2100
.030 +–..000084
.004 –+..000026
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
82
DS702-00003-1v0-E
MB95560H/570H/580H Series
MEMO
DS702-00003-1v0-E
83
MB95560H/570H/580H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
相关型号：
©2020 ICPDF网 联系我们和版权申明