MB96F346RWA [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB96F346RWA |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总130页 (文件大小：3759K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
FME-MB96340 rev 10
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96340 Series
MB96345/346 MB96F345 *1
MB96F346/F347/F348
■ DESCRIPTION
MB96340 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.6
MB96340 Series
■ FEATURES
Feature
Description
Technology
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 56 MHz internal, 17.8 ns instruction cycle time
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
CPU
• 8-byte instruction execution queue
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
• 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using
ceramic resonator depends on Q-factor).
• Up to 56 MHz external clock for devices with fast clock input feature
• 32-100 kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection,
watchdog
System clock
• Clock source selectable from main- and subclock oscillator (part number suffix “W”)
and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
and low power consumption figures
On-chip voltage regula-
tor
Low voltage reset
Code Security
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
• Replaces ROM content
Memory Patch Function
DMA
• Can also be used to implement embedded debug support
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
Interrupts
Timers
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
2
FME-MB96340 rev 10
MB96340 Series
Feature
Description
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• Up to 400 kbps
USART
I2C
• Master and Slave functionality, 7-bit and 10-bit addressing
• SAR-type
• 10-bit resolution
A/D converter
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
A/D Converter Refer- • 2 independent positive A/D converter reference voltages available
ence Voltage switch
• 16-bit wide
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
• Event count function
Reload Timers
Free Running Timers
Input Capture Units
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of
peripheral clock frequency
• 16-bit wide
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
• 16-bit wide
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
FME-MB96340 rev 10
3
MB96340 Series
Feature
Description
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
• PWM operation and one-shot operation
Programmable Pulse
Generator
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer underflow as clock input
• Can be triggered by software or reload timer
• Can be clocked either from sub oscillator (devices with part number suffix “W”), main
oscillator or from the RC oscillator
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
Real Time Clock
• Read/write accessible second/minute/hour registers
• Can signal interrupts every half second/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock
• Edge sensitive or level sensitive
• Interrupt mask and pending bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
External Interrupts
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
Non Maskable Interrupt
• Pin shared with external interrupt 0.
• 8-bit or 16-bit bidirectional data
• Up to 24-bit addresses
• 6 chip select signals
External bus interface • Multiplexed address/data lines
• Wait state request
• External bus master possible
• Timing programmable
• Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
Alarm comparator
• Threshold voltages defined externally or generated internally
• Status is readable, interrupts can be masked separately
4
FME-MB96340 rev 10
MB96340 Series
Feature
Description
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
• Bit-wise programmable as input/output or peripheral signal
• Bit-wise programmable input enable
I/O Ports
• Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL (TTL
levels not supported by all devices)
• Bit-wise programmable pull-up resistor
• Bit-wise programmable output driving strength for EMI optimization
• 100-pin plastic QFP and LQFP
Packages
• Supports automatic programming, Embedded Algorithm
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles: 10,000 times
Flash Memory
• Data retention time: 20 years
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash
• Low voltage detection during Flash erase
FME-MB96340 rev 10
5
MB96340 Series
■ PRODUCT LINEUP
Features
MB96V300B
Evaluation sample
MB96(F)34x
Flash product: MB96F34x
Mask ROM product: MB9634x
Product type
Product options
YS
RS
YW
RW
TS
Low voltage reset persistently on / Single clock
Low voltage reset can be disabled / Single clock
Low voltage reset persistently on / Dual clock
Low voltage reset can be disabled / Dual clock
indep. 32KB Flash / Low voltage reset persistently on / Single clock
indep. 32KB Flash / Low voltage reset can be disabled / Single clock
indep. 32KB Flash / Low voltage reset persistently on / Dual clock
indep. 32KB Flash / Low voltage reset can be disabled / Dual clock
64KB Data Flash / Low voltage reset persistently on / Single clock
64KB Data Flash / Low voltage reset can be disabled / Single clock
64KB Data Flash / Low voltage reset persistently on / Dual clock
64KB Data Flash / Low voltage reset can be disabled / Dual clock
No CAN / Low voltage reset can be disabled / Single clock devices
HS
TW
HW
FS
NA
DS
FW
DW
AS
No CAN / indep. 32KB Flash / Low voltage reset can be disabled /
Single clock
CS
AW
CW
No CAN / Low voltage reset can be disabled / Dual clock
No CAN / indep. 32KB Flash / Low voltage reset can be disabled /
Dual clock
Flash/ROM
160KB
RAM
8KB
MB96345Y*1, MB96345R*1
224KB
[Flash A: 160KB,
Data Flash A: 64KB]
MB96F345F *1, MB96F345D*1
8KB
ROM/Flash
memory emulation
by external RAM,
92KB internal
RAM
288KB
416KB
544KB
16KB
16KB
24KB
*1, MB96F346R, MB96346R *1, MB96F346A
MB96F346Y, MB96346Y
MB96F347Y, MB96F347R, MB96F347A
MB96F348Y, MB96F348R, MB96F348A
MB96F348T, MB96F348H, MB96F348C
576KB
[Flash A: 544KB,
Flash B: 32KB]
24KB
Package
BGA416
FPT-100P-M20
FPT-100P-M22
6
FME-MB96340 rev 10
MB96340 Series
Features
MB96V300B
MB96(F)34x
DMA
USART
16 channels
10 channels
2 channels
40 channels
6 channels
7 channels
2 channels
24 channels
I2C
A/D Converter
A/D Converter Reference
Voltage switch
yes
yes (except MB96F345Dyy or MB96F345Fyy)
4 channels + 1 channel (for PPG)
6 channels + 1
channel (for PPG)
16-bit Reload Timer
16-bit Free-Running Timer
16-bit Output Compare
16-bit Input Capture
4 channels
12 channels
12 channels
2 channels
8 channels
8 channels
16-bit Programmable Pulse
Generator
20 channels
5 channels
16 channels
MB96(F)34xAyy or MB96(F)34xCyy: no
MB96F345Dyy or MB96F345Fyy: 1 channel
others: 2 channels
CAN Interface
External Interrupts
Non-Maskable Interrupt
Real Time Clock
I/O Ports
16 channels
1 channel
1
136
80 for part number with suffix "W", 82 for part number with suffix "S"
2 channels
MB96F345Dyy or MB96F345Fyy: no
others: 2 channels
Alarm comparator
External bus interface
Chip select
Yes
Yes (multiplexed address/data)
6 signals
2 channels
Yes
Clock output function
Low voltage reset
On-chip RC-oscillator
Yes
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
FME-MB96340 rev 10
7
MB96340 Series
■ BLOCK DIAGRAM
Block diagram of MB96(F)34x
AD00 ... AD15
CKOT0, CKOT1
CKOTX0, CKOTX1
X0, X1
A16 ... A23
ALE
RDX
WR(L)X, WRHX
HRQ
X0A, X1A *1
RSTX
MD0...MD2
HAKX
NMI, NMI_R
RDY
ECLK
LBX, UBX
CS0 ... CS5
Memory Patch
Unit
External Bus
16FX
Interface
CPU
Flash
Memory A
Flash Memory B
or Data Flash A*2
Clock &
Mode Controller
Interrupt
Controller
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
Controller
RAM
Boot ROM
VCC
VSS
C
SDA0, SDA1
I2C
2 ch.
SCL0, SCL1
TX0, TX1 *3
RX0, RX1 *3
CAN
Interface
2 ch.
AVCC
AVSS
AVRH
AVRL/AVRH2 *5
AN0 ... AN23
10-bit ADC
24 ch.
ADTG, ADTG_R
16-bit Reload
Timer
TIN0 ... TIN3
SIN0...SIN3, SIN2_R, SIN7_R...SIN9_R
SOT0...SOT3, SOT2_R, SOT7_R...SOT9_R
SCK0...SCK3, SCK2_R, SCK7_R...SCK9_R
USART
7 ch.
TOT0 ... TOT3
4 ch.
FRCK0
IN0 ... IN3
OUT0 ... OUT3
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
ALARM0 *4
ALARM1 *4
Alarm
Comparator
2 ch. *4
FRCK1
IN4 ... IN7
OUT4 ... OUT7
I/O Timer 1
ICU 4/5/6/7
OCU 4/5/6/7
TTG0 ... TTG15
PPG0 ... PPG15
16-bit PPG
16 ch.
RLT6
INT0 ... INT15
INT0_R ... INT2_R
INT4_R, INT5_R
INT7_R ... INT15_R
INT3_R1
External
Interrupt
Real Time
Clock
WOT
*1: X0A, X1A only available on MB96(F)34xyWy
*2: Flash B only available on MB96F34xCyy, MB96F34xHyy or MB96F34xTyy
Data Flash A only available on MB96F34xDyy or MB96F34xFyy
*3: CAN interfaces are not available on MB96(F)34xAyy or MB96(F)34xCyy
CAN1 is not available on MB96F345Dyy or MB96F345Fyy
*4: Alarm comparator is not available on MB96F345Dyy or MB96F345Fyy
*5: A/D converter reference voltage switch is not available on MB96F345Dyy or MB96F345Fyy
8
FME-MB96340 rev 10
MB96340 Series
■ PIN ASSIGNMENTS
Pin assignment of MB96(F)34x (FPT-100P-M22)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P00_4/AD04/INT12/SOT8_R
P00_5/AD05/INT13/SIN8_R
P00_6/AD06/INT14
P00_7/AD07/INT15
P01_0/AD08/CKOT1/TIN1
P01_1/AD09/CKOTX1/TOT1
P01_2/AD10/INT11_R/SIN3
P01_3/AD11/SOT3
P01_4/AD12/SCK3
Vcc
P07_5/AN21/INT5/SCK9_R
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
P07_0/AN16/INT0/NMI
Vss
P06_7/AN7/PPG7
P06_6/AN6/PPG6
P06_5/AN5/PPG5
P06_4/AN4/PPG4
P06_3/AN3/PPG3
P06_2/AN2/PPG2
P06_1/AN1/PPG1
P06_0/AN0/PPG0
AVss
QFP - 100
Vss
Package code (mold)
FPT-100P-M22
X1
X0
P01_5/AD13/INT7_R/SIN2_R
P01_6/AD14/SOT2_R
P01_7/AD15/SCK2_R
P02_0/A16/PPG12
P02_1/A17/PPG13
P02_2/A18/PPG14
P02_3/A19/PPG15
AVRL/AVRH2*4
AVRH
AVcc
100
P05_7/AN15/INT5_R
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*1: MB96(F)34xyWy: X0A, X1A
MB96(F)34xySy: P04_0, P04_1
*2: TX0, RX0, TX1, RX1 are not available on MB96(F)34xAyy or MB96(F)34xCyy
TX1, RX1 are not available on MB96F345Dyy or MB96F345Fyy
*3: ALARM0, ALARM1 are not available on MB96F345Dyy or MB96F345Fyy
*4: AVRH2 is not available on MB96F345Dyy or MB96F345Fyy
(FPT-100P-M22)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
FME-MB96340 rev 10
9
MB96340 Series
Pin assignment of MB96(F)34x (FPT-100P-M20)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
MD1
P00_1AD01/INT9/SOT7_R
P00_2/AD02/INT10/SIN7_R
P00_3/AD03/INT11/SCK8_R
P00_4/AD04/INT12/SOT8_R
P00_5/AD05/INT13/SIN8_R
P00_6/AD06/INT14
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD2
P07_5/AN21/INT5/SCK9_R
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
P07_0/AN16/INT0/NMI
Vss
P00_7/AD07/INT15
P01_0/AD08/CKOT1/TIN1
P01_1/AD09/CKOTX1/TOT1
P01_2/AD10/INT11_R/SIN3
P01_3/AD11/SOT3
P06_7/AN7/PPG7
P06_6/AN6/PPG6
P06_5/AN5/PPG5
P06_4/AN4/PPG4
P06_3/AN3/PPG3
P06_2/AN2/PPG2
P06_1/AN1/PPG1
P06_0/AN0/PPG0
AVss
LQFP - 100
P01_4/AD12/SCK3
Vcc
Vss
Package code (mold)
FPT-100P-M20
X1
X0
P01_5/AD13/INT7_R/SIN2_R
P01_6/AD14/SOT2_R
P01_7/AD15/SCK2_R
P02_0/A16/PPG12
AVRL/AVRH2*4
AVRH
P02_1/A17/PPG13
AVcc
P02_2/A18/PPG14
P05_7/AN15/INT5_R
P05_6/AN14/INT4_R
P05_5/AN13/INT0_R/NMI_R
P05_4/AN12/TOT3/INT2_R
P02_3/A19/PPG15
P02_4/A20/TTG8/TTG0/IN0
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
*1: MB96(F)34xyWy: X0A, X1A
MB96(F)34xySy: P04_0, P04_1
*2: TX0, RX0, TX1, RX1 are not available on MB96(F)34xAyy or MB96(F)34xCyy
TX1, RX1 are not available on MB96F345Dyy or MB96F345Fyy
*3: ALARM0, ALARM1 are not available on MB96F345Dyy or MB96F345Fyy
*4: AVRH2 is not available on MB96F345Dyy or MB96F345Fyy
(FPT-100P-M20)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
10
FME-MB96340 rev 10
MB96340 Series
■ PIN FUNCTION DESCRIPTION
Pin Function description (1 of 2)
Pin name
ADn
Feature
Description
External bus interface (multiplexed mode) address output and
data input/output
External bus
ADTG
ADTG_R
ALARMn
ALE
ADC
ADC
A/D converter trigger input
Relocated A/D converter trigger input
Alarm Comparator n input
Alarm comparator
External bus
External bus
ADC
External bus Address Latch Enable output
External bus address output
An
ANn
A/D converter channel n input
AVCC
Supply
Analog circuits power supply
AVRH
AVRH2
AVRL
AVSS
ADC
A/D converter high reference voltage input
Alternative A/D converter high reference voltage input
A/D converter low reference voltage input
Analog circuits power supply
ADC
ADC
Supply
C
Voltage regulator
Clock output function
Clock output function
External bus
External bus
Free Running Timer
External bus
External bus
ICU
Internally regulated power supply stabilization capacitor pin
Clock Output function n output
CKOTn
CKOTXn
ECLK
CSn
Clock Output function n inverted output
External bus clock output
External bus chip select n output
Free Running Timer n input
FRCKn
HAKX
HRQ
External bus Hold Acknowledge
External bus Hold Request
INn
Input Capture Unit n input
INTn
External Interrupt
External Interrupt
External bus
Core
External Interrupt n input
INTn_R
LBX
Relocated External Interrupt n input
External Bus Interface Lower Byte select strobe output
Input pins for specifying the operating mode.
Non-Maskable Interrupt input
MDn
NMI
External Interrupt
External Interrupt
OCU
NMI_R
OUTn
Relocated Non-Maskable Interrupt input
Output Compare Unit n waveform output
FME-MB96340 rev 10
11
MB96340 Series
Pin Function description (2 of 2)
Pin name
Feature
Description
Pxx_n
PPGn
RDX
GPIO
PPG
General purpose IO
Programmable Pulse Generator n output
External bus interface read strobe output
External bus interface external wait state request input
Reset input
External bus
External bus
Core
RDY
RSTX
RXn
CAN
CAN interface n RX input
SCKn
SCKn_R
SCLn
SDAn
SINn
USART
USART
I2C
USART n serial clock input/output
Relocated USART n serial clock input/output
I2C interface n clock I/O input/output
I2C interface n serial data I/O input/output
USART n serial data input
I2C
USART
USART
USART
USART
Reload Timer
Reload Timer
PPG
SINn_R
SOTn
SOTn_R
TINn
Relocated USART n serial data input
USART n serial data output
Relocated USART n serial data output
Reload Timer n event input
TOTn
TTGn
TXn
Reload Timer n output
Programmable Pulse Generator n trigger input
CAN interface n TX output
CAN
UBX
External bus
Supply
External Bus Interface Upper Byte select strobe output
Power supply
VCC
VSS
Supply
Power supply
WOT
RTC
Real Timer clock output
WRHX
WRLX/WRX
X0
External bus
External bus
Clock
External bus High byte write strobe output
External bus Low byte / Word write strobe output
Oscillator input
X0A
Clock
Subclock Oscillator input (only for devices with suffix "W")
Oscillator output
X1
Clock
X1A
Clock
Subclock Oscillator output (only for devices with suffix "W")
12
FME-MB96340 rev 10
MB96340 Series
■ PIN CIRCUIT TYPE
Pin circuit types
FPT-100P-M20
FPT-100P-M22
Circuit
Pin no.
Circuit
type *1
Pin no.
type *1
1-10
11,12
11,12
13,14
15
H
1-12
13, 14
13, 14
15,16
17
H
B *2
B *2
H *3
H *3
Supply
Supply
F
F
16,17
18-21
22-29
30
H
18,19
20-23
24-31
32
H
N
N
I
I
Supply
Supply
31-32
33
G
33-34
35
G
Supply
Supply
34 to 41
42
I
36 to 43
44
I
Supply
Supply
43 to 48
49 to 51
52
I
45 to 50
51 to 53
54
I
C
C
E
E
53 to 54
55 to 62
63, 64
65 to 87
88,89
90, 91
92-100
I
55 to 56
57 to 64
65, 66
67 to 89
90, 91
92, 93
94 to 100
I
H
Supply
H
H
Supply
H
Supply
A
Supply
A
H
H
*1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types
*2: Devices with suffix ”W”
*3: Devices without suffix ”W”
FME-MB96340 rev 10
13
MB96340 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
High-speed oscillation circuit:
• Programmable between oscillation mode (ex-
ternal crystal or resonator connected to X0/X1
pins) and Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 MΩ. Feedback resistor is grounded in
the center when the oscillator is disabled or in
FCI mode
X1
R
0
1
Xout
MRFBE
FCI
R
X0
FCI or osc disable
B
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
2 * 5 MΩ. Feedback resistor is grounded in the
center when the oscillator is disabled
Xout
X1A
R
SRFBE
R
X0A
osc disable
C
E
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
R
Hysteresis
inputs
CMOS input pin
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
Hysteresis
inputs
14
FME-MB96340 rev 10
MB96340 Series
Type
Circuit
Remarks
F
• Power supply input protection circuit
G
• A/D converter ref+ (AVRH/AVRH2) power sup-
ply input pin with protection circuit
ANE
AVR
• Flash devices do not have a protection circuit
against VCC for pins AVRH/AVRH2
• Devices without AVRH reference switch do not
have an analog switch for the AVRL pin
ANE
H
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function *
• Automotive input with input shutdown function
• TTL input with input shutdown function *
• Programmable pull-up resistor: 50kΩ approx.
pull-up control
Pout
Nout
R
Note: MB96F345Dyy or MB96F345Fyy:
Only Automotive input and CMOS hyster-
esis input (0.7/0.3) are supported
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
FME-MB96340 rev 10
15
MB96340 Series
Type
Circuit
Remarks
I
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function *
Pull-up control
Pout
Nout
• Automotive input with input shutdown function
• TTL input with input shutdown function *
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
R
Note: MB96F345Dyy or MB96F345Fyy:
Only Automotive input and CMOS hyster-
esis input (0.7/0.3) are supported
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Automotive input
Standby control
for input shutdown
Standby control
for input shutdown
TTL input
Standby control
for input shutdown
Analog input
N
• CMOS level output (IOL = 3mA, IOH = -3mA)
• 2 different CMOS hysteresis inputs with input
shutdown function *
• Automotive input with input shutdown function
• TTL input with input shutdown function *
• Programmable pull-up resistor: 50kΩ approx.
pull-up control
Pout
Nout*1
*1: N-channel transistor has slew rate control ac-
cording to I2C spec, irrespective of usage
R
Hysteresis input
Standby control
for input shutdown
Note: MB96F345Dyy or MB96F345Fyy:
Only Automotive input and CMOS hyster-
esis input (0.7/0.3) are supported
Standby control
for input shutdown
Hysteresis input
Automotive input
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
16
FME-MB96340 rev 10
MB96340 Series
■ MEMORY MAP
MB96V300B
MB96(F)34x
FF:FFFFH
DE:0000H
USER ROM /
Emulation ROM
*4
External Bus
External Bus
External Bus
10:0000H
0F:E000H
Boot-ROM
Reserved
Boot-ROM
Reserved
0F:0000H
0C:0000H
DATA FLASH /
0E:0000H
02:0000H
*4
Reserved
External RAM
Reserved
Reserved
Internal RAM
RAMEND1*2
RAMSTART12
Internal RAM
bank 1
RAM availability de-
pending on the device
bank 1
01:0000H
00:8000H
Reserved
ROM/RAM MIRROR
ROM/RAM MIRROR
Internal RAM
bank 0
RAMSTART0*2
Internal RAM
bank 0
Reserved
External Bus end
*2
address
RAMSTART0*3
00:0C00H
External Bus
External Bus
Peripherals
Peripherals
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
GPR*1
DMA
GPR*1
DMA
External Bus
Peripheral
External Bus
Peripheral
*1: Unused GPR banks can be used as RAM area
*2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area or DATA FLASH area, see the ■ USER ROM MEMORY MAP FOR
FLASH DEVICES and ■ USER ROM MEMORY MAP FOR MASK ROM DEVICES on the following pages.
The External Bus area and DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
FME-MB96340 rev 10
17
MB96340 Series
■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES
Bank 0
Bank 1 External Bus
Devices
RAMSTART0 RAMSTART1 RAMEND1
RAM size RAM size end address
MB96(F)345
8KByte
16KByte
24KByte
-
-
-
00:21FFH
00:21FFH
00:21FFH
00:6240H
00:4240H
00:2240H
-
-
-
-
-
-
MB96(F)346,
MB96F347
MB96F348
18
FME-MB96340 rev 10
MB96340 Series
■ USER ROM MEMORY MAP FOR FLASH DEVICES
MB96F345D
MB96F345F
Flash size 160kByte
+64KByte Data Flash
Alternative mode Flash memory
CPU address
mode address
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
S39 - 64K
S38 - 64K
Flash A
External bus
E0:0000H
DF:FFFFH
Reserved
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
Flash A
Reserved
DE:0000H
0E:FFFFH
0E:FF00H
0E:FEFFH
0E:0000H
0D:FFFFH
0D:C000H
0D:BFFFH
0D:8000H
0D:7FFFH
0D:4000H
0D:3FFFH
0D:0000H
0C:FFFFH
0C:0000H
(0E:FFFFH)
(0E:FF00H)
SDA0-256 *2
Reserved
SDA4-16K
SDA3-16K
SDA2-16K
SDA1-16K
Reserved
Data Flash A
Data Flash A
(0F:FFFFH)
(0F:C000H)
(0F:BFFFH)
(0F:8000H)
(0F:7FFFH)
(0F:4000H)
(0F:3FFFH)
(0F:0000H)
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
*2: Sector SDA0 contains the ROM Configuration Block RCBDA at CPU address DE:FF00H - DE:FF2FH
FME-MB96340 rev 10
19
MB96340 Series
MB96F346Y
MB96F346R
MB96F346A
MB96F347Y
MB96F347R
MB96F347A
Flash size
288kByte
Flash size
416kByte
Alternative mode Flash memory
CPU address
mode address
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
Flash A
External bus
External bus
E0:0000H
DF:FFFFH
Reserved
Reserved
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
Flash A
Reserved
Reserved
DE:0000H
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
20
FME-MB96340 rev 10
MB96340 Series
MB96F348Y
MB96F348R
MB96F348A
MB96F348T
MB96F348H
MB96F348C
Flash size
544kByte
Flash size
576kByte
Alternative mode Flash memory
CPU address
mode address
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
S33 - 64K
S32 - 64K
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
S33 - 64K
S32 - 64K
Flash A
External bus
External bus
Reserved
E0:0000H
DF:FFFFH
Reserved
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
Flash A
Reserved
DE:8000H
DE:7FFFH
DE:6000H
DE:5FFFH
DE:4000H
DE:3FFFH
DE:2000H
DE:1FFFH
DE:0000H
1E:7FFFH
1E:6000H
1E:5FFFH
1E:4000H
1E:3FFFH
1E:2000H
1E:1FFFH
1E:0000H
SB3 - 8K
SB2 - 8K
SB1 - 8K
SB0 - 8K *2
Reserved
Flash B
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
*2: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000H - DE:002FH
FME-MB96340 rev 10
21
MB96340 Series
■ USER ROM MEMORY MAP FOR MASK ROM DEVICES
MB96345
MB96346
ROM size
160kByte
ROM size
288kByte
CPU address
FF:FFFFH
FF:0000H
FE:FFFFH
128K ROM
FE:0000H
FD:FFFFH
256K ROM
FD:0000H
FC:FFFFH
Reserved
FC:0000H
FB:FFFFH
External bus
External bus
E0:0000H
DF:FFFFH
Reserved
32K ROM
Reserved
32K ROM
DF:8000H
DF:7FFFH
DF:0080H
DF:007FH
DF:0000H
ROM configuration
block RCB
ROM configuration
block RCB
DE:FFFFH
Reserved
Reserved
DE:0000H
22
FME-MB96340 rev 10
MB96340 Series
■ SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010, Serial Communication mode)
MB96F34x
Pin number
LQFP-100
Pin number
QFP-100
Normal function
USART Number
USART0
57
58
59
60
61
62
22
23
24
85
86
87
59
60
61
62
63
64
24
25
26
87
88
89
SIN0
SOT0
SCK0
SIN1
USART1
USART2
USART3
SOT1
SCK1
SIN2
SOT2
SCK2
SIN3
SOT3
SCK3
Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor
to support at least port P00_1 on pin 76/78.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the
customer to check the tool manual or to contact the tool vendor for alternative handshaking pins.
FME-MB96340 rev 10
23
MB96340 Series
■ I/O MAP
I/O map MB96(F)34x (1 of 30)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
Access
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
I/O Port P00 - Port Data Register
I/O Port P01 - Port Data Register
I/O Port P02 - Port Data Register
I/O Port P03 - Port Data Register
I/O Port P04 - Port Data Register
I/O Port P05 - Port Data Register
I/O Port P06 - Port Data Register
I/O Port P07 - Port Data Register
I/O Port P08 - Port Data Register
I/O Port P09 - Port Data Register
I/O Port P10 - Port Data Register
PDR00
PDR01
PDR02
PDR03
PDR04
PDR05
PDR06
PDR07
PDR08
PDR09
PDR10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000BH-
000017H
Reserved
-
000018H
000019H
00001AH
00001BH
00001CH
00001DH
00001EH
00001FH
000020H
000021H
ADC0 - Control Status register Low
ADC0 - Control Status register High
ADC0 - Data Register Low
ADCSL
ADCSH
ADCRL
ADCRH
ADCS
ADCR
ADSR
R/W
R/W
R
ADC0 - Data Register High
R
ADC0 - Setting Register
R/W
R/W
R/W
-
ADC0 - Setting Register
ADC0 - Extended Configuration Register
Reserved
ADECR
FRT0 - Data register of free-running timer
FRT0 - Data register of free-running timer
TCDT0
TCCS0
R/W
R/W
FRT0 - Control status register of free-running timer
Low
000022H
000023H
TCCSL0
TCCSH0
R/W
R/W
FRT0 - Control status register of free-running timer
High
000024H
000025H
FRT1 - Data register of free-running timer
FRT1 - Data register of free-running timer
TCDT1
R/W
R/W
24
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (2 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
R/W
FRT1 - Control status register of free-running timer
Low
000026H
000027H
TCCSL1
TCCSH1
TCCS1
FRT1 - Control status register of free-running timer
High
R/W
000028H
000029H
00002AH
00002BH
00002CH
00002DH
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
00003EH
00003FH
000040H
000041H
000042H
OCU0 - Output Compare Control Status
OCU1 - Output Compare Control Status
OCU0 - Compare Register
OCS0
OCS1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
OCCP0
OCCP1
OCU0 - Compare Register
OCU1 - Compare Register
OCU1 - Compare Register
OCU2 - Output Compare Control Status
OCU3 - Output Compare Control Status
OCU2 - Compare Register
OCS2
OCS3
OCCP2
OCCP3
OCU2 - Compare Register
OCU3 - Compare Register
OCU3 - Compare Register
OCU4 - Output Compare Control Status
OCU5 - Output Compare Control Status
OCU4 - Compare Register
OCS4
OCS5
OCCP4
OCCP5
OCU4 - Compare Register
OCU5 - Compare Register
OCU5 - Compare Register
OCU6 - Output Compare Control Status
OCU7 - Output Compare Control Status
OCU6 - Compare Register
OCS6
OCS7
OCCP6
OCCP7
OCU6 - Compare Register
OCU7 - Compare Register
OCU7 - Compare Register
ICU0/ICU1 - Control Status Register
ICU0/ICU1 - Edge register
ICS01
ICE01
ICU0 - Capture Register Low
IPCPL0
IPCP0
FME-MB96340 rev 10
25
MB96340 Series
I/O map MB96(F)34x (3 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000043H
000044H
000045H
000046H
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
000058H
ICU0 - Capture Register High
ICU1 - Capture Register Low
ICU1 - Capture Register High
ICU2/ICU3 - Control Status Register
ICU2/ICU3 - Edge register
IPCPH0
IPCPL1
IPCPH1
ICS23
R
R
IPCP1
R
R/W
R/W
R
ICE23
ICU2 - Capture Register Low
ICU2 - Capture Register High
ICU3 - Capture Register Low
ICU3 - Capture Register High
ICU4/ICU5 - Control Status Register
ICU4/ICU5 - Edge register
IPCPL2
IPCPH2
IPCPL3
IPCPH3
ICS45
IPCP2
IPCP3
R
R
R
R/W
R/W
R
ICE45
ICU4 - Capture Register Low
ICU4 - Capture Register High
ICU5 - Capture Register Low
ICU5 - Capture Register High
ICU6/ICU7 - Control Status Register
ICU6/ICU7 - Edge register
IPCPL4
IPCPH4
IPCPL5
IPCPH5
ICS67
IPCP4
IPCP5
R
R
R
R/W
R/W
R
ICE67
ICU6 - Capture Register Low
ICU6 - Capture Register High
ICU7 - Capture Register Low
ICU7 - Capture Register High
EXTINT0 - External Interrupt Enable Register
IPCPL6
IPCPH6
IPCPL7
IPCPH7
ENIR0
IPCP6
IPCP7
R
R
R
R/W
EXTINT0 - External Interrupt Interrupt request
Register
000059H
EIRR0
R/W
00005AH
00005BH
00005CH
EXTINT0 - External Interrupt Level Select Low
EXTINT0 - External Interrupt Level Select High
EXTINT1 - External Interrupt Enable Register
ELVRL0
ELVRH0
ENIR1
ELVR0
ELVR1
R/W
R/W
R/W
EXTINT1 - External Interrupt Interrupt request
Register
00005DH
EIRR1
R/W
00005EH
00005FH
EXTINT1 - External Interrupt Level Select Low
EXTINT1 - External Interrupt Level Select High
ELVRL1
ELVRH1
R/W
R/W
26
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (4 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000060H
000061H
000062H
000062H
000063H
000063H
000064H
000065H
000066H
000066H
000067H
000067H
000068H
000069H
00006AH
00006AH
00006BH
00006BH
00006CH
00006DH
00006EH
00006EH
00006FH
00006FH
RLT0 - Timer Control Status Register Low
RLT0 - Timer Control Status Register High
RLT0 - Reload Register - for writing
RLT0 - Reload Register - for reading
RLT0 - Reload Register - for writing
RLT0 - Reload Register - for reading
RLT1 - Timer Control Status Register Low
RLT1 - Timer Control Status Register High
RLT1 - Reload Register - for writing
RLT1 - Reload Register - for reading
RLT1 - Reload Register - for writing
RLT1 - Reload Register - for reading
RLT2 - Timer Control Status Register Low
RLT2 - Timer Control Status Register High
RLT2 - Reload Register - for writing
RLT2 - Reload Register - for reading
RLT2 - Reload Register - for writing
RLT2 - Reload Register - for reading
RLT3 - Timer Control Status Register Low
RLT3 - Timer Control Status Register High
RLT3 - Reload Register - for writing
RLT3 - Reload Register - for reading
RLT3 - Reload Register - for writing
RLT3 - Reload Register - for reading
TMCSRL0
TMCSRH0
TMCSR0
R/W
R/W
W
TMRLR0
TMR0
R
W
R
TMCSRL1
TMCSRH1
TMCSR1
R/W
R/W
W
TMRLR1
TMR1
R
W
R
TMCSRL2
TMCSRH2
TMCSR2
R/W
R/W
W
TMRLR2
TMR2
R
W
R
TMCSRL3
TMCSRH3
TMCSR3
R/W
R/W
W
TMRLR3
TMR3
R
W
R
RLT6 - Timer Control Status Register Low (dedic.
RLT for PPG)
000070H
000071H
000072H
TMCSRL6
TMCSRH6
TMCSR6
TMRLR6
R/W
R/W
W
RLT6 - Timer Control Status Register High (dedic.
RLT for PPG)
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
FME-MB96340 rev 10
27
MB96340 Series
I/O map MB96(F)34x (5 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
000072H
000073H
000073H
TMR6
R
W
R
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
PPG3-PPG0 - General Control register 1 Low
PPG3-PPG0 - General Control register 1 High
PPG3-PPG0 - General Control register 2 Low
PPG3-PPG0 - General Control register 2 High
PPG0 - Timer register
GCN1L0
GCN1H0
GCN2L0
GCN2H0
GCN10
GCN20
PTMR0
PCSR0
PDUT0
PCN0
R/W
R/W
R/W
R/W
R
PPG0 - Timer register
R
PPG0 - Period setting register
PPG0 - Period setting register
PPG0 - Duty cycle register
W
W
W
PPG0 - Duty cycle register
W
PPG0 - Control status register Low
PPG0 - Control status register High
PPG1 - Timer register
PCNL0
PCNH0
R/W
R/W
R
PTMR1
PCSR1
PDUT1
PCN1
PPG1 - Timer register
R
PPG1 - Period setting register
PPG1 - Period setting register
PPG1 - Duty cycle register
W
W
W
PPG1 - Duty cycle register
W
PPG1 - Control status register Low
PPG1 - Control status register High
PPG2 - Timer register
PCNL1
PCNH1
R/W
R/W
R
PTMR2
PCSR2
PDUT2
PPG2 - Timer register
R
PPG2 - Period setting register
PPG2 - Period setting register
PPG2 - Duty cycle register
W
W
W
28
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (6 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00008DH
00008EH
00008FH
000090H
000091H
000092H
000093H
000094H
000095H
000096H
000097H
000098H
000099H
00009AH
00009BH
00009CH
00009DH
00009EH
00009FH
0000A0H
0000A1H
0000A2H
0000A3H
0000A4H
0000A5H
0000A6H
0000A7H
0000A8H
0000A9H
0000AAH
PPG2 - Duty cycle register
W
R/W
R/W
R
PPG2 - Control status register Low
PPG2 - Control status register High
PPG3 - Timer register
PCNL2
PCNH2
PCN2
PTMR3
PCSR3
PDUT3
PCN3
PPG3 - Timer register
R
PPG3 - Period setting register
PPG3 - Period setting register
PPG3 - Duty cycle register
W
W
W
PPG3 - Duty cycle register
W
PPG3 - Control status register Low
PPG3 - Control status register High
PPG7-PPG4 - General Control register 1 Low
PPG7-PPG4 - General Control register 1 High
PPG7-PPG4 - General Control register 2 Low
PPG7-PPG4 - General Control register 2 High
PPG4 - Timer register
PCNL3
PCNH3
R/W
R/W
R/W
R/W
R/W
R/W
R
GCN1L1
GCN1H1
GCN2L1
GCN2H1
GCN11
GCN21
PTMR4
PCSR4
PDUT4
PCN4
PPG4 - Timer register
R
PPG4 - Period setting register
PPG4 - Period setting register
PPG4 - Duty cycle register
W
W
W
PPG4 - Duty cycle register
W
PPG4 - Control status register Low
PPG4 - Control status register High
PPG5 - Timer register
PCNL4
PCNH4
R/W
R/W
R
PTMR5
PCSR5
PDUT5
PCN5
PPG5 - Timer register
R
PPG5 - Period setting register
PPG5 - Period setting register
PPG5 - Duty cycle register
W
W
W
PPG5 - Duty cycle register
W
PPG5 - Control status register Low
PCNL5
R/W
FME-MB96340 rev 10
29
MB96340 Series
I/O map MB96(F)34x (7 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0000ABH
0000ACH
0000ADH
0000AEH
0000AFH
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
0000C0H
0000C1H
0000C2H
0000C2H
0000C3H
0000C4H
0000C5H
0000C6H
0000C7H
PPG5 - Control status register High
I2C0 - Bus Status Register
PCNH5
IBSR0
IBCR0
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
R/W
R
I2C0 - Bus Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
I2C0 - Ten bit Slave address Register Low
I2C0 - Ten bit Slave address Register High
I2C0 - Ten bit Address mask Register Low
I2C0 - Ten bit Address mask Register High
I2C0 - Seven bit Slave address Register
I2C0 - Seven bit Address mask Register
I2C0 - Data Register
ITBA0
ITMK0
ISMK0
IDAR0
ICCR0
IBSR1
IBCR1
ITBAL1
ITBAH1
ITMKL1
ITMKH1
ISBA1
I2C0 - Clock Control Register
I2C1 - Bus Status Register
I2C1 - Bus Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
I2C1 - Ten bit Slave address Register Low
I2C1 - Ten bit Slave address Register High
I2C1 - Ten bit Address mask Register Low
I2C1 - Ten bit Address mask Register High
I2C1 - Seven bit Slave address Register
I2C1 - Seven bit Address mask Register
I2C1 - Data Register
ITBA1
ITMK1
ISMK1
IDAR1
ICCR1
SMR0
I2C1 - Clock Control Register
USART0 - Serial Mode Register
USART0 - Serial Control Register
USART0 - TX Register
SCR0
TDR0
USART0 - RX Register
RDR0
R
USART0 - Serial Status
SSR0
R/W
R/W
R/W
R/W
R/W
USART0 - Control/Com. Register
USART0 - Ext. Status Register
ECCR0
ESCR0
BGRL0
BGRH0
USART0 - Baud Rate Generator Register Low
USART0 - Baud Rate Generator Register High
BGR0
30
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (8 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0000C8H
0000C9H
0000CAH
0000CBH
0000CCH
0000CCH
0000CDH
0000CEH
0000CFH
0000D0H
0000D1H
0000D2H
0000D3H
0000D4H
0000D5H
0000D6H
0000D6H
0000D7H
0000D8H
0000D9H
0000DAH
0000DBH
0000DCH
0000DDH
0000DEH
0000DFH
0000E0H
0000E0H
0000E1H
0000E2H
USART0 - Extended Serial Interrupt Register
Reserved
ESIR0
R/W
-
USART1 - Serial Mode Register
USART1 - Serial Control Register
USART1 - TX Register
SMR1
SCR1
R/W
R/W
W
TDR1
USART1 - RX Register
RDR1
R
USART1 - Serial Status
SSR1
R/W
R/W
R/W
R/W
R/W
R/W
-
USART1 - Control/Com. Register
USART1 - Ext. Status Register
USART1 - Baud Rate Generator Register Low
USART1 - Baud Rate Generator Register High
USART1 - Extended Serial Interrupt Register
Reserved
ECCR1
ESCR1
BGRL1
BGRH1
ESIR1
BGR1
USART2 - Serial Mode Register
USART2 - Serial Control Register
USART2 - TX Register
SMR2
SCR2
R/W
R/W
W
TDR2
USART2 - RX Register
RDR2
R
USART2 - Serial Status
SSR2
R/W
R/W
R/W
R/W
R/W
R/W
-
USART2 - Control/Com. Register
USART2 - Ext. Status Register
USART2 - Baud Rate Generator Register Low
USART2 - Baud Rate Generator Register High
USART2 - Extended Serial Interrupt Register
Reserved
ECCR2
ESCR2
BGRL2
BGRH2
ESIR2
BGR2
USART3 - Serial Mode Register
USART3 - Serial Control Register
USART3 - TX Register
SMR3
SCR3
TDR3
RDR3
SSR3
ECCR3
R/W
R/W
W
USART3 - RX Register
R
USART3 - Serial Status
R/W
R/W
USART3 - Control/Com. Register
FME-MB96340 rev 10
31
MB96340 Series
I/O map MB96(F)34x (9 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0000E3H
0000E4H
0000E5H
0000E6H
USART3 - Ext. Status Register
ESCR3
BGRL3
BGRH3
ESIR3
R/W
R/W
R/W
R/W
USART3 - Baud Rate Generator Register Low
USART3 - Baud Rate Generator Register High
USART3 - Extended Serial Interrupt Register
BGR3
0000E7H-
0000EFH
Reserved
-
0000F0H-
0000FFH
External Bus area
EXTBUS0
R/W
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000108H
000109H
00010AH
00010BH
00010CH
00010DH
00010EH
00010FH
000110H
000111H
000112H
000113H
000114H
000115H
000116H
DMA0 - Buffer address pointer low byte
DMA0 - Buffer address pointer middle byte
DMA0 - Buffer address pointer high byte
DMA0 - DMA control register
BAPL0
BAPM0
BAPH0
DMACS0
IOAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA0 - I/O register address pointer low byte
DMA0 - I/O register address pointer high byte
DMA0 - Data counter low byte
IOA0
IOAH0
DCTL0
DCTH0
BAPL1
BAPM1
BAPH1
DMACS1
IOAL1
DCT0
DMA0 - Data counter high byte
DMA1 - Buffer address pointer low byte
DMA1 - Buffer address pointer middle byte
DMA1 - Buffer address pointer high byte
DMA1 - DMA control register
DMA1 - I/O register address pointer low byte
DMA1 - I/O register address pointer high byte
DMA1 - Data counter low byte
IOA1
IOAH1
DCTL1
DCTH1
BAPL2
BAPM2
BAPH2
DMACS2
IOAL2
DCT1
DMA1 - Data counter high byte
DMA2 - Buffer address pointer low byte
DMA2 - Buffer address pointer middle byte
DMA2 - Buffer address pointer high byte
DMA2 - DMA control register
DMA2 - I/O register address pointer low byte
DMA2 - I/O register address pointer high byte
DMA2 - Data counter low byte
IOA2
IOAH2
DCTL2
DCT2
32
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (10 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000117H
000118H
000119H
00011AH
00011BH
00011CH
00011DH
00011EH
00011FH
000120H
000121H
000122H
000123H
000124H
000125H
000126H
000127H
000128H
000129H
00012AH
00012BH
00012CH
00012DH
00012EH
00012FH
DMA2 - Data counter high byte
DCTH2
BAPL3
BAPM3
BAPH3
DMACS3
IOAL3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA3 - Buffer address pointer low byte
DMA3 - Buffer address pointer middle byte
DMA3 - Buffer address pointer high byte
DMA3 - DMA control register
DMA3 - I/O register address pointer low byte
DMA3 - I/O register address pointer high byte
DMA3 - Data counter low byte
IOA3
IOAH3
DCTL3
DCTH3
BAPL4
BAPM4
BAPH4
DMACS4
IOAL4
DCT3
DMA3 - Data counter high byte
DMA4 - Buffer address pointer low byte
DMA4 - Buffer address pointer middle byte
DMA4 - Buffer address pointer high byte
DMA4 - DMA control register
DMA4 - I/O register address pointer low byte
DMA4 - I/O register address pointer high byte
DMA4 - Data counter low byte
IOA4
IOAH4
DCTL4
DCTH4
BAPL5
BAPM5
BAPH5
DMACS5
IOAL5
DCT4
DMA4 - Data counter high byte
DMA5 - Buffer address pointer low byte
DMA5 - Buffer address pointer middle byte
DMA5 - Buffer address pointer high byte
DMA5 - DMA control register
DMA5 - I/O register address pointer low byte
DMA5 - I/O register address pointer high byte
DMA5 - Data counter low byte
IOA5
IOAH5
DCTL5
DCTH5
DCT5
DMA5 - Data counter high byte
000130H-
00017FH
Reserved
-
000180H-
00037FH
CPU - General Purpose registers (RAM access)
GPR_RAM
R/W
000380H
000381H
DMA0 - Interrupt select
DMA1 - Interrupt select
DISEL0
DISEL1
R/W
R/W
FME-MB96340 rev 10
33
MB96340 Series
I/O map MB96(F)34x (11 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000382H
000383H
000384H
000385H
DMA2 - Interrupt select
DISEL2
DISEL3
DISEL4
DISEL5
R/W
R/W
R/W
R/W
DMA3 - Interrupt select
DMA4 - Interrupt select
DMA5 - Interrupt select
000386H-
00038FH
Reserved
-
000390H
000391H
000392H
000393H
000394H
000395H
DMA - Status register low byte
DMA - Status register high byte
DMA - Stop status register low byte
DMA - Stop status register high byte
DMA - Enable register low byte
DMA - Enable register high byte
DSRL
DSRH
DSSRL
DSSRH
DERL
DSR
DSSR
DER
R/W
R/W
R/W
R/W
R/W
R/W
DERH
000396H-
00039FH
Reserved
-
0003A0H
0003A1H
0003A2H
0003A3H
0003A4H
0003A5H
Interrupt level register
ILR
IDX
ICR
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt index register
Interrupt vector table base register Low
Interrupt vector table base register High
Delayed Interrupt register
TBRL
TBRH
DIRR
NMI
TBR
Non Maskable Interrupt register
0003A6H-
0003ABH
Reserved
-
0003ACH
0003ADH
0003AEH
0003AFH
0003B0H
0003B1H
0003B2H
0003B3H
0003B4H
EDSU communication interrupt selection Low
EDSU communication interrupt selection High
ROM mirror control register
EDSU2L
EDSU2H
ROMM
EDSU2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EDSU configuration register
EDSU
Memory patch control/status register ch 0/1
Memory patch control/status register ch 0/1
Memory patch control/status register ch 2/3
Memory patch control/status register ch 2/3
Memory patch control/status register ch 4/5
PFCS0
PFCS1
PFCS2
34
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (12 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003B5H
0003B6H
0003B7H
0003B8H
0003B9H
0003BAH
0003BBH
0003BCH
0003BDH
0003BEH
0003BFH
0003C0H
0003C1H
0003C2H
0003C3H
0003C4H
0003C5H
0003C6H
0003C7H
0003C8H
0003C9H
0003CAH
0003CBH
0003CCH
0003CDH
0003CEH
0003CFH
0003D0H
0003D1H
0003D2H
Memory patch control/status register ch 4/5
Memory patch control/status register ch 6/7
Memory patch control/status register ch 6/7
Memory Patch function - Patch address 0 low
Memory Patch function - Patch address 0 middle
Memory Patch function - Patch address 0 high
Memory Patch function - Patch address 1 low
Memory Patch function - Patch address 1 middle
Memory Patch function - Patch address 1 high
Memory Patch function - Patch address 2 low
Memory Patch function - Patch address 2 middle
Memory Patch function - Patch address 2 high
Memory Patch function - Patch address 3 low
Memory Patch function - Patch address 3 middle
Memory Patch function - Patch address 3 high
Memory Patch function - Patch address 4 low
Memory Patch function - Patch address 4 middle
Memory Patch function - Patch address 4 high
Memory Patch function - Patch address 5 low
Memory Patch function - Patch address 5 middle
Memory Patch function - Patch address 5 high
Memory Patch function - Patch address 6 low
Memory Patch function - Patch address 6 middle
Memory Patch function - Patch address 6 high
Memory Patch function - Patch address 7 low
Memory Patch function - Patch address 7 middle
Memory Patch function - Patch address 7 high
Memory Patch function - Patch data 0 Low
Memory Patch function - Patch data 0 High
Memory Patch function - Patch data 1 Low
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFCS3
PFAL0
PFAM0
PFAH0
PFAL1
PFAM1
PFAH1
PFAL2
PFAM2
PFAH2
PFAL3
PFAM3
PFAH3
PFAL4
PFAM4
PFAH4
PFAL5
PFAM5
PFAH5
PFAL6
PFAM6
PFAH6
PFAL7
PFAM7
PFAH7
PFDL0
PFDH0
PFDL1
PFD0
PFD1
FME-MB96340 rev 10
35
MB96340 Series
I/O map MB96(F)34x (13 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003D3H
0003D4H
0003D5H
0003D6H
0003D7H
0003D8H
0003D9H
0003DAH
0003DBH
0003DCH
0003DDH
0003DEH
0003DFH
0003E0H
Memory Patch function - Patch data 1 High
Memory Patch function - Patch data 2 Low
Memory Patch function - Patch data 2 High
Memory Patch function - Patch data 3 Low
Memory Patch function - Patch data 3 High
Memory Patch function - Patch data 4 Low
Memory Patch function - Patch data 4 High
Memory Patch function - Patch data 5 Low
Memory Patch function - Patch data 5 High
Memory Patch function - Patch data 6 Low
Memory Patch function - Patch data 6 High
Memory Patch function - Patch data 7 Low
Memory Patch function - Patch data 7 High
Data Flash Control and Status register A
PFDH1
PFDL2
PFDH2
PFDL3
PFDH3
PFDL4
PFDH4
PFDL5
PFDH5
PFDL6
PFDH6
PFDL7
PFDH7
DFCSA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFD2
PFD3
PFD4
PFD5
PFD6
PFD7
Data Flash Write command sequencer Control
register A
0003E1H
0003E2H
DFWCA
DFWSA
R/W
R/W
-
Data Flash Write command sequencer Status reg-
ister A
0003E3H-
0003F0H
Reserved
0003F1H
0003F2H
0003F3H
0003F4H
0003F5H
0003F6H
0003F7H
0003F8H
0003F9H
0003FAH
0003FBH
Memory Control Status Register A
Memory Timing Configuration Register A Low
Memory Timing Configuration Register A High
Reserved
MCSRA
MTCRAL
MTCRAH
R/W
R/W
R/W
-
MTCRA
MTCRB
Memory Control Status Register B
Memory Timing Configuration Register B Low
Memory Timing Configuration Register B High
Flash Memory Write Control register 0
Flash Memory Write Control register 1
Flash Memory Write Control register 2
Flash Memory Write Control register 3
MCSRB
MTCRBL
MTCRBH
FMWC0
FMWC1
FMWC2
FMWC3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
36
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (14 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0003FCH
0003FDH
Flash Memory Write Control register 4
Flash Memory Write Control register 5
FMWC4
FMWC5
R/W
R/W
0003FEH-
0003FFH
Reserved
-
000400H
000401H
000402H
000403H
000404H
000405H
000406H
000407H
000408H
000409H
00040AH
Standby Mode control register
Clock select register
SMCR
CKSR
R/W
R/W
R/W
R
Clock Stabilization select register
Clock monitor register
CKSSR
CKMR
Clock Frequency control register Low
Clock Frequency control register High
PLL Control register Low
CKFCRL
CKFCRH
PLLCRL
PLLCRH
RCTCR
MCTCR
SCTCR
CKFCR
PLLCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PLL Control register High
RC clock timer control register
Main clock timer control register
Sub clock timer control register
Reset cause and clock status register with clear
function
00040BH
RCCSRC
R
00040CH
00040DH
00040EH
00040FH
Reset configuration register
RCR
R/W
R
Reset cause and clock status register
Watch dog timer configuration register
Watch dog timer clear pattern register
RCCSR
WDTC
WDTCP
R/W
W
000410H-
000414H
Reserved
-
000415H
000416H
000417H
000418H
000419H
00041AH
00041BH
Clock output activation register
Clock output configuration register 0
Clock output configuration register 1
Clock Modulator control register
Reserved
COAR
COCR0
COCR1
CMCR
R/W
R/W
R/W
R/W
-
Clock Modulator Parameter register Low
Clock Modulator Parameter register High
CMPRL
CMPRH
CMPR
R/W
R/W
FME-MB96340 rev 10
37
MB96340 Series
I/O map MB96(F)34x (15 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00041CH-
Reserved
00042BH
-
00042CH
00042DH
Voltage Regulator Control register
VRCR
CILCR
R/W
R/W
Clock Input and LVD Control Register
00042EH-
00042FH
Reserved
-
000430H
000431H
000432H
000433H
000434H
000435H
000436H
000437H
000438H
000439H
00043AH
I/O Port P00 - Data Direction Register
I/O Port P01 - Data Direction Register
I/O Port P02 - Data Direction Register
I/O Port P03 - Data Direction Register
I/O Port P04 - Data Direction Register
I/O Port P05 - Data Direction Register
I/O Port P06 - Data Direction Register
I/O Port P07 - Data Direction Register
I/O Port P08 - Data Direction Register
I/O Port P09 - Data Direction Register
I/O Port P10 - Data Direction Register
DDR00
DDR01
DDR02
DDR03
DDR04
DDR05
DDR06
DDR07
DDR08
DDR09
DDR10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00043BH-
000443H
Reserved
-
000444H
000445H
000446H
000447H
000448H
000449H
00044AH
00044BH
00044CH
00044DH
00044EH
I/O Port P00 - Port Input Enable Register
I/O Port P01 - Port Input Enable Register
I/O Port P02 - Port Input Enable Register
I/O Port P03 - Port Input Enable Register
I/O Port P04 - Port Input Enable Register
I/O Port P05 - Port Input Enable Register
I/O Port P06 - Port Input Enable Register
I/O Port P07 - Port Input Enable Register
I/O Port P08 - Port Input Enable Register
I/O Port P09 - Port Input Enable Register
I/O Port P10 - Port Input Enable Register
PIER00
PIER01
PIER02
PIER03
PIER04
PIER05
PIER06
PIER07
PIER08
PIER09
PIER10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
38
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (16 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00044FH-
Reserved
000457H
-
000458H
000459H
00045AH
00045BH
00045CH
00045DH
00045EH
00045FH
000460H
000461H
000462H
I/O Port P00 - Port Input Level Register
I/O Port P01 - Port Input Level Register
I/O Port P02 - Port Input Level Register
I/O Port P03 - Port Input Level Register
I/O Port P04 - Port Input Level Register
I/O Port P05 - Port Input Level Register
I/O Port P06 - Port Input Level Register
I/O Port P07 - Port Input Level Register
I/O Port P08 - Port Input Level Register
I/O Port P09 - Port Input Level Register
I/O Port P10 - Port Input Level Register
PILR00
PILR01
PILR02
PILR03
PILR04
PILR05
PILR06
PILR07
PILR08
PILR09
PILR10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000463H-
00046BH
Reserved
-
00046CH
00046DH
00046EH
00046FH
000470H
000471H
000472H
000473H
000474H
000475H
000476H
I/O Port P00 - Extended Port Input Level Register
I/O Port P01 - Extended Port Input Level Register
I/O Port P02 - Extended Port Input Level Register
I/O Port P03 - Extended Port Input Level Register
I/O Port P04 - Extended Port Input Level Register
I/O Port P05 - Extended Port Input Level Register
I/O Port P06 - Extended Port Input Level Register
I/O Port P07 - Extended Port Input Level Register
I/O Port P08 - Extended Port Input Level Register
I/O Port P09 - Extended Port Input Level Register
I/O Port P10 - Extended Port Input Level Register
EPILR00
EPILR01
EPILR02
EPILR03
EPILR04
EPILR05
EPILR06
EPILR07
EPILR08
EPILR09
EPILR10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000477H-
00047FH
Reserved
-
000480H
000481H
000482H
I/O Port P00 - Port Output Drive Register
I/O Port P01 - Port Output Drive Register
I/O Port P02 - Port Output Drive Register
PODR00
PODR01
PODR02
R/W
R/W
R/W
FME-MB96340 rev 10
39
MB96340 Series
I/O map MB96(F)34x (17 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000483H
000484H
000485H
000486H
000487H
000488H
000489H
00048AH
I/O Port P03 - Port Output Drive Register
I/O Port P04 - Port Output Drive Register
I/O Port P05 - Port Output Drive Register
I/O Port P06 - Port Output Drive Register
I/O Port P07 - Port Output Drive Register
I/O Port P08 - Port Output Drive Register
I/O Port P09 - Port Output Drive Register
I/O Port P10 - Port Output Drive Register
PODR03
PODR04
PODR05
PODR06
PODR07
PODR08
PODR09
PODR10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00048BH-
0004A7H
Reserved
-
0004A8H
0004A9H
0004AAH
0004ABH
0004ACH
0004ADH
0004AEH
0004AFH
0004B0H
0004B1H
0004B2H
I/O Port P00 - Pull-Up resistor Control Register
I/O Port P01 - Pull-Up resistor Control Register
I/O Port P02 - Pull-Up resistor Control Register
I/O Port P03 - Pull-Up resistor Control Register
I/O Port P04 - Pull-Up resistor Control Register
I/O Port P05 - Pull-Up resistor Control Register
I/O Port P06 - Pull-Up resistor Control Register
I/O Port P07 - Pull-Up resistor Control Register
I/O Port P08 - Pull-Up resistor Control Register
I/O Port P09 - Pull-Up resistor Control Register
I/O Port P10 - Pull-Up resistor Control Register
PUCR00
PUCR01
PUCR02
PUCR03
PUCR04
PUCR05
PUCR06
PUCR07
PUCR08
PUCR09
PUCR10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0004B3H-
0004BBH
Reserved
-
0004BCH
0004BDH
0004BEH
0004BFH
0004C0H
0004C1H
0004C2H
0004C3H
I/O Port P00 - External Pin State Register
I/O Port P01 - External Pin State Register
I/O Port P02 - External Pin State Register
I/O Port P03 - External Pin State Register
I/O Port P04 - External Pin State Register
I/O Port P05 - External Pin State Register
I/O Port P06 - External Pin State Register
I/O Port P07 - External Pin State Register
EPSR00
EPSR01
EPSR02
EPSR03
EPSR04
EPSR05
EPSR06
EPSR07
R
R
R
R
R
R
R
R
40
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (18 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0004C4H
0004C5H
0004C6H
I/O Port P08 - External Pin State Register
I/O Port P09 - External Pin State Register
I/O Port P10 - External Pin State Register
EPSR08
EPSR09
EPSR10
R
R
R
0004C7H-
0004CFH
Reserved
-
0004D0H
0004D1H
0004D2H
0004D3H
0004D4H
0004D5H
0004D6H
0004D7H
0004D8H
0004D9H
0004DAH
0004DBH
0004DCH
0004DDH
0004DEH
0004DFH
0004E0H
0004E1H
0004E2H
0004E3H
0004E4H
0004E5H
0004E6H
0004E7H
0004E8H
ADC analog input enable register 0
ADC analog input enable register 1
ADC analog input enable register 2
ADC analog input enable register 3
ADC analog input enable register 4
Reserved
ADER0
ADER1
ADER2
ADER3
ADER4
R/W
R/W
R/W
R/W
R/W
-
Peripheral Resource Relocation Register 0
Peripheral Resource Relocation Register 1
Peripheral Resource Relocation Register 2
Peripheral Resource Relocation Register 3
Peripheral Resource Relocation Register 4
Peripheral Resource Relocation Register 5
Peripheral Resource Relocation Register 6
Peripheral Resource Relocation Register 7
Peripheral Resource Relocation Register 8
Peripheral Resource Relocation Register 9
RTC - Sub Second Register L
PRRR0
PRRR1
PRRR2
PRRR3
PRRR4
PRRR5
PRRR6
PRRR7
PRRR8
PRRR9
WTBRL0
WTBRH0
WTBR1
WTSR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTBR0
RTC - Sub Second Register M
RTC - Sub-Second Register H
RTC - Second Register
RTC - Minutes
WTMR
RTC - Hour
WTHR
RTC - Timer Control Extended Register
RTC - Clock select register
WTCER
WTCKSR
WTCRL
RTC - Timer Control Register Low
WTCR
FME-MB96340 rev 10
41
MB96340 Series
I/O map MB96(F)34x (19 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0004E9H
0004EAH
0004EBH
0004ECH
0004EDH
0004EEH
0004EFH
0004F0H
0004F1H
RTC - Timer Control Register High
CAL - Calibration unit Control register
Reserved
WTCRH
CUCR
R/W
R/W
-
CAL - Duration Timer Data Register Low
CAL - Duration Timer Data Register High
CAL - Calibration Timer Register 2 Low
CAL - Calibration Timer Register 2 High
CAL - Calibration Timer Register 1 Low
CAL - Calibration Timer Register 1 High
CUTDL
CUTDH
CUTR2L
CUTR2H
CUTR1L
CUTR1H
CUTD
CUTR2
CUTR1
R/W
R/W
R
R
R
R
0004F2H-
0004F9H
Reserved
-
R/W
-
0004FAH
RLT - Timer input select (for Cascading)
Reserved
TMISR
0004FBH-
00053DH
00053EH
00053FH
000540H
000540H
000541H
000542H
000543H
000544H
000545H
000546H
000547H
000548H
000549H
00054AH
00054AH
00054BH
00054CH
USART7 - Serial Mode Register
USART7 - Serial Control Register
USART7 - Serial TX Register
SMR7
SCR7
R/W
R/W
W
TDR7
USART7 - Serial RX Register
RDR7
R
USART7 - Serial Status Register
USART7 - Ext. Control/Com. Register
USART7 - Ext. Status Com. Register
USART7 - Baud Rate Generator Register Low
USART7 - Baud Rate Generator Register High
USART7 - Extended Serial Interrupt Register
Reserved
SSR7
R/W
R/W
R/W
R/W
R/W
R/W
-
ECCR7
ESCR7
BGRL7
BGRH7
ESIR7
BGR7
USART8 - Serial Mode Register
USART8 - Serial Control Register
USART8 - Serial TX Register
SMR8
SCR8
TDR8
RDR8
SSR8
ECCR8
R/W
R/W
W
USART8 - Serial RX Register
R
USART8 - Serial Status Register
USART8 - Ext. Control/Com. Register
R/W
R/W
42
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (20 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00054DH
00054EH
00054FH
000550H
000551H
000552H
000553H
000554H
000554H
000555H
000556H
000557H
000558H
000559H
00055AH
USART8 - Ext. Status Com. Register
USART8 - Baud Rate Generator Register Low
USART8 - Baud Rate Generator Register High
USART8 - Extended Serial Interrupt Register
Reserved
ESCR8
BGRL8
BGRH8
ESIR8
R/W
R/W
R/W
R/W
-
BGR8
USART9 - Serial Mode Register
SMR9
SCR9
R/W
R/W
W
USART9 - Serial Control Register
USART9 - Serial TX Register
TDR9
USART9 - Serial RX Register
RDR9
R
USART9 - Serial Status Register
SSR9
R/W
R/W
R/W
R/W
R/W
R/W
USART9 - Ext. Control/Com. Register
USART9 - Ext. Status Com. Register
USART9 - Baud Rate Generator Register Low
USART9 - Baud Rate Generator Register High
USART9 - Extended Serial Interrupt Register
ECCR9
ESCR9
BGRL9
BGRH9
ESIR9
BGR9
00055BH-
00055FH
Reserved
-
000560H
000561H
000562H
000563H
000564H
000565H
000566H
000567H
000568H
000569H
00056AH
00056BH
00056CH
ALARM0 - Control Status Register
ALARM0 - Extended Control Status Register
ALARM1 - Control Status Register
ALARM1 - Extended Control Status Register
PPG6 - Timer register
ACSR0
AECSR0
ACSR1
R/W
R/W
R/W
R/W
R
AECSR1
PTMR6
PCSR6
PDUT6
PCN6
PPG6 - Timer register
R
PPG6 - Period setting register
PPG6 - Period setting register
PPG6 - Duty cycle register
W
W
W
PPG6 - Duty cycle register
W
PPG6 - Control status register Low
PPG6 - Control status register High
PPG7 - Timer register
PCNL6
PCNH6
R/W
R/W
R
PTMR7
FME-MB96340 rev 10
43
MB96340 Series
I/O map MB96(F)34x (21 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00056DH
00056EH
00056FH
000570H
000571H
000572H
000573H
000574H
000575H
000576H
000577H
000578H
000579H
00057AH
00057BH
00057CH
00057DH
00057EH
00057FH
000580H
000581H
000582H
000583H
000584H
000585H
000586H
000587H
000588H
000589H
00058AH
PPG7 - Timer register
R
W
PPG7 - Period setting register
PPG7 - Period setting register
PPG7 - Duty cycle register
PCSR7
PDUT7
PCN7
W
W
PPG7 - Duty cycle register
W
PPG7 - Control status register Low
PPG7 - Control status register High
PPG11-PPG8 - General Control register 1 Low
PPG11-PPG8 - General Control register 1 High
PPG11-PPG8 - General Control register 2 Low
PPG11-PPG8 - General Control register 2 High
PPG8 - Timer register
PCNL7
PCNH7
R/W
R/W
R/W
R/W
R/W
R/W
R
GCN1L2
GCN1H2
GCN2L2
GCN2H2
GCN12
GCN22
PTMR8
PCSR8
PDUT8
PCN8
PPG8 - Timer register
R
PPG8 - Period setting register
PPG8 - Period setting register
PPG8 - Duty cycle register
W
W
W
PPG8 - Duty cycle register
W
PPG8 - Control status register Low
PPG8 - Control status register High
PPG9 - Timer register
PCNL8
PCNH8
R/W
R/W
R
PTMR9
PCSR9
PDUT9
PCN9
PPG9 - Timer register
R
PPG9 - Period setting register
PPG9 - Period setting register
PPG9 - Duty cycle register
W
W
W
PPG9 - Duty cycle register
W
PPG9 - Control status register Low
PPG9 - Control status register High
PPG10 - Timer register
PCNL9
PCNH9
R/W
R/W
R
PTMR10
PCSR10
PPG10 - Timer register
R
PPG10 - Period setting register
W
44
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (22 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00058BH
00058CH
00058DH
00058EH
00058FH
000590H
000591H
000592H
000593H
000594H
000595H
000596H
000597H
000598H
000599H
00059AH
00059BH
00059CH
00059DH
00059EH
00059FH
0005A0H
0005A1H
0005A2H
0005A3H
0005A4H
0005A5H
0005A6H
0005A7H
0005A8H
PPG10 - Period setting register
PPG10 - Duty cycle register
W
W
PDUT10
PCN10
PPG10 - Duty cycle register
W
PPG10 - Control status register Low
PPG10 - Control status register High
PPG11 - Timer register
PCNL10
PCNH10
R/W
R/W
R
PTMR11
PCSR11
PDUT11
PCN11
PPG11 - Timer register
R
PPG11 - Period setting register
PPG11 - Period setting register
PPG11 - Duty cycle register
W
W
W
PPG11 - Duty cycle register
W
PPG11 - Control status register Low
PPG11 - Control status register High
PPG15-PPG12 - General Control register 1 Low
PPG15-PPG12 - General Control register 1 High
PPG15-PPG12 - General Control register 2 Low
PPG15-PPG12 - General Control register 2 High
PPG12 - Timer register
PCNL11
PCNH11
GCN1L3
GCN1H3
GCN2L3
GCN2H3
R/W
R/W
R/W
R/W
R/W
R/W
R
GCN13
GCN23
PTMR12
PCSR12
PDUT12
PCN12
PPG12 - Timer register
R
PPG12 - Period setting register
PPG12 - Period setting register
PPG12 - Duty cycle register
W
W
W
PPG12 - Duty cycle register
W
PPG12 - Control status register Low
PPG12 - Control status register High
PPG13 - Timer register
PCNL12
PCNH12
R/W
R/W
R
PTMR13
PCSR13
PDUT13
PPG13 - Timer register
R
PPG13 - Period setting register
PPG13 - Period setting register
PPG13 - Duty cycle register
W
W
W
FME-MB96340 rev 10
45
MB96340 Series
I/O map MB96(F)34x (23 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0005A9H
0005AAH
0005ABH
0005ACH
0005ADH
0005AEH
0005AFH
0005B0H
0005B1H
0005B2H
0005B3H
0005B4H
0005B5H
0005B6H
0005B7H
0005B8H
0005B9H
0005BAH
0005BBH
PPG13 - Duty cycle register
PPG13 - Control status register Low
PPG13 - Control status register High
PPG14 - Timer register
W
R/W
R/W
R
PCNL13
PCNH13
PCN13
PTMR14
PCSR14
PDUT14
PCN14
PPG14 - Timer register
R
PPG14 - Period setting register
PPG14 - Period setting register
PPG14 - Duty cycle register
PPG14 - Duty cycle register
PPG14 - Control status register Low
PPG14 - Control status register High
PPG15 - Timer register
W
W
W
W
PCNL14
PCNH14
R/W
R/W
R
PTMR15
PCSR15
PDUT15
PCN15
PPG15 - Timer register
R
PPG15 - Period setting register
PPG15 - Period setting register
PPG15 - Duty cycle register
PPG15 - Duty cycle register
PPG15 - Control status register Low
PPG15 - Control status register High
W
W
W
W
PCNL15
PCNH15
R/W
R/W
0005BCH-
00065FH
Reserved
-
000660H
000661H
000662H
000663H
Peripheral Resource Relocation Register 10
Peripheral Resource Relocation Register 11
Peripheral Resource Relocation Register 12
Peripheral Resource Relocation Register 13
PRRR10
PRRR11
PRRR12
PRRR13
R/W
R/W
R/W
W
000664H-
0006DFH
Reserved
-
0006E0H
0006E1H
0006E2H
0006E3H
External Bus - Area configuration register 0 Low
External Bus - Area configuration register 0 High
External Bus - Area configuration register 1 Low
External Bus - Area configuration register 1 High
EACL0
EACH0
EACL1
EACH1
EAC0
EAC1
R/W
R/W
R/W
R/W
46
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (24 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
0006E4H
0006E5H
0006E6H
0006E7H
0006E8H
0006E9H
0006EAH
0006EBH
0006ECH
0006EDH
0006EEH
0006EFH
0006F0H
0006F1H
0006F2H
0006F3H
0006F4H
0006F5H
External Bus - Area configuration register 2 Low
External Bus - Area configuration register 2 High
External Bus - Area configuration register 3 Low
External Bus - Area configuration register 3 High
External Bus - Area configuration register 4 Low
External Bus - Area configuration register 4 High
External Bus - Area configuration register 5 Low
External Bus - Area configuration register 5 High
External Bus - Area select register 2
EACL2
EACH2
EACL3
EACH3
EACL4
EACH4
EACL5
EACH5
EAS2
EAC2
EAC3
EAC4
EAC5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
External Bus - Area select register 3
EAS3
External Bus - Area select register 4
EAS4
External Bus - Area select register 5
EAS5
External Bus - Mode register
EBM
External Bus - Clock and Function register
External Bus - Address output enable register 0
External Bus - Address output enable register 1
External Bus - Address output enable register 2
External Bus - Control signal register
EBCF
EBAE0
EBAE1
EBAE2
EBCS
0006F6H-
0006FFH
Reserved
-
000700H
000701H
000702H
000703H
000704H
000705H
000706H
000707H
000708H
000709H
CAN0 - Control register Low
CTRLRL0
CTRLRH0
STATRL0
STATRH0
ERRCNTL0
ERRCNTH0
BTRL0
CTRLR0
STATR0
ERRCNT0
BTR0
R/W
R
CAN0 - Control register High (reserved)
CAN0 - Status register Low
R/W
R
CAN0 - Status register High (reserved)
CAN0 - Error Counter Low (Transmit)
CAN0 - Error Counter High (Receive)
CAN0 - Bit Timing Register Low
CAN0 - Bit Timing Register High
CAN0 - Interrupt Register Low
R
R
R/W
R/W
R
BTRH0
INTRL0
INTR0
CAN0 - Interrupt Register High
INTRH0
R
FME-MB96340 rev 10
47
MB96340 Series
I/O map MB96(F)34x (25 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00070AH
00070BH
00070CH
00070DH
CAN0 - Test Register Low
TESTRL0
TESTRH0
BRPERL0
BRPERH0
TESTR0
R/W
R
CAN0 - Test Register High (reserved)
CAN0 - BRP Extension register Low
BRPER0
R/W
R
CAN0 - BRP Extension register High (reserved)
00070EH-
00070FH
Reserved
-
000710H
000711H
000712H
CAN0 - IF1 Command request register Low
CAN0 - IF1 Command request register High
CAN0 - IF1 Command Mask register Low
IF1CREQL0
IF1CREQH0
IF1CMSKL0
IF1CREQ0
IF1CMSK0
R/W
R/W
R/W
CAN0 - IF1 Command Mask register High (re-
served)
000713H
IF1CMSKH0
R
000714H
000715H
000716H
000717H
000718H
000719H
00071AH
00071BH
00071CH
00071DH
00071EH
00071FH
000720H
000721H
000722H
000723H
000724H
000725H
CAN0 - IF1 Mask 1 Register Low
CAN0 - IF1 Mask 1 Register High
CAN0 - IF1 Mask 2 Register Low
CAN0 - IF1 Mask 2 Register High
CAN0 - IF1 Arbitration 1 Register Low
CAN0 - IF1 Arbitration 1 Register High
CAN0 - IF1 Arbitration 2 Register Low
CAN0 - IF1 Arbitration 2 Register High
CAN0 - IF1 Message Control Register Low
CAN0 - IF1 Message Control Register High
CAN0 - IF1 Data A1 Low
IF1MSK1L0
IF1MSK1H0
IF1MSK2L0
IF1MSK2H0
IF1ARB1L0
IF1ARB1H0
IF1ARB2L0
IF1ARB2H0
IF1MCTRL0
IF1MCTRH0
IF1DTA1L0
IF1DTA1H0
IF1DTA2L0
IF1DTA2H0
IF1DTB1L0
IF1DTB1H0
IF1DTB2L0
IF1DTB2H0
IF1MSK10
IF1MSK20
IF1ARB10
IF1ARB20
IF1MCTR0
IF1DTA10
IF1DTA20
IF1DTB10
IF1DTB20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN0 - IF1 Data A1 High
CAN0 - IF1 Data A2 Low
CAN0 - IF1 Data A2 High
CAN0 - IF1 Data B1 Low
CAN0 - IF1 Data B1 High
CAN0 - IF1 Data B2 Low
CAN0 - IF1 Data B2 High
000726H-
00073FH
Reserved
-
48
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (26 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000740H
000741H
000742H
CAN0 - IF2 Command request register Low
CAN0 - IF2 Command request register High
CAN0 - IF2 Command Mask register Low
IF2CREQL0
IF2CREQH0
IF2CMSKL0
IF2CREQ0
R/W
R/W
R/W
IF2CMSK0
CAN0 - IF2 Command Mask register High (re-
served)
000743H
IF2CMSKH0
R
000744H
000745H
000746H
000747H
000748H
000749H
00074AH
00074BH
00074CH
00074DH
00074EH
00074FH
000750H
000751H
000752H
000753H
000754H
000755H
CAN0 - IF2 Mask 1 Register Low
CAN0 - IF2 Mask 1 Register High
CAN0 - IF2 Mask 2 Register Low
CAN0 - IF2 Mask 2 Register High
CAN0 - IF2 Arbitration 1 Register Low
CAN0 - IF2 Arbitration 1 Register High
CAN0 - IF2 Arbitration 2 Register Low
CAN0 - IF2 Arbitration 2 Register High
CAN0 - IF2 Message Control Register Low
CAN0 - IF2 Message Control Register High
CAN0 - IF2 Data A1 Low
IF2MSK1L0
IF2MSK1H0
IF2MSK2L0
IF2MSK2H0
IF2ARB1L0
IF2ARB1H0
IF2ARB2L0
IF2ARB2H0
IF2MCTRL0
IF2MCTRH0
IF2DTA1L0
IF2DTA1H0
IF2DTA2L0
IF2DTA2H0
IF2DTB1L0
IF2DTB1H0
IF2DTB2L0
IF2DTB2H0
IF2MSK10
IF2MSK20
IF2ARB10
IF2ARB20
IF2MCTR0
IF2DTA10
IF2DTA20
IF2DTB10
IF2DTB20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN0 - IF2 Data A1 High
CAN0 - IF2 Data A2 Low
CAN0 - IF2 Data A2 High
CAN0 - IF2 Data B1 Low
CAN0 - IF2 Data B1 High
CAN0 - IF2 Data B2 Low
CAN0 - IF2 Data B2 High
000756H-
00077FH
Reserved
-
000780H
000781H
000782H
000783H
CAN0 - Transmission Request 1 Register Low
CAN0 - Transmission Request 1 Register High
CAN0 - Transmission Request 2 Register Low
CAN0 - Transmission Request 2 Register High
TREQR1L0
TREQR1H0
TREQR2L0
TREQR2H0
TREQR10
TREQR20
R
R
R
R
000784H-
00078FH
Reserved
-
FME-MB96340 rev 10
49
MB96340 Series
I/O map MB96(F)34x (27 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000790H
000791H
000792H
000793H
CAN0 - New Data 1 Register Low
CAN0 - New Data 1 Register High
CAN0 - New Data 2 Register Low
CAN0 - New Data 2 Register High
NEWDT1L0
NEWDT1H0
NEWDT2L0
NEWDT2H0
NEWDT10
R
R
R
R
NEWDT20
000794H-
00079FH
Reserved
-
0007A0H
0007A1H
0007A2H
0007A3H
CAN0 - Interrupt Pending 1 Register Low
CAN0 - Interrupt Pending 1 Register High
CAN0 - Interrupt Pending 2 Register Low
CAN0 - Interrupt Pending 2 Register High
INTPND1L0
INTPND1H0
INTPND2L0
INTPND2H0
INTPND10
INTPND20
R
R
R
R
0007A4H-
0007AFH
Reserved
-
0007B0H
0007B1H
0007B2H
0007B3H
CAN0 - Message Valid 1 Register Low
CAN0 - Message Valid 1 Register High
CAN0 - Message Valid 2 Register Low
CAN0 - Message Valid 2 Register High
MSGVAL1L0
MSGVAL1H0
MSGVAL2L0
MSGVAL2H0
MSGVAL10
MSGVAL20
R
R
R
R
0007B4H-
0007CDH
Reserved
-
R/W
-
0007CEH
CAN0 - Output enable register
Reserved
COER0
0007CFH-
0007FFH
000800H
000801H
000802H
000803H
000804H
000805H
000806H
000807H
000808H
000809H
CAN1 - Control register Low
CTRLRL1
CTRLRH1
STATRL1
STATRH1
ERRCNTL1
ERRCNTH1
BTRL1
CTRLR1
STATR1
ERRCNT1
BTR1
R/W
R
CAN1 - Control register High (reserved)
CAN1 - Status register Low
R/W
R
CAN1 - Status register High (reserved)
CAN1 - Error Counter Low (Transmit)
CAN1 - Error Counter High (Receive)
CAN1 - Bit Timing Register Low
CAN1 - Bit Timing Register High
CAN1 - Interrupt Register Low
R
R
R/W
R/W
R
BTRH1
INTRL1
INTR1
CAN1 - Interrupt Register High
INTRH1
R
50
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (28 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
00080AH
00080BH
00080CH
00080DH
CAN1 - Test Register Low
TESTRL1
TESTRH1
BRPERL1
BRPERH1
TESTR1
R/W
R
CAN1 - Test Register High (reserved)
CAN1 - BRP Extension register Low
BRPER1
R/W
R
CAN1 - BRP Extension register High (reserved)
00080EH-
00080FH
Reserved
-
000810H
000811H
000812H
CAN1 - IF1 Command request register Low
CAN1 - IF1 Command request register High
CAN1 - IF1 Command Mask register Low
IF1CREQL1
IF1CREQH1
IF1CMSKL1
IF1CREQ1
IF1CMSK1
R/W
R/W
R/W
CAN1 - IF1 Command Mask register High (re-
served)
000813H
IF1CMSKH1
R
000814H
000815H
000816H
000817H
000818H
000819H
00081AH
00081BH
00081CH
00081DH
00081EH
00081FH
000820H
000821H
000822H
000823H
000824H
000825H
CAN1 - IF1 Mask 1 Register Low
CAN1 - IF1 Mask 1 Register High
CAN1 - IF1 Mask 2 Register Low
CAN1 - IF1 Mask 2 Register High
CAN1 - IF1 Arbitration 1 Register Low
CAN1 - IF1 Arbitration 1 Register High
CAN1 - IF1 Arbitration 2 Register Low
CAN1 - IF1 Arbitration 2 Register High
CAN1 - IF1 Message Control Register Low
CAN1 - IF1 Message Control Register High
CAN1 - IF1 Data A1 Low
IF1MSK1L1
IF1MSK1H1
IF1MSK2L1
IF1MSK2H1
IF1ARB1L1
IF1ARB1H1
IF1ARB2L1
IF1ARB2H1
IF1MCTRL1
IF1MCTRH1
IF1DTA1L1
IF1DTA1H1
IF1DTA2L1
IF1DTA2H1
IF1DTB1L1
IF1DTB1H1
IF1DTB2L1
IF1DTB2H1
IF1MSK11
IF1MSK21
IF1ARB11
IF1ARB21
IF1MCTR1
IF1DTA11
IF1DTA21
IF1DTB11
IF1DTB21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN1 - IF1 Data A1 High
CAN1 - IF1 Data A2 Low
CAN1 - IF1 Data A2 High
CAN1 - IF1 Data B1 Low
CAN1 - IF1 Data B1 High
CAN1 - IF1 Data B2 Low
CAN1 - IF1 Data B2 High
000826H-
00083FH
Reserved
-
FME-MB96340 rev 10
51
MB96340 Series
I/O map MB96(F)34x (29 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000840H
000841H
000842H
CAN1 - IF2 Command request register Low
CAN1 - IF2 Command request register High
CAN1 - IF2 Command Mask register Low
IF2CREQL1
IF2CREQH1
IF2CMSKL1
IF2CREQ1
R/W
R/W
R/W
IF2CMSK1
CAN1 - IF2 Command Mask register High (re-
served)
000843H
IF2CMSKH1
R
000844H
000845H
000846H
000847H
000848H
000849H
00084AH
00084BH
00084CH
00084DH
00084EH
00084FH
000850H
000851H
000852H
000853H
000854H
000855H
CAN1 - IF2 Mask 1 Register Low
CAN1 - IF2 Mask 1 Register High
CAN1 - IF2 Mask 2 Register Low
CAN1 - IF2 Mask 2 Register High
CAN1 - IF2 Arbitration 1 Register Low
CAN1 - IF2 Arbitration 1 Register High
CAN1 - IF2 Arbitration 2 Register Low
CAN1 - IF2 Arbitration 2 Register High
CAN1 - IF2 Message Control Register Low
CAN1 - IF2 Message Control Register High
CAN1 - IF2 Data A1 Low
IF2MSK1L1
IF2MSK1H1
IF2MSK2L1
IF2MSK2H1
IF2ARB1L1
IF2ARB1H1
IF2ARB2L1
IF2ARB2H1
IF2MCTRL1
IF2MCTRH1
IF2DTA1L1
IF2DTA1H1
IF2DTA2L1
IF2DTA2H1
IF2DTB1L1
IF2DTB1H1
IF2DTB2L1
IF2DTB2H1
IF2MSK11
IF2MSK21
IF2ARB11
IF2ARB21
IF2MCTR1
IF2DTA11
IF2DTA21
IF2DTB11
IF2DTB21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAN1 - IF2 Data A1 High
CAN1 - IF2 Data A2 Low
CAN1 - IF2 Data A2 High
CAN1 - IF2 Data B1 Low
CAN1 - IF2 Data B1 High
CAN1 - IF2 Data B2 Low
CAN1 - IF2 Data B2 High
000856H-
00087FH
Reserved
-
000880H
000881H
000882H
000883H
CAN1 - Transmission Request 1 Register Low
CAN1 - Transmission Request 1 Register High
CAN1 - Transmission Request 2 Register Low
CAN1 - Transmission Request 2 Register High
TREQR1L1
TREQR1H1
TREQR2L1
TREQR2H1
TREQR11
TREQR21
R
R
R
R
000884H-
00088FH
Reserved
-
52
FME-MB96340 rev 10
MB96340 Series
I/O map MB96(F)34x (30 of 30)
Address
Abbreviation
8-bit access
Abbreviation
16-bit access
Register
Access
000890H
000891H
000892H
000893H
CAN1 - New Data 1 Register Low
CAN1 - New Data 1 Register High
CAN1 - New Data 2 Register Low
CAN1 - New Data 2 Register High
NEWDT1L1
NEWDT1H1
NEWDT2L1
NEWDT2H1
NEWDT11
R
R
R
R
NEWDT21
000894H-
00089FH
Reserved
-
0008A0H
0008A1H
0008A2H
0008A3H
CAN1 - Interrupt Pending 1 Register Low
CAN1 - Interrupt Pending 1 Register High
CAN1 - Interrupt Pending 2 Register Low
CAN1 - Interrupt Pending 2 Register High
INTPND1L1
INTPND1H1
INTPND2L1
INTPND2H1
INTPND11
INTPND21
R
R
R
R
0008A4H-
0008AFH
Reserved
-
0008B0H
0008B1H
0008B2H
0008B3H
CAN1 - Message Valid 1 Register Low
CAN1 - Message Valid 1 Register High
CAN1 - Message Valid 2 Register Low
CAN1 - Message Valid 2 Register High
MSGVAL1L1
MSGVAL1H1
MSGVAL2L1
MSGVAL2H1
MSGVAL11
MSGVAL21
R
R
R
R
0008B4H-
0008CDH
Reserved
-
R/W
-
0008CEH
CAN1 - Output enable register
Reserved
COER1
0008CFH-
0009FFH
000A00H
000A01H
000A02H
000A03H
000A04H
000A05H
DMA - IO address block register 0
DMA - IO address block register 1
DMA - IO address block register 2
DMA - IO address block register 3
DMA - IO address block register 4
DMA - IO address block register 5
IOABK0
IOABK1
IOABK2
IOABK3
IOABK4
IOABK5
R/W
R/W
R/W
R/W
R/W
R/W
000A06H-
000BFFH
Reserved
-
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved
address results in reading ‘X’.
Registers of resources which are described in this table, but which are not supported by the device, should
also be handled as “Reserved”.
FME-MB96340 rev 10
53
MB96340 Series
■ INTERRUPT VECTOR TABLE
Interrupt vector table MB96(F)34x (1 of 4)
Offset in
Vector
number
Index in
ICR to
program
Cleared
by DMA
vector ta-
ble
Vector name
Description
0
3FCH
3F8H
3F4H
3F0H
3ECH
3E8H
3E4H
3E0H
3DCH
3D8H
3D4H
3D0H
3CCH
3C8H
3C4H
3C0H
3BCH
3B8H
3B4H
3B0H
3ACH
3A8H
3A4H
3A0H
39CH
398H
394H
390H
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
No
No
-
-
1
2
No
-
3
No
-
4
No
-
5
No
-
6
No
-
7
No
-
8
No
-
9
INT9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
Delayed Interrupt
RC Timer
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
RC_TIMER
MC_TIMER
SC_TIMER
RESERVED
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
EXTINT8
EXTINT9
EXTINT10
No
No
Main Clock Timer
Sub Clock Timer
Reserved
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
External Interrupt 8
External Interrupt 9
External Interrupt 10
54
FME-MB96340 rev 10
MB96340 Series
Interrupt vector table MB96(F)34x (2 of 4)
Offset in
Vector
number
Index in
ICR to
program
Cleared
by DMA
vector ta-
ble
Vector name
Description
External Interrupt 11
28
29
30
31
32
38CH
388H
384H
380H
37CH
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
Yes
Yes
Yes
Yes
Yes
28
29
30
31
32
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
CAN Controller 0 (except
MB96(F)34xAyy or MB96(F)34xCyy)
33
34
378H
374H
CAN0
CAN1
No
No
33
34
CAN Controller 1 (except
MB96(F)34xAyy, MB96(F)34xCyy,
MB96F345Dyy or MB96F345Fyy)
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
370H
36CH
368H
364H
360H
35CH
358H
354H
350H
34CH
348H
344H
340H
33CH
338H
334H
330H
32CH
328H
324H
PPG0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
RLT0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Reload Timer 0
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
FME-MB96340 rev 10
55
MB96340 Series
Interrupt vector table MB96(F)34x (3 of 4)
Offset in
Vector
number
Index in
ICR to
program
Cleared
by DMA
vector ta-
ble
Vector name
Description
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
320H
31CH
318H
314H
310H
30CH
308H
304H
300H
2FCH
2F8H
2F4H
2F0H
2ECH
2E8H
2E4H
2E0H
2DCH
2D8H
2D4H
2D0H
2CCH
PPGRLT
ICU0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Reload Timer 6 - dedicated for PPG
Input Capture Unit 0
Input Capture Unit 1
Input Capture Unit 2
Input Capture Unit 3
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
Output Compare Unit 0
Output Compare Unit 1
Output Compare Unit 2
Output Compare Unit 3
Output Compare Unit 4
Output Compare Unit 5
Output Compare Unit 6
Output Compare Unit 7
Free Running Timer 0
Free Running Timer 1
I2C interface
ICU1
ICU2
ICU3
ICU4
ICU5
ICU6
ICU7
OCU0
OCU1
OCU2
OCU3
OCU4
OCU5
OCU6
OCU7
FRT0
FRT1
IIC0
IIC1
I2C interface
ADC0
A/D Converter
Alarm Comparator 0 (except
MB96F345Dyy or MB96F345Fyy)
77
78
2C8H
2C4H
ALARM0
ALARM1
No
No
77
78
Alarm Comparator 1 (except
MB96F345Dyy or MB96F345Fyy)
79
80
81
82
2C0H
2BCH
2B8H
2B4H
LINR0
LINT0
LINR1
LINT1
Yes
Yes
Yes
Yes
79
80
81
82
LIN USART 0 RX
LIN USART 0 TX
LIN USART 1 RX
LIN USART 1 TX
56
FME-MB96340 rev 10
MB96340 Series
Interrupt vector table MB96(F)34x (4 of 4)
Offset in
Vector
number
Index in
ICR to
program
Cleared
by DMA
vector ta-
ble
Vector name
Description
LIN USART 2 RX
83
84
85
86
87
2B0H
2ACH
2A8H
2A4H
2A0H
LINR2
LINT2
Yes
Yes
Yes
Yes
No
83
84
85
86
87
LIN USART 2 TX
LINR3
LIN USART 3 RX
LINT3
LIN USART 3 TX
FLASH_A
Flash memory A (only Flash devices)
Flash memory B
(only MB96F348T/H/C)
88
29CH
FLASH_B
No
88
89
90
91
92
93
94
95
96
298H
294H
290H
28CH
288H
284H
280H
27CH
LINR7
LINT7
LINR8
LINT8
LINR9
LINT9
RTC0
CAL0
Yes
Yes
Yes
Yes
Yes
Yes
No
89
90
91
92
93
94
95
96
LIN USART 7 RX
LIN USART 7 TX
LIN USART 8 RX
LIN USART 8 TX
LIN USART 9 RX
LIN USART 9 TX
Real Timer Clock
Clock Calibration Unit
No
Data Flash A
(only MB96F345Dyy, MB96F345Fyy)
97
278H
DFLASH_A
Yes
97
FME-MB96340 rev 10
57
MB96340 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Unused sub clock signal
• Notes on PLL clock mode operation
• Power supply pins (VCC/VSS)
• Crystal oscillator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on energization
• Stabilization of power supply voltage
• Serial communication
• Handling of Data Flash
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up,
those resistors should be more than 2 kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC
Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be
connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.
X0
X1
58
FME-MB96340 rev 10
MB96340 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the
opposite phase to the X0 (X0A) pins.
X0
X1
4. Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
5. Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
6. Power supply pins (VCC/VSS
)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more
than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating
range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between
VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and
ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
8. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this
case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously
on or off is acceptable).
9. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on
should be slower than 50µs from 0.2 V to 2.7 V.
FME-MB96340 rev 10
59
MB96340 Series
11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage,
a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines,
the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in
the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
12. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
13. Handling of Data Flash
The Data Flash requires different and additional control signals for parallel programming. Please check with
your programming equipment maker for support of this interface.
60
FME-MB96340 rev 10
MB96340 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
VCC
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
Power supply voltage
*1
AVCC
VCC = AVCC
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > AVRL, AVRL ≥ AVSS
AD Converter voltage references
VSS - 0.3 VSS + 6.0
V
*2
Input voltage
VI
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
VI ≤ VCC + 0.3V
VO ≤ VCC + 0.3V *2
Output voltage
VO
Applicable to general purpose
I/O pins *3
Maximum Clamp Current
ICLAMP
-4.0
+4.0
mA
mA
Applicable to general purpose
I/O pins *3
Total Maximum Clamp Current
“L” level maximum output current
Σ|ICLAMP|
-
-
40
15
IOL1
mA Normal outputs with driving
strength set to 5mA
“L” level average output current
IOLAV1
-
5
mA Normal outputs with driving
strength set to 5mA
“L” level maximum overall output current
“L” level average overall output current
”H” level maximum output current
ΣIOL1
ΣIOLAV1
IOH1
-
-
-
100
50
mA Normal outputs
mA Normal outputs
-15
mA Normal outputs with driving
strength set to 5mA
”H” level average output current
IOHAV1
-
-5
mA Normal outputs with driving
strength set to 5mA
”H” level maximum overall output current
”H” level average overall output current
ΣIOH1
-
-
-
-
-100
-50
mA Normal outputs
mA Normal outputs
ΣIOHAV1
430*5
750*5
TA=105oC
TA=90oC
mW
mW
Permitted Power dissipation (Flash de-
vices in QFP package)*4
PD
PD
TA=125oC, no Flash program/
erase *6
540*5
-
mW
375*5
750*5
TA=105oC
TA=85oC
-
-
mW
mW
Permitted Power dissipation
(MB96F346/F347/F348 in LQFP pack-
age) *4
TA=125oC, no Flash program/
erase *6
470*5
560*5
-
-
mW
mW
TA=120oC, no Flash program/
erase *6
FME-MB96340 rev 10
61
MB96340 Series
Rating
Max
Parameter
Symbol
Unit
Remarks
Min
335*5
670*5
840*5
TA=105oC
TA=85oC
TA=75oC
-
-
-
mW
mW
mW
PermittedPowerdissipation(MB96F345
in LQFP package)*4
PD
TA=125oC, no Flash program/
erase *6
420*5
590*5
-
-
mW
mW
TA=115oC, no Flash program/
erase *6
TA=105oC
-
350
360
mW
mW
PermittedPowerdissipation(MaskROM
devices) *4
PD
TA=125oC *6
MB96V300B
-
0
+70
oC
oC
-40
-40
-55
+105
+125
+150
Operating ambient temperature
Storage temperature
TA
*6
TSTG
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage
at the analog inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from a input is limited by some means with external components, the ICLAMP rating super-
sedes the VI rating. Input/output voltages of standard ports depend on VCC.
*3: • Applicable to all general purpose I/O pins (Pnn_m)
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Notethatifthe+Binputisappliedduringpower-on, thepowersupplyisprovidedfromthepinsandtheresulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage
reset in internal vector mode).
62
FME-MB96340 rev 10
MB96340 Series
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0V to 16V)
R
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming or the clock
modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Fujitsu for reliability limitations when using under these conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
FME-MB96340 rev 10
63
MB96340 Series
2. Recommended Operating Conditions
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage
VCC
3.0
5.5
V
UseaX7Rceramiccapacitoror
Smoothing capacitor at C
pin
CS
3.5
4.7
15
µF a capacitor that has similar fre-
quency characteristics
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
64
FME-MB96340 rev 10
MB96340 Series
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
Input H voltage
CMOSHysteresis
0.8/0.2 input se-
lected
Not available in
MB96F345
0.8
VCC
VCC +
0.3
-
V
0.7
VCC +
-
-
V
V
VCC ≥ 4.5V
CMOSHysteresis
0.7/0.3 input se-
lected
VCC
0.3
Port inputs
Pnn_m
0.74
VCC
VCC +
0.3
VCC < 4.5V
VIH
AUTOMOTIVE
Hysteresis input
selected
0.8
VCC +
-
-
-
-
V
V
V
VCC
0.3
TTL input select-
ed
Not available in
MB96F345
VCC +
0.3
2.0
External clock in
“Fast Clock Input
mode”
Not available in
MB96F34xY/R/AxA
0.8
VCC
VCC +
0.3
VIHX0F
X0
X0,X1,
External clock in
VCC +
0.3
2.5
VIHX0S
V
V
V
X0A,X1A “oscillation mode”
CMOS Hysteresis in-
put
0.8
VCC
VCC +
0.3
-
-
VIHR
VIHM
RSTX
-
-
VCC -
0.3
VCC +
0.3
MD2-MD0
Input L voltage
CMOSHysteresis
0.8/0.2 input se-
lected
Not available in
MB96F345
VSS -
0.2
-
-
V
0.3
VCC
CMOSHysteresis
0.7/0.3 input se-
lected
VSS -
0.3
0.3
VCC
V
V
Port inputs
Pnn_m
VIL
VSS -
0.3
0.5
VCC
-
-
VCC ≥ 4.5V
AUTOMOTIVE
Hysteresis input
selected
VSS -
0.3
0.46
VCC
VCC < 4.5V
TTL input select-
ed
Not available in
MB96F345
VSS -
-
-
-
0.8
V
V
0.3
External clock in
“Fast Clock Input
mode”
Not available in
MB96F34xY/R/AxA
VSS -
0.3
0.2 VCC
VILX0F
VILX0S
X0
X0,X1,
External clock in
X0A,X1A “oscillation mode”
VSS -
0.3
0.4
V
V
V
CMOS Hysteresis in-
put
VSS -
0.3
-
-
0.2 VCC
VILR
VILM
RSTX
-
-
VSS -
0.3
VSS +
0.3
MD2-MD0
FME-MB96340 rev 10
65
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Typ
Max
4.5V ≤ VCC ≤ 5.5V
IOH = -2mA
Output H voltage
Driving strength set
to 2mA
(PODR:OD=1)
Normal
outputs
VCC -
0.5
-
-
VOH2
V
3.0V ≤ VCC < 4.5V
IOH = -1.6mA
4.5V ≤ VCC ≤ 5.5V
IOH = -5mA
Driving strength set
to 5mA
(PODR:OD=0)
Normal
outputs
VCC -
0.5
-
-
-
-
-
VOH5
VOH3
VOL2
VOL5
V
V
V
3.0V ≤ VCC < 4.5V
IOH = -3mA
4.5V ≤ VCC ≤ 5.5V
IOH = -3mA
3mA out-
puts
VCC -
0.5
-
I/O circuit type “N”
3.0V ≤ VCC < 4.5V
IOH = -2mA
4.5V ≤ VCC ≤ 5.5V
IOL = +2mA
Output L voltage
Driving strength set
to 2mA
(PODR:OD=1)
Normal
outputs
-
-
0.4
0.4
3.0V ≤ VCC < 4.5V
IOL = +1.6mA
4.5V ≤ VCC ≤ 5.5V
IOL = +5mA
Driving strength set
to 5mA
(PODR:OD=0)
Normal
outputs
V
V
3.0V ≤ VCC < 4.5V
IOL = +3mA
3.0V ≤ VCC ≤ 5.5V
IOL = +3mA
3mA out-
puts
-
-
-
0.4
+1
VOL3
IIL
I/O circuit type “N”
VSS < VI < VCC
-1
Input leak current
Pull-up resistance
Pnn_m
µA Single port pin
AVSS, AVRL < VI <
AVCC, AVRH
40
25
100
50
160
100
VCC = 3.3V 10%
VCC = 5.0V 10%
kΩ
kΩ
Pnn_m,
RSTX
RUP
66
FME-MB96340 rev 10
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C
8
11
mA MB96345/346
+125˚C 8.5
13
20
23
22
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 16MHz,
CLKP2 = 8MHz
+25˚C
+125˚C
+25˚C
15
16
17
mA MB96F345
1 Flash/ROM wait state
MB96F346/F347/F348Y/
R/Ayy
mA
(CLKRC and CLKSC
stopped)
+125˚C 18.5 25.5
+25˚C 16 21
+125˚C 17.5 24.5
mA MB96F348T/H/CyB/C
mA MB96345/346
mA MB96F345
+25˚C
14
18
20
+125˚C 14.5
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 32MHz,
CLKP2 = 16MHz
+25˚C 23.5 29.5
+125˚C
+25˚C
25
26
28
25
27
13
32.5
32
36
31
35
17
19
39
42
43
47
42
46
Power supply
current in Run
modes*
ICCPLL
2 Flash/ROM wait states
MB96F346/F347/F348Y/
R/Ayy
mA
(CLKRC and CLKSC
stopped)
+125˚C
+25˚C
mA MB96F348T/H/CyB/C
mA MB96345/346
mA MB96F345
+125˚C
+25˚C
+125˚C 13.5
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
+25˚C
+125˚C
+25˚C
27
29
31
33
30
32
0 Flash/ROM wait states
MB96F346/F347/F348Y/
R/Ayy
mA
(CLKRC and CLKSC
stopped)
+125˚C
+25˚C
mA MB96F348T/H/CyB/C
+125˚C
FME-MB96340 rev 10
67
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C
24
29
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1= 56MHz,
CLKP2 = 28MHz
mA MB96345/346
+125˚C 24.5
31
57
61
55
59
51
+25˚C
+125˚C
+25˚C
46
48
44
46
38
MB96F346/F347/F348Y/
R/Ayy
mA
2 Flash/ROM wait states
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
mA MB96F348T/H/CyB/C
+125˚C
+25˚C
PLL Run mode with
CLKS1/2 = 72MHz,
CLKB = CLKP1 = 36MHz,
CLKP2 = 18MHz
MB96F346/F347/F348Y/
R/Ayy
mA
1 Flash wait state
+125˚C
+25˚C
40
38
40
24
55
51
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
ICCPLL
PLL Run mode with
CLKS1/2 = 80MHz,
CLKB = CLKP1 = 40MHz,
CLKP2 = 20MHz
Power supply
current in Run
modes*
mA MB96F345
1 Flash wait state
+125˚C
+25˚C
54
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
PLL Run mode with
CLKS1/2 = 96MHz,
CLKB = CLKP1= 48MHz,
CLKP2 = 24MHz
28.5
mA MB96345/346
+125˚C 24.5 30.5
+25˚C
+125˚C
+25˚C
49
51
62
66
1 Flash/ROM wait state
mA MB96F348T/H/CyB/C
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
2.3
3.3
5.3
5
mA MB96345/346
mA MB96F345
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
+125˚C 2.8
+25˚C
+125˚C 4.6
+25˚C 4.5
+125˚C 5.2
4
ICCMAIN
1 Flash/ROM wait state
7.2
5.5
8.5
(CLKPLL, CLKSC and
CLKRC stopped)
mA MB96F346/F347/F348
68
FME-MB96340 rev 10
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C
+125˚C
+25˚C
1.5
2.5
mA MB96345/346
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
2
4.4
3.5
5.7
4
2.5
ICCRCH
mA MB96F345
1 Flash/ROM wait state
+125˚C 3.1
+25˚C 2.9
+125˚C 3.6
(CLKMC, CLKPLL and
CLKSC stopped)
mA MB96F346/F347/F348
mA MB96345/346
7
+25˚C 0.35 0.55
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
+125˚C 0.75
+25˚C 0.18
+125˚C 0.73
2.3
0.3
2.3
0.6
3.4
1 Flash/ROM wait state
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C
0.4
mA MB96F346/F347/F348
mA MB96345/346
Power supply
current in Run
modes*
+125˚C 0.95
ICCRCL
+25˚C 0.08 0.17
+125˚C 0.47 1.92
+25˚C 0.15 0.25
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
1 Flash/ROM wait state
mA MB96F345
+125˚C 0.7
2.25
+25˚C 0.15 0.25
+125˚C 0.7 3.05
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode, no Flash program-
ming/erasing allowed)
mA MB96F346/F347/F348
mA MB96345/346
+25˚C 0.04 0.12
+125˚C 0.43 1.85
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
+25˚C
0.1
0.2
2.2
0.2
3
1 Flash/ROM wait state
ICCSUB
mA MB96F345
+125˚C 0.65
(CLKMC, CLKPLL and
CLKRCstopped, noFlash
programming/erasing al-
lowed)
+25˚C
0.1
mA MB96F346/F347/F348
+125˚C 0.65
FME-MB96340 rev 10
69
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C
4
6
mA MB96345/346
+125˚C 4.5
+25˚C
+125˚C 4.7
+25˚C
+125˚C 4.7
+25˚C 4.7
+125˚C 5.5
8
6
4
PLL Sleep mode with
CLKS1/2 = CLKP1 =
16MHz,
mA MB96F345
8.5
6
CLKP2 = 8MHz
4
MB96F346/F347/F348Y/
R/Ayy
(CLKRC and CLKSC
stopped)
mA
9
6.7
9.7
10
mA MB96F348T/H/CyB/C
mA MB96345/346
mA MB96F345
+25˚C
+125˚C
+25˚C
7.5
8
12
7
9.5
12
PLL Sleep mode with
CLKS1/2 = CLKP1 =
32MHz,
+125˚C 7.7
+25˚C 7.5
+125˚C 8.4
+25˚C 8.5
+125˚C 9.5
Power supply
current in Sleep
modes*
ICCSPLL
CLKP2 = 16MHz
10
MB96F346/F347/F348Y/
R/Ayy
(CLKRC and CLKSC
stopped)
mA
13
11
mA MB96F348T/H/CyB/C
mA MB96345/346
mA MB96F345
14
+25˚C
+125˚C
+25˚C
7.5
8
9.5
11.5
9
7
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
+125˚C 7.7
+25˚C 7.5
+125˚C 8.4
+25˚C 8.5
+125˚C 9.5
11.5
9.5
12.5
10.5
13.5
(CLKRC and CLKSC
stopped)
MB96F346/F347/F348Y/
R/Ayy
mA
mA MB96F348T/H/CyB/C
70
FME-MB96340 rev 10
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C 12.5
16
mA MB96345/346
+125˚C
13
18
16
PLL Sleep mode with
CLKS1/2 = CLKP1=
56MHz, CLKP2 = 28MHz
+25˚C 12.5
+125˚C 13.5
+25˚C 13.5
+125˚C 14.5
MB96F346/F347/F348Y/
R/Ayy
mA
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
19
17
mA MB96F348T/H/CyB/C
20
PLL Sleep mode with
CLKS1/2 = 72MHz,
CLKP1 = 36MHz,
CLKP2 = 18MHz
+25˚C
9.5
12.5
MB96F346/F347/F348Y/
R/Ayy
mA
+125˚C 10.5 15.5
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
ICCSPLL
PLL Sleep mode with
CLKS1/2 = 80MHz,
CLKP1 = 40MHz,
CLKP2 = 20MHz
+25˚C
11
13.5
16
Power supply
current in Sleep
modes*
mA MB96F345
+125˚C 11.7
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
PLL Sleep mode with
CLKS1/2 = 96MHz,
CLKP1= 48MHz,
+25˚C
13
16
18
mA MB96345/346
+125˚C 13.5
CLKP2 = 24MHz
+25˚C
+125˚C
+25˚C
15
16
18
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
mA MB96F348T/H/CyB/C
mA MB96345/346
21
1.3
1.8
3.7
1.3
3.4
1.8
4.6
+125˚C 1.8
+25˚C
+125˚C 1.6
+25˚C 1.3
+125˚C 1.9
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
1
ICCSMAIN
mA MB96F345
(CLKPLL, CLKSC and
CLKRC stopped)
mA MB96F346/F347/F348
FME-MB96340 rev 10
71
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C
0.8
1.4
mA MB96345/346
+125˚C 1.3
+25˚C 0.55
+125˚C 1.1
3.2
1.1
3.1
1.4
4.2
0.5
2.3
0.2
2.2
0.5
3.3
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
ICCSRCH
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped)
+25˚C
+125˚C 1.4
+25˚C 0.3
0.8
mA MB96F346/F347/F348
mA MB96345/346
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
+125˚C 0.7
+25˚C 0.09
+125˚C 0.59
SMCR:LPMSS = 0
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+25˚C
+125˚C 0.8
+25˚C 0.05 0.14
+125˚C 0.44 1.9
+25˚C 0.05 0.15
+125˚C 0.56 2.1
+25˚C 0.05 0.15
+125˚C 0.56 2.9
0.3
mA MB96F346/F347/F348
mA MB96345/346
Power supply
current in Sleep
modes*
ICCSRCL
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 1
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
mA MB96F346/F347/F348
mA MB96345/346
+25˚C 0.04 0.12
+125˚C 0.43 1.85
+25˚C 0.04 0.12
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
ICCSSUB
mA MB96F345
+125˚C 0.54
+25˚C 0.04 0.12
+125˚C 0.54 2.9
2.1
(CLKMC, CLKPLL and
CLKRC stopped)
mA MB96F346/F347/F348
72
FME-MB96340 rev 10
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C
1.4
1.9
mA MB96345/346
+125˚C 1.9
3.9
1.8
4
PLL Timer mode with
CLKMC = 4MHz, CLKPLL
= 48MHz
+25˚C
+125˚C 1.9
+25˚C 1.5
1.3
ICCTPLL
mA MB96F345
(CLKRC and CLKSC
stopped)
2
mA MB96F346/F347/F348
mA MB96345/346
+125˚C 2.1
+25˚C 0.35
+125˚C 0.7
+25˚C 0.11
+125˚C 0.63
+25˚C 0.35
+125˚C 0.85
5
0.5
2.3
0.2
2.2
0.5
3.3
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
Power supply
current in Timer
modes*
mA MB96F345
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in high power
mode)
mA MB96F346/F347/F348
mA MB96345/346
ICCTMAIN
+25˚C 0.08 0.15
+125˚C 0.47 1.9
+25˚C 0.08 0.15
+125˚C 0.6 2.1
+25˚C 0.08 0.15
+125˚C 0.6 2.9
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 1
mA MB96F345
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in low power
mode)
mA MB96F346/F347/F348
FME-MB96340 rev 10
73
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C 0.35
0.5
mA MB96345/346
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
+125˚C 0.7
+25˚C 0.13
+125˚C 0.63
+25˚C 0.35
+125˚C 0.85
2.3
0.2
2.2
0.5
3.3
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
mA MB96F346/F347/F348
mA MB96345/346
ICCTRCH
+25˚C 0.07 0.15
+125˚C 0.46 1.9
+25˚C 0.07 0.15
+125˚C 0.6 2.1
+25˚C 0.07 0.15
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 1
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
mA MB96F346/F347/F348
mA MB96345/346
+125˚C 0.6
+25˚C 0.3
+125˚C 0.65
2.9
0.45
2.2
Power supply
current in Timer
modes*
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
+25˚C 0.08 0.15
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+125˚C 0.58
+25˚C 0.3
2.1
0.45
3.2
mA MB96F346/F347/F348
mA MB96345/346
+125˚C 0.8
+25˚C 0.03
ICCTRCL
0.1
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
+125˚C 0.41 1.85
+25˚C 0.03 0.1
+125˚C 0.53 2.05
+25˚C 0.03 0.1
+125˚C 0.53 2.85
mA MB96F345
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
mA MB96F346/F347/F348
74
FME-MB96340 rev 10
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
+25˚C 0.035 0.1
+125˚C 0.42 1.85
+25˚C 0.035 0.1
+125˚C 0.53 2.05
+25˚C 0.035 0.1
+125˚C 0.53 2.85
+25˚C 0.02 0.08
mA MB96345/346
Sub Timer mode with
CLKSC = 32kHz
Power supply
current in Timer
modes*
ICCTSUB
mA MB96F345
(CLKMC, CLKPLL and
CLKRC stopped)
mA MB96F346/F347/F348
mA MB96345/346
+125˚C 0.4
+25˚C 0.02 0.08
+125˚C 0.52 2.0
+25˚C 0.02 0.08
+125˚C 0.52 2.8
+25˚C 0.015 0.06
+125˚C 0.3 1.4
+25˚C 0.015 0.06
+125˚C 0.4 1.5
+25˚C 0.015 0.06
1.8
VRCR:LPMB[2:0] = 110B
(Core voltage at 1.8V)
mA MB96F345
mA MB96F346/F347/F348
mA MB96345/346
Power supply
current in Stop
Mode
ICCH
VRCR:LPMB[2:0] = 000B
(Core voltage at 1.2V)
mA MB96F345
mA MB96F346/F347/F348
+125˚C 0.4
2.3
10
MB96F345
+25˚C
+125˚C
+25˚C
5
7
µA
Power supply
currentforactive
Low Voltage de-
tector
Must be added to all cur-
rent above
20
µA
Low voltage detector en-
abled (RCR:LVDE = 1)
ICCLVD
Other devices
90
140
150
µA
Must be added to all cur-
rent above
+125˚C 100
Power supply
currentforactive ICCCLOMO
Clock modulator
Clock modulator enabled
(CMCR:PDX = 1)
Must be added to all cur-
rent above
-
-
3
4.5
mA
Current for one Flash
module
Must be added to all cur-
rent above
ICCFLASH
15
10
40
20
mA
mA
Flash Write/
Erase current
CurrentforoneDataFlash
module
Must be added to all cur-
rent above
ICCDFLASH
FME-MB96340 rev 10
75
MB96340 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition (at TA)
Remarks
Typ
Max Unit
Input capaci-
tance
Other than C, AVCC, AVSS,
AVRH, AVRL, VCC, VSS
CIN
-
-
5
15
pF
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz
external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of
the Hardware Manual for further details about voltage regulator control.
76
FME-MB96340 rev 10
MB96340 Series
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
3
-
16
MHz When using a crystal oscillator, PLL off
When using an opposite phase external
clock, PLL off
0
-
-
16
16
MHz
Clock frequency
fC
X0, X1
When using a crystal oscillator or oppo-
MHz
3.5
site phase external clock, PLL on
When using a single phase external
clock in “Fast Clock Input mode” (not
available in MB96F34xY/R/AxA), PLL
off
0
-
-
56
56
MHz
Clock frequency
fFCI
X0
When using a single phase external
clock in “Fast Clock Input mode” (not
available in MB96F34xY/R/AxA), PLL
3.5
MHz
on
32
0
32.768
-
100 kHz When using an oscillation circuit
X0A, X1A
X0A
When using an opposite phase external
100 kHz
clock
Clock frequency
Clock frequency
fCL
When using a single phase external
clock
0
50
1
-
100
2
50
kHz
When using slow frequency of RC oscil-
lator
200 kHz
fCR
-
-
When using fast frequency of RC oscil-
lator
4
MHz
Applied after any reset and when acti-
vating the RC oscillator.
MB96F345: 256 cycles
others 64 cycles
RC clock stabili-
zation time
tRCSTAB
64 or 256 RC clock cycles
PLL Clock fre-
quency
Permitted VCO output frequency of PLL
(CLKVCO)
fCLKVCO
TPSKEW
-
-
64
-
-
-
200 MHz
For CLKMC (PLL input clock) ≥ 4MHz,
ns jitter coming from external oscillator,
crystal or resonator is not covered
PLL Phase Jitter
5
Inputclockpulse
width
PWH, PWL
X0,X1
8
5
-
-
-
-
ns Duty ratio is about 30% to 70%
Inputclockpulse
width
PWHL, PWLL X0A,X1A
µs
FME-MB96340 rev 10
77
MB96340 Series
tCYL
VIH
VIL
X0
PWH
PWL
tCYLL
VIH
VIL
X0A
PWHL
PWLL
78
FME-MB96340 rev 10
MB96340 Series
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Core Voltage Settings
Parameter
Symbol
1.8V
1.9V
Unit
Remarks
Min
Max
Min
Max
Internal System clock fre-
quency (CLKS1 and
CLKS2)
fCLKS1, fCLKS2
0
92
0
96
MHz
Others than below
0
0
0
86
72
68
0
0
0
96
80
74
MHz MB96F348T/H/CxB/C
MHz MB96F345
MHz MB96F34xY/R/Axx
Internal CPU clock fre-
quency (CLKB), internal
peripheralclockfrequency
(CLKP1)
fCLKB, fCLKP1
0
52
0
56
MHz
Others than below
0
0
0
36
28
26
0
0
0
40
32
28
MHz
MHz
MB96F345
Internal peripheral clock
frequency (CLKP2)
fCLKP2
Others than below
MHz MB96F34xY/R/Axx
FME-MB96340 rev 10
79
MB96340 Series
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Reset input time
Symbol
Pin
Unit
Remarks
Min
Typ
Max
tRSTL
RSTX
500
-
-
ns
tRSTL
RSTX
0.2 VCC
0.2 VCC
80
FME-MB96340 rev 10
MB96340 Series
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
0.05
1
Typ
Max
30
-
Power on rise time
Power off time
tR
Vcc
Vcc
-
-
ms
ms
tOFF
tR
2.7V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
VCC
3 V
Rising edge of 50 mV/ms
maximum is allowed
FME-MB96340 rev 10
81
MB96340 Series
External Input timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Used Pin input func-
Parameter Symbol
Pin
Condition
Unit
tion
Min
Max
INTn(_R)
NMI(_R)
Pnn_m
External Interrupt
NMI
200
⎯
ns
General Purpose IO
Reload Timer
TINn(_R)
TTGn(_R)
ADTG(_R)
Input pulse
width
tINH
tINL
⎯
PPG Trigger input
AD Converter Trigger
2*tCLKP1 + 200
(tCLKP1=1/
fCLKP1)
⎯
ns
Free Running Timer
external clock
FRCKn(_R)
INn(_R)
Input Capture
Note : Relocated Resource Inputs have same characteristics
VIH
VIH
External Pin input
VIL
VIL
tINH
tINL
82
FME-MB96340 rev 10
MB96340 Series
External Bus timing
Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output
timing described in the different tables must then be increased by 10ns.
Basic Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
25
Max
⎯
tCYC
tCHCL
ECLK
ECLK
⎯
tCYC/2-5
tCYC/2-5
-20
tCYC/2+5
tCYC/2+5
20
ns
tCLCH
tCHCBH
tCHCBL
tCLCBH
tCLCBL
tCHLH
-20
20
ECLK →
UBX/ LBX / CSn time
CSn, UBX,
LBX, ECLK
⎯
⎯
ns
ns
-20
20
-20
20
-10
10
tCHLL
-10
10
ECLK → ALE time
ALE, ECLK
tCLLH
-10
10
tCLLL
-10
10
tCHAV
-15
15
A[23:16],
ECLK
⎯
⎯
ns
ns
tCLAV
-15
15
ECLK → address valid time
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
-15
15
AD[15:0],
ECLK
-15
15
-10
10
RDX, WRX,
WRLX,WRHX,
ECLK
-10
10
ECLK → RDX /WRX time
⎯
ns
-10
10
-10
10
FME-MB96340 rev 10
83
MB96340 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
Max
⎯
tCYC
tCHCL
30
ECLK
ECLK
⎯
tCYC/2-8
tCYC/2-8
-25
tCYC/2+8
tCYC/2+8
25
ns
tCLCH
tCHCBH
tCHCBL
tCLCBH
tCLCBL
tCHLH
-25
25
ECLK →
UBX/ LBX / CSn time
CSn, UBX,
LBX, ECLK
⎯
⎯
ns
ns
-25
25
-25
25
-15
15
tCHLL
-15
15
ECLK → ALE time
ALE, ECLK
tCLLH
-15
15
tCLLL
-15
15
tCHAV
-20
20
A[23:16],
ECLK
⎯
⎯
ns
ns
tCLAV
-20
20
ECLK → address valid time
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
-20
20
AD[15:0],
ECLK
-20
20
-15
15
RDX, WRX,
WRLX, WRHX,
ECLK
-15
15
ECLK → RDX /WRX time
⎯
ns
-15
15
-15
15
84
FME-MB96340 rev 10
MB96340 Series
tCYC
tCHCL
tCLCH
0.8*Vcc
ECLK
0.2*Vcc
tCLAV
tCHAV
A[23:16]
tCHCBL
tCLCBL
tCHCBH
tCLCBH
CSn
LBX UBX
tCHRWL
tCLRWL
tCHRWH
tCLRWH
RDX
WRX (WRLX, WRHX)
tCHLL
tCLLL
tCLLH
tCHLH
ALE
tCHADV
tCLADV
Address
AD[15:0]
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96340 rev 10
85
MB96340 Series
Bus Timing (Read)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
Conditions
Unit
Min
Max
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 5
tCYC − 5
ALE pulse width
EACL:STS=1
tLHLL ALE
⎯
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 5
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC − 15
3tCYC/2 − 15
2tCYC − 15
5tCYC/2 − 15
tCYC/2 − 15
tCYC − 15
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EACL:STS=1 and
EACL:ACE=0
tAVLL ALE, A[23:16],
ns
EACL:STS=0 and
EACL:ACE=1
EACL:STS=1 and
EACL:ACE=1
Valid address
⇒ ALE ↓ time
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL ALE,AD[15:0]
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 15
EACL:STS=1 and
EACL:ACE=1
2tCYC − 15
tCYC/2 − 15
-15
⎯
⎯
⎯
EACL:STS=0
EACL:STS=1
EACL:ACE=0
ALE ↓
⇒ Address valid time
tLLAX ALE, AD[15:0]
tAVRL RDX, A[23:16]
ns
ns
3tCYC/2 − 15
5tCYC/2 − 15
tCYC − 15
2tCYC − 15
⎯
⎯
⎯
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
Valid address
⇒ RDX ↓ time
⎯
tADVRL RDX, AD[15:0]
ns
ns
⎯
3tCYC − 55
4tCYC − 55
5tCYC/2 − 55
7tCYC/2 − 55
⎯
A[23:16],
tAVDV
w/o cycle
extension
AD[15:0]
⎯
Valid address
⇒ Valid data input
⎯
w/o cycle
extension
tADVDV AD[15:0]
tRLRH RDX
ns
ns
⎯
w/o cycle
extension
RDX pulse width
⎯
3 tCYC/2 − 5
w/o cycle
extension
RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]
⎯
⎯
⎯
3 tCYC/2 − 50 ns
RDX ↑ ⇒ Data hold time
tRHDX RDX, AD[15:0]
0
⎯
ns
86
FME-MB96340 rev 10
MB96340 Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
A[23:16],
Conditions
Unit
Min
Max
Address valid ⇒ Data hold
tAXDX
⎯
0
⎯
ns
time
AD[15:0]
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 − 10
tCYC/2 − 10
⎯
⎯
RDX ↑ ⇒ ALE ↑ time
tRHLH RDX, ALE
ns
other ECL:STS,
EACL:ACE setting
tAVCH A[23:16], ECLK
tADVCH AD[15:0], ECLK
tRLCH RDX, ECLK
tCYC − 15
tCYC/2 − 15
tCYC/2 − 10
tCYC/2 − 10
− 10
⎯
⎯
Valid address
⇒ ECLK ↑ time
⎯
ns
ns
ns
ns
RDX ↓ ⇒ ECLK ↑ time
⎯
EACL:STS=0
EACL:STS=1
⎯
⎯
⎯
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
⎯
ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK
⎯
tCYC − 50
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
Conditions
Unit
Min
Max
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 8
tCYC − 8
ALE pulse width
EACL:STS=1
tLHLL ALE
⎯
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 8
⎯
EACL:STS=0 and
EACL:ACE=0
tCYC − 20
3tCYC/2 − 20
2tCYC − 20
5tCYC/2 − 20
tCYC/2 − 20
tCYC − 20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
EACL:STS=1 and
EACL:ACE=0
tAVLL ALE, A[23:16],
ns
EACL:STS=0 and
EACL:ACE=1
EACL:STS=1 and
EACL:ACE=1
Valid address
⇒ ALE ↓ time
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL ALE, AD[15:0]
tLLAX ALE, AD[15:0]
ns
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 20
EACL:STS=1 and
EACL:ACE=1
2tCYC − 20
tCYC/2 − 20
-20
⎯
⎯
⎯
EACL:STS=0
EACL:STS=1
ALE ↓
⇒ Address valid time
FME-MB96340 rev 10
87
MB96340 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Sym-
bol
Remarks
Parameter
Pin
Conditions
Unit
Min
Max
EACL:ACE=0
3tCYC/2 − 20
5tCYC/2 − 20
tCYC − 20
2tCYC − 20
⎯
⎯
tAVRL RDX, A[23:16]
tADVRL RDX, AD[15:0]
ns
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
⎯
⎯
Valid address
⇒ RDX ↓ time
ns
ns
⎯
3tCYC − 60
4tCYC − 60
5tCYC/2 − 60
7tCYC/2 − 60
⎯
A[23:16],
tAVDV
w/o cycle
extension
AD[15:0]
⎯
Valid address
⇒ Valid data input
⎯
w/o cycle
extension
tADVDV AD[15:0]
tRLRH RDX
ns
ns
⎯
w/o cycle
extension
RDX pulse width
⎯
3tCYC/2 − 8
w/o cycle
extension
RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]
⎯
⎯
⎯
3tCYC/2 − 55 ns
RDX ↑ ⇒ Data hold time
tRHDX RDX, AD[15:0]
tAXDX A[23:16]
0
⎯
⎯
ns
ns
Address valid ⇒ Data hold
⎯
0
time
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 − 15
tCYC/2 − 15
⎯
⎯
RDX ↑ ⇒ ALE ↑ time
tRHLH RDX, ALE
ns
other ECL:STS,
EACL:ACE setting
tAVCH A[23:16], ECLK
tADVCH AD[15:0], ECLK
tRLCH RDX, ECLK
tCYC − 20
tCYC/2 − 20
tCYC/2 − 15
tCYC/2 − 15
− 15
⎯
⎯
Valid address
⇒ ECLK ↑ time
⎯
ns
ns
ns
ns
RDX ↓ ⇒ ECLK ↑ time
⎯
EACL:STS=0
EACL:STS=1
⎯
⎯
⎯
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
⎯
ECLK↑ ⇒ Valid data input tCHDV AD[15:0], ECLK
⎯
tCYC − 55
88
FME-MB96340 rev 10
MB96340 Series
tAVCH
tCHDV
tRLCH
tADVCH
0.8*Vcc
ECLK
tAVLL
tLLAX
tADVLL
tRHLH
ALE
0.2*VCC
tLHLL
tAVRL
tADVRL
tRLRH
RDX
tLLRL
A[23:16]
tRLDV
tAXDX
tAVDV
tRHDX
tADVDV
VIH
VIL
VIH
VIL
AD[15:0]
Address
Read data
Refer to the Hardware Manual for detailed Timing Charts
.
Bus Timing (Write)
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
EACL:ACE=0
3tCYC/2 −
⎯
WRX, WRLX,
WRHX,
A[23:16]
15
tAVWL
ns
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
5tCYC/2 −
⎯
⎯
⎯
⎯
Valid address
⇒ WRX ↓ time
15
tCYC − 15
2tCYC − 15
tCYC − 5
WRX, WRLX,
tADVWL WRHX,
ns
AD[15:0]
WRX, WRXL,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
tDVWH
⎯
⎯
ns
ns
WRX, WRLX,
WRHX,
AD[15:0]
Valid data output
⇒ WRX ↑ time
w/o cycle
extension
tCYC − 20
⎯
FME-MB96340 rev 10
89
MB96340 Series
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
tWHDX
⎯
⎯
tCYC/2 − 15
tCYC/2 − 15
⎯
ns
⇒ Data hold time
WRX ↑
⇒ Address valid time
WRX, WRLX,
WRHX,
A[23:16]
tWHAX
⎯
ns
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
2tCYC − 10
tCYC − 10
⎯
⎯
WRX ↑ ⇒ ALE ↑ time
WRX, WRLX,
WRHX, ALE
tWHLH
tWLCH
ns
ns
ns
ns
EACL:STS setting
WRX ↓ ⇒ ECLK ↑
time
WRX, WRLX,
WRHX, ECLK
⎯
tCYC/2 − 10
⎯
⎯
3tCYC/2 −
EACL:ACE=0
15
CSn ⇒ WRX time
WRX ⇒ CSn time
WRX, WRLX,
WRHX, CSn
tCSLWL
5tCYC/2 −
EACL:ACE=1
⎯
15
WRX, WRLX,
WRHX, CSn
⎯
tWHCSH
tCYC/2 − 15
⎯
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
EACL:ACE=0
3tCYC/2 −
⎯
WRX, WRLX,
WRHX,
A[23:16]
20
tAVWL
ns
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
5tCYC/2 −
⎯
⎯
⎯
⎯
Valid address
⇒ WRX ↓ time
20
tCYC − 20
2tCYC − 20
tCYC − 8
WRX, WRLX,
tADVWL WRHX,
ns
AD[15:0]
WRX, WRXL,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
⎯
⎯
ns
ns
WRX, WRLX,
WRHX,
AD[15:0]
Valid data output
⇒ WRX ↑ time
w/o cycle
extension
tDVWH
tCYC − 25
tCYC/2 − 20
tCYC/2 − 20
⎯
⎯
⎯
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
tWHDX
tWHAX
⎯
⎯
ns
ns
⇒ Data hold time
WRX ↑
⇒ Address valid time
WRX, WRLX,
WRHX,
A[23:16]
90
FME-MB96340 rev 10
MB96340 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Remarks
Parameter
Symbol
Pin
Condition
Unit
Min
Max
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
2tCYC − 15
tCYC − 15
⎯
WRX ↑ ⇒ ALE ↑ time
WRX, WRLX,
WRHX, ALE
tWHLH
tWLCH
ns
ns
ns
ns
⎯
⎯
EACL:STS setting
WRX ↓ ⇒ ECLK ↑
time
WRX, WRLX,
WRHX, ECLK
⎯
tCYC/2 − 15
⎯
3tCYC/2 −
EACL:ACE=0
20
CSn ⇒ WRX time
WRX ⇒ CSn time
WRX, WRLX,
WRHX, CSn
tCSLWL
tWHCSH
5tCYC/2 −
EACL:ACE=1
⎯
20
WRX, WRLX,
WRHX, CSn
⎯
tCYC/2 − 20
⎯
tWLCH
0.8*VCC
ECLK
tWHLH
ALE
.
tAVWL
tWLWH
tADVWL
WRX (WRLX, WRHX)
0.2*VCC
tCSLWL
tWHCSH
CSn
tWHAX
A[23:16]
tDVWH
tWHDX
AD[15:0]
Address
Write data
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96340 rev 10
91
MB96340 Series
Ready Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Rated Value
Test
Condition
Parameter
Symbol
Pin
Units
Remarks
Min
Max
⎯
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
35
0
ns
ns
⎯
⎯
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Rated Value
Test
Parameter
Symbol
Pin
Units
Remarks
Condition
Min
45
0
Max
RDY setup time
RDY hold time
tRYHS
tRYHH
RDY
RDY
⎯
ns
ns
⎯
⎯
Note : If the RDY setup time is insufficient, use the auto-ready function.
0.8*VCC
ECLK
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
Refer to the Hardware Manual for detailed Timing Charts
Hold Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min
Max
Pin floating ⇒ HAKX ↓ time
HAKX ↑ time ⇒ Pin valid time
tXHAL
HAKX
HAKX
tCYC − 20 tCYC + 20
tCYC − 20 tCYC + 20
ns
ns
⎯
tHAHV
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min
Max
Pin floating ⇒ HAKX ↓ time
HAKX ↑ time ⇒ Pin valid time
tXHAL
tHAHV
HAKX
HAKX
tCYC − 25 tCYC + 25
tCYC − 25 tCYC + 25
ns
ns
⎯
92
FME-MB96340 rev 10
MB96340 Series
0.8*VCC
HAKX
0.2*VCC
tHAHV
tXHAL
High-Z
0.8*VCC
0.2*VCC
Each pin
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96340 rev 10
93
MB96340 Series
USART timing
WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum
output timing described in the different tables must then be increased by 10ns.
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
VCC = AVCC= 4.5V VCC = AVCC= 3.0V
to 5.5V
to 4.5V
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYCI
tSLOVI
SCKn
4 tCLKP1
⎯
4 tCLKP1
⎯
ns
ns
SCK ↓ → SOT delay
time
SCKn,
SOTn
-20
+20
⎯
-30
+30
⎯
SOT → SCK ↑ delay
time
SCKn,
SOTn
N*tCLKP1
- 20 *1
N*tCLKP1 -
30 *1
tOVSHI
tIVSHI
Internal Shift
Clock Mode
ns
ns
ns
ns
ns
ns
ns
ns
SCKn,
SINn
tCLKP1 +
45
tCLKP1 +
55
Valid SIN → SCK ↑
⎯
⎯
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tSHIXI
0
⎯
0
⎯
Serial clock “L” pulse
width
tCLKP1 +
10
tCLKP1 +
10
tSLSHE
tSHSLE
tSLOVE
tIVSHE
tSHIXE
SCKn
SCKn
⎯
⎯
Serial clock “H” pulse
width
tCLKP1 +
10
tCLKP1 +
10
⎯
⎯
SCK ↓ → SOT delay
time
SCKn,
SOTn
2 tCLKP1
+ 45
2 tCLKP1
+ 55
⎯
⎯
External Shift
Clock Mode
SCKn,
SINn
tCLKP1/2
+ 10
tCLKP1/2+
Valid SIN → SCK ↑
⎯
⎯
⎯
⎯
10
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tCLKP1 +
10
tCLKP1 +
10
SCK fall time
SCK rise time
tFE
tRE
SCKn
SCKn
⎯
⎯
20
20
⎯
⎯
20
20
ns
ns
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
4*tCLKP1
N
2
5*tCLKP1, 6*tCLKP1
7*tCLKP1, 8*tCLKP1
...
3
4
...
94
FME-MB96340 rev 10
MB96340 Series
tSCYCI
SCK for
0.8*VCC
ESCR:SCES = 0
0.2*VCC
0.2*VCC
0.8*VCC
SCK for
0.8*VCC
ESCR:SCES = 1
0.2*VCC
tOVSHI
tSLOVI
0.8*VCC
0.2*VCC
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Internal Shift Clock Mode
tSLSHE
tSHSLE
SCK for
VIH
VIL
VIH
VIH
VIL
ESCR:SCES = 0
VIL
SCK for
VIH
VIH
ESCR:SCES = 1
VIL
VIL
tSLOVE
tFE
tRE
0.8*VCC
0.2*VCC
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
External Shift Clock Mode
FME-MB96340 rev 10
95
MB96340 Series
I2C Timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V)
Fast-mode*1
Standard-mode
Parameter
Symbol
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA↓→SCL↓
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
⎯
3.45
⎯
0.6
0
⎯
0.9
⎯
µs
µs
ns
µs
µs
Data hold time
SCL↓→SDA↓↑
Data set-up time
SDA↓↑→SCL↑
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL↑→SDA↑
⎯
⎯
Bus free time between a STOP and START
condition
⎯
⎯
Output fall time from 0.7*Vcc to 0.3*Vcc with
a bus capacitance from 10 pF to 400 pF
tof
Cb
tSP
20 + 0.1*Cb *2
250
400
n/a
20 + 0.1*Cb *2
250
400
ns
pF
ns
Capacitive load for each bus line
⎯
⎯
Pulse width of spikes which will be sup-
pressed by input noise filter
n/a
0
1*tCLKP1*3
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
*2 : Cb = capacitance of one bus line in pF.
*3 : tCLKP1 is the cycle time of the periperal clock CLKP1.
SDA
t
BUS
tSUDAT
t
HDSTA
t
LOW
SCL
tHIGH
t
HDSTA
t
HDDAT
t
SUSTA
tSUSTO
• VOH = 0.7 * VCC
• VOL = 0.3 * VCC
• CMOS Hysteresis 0.7/0.3 input selected
96
FME-MB96340 rev 10
MB96340 Series
5. Analog Digital Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Resolution
Symbol
Pin
Unit
Remarks
Min
Typ
Max
10
3
-
-
-
-
-
-
-
-
-
-
-
-
-
bit
Total error
LSB
Nonlinearity error
2.5 LSB
Differentialnonlinearity
error
-
-
-
1.9 LSB
AVRL - AVRL+ AVRL +
1.5 LSB 0.5 LSB 2.5 LSB
Zero transition voltage
VOT
ANn
ANn
V
V
Full scale transition
voltage
AVRH - AVRH - AVRH+
3.5 LSB 1.5 LSB 0.5 LSB
VFST
1.0
2.0
0.5
1.2
-
-
-
-
16,500 µs
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
TA ≤ 105 ˚C,
Compare time
Sampling time
-
-
-
-
-
-
-
µs
µs
µs
-1
-
-
+1
µA AVSS, AVRL < VI <
Analog input leakage
current (during conver-
sion)
AVCC, AVRH
IAIN
ANn
ANn
105 ˚C < TA ≤ 125 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
-1.2
+1.2
Analog input voltage
range
VAIN
AVRL
-
-
AVRH
AVcc
V
V
AVRH/
AVRH2
0.75
AVcc
AVRH
Reference voltage
range
0.25
AVCC
AVRL
IA
AVRL
AVcc
AVcc
AVSS
-
2.5
-
V
-
-
5
5
mA A/D Converter active
Power supply current
A/DConverternotop-
erated
IAH
µA
AVRH/
AVRL
IR
IRH
-
-
-
-
0.7
1
5
4
mA A/D Converter active
Reference voltage cur-
rent
AVRH/
AVRL
A/DConverternotop-
erated
-
-
µA
Offset between input
channels
ANn
LSB
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
FME-MB96340 rev 10
97
MB96340 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”)
and full-scale transition line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB,
from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
1.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
N: A/D converter digital output value
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
98
FME-MB96340 rev 10
MB96340 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
3FE
N + 1
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
3FD
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004
003
002
001
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Nonlinearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential nonlinearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
FME-MB96340 rev 10
99
MB96340 Series
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal
sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time
depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and
the AVcc voltage level. The following replacement model can be used for the calculation:
MCU
Analog
input
Rext
RADC
Comparator
Source
Cext
CIN
CADC
Sampling switch
Rext: external driving impedance
Cext: capacitance of PCB at A/D converter input
CIN: capacitance of MCU input pin: 15pF (max)
RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤ AVcc ≤ 5.5V
12kΩ (max) for 3.0V ≤ AVcc < 4.5V
CADC: sampling capacitance within MCU: 10pF (max)
The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement
model above can be used:
Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC)
• Do not select a sampling time below the absolute minimum permitted value
(0.5µs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 µs for 3.0V ≤ AVcc < 4.5V).
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. In this
case the internal sampling capacitance CADC will be charged out of this external capacitance.
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input
leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total
leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL
cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVRL| becomes smaller.
100
FME-MB96340 rev 10
MB96340 Series
6. Alarm Comparator
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
Alarm comparator
enabled in fast
mode (one channel)
IA5ALMF
-
25
45
µA
Alarm comparator
enabled in slow
mode (one channel)
Power supply current
AVCC
IA5ALMS
-
-
7
-
13
5
µA
µA
Alarm comparator
disabled
IA5ALMH
IALIN
-1
-3
-
-
+1
+3
µA TA = 25 ˚C
µA TA = 125 ˚C
ALARM pin input cur-
rent
ALARM pin input volt-
age range
VALIN
0
-
AVCC
V
V
V
External low threshold
high->low transition
0.36 * AVCC 0.36*AVCC
VEVTL(H->L)
VEVTL(L->H)
VEVTH(H->L)
VEVTH(L->H)
VIVTL(H->L)
VIVTL(L->H)
VIVTH(H->L)
VIVTH(L->H)
-
-0.25
-0.1
External low threshold
low->high transition
0.36*AVCC 0.36 * AVCC
-
+0.1
+0.25
INTREF = 0
Externalhighthreshold
high->low transition
0.78 * AVCC 0.78*AVCC
-
V
V
V
V
V
V
-0.25
-0.1
Externalhighthreshold
low->high transition
0.78*AVCC 0.78 * AVCC
+0.1
+0.25
Internal low threshold
high->low transition
0.9
-
1.1
-
ALARM0,
ALARM1
Internal low threshold
low->high transition
1.3
2.4
2.6
1.55
-
INTREF = 1
Internal high threshold
high->low transition
2.2
-
Internal high threshold
low->high transition
2.85
Switching hysteresis
VHYS
tCOMPF
tCOMPS
50
-
-
0.1
1
300
1
mV
µs
CMD = 1 (fast)
CMD = 0 (slow)
Comparison time
-
10
µs
Power-up stabilization
time after enabling
alarm comparator
Threshold levels
specified above are
not guaranteed
tPD
-
-
1
10
ms
Slow/Fast mode transi-
tion time
within this time
tCMD
100
500
µs
FME-MB96340 rev 10
101
MB96340 Series
Comparator
Output
H
L
VALIN
VxVTx(H->L)
VHYS
VxVTx(L->H)
102
FME-MB96340 rev 10
MB96340 Series
7. Low Voltage Detector characteristics
(TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Value *1
Value *2
Parameter
Symbol
Unit
Remarks
Min
Max
Min
Max
After power-up or change
of detection level
Stabilization time TLVDSTAB
-
75
-
110
µs
CILCR:LVL[3:0]=”0000”
CILCR:LVL[3:0]=”0001”
CILCR:LVL[3:0]=”0010”
CILCR:LVL[3:0]=”0011”
CILCR:LVL[3:0]=”0100”
CILCR:LVL[3:0]=”0101”
CILCR:LVL[3:0]=”0110”
CILCR:LVL[3:0]=”0111”
CILCR:LVL[3:0]=”1000”
CILCR:LVL[3:0]=”1001”
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
Level 12
Level 13
Level 14
Level 15
VDL0
VDL1
VDL2
VDL3
VDL4
VDL5
VDL6
VDL7
VDL8
VDL9
VDL10
VDL11
VDL12
VDL13
VDL14
VDL15
2.7
2.9
3.1
3.5
3.6
3.7
3.8
3.9
4.0
4.1
2.9
3.1
2.5
2.8
3
2.9
3.2
3.4
3.8
3.95
4.1
4.2
4.3
4.4
4.5
V
V
V
V
V
V
V
V
V
V
3.3
3.75
3.85
3.95
4.05
4.15
4.25
4.35
3.35
3.5
3.6
3.7
3.8
3.9
3.95
not used
not used
not used
2.6
not used
not used
not used
not used
not used
CILCR:LVL[3:0]=”1100”
3
V
not used
not used
not used
*1: valid for all devices except devices listed under “*2”
*2: valid for: MB96F345
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
V
dV
dt
-----
µs
For correct detection, the slope of the voltage level must satisfy
≤ 0.004
.
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of
“Level 0” (VDL0_MIN). The electrical characteristics however are only valid in the specified range (usually down to
3.0V).
FME-MB96340 rev 10
103
MB96340 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the
reset and startup behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
VDLx, Max
VDLx, Min
dV
dt
Time [s]
Power Reset Extension Time
Low Voltage Reset Assertion
Normal Operation
104
FME-MB96340 rev 10
MB96340 Series
8. FLASH memory program/erase characteristics
(TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Sector erase time
Unit
Remarks
Min
Typ
Max
Without erasure pre-program-
ming time
-
0.9
3.6
s
Program/Data Flash (Main Flash)
Without erasure pre-program-
ming time
-
-
0.5
0.8
2
s
s
Sector erase time
Data Flash
Including erasure pre-program-
ming time
3.6
Without erasure pre-program-
ming time (n is the number of
Flash sector of the device)
Chip erase time
-
n*0.9
n*3.6
s
Program/Data Flash (Main Flash)
Without erasure pre-program-
ming time
-
-
2.5
3.7
10
s
s
Chip erase time
Data Flash
Including erasure pre-program-
ming time
16.4
Word (16-bit width) programming time
Program/Data Flash (Main Flash)
Byte (8-bit width) programming time
Data Flash
Without overhead time for sub-
mitting write command
-
-
23
15
370
100
us
us
Without overhead time for sub-
mitting write command
100 000 Program/Erase cycles
are under evaluation by Fujitsu
Microelectronics
Program/Erase cycle
10 000
20
-
-
-
-
cycle
year
Flash data retention time
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
FME-MB96340 rev 10
105
MB96340 Series
■ EXAMPLE CHARACTERISTICS
1. Temperature dependency of power supply currents
The following diagrams show the current consumption of samples with typical wafer process parameters in differ-
ent operation modes.
Common condition for all operation modes:
•
V
= AV = 5.0V
CC CC
•
•
Main clock = 4MHz external clock
Sub clock = 32kHz external clock
Operation mode details:
Mode name
Details
PLL Run 56
PLL Run mode current I
with the following settings:
CCPLL
•
•
f
f
= f
= f
= f
= 56MHz
CLKP1
CLKS1
CLKS2
CLKB
= 28MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
•
2 Flash/ROM wait states (MTCRA=233A )
H
RC oscillator and Sub oscillator stopped
PLL Run 48
PLL Run mode current I
with the following settings:
CCPLL
•
•
•
f
f
f
= f
= 96MHz
CLKS2
CLKS1
= f
= 48MHz
CLKP1
CLKB
= 24MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
•
1 Flash/ROM wait states (MTCRA=6B09 )
H
RC oscillator and Sub oscillator stopped
PLL Run 40
PLL Run mode current I
with the following settings:
CCPLL
•
•
•
f
f
f
= f
= 80MHz
CLKS2
CLKS1
= f
= 40MHz
CLKP1
CLKB
= 20MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
•
1 Flash/ROM wait states (MTCRA=6B09 )
H
RC oscillator and Sub oscillator stopped
PLL Run 36
PLL Run mode current I
with the following settings:
CCPLL
•
•
•
f
f
f
= f
= 72MHz
CLKS2
CLKS1
= f
= 36MHz
CLKP1
CLKB
= 18MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
•
1 Flash/ROM wait states (MTCRA=6B09 )
H
RC oscillator and Sub oscillator stopped
106
FME-MB96340 rev 10
MB96340 Series
Mode name
Details
PLL Run 24
PLL Run mode current I
with the following settings:
CCPLL
•
•
f
f
= f
= 48MHz
CLKS2
CLKS1
= f
= f
= 24MHz
CLKP2
CLKB
CLKP1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
•
0 Flash/ROM wait states (MTCRA=2208 )
H
RC oscillator and Sub oscillator stopped
Main Run
Main Run mode current I
with the following settings:
CCMAIN
•
f
= f
= f
= f
= f
= 4MHz
CLKP2
CLKS1
CLKS2
CLKB
CLKP1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, RC oscillator and Sub oscillator stopped
RC Run 2M
RC Run mode current I
with the following settings:
CCRCH
•
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
= f = f = f = f = 2MHz
f
CLKS1
CLKS2
CLKB
CLKP1
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, Main oscillator and Sub oscillator stopped
RC Run 100k
RC Run mode current I
with the following settings:
CCRCL
•
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
= f = f = f = f = 100kHz
f
CLKS1
CLKS2
CLKB
CLKP1
CLKP2
•
•
Regulator in Low Power Mode A (SMCR:LPMS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, Main oscillator and Sub oscillator stopped
Sub Run
Sub Run mode current I
with the following settings:
CCSUB
•
f
= f
= f
= f
= f
= 32kHz
CLKP2
CLKS1
CLKS2
CLKB
CLKP1
•
•
Regulator in Low Power Mode A (by hardware)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
•
1 Flash/ROM wait states (MTCRA=0239 )
H
PLL, RC oscillator and Main oscillator stopped
PLL Sleep 56
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
f
f
= f
= f
= 56MHz
CLKP1
CLKS1
CLKS2
= 28MHz
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
RC oscillator and Sub oscillator stopped
FME-MB96340 rev 10
107
MB96340 Series
Mode name
Details
PLL Sleep 48
PLL Sleep 40
PLL Sleep 36
PLL Sleep 24
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
•
f
f
f
= f
= 96MHz
CLKS2
CLKS1
CLKP1
CLKP2
= 48MHz
= 24MHz
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
RC oscillator and Sub oscillator stopped
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
•
f
f
f
= f
= 80MHz
CLKS2
CLKS1
CLKP1
CLKP2
= 40MHz
= 20MHz
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
RC oscillator and Sub oscillator stopped
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
•
f
f
f
= f
= 72MHz
CLKS2
CLKS1
CLKP1
CLKP2
= 36MHz
= 18MHz
•
•
Regulator in High Power Mode
Core voltage at 1.9V (VRCR:HPM[1:0] = 11 )
B
•
RC oscillator and Sub oscillator stopped
PLL Sleep mode current I
with the following settings:
CCSPLL
•
•
f
f
= f
= f
= 48MHz
CLKS1
CLKS2
= 24MHz
CLKP1
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
RC oscillator and Sub oscillator stopped
Main Sleep
Main Sleep mode current I
with the following settings:
CCSMAIN
•
f
= f
= f
= f
= 4MHz
CLKP2
CLKS1
CLKS2
CLKP1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
PLL, RC oscillator and Sub oscillator stopped
RC Sleep 2M
RC Sleep mode current I
with the following settings:
CCSRCH
•
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
= f = f = f = 2MHz
f
CLKS1
CLKS2
CLKP1
CLKP2
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
PLL, Main oscillator and Sub oscillator stopped
RC Sleep 100k RC Sleep mode current I
with the following settings:
CCSRCL
•
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
= f = f = f = 100kHz
f
CLKS1
CLKS2
CLKP1
CLKP2
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, Main oscillator and Sub oscillator stopped
108
FME-MB96340 rev 10
MB96340 Series
Mode name
Details
Sub Sleep
Sub Sleep mode current I
with the following settings:
CCSSUB
•
f
= f
= f
= f
= 32kHz
CLKP2
CLKS1
CLKS2
CLKP1
•
•
Regulator in Low Power Mode A (by hardware)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, RC oscillator and Main oscillator stopped
PLL Timer 48
Main Timer
RC Timer 2M
PLL Timer mode current I
with the following settings:
CCTPLL
•
f
= f
= 48MHz
CLKS2
CLKS1
•
•
Regulator in High Power Mode
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 )
B
•
RC oscillator and Sub oscillator stopped
Main Timer mode current I
with the following settings:
CCTMAIN
•
f
= f
= 4MHz
CLKS2
CLKS1
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, RC oscillator and Sub oscillator stopped
RC Timer mode current I
with the following settings:
CCTRCH
•
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
= f = 2MHz
f
CLKS1
CLKS2
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, Main oscillator and Sub oscillator stopped
RC Timer 100k RC Timer mode current I
with the following settings:
CCTRCL
•
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
= f = 100kHz
f
CLKS1
CLKS2
•
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, Main oscillator and Sub oscillator stopped
Sub Timer
Sub Timer mode current I
with the following settings:
CCTSUB
•
f
= f
= 32kHz
CLKS2
CLKS1
•
•
Regulator in Low Power Mode A (by hardware)
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110 )
B
•
PLL, RC oscillator and Main oscillator stopped
Stop 1.8V
Stop 1.2V
Stop mode current I
with the following settings:
CCH
•
•
Regulator in Low Power Mode B (by hardware)
Core voltage at 1.8V (VRCR:LPMB[2:0] = 110 )
B
Stop mode current I
with the following settings:
CCH
•
•
Regulator in Low Power Mode B (by hardware)
Core voltage at 1.2V (VRCR:LPMB[2:0] = 000 )
B
FME-MB96340 rev 10
109
MB96340 Series
MB96345/346 PLL Run and Sleep mode currents
25
20
15
10
5
PLL Run 48
PLL Run 56
PLL Run 24
PLL Sleep 48
PLL Sleep 56
PLL Sleep 24
0
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96345/346 operation modes with medium currents
3
2.5
Main Run
2
RC Run 2M
1.5
Main Sleep
PLL Timer 48
1
RC Sleep 2M
0.5
0
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
110
FME-MB96340 rev 10
MB96340 Series
MB96345/346 Low power mode currents
1
0.1
Main Timer
RC Run 100k
RC Timer 2M
RC Sleep 100k
Sub Run
Sub Sleep
Sub Timer
RC Timer 100k
Stop 1.8V
Stop 1.2V
0.01
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96F345 PLL Run and Sleep mode currents
40
30
20
10
0
PLL Run 40
PLL Run 24
PLL Sleep 40
PLL Sleep 24
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
FME-MB96340 rev 10
111
MB96340 Series
MB96F345 operation modes with medium currents
5
4
3
2
1
0
Main Run
RC Run 2M
PLL Timer 48
Main Sleep
RC Sleep 2M
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96F345 Low power mode currents
1
RC Run 100k
0.1
Sub Run
Main Timer
RC Timer 2M
Sub Sleep
RC Sleep 100k
Sub Timer
RC Timer 100k
0.01
Stop 1.8V
Stop 1.2V
0.001
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
112
FME-MB96340 rev 10
MB96340 Series
MB96F346/F347/F348Y/R/A PLL Run and Sleep mode currents
50
40
30
20
10
0
PLL Run 56
PLL Run 36
PLL Run 24
PLL Sleep 56
PLL Sleep 36
PLL Sleep 24
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96F346/F347/F348Y/R/A operation modes with medium currents
5
4
3
2
1
0
Main Run
RC Run 2M
PLL Timer 48
Main Sleep
RC Sleep 2M
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
FME-MB96340 rev 10
113
MB96340 Series
MB96F346/F347/F348Y/R/A Low power mode currents
1
RC Run 100k
Sub Run
0.1
RC Timer 2M
Main Timer
RC Sleep 100k
Sub Sleep
Sub Timer
RC Timer 100k
Stop 1.8V
Stop 1.2V
0.01
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96F348T/H/C PLL Run and Sleep mode currents
50
40
30
20
10
0
PLL Run 48
PLL Run 56
PLL Run 24
PLL Sleep 48
PLL Sleep 56
PLL Sleep 24
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
114
FME-MB96340 rev 10
MB96340 Series
MB96F348T/H/C operation modes with medium currents
6
5
4
3
2
1
0
Main Run
RC Run 2M
PLL Timer 48
Main Sleep
RC Sleep 2M
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
MB96F348T/H/C Low power mode currents
1
RC Run 100k
0.1
Sub Run
Main Timer
RC Timer 2M
RC Sleep 100k
Sub Sleep
Sub Timer
RC Timer 100k
0.01
Stop 1.8V
Stop 1.2V
0.001
-60
-40
-20
0
20
40
60
80
100
120
Ta [˚C]
FME-MB96340 rev 10
115
MB96340 Series
2. Frequency dependency of power supply currents in PLL Run mode
The following diagrams show the current consumption of samples with typical wafer process parameters in PLL
Run mode at different frequencies and Flash timing settings.
Measurement conditions:
•
V
= AV = 5.0V
CC CC
•
•
Ta = 25˚C
f
f
f
f
= f
= f
= f
= f
or f
= 2*f
as described in diagram
CLKB
CLKS1
CLKS2
CLKP1
CLKP2
CLKB
CLKS1
•
•
•
•
CLKS1
CLKB
/2
CLKB
Core voltage at 1.8V (VRCR:HPM[1:0] = 10 ) or 1.9V (VRCR:HPM[1:0] = 11 ) as described in diagram
B
B
•
•
Main clock = 4MHz external clock
Flash memory timing settings:
• MTCRA=2128 /2208 (0 Flash wait states, f
= 2*f
)
CLKB
H
H
CLKS1
• MTCRA=0239 /2129 (1 Flash wait state, f
= f
CLKB
)
H
H
CLKS1
• MTCRA=4C09 /6B09 (1 Flash wait state, f
= 2*f
)
CLKB
H
H
CLKS1
• MTCRA=233A (2 Flash wait states, f
= f
)
CLKB
H
CLKS1
•
Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):
• 0 Flash wait states: 0.5
• 1 Flash wait states: 0.33
• 2 Flash wait states: 0.25
MB96F345 PLL Run mode currents
40
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
35
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
30
25
0 Flash wait states
2 Flash wait states
(CLKS1=2*CLKB, 1.8V)
(CLKS1=CLKB, 1.9V)
20
2 Flash wait states
(CLKS1=CLKB, 1.8V)
15
10
1 Flash wait state
(CLKS1=CLKB, 1.8V)
: Specified in "DC characteristics"
5
0
0
4
8
12
16
20
CLKB/CLKP1 (MHz)
24
28
32
36
40
116
FME-MB96340 rev 10
MB96340 Series
MB96F346/F347/F348Y/R/A PLL Run mode currents
50
45
40
35
30
25
20
15
10
5
2 Flash wait states
(CLKS1=CLKB, 1.9V)
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
1 Flash wait state
(CLKS1=CLKB, 1.8V)
: Specified in "DC characteristics"
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
CLKB/CLKP1 (MHz)
MB96F348T/H/C PLL Run mode currents
50
45
40
35
30
25
20
15
10
5
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)
2 Flash wait states
(CLKS1=CLKB, 1.9V)
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
0 Flash wait states
(CLKS1=2*CLKB, 1.8V)
2 Flash wait states
(CLKS1=CLKB, 1.8V)
1 Flash wait state
(CLKS1=CLKB, 1.8V)
: Specified in "DC characteristics"
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
CLKB/CLKP1 (MHz)
FME-MB96340 rev 10
117
MB96340 Series
■ PACKAGE DIMENSION MB96(F)34x LQFP 100P
100-pin plastic LQFP
Lead pitch
0.50 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
(Mounting height)
–
0.10 .059 +.008
–.004
INDEX
0.10
±
0.10
(.004
±
.004)
(Stand off)
100
26
0
˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60
(.024
±
±
0.15
.006)
1
25
0.50(.020)
0.20±0.05
(.008 .002)
0.145
±
0.055
.0022)
M
0.08(.003)
±
(.0057
±
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2
2005 FUJITSU LIMITED F100031S-c-2-1
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
118
FME-MB96340 rev 10
MB96340 Series
■ PACKAGE DIMENSION MB96(F)34x QFP 100P
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 mm × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M22)
100-pin plastic QFP
(FPT-100P-M22)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8
°
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2006-2008 FUJITSU MICROELECTRONICS LIMITED F100033S-c-1-2
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
FME-MB96340 rev 10
119
MB96340 Series
■ ORDERING INFORMATION
MCU with CAN controller
Part number
Persistent
Subclock Low Volt-
age Reset
Flash/ROM
Package
MB96345YSA PQC-GSE2 *1
MB96345RSA PQC-GSE2 *1
MB96345YWA PQC-GSE2 *1
MB96345RWA PQC-GSE2 *1
MB96345YSA PMC-GSE2 *1
MB96345RSA PMC-GSE2 *1
MB96345YWA PMC-GSE2 *1
MB96345RWA PMC-GSE2 *1
MB96346YSA PQC-GSE2 *1
MB96346RSA PQC-GSE2 *1
MB96346YWA PQC-GSE2 *1
MB96346RWA PQC-GSE2 *1
MB96346YSA PMC-GSE2 *1
MB96346RSA PMC-GSE2 *1
MB96346YWA PMC-GSE2 *1
MB96346RWA PMC-GSE2 *1
MB96F345FSB PQC-GSE2 *1
MB96F345DSB PQC-GSE2 *1
MB96F345FWB PQC-GSE2 *1
MB96F345DWB PQC-GSE2 *1
MB96F345FSB PMC-GSE2 *1
MB96F345DSB PMC-GSE2 *1
MB96F345FWB PMC-GSE2 *1
MB96F345DWB PMC-GSE2 *1
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
ROM (160KB)
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
ROM (288KB)
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Flash A (160KB)
Data Flash A (64KB)
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
120
FME-MB96340 rev 10
MB96340 Series
MCU with CAN controller
Persistent
Subclock Low Volt-
age Reset
Part number
Flash/ROM
Package
MB96F346YSB PQC-GSE2
MB96F346RSB PQC-GSE2
MB96F346YWB PQC-GSE2
MB96F346RWB PQC-GSE2
MB96F346YSB PMC-GSE2
MB96F346RSB PMC-GSE2
MB96F346YWB PMC-GSE2
MB96F346RWB PMC-GSE2
MB96F346YSC PQC-GSE2*1
MB96F346RSC PQC-GSE2*1
MB96F346YWC PQC-GSE2*1
MB96F346RWC PQC-GSE2*1
MB96F346YSC PMC-GSE2*1
MB96F346RSC PMC-GSE2*1
MB96F346YWC PMC-GSE2*1
MB96F346RWC PMC-GSE2*1
MB96F347YSB PQC-GSE2
MB96F347RSB PQC-GSE2
MB96F347YWB PQC-GSE2
MB96F347RWB PQC-GSE2
MB96F347YSB PMC-GSE2
MB96F347RSB PMC-GSE2
MB96F347YWB PMC-GSE2
MB96F347RWB PMC-GSE2
MB96F347YSC PQC-GSE2*1
MB96F347RSC PQC-GSE2*1
MB96F347YWC PQC-GSE2*1
MB96F347RWC PQC-GSE2*1
MB96F347YSC PMC-GSE2*1
MB96F347RSC PMC-GSE2*1
MB96F347YWC PMC-GSE2*1
MB96F347RWC PMC-GSE2*1
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Flash A (288KB)
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Flash A (416KB)
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
FME-MB96340 rev 10
121
MB96340 Series
MCU with CAN controller
Persistent
Subclock Low Volt-
age Reset
Part number
Flash/ROM
Package
MB96F348YSB PQC-GSE2
MB96F348RSB PQC-GSE2
MB96F348YWB PQC-GSE2
MB96F348RWB PQC-GSE2
MB96F348YSB PMC-GSE2
MB96F348RSB PMC-GSE2
MB96F348YWB PMC-GSE2
MB96F348RWB PMC-GSE2
MB96F348YSC PQC-GSE2*1
MB96F348RSC PQC-GSE2*1
MB96F348YWC PQC-GSE2*1
MB96F348RWC PQC-GSE2*1
MB96F348YSC PMC-GSE2*1
MB96F348RSC PMC-GSE2*1
MB96F348YWC PMC-GSE2*1
MB96F348RWC PMC-GSE2*1
MB96F348TSC PQC-GSE2
MB96F348HSC PQC-GSE2
MB96F348TWC PQC-GSE2
MB96F348HWC PQC-GSE2
MB96F348TSC PMC-GSE2
MB96F348HSC PMC-GSE2
MB96F348TWC PMC-GSE2
MB96F348HWC PMC-GSE2
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Flash A (544KB)
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Flash A (544KB)
Flash B (32KB)
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
MB96V300BRB-ES
(for evaluation)
416 pin Plastic BGA
(BGA-416P-M02)
Emulated by ext. RAM
Yes
No
122
FME-MB96340 rev 10
MB96340 Series
MCU without CAN controller
Part number
Flash/ROM
Subclock
No
Package
MB96F346ASB PQC-GSE2
MB96F346AWB PQC-GSE2
MB96F346ASB PMC-GSE2
MB96F346AWB PMC-GSE2
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
Flash A (288KB)
Flash A (416KB)
Flash A (544KB)
MB96F346ASC PQC-GSE2*1
MB96F346AWC PQC-GSE2*1
MB96F346ASC PMC-GSE2*1
MB96F346AWC PMC-GSE2*1
MB96F347ASB PQC-GSE2
MB96F347AWB PQC-GSE2
MB96F347ASB PMC-GSE2
MB96F347AWB PMC-GSE2
MB96F347ASC PQC-GSE2*1
MB96F347AWC PQC-GSE2*1
MB96F347ASC PMC-GSE2*1
MB96F347AWC PMC-GSE2*1
MB96F348ASB PQC-GSE2
MB96F348AWB PQC-GSE2
MB96F348ASB PMC-GSE2
MB96F348AWB PMC-GSE2
MB96F348ASC PQC-GSE2*1
MB96F348AWC PQC-GSE2*1
MB96F348ASC PMC-GSE2*1
MB96F348AWC PMC-GSE2*1
MB96F348CSC PQC-GSE2
MB96F348CWC PQC-GSE2
MB96F348CSC PMC-GSE2
MB96F348CWC PMC-GSE2
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
Flash A (544KB)
Flash B (32KB)
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
*1: These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
This datasheet is also valid for the following outdated devices:
MB96F346YSA, MB96F346RSA, MB96F346YWA, MB96F346RWA,
MB96F347YSA, MB96F347RSA, MB96F347YWA, MB96F347RWA,
MB96F348YSA, MB96F348RSA, MB96F348YWA, MB96F348RWA,
MB96F348TSB, MB96F348HSB, MB96F348TWB, MB96F348HWB,
FME-MB96340 rev 10
123
MB96340 Series
MB96F346ASA, MB96F346AWA,
MB96F347ASA, MB96F347AWA,
MB96F348ASA, MB96F348AWA,
MB96F348CSB, MB96F348CWB
124
FME-MB96340 rev 10
MB96340 Series
■ REVISION HISTORY
Revision
Date
Modification
Prelim 1
Prelim 2
Prelim 3
Prelim 4
2007-05-07 Creation
2007-05-10 External bus hold timing update
2007-05-23 Electrical characteristics updates
2007-08-02 Electrical characteristics updates, Product lineup, changes and ordering
information
Prelim 5
2007-09-12 Addition of the electrical characteristic examples and the LVD characteristics
specifications, updates of the DC characteristics. Pin circuit type drawing
modifications.
Prelim 6
Prelim 7
2007-11-21 LVD typo correction.
Update of the DC characteristics. Typos corrections.
2007-12-04 Absolute maximum rating asterisks numbering corrected.
Typos page 59: Hardware -> Hardware.
IO map table regenerated.
Typos corrections.
IO circuit drawings modified.
Renaming of the Main/Satellite Flash into Flash memory A/B.
Memory map reworked.
FME-MB96340 rev 10
125
MB96340 Series
Revision
Prelim 8
Date
Modification
2008-02-04 • Satellite Flash -> 32kB Data Flash
• MB96345 added (under development)
• MB96F348 TSA/HSA/TWA/HWA removed (outdated devices)
• Block diagram and pin assignment corrected (existing resource pins)
• Pin function table corrected
• I/O circuit type diagrams corrected
• Memory map cleaned up
• "Flash sector configuration" replaced by corrected "User ROM Memory map
for Flash devices", “ROM configuration” replaced by “User ROM Memory map
for Mask ROM devices”
• Parallel Flash programming pinning removed
• IO map table regenerated:
- Port register: Naming style corrected
- Memory control registers renamed (Main/Sat -> A/B)
- addresses after 000BFFh removed
• Absolute maximum ratings: Pd and Ta specified more precisely
• oscillator input levels in oscillation mode with external clock added
• Run and Sleep mode currents: 96/48MHz and 72/36MHz settings added
• Run mode current spec in 48/24MHz mode corrected
• Maximum CLKS1/2 frequency for all devices correctly specified
• Maximum CLKP2 for MB96F34xY/R/Axx corrected
• External bus timings: missing conditions added and readability improved
• Alarm comparator spec updated (transition voltages defined)
• MB96V300A removed
• Ordering information updated
• Typos and formatting corrected
126
FME-MB96340 rev 10
MB96340 Series
Revision
9
Date
Modification
2009-01-09 • Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly
style changes and official notes and disclaimer added)
• Numbering of Electrical Characteristics subchapters automated
• Note about devices under development modified
• I/O map: Note added about reserved addresses
• ICCSPLL for CLKS1=96MHz mode: increased by 1mA
• Serial programming interface: Note about handshaking pins improved
• specified AD converter channel offset to 4LSB
• package code of MB96V300 corrected in ordering information
• Added voltage condition to pull-up resistance spec
• Lineup: Term “Data Flash” replaced by “independent 32KB Flash”
• Ordering information: column “Independent 32KB Data Flash” replaced by new
column “Flash/ROM”, column “Remarks” removed
• Official package dimension drawing with additional notes added
• Empty pages removed
• Alarm comparator: Power supply current max values increased, comparison
timereduced, modetransitiontimeandpower-upstabilizationtimenewlyadded
• Handling devices: Notes added about Serial communication and about using
ceramic resonators.
• Feature list and AC Characteristics: 16MHz maximum frequency is valid for
crystal oscillators. For resonators, maximum frequency depends on Q-factor
• AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz
• VOL3 spec improved: spec valid for 3mA load for full Vcc range
• MB96F345 added
• Preliminary DC spec of MB96345/346 added
• Permitted power dissipation of Flash devices in QFP package improved
• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted
• “Preliminary” watermark removed
FME-MB96340 rev 10
127
MB96340 Series
FME-MB96340 rev 10
Revision
10
Date
Modification
2010-06-23 • I/O map: IOABK0-5 added at address 000A00H-000A05H
• Ordering Information: Suffix “A” added to all MB96F345 device versions
• AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg
• Corrected MB96F345 part names in ordering information
• Low voltage detector: Detection levels of MB96F345 updated
• Example characteristics updated, new figures added showing dependency of
PLL Run mode current on frequency
• Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new
spec items in PLL Run/Sleep mode, small adjustment of most other values)
• Note added that PLL phase jitter spec does not include jitter coming from Main
clock
• Alarm comparator: Maximum power-up stabilization time increased to 10ms
• Removed PHDR register from IO map
• Note added in DC characteristics how to select driving strength of ports
• I2C AC spec updated: tof, Cb and tSP spec added, wrong footnotes and Con-
dition removed
• I/OCircuittype:Noteaddedfortype“N”(slewratecontrolaccordingtoI2Cspec)
• Package dimension: Added the following sentence under the figure: “Please
confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/”
• AD converter: Impact of input pin capacitance and external capacitance added
to formula for calculation of the sampling time
• Added specification of RC clock stabilization time
• Feature description I2C: ‘8-bit addressing’ corrected to ‘7-bit addressing’
• Feature description PPG: ‘Reload timer overflow as clock input’ corrected to
‘Reload timer underflow as clock input’
• Company name updated on the cover page: Fujitsu Microelectronics Limited -
> Fujitsu Semiconductor Limited
• ICCLVD specification updated, at 125deg typical value is 7uA and maximum
value is 20uA
• Ordering information: added devices under development MB96F346A*C,
MB96F347A*C, MB96F348A*C, MB96F346Y*C, MB96F347Y*C,
MB96F348Y*C, MB96F346R*C, MB96F347R*C, MB96F348R*C
MB96340 Series
FME-MB96340 rev 10
129
MB96340 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-
ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
130
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