MB96F347YSAPMC-GSE2 [FUJITSU]
16-bit Proprietary Microcontroller;
| 型号： | MB96F347YSAPMC-GSE2 |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总118页 (文件大小：1357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB96340
SPECIFICATION
FME-MB96340 rev 5
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96340 Series
■ DESCRIPTION
MB96340 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimised by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
FME/EMDC- 2007-9-12MB96340_DS_cover.fm
MB96340 Series
Specification
2
FME/EMDC- 2007-9-12
MB96340_DS_cover.fm
Specification
MB96340
■ FEATURES
Feature
Description
Technology
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 56 MHz internal, 17.8 ns instruction cycle time
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
CPU
• 8-byte instruction execution queue
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier (x1..25, x1 when PLL stop)
• 3-16 MHz external quartz clock, up to 4MHz external clock
• 32-100 kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and save startup, oscillator stop detection,
watchdog
System clock
• Clock source selectable from main- and subclock oscillator (partnumber suffix “W”)
on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
and low power consumption figures
On-chip voltage regula-
tor
Low voltage reset
Code Security
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
• Replaces ROM content
Memory Patch Function
DMA
• Can also be used to implement embedded debug support
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
Interrupts
Timers
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
• Two independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
3
MB96340 Series
Specification
Feature
Description
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• Up to 400 kbit/s
USART
I2C
• Master and Slave functionality, 8-bit and 10-bit addressing
• SAR-type
• 10bit resolution
A/D converter
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
A/D Converter Refer- • 2 independant positive A/D converter reference voltages available
ence Voltage switch
• 16-bit wide
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
• Event count function
Reload Timers
Free Running Timers
Input Capture Units
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 , 1/27 ,1/28 of
peripheral clock frequency
• 16-bit wide
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
• 16-bit wide
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
4
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
Specification
MB96340
Feature
Description
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
• PWM operation and one-shot operation
Programmable Pulse
Generator
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer overflow as clock input
• Can be triggered by software or reload timer
• Can be clocked either from sub oscillator (devices with partnumber suffix “W”),main
oscillator or from the RC oscillator
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
Real Time Clock
• Read/write accessible second/minute/hour registers
• Can signal interrupts every halfsecond/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32
kHz clock input (devices with partnumber suffix “W”) clock input
• Edge sensitive or level sensitive
• Interrupt mask and pending bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
External Interrupts
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
Non Maskable Interrupt
• Pin shared with external interrupt 0.
• 8-bit or 16-bit bidirectional data
• Up to 24-bit addresses
• 6 chip select signals
External bus interface • Multiplexed address/data lines
• Wait state request
• External bus master possible
• Timing programmable
• Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
Alarm comparators
• Threshold voltages defined externally or generated internally
• Status is readable, interrupts can be masked separately
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
5
MB96340 Series
Specification
Feature
Description
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
• Bit-wise programmable as input/output or peripheral signal
• Bit-wise programmable input enable
I/O Ports
Package
• Bit-wise programmable input levels (Automotive / CMOS-Schmitt trigger / TTL)
• Bit-wise programmable pull-up resistor
• Bit-wise programmable output driving strength for EMI optimization
• 100-pin plastic QFP and LQFP
• Supports automatic programming, Embedded AlgorithmTM*1
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles : 10,000 times
Flash Memory
• Data retention time : 20 years
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash
• Low voltage detection during Flash erase
*1 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
6
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
Specification
MB96340
■ PRODUCT LINEUP
Features
MB96V300
Evaluation sample
MB9634x
Flash product: MB96F34x
Mask ROM product: MB9634x
Product type
Product options
YS
RS
YW
RW
TS
LVD persistently on / Single clock devices
LVD can be disabled / Single clock devices
LVD persistently on / Dual clock devices
LVD can be disabled / Dual clock devices
Satellite Flash / LVD persistently on / Single clock devices
Satellite Flash / LVD can be disabled / Single clock devices
Satellite Flash / LVD persistently on / Dual clock devices
Satellite Flash / LVD can be disabled / Dual clock devices
HS
TW
HW
NA
No CAN / No Satellite Flash / LVD persistently on / Single clock
devices
AS
CS
No CAN / /Satellite Flash / LVD can be disabled / Single clock
devices
No CAN / No Satellite Flash / LVD persistently on / Dual clock
devices
AW
CW
No CAN / Satellite Flash / LVD can be disabled / Dual clock devices
Flash/
RAM
ROM
128kB
288kB
416kB
544kB
6kB
MB96344R, MB96344Y
16kB
16kB
24kB
MB96F346R, MB96346R, MB96F346Y, MB96346Y, MB96F346A
MB96F347R, MB96347R, MB96F347Y, MB96347Y, MB96F347A
MB96F348R, MB96F348Y, MB96F348A
ROM/Flash memory emulation
by external RAM,
92kB internal RAM
Main:
544kB,
Sat.:
MB96F348C,
MB96F348H, MB96F348T
24kB
32kB
Package
BGA416
FPT-100P-M20
FPT-100P-M22
DMA
16 channels
6 channels
7 channels
USART
10 channels
MB96F348 TSA/HSA/TWA/HWA: 4 channels
I2C
2 channels
2 channel
A/D Converter
40 channels
24 channels
FME/EMDC- 2007-9-12
MB96340_DS_lineup.fm
7
MB96340 Series
Specification
Features
MB96V300
MB9634x
A/D Converter
Reference
yes
yes
Voltage switch
16-bit Reload
Timer
6 channels
4 channels
12 channels
12 channels
4 channels
2 channels
8 channels
8 channels
16-bit Free-
Running Timer
16-bit Output
Compare
16-bit Input
Capture
16-bit
Programmable
Pulse Generator
20 channels
5 channels
16 channels
2 channels
CAN Interface
(not available on
MB963xxA,
MB963xxC)
External
Interrupts
16 channels
Non-Maskable
Interrupt
1 channel
1
Real Time Clock
MB96F348TSA/HSA/TWA/HWA: not available
80 for part number with suffix "W", 82 for part number with suffix "S"
2 channels
I/O Ports
136
Yes
Alarm comparator
External bus
interface
Multiplexed
Chip select
6 signal
Clock output
function
2 channels
Low voltage reset
Reset is generated when supply voltage is below minimum.
Yes
On-chip RC-
oscillator
8
FME/EMDC- 2007-9-12
MB96340_DS_lineup.fm
Specification
MB96340
■ BLOCK DIAGRAM
AD00 ... AD15
A16 ... A23
ALE
RDX
X0, X1
WRLX, WRHX
HRQ
X0A, X1A
RSTX
MD0...MD2
HAKX
NMI
RDY
ECLK
LBX, UBX
CS0 ... CS5
Memory Patch
Clock &
Mode Controller
Interrupt
Controller
External Bus
Interface
Main Flash
Memory
Satellite Flash
Memory 1)
16FX
CPU
Unit
16FX Core Bus (CLKB)
Voltage
Regulator
DMA
Controller
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Watchdog
RAM
Boot ROM
VCC
VSS
C
SDA0 ... SDA1
SCL0 ... SCL1
I2C
2 ch.
CAN
Interface
2 ch.
TX0, TX1
RX0, RX1
AVCC
AVSS
10-bit ADC
24 ch.
AVRH
AVRL
AN0 ... AN23
ADTG
16-bit Reload
Timer
TIN0 ... TIN3
SIN0...SIN3, SIN72)...SIN92)
SOT0...SOT3, SOT72)...SOT92)
SCK0...SCK3, SCK72)...SCK92)
TOT0 ... TOT3
USART
7 ch.
4 ch.
FRCK0
IN0 ... IN3
OUT0 ... OUT3
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
ALARM0
ALARM1
Alarm
Comparator
2 ch.
FRCK1
IN4 ... IN7
OUT4 ... OUT7
I/O Timer 1
ICU 4/5/6/7
OCU 4/5/6/7
TTG0 ... TTG15
PPG0 ... PPG15
16-bit PPG
16 ch.
External
Interrupt
Real Time
Clock 2)
WOT
INT0 ... INT15
Clock Output
Function
2 ch.
CKOT0, CKOT1
CKOTX0, CKOTX1
1) Available only on devices with suffix , “C”, “H” or suffix “T”
2)
Not available on MB96F348 HSA/HWA/TSA/TWA
FME/EMDC- 2007-9-11
MB96340_DS_block_diagram.fm
9
MB96340 Series
Specification
10
FME/EMDC- 2007-9-11
MB96340_DS_block_diagram.fm
Specification
MB96340
■ PIN ASSIGNMENTS
Pin assignment (FPT-100P-M22)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P00_4/AD04/INT12/SOT8_R2)
P00_5/AD05/INT13/SIN8_R2)
P00_6/AD06/INT14
P00_7/AD07/INT15
P01_0/AD08/CKOT1/TIN1
P01_1/AD09/CKOTX1/TOT1
P01_2/AD10/INT11_R/SIN3
P01_3/AD11/SOT3
P01_4/AD12/SCK3
Vcc
P07_5/AN21/INT5/SCK9_R2)
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
P07_0/AN16/INT0/NMI
Vss
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P06_7/AN7/PPG7
P06_6/AN6/PPG6
P06_5/AN5/PPG5
P06_4/AN4/PPG4
P06_3/AN3/PPG3
P06_2/AN2/PPG2
P06_1/AN1/PPG1
P06_0/AN0/PPG0
AVss
QFP - 100
Vss
Package code (mold)
FPT-100P-M22
X1
X0
P01_5/AD13/INT7_R/SIN2_R
P01_6/AD14/SOT2_R
P01_7/AD15/SCK2_R
P02_0/A16/PPG12
P02_1/A17/PPG13
P02_2/A18/PPG14
P02_3/A19/PPG15
AVRL
AVRH
AVcc
P05_7/AN15/INT5_R
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1)
Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R not available on MB96F348TSB/HSB/TWB/HWB
(FPT-100P-M22)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
FME/EMDC- 2007-9-12
MB96340_DS_pin_assignement.fm
11
MB96340 Series
Specification
Pin assignment (FPT-100P-M20)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P00_1AD01/INT9/SOT7_R2)
P00_2/AD02/INT10/SIN7_R2)
P00_3/AD03/INT11/SCK8_R2)
P00_4/AD04/INT12/SOT8_R2)
P00_5/AD05/INT13/SIN8_R2)
P00_6/AD06/INT14
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD1
MD2
P07_5/AN21/INT5/SCK9_R2)
P07_4/AN20/INT4
P07_3/AN19/INT3
P07_2/AN18/INT2
P07_1/AN17/INT1
P07_0/AN16/INT0/NMI
Vss
P00_7/AD07/INT15
P01_0/AD08/CKOT1/TIN1
P01_1/AD09/CKOTX1/TOT1
P01_2/AD10/INT11_R/SIN3
P01_3/AD11/SOT3
P06_7/AN7/PPG7
P06_6/AN6/PPG6
P06_5/AN5/PPG5
P06_4/AN4/PPG4
P06_3/AN3/PPG3
P06_2/AN2/PPG2
P06_1/AN1/PPG1
P06_0/AN0/PPG0
AVss
LQFP - 100
P01_4/AD12/SCK3
Vcc
Vss
Package code (mold)
FPT-100P-M20
X1
X0
P01_5/AD13/INT7_R/SIN2_R
P01_6/AD14/SOT2_R
P01_7/AD15/SCK2_R
P02_0/A16/PPG12
AVRL
AVRH
P02_1/A17/PPG13
AVcc
P02_2/A18/PPG14
P05_7/AN15/INT5_R
P05_6/AN14/INT4_R
P05_5/AN13/INT0_R/NMI_R
P05_4/AN12/TOT3/INT2_R
P02_3/A19/PPG15
P02_4/A20/TTG8/TTG0/IN0
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1) Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R not available on MB96F348TSB/HSB/TWB/HWB
(FPT-100P-M20)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
12
FME/EMDC- 2007-9-12
MB96340_DS_pin_assignement.fm
Specification
MB96340
■ PIN CIRCUIT TYPE
FPT-100P-M20
FPT-100P-M22
Circuit
type
Pin no.
Circuit
type
Pin no.
1-10
11,12
11,12
13,14
15
H
1-12
13, 14
13, 14
15,16
17
H
B1)
B1)
H2)
H2)
Supply
Supply
C-Pin
C-Pin
16,17
18-21
22-29
30
H
18,19
20-23
24-31
32
H
N
N
I
I
F
F
31
G
33
G
32-33
34 to 41
42
F
34-35
36 to 43
44
F
I
I
Supply
Supply
43 to 48
49 to 51
52
I
45 to 50
51 to 53
54
I
C
C
E
E
53 to 54
55 to 62
63, 64
65 to 87
88,89
90, 91
92-100
I
55 to 56
57 to 64
65, 66
67 to 89
90, 91
92, 93
94 to 100
I
H
Supply
H
H
Supply
H
Supply
A
Supply
A
H
H
1) Devices with suffix ”W”
2) Devices without suffix ”W”
FME/EMDC- 2007-9-12
MB96340_DS_pin_circuit_type.fm
13
MB96340 Series
Specification
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Oscillation circuit
High-speed oscillation feedback resistor =
approx. 1 MΩ
X1
X0
Xout
Standby control signal
B
Oscillation circuit
Low-speed oscillation feedback resistor =
approx. 10 MΩ
X1A
X0A
Xout
Standby control signal
C
E
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
R
Hysteresis
inputs
CMOS input pin
CMOS Hysteresis input pin
Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
Hysteresis
inputs
F
Power supply input protection circuit
14
FME/EMDC- 2007-9-12
MB96340_DS_pin_circuit_type.fm
Specification
MB96340
Type
G
Circuit
Remarks
A/D converter ref+ (AVRH) power supply input
pin, With the protection circuit
ANE
AVR
Flash devices do not have a protection circuit
against VCC for pin AVRH
ANE
H
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
pull-up control
Pout
Nout
R
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Automotive inputs
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
FME/EMDC- 2007-9-12
MB96340_DS_pin_circuit_type.fm
15
MB96340 Series
Specification
Type
Circuit
Remarks
I
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up registor: 50kΩ approx.
Analogue input
pull-up control
Pout
Nout
R
Hysteresis input
Hysteresis input
Automotive inputs
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
TTL input
Standby control
for input shutdown
Analog input
N
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
pull-up control
Pout
Nout
R
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Automotive inputs
TTL input
Standby control
for input shutdown
Standby control
for input shutdown
Standby control
for input shutdown
16
FME/EMDC- 2007-9-12
MB96340_DS_pin_circuit_type.fm
Specification
MB96340
■ PIN FUNCTION DESCRIPTION
Pin Function description (1 / 2)
Pin name
ADn
Feature
Description
External bus interface (multiplexed mode) address/data input/
output
External bus
ADTG
ADTG_R
ALARMn
ALE
ADC
ADC
A/D converter trigger input
Relocated A/D converter trigger input
Alarm Comparator n input
Alarm comparator
External bus
ADC
External bus Address Latch Enable output
A/D converter channel n input
ANn
AVCC
AVRH
AVRL
AVSS
C
Supply
Analogue circuits power supply
ADC
A/D converter high reference voltage input
A/D converter low reference voltage input
Analogue circuits power supply
ADC
Supply
Voltage regulator
Clock output function
Clock output function
External bus
External bus
Free Running Timer
External bus
External bus
ICU
Internally regulated power supply stabilization capacitor pin.
Clock Output function n output
CKOTn
CKOTXn
ECLK
CSn
Clock Output Function n inverted output
External bus clock output
External bus chip select n output
FRCKn
HAKX
HRQ
Free Running Timer n input
External bus Hold Acknowlegde
External bus Hold Request
INn
Input Capture Unit n input
INTn
External Interrupt
External Interrupt
External bus
Core
External Interrupt n input
INTn_R
LBX
Relocated External Interrupt n input
External Bus Interface Lower Byte select strobe output
Input pins for specifying the operating mode.
Non-Maskable Interrupt input
MDn
NMI
External Interrupt
External Interrupt
OCU
NMI_R
OUTn
PPGn
PPGn_R
Relocated Non-Maskable Interrupt input
Output Compare Unit n waveform output
Programmable Pulse Generator n output
Relocated Programmable Pulse Generator n output
MB96300_DS_pin_function_desc.fm
PPG
PPG
FME/EMDC- 2007-9-12
17
MB96340 Series
Specification
Pin Function description (2 / 2)
Pin name
Feature
Description
RDX
RDY
External bus
External bus
Core
External bus interface read strobe output
External bus interface external wait state request input
Reset input
RSTX
RXn
CAN
CAN interface n RX input
SCKn
SCKn_R
SCLn
SDAn
SINn
USART
USART
I2C
USART n serial clock input/output
Relocated USART n serial clock input/output
I2C interface n clock I/O input/output
I2C interface n serial data I/O input/output
USART n serial data input
I2C
USART
USART
USART
USART
Reload Timer
Reload Timer
PPG
SINn_R
SOTn
SOTn_R
TINn
Relocated USART n serial data input
USART n serial data output
Relocated USART n serial data output
Reload Timer n event input
TOTn
TTGn
TTGn_R
TXn
Reload Timer n output
Programmable Pulse Generator n trigger input
Relocated Programmable Pulse Generator n trigger input
CAN interface n TX output
PPG
CAN
UBX
External bus
Supply
External Bus Interface Upper Byte select strobe output
Power supply
VCC
VSS
Supply
Power supply
WOT
WRHX
WRLX
X0
RTC
Real Timer clock output
External bus
External bus
Clock
External bus High byte Write strobe output
External bus Low byte Write strobe output
Oscillator input
X0A
Clock
"Subclock Oscillator input (only for devices with suffix ""W"")"
Oscillator output
X1
Clock
"Subclock Oscillator output (only for devices with suffix
""W"")"
X1A
Clock
18
FME/EMDC- 2007-9-12
MB96300_DS_pin_function_desc.fm
Specification
MB96340
■ MEMORY MAP
MB96V300
MB96(F)34x
ff.ffff
User
ROM
Start address of
User ROM area and
number of small sector
depends on the device
Main Flash
Emulation
ROM
Small Sectors
Main RCB ***
df.007f
df.0000
Satellite Flash
(available on devices with suffix”T”, “H”, “C”)
de.002f
de.0000
de.0000
10.0000
Sat RCB ***
external
Bus
external
Bus
Boot-ROM
0f.e000
DSU
area
0f.0000
0e.0000
external
RAM
02.0000
RAM availability and mapping
internal
RAM
internal
RAM
depending on device
Not used for current available devices
01.0000
00.8000
ROM/RAM
-Mirror
ROM/RAM
-Mirror
internal
RAM
internal
RAM
RAMSTART**
Reserved
00.1200
00.0c00
External Bus end address**
ext. bus
ext. bus
Peripheral
Peripheral
00.0380
00.0180
00.0100
00.00f0
GPR*
DMA
GPR*
DMA
ext. bus
ext. bus
Peripheral
00.0000 Peripheral
* Unused GPR banks can be used as RAM area.
** Please refer to the table “RAMSTART for different RAM sizes” on the next page
*** ROM Configuration Block (RCB) must not be used for other purposes than described in the manual
The external Bus area DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device configuration.
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
19
MB96340 Series
Specification
■ RAMSTART AND EXTERNAL BUS END ADDRESS FOR DIFFERENT RAM SIZES
End address of exter-
Devices
RAM size
RAMSTART
nal bus area
MB96344
MB96(F)346, MB96(F)347
MB96F348
6 kB
16 kB
24 kB
6A40
4240
2240
69FF
41FF
21FF
20
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
■ FLASH SECTOR CONFIGURATION
MB96F346Y
MB96F346R
MB96F346A
MB96F347Y
MB96F347R
MB96F347A
MB96F348Y
MB96F348R
MB96F348A
MB96F348C
MB96F348H
MB96F348T
Main Flash size
544kByte
Satellite Flash size
32kByte
Alternative mode Flash memory Main Flash size
Main Flash size
416kByte
Main Flash size
544kByte
CPU address mode address
288kByte
SA39 - 64K
SA38 - 64K
SA37 - 64K
SA36 - 64K
FF:FFFFh
3F:FFFFh
SA39 - 64K
SA38 - 64K
SA37 - 64K
SA36 - 64K
SA35 - 64K
SA34 - 64K
SA39 - 64K
SA38 - 64K
SA37 - 64K
SA36 - 64K
SA35 - 64K
SA34 - 64K
SA33 - 64K
SA32 - 64K
SA39 - 64K
SA38 - 64K
SA37 - 64K
SA36 - 64K
SA35 - 64K
SA34 - 64K
SA33 - 64K
SA32 - 64K
FF:0000h
FE:FFFFh
3F:0000h
3E:FFFFh
FE:0000h
FD:FFFFh
3E:0000h
3D:FFFFh
FD:0000h
FC:FFFFh
3D:0000h
3C:FFFFh
FC:0000h
FB:FFFFh
3C:0000h
3B:FFFFh
FB:0000h
FA:FFFFh
3B:0000h
3A:FFFFh
FA:0000h
F9:FFFFh
3A:0000h
39:FFFFh
F9:0000h
F8:FFFFh
39:0000h
38:FFFFh
F8:0000h
F7:FFFFh
38:0000h
37:FFFFh
F7:0000h
37:0000h
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
E0:FFFFh
E0:0000h
20:FFFFh
20:0000h
DF:FFFFh
DF:E000h
1F:FFFFh
1F:E000h
DF:DFFFh
DF:C000h
1F:DFFFh
1F:C000h
DF:BFFFh
DF:A000h
1F:BFFFh
1F:A000h
DF:9FFFh
DF:8000h
1F:9FFFh
1F:8000h
DF:7FFFh
DF:6000h
1F:7FFFh
1F:6000h
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
DF:5FFFh
DF:4000h
1F:5FFFh
1F:4000h
DF:3FFFh
DF:2000h
DF:1FFFh
DF:0000h
1F:3FFFh
1F:2000h
1F:1FFFh
1F:0000h
DE:FFFFh
1E:FFFFh
DE:E000h
1E:E000h
DE:DFFFh
DE:C000h
1E:DFFFh
1E:C000h
DE:BFFFh
DE:A000h
1E:BFFFh
1E:A000h
DE:9FFFh
DE:8000h
1E:9FFFh
1E:8000h
DE:7FFFh
DE:6000h
1E:7FFFh
1E:6000h
SB3 - 8K
SB2 - 8K
SB1 - 8K
SB0 - 8K
DE:5FFFh
DE:4000h
1E:5FFFh
1E:4000h
DE:3FFFh
DE:2000h
DE:1FFFh
DE:0000h
1E:3FFFh
1E:2000h
1E:1FFFh
1E:0000h
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
21
MB96340 Series
Specification
■ PARALLEL PROGRAMMING FLASH MEMORY CONTROL SIGNALS
Flash memory control signals (MD[2:0] = 111)
MB96F34X
Pin number
MBM29LV200
Normal function
Flash memory mode
LQFP
QFP
3
5
P03_0
P03_1
AQ16
CE
A15
CE
4
6
5
7
P03_2
OE
OE
6
7
8
P03_3
WE
WE
A16
9
10
P03_4
AQ17
8
P03_5
AQ18
9
11
P03_6
BYTE
BYTE
10
12
P03_7
RY/BY
RY/BY
16 to 19
20 to 21
22 to 23
27 to 29
49
18 to 21
22 to 23
24 to 25
29 to 31
51
P04_2 to P04_5
P04_6 to P04_7
P05_0 to P05_1
P05_5 to P05_7
MD2
AQ8 to AQ11
AQ12 to AQ13
AQ14 to AQ15
AQ19 to AQ21
MD2
A7 to A10
A11 to A12
A13 to A14
OE
50
52
MD1
MD1
RESET
51
53
MD0
MDO
A9
52
54
RST
RESET
RESET
75 to 82
83 to 86
77 to 84
85 to 88
89, 94 to 96
1 to 4, 97 to 100
P00_0 to P00_7
P01_0 to P01_3
P01_4 to P01_7
P02_0 to P02_7
DQ0 to DQ7
DQ8 to DQ11
DQ12 to DQ15
AQ0 to AQ7
DQ0 to DQ7
DQ8 to DQ11
DQ12 to DQ15
A-1, A0 to A6
87, 92 to 94
99 to 2, 95 to 98
22
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
■ SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010)
MB96F34x
Pin number
LQFP-100
Pin number
QFP-100
Normal function
USART Number
USART0
57
58
59
60
61
62
22
23
24
92
93
94
85
86
87
77
76
75
80
79
78
54
53
48
59
60
61
62
63
64
24
25
26
94
95
96
87
88
89
79
78
77
82
81
80
56
55
50
SIN0
SOT0
SCK0
SIN1
USART1
USART2
USART2
USART3
USART7
USART8
USART9
SOT1
SCK1
SIN2
SOT2
SCK2
SIN2_R
SOT2_R
SCK2_R
SIN3
SOT3
SCK3
SIN7_R
SOT7_R
SCK7_R
SIN8_R
SOT8_R
SCK8_R
SIN9_R
SOT9_R
SCK9_R
Note: For handshaking pin, please use for this device the default pin P00_1. If any other pin is required, please
contact the Flash programmer device vendor.
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
23
MB96340 Series
Specification
■ I/O MAP
I/O map (1 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000000H P00 - I/O Port Port Data Register
000001H P01 - I/O Port Port Data Register
000002H P02 - I/O Port Port Data Register
000003H P03 - I/O Port Port Data Register
000004H P04 - I/O Port Port Data Register
000005H P05 - I/O Port Port Data Register
000006H P06 - I/O Port Port Data Register
000007H P07 - I/O Port Port Data Register
000008H P08 - I/O Port Port Data Register
000009H P09 - I/O Port Port Data Register
00000AH P10 - I/O Port Port Data Register
00000BH
PDR00
PDR01
PDR02
PDR03
PDR04
PDR05
PDR06
PDR07
PDR08
PDR09
PDR10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
-
Reserved
000017H
000018H ADC - Control Status register 0 Low
000019H ADC - Control Status register 0 High
00001AH ADC - Data Register 0 Low
00001BH ADC - Data Register 0 High
00001CH ADC - Setting Register Low 0
00001DH ADC - Setting Register High 0
ADCSL
ADCSH
ADCRL
ADCRH
ADCS
ADCR
ADSR
RW
RW
R
R
RW
ADC - Extended Configuration
00001EH
Register
ADECR
RW
RW
RW
RW
RW
RW
FRT0 - Data register of free-running
000020H
timer
TCDT0
TCCS0
TCDT1
FRT0 - Data register of free-running
000021H
timer
FRT0 - Control status register of free-
running timer
000022H
TCCSL0
TCCSH0
FRT0 - Control status register of free-
running timer
000023H
FRT1 - Data register of free-running
000024H
timer
24
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (2 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
FRT1 - Data register of free-running
timer
000025H
000026H
000027H
000028H
000029H
RW
RW
RW
RW
RW
FRT1 - Control status register of free-
running timer
TCCSL1
TCCSH1
OCS0
TCCS1
FRT1 - Control status register of free-
running timer
OCU0 - Output Compare Control
Status
OCU1 - Output Compare Control
Status
OCS1
00002AH OCU0 - Compare Register
00002BH OCU0 - Compare Register
00002CH OCU1 - Compare Register
00002DH OCU1 - Compare Register
OCCP0
OCCP1
RW
RW
RW
RW
OCU2 - Output Compare Control
00002EH
Status
OCS2
OCS3
RW
RW
OCU3 - Output Compare Control
00002FH
Status
000030H OCU2 - Compare Register
000031H OCU2 - Compare Register
000032H OCU3 - Compare Register
000033H OCU3 - Compare Register
OCCP2
OCCP3
RW
RW
RW
RW
OCU4 - Output Compare Control
000034H
Status
OCS4
OCS5
RW
RW
OCU5 - Output Compare Control
000035H
Status
000036H OCU4 - Compare Register
000037H OCU4 - Compare Register
000038H OCU5 - Compare Register
000039H OCU5 - Compare Register
OCCP4
OCCP5
RW
RW
RW
RW
OCU6 - Output Compare Control
00003AH
Status
OCS6
OCS7
RW
RW
OCU7 - Output Compare Control
00003BH
Status
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
25
MB96340 Series
Specification
I/O map (3 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
00003CH OCU6 - Compare Register
00003DH OCU6 - Compare Register
00003EH OCU7 - Compare Register
00003FH OCU7 - Compare Register
000040H ICU0/ICU1 - Control Status Register
000041H ICU0/ICU1 - Edge register
000042H ICU0 - Capture Register
000043H ICU0 - Capture Register
000044H ICU1 - Capture Register
000045H ICU1 - Capture Register
000046H ICU2/ICU3 - Control Status Register
000047H ICU2/3 - Edge register
OCCP6
RW
RW
RW
RW
RW
RW
R
OCCP7
ICS01
ICE01
IPCPL0
IPCPH0
IPCPL1
IPCPH1
ICS23
IPCP0
IPCP1
R
R
R
RW
RW
R
ICE23
000048H ICU2 - Capture Register
000049H ICU2 - Capture Register
00004AH ICU3 - Capture Register
00004BH ICU3 - Capture Register
00004CH ICU4/ICU5 - Control Status Register
00004DH ICU4/ICU5 - Edge register
00004EH ICU4 - Capture Register
00004FH ICU4 - Capture Register
000050H ICU5 - Capture Register
000051H ICU5 - Capture Register
000052H ICU6/ICU7 - Control Status Register
000053H ICU6/ICU7 - Edge register
000054H ICU6 - Capture Register
000055H ICU6 - Capture Register
000056H ICU7 - Capture Register
000057H ICU7 - Capture Register
IPCPL2
IPCPH2
IPCPL3
IPCPH3
ICS45
IPCP2
IPCP3
R
R
R
RW
RW
R
ICE45
IPCPL4
IPCPH4
IPCPL5
IPCPH5
ICS67
IPCP4
IPCP5
R
R
R
RW
RW
R
ICE67
IPCPL6
IPCPH6
IPCPL7
IPCPH7
IPCP6
IPCP7
R
R
R
EXTINT0 - External Interrupt Enable
000058H
Register
ENIR0
RW
26
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (4 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
EXTINT0 - External Interrupt Interrupt
request Register
000059H
00005AH
00005BH
00005CH
00005DH
00005EH
00005FH
000060H
000061H
EIRR0
ELVRL0
ELVRH0
ENIR1
RW
RW
RW
RW
RW
RW
RW
RW
RW
EXTINT0 - External Interrupt Level
Select
ELVR0
EXTINT0 - External Interrupt Level
Select
EXTINT1 - External Interrupt Enable
Register
EXTINT1 - External Interrupt Interrupt
request Register
EIRR1
EXTINT1 - External Interrupt Level
Select
ELVRL1
ELVRH1
TMCSRL0
TMCSRH0
ELVR1
EXTINT1 - External Interrupt Level
Select
RLT0 - Timer Control Status Register
Low
TMCSR0
RLT0 - Timer Control Status Register
High
000062H RLT0 - Reload Register Low
000063H RLT0 - Reload Register High
TMRLR0
TMRHR0
TMR0
RW
RW
RLT1 - Timer Control Status Register
000064H
Low
TMCSRL1
TMCSRH1
TMCSR1
RW
RW
RLT1 - Timer Control Status Register
000065H
High
000066H RLT1 - Reload Register Low
000067H RLT1 - Reload Register High
TMRLR1
TMRHR1
TMR1
RW
RW
RLT2 - Timer Control Status Register
000068H
Low
TMCSRL2
TMCSRH2
TMCSR2
RW
RW
RLT2 - Timer Control Status Register
000069H
High
00006AH RLT2 - Reload Register Low
00006BH RLT2 - Reload Register High
TMRLR2
TMRHR2
TMR2
RW
RW
RLT3 - Timer Control Status Register
00006CH
Low
TMCSRL3
TMCSRH3
TMCSR3
RW
RW
RLT3 - Timer Control Status Register
00006DH
High
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
27
MB96340 Series
Specification
I/O map (5 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
00006EH RLT3 - Reload Register Low
00006FH RLT3 - Reload Register High
TMRLR3
TMRHR3
TMR3
RW
RW
RLT6 - Timer Control Status Register
000070H
TMCSRL6
TMCSRH6
TMCSR6
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Low (dedic. RLT for PPG)
RLT6 - Timer Control Status Register
000071H
High (dedic. RLT for PPG)
RLT6 - Reload Register Low (dedic.
000072H
TMRLR6
TMR6
RLT for PPG) - for writing
RLT6 - Reload Register Low (dedic.
000072H
RLT for PPG) - for reading
RLT6 - Reload Register High (dedic.
000073H
RLT for PPG) - for writing
RLT6 - Reload Register High (dedic.
000073H
RLT for PPG) - for reading
PPG3-PPG0 - General Control register
000074H
1 Low
GCN1L0
GCN1H0
GCN2L0
GCN2H0
GCN10
GCN20
PPG3-PPG0 - General Control register
000075H
1 High
PPG3-PPG0 - General Control register
000076H
2 Low
PPG3-PPG0 - General Control register
000077H
2 High
000078H PPG0 - Timer register
PTMR0
PCSR0
PDUT0
PCN0
R
R
000079H PPG0 - Timer register
00007AH PPG0 - Period setting register
00007BH PPG0 - Period setting register
00007CH PPG0 - Duty cycle register
00007DH PPG0 - Duty cycle register
00007EH PPG0 - Control status register
00007FH PPG0 - Control status register
000080H PPG1 - Timer register
W
W
W
W
RW
RW
R
PCNL0
PCNH0
PTMR1
PCSR1
000081H PPG1 - Timer register
R
000082H PPG1 - Period setting register
000083H PPG1 - Period setting register
W
W
28
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (6 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000084H PPG1 - Duty cycle register
000085H PPG1 - Duty cycle register
000086H PPG1 - Control status register
000087H PPG1 - Control status register
000088H PPG2 - Timer register
PDUT1
W
W
PCNL1
PCNH1
PCN1
PTMR2
PCSR2
PDUT2
PCN2
RW
RW
R
000089H PPG2 - Timer register
R
00008AH PPG2 - Period setting register
00008BH PPG2 - Period setting register
00008CH PPG2 - Duty cycle register
00008DH PPG2 - Duty cycle register
00008EH PPG2 - Control status register
00008FH PPG2 - Control status register
000090H PPG3 - Timer register
W
W
W
W
PCNL2
PCNH2
RW
RW
R
PTMR3
PCSR3
PDUT3
PCN3
000091H PPG3 - Timer register
R
000092H PPG3 - Period setting register
000093H PPG3 - Period setting register
000094H PPG3 - Duty cycle register
000095H PPG3 - Duty cycle register
000096H PPG3 - Control status register
000097H PPG3 - Control status register
W
W
W
W
PCNL3
PCNH3
RW
RW
PPG7-PPG4 - General Control register
000098H
1 Low
GCN1L1
GCN1H1
GCN2L1
GCN2H1
GCN11
GCN21
RW
RW
RW
RW
PPG7-PPG4 - General Control register
000099H
1 High
PPG7-PPG4 - General Control register
00009AH
2 Low
PPG7-PPG4 - General Control register
00009BH
2 High
00009CH PPG4 - Timer register
00009DH PPG4 - Timer register
00009EH PPG4 - Period setting register
PTMR4
PCSR4
R
R
W
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
29
MB96340 Series
Specification
I/O map (7 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
00009FH PPG4 - Period setting register
0000A0H PPG4 - Duty cycle register
0000A1H PPG4 - Duty cycle register
0000A2H PPG4 - Control status register
0000A3H PPG4 - Control status register
0000A4H PPG5 - Timer register
W
W
PDUT4
PCN4
W
PCNL4
PCNH4
RW
RW
R
PTMR5
PCSR5
PDUT5
PCN5
0000A5H PPG5 - Timer register
R
0000A6H PPG5 - Period setting register
0000A7H PPG5 - Period setting register
0000A8H PPG5 - Duty cycle register
0000A9H PPG5 - Duty cycle register
0000AAH PPG5 - Control status register
0000ABH PPG5 - Control status register
0000ACH I2C0 - Bus Status Register
0000ADH I2C0 - Bus Control Register
W
W
W
W
PCNL5
PCNH5
IBSR0
IBCR0
RW
RW
R
RW
I2C0 - Ten bit Slave address Register
0000AEH
Low
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
ITBA0
ITMK0
RW
RW
RW
RW
RW
RW
I2C0 - Ten bit Slave address Register
0000AFH
High
I2C0 - Ten bit Address mask Register
0000B0H
Low
I2C0 - Ten bit Address mask Register
0000B1H
High
I2C0 - Seven bit Slave address
0000B2H
Register
I2C0 - Seven bit Address mask
0000B3H
Register
ISMK0
0000B4H I2C0 - Data Register
IDAR0
ICCR0
IBSR1
IBCR1
RW
RW
R
0000B5H I2C0 - Clock Control Register
0000B6H I2C1 - Bus Status Register
0000B7H I2C1 - Bus Control Register
RW
I2C1 - Ten bit Slave address Register
0000B8H
Low
ITBAL1
ITBA1
RW
30
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (8 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
I2C1 - Ten bit Slave address Register
High
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
ITBAH1
ITMKL1
ITMKH1
ISBA1
RW
RW
RW
RW
RW
I2C1 - Ten bit Address mask Register
Low
ITMK1
I2C1 - Ten bit Address mask Register
High
I2C1 - Seven bit Slave address
Register
I2C1 - Seven bit Address mask
Register
ISMK1
0000BEH I2C1 - Data Register
IDAR1
ICCR1
RW
RW
0000BFH I2C1 - Clock Control Register
USART0 USART - Serial Mode
0000C0H
Register
SMR0
RW
0000C1H USART0 - Serial Control Register
0000C2H USART0 - TX Register
SCR0
TDR0
RW
W
0000C2H USART0 - RX Register
RDR0
SSR0
R
0000C3H USART0 - Serial Status
RW
RW
RW
0000C4H USART0 - Control/Com. Register
0000C5H USART0 - Ext. Status Register
ECCR0
ESCR0
USART0 - Baud Rate Generator
Register Low
0000C6H
BGRL0
BGRH0
ESIR0
BGR0
RW
RW
RW
USART0 - Baud Rate Generator
Register High
0000C7H
USART0 - Extended Serial Interrupt
0000C8H
Register
0000C9H Reserved
0000CAH USART1 - Serial Mode Register
0000CBH USART1 - Serial Control Register
0000CCH USART1 - TX Register
0000CCH USART1 - RX Register
0000CDH USART1 - Serial Status
0000CEH USART1 - Control/Com. Register
SMR1
SCR1
TDR1
RDR1
SSR1
ECCR1
RW
RW
W
R
RW
RW
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
31
MB96340 Series
Specification
I/O map (9 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0000CFH USART1 - Ext. Status Register
ESCR1
BGRL1
RW
RW
USART1 - Baud Rate Generator
0000D0H
BGR1
Register Low
USART1 - Baud Rate Generator
Register High
0000D1H
BGRH1
ESIR1
RW
RW
USART1 - Extended Serial Interrupt
0000D2H
Register
0000D3H Reserved
0000D4H USART2 - Serial Mode Register
0000D5H USART2 - Serial Control Register
0000D6H USART2 - TX Register
0000D6H USART2 - RX Register
0000D7H USART2 - Serial Status
0000D8H USART2 - Control/Com. Register
0000D9H USART2 - Ext. Status Register
SMR2
SCR2
TDR2
RW
RW
W
RDR2
SSR2
R
RW
RW
RW
ECCR2
ESCR2
USART2 - Baud Rate Generator
Register Low
0000DAH
BGRL2
BGRH2
ESIR2
BGR2
RW
RW
RW
USART2 - Baud Rate Generator
Register High
0000DBH
USART2 - Extended Serial Interrupt
0000DCH
Register
0000DDH Reserved
0000DEH USART3 - Serial Mode Register
0000DFH USART3 - Serial Control Register
0000E0H USART3 - TX Register
0000E0H USART3 - RX Register
0000E1H USART3 - Serial Status
0000E2H USART3 - Control/Com. Register
0000E3H USART3 - Ext. Status Register
SMR3
SCR3
TDR3
RW
RW
W
RDR3
SSR3
R
RW
RW
RW
ECCR3
ESCR3
USART3 - Baud Rate Generator
Register Low
0000E4H
BGRL3
BGRH3
BGR3
RW
RW
USART3 - Baud Rate Generator
Register High
0000E5H
32
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (10 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
USART3 - Extended Serial Interrupt
Register
0000E6H
ESIR3
RW
0000F0H external bus
EXTBUS0
BAPL0
RW
RW
000100H DMA0 -Buffer address pointer low byte
DMA0 - Buffer address pointer middle
000101H
byte
BAPM0
RW
DMA0 - Buffer address pointer high
000102H
byte
BAPH0
DMACS0
IOAL0
RW
RW
RW
000103H DMA0 - DMA control register
DMA0 - I/O register address pointer
000104H
low byte
IOA0
DMA0 - I/O register address pointer
000105H
high byte
IOAH0
RW
000106H DMA0 - Data counter low byte
000107H DMA0 - Data counter high byte
000108H DMA1 -Buffer address pointer low byte
DCTL0
DCTH0
BAPL1
DCT0
RW
RW
RW
DMA1 - Buffer address pointer middle
000109H
byte
BAPM1
RW
DMA1 - Buffer address pointer high
00010AH
byte
BAPH1
DMACS1
IOAL1
RW
RW
RW
00010BH DMA1 - DMA control register
DMA1 - I/O register address pointer
00010CH
low byte
IOA1
DMA1 - I/O register address pointer
00010DH
high byte
IOAH1
RW
00010EH DMA1 - Data counter low byte
00010FH DMA1 - Data counter high byte
000110H DMA2 -Buffer address pointer low byte
DCTL1
DCTH1
BAPL2
DCT1
RW
RW
RW
DMA2 - Buffer address pointer middle
000111H
byte
BAPM2
RW
DMA2 - Buffer address pointer high
000112H
byte
BAPH2
DMACS2
IOAL2
RW
RW
RW
000113H DMA2 - DMA control register
DMA2 - I/O register address pointer
000114H
low byte
IOA2
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
33
MB96340 Series
Specification
I/O map (11 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
DMA2 - I/O register address pointer
high byte
000115H
IOAH2
RW
000116H DMA2 - Data counter low byte
000117H DMA2 - Data counter high byte
000118H DMA3 -Buffer address pointer low byte
DCTL2
DCTH2
BAPL3
DCT2
RW
RW
RW
DMA3 - Buffer address pointer middle
000119H
byte
BAPM3
RW
DMA3 - Buffer address pointer high
00011AH
byte
BAPH3
DMACS3
IOAL3
RW
RW
RW
00011BH DMA3 - DMA control register
DMA3 - I/O register address pointer
00011CH
low byte
IOA3
DMA3 - I/O register address pointer
00011DH
high byte
IOAH3
RW
00011EH DMA3 - Data counter low byte
00011FH DMA3 - Data counter high byte
000120H DMA4 -Buffer address pointer low byte
DCTL3
DCTH3
BAPL4
DCT3
RW
RW
RW
DMA4 - Buffer address pointer middle
000121H
byte
BAPM4
RW
DMA4 - Buffer address pointer high
000122H
byte
BAPH4
DMACS4
IOAL4
RW
RW
RW
000123H DMA4 - DMA control register
DMA4 - I/O register address pointer
000124H
low byte
IOA4
DMA4 - I/O register address pointer
000125H
high byte
IOAH4
RW
000126H DMA4 - Data counter low byte
000127H DMA4 - Data counter high byte
000128H DMA5 -Buffer address pointer low byte
DCTL4
DCTH4
BAPL5
DCT4
RW
RW
RW
DMA5 - Buffer address pointer middle
000129H
byte
BAPM5
RW
DMA5 - Buffer address pointer high
00012AH
byte
BAPH5
RW
RW
00012BH DMA5 - DMA control register
DMACS5
34
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (12 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
DMA5 - I/O register address pointer
low byte
00012CH
00012DH
IOAL5
IOAH5
IOA5
RW
RW
DMA5 - I/O register address pointer
high byte
00012EH DMA5 - Data counter low byte
00012FH DMA5 - Data counter high byte
DCTL5
DCTH5
DCT5
RW
RW
CPU - General Purpose registers
(RAM access)
000180H
GPR_RAM
RW
000380H DMA0 - Interrupt select
000381H DMA1 - Interrupt select
000382H DMA2 - Interrupt select
000383H DMA3 - Interrupt select
000384H DMA4 - Interrupt select
000385H DMA5 - Interrupt select
000386H
DISEL0
DISEL1
DISEL2
DISEL3
DISEL4
DISEL5
RW
RW
RW
RW
RW
RW
-
Reserved
00038FH
000390H DMA7-DMA0 - status register
000391H Reserved
DSRL
DSSRL
DERL
DSR
DSSR
DER
RW
RW
RW
000392H DMA7-DMA0 - stop status register
000393H Reserved
000394H DMA7-DMA0 - enable register
000395H
-
Reserved
000398H
000399H Unused
0003A0H Interrupt level register
ILR
IDX
ICR
RW
RW
RW
RW
RW
RW
0003A1H Interrupt Index register
0003A2H Interrupt vector Table base register
0003A3H Interrupt vector Table base register
0003A4H Delayed Interrupt register
0003A5H Non maskable Interrupt register
TBRL
TBRH
DIRR
NMI
TBR
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
35
MB96340 Series
Specification
I/O map (13 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0003A6H
-
Reserved
0003ADH
0003AEH ROM mirror control register
0003AFH EDSU configuration register
ROMM
EDSU
RW
RW
Memory patch control/status register
0003B0H
ch 0/1
PFCS0
PFCS1
PFCS2
PFCS3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Memory patch control/status register
0003B1H
ch 0/1
Memory patch control/status register
0003B2H
ch 2/3
Memory patch control/status register
0003B3H
ch 2/3
Memory patch control/status register
0003B4H
ch 4/5
Memory patch control/status register
0003B5H
ch 4/5
Memory patch control/status register
0003B6H
ch 6/7
Memory patch control/status register
0003B7H
ch 6/7
Memory Patch function - Patch
address 0 low
0003B8H
PFAL0
PFAM0
PFAH0
PFAL1
PFAM1
PFAH1
PFAL2
PFAM2
Memory Patch function - Patch
0003B9H
address 0 middle
Memory Patch function - Patch
address 0 high
0003BAH
Memory Patch function - Patch
address 1 low
0003BBH
Memory Patch function - Patch
0003BCH
address 1 middle
Memory Patch function - Patch
address 1 high
0003BDH
Memory Patch function - Patch
address 2 low
0003BEH
Memory Patch function - Patch
0003BFH
address 2 middle
36
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (14 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
Memory Patch function - Patch
address 2 high
0003C0H
0003C1H
0003C2H
0003C3H
0003C4H
0003C5H
0003C6H
0003C7H
0003C8H
0003C9H
0003CAH
0003CBH
0003CCH
0003CDH
0003CEH
0003CFH
PFAH2
PFAL3
PFAM3
PFAH3
PFAL4
PFAM4
PFAH4
PFAL5
PFAM5
PFAH5
PFAL6
PFAM6
PFAH6
PFAL7
PFAM7
PFAH7
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Memory Patch function - Patch
address 3 low
Memory Patch function - Patch
address 3 middle
Memory Patch function - Patch
address 3 high
Memory Patch function - Patch
address 4 low
Memory Patch function - Patch
address 4 middle
Memory Patch function - Patch
address 4 high
Memory Patch function - Patch
address 5 low
Memory Patch function - Patch
address 5 middle
Memory Patch function - Patch
address 5 high
Memory Patch function - Patch
address 6 low
Memory Patch function - Patch
address 6 middle
Memory Patch function - Patch
address 6 high
Memory Patch function - Patch
address 7 low
Memory Patch function - Patch
address 7 middle
Memory Patch function - Patch
address 7 high
0003D0H Memory Patch function - Patch data 0
0003D1H Memory Patch function - Patch data 0
0003D2H Memory Patch function - Patch data 1
0003D3H Memory Patch function - Patch data 1
PFDL0
PFDH0
PFDL1
PFDH1
PFD0
PFD1
RW
RW
RW
RW
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
37
MB96340 Series
Specification
I/O map (15 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0003D4H Memory Patch function - Patch data 2
0003D5H Memory Patch function - Patch data 2
0003D6H Memory Patch function - Patch data 3
0003D7H Memory Patch function - Patch data 3
0003D8H Memory Patch function - Patch data 4
0003D9H Memory Patch function - Patch data 4
0003DAH Memory Patch function - Patch data 5
0003DBH Memory Patch function - Patch data 5
0003DCH Memory Patch function - Patch data 6
0003DDH Memory Patch function - Patch data 6
0003DEH Memory Patch function - Patch data 7
0003DFH Memory Patch function - Patch data 7
0003E0H
PFDL2
PFDH2
PFDL3
PFDH3
PFDL4
PFDH4
PFDL5
PFDH5
PFDL6
PFDH6
PFDL7
PFDH7
PFD2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PFD3
PFD4
PFD5
PFD6
PFD7
-
Reserved
0003EFH
0003F0H
-
Reserved
0003F2H
Flash Memory Timing Configuration
register 1 (Main Flash)
0003F3H
0003F7H
MFMTCH
SFMTCH
RW
RW
Flash Memory Timing Configuration
register 1 (Sat Flash)
0003F8H Flash Memory Write Control register 0
0003F9H Flash Memory Write Control register 1
0003FDH Flash Memory Write Control register 5
000401H Clock select register
FMWC0
FMWC1
FMWC5
CKSR
RW
RW
RW
RW
RW
R
000402H Clock Stabilisation select register
000403H Clock monitor register
CKSSR
CKMR
000404H Clock Frequency control register Low
000405H Clock Frequency control register High
000406H PLL Control register Low
CKFCRL
CKFCRH
PLLCRL
RCTCR
CKFCR
PLLCR
RW
RW
RW
RW
000408H RC clock timer control register
38
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (16 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000409H Main clock timer control register
00040AH Sub clock timer control register
MCTCR
SCTCR
RW
RW
Reset cause and clock status register
with clear function
00040BH
RCCSRC
R
00040CH Reset configuration register
00040DH Reset cause and clock status register
00040EH Watch dog timer configuration register
00040FH Watch dog timer clear pattern register
000410H
RCR
RW
R
RCCSR
WDTC
WDTCP
RW
W
-
Reserved
000414H
000415H Clock output activation register
000416H Clock output configuration register 0
000417H Clock output configuration register 1
000418H Clock Modulator control register
000419H Unused
COAR
COCR0
COCR1
CMCR
RW
RW
RW
RW
Clock Modulator Parameter register
00041AH
Low
CMPRL
CMPRH
CMPR
RW
RW
Clock Modulator Parameter register
00041BH
High
00041CH
-
Reserved
00042BH
00042CH Voltage Regulator Control register
VRCR
RW
00042DH
-
Reserved
00042FH
000430H P00 - I/O Port Data Direction Register
000431H P01 - I/O Port Data Direction Register
000432H P02 - I/O Port Data Direction Register
000433H P03 - I/O Port Data Direction Register
000434H P04 - I/O Port Data Direction Register
000435H P05 - I/O Port Data Direction Register
DDR00
DDR01
DDR02
DDR03
DDR04
DDR05
RW
RW
RW
RW
RW
RW
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
39
MB96340 Series
Specification
I/O map (17 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000436H P06 - I/O Port Data Direction Register
000437H P07 - I/O Port Data Direction Register
000438H P08 - I/O Port Data Direction Register
000439H P09 - I/O Port Data Direction Register
00043AH P10 - I/O Port Data Direction Register
00043BH
DDR06
DDR07
DDR08
DDR09
DDR10
RW
RW
RW
RW
RW
-
Reserved
000443H
P00 - I/O Port Port Input Enable
Register
000444H
000445H
000446H
000447H
000448H
000449H
00044AH
00044BH
00044CH
00044DH
00044EH
PIER00
PIER01
PIER02
PIER03
PIER04
PIER05
PIER06
PIER07
PIER08
PIER09
PIER10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
P01 - I/O Port Port Input Enable
Register
P02 - I/O Port Port Input Enable
Register
P03 - I/O Port Port Input Enable
Register
P04 - I/O Port Port Input Enable
Register
P05 - I/O Port Port Input Enable
Register
P06 - I/O Port Port Input Enable
Register
P07 - I/O Port Port Input Enable
Register
P08 - I/O Port Port Input Enable
Register
P09 - I/O Port Port Input Enable
Register
P10 - I/O Port Port Input Enable
Register
00044FH
-
Reserved
000457H
000458H P00 -I/O Port Port Input Level Register
000459H P01 -I/O Port Port Input Level Register
00045AH P02 -I/O Port Port Input Level Register
PILR00
PILR01
PILR02
RW
RW
RW
40
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (18 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
00045BH P03 -I/O Port Port Input Level Register
00045CH P04 -I/O Port Port Input Level Register
00045DH P05 -I/O Port Port Input Level Register
00045EH P06 -I/O Port Port Input Level Register
00045FH P07 -I/O Port Port Input Level Register
000460H P08 -I/O Port Port Input Level Register
000461H P09 -I/O Port Port Input Level Register
000462H P10 -I/O Port Port Input Level Register
000463H
PILR03
PILR04
PILR05
PILR06
PILR07
PILR08
PILR09
PILR10
RW
RW
RW
RW
RW
RW
RW
RW
-
Reserved
00046BH
P00 - I/O Port Extended Port Input
Level Register
00046CH
00046DH
00046EH
00046FH
000470H
000471H
000472H
000473H
000474H
000475H
000476H
EPILR00
EPILR01
EPILR02
EPILR03
EPILR04
EPILR05
EPILR06
EPILR07
EPILR08
EPILR09
EPILR10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
P01 - I/O Port Extended Port Input
Level Register
P02 - I/O Port Extended Port Input
Level Register
P03 - I/O Port Extended Port Input
Level Register
P04 - I/O Port Extended Port Input
Level Register
P05 - I/O Port Extended Port Input
Level Register
P06 - I/O Port Extended Port Input
Level Register
P07 - I/O Port Extended Port Input
Level Register
P08 - I/O Port Extended Port Input
Level Register
P09 - I/O Port Extended Port Input
Level Register
P10 - I/O Port Extended Port Input
Level Register
000477H
-
Reserved
00047FH
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
41
MB96340 Series
Specification
I/O map (19 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
P00 - I/O Port Port Output Drive
Register
000480H
000481H
000482H
000483H
000484H
000485H
000486H
000487H
000488H
000489H
00048AH
PODR00
PODR01
PODR02
PODR03
PODR04
PODR05
PODR06
PODR07
PODR08
PODR09
PODR10
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
P01 - I/O Port Port Output Drive
Register
P02 - I/O Port Port Output Drive
Register
P03 - I/O Port Port Output Drive
Register
P04 - I/O Port Port Output Drive
Register
P05 - I/O Port Port Output Drive
Register
P06 - I/O Port Port Output Drive
Register
P07 - I/O Port Port Output Drive
Register
P08 - I/O Port Port Output Drive
Register
P09 - I/O Port Port Output Drive
Register
P10 - I/O Port Port Output Drive
Register
00049CH
-
Reserved
0004A7H
P00 - I/O Port Pull-Up resistor Control
Register
0004A8H
0004A9H
0004AAH
0004ABH
0004ACH
0004ADH
PUCR00
PUCR01
PUCR02
PUCR03
PUCR04
PUCR05
RW
RW
RW
RW
RW
RW
P01 - I/O Port Pull-Up resistor Control
Register
P02 - I/O Port Pull-Up resistor Control
Register
P03 - I/O Port Pull-Up resistor Control
Register
P04 - I/O Port Pull-Up resistor Control
Register
P05 - I/O Port Pull-Up resistor Control
Register
42
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (20 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
P06 - I/O Port Pull-Up resistor Control
Register
0004AEH
0004AFH
0004B0H
0004B1H
0004B2H
PUCR06
PUCR07
PUCR08
PUCR09
PUCR10
RW
RW
RW
RW
RW
P07 - I/O Port Pull-Up resistor Control
Register
P08 - I/O Port Pull-Up resistor Control
Register
P09 - I/O Port Pull-Up resistor Control
Register
P10 - I/O Port Pull-Up resistor Control
Register
0004B3H
-
Reserved
0004BBH
P00 - I/O Port External Pin State
Register
0004BCH
0004BDH
0004BEH
0004BFH
0004C0H
0004C1H
0004C2H
0004C3H
0004C4H
0004C5H
0004C6H
EPSR00
EPSR01
EPSR02
EPSR03
EPSR04
EPSR05
EPSR06
EPSR07
EPSR08
EPSR09
EPSR10
R
R
R
R
R
R
R
R
R
R
R
P01 - I/O Port External Pin State
Register
P02 - I/O Port External Pin State
Register
P03 - I/O Port External Pin State
Register
P04 - I/O Port External Pin State
Register
P05 - I/O Port External Pin State
Register
P06 - I/O Port External Pin State
Register
P07 - I/O Port External Pin State
Register
P08 - I/O Port External Pin State
Register
P09 - I/O Port External Pin State
Register
P10 - I/O Port External Pin State
Register
0004C7H
-
Reserved
0004CFH
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
43
MB96340 Series
Specification
I/O map (21 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0004D0H ADC analog input enable register 0
0004D1H ADC analog input enable register 1
0004D2H ADC analog input enable register 2
0004D3H
ADER0
ADER1
ADER2
RW
RW
RW
-
Reserved
0004D4H
0004D5H Reserved
Peripheral Resource Relocation
Register 0
0004D6H
0004D7H
PRRR0
PRRR1
RW
RW
Peripheral Resource Relocation
Register 1
0004D8H
-
Reserved
0004DBH
Peripheral Resource Relocation
Register 6
0004DCH
0004DDH
0004DEH
0004DFH
PRRR6
PRRR7
PRRR8
PRRR9
RW
RW
RW
RW
Peripheral Resource Relocation
Register 7
Peripheral Resource Relocation
Register 8
Peripheral Resource Relocation
Register 9
0004E0H RTC - Sub Second Register L
0004E1H RTC - Sub Second Register M
0004E2H RTC - Sub-Second Register H
0004E3H RTC - Second Register
0004E4H RTC - Minutes
WTBRL0
WTBRH0
WTBR1
WTSR
WTBR0
RW
RW
RW
RW
RW
RW
WTMR
0004E5H RTC - Hour
WTHR
RTC - Timer Control Extended
0004E6H
Register
WTCER
RW
RW
0004E7H RTC - Clock select register
0004E8H Reserved
WTCKSR
0004E9H RTC - Timer Control Register H
0004EAH CAL - Calibration unit Control register
WTCRH
CUCR
RW
RW
44
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (22 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0004EBH Reserved
CAL -Sub/RC-clock timer data register
L
0004ECH
0004EDH
0004EEH
0004EFH
0004F0H
0004F1H
CUTDL
CUTDH
CUTR2L
CUTR2H
CUTR1L
CUTR1H
CUTD
RW
RW
R
CAL -Sub/RC-clock timer data register
H
CAL - Main clock timer data register 2
L
CUTR2
CUTR1
CAL - Main clock timer data register 2
H
R
CAL - Main clock timer data register 1
L
R
CAL - Main clock timer data register 1
H
R
0004F2H
-
Reserved
0004F9H
RLT - Timer input select (for
Cascading)
0004FAH
TMISR
RW
0004FBH
-
Reserved
00053DH
00053EH USART7 - Serial Mode Register
00053FH USART7 - Serial Control Register
000540H USART7 - Serial TX Register
000540H USART7 - Serial RX Register
000541H USART7 - Serial Status Register
000542H USART7 - Ext. Control/Com. Register
000543H USART7 - Ext. Status Com. Register
SMR7
SCR7
TDR7
RW
RW
W
RDR7
SSR7
R
RW
RW
RW
ECCR7
ESCR7
USART7 - Baud Rate Generator
000544H
Register
BGRL7
BGRH7
BGR7
RW
RW
USART7 - Baud Rate Generator
000545H
Register
USART7 - Extended Serial Interrupt
000546H
Register
ESIR7
SMR8
RW
RW
000548H USART8 - Serial Mode Register
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
45
MB96340 Series
Specification
I/O map (23 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000549H USART8 - Serial Control Register
00054AH USART8 - Serial TX Register
00054AH USART8 - Serial RX Register
00054BH USART8 - Serial Status Register
00054CH USART8 - Ext. Control/Com. Register
00054DH USART8 - Ext. Status Com. Register
SCR8
TDR8
RW
W
RDR8
SSR8
R
RW
RW
RW
ECCR8
ESCR8
USART8 - Baud Rate Generator
00054EH
Register
BGRL8
BGRH8
ESIR8
BGR8
RW
RW
RW
USART8 - Baud Rate Generator
00054FH
Register
USART8 - Extended Serial Interrupt
000550H
Register
000552H USART9 - Serial Mode Register
000553H USART9 - Serial Control Register
000554H USART9 - Serial TX Register
000554H USART9 - Serial RX Register
000555H USART9 - Serial Status Register
000556H USART9 - Ext. Control/Com. Register
000557H USART9 - Ext. Status Com. Register
SMR9
SCR9
TDR9
RW
RW
W
RDR9
SSR9
R
RW
RW
RW
ECCR9
ESCR9
USART9 - Baud Rate Generator
000558H
Register
BGRL9
BGRH9
BGR9
RW
RW
USART9 - Baud Rate Generator
000559H
Register
USART9 - Extended Serial Interrupt
00055AH
Register
ESIR9
ACSR0
AECSR0
ACSR1
AECSR1
RW
RW
RW
RW
RW
000560H ALARM0 - Control Status Register
ALARM0 - Extended Control Status
000561H
Register
000562H ALARM1 - Control Status Register
ALARM1 - Extended Control Status
000563H
Register
000564H PPG6 - Timer register
000565H PPG6 - Timer register
PTMR6
R
R
46
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (24 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000566H PPG6 - Period setting register
000567H PPG6 - Period setting register
000568H PPG6 - Duty cycle register
000569H PPG6 - Duty cycle register
00056AH PPG6 - Control status register
00056BH PPG6 - Control status register
00056CH PPG7 - Timer register
PCSR6
W
W
PDUT6
PCN6
W
W
PCNL6
PCNH6
RW
RW
R
PTMR7
PCSR7
PDUT7
PCN7
00056DH PPG7 - Timer register
R
00056EH PPG7 - Period setting register
00056FH PPG7 - Period setting register
000570H PPG7 - Duty cycle register
000571H PPG7 - Duty cycle register
000572H PPG7 - Control status register
000573H PPG7 - Control status register
W
W
W
W
PCNL7
PCNH7
RW
RW
PPG11-PPG8 - General Control
register 1 Low
000574H
GCN1L2
GCN1H2
GCN2L2
GCN2H2
GCN12
GCN22
RW
RW
RW
RW
PPG11-PPG8 - General Control
register 1 High
000575H
PPG11-PPG8 - General Control
register 2 Low
000576H
PPG11-PPG8 - General Control
register 2 High
000577H
000578H PPG8 - Timer register
PTMR8
PCSR8
PDUT8
PCN8
R
R
000579H PPG8 - Timer register
00057AH PPG8 - Period setting register
00057BH PPG8 - Period setting register
00057CH PPG8 - Duty cycle register
00057DH PPG8 - Duty cycle register
00057EH PPG8 - Control status register
00057FH PPG8 - Control status register
000580H PPG9 - Timer register
W
W
W
W
PCNL8
PCNH8
RW
RW
R
PTMR9
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
47
MB96340 Series
Specification
I/O map (25 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000581H PPG9 - Timer register
R
W
000582H PPG9 - Period setting register
000583H PPG9 - Period setting register
000584H PPG9 - Duty cycle register
000585H PPG9 - Duty cycle register
000586H PPG9 - Control status register
000587H PPG9 - Control status register
000588H PPG10 - Timer register
PCSR9
PDUT9
PCN9
W
W
W
PCNL9
PCNH9
RW
RW
R
PTMR10
PCSR10
PDUT10
PCN10
000589H PPG10 - Timer register
R
00058AH PPG10 - Period setting register
00058BH PPG10 - Period setting register
00058CH PPG10 - Duty cycle register
00058DH PPG10 - Duty cycle register
00058EH PPG10 - Control status register
00058FH PPG10 - Control status register
000590H PPG11 - Timer register
W
W
W
W
PCNL10
PCNH10
RW
RW
R
PTMR11
PCSR11
PDUT11
PCN11
000591H PPG11 - Timer register
R
000592H PPG11 - Period setting register
000593H PPG11 - Period setting register
000594H PPG11 - Duty cycle register
000595H PPG11 - Duty cycle register
000596H PPG11 - Control status register
000597H PPG11 - Control status register
W
W
W
W
PCNL11
PCNH11
RW
RW
PPG15-PPG12 - General Control
register 1 Low
000598H
GCN1L3
GCN1H3
GCN2L3
GCN2H3
GCN13
GCN23
RW
RW
RW
RW
PPG15-PPG12 - General Control
register 1 High
000599H
PPG15-PPG12 - General Control
register 2 Low
00059AH
PPG15-PPG12 - General Control
register 2 High
00059BH
48
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (26 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
00059CH PPG12 - Timer register
PTMR12
R
R
00059DH PPG12 - Timer register
00059EH PPG12 - Period setting register
00059FH PPG12 - Period setting register
0005A0H PPG12 - Duty cycle register
0005A1H PPG12 - Duty cycle register
0005A2H PPG12 - Control status register
0005A3H PPG12 - Control status register
0005A4H PPG13 - Timer register
PCSR12
PDUT12
PCN12
W
W
W
W
PCNL12
PCNH12
RW
RW
R
PTMR13
PCSR13
PDUT13
PCN13
0005A5H PPG13 - Timer register
R
0005A6H PPG13 - Period setting register
0005A7H PPG13 - Period setting register
0005A8H PPG13 - Duty cycle register
0005A9H PPG13 - Duty cycle register
0005AAH PPG13 - Control status register
0005ABH PPG13 - Control status register
0005ACH PPG14 - Timer register
W
W
W
W
PCNL13
PCNH13
RW
RW
R
PTMR14
PCSR14
PDUT14
PCN14
0005ADH PPG14 - Timer register
R
0005AEH PPG14 - Period setting register
0005AFH PPG14 - Period setting register
0005B0H PPG14 - Duty cycle register
0005B1H PPG14 - Duty cycle register
0005B2H PPG14 - Control status register
0005B3H PPG14 - Control status register
0005B4H PPG15 - Timer register
W
W
W
W
PCNL14
PCNH14
RW
RW
R
PTMR15
PCSR15
PDUT15
0005B5H PPG15 - Timer register
R
0005B6H PPG15 - Period setting register
0005B7H PPG15 - Period setting register
0005B8H PPG15 - Duty cycle register
0005B9H PPG15 - Duty cycle register
W
W
W
W
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
49
MB96340 Series
Specification
I/O map (27 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0005BAH PPG15 - Control status register
0005BBH PPG15 - Control status register
0005BCH
PCNL15
PCNH15
PCN15
RW
RW
-
Reserved
0006DFH
External bus Area configuration
register 0
0006E0H
0006E1H
0006E2H
0006E3H
0006E4H
0006E5H
0006E6H
0006E7H
0006E8H
0006E9H
0006EAH
0006EBH
EACL0
EACH0
EACL1
EACH1
EACL2
EACH2
EACL3
EACH3
EACL4
EACH4
EACL5
EACH5
EAC0
EAC1
EAC2
EAC3
EAC4
EAC5
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
External bus Area configuration
register 0
External bus Area configuration
register 1
External bus Area configuration
register 1
External bus Area configuration
register 2
External bus Area configuration
register 2
External bus Area configuration
register 3
External bus Area configuration
register 3
External bus Area configuration
register 4
External bus Area configuration
register 4
External bus Area configuration
register 5
External bus Area configuration
register 5
0006ECH External bus Area select register 2
0006EDH External bus Area select register 3
0006EEH External bus Area select register 4
0006EFH External bus Area select register 5
0006F0H External bus Mode register
EAS2
EAS3
EAS4
EAS5
EBM
RW
RW
RW
RW
RW
External bus Clock and Function
0006F1H
register
EBCF
RW
50
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (28 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
External bus Address output enable
register 0
0006F2H
0006F3H
0006F4H
EBAE0
EBAE1
RW
RW
External bus Address output enable
register 1
External bus Address output enable
register 2
EBAE2
EBCS
RW
RW
0006F5H External bus Control signal register
0006F6H
-
Reserved
0006FFH
000700H CAN0 - Control register
000701H CAN0 - Control register
000702H CAN0 - Status register
000703H CAN0 - Status register
000704H CAN0 - Error Counter (Transmit)
000705H CAN0 - Error Counter (Receive)
000706H CAN0 - Bit Timing Register
000707H CAN0 - Bit Timing Register
000708H CAN0 - Interrupt Register
000709H CAN0 - Interrupt Register
00070AH CAN0 - Test Register
00070BH CAN0 - Test Register
00070CH CAN0 - BRP Extension register
00070DH CAN0 - BRP Extension register
00070EH
CTRLRL0
CTRLRH0
STATRL0
STATRH0
ERRCNTL0
ERRCNTH0
BTRL0
CTRLR0
STATR0
ERRCNT0
BTR0
RW
R
RW
R
R
R
RW
RW
R
BTRH0
INTRL0
INTR0
INTRH0
R
TESTRL0
TESTRH0
BRPERL0
BRPERH0
TESTR0
BRPER0
RW
R
RW
R
-
Reserved
00070FH
000710H CAN0 - IF1 Command request register
000711H CAN0 - IF1 Command request register
000712H CAN0 - IF1 Command Mask register
000713H CAN0 - IF1 Command Mask register
000714H CAN0 - IF1 Mask Register
IF1CREQL0
IF1CREQH0
IF1CMSKL0
IF1CMSKH0
IF1MSK1L0
IF1MSK1H0
IF1CREQ0
IF1CMSK0
RW
RW
RW
R
IF1MSK10
IF1MSK0
RW
RW
000715H CAN0 - IF1 Mask Register
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
51
MB96340 Series
Specification
I/O map (29 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000716H CAN0 - IF1 Mask Register
000717H CAN0 - IF1 Mask Register
000718H CAN0 - IF1 Arbitration register
000719H CAN0 - IF1 Arbitration register
00071AH CAN0 - IF1 Arbitration register
00071BH CAN0 - IF1 Arbitration register
00071CH CAN0 - IF1 Message Control Register
00071DH CAN0 - IF1 Message Control Register
00071EH CAN0 - IF1 Data A1
IF1MSK2L0
IF1MSK2H0
IF1ARB1L0
IF1ARB1H0
IF1ARB2L0
IF1ARB2H0
IF1MCTRL0
IF1MCTRH0
IF1DTA1L0
IF1DTA1H0
IF1DTA2L0
IF1DTA2H0
IF1DTB1L0
IF1DTB1H0
IF1DTB2L0
IF1DTB2H0
IF1MSK20
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IF1ARB10
IF1ARB20
IF1MCTR0
IF1DTA10
IF1DTA20
IF1DTB10
IF1DTB20
1F1ARB0
IF1DTA0
IF1DTB0
00071FH CAN0 - IF1 Data A1
000720H CAN0 - IF1 Data A2
000721H CAN0 - IF1 Data A2
000722H CAN0 - IF1 Data B1
000723H CAN0 - IF1 Data B1
000724H CAN0 - IF1 Data B2
000725H CAN0 - IF1 Data B2
000726H
-
Reserved
00073FH
000740H CAN0 - IF2 Command request register
000741H CAN0 - IF2 Command request register
000742H CAN0 - IF2 Command Mask register
000743H CAN0 - IF2 Command Mask register
000744H CAN0 - IF2 Mask Register
000745H CAN0 - IF2 Mask Register
000746H CAN0 - IF2 Mask Register
000747H CAN0 - IF2 Mask Register
000748H CAN0 - IF2 Arbitration register
000749H CAN0 - IF2 Arbitration register
00074AH CAN0 - IF2 Arbitration register
00074BH CAN0 - IF2 Arbitration register
FME/EMDC- 2007-9-12
IF2CREQL0
IF2CREQH0
IF2CMSKL0
IF2CMSKH0
IF2MSK1L0
IF2MSK1H0
IF2MSK2L0
IF2MSK2H0
IF2ARB1L0
IF2ARB1H0
IF2ARB2L0
IF2ARB2H0
IF2CREQ0
IF2CMSK0
IF2MSK10
IF2MSK20
IF2ARB10
IF2ARB20
RW
RW
RW
R
IF2MSK0
IF2ARB0
RW
RW
RW
RW
RW
RW
RW
RW
52
MB96340_DS_memory.fm
Specification
MB96340
I/O map (30 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
00074CH CAN0 - IF2 Message Control Register
00074DH CAN0 - IF2 Message Control Register
00074EH CAN0 - IF2 Data A1
00074FH CAN0 - IF2 Data A1
000750H CAN0 - IF2 Data A2
000751H CAN0 - IF2 Data A2
000752H CAN0 - IF2 Data B1
000753H CAN0 - IF2 Data B1
000754H CAN0 - IF2 Data B2
000755H CAN0 - IF2 Data B2
000756H
IF2MCTRL0
IF2MCTRH0
IF2DTA1L0
IF2DTA1H0
IF2DTA2L0
IF2DTA2H0
IF2DTB1L0
IF2DTB1H0
IF2DTB2L0
IF2DTB2H0
IF2MCTR0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IF2DTA10
IF2DTA20
IF2DTB10
IF2DTB20
IF2DTA0
IF2DTB0
-
Reserved
000779H
CAN0 - Transmission Request
Register
000780H
000781H
000782H
000783H
TREQR1L0
TREQR1H0
TREQR2L0
TREQR2H0
TREQR10
TREQR20
TREQR0
R
R
R
R
CAN0 - Transmission Request
Register
CAN0 - Transmission Request
Register
CAN0 - Transmission Request
Register
000784H
-
Reserved
00078FH
000790H CAN0 - New Data Register
000791H CAN0 - New Data Register
000792H CAN0 - New Data Register
000793H CAN0 - New Data Register
000794H
NEWDT1L0
NEWDT1H0
NEWDT2L0
NEWDT2H0
NEWDT10
NEWDT20
NEWDT0
R
R
R
R
-
Reserved
00079FH
0007A0H CAN0 - Interrupt Pending Register
0007A1H CAN0 - Interrupt Pending Register
0007A2H CAN0 - Interrupt Pending Register
INTPND1L0
INTPND1H0
INTPND2L0
INTPND10
INTPND20
INTPND0
R
R
R
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
53
MB96340 Series
Specification
I/O map (31 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0007A3H CAN0 - Interrupt Pending Register
0007A4H
INTPND2H0
R
-
Reserved
0007AFH
0007B0H CAN0 - Message Valid Register
0007B1H CAN0 - Message Valid Register
0007B2H CAN0 - Message Valid Register
0007B3H CAN0 - Message Valid Register
0007B4H
MSGVAL1L0
MSGVAL1H0
MSGVAL2L0
MSGVAL2H0
MSGVAL10
MSGVAL20
MSGVAL0
R
R
R
R
-
Reserved
0007CDH
0007CEH CAN0 - Output enable register
COER0
RW
0007CFH
-
Reserved
0007FFH
000800H CAN1 - Control register
000801H CAN1 - Control register
000802H CAN1 - Status register
000803H CAN1 - Status register
000804H CAN1 - Error Counter (Transmit)
000805H CAN1 - Error Counter (Receive)
000806H CAN1 - Bit Timing Register
000807H CAN1 - Bit Timing Register
000808H CAN1 - Interrupt Register
000809H CAN1 - Interrupt Register
00080AH CAN1 - Test Register
00080BH CAN1 - Test Register
00080CH CAN1 - BRP Extension register
00080DH CAN1 - BRP Extension register
00080EH
CTRLRL1
CTRLRH1
STATRL1
STATRH1
ERRCNTL1
ERRCNTH1
BTRL1
CTRLR1
STATR1
ERRCNT1
BTR1
RW
R
RW
R
R
R
RW
RW
R
BTRH1
INTRL1
INTR1
INTRH1
R
TESTRL1
TESTRH1
BRPERL1
BRPERH1
TESTR1
BRPER1
RW
R
RW
R
-
Reserved
00080FH
000810H CAN1 - IF1 Command request register
IF1CREQL1
IF1CREQ1
RW
54
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (32 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000811H CAN1 - IF1 Command request register
000812H CAN1 - IF1 Command Mask register
000813H CAN1 - IF1 Command Mask register
000814H CAN1 - IF1 Mask Register
000815H CAN1 - IF1 Mask Register
000816H CAN1 - IF1 Mask Register
000817H CAN1 - IF1 Mask Register
000818H CAN1 - IF1 Arbitration register
000819H CAN1 - IF1 Arbitration register
00081AH CAN1 - IF1 Arbitration register
00081BH CAN1 - IF1 Arbitration register
00081CH CAN1 - IF1 Message Control Register
00081DH CAN1 - IF1 Message Control Register
00081EH CAN1 - IF1 Data A1
IF1CREQH1
IF1CMSKL1
IF1CMSKH1
IF1MSK1L1
IF1MSK1H1
IF1MSK2L1
IF1MSK2H1
IF1ARB1L1
IF1ARB1H1
IF1ARB2L1
IF1ARB2H1
IF1MCTRL1
IF1MCTRH1
IF1DTA1L1
IF1DTA1H1
IF1DTA2L1
IF1DTA2H1
IF1DTB1L1
IF1DTB1H1
IF1DTB2L1
IF1DTB2H1
RW
RW
R
IF1CMSK1
IF1MSK11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IF1MSK21
IF1ARB11
IF1ARB21
IF1MCTR1
IF1DTA11
00081FH CAN1 - IF1 Data A1
000820H CAN1 - IF1 Data A2
IF1DTA21
000821H CAN1 - IF1 Data A2
000822H CAN1 - IF1 Data B1
IF1DTB11
000823H CAN1 - IF1 Data B1
000824H CAN1 - IF1 Data B2
IF1DTB21
000825H CAN1 - IF1 Data B2
000826H
-
Reserved
00083FH
000840H CAN1 - IF2 Command request register
000841H CAN1 - IF2 Command request register
000842H CAN1 - IF2 Command Mask register
000843H CAN1 - IF2 Command Mask register
000844H CAN1 - IF2 Mask Register
IF2CREQL1
IF2CREQH1
IF2CMSKL1
IF2CMSKH1
IF2MSK1L1
IF2MSK1H1
IF2MSK2L1
IF2CREQ1
IF2CMSK1
IF2MSK11
IF2MSK21
RW
RW
RW
R
RW
RW
RW
000845H CAN1 - IF2 Mask Register
000846H CAN1 - IF2 Mask Register
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
55
MB96340 Series
Specification
I/O map (33 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
000847H CAN1 - IF2 Mask Register
000848H CAN1 - IF2 Arbitration register
000849H CAN1 - IF2 Arbitration register
00084AH CAN1 - IF2 Arbitration register
00084BH CAN1 - IF2 Arbitration register
00084CH CAN1 - IF2 Message Control Register
00084DH CAN1 - IF2 Message Control Register
00084EH CAN1 - IF2 Data A1
IF2MSK2H1
IF2ARB1L1
IF2ARB1H1
IF2ARB2L1
IF2ARB2H1
IF2MCTRL1
IF2MCTRH1
IF2DTA1L1
IF2DTA1H1
IF2DTA2L1
IF2DTA2H1
IF2DTB1L1
IF2DTB1H1
IF2DTB2L1
IF2DTB2H1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
IF2ARB11
IF2ARB21
IF2MCTR1
IF2DTA11
00084FH CAN1 - IF2 Data A1
000850H CAN1 - IF2 Data A2
IF2DTA21
000851H CAN1 - IF2 Data A2
000852H CAN1 - IF2 Data B1
IF2DTB11
000853H CAN1 - IF2 Data B1
000854H CAN1 - IF2 Data B2
IF2DTB21
000855H CAN1 - IF2 Data B2
000856H
-
Reserved
00087FH
CAN1 - Transmission Request
Register
000880H
000881H
000882H
000883H
TREQR1L1
TREQR1H1
TREQR2L1
TREQR2H1
TREQR11
TREQR21
R
R
R
R
CAN1 - Transmission Request
Register
CAN1 - Transmission Request
Register
CAN1 - Transmission Request
Register
000890H CAN1 - New Data Register
000891H CAN1 - New Data Register
000892H CAN1 - New Data Register
000893H CAN1 - New Data Register
000894H
NEWDT1L1
NEWDT1H1
NEWDT2L1
NEWDT2H1
NEWDT11
NEWDT21
R
R
R
R
-
Reserved
00089FH
56
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (34 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access 32-bit access
Abbreviation
Ac-
cess
Address Register
0008A0H CAN1 - Interrupt Pending Register
0008A1H CAN1 - Interrupt Pending Register
0008A2H CAN1 - Interrupt Pending Register
0008A3H CAN1 - Interrupt Pending Register
0008B0H CAN1 - Message Valid Register
0008B1H CAN1 - Message Valid Register
0008B2H CAN1 - Message Valid Register
0008B3H CAN1 - Message Valid Register
0008CEH CAN1 - Output enable register
INTPND1L1
INTPND1H1
INTPND2L1
INTPND2H1
MSGVAL1L1
MSGVAL1H1
MSGVAL2L1
MSGVAL2H1
COER1
INTPND11
R
R
INTPND21
MSGVAL11
MSGVAL21
R
R
R
R
R
R
RW
External bus area (16-bit address up to
000C00H
000FFFH)
EXTBUS1
EXTBUS1
RW
RW
External bus area (Remaining RAM
001000H
AREA)
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
57
MB96340 Series
Specification
■ INTERRUPT VECTOR TABLE
Interrupt vector table (1 / 4)
Offset in
Vector
number
Index in
ICR to
program
Cleared
by DMA
vector ta-
ble
Vector name
Description
0
1
3FC
3F8
3F4
3F0
3EC
3E8
3E4
3E0
3DC
3D8
3D4
3D0
3CC
3C8
3C4
3C0
3BC
3B8
3B4
3B0
3AC
3A8
3A4
3A0
39C
398
394
CALLV0
CALLV1
CALLV2
CALLV3
CALLV4
CALLV5
CALLV6
CALLV7
RESET
No
No
-
-
2
No
-
3
No
-
4
No
-
5
No
-
6
No
-
7
No
-
8
No
-
9
INT9
No
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
EXCEPTION
NMI
No
-
No
-
Non-Maskable Interrupt
DLY
No
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Delayed Interrupt
RC Timer
RC_TIMER
MC_TIMER
SC_TIMER
RESERVED
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
EXTINT8
EXTINT9
No
No
Main Clock Timer
Sub Clock Timer
Reserved
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
External Interrupt 8
External Interrupt 9
58
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
Interrupt vector table (2 / 4)
Offset in
Vector
Index in
ICR to
program
Cleared
by DMA
vector ta-
number
Vector name
Description
External Interrupt 10
ble
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
390
38C
388
384
380
37C
378
374
370
36C
368
364
360
35C
358
354
350
34C
348
344
340
33C
338
334
330
32C
328
324
320
EXTINT10
EXTINT11
EXTINT12
EXTINT13
EXTINT14
EXTINT15
CAN0
Yes
Yes
Yes
Yes
Yes
Yes
No
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
External Interrupt 11
External Interrupt 12
External Interrupt 13
External Interrupt 14
External Interrupt 15
CAN Controller 0
CAN1
No
CAN Controller 1
PPG0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programmable Pulse Generator 0
Programmable Pulse Generator 1
Programmable Pulse Generator 2
Programmable Pulse Generator 3
Programmable Pulse Generator 4
Programmable Pulse Generator 5
Programmable Pulse Generator 6
Programmable Pulse Generator 7
Programmable Pulse Generator 8
Programmable Pulse Generator 9
Programmable Pulse Generator 10
Programmable Pulse Generator 11
Programmable Pulse Generator 12
Programmable Pulse Generator 13
Programmable Pulse Generator 14
Programmable Pulse Generator 15
Reload Timer 0
PPG1
PPG2
PPG3
PPG4
PPG5
PPG6
PPG7
PPG8
PPG9
PPG10
PPG11
PPG12
PPG13
PPG14
PPG15
RLT0
RLT1
Reload Timer 1
RLT2
Reload Timer 2
RLT3
Reload Timer 3
PPGRLT
Reload Timer 6 - dedicated for PPG
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
59
MB96340 Series
Specification
Interrupt vector table (3 / 4)
Offset in
Vector
number
Index in
ICR to
program
Cleared
by DMA
vector ta-
ble
Vector name
Description
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
31C
318
314
310
30C
308
304
300
2FC
2F8
2F4
2F0
2EC
2E8
2E4
2E0
2DC
2D8
2D4
2D0
2CC
2C8
2C4
2C0
2BC
2B8
2B4
2B0
2AC
ICU0
ICU1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Input Capture Unit 0
Input Capture Unit 1
Input Capture Unit 2
Input Capture Unit 3
Input Capture Unit 4
Input Capture Unit 5
Input Capture Unit 6
Input Capture Unit 7
Output Compare Unit 0
Output Compare Unit 1
Output Compare Unit 2
Output Compare Unit 3
Output Compare Unit 4
Output Compare Unit 5
Output Compare Unit 6
Output Compare Unit 7
Free Running Timer 0
Free Running Timer 1
I2C interface
ICU2
ICU3
ICU4
ICU5
ICU6
ICU7
OCU0
OCU1
OCU2
OCU3
OCU4
OCU5
OCU6
OCU7
FRT0
FRT1
IIC0
IIC1
I2C interface
ADC0
ALARM0
ALARM1
LINR0
LINT0
LINR1
LINT1
LINR2
LINT2
A/D Converter
Alarm Comparator 0
Alarm Comparator 1
LIN USART 0 RX
No
Yes
Yes
Yes
Yes
Yes
Yes
LIN USART 0 TX
LIN USART 1 RX
LIN USART 1 TX
LIN USART 2 RX
LIN USART 2 TX
60
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
Interrupt vector table (4 / 4)
Offset in
Vector
Index in
ICR to
program
Cleared
by DMA
vector ta-
number
Vector name
Description
LIN USART 3 RX
ble
85
86
87
2A8
2A4
2A0
LINR3
LINT3
Yes
Yes
No
85
86
87
LIN USART 3 TX
MAIN_FLASH
Main Flash memory
Satellite Flash memory
(only MB96F348H/T)
88
89
29C
298
SAT_FLASH
LINR7
No
88
89
LIN USART 7 RX
(not available on MB96F348TSA/HSA/
TWA/HWA)
Yes
LIN USART 7 TX
90
91
92
93
94
95
96
294
290
28C
288
284
280
27C
LINT7
LINR8
LINT8
LINR9
LINT9
RTC0
CAL0
Yes
Yes
Yes
Yes
Yes
No
90
91
92
93
94
95
96
(not available on MB96F348TSA/HSA/
TWA/HWA)
LIN USART 8 RX
(not available on MB96F348TSA/HSA/
TWA/HWA)
LIN USART 8 TX
(not available on MB96F348TSA/HSA/
TWA/HWA)
LIN USART 9 RX
(not available on MB96F348TSA/HSA/
TWA/HWA)
LIN USART 9 TX
(not available on MB96F348TSA/HSA/
TWA/HWA)
Real Timer Clock
(not available on MB96F348TSA/HSA/
TWA/HWA)
Clock Calibration Unit
(not available on MB96F348TSA/HSA/
TWA/HWA)
No
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
61
MB96340 Series
Specification
62
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
■ HANDLING DEVICES
Special care is required for the following when handling the device:
• Latch-up prevention
• Treatment of unused pins
• External clock
• Precautions for when not using a sub clock signal
• Notes on PLL clock mode operation
• Power supply pins (VCC/VSS)
• Crystal Oscillator Circuit
• Turn on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
1. Preventing latch-up
• CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
• Latch-up may increase the power supply current drastically, causing thermal damage to the device.
• For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the
digital power-supply voltage.
2. Treatment of unused pins
• Unused input pins may be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
• Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. Therefore they must be pulled up or pulled down through resistors. To prevent latch-
up, those resistors should be more than 2 kΩ.
• Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
• To use external clock, drive the X0 pin and leave X1 pin open.
4. Precautions for when not using a sub clock signal
• If you do not connect pins X0A and X1A to an oscillator, use a pull-down resistor on the X0A pin, and leave
the X1A pin open.
5. Notes on PLL clock mode operation
• If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the freely oscillating PLL. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• Ensure that all VCC-level power supply pins are at the same potential. In addition, ensure the same for all
VSS-level power supply pins. If there are more than one VCC or VSS systems, the device may operate
incorrectly even within the guaranteed operating range.
• Connect VCC and VSS to the device from the power supply with lowest possible impedance.
FME/EMDC- 2007-9-12
MB96300_DS_handling.fm
51
MB96340 Series
Specification
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor
between VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal Oscillator Circuit
• Noise at X0 or X1 pins may possibly cause abnormal operation. Make sure to provide bypass capacitors with
shortest distance to X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to
the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
• It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
• It is highly recommended to evaluate the quartz/MCU system at the quartz manufacturer.
8. Turn on Sequence of Power Supply to A/D Converter and Analog Inputs
• Make sure to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
• Turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning the analog and digital power supplies
simultaneously on or off is acceptable).
9. Connection of Unused Pins of A/D Converter
• Connect unused pins of A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Energization
• To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply
on should be slower than 50µs from 0.2 V to 2.7 V.
11. Stabilization of power supply voltage
• If the power supply voltage varies acutely even within the operation assurance range of the Vcc power supply
voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization
guidelines, stabilize the power supply voltage so that Vcc ripple fluctuations (peak to peak value) in the
commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
52
FME/EMDC- 2007-9-12
MB96300_DS_handling.fm
Specification
MB96340
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Max
Parameter
Power supply voltage
Symbol
Unit
Remarks
Min
VCC
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
*1
AVCC
VCC = AVCC
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > AVRL, AVRL ≥ AVSS
AVRH, AVRL VSS - 0.3 VSS + 6.0
V
*2
Input voltage
VI
VSS - 0.3 VSS + 6.0
VSS - 0.3 VSS + 6.0
V
V
VI ≤ VCC + 0.3V
VO ≤ VCC + 0.3V *2
Output voltage
VO
Applicable to general purpose
I/O pins *3
Maximum Clamp Current
ICLAMP
Σ|ICLAMP|
IOL1
-4.0
+4.0
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
Applicable to general purpose
I/O pins *3
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
-
-
-
-
-
-
-
-
-
Normaloutputsfornormaldrive
output port setting
15
Normaloutputsfornormaldrive
output port setting
IOLAV1
ΣIOL1
5
Normaloutputsfornormaldrive
output port setting
100
50
Normaloutputsfornormaldrive
output port setting
ΣIOLAV1
IOH1
Normaloutputsfornormaldrive
output port setting
-15
-5
Normaloutputsfornormaldrive
output port setting
IOHAV1
ΣIOH1
Normaloutputsfornormaldrive
output port setting
-100
-50
Normaloutputsfornormaldrive
output port setting
“H” level average overall output current
ΣIOHAV1
mA
Power consumption
PD
-
0
600
+70
mW
MB96V300B
others
Operating temperature
TA
oC
+125*4
-40
Operating temperature at Flash erase/
write
oC
oC
TAF
-40
-55
+105
+150
Storage temperature
TSTG
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating. Input/output voltages of standard ports depend on VCC.
FME/EMDC- 2007-9-12
MB96300_DS_el_abs_max_rat.fm
53
MB96340 Series
Specification
*3: • Applicable to all general purpose I/O pins (Pnn_m)
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Notethatifthe+Binputisappliedduringpower-on, thepowersupplyisprovidedfromthepinsandtheresulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistant low voltage
reset in internal vector mode).
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
N-ch
+B input (0V to 16V)
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
*4 If used exceeding TA = +105˚C, be sure to contact Fujitsu for reliability limitations.
*
54
FME/EMDC- 2007-9-12
MB96300_DS_el_abs_max_rat.fm
Specification
MB96340
2. Recommended Conditions
Value
Typ
-
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage
Vcc, DVcc
3.0
5.5
V
Smoothing capacitor at C
pin
CS
4.7
-
10
µF Use a X7R Ceramic Capacitor
0
-
-
+70
MB96V300B
oC
Operating temperature
TA
+125*1
-40
others
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the devices electrical characteristics are warranted when the device is operated
within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU repre-
sentatives beforehand.
*1: If used exceeding TA = +105˚C, be sure to contact Fujitsu for reliability limitations.
FME/EMDC- 2007-9-12
MB96300_DS_el_rec_cond.fm
55
MB96340 Series
Specification
56
FME/EMDC- 2007-9-12
MB96300_DS_el_rec_cond.fm
Specification
MB96340
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Typ
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
Port inputs if
CMOSHysteresis 0.8
VCC +
-
-
-
-
V
V
V
0.3
0.8/0.2 input is
selected
VCC
Port inputs if
CMOSHysteresis 0.7
VCC +
0.3
-
-
0.7/0.3 input is
selected
VCC
VIH
Port inputs if AU-
TOMOTIVE Hys-
0.8
VCC +
0.3
teresis input is se- VCC
lected
Input “H” voltage
Port inputs if TTL
2.0
VCC +
-
-
-
-
-
V
V
V
V
0.3
input is selected
0.8
VCC
RSTX input pin
(CMOS Hysteresis)
VCC +
0.3
VIHR
VIHM
RSTX
-
VCC -
0.3
VCC +
0.3
MD2-MD0
X0,X0A
-
MDx input pins
External clock in “Os-
cillation mode”
VCC +
0.3
VIHX0S
-
2.5
External clock in
“Fast Clock Input
mode” (Not available
in MB96V300,
0.8
VCC
VCC +
0.3
Input “H” voltage
VIHX0F
X0
-
-
V
MB96F34xY/R/A)
Port inputs if
CMOSHysteresis VSS -
0.2
-
-
-
-
-
-
V
V
V
VCC
0.8/0.2 input is
selected
0.3
Port inputs if
CMOSHysteresis VSS -
0.3
VCC
0.7/0.3 input is
selected
0.3
VIL
Port inputs if AU-
TOMOTIVE Hys-
VSS -
0.5
VCC
teresis input is se- 0.3
lected
Input “L” voltage
Port inputs if TTL
input is selected
VSS -
0.3
-
-
-
-
-
0.8
V
V
V
V
VSS -
0.3
RSTX input pin
(CMOS Hysteresis)
VILR
VILM
RSTX
-
-
-
0.2 VCC
VSS -
0.3
VSS +
0.3
MD2-MD0
X0, X0A
MDx input pins
VSS -
0.3
External clock in “Os-
cillation mode”
VILX0S
0.5
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
57
MB96340 Series
Specification
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Typ
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
External clock in
“Fast Clock Input
mode” (Not available
in MB96V300,
VSS -
0.3
VILX0F
X0
-
-
-
-
-
-
-
-
0.2 VCC
V
MB96F34xY/R/A)
4.5V ≤ VCC ≤ 5.5V
IOH = -2mA
Normal
outputs
Driving strength set
to 2mA
VCC -
0.5
VOH2
VOH5
VOH3
VOL2
VOL5
VOL3
-
V
V
V
V
V
V
3.0V ≤ VCC < 4.5V
IOH = -1.6mA
Output“H”voltage
Output“H”voltage
Output “L” voltage
Output “L” voltage
4.5V ≤ VCC ≤ 5.5V
IOH = -5mA
Normal
outputs
Driving strength set
to 5mA
VCC -
0.5
-
3.0V ≤ VCC < 4.5V
IOH = -3mA
4.5V ≤ VCC ≤ 5.5V
IOH = -3mA
VCC -
0.5
I2C outputs
-
3.0V ≤ VCC < 4.5V
IOH = -2mA
4.5V ≤ VCC ≤ 5.5V
IOL = +2mA
Normal
outputs
Driving strength set
to 2mA
-
-
-
0.4
0.4
0.4
3.0V ≤ VCC < 4.5V
IOL = +1.6mA
4.5V ≤ VCC ≤ 5.5V
IOL = +5mA
Normal
outputs
Driving strength set
to 5mA
3.0V ≤ VCC < 4.5V
IOL = +3mA
4.5V ≤ VCC ≤ 5.5V
IOL = +3mA
I2C outputs
Pnn_m
3.0V ≤ VCC < 4.5V
IOL = +2mA
VCC = 5.5V
Input leak current
Pull-up resistance
IIL
-1
-
+1
µA
kΩ
VSS < VI < VCC
Pnn_m,
RSTX
RUP
-
25
50
100
Note: Input/output voltages of ports depend on VCC.
58
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
Specification
MB96340
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Condition
temp
Remarks
Typ
Max Unit
44
57
25˚C
PLL Run mode with
CLKS1/2 = 56MHz =
CLKB = CLKP1, CLKP2
= 28MHz
CLKRC and CLKSC
stopped. Core voltage at
1.9V
mA
60
45
25
125˚C
25˚C
ICCPLL
34
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
CLKRC and CLKSC
stopped. Core voltage at
1.9V
mA
37
26
125˚C
25˚C
4.5
5.1
2.9
3.5
0.4
0.9
5.5
mA
8.5
Main Run mode with
CLKS1/2=CLKB =
CLKP1/2 = 4MHz
CLKPLL, CLKSC and
CLKRC stopped
ICCMAIN
125˚C
25˚C
Power supply cur-
rent in Run
modes*
4
RC Run mode with
CLKS1=CLKS2=CLKB
= CLKP1/2 = 2MHz
CLKMC, CLKPLL and
CLKSC stopped
ICCRCH
mA
6.5
125˚C
25˚C
0.6
mA
3.5
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2=100kHz, SM-
CR:LPMS=0
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age regulator in high
power mode
125˚C
25˚C
ICCRCL
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age regulator in low pow-
er mode, no Flash pro-
gramming/erasing
allowed.
0.15 0.25
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2=100kHz, SM-
CR:LPMS=1
mA
mA
0.65
0.1
3.2
0.2
3
125˚C
25˚C
CLKMC, CLKPLL and
CLKRC stopped, no
Flash programming/
erasing allowed.
Power supply cur-
rent in Run
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
ICCSUB
modes*
0.6
125˚C
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
59
MB96340 Series
Specification
Value
Parameter
Symbol
Condition
temp
Remarks
Typ
Max Unit
9
10.5
mA
13
25˚C
125˚C
25˚C
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
CLKRC and CLKSC
stopped.
9.7
14
ICCSPLL
15.5
mA
18
PLL Sleep mode with
CLKS1/2 = CLKP1 =
56MHz, CLKP2 =
28MHz
CLKRC and CLKSC
stopped.
14.8
1.5
2
125˚C
25˚C
1.8
mA
4.5
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
CLKPLL CLKRC and
CLKSC stopped
ICCSMAIN
125˚C
25˚C
Power supply cur-
rent in Sleep
modes*
0.8
1.4
0.3
0.8
1.3
mA
4
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
CLKMC, CLKPLL and
CLKSC stopped
ICCSRCH
125˚C
25˚C
0.5
mA
3.4
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz, SM-
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age regulator in high
power mode
CR:LPMSS=0
125˚C
25˚C
ICCSRCL
0.06 0.15
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz, SM-
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age regulator in low pow-
er mode
mA
mA
CR:LPMSS=1
0.56
3
125˚C
25˚C
0.04 0.12
Power supply cur-
rent in Sleep
modes*
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
CLKMC, CLKPLL and
CLKRC stopped
ICCSSUB
0.54
2.9
125˚C
60
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
Specification
MB96340
Value
Parameter
Symbol
Condition
temp
Remarks
Typ
Max Unit
1.6
2
25˚C
PLL Timer mode with
CLKMC = 4MHz, CLK-
PLL = 56MHz
CLKRC and CLKSC
stopped. Core voltage at
1.9V
ICCTPLL
mA
4.8
2.1
0.35
0.85
0.1
125˚C
25˚C
0.5
mA
3.3
CLKPLL, CLKRC and
CLKSC stopped. Volt-
age regulator in high
power mode
Main Timer mode with
CLKMC = 4MHz, SM-
CR:LPMSS=0
125˚C
25˚C
ICCTMAIN
ICCTRCH
ICCTRCL
0.15
mA
2.9
CLKPLL, CLKRC and
CLKSC stopped. Volt-
age regulator in low pow-
er mode
Main Timer mode with
CLKMC = 4MHz, SM-
CR:LPMSS=1
0.6
125˚C
25˚C
0.35
0.85
0.1
0.5
mA
3.3
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age regulator in high
power mode
Power supply cur-
rent in Timer
modes*
RC Timer mode with
CLKRC = 2MHz, SM-
CR:LPMSS=0
125˚C
25˚C
0.15
mA
2.9
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age regulator in low pow-
er mode
RC Timer mode with
CLKRC = 2MHz, SM-
CR:LPMSS=1
0.6
125˚C
25˚C
0.3
0.45
mA
3.2
RC Timer mode with
CLKRC = 100kHz, SM-
CR:LPMSS=0
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age in high power mode
0.8
125˚C
25˚C
0.05
0.55
0.1
mA
2.8
RC Timer mode with
CLKRC = 100kHz, SM-
CR:LPMSS=1
CLKMC, CLKPLL and
CLKSC stopped. Volt-
age in low power mode
125˚C
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
61
MB96340 Series
Specification
Value
Parameter
Symbol
Condition
temp
Remarks
Typ
Max Unit
0.03
0.1
mA
2.8
25˚C
Power supply cur-
rent in Timer
modes*
Sub Timer mode with
CLKSC = 32kHz
CLKMC, CLKPLL and
CLKRC stopped
ICCTSUB
0.53
125˚C
0.02 0.08
0.52 2.8
0.015 0.06
25˚C
125˚C
25˚C
VRCR:LPMB[2:0] =
mA
mA
Core voltage at 1.8V
Core voltage at 1.2V
“110”
Stop Mode
ICCH
VRCR:LPMB[2:0] =
“000”
0.4
2.3
125˚C
70
100
25˚C
Power supply cur-
rent foractiveLow
Voltage detector
This current must be
added to all Power sup-
ply currents above
Low voltage detector en-
abled (RCR:LVDE=’1’)
ICCLVD
µA
70
100
125˚C
3
3
4
25˚C
125˚C
25˚C
Clock modulator
current
Clock modulator en-
abled (CMCR:PDX = ‘1’)
Must be added to all cur-
rent above
ICCCLOMO
mA
4
15
15
5
40
40
15
FlashWrite/Erase
current
Must be added to all cur-
rent above
ICCFLASH
CIN
mA
pF
125˚C
Input capacitance
-
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a
32kHz external clock connected to the Sub oscillator. See chapter 10 of the Harware Manual for further details
about voltage regulator control.
62
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
Specification
MB96340
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
3
Typ
Max
16
16
4
-
-
-
-
MHz Whenusinganoscillationcircuit, PLLoff
MHz Whenusinganoscillationcircuit, PLLon
MHz When using an external clock, PLL off
MHz When using an external clock, PLL on
3.5
0
Clock frequency
fC
X0, X1
3.5
4
When using an external clock in “Fast
MHz Clock Input mode” (not available in
MB96V300, MB96F34xY/R/A)
Clock frequency
Clock frequency
fFCI
fCL
X0
0
-
56
32
0
32.768
-
100 kHz When using an oscillation circuit
100 kHz When using an external clock
X0A, X1A
When using slow frequency of RC oscil-
50
1
100
200 kHz
lator
Clock frequency
Clock frequency
fCR
-
When using fast frequency of RC oscil-
lator
2
-
4
MHz
VCO output frequency of PLL
(CLKVCO)
fCLKVCO
PWH, PWL
PWHL, PWLL
tCR, tCF
-
50
8
200 MHz
Inputclockpulse
width
X0
-
-
-
ns Duty ratio is about 30% to 70%
µs
Inputclockpulse
width
X0A
X0
5
-
Input clock rise
and fall time
-
-
5
ns When using external clock
tCYL
VIH
VIL
X0
PWH
PWL
tCR
tCF
tCYLL
VIH
VIL
X0A
PWHL
PWLL
tCR
tCF
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_src_clk.fm
63
MB96340 Series
Specification
64
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_src_clk.fm
Specification
MB96340
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Core Voltage Settings
1.8V 1.9V
Parameter
Symbol
Unit
Remarks
Min
Max
Min
Max
Internal System clock fre-
quency (CLKS1 and
CLKS2)
0
92
0
96
MHz
MHz
fCLKS1, fCLKS2
0
68
0
74
MB96F34xY/R
Internal CPU clock frequen-
cy (CLKB), internal periph-
eral clock frequency
(CLKP1)
fCLKB, fCLKP1
fCLKP2
0
52
0
56
MHz
MHz
Internal peripheral clock fre-
quency (Clock CLKP2)
0
28
0
32
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_int_clk.fm
65
MB96340 Series
Specification
66
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_int_clk.fm
Specification
MB96340
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Typ
-
Parameter
Reset input time
Symbol
Pin
Unit
Remarks
Min
Max
tRSTL
RSTX
500
-
ns
tRSTL
RSTX
0.2 VCC
0.2 VCC
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_rst.fm
67
MB96340 Series
Specification
68
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_rst.fm
Specification
MB96340
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
0.05
1
Typ
Max
30
-
Power on rise time
Power off time
tR
Vcc
Vcc
-
-
ms
tOFF
ms Due to repetitive operation
tR
2.7V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply too rapidly, a power-on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However if voltage drops are below 1 V/s, you can
operate while using the PLL clock.
VCC
Rising edge of 50 mV/ms
maximum is allowed
3 V
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_pon_rst.fm
69
MB96340 Series
Specification
70
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_pon_rst.fm
Specification
MB96340
External Input timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Min
Used Pin input func-
tion
Parameter Symbol
Pin
Condition
Unit
Max
INTn
NMI
External Interrupt
NMI
200
ns
Pnn_m
TINn
General Purpose IO
Reload Timer
Input pulse
width
tINH
tINL
TTGn
ADTG
PPG Trigger input
AD Converter Trigger
tCLKP1 + 200
(tCLKP1=1/fCLKP1)
ns
Free Running Timer
external clock
FRCKn
INn
Input Capture
Note : Relocated Resource Inputs have same characteristics
VIH
VIH
External Pin input
VIL
VIL
tINH
tINL
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_inpt.fm
71
MB96340 Series
Specification
72
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_inpt.fm
Specification
MB96340
External Bus timing
Basic Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
25
Max
tCYC
tCHCL
ns
ECLK
ECLK
tCYC/2-5
tCYC/2-5
-20
tCYC/2+5
tCYC/2+5
20
ns
if CLKB duty cy-
cle is 50%
tCLCH
ns
tCHCBH
tCHCBL
tCLCBH
tCLCBL
tCHLH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-20
20
ECLK →
UBX/ LBX / CSn time
CSn, UBX,
LBX,ECLK
-20
20
-20
20
-10
10
tCHLL
-10
10
ECLK → ALE time
ALE, ECLK
tCLLH
-10
10
tCLLL
-10
10
tCHAV
-15
15
ECLK → address valid time
ECLK → address valid time
A[23:16],ECLK
AD[15:0],ECLK
tCLAV
-15
15
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
-15
15
-15
15
-10
10
RDX, WRX,
WRLX,WRHX,
ECLK
-10
10
ECLK → RDX /WRX time
-10
10
-10
10
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
30
Max
tCYC
tCHCL
ns
ECLK
ECLK
tCYC/2-8
tCYC/2-8
-25
tCYC/2+8
tCYC/2+8
25
ns
if CLKB duty cy-
cle is 50%
tCLCH
ns
tCHCBH
tCHCBL
tCLCBH
tCLCBL
ns
ns
ns
ns
-25
25
ECLK →
UBX/ LBX / CSn time
CSn, UBX,
LBX,ECLK
-25
25
-25
25
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
81
MB96340 Series
Specification
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
-15
-15
-15
-15
-20
-20
-20
-20
-15
-15
-15
-15
Max
15
15
15
15
20
20
20
20
15
15
15
15
tCHLH
tCHLL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ECLK → ALE time
ALE, ECLK
tCLLH
tCLLL
tCHAV
ECLK → address valid time
ECLK → address valid time
A[23:16],ECLK
AD[15:0],ECLK
tCLAV
tCLADV
tCHADV
tCHRWH
tCHRWL
tCLRWH
tCLRWL
RDX, WRX,
WRLX, WRHX,
ECLK
ECLK → RDX /WRX time
tCYC
tCHCL
tCLCH
0.8*Vcc
ECLK
0.2*Vcc
tCLAV
tCHAV
A[23:16]
tCHCBL
tCLCBL
tCHCBH
tCLCBH
CSn
LBX UBX
tCHRWL
tCLRWL
tCHRWH
tCLRWH
RDX
WRX (WRLX, WRHX)
tCHLL
tCLLH
tCLLL
tCHLH
ALE
tCHADV
tCLADV
Address
AD[15:0]
Refer to the Hardware Manual for detailed Timing Charts.
82
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
MB96340
Bus Timing (Read)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF
Value
Sym-
bol
Parameter
Pin
Conditions
Unit Remarks
Min
Max
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 5
tCYC − 5
ns
ns
ns
EACL:STS=1
ALE pulse width
tLHLL ALE
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 5
EACL:STS=0 and
EACL:ACE=0
tCYC − 15
3tCYC/2 − 15
2tCYC − 15
5tCYC/2 − 15
tCYC/2 − 15
tCYC − 15
ns
ns
ns
ns
ns
ns
ns
ns
EACL:STS=1 and
EACL:ACE=0
tAVLL ALE, A[23:16],
EACL:STS=0 and
EACL:ACE=1
EACL:STS=1 and
EACL:ACE=1
Valid address
ALE ↓ time
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL ALE,AD[15 :0]
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 15
2tCYC − 15
EACL:STS=1 and
EACL:ACE=1
EACL:STS=0
EACL:STS=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
tCYC/2 − 15
-15
ns
ns
ns
ns
ns
ns
ALE ↓
tLLAX ALE, AD[15 :0]
tAVRL RDX, A[23:16]
tADVRL RDX,AD[15 :0]
Address valid time
3tCYC/2 − 15
5tCYC/2 − 15
tCYC − 15
2tCYC − 15
Valid address
RDX ↓ time
Valid address
RDX ↓ time
3tCYC − 55
4tCYC − 55
ns
Valid address
A[23:16],
tAVDV
w/o cycle
extension
Valid data input
AD[15;0]
ns
5tCYC/2 − 55 ns
7tCYC/2 − 55 ns
Valid address
w/o cycle
extension;
tADVDV AD[15 :0]
tRLRH RDX
Valid data input
w/o cycle
extension
RDX pulse width
3 tCYC/2 − 5
ns
w/o cycle
extension
RDX ↓
RDX ↑
Valid data input tRLDV RDX, AD[15:0]
Data hold time tRHDX RDX, AD[15:0]
3 tCYC/2 − 50 ns
0
0
ns
Address valid
time
Data hold
A[23:16],
AD[15:0]
tAXDX
ns
ns
ns
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 − 10
tCYC/2 − 10
RDX ↑
ALE ↑ time
tRHLH RDX, ALE
other ECL:STS,
EACL:ACE setting
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
83
MB96340 Series
Specification
Value
Sym-
Parameter
bol
Pin
Conditions
Unit Remarks
Min
Max
tAVCH A[23:16], ECLK
tADVCH AD[15:0], ECLK
tRLCH RDX, CLK
tCYC − 15
tCYC/2 − 15
tCYC/2 − 10
tCYC/2 − 10
− 10
ns
ns
ns
ns
ns
ns
Valid address
ECLK ↑ time
RDX ↓
ALE ↓
ECLK↑
ECLK ↑ time
RDX ↓ time
EACL:STS=0
EACL:STS=1
tLLRL ALE, RDX
Valid data input tCHDV AD[15:0], ECLK
tCYC − 50
(TA = −40 °C to +125 °C, VCC = , VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
Sym-
bol
Parameter
Pin
Conditions
Unit Remarks
Min
Max
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 8
tCYC − 8
ns
ns
ns
EACL:STS=1
ALE pulse width
tLHLL ALE
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 8
EACL:STS=0 and
EACL:ACE=0
tCYC − 20
3tCYC/2 − 20
2tCYC − 20
5tCYC/2 − 20
tCYC/2 − 20
tCYC − 20
ns
ns
ns
ns
ns
ns
ns
ns
EACL:STS=1 and
EACL:ACE=0
tAVLL ALE, A[23:16],
EACL:STS=0 and
EACL:ACE=1
EACL:STS=1 and
EACL:ACE=1
Valid address
ALE ↓ time
EACL:STS=0 and
EACL:ACE=0
EACL:STS=1 and
EACL:ACE=0
tADVLL ALE,AD[15 :0]
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 20
2tCYC − 20
EACL:STS=1 and
EACL:ACE=1
EACL:STS=0
EACL:STS=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
EACL:ACE=0
EACL:ACE=1
tCYC/2 − 20
-20
ns
ns
ns
ns
ns
ns
ALE ↓
tLLAX ALE, AD[15 :0]
tAVRL RDX, A[23:16]
tADVRL RDX,AD[15 :0]
Address valid time
3tCYC/2 − 20
5tCYC/2 − 20
tCYC − 20
2tCYC − 20
Valid address
RDX ↓ time
Valid address
RDX ↓ time
3tCYC − 60
4tCYC − 60
ns
Valid address
A[23:16],
tAVDV
w/o cycle
extension
Valid data input
AD[15;0]
ns
5tCYC/2 − 60 ns
7tCYC/2 − 60 ns
Valid address
w/o cycle
extension;
tADVDV AD[15 :0]
Valid data input
w/o cycle
extension
RDX pulse width
tRLRH RDX
3tCYC/2 − 8
ns
84
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
MB96340
Value
Sym-
bol
Parameter
Pin
Conditions
Unit Remarks
Min
Max
w/o cycle
extension
RDX ↓
RDX ↑
Valid data input tRLDV RDX, AD[15:0]
Data hold time tRHDX RDX, AD[15:0]
3tCYC/2 − 55 ns
0
0
ns
Address valid
time
Data hold
A[23:16]
tAXDX
ns
ns
ns
EACL:STS=1 and
EACL:ACE=1
3tCYC/2 − 15
tCYC/2 − 15
RDX ↑
ALE ↑ time
tRHLH RDX, ALE
other ECL:STS,
EACL:ACE setting
tAVCH A[23:16], ECLK
tADVCH AD[15:0], ECLK
tRLCH RDX, CLK
tCYC − 20
tCYC/2 − 20
tCYC/2 − 15
tCYC/2 − 15
− 15
ns
ns
ns
ns
ns
Valid address
ECLK ↑ time
RDX ↓
ALE ↓
ECLK↑
ECLK ↑ time
RDX ↓ time
EACL:STS=0
EACL:STS=1
tLLRL ALE, RDX
Valid data input tCHDV AD[15:0], ECLK
tCYC − 55
ns
tAVCH
tCHDV
tRLCH
tADVCH
0.8*Vcc
ECLK
tAVLL
tLLAX
tADVLL
tRHLH
ALE
0.2*Vcc
tLHLL
tAVRL
tADVRL
tRLRH
RDX
tLLRL
A[23:16]
tRLDV
tAXDX
tAVDV
tRHDX
tADVDV
VIH
VIL
VIH
VIL
AD[15:0]
Address
Read data
Refer to the Hardware Manual for detailed Timing Charts.
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
85
MB96340 Series
Specification
Bus Timing (Write)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
3tCYC/2 −
EACL:ACE=0
EACL:ACE=1
ns
ns
WRX, WRLX,
WRHX,
A[23:16]
15
Valid address
tAVWL
WRX ↓ time
5tCYC/2 −
15
EACL:ACE=0
EACL:ACE=1
Valid address
WRX, WRLX,
tADVWL WRHX,
tCYC − 15
ns
ns
WRX ↓ time
2tCYC − 15
AD[15:0]
WRX, WRXL,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
tDVWH
tCYC − 5
ns
ns
WRX, WRLX,
WRHX,
AD[15:0]
Valid data output
w/o cycle
extension
tCYC − 20
WRX ↑ time
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
tWHDX
tWHAX
tCYC/2 − 15
tCYC/2 − 15
ns
ns
Data hold time
WRX, WRLX,
WRHX,
A[23:16]
WRX ↑
EACL:STS=0
Address valid time
EBM:ACE=1 and
EACL:STS=1
2tCYC − 10
tCYC − 10
ns
ns
WRX, WRLX,
WRHX, ALE
WRX ↑
ALE ↑ time
ECLK ↑
tWHLH
tWLCH
other EBM:ACE and
EACL:STS setting
WRX ↓
time
WRX, WRLX,
WRHX, ECLK
tCYC/2 − 10
ns
ns
ns
ns
3tCYC/2 −
EACL:ACE=0
EACL:ACE=1
EACL:STS=0
15
WRX, WRLX,
WRHX, CSn
WRX
WRX
CSn time
CSn time
tCSLWL
5tCYC/2 −
15
WRX, WRLX,
WRHX, CSn
tWHCSH
tCYC/2 − 15
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
3tCYC/2 −
EACL:ACE=0
EACL:ACE=1
ns
ns
WRX, WRLX,
WRHX,
A[23:16]
20
Valid address
tAVWL
WRX ↓ time
5tCYC/2 −
20
EACL:ACE=0
EACL:ACE=1
WRX, WRLX,
tADVWL WRHX,
tCYC − 20
Valid address
WRX ↓ time
2tCYC − 20
AD[15:0]
86
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
MB96340
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
WRX, WRLX,
WRHX
w/o cycle
extension
WRX pulse width
tWLWH
tDVWH
tCYC − 8
ns
WRX, WRLX,
WRHX,
AD[15:0]
Valid data output
w/o cycle
extension
tCYC − 25
tCYC/2 − 20
tCYC/2 − 20
ns
ns
ns
WRX ↑ time
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
tWHDX
tWHAX
Data hold time
WRX, WRLX,
WRHX,
A[23:16]
WRX ↑
EACL:STS=0
Address valid time
EBM:ACE=1 and
EACL:STS=1
2tCYC − 15
tCYC − 15
ns
ns
WRX, WRLX,
WRHX, ALE
WRX ↑
ALE ↑ time
ECLK ↑
tWHLH
other EBM:ACE and
EACL:STS setting
WRX ↓
time
WRX, WRLX,
WRHX, ECLK
tWLCH
tCYC/2 − 15
ns
ns
ns
ns
3tCYC/2 −
EACL:ACE=0
EACL:ACE=1
EACL:STS=0
20
WRX, WRLX,
WRHX, CSn
CSn
WRX time
CSn time
tCSLWL
5tCYC/2 −
20
WRX, WRLX,
WRHX, CSn
WRX
tWHCSH
tCYC/2 − 20
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
87
MB96340 Series
Specification
tWLCH
0.8*Vcc
ECLK
ALE
tWHLH
tAVWL
tWLWH
tADVWL
WRX (WRLX, WRHX)
0.2*Vcc
tCSLWL
tWHCSH
CSn
tWHAX
A[23:16]
tDVWH
tWHDX
AD[15:0]
Address
Write data
Refer to the Hardware Manual for detailed Timing Charts.
Ready Input Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Rated Value
Sym-
bol
Test
Condition
Parameter
Pin
Units
Remarks
Min
35
0
Max
RDY setup time
RDY hold time
tRYHS
RDY
RDY
ns
ns
tRYHH
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Rated Value
Sym-
bol
Test
Condition
Parameter
Pin
Units
Remarks
Min
45
0
Max
RDY setup time
RDY hold time
tRYHS
RDY
RDY
ns
ns
tRYHH
Note : If the RDY setup time is insufficient, use the auto-ready function.
88
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
MB96340
0.8*Vcc
ECLK
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
Refer to the Hardware Manual for detailed Timing Charts.
Hold Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,Cl=50pF)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min
Max
Pin floating
HAKX ↓ time
tXHAL
tHAHV
HAKX
HAKX
tCYC − 20 tCYC + 20
tCYC − 20 tCYC + 20
ns
ns
HAKX ↑ time
Pin valid time
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,Cl=50pF)
Value
Parameter
Symbol
Pin
Condition
Units Remarks
Min
Max
Pin floating
HAKX ↓ time
tXHAL
tHAHV
HAKX
HAKX
tCYC − 25 tCYC + 25
tCYC − 25 tCYC + 25
ns
ns
HAKX ↑ time
Pin valid time
0.8*Vcc
HAKX
0.2*Vcc
tHAHV
tXHAL
High-Z
0.8*Vcc
0.2*Vcc
Each pin
Refer to the Hardware Manual for detailed Timing Charts.
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
89
MB96340 Series
Specification
90
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
MB96340
USART timing
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V, IOdrive=5mA, CL=50pF)
VCC = AVCC= 4.5V VCC = AVCC= 3.0V
to 5.5V
to 4.5V
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYCI
tSLOVI
SCKn
4 tCLKP1
4 tCLKP1
ns
ns
SCK ↓ → SOT delay
time
SCKn,
SOTn
-20
+20
-30
+30
SOT → SCK ↑ delay
time
SCKn,
SOTn
N*tCLKP1
N*tCLKP1 -
tOVSHI
tIVSHI
Internal Shift
Clock Mode
- 20 *1
30 *1
SCKn,
SINn
tCLKP1 +
45
tCLKP1 +
55
Valid SIN → SCK ↑
ns
ns
ns
ns
ns
ns
ns
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tSHIXI
0
0
Serial clock “L” pulse
width
tCLKP1 +
10
tCLKP1 +
10
tSLSHE
tSHSLE
tSLOVE
tIVSHE
tSHIXE
SCKn
SCKn
Serial clock “H” pulse
width
tCLKP1 +
10
tCLKP1 +
10
SCK ↓ → SOT delay
time
SCKn,
SOTn
2 tCLKP1
+ 45
2 tCLKP1
+ 55
External Shift
Clock Mode
SCKn,
SINn
tCLKP1/2
+ 10
tCLKP1/2+
Valid SIN → SCK ↑
10
SCK ↑ → Valid SIN
hold time
SCKn,
SINn
tCLKP1 +
10
tCLKP1 +
10
SCK fall time
SCK rise time
tFE
tRE
SCKn
SCKn
20
20
20
20
ns
ns
Notes: • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
4*tCLKP1
2
5*tCLKP1, 6*tCLKP1
7*tCLKP1, 8*tCLKP1
...
3
4
...
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_usart.fm
73
MB96340 Series
Specification
tSCYCI
SCK for
0.8*Vcc
ESCR:SCES = 0
0.2*Vcc
0.2*Vcc
0.8*Vcc
SCK for
0.8*Vcc
ESCR:SCES = 1
0.2*Vcc
tSLOVI
tOVSHI
0.8*Vcc
0.2*Vcc
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Internal Shift Clock Mode
tSLSHE
tSHSLE
SCK for
VIH
VIL
VIH
VIL
VIH
VIL
ESCR:SCES = 0
VIL
SCK for
VIH
VIL
VIH
ESCR:SCES = 1
tFE
tSLOVE
tRE
0.8*Vcc
0.2*Vcc
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
External Shift Clock Mode
74
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_usart.fm
Specification
MB96340
I2C Timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Fast-mode*4
Unit
Standard-mode
Parameter
Symbol
Condition
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA↓→SCL↓
tHDSTA
4.0
0.6
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
1.3
0.6
µs
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
0.6
0
µs
µs
ns
µs
µs
R = 1.7 kΩ,
C = 50 pF*1
Data hold time
SCL↓→SDA↓↑
3.45*2
0.9*3
Data set-up time
SDA↓↑→SCL↑
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL↑→SDA↑
Bus free time between a STOP and START
condition
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
SDA
t
BUS
tSUDAT
t
HDSTA
t
LOW
SCL
tHIGH
t
HDSTA
t
HDDAT
t
SUSTA
tSUSTO
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_i2c.fm
95
MB96340 Series
Specification
96
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_i2c.fm
Specification
MB96340
5. Analogue Digital Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
-
Typ
Max
10
Resolution
-
-
-
-
-
-
-
-
-
bit
Total error
-3
+3
LSB
LSB
Nonlinearity error
-2.5
+2.5
Differential nonlineari-
ty error
-
-
-1.9
-
+1.9
LSB
LSB
AVRL - AVRL+ AVRL +
1.5 0.5 2.5
Zero reading voltage
VOT
ANn
Full scale reading
voltage
AVRH - AVRH - AVRH +
VFST
ANn
LSB
3.5
1.5
0.5
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
4.5V ≤ ΑVCC ≤ 5.5V
3.0V ≤ ΑVCC < 4.5V
1.0
2.0
0.5
1.2
-1
-
-
-
-
-
-
16,500 µs
Compare time
Sampling time
-
-
-
-
-
-
µs
µs
µs
-
+1
+3
µA TA = 25 ˚C
µA TA = 125 ˚C
Analog port input cur-
rent
IAIN
ANn
ANn
-3
Analog input voltage
range
VAIN
AVRL
-
-
AVRH
AVcc
V
V
AVRH/
AVRH2
0.75
AVcc
AVRH
Reference voltage
range
0.25
AVCC
AVRL
IA
AVRL
AVcc
AVcc
AVSS
-
2.5
-
V
-
-
5
5
mA AC Converter active
Power supply current
AD Converter not
operated *1
IAH
µA
AVRH/
AVRL
IR
IRH
-
-
-
-
0.7
1
5
mA AC Converter active
Reference voltage cur-
rent
AVRH/
AVRL
AD Converter not
operated
-
-
µA
Offset between input
channels
ANn
TBD
LSB
*1: If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as AVRH - AVRL becomes smaller.
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Non linearity error: Deviation between a line across zero-transition line ( “00 0000 0000” <--> “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” <--> “11 1111 1111” ) and actual conversion characteristics.
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
75
MB96340 Series
Specification
Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from
an ideal value.
Total error: Difference between an actual value and an ideal value. A total error includes zero transition error,
full-scale transition error, and linear error.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
1.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
76
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
Specification
MB96340
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1)
N + 1
Actual conversion
characteristics
+ VOT }
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004
003
002
001
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Notes on A/D Converter Section
About the external impedance of the analog input and its sampling time
•
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision.
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
77
MB96340 Series
Specification
• Analog input circuit model:
R
Comparator
Analog input
C
Sampling switch
Reference values:
• R = 2.6 kΩ (Max)
• C = 8.5 pF (Max)
To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and
minimum sampling time and either adjust the resistor value and operating frequency or decrease the external
impedance so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7τ,
where τ = RC. If you include the external input resistance (Rext) connected to the analog input, the sampling time
is expressed:
Tsamp [min] = 7.(Rext + R).C
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 mF to the analog input pin.
•
About the error
The accuracy gets worse as |AVRH - AVRL| becomes smaller.
78
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
Specification
MB96340
6. Alarm Comparator
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
Alarm comparator
enabled in fast
IA5ALMF
-
25
40
µA
mode (onechannel)
Alarm comparator
enabled in slow
mode (onechannel)
Power supply current
AVCC
IA5ALMS
-
-
7
-
10
5
µA
µA
Alarm comparator
disabled
IA5ALMH
IALIN
-1
-3
-
-
+1
+3
µA TA = 25 ˚C
µA TA = 125 ˚C
ALARM pin input cur-
rent
ALARM pin input volt-
age range
VALIN
VEVTL
VEVTH
0
-
AVCC
V
0.36 * AVCC
-5%
0.36 * AVCC
+5%
External low threshold
External high threshold
0.36*AVCC
0.78*AVCC
V
V
INTREF=0
ALARM0,
ALARM1
0.78 * AVCC
-3%
0.78 * AVCC
+3%
INTREF=0
Internal low threshold
Internal high threshold
Switching hysteresis
VIVTL
VIVTH
VHYS
1.15
2.45
50
-
1.25
2.55
-
1.35
2.65
250
-
V
V
INTREF=1
INTREF=1
mV
µs
µs
tCOMPF
tCOMPS
0.1
-
CMD=1 (fast)
CMD=0 (slow)
Comparison time
-
100
Comparator
Output
H
L
VEVTL, VEVTH
VIVTL, VIVTH
VALIN
VHYS
FME/EMDC- 2007-9-12
MB96300_DS_el_alarm.fm 101
MB96340 Series
Specification
102
FME/EMDC- 2007-9-12
MB96300_DS_el_alarm.fm
Specification
MB96340
7. LOW VOLTAGE DETECTOR CHARACTERISTICS
(T = -40 ˚C to +125 ˚C, V = AV = 3.0V - 5.5V, V = AV = 0V)
A
CC
CC
SS
SS
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
100
2.95
3.2
I
Power consumptiont
Level 0
-
75
-
µA
V
V
V
V
V
V
V
V
V
V
CCLVD
V
2.7
2.9
3.1
3.5
3.6
3.7
3.8
3.9
4.0
4.1
DL0
V
Level 1
-
DL1
V
Level 2
-
3.4
DL2
V
Level 3
-
3.85
3.95
4.05
4.15
4.3
DL3
V
Level 4
-
DL4
V
Level 5
-
DL5
V
Level 6
-
DL6
V
V
Level 7
-
DL7
CC
V
Level 8
-
4.4
DL8
V
Level 9
-
4.5
DL9
V
Level 10
Level 11
Level 12
Level 13
Level 14
Level 15
DL10
V
DL11
V
DL12
Not supported for this device
V
DL13
V
DL14
V
DL15
FME/EMDC- 2007-9-12
MB96300_DS_el_LVD_char.fm 105
Specification
MB96340
FME/EMDC- 2007-9-12
MB96300_DS_el_LVD_char.fm 106
Specification
MB96340
8. FLASH memory program/erase characteristics
(TA = 25oC, Vcc = 5.0V)
Value
Parameter
Unit
Remarks
Min
Typ
Max
Erasure programming time not
included
Sector erase time
Chip erase time
-
0.9
3.6
s
s
n is the number of Flash sector
of the device
-
-
n*0.9
23
n*3.6
370
Word (16-bit width) pro-
gramming time
System overhead time not in-
cluded
us
100 000 cycles for Tj < 105 oC
*1
Programme/Erase cycle 10 000
Flash data retention time 20
cycle
year
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into into normalized value at 85oC))
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_Flash.fm 107
MB96340 Series
Specification
108
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_Flash.fm
Specification
MB96340
■ EXAMPLE CHARACTERISTICS
The diagrams below show the characteristics of one measured sample of MB96F348HSB with typical process
parameters.
Run Mode
100.00
PLL clock (56 MHz)
10.00
Main osc. (4 MHz)
RC clock (2 MHz)
1.00
RC clock (100 kHz)
0.10
Sub osc.(32 kHz)
0.01
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
Sleep mode
100.00
PLL clock (56 MHz)
10.00
1.00
0.10
0.01
Main osc. (4 MHz)
RC clock (2 MHz)
RC clock (100 kHz)
Sub osc.(32 kHz)
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
FME/EMDC- 2007-9-12
MB96300_DS_el_example_char.fm 109
Specification
MB96340
Timer mode
10.00
PLL clock (56 MHz)
1.00
0.10
0.01
Main osc. (4 MHz)
RC clock (2 MHz)
RC clock (100 kHz)
Sub osc. (32 kHz)
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
Stop mode
1.00
0.10
0.01
0.00
-50.00
0.00
50.00
100.00
150.00
Ta [ºC]
FME/EMDC- 2007-9-12
MB96300_DS_el_example_char.fm 110
Specification
MB96340
Used settings
Clock/Regulator Settings
Selected Source
Clock
Mode
Run mode
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz
CLKP2 = 28 MHz
Regulator in High Power Mode
Core Voltage = 1.9 V
Main osc.
RC clock fast
RC clock slow
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz
Regulator in Low Power Mode A
Core Voltage = 1.8 V
Sleep mode
PLL
CLKS1 = CLKS2 = CLKP1 = 56 MHz
CLKP2 = 28 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.9 V
Main osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
RC clock fast
RC clock slow
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz
(CLKB is stopped in this mode)
Regulator in Low Power Mode A
Core Voltage = 1.8 V
FME/EMDC- 2007-9-12
MB96300_DS_el_example_char.fm 111
Specification
MB96340
Used settings
Clock/Regulator Settings
Selected Source
Clock
Mode
Timer mode
PLL
CLKMC = 4 MHz, CLKPLL = 56 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.9 V
Main osc.
CLKMC = 4 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
RC clock fast
RC clock slow
Sub osc.
CLKRC = 2 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
CLKRC = 100 kHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
CLKSC = 100 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode A, Core Voltage = 1.8 V
Stop mode
stopped
(All clocks are stopped in this mode)
Regulator in Low Power Mode B
FME/EMDC- 2007-9-12
MB96300_DS_el_example_char.fm 112
Specification
MB96340
■ PACKAGE DIMENSION MB96(F)34x LQFP 100P
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Gullwing
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
INDEX
0.10±0.10
(.004±.004)
(Stand off)
100
26
0˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
1
25
0.50(.020)
0.20±0.05
(.008±.002)
0.145±0.055
(.0057±.0022)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2005 FUJITSU LIMITED F100031S-c-2-1
FME/EMDC- 2007-9-12
MB96340_DS_package.fm 113
MB96340 Series
Specification
■ PACKAGE DIMENSION MB96(F)34x QFP 100P
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Gullwing
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
P-QFP100-14×20-0.65
Code
(Reference)
(FPT-100P-M22)
100-pin plastic QFP
(FPT-100P-M22)
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8˚
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F100008S-c-5-5
114
FME/EMDC- 2007-9-12
MB96340_DS_package.fm
Specification
MB96340
■ ORDERING INFORMATION
MCU with CAN controller
Part number
Satellite
flash
Persistant
Subclock Low Volt-
age Reset
Package
Remarks
memory
MB96F346YSA PQC-GSE2
MB96F346RSA PQC-GSE2
MB96F346YWA PQC-GSE2
MB96F346RWA PQC-GSE2
MB96F346YSA PMC-GSE2
MB96F346RSA PMC-GSE2
MB96F346YWA PMC-GSE2
MB96F346RWA PMC-GSE2
MB96F347YSA PQC-GSE2
MB96F347RSA PQC-GSE2
MB96F347YWA PQC-GSE2
MB96F347RWA PQC-GSE2
MB96F347YSA PMC-GSE2
MB96F347RSA PMC-GSE2
MB96F347YWA PMC-GSE2
MB96F347RWA PMC-GSE2
MB96F348TSB PQC-GSE2
MB96F348HSB PQC-GSE2
MB96F348TWB PQC-GSE2
MB96F348HWB PQC-GSE2
MB96F348TSB PMC-GSE2
MB96F348HSB PMC-GSE2
MB96F348TWB PMC-GSE2
MB96F348HWB PMC-GSE2
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
No
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Yes
No
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
Yes
No
Yes
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
Yes
No
Emulated
by ext.
RAM
416 pin Plastic BGA For evalua-
MB96V300BRB-ES
Yes
No
(BGA416-M02)
tion
FME/EMDC- 2007-9-12
MB96340_DS_order.fm 115
MB96340 Series
Specification
MCU without CAN controller
Satellite
flash
Part number
Subclock
Package
Remarks
memory
MB96F346ASA PQC-GSE2
MB96F346AWA PQC-GSE2
MB96F346ASA PMC-GSE2
MB96F346AWA PMC-GSE2
MB96F347ASA PQC-GSE2
MB96F347AWA PQC-GSE2
MB96F347ASA PMC-GSE2
MB96F347AWA PMC-GSE2
MB96F348ASA PQC-GSE2
MB96F348AWA PQC-GSE2
MB96F348ASA PMC-GSE2
MB96F348AWA PMC-GSE2
MB96F348CSB PQC-GSE2
MB96F348CWB PQC-GSE2
MB96F348CSB PMC-GSE2
MB96F348CWB PMC-GSE2
No
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
No
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
100 pin Plastic QFP
(FPT-100P-M22)
Yes
No
Yes
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
116
FME/EMDC- 2007-9-12
MB96340_DS_order.fm
Specification
MB96340
■ REVISION HISTORY
Revision
Date
Modification
1
2007-05-07
2007-05-10
2007-05-23
2007-08-02
Creation
2
3
4
External bus hold timing update
Electrical characteristics updates
Electrical characteristics updates, Product lineup, changes and ordering
information
5
2007-09-12
Addition of the electrical charcateristic examples and the LVD
characteristics specifications, updates of the DC charcateristics. Pin circuit
type drawing modifications.
FME/EMDC- 2007-9-12
MB96340_DS_revisions.fm 117
MB96340 Series
Specification
118
FME/EMDC- 2007-9-12
MB96340_DS_revisions.fm
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