MBM29DL323BE-90TR_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20881-3E

FLASH MEMORY

CMOS

32M (4M × 8/2M × 16) BIT Dual Operation

MBM29DL32XTE/BE ^-80/90/12

■ DESCRIPTION

The MBM29DL32XTE/BE are a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes of 8 bits each or 2M

words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V

V^CCsupply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be

reprogrammed in standard EPROM programmers.

MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which can be considered to be two

separate memory arrays as far as certain operations are concerned. These devices are the same as Fujitsu’s

standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access

from a non-busy bank of the array while an embedded write (either a program or an erase) operation is

simultaneously taking place on the other bank.

(Continued)

■ PRODUCT LINE UP

Part No.

V^CC= 3.3 V

MBM29DL32XTE/BE

+0.3 V

–0.3 V

80

—

Ordering Part No.

+0.6 V

–0.3 V

V^CC= 3.0 V

—

80

30

90

35

12

120

50

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

■ PACKAGES

48-pin plastic TSOP (I)

63-ball plastic FBGA

Marking Side

(BGA-63P-M01)

(FPT-48P-M19)

(FPT-48P-M20)

MBM29DL32XTE/BE^-80/90/12

)

(Continued)

In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under

this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size

combinations; 0.5 Mb/31.5 Mb, 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.

To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable

(OE) controls.

The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E²PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations.

Typically, each sector can be programmed and verified in about 0.5 seconds.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the

factory.

Internallygeneratedandregulatedvoltagesareprovidedfortheprogramanderaseoperations.AlowV^CCdetector

automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data

Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase

cycle has been completed, the devices internally reset to the read mode.

The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously

via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM

programming mechanism of hot electron injection.

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MBM29DL32XTE/BE^-80/90/12

■ FEATURES

• 0.23 µm Process Technology

• Simultaneous Read/Write operations (dual bank)

Multiple devices available with different bank sizes (Refer to Table 1)

Host system can program or erase in one bank, then immediately and simultaneously read from the other bank

Zero latency between read and write operations

Read-while-erase

Read-while-program

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E²PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP(I) (Package suffix: TN – Normal Bend Type, TR – Reversed Bend Type)

63-ball FBGA (Package suffix: PBT

• Minimum 100,000 program/erase cycles

• High performance

80 ns maximum access time

• Sector erase architecture

Eight 4K word and sixty-three 32K word sectors in word mode

Eight 8K byte and sixty-three 64K byte sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Hidden ROM (Hi-ROM) region

64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At V^IL, allows protection of boot sectors, regardless of sector protection/unprotection status

At VIH, allows removal of boot sector protection

At VACC, increases program performance

• Embedded Erase^TM*Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector group protection

Hardware method disables any combination of sector groups from program or erase operations

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

• Temporary sector group unprotection

Temporary sector group unprotection via the RESET pin.

• In accordance with CFI (Common Flash Memory Interface)

*: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

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MBM29DL32XTE/BE^-80/90/12

Table 1 MBM29DL32XTE/BE Device Bank Divisions

Bank 1

Sector sizes

Bank 2

Sector sizes

Device

Part Number

Organization

Megabits

Sixty-three

64K byte/32K word

MBM29DL321TE/BE

MBM29DL322TE/BE

MBM29DL323TE/BE

0.5 Mbit

Eight 8K byte/4K word

31.5 Mbit

Eight 8K byte/4K word,

seven 64K byte/32K word

Fifty-six

64K byte/32K word

4 Mbit

8 Mbit

28 Mbit

24 Mbit

× 8/× 16

Eight 8K byte/4K word,

fifteen 64K byte/32K word

Forty-eight

64K byte/32K word

Eight 8K byte/4K word,

thirty-one 64K byte/

32K word

Thirty-two

64K byte/32K word

MBM29DL324TE/BE

16 Mbit

4

MBM29DL32XTE/BE^-80/90/12

■ PIN ASSIGNMENTS

TSOP(I)

A15

A14

A13

A12

A11

A10

A9

A8

A19

A16

BYTE

VSS

1

2

3

4

5

6

7

8

48

(Marking Side)

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ 15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE

9

A20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE

RESET

N.C.

WP/ACC

RY/BY

A¹⁸

Standard Pinout

A17

A7

A6

A5

A4

A3

A2

A1

VSS

CE

A⁰

FPT-48P-M19

A1

A2

A3

A4

A5

A6

A7

A17

A18

A0

CE

VSS

OE

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

(Marking Side)

DQ⁰

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

VCC

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15/A-1

VSS

RY/BY

WP/ACC

N.C.

RESET

WE

A²⁰

Reverse Pinout

A19

A8

A9

A10

A11

A12

A13

A14

BYTE

A¹⁶

A15

FPT-48P-M20

(Continued)

5

MBM29DL32XTE/BE^-80/90/12

(Continued)

FBGA

(TOP VIEW)

Marking side

A8

B8

L8

M8

*

N.C.

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

N.C.

A13

A12

A14

A15

A16

BYTE DQ15/A-1

Vss

N.C.

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

WE

RESET

N.C.

A19

DQ5

DQ12

Vcc

DQ4

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY WP/ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

CE

J2

K2

L2

M2

*

N.C.

OE

Vss

N.C.

A1

B1

L1

M1

*

N.C.

(BGA-63P-M01)

*: Peripheral Balls on each corner are shorted together via substrate but not connected to the die.

A1 N.C. A2 N.C.

—

A7

A17

A6

A5

—

A7

B7

C7

D7

E7

F7

N.C.

A13

A8 N.C.

B8 N.C.

B1 N.C.

—

C2

D2

E2

F2

G2

H2

J2

—

A³

—

C3

D3

E3

F3

C4 RY/BY C5

WE

C6

A9

—

A4

D4 WP/ACC D5 RESET D6

A8

A12

A2

E4

F4

A18

A20

E5 N.C. E6

A10

A11

A14

A1

F5

A19

F6

A15

A0

G3 DQ0 G4

H3 DQ8 H4

J3 DQ9 J4

K3 DQ1 K4

DQ2

DQ10

DQ11

DQ3

—

G5

DQ5

G6 DQ7 G7

A16

CE

OE

VSS

H5 DQ12 H6 DQ14 H7 BYTE

J5

K5

—

VCC

DQ4

—

J6 DQ13 J7 DQ15/A-1 —

K2

K6 DQ6 K7

VSS

—

L1 N.C. L2 N.C.

M1 N.C. M2 N.C.

—

L7

N.C.

L8 N.C.

—

M7 N.C. M8 N.C.

6

MBM29DL32XTE/BE^-80/90/12

■ BLOCK DIAGRAM

V CC

V SS

Bank 2 Address

Cell Matrix

(Bank 2)

A0 to A20

(A-1)

X-Decoder

RY/BY

RESET

State

Control

&

Command

Register

WE

CE

OE

Status

DQ 0 to DQ 15

Control

BYTE

WP/ACC

DQ 0 to DQ 15

X-Decoder

Bank 1 Address

Cell Matrix

(Bank 1)

7

MBM29DL32XTE/BE^-80/90/12

■ LOGIC SYMBOL

Table 2 MBM29DL32XTE/BE Pin Configuration

Pin Function

A-1

A^-1, A0 to A20

DQ⁰to DQ15

CE

Address Inputs

Data Inputs/Outputs

Chip Enable

21

A0 to A20

16 or 8

DQ 0 to DQ 15

RY/BY

OE

Output Enable

CE

WE

Write Enable

OE

RY/BY

Ready/Busy Output

WE

RESET

BYTE

WP/ACC

Hardware Reset Pin/Temporary Sector

Group Unprotection

RESET

BYTE

Selects 8-bit or 16-bit mode

Hardware Write Protection/Program

Acceleration

WP/ACC

N.C.

V^SS

No Internal Connection

Device Ground

V^CC

Device Power Supply

8

MBM29DL32XTE/BE^-80/90/12

■ DEVICE BUS OPERATION

Table 3 MBM29DL32XTE/BE User Bus Operations (BYTE = V^IH)

Operation

CE OE WE A⁰

A¹

A⁶

A⁹DQ⁰to DQ¹⁵RESET WP/ACC

Auto-Select Manufacturer Code (1)

Auto-Select Device Code (1)

Read (3)

L

H

L

X

L

H

X

H

L

H

A⁰

X

A⁰

L

V^ID

A9

X

Code

DOUT

HIGH-Z

DIN

H

V^ID

L

X

L

A1

X

A6

X

A6

L

Standby

X

H

V^ID

L

Output Disable

X

Write (Program/Erase)

A1

H

X

A9

VID

V^ID

X

Enable Sector Group Protection (2), (4)

Verify Sector Group Protection (2), (4)

Temporary Sector Group Unprotection (5)

Reset (Hardware) / Standby

Boot Block Sector Write Protection

X

H

X

L

Code

X

HIGH-Z

X

Table 4 MBM29DL32XTE/BE User Bus Operations (BYTE = V^IL)

DQ¹⁵/

Operation

CE OE WE

A⁰

A¹

A⁶

A⁹DQ⁰to DQ⁷RESET WP/ACC

A^-1

Auto-Select Manufacturer Code (1)

Auto-Select Device code (1)

Read (3)

L

H

L

H

X

H

L

H

L

V^ID

A9

X

Code

DOUT

H

X

L

A^-1

X

A0

X

A1

X

A6

X

Standby

X

H

HIGH-Z

DIN

Output Disable

X

Write (Program/Erase)

A^-1

A0

A1

A6

A9

Enable Sector Group Protection

(2), (4)

L

X

V^ID

L

H

X

L

X

VID

V^ID

X

Code

X

H

X

Verify Sector Group Protection

(2), (4)

H

X

Temporary Sector Group

Unprotection (5)

X

V^ID

Reset (Hardware) / Standby

X

HIGH-Z

X

L

X

L

Boot Block Sector Write Protection

X

Legend: L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See DC Characteristics for voltage levels.

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 5.

2. Refer to the section on Sector Group Protection.

3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

4. VCC = 3.3 V ± 10%

5. It is also used for the extended sector group protection.

9

MBM29DL32XTE/BE^-80/90/12

Table 5 MBM29DL32XTE/BE Command Definitions

Fourth bus

read/write

cycle

First bus Second bus Third bus

write cycle write cycle write cycle

Fifth bus

Sixth bus

Bus

write

cycles

req’d

Command

sequence

write cycle write cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Read/Reset

1

3

XXXh F0h

—

Byte

Word

Byte

555h

AAh

2AAh

555h

55h

F0h

RA

RD

AAAh

(BA)

555h

Word

Byte

555h

AAh

AAAh

2AAh

555h

Autoselect

3

4

55h

90h

A0h

—

(BA)

AAAh

Word

Byte

555h

AAh

2AAh

555h

—

555h

AAAh

—

Program

PA

PD

AAAh

Program Suspend

Program Resume

1

BA

B0h

30h

—

Word

555h

AAAh

555h

AAAh

BA

2AAh

555h

2AAh

555h

—

555h

AAAh

555h

AAAh

—

555h

AAAh

555h

AAAh

—

2AAh

555h

2AAh

555h

—

555h

AAAh

Chip Erase

6

AAh

55h

80h

AAh

55h

10h

30h

Byte

Word

Byte

Sector Erase

SA

Erase Suspend

Erase Resume

1

B0h

30h

—

BA

—

Word

555h

AAAh

XXXh

BA

2AAh

555h

AAAh

Set to

3

2

4

1

3

4

6

AAh

A0h

90h

55h

PD

20h

—

Fast Mode

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Fast

Program *1

PA

—

XXXh

Reset from

Fast Mode *1

F0h

—

BA

Extended

Sector Group

Protection *2

XXXh 60h SPA 60h SPA 40h SPA SD

55h

Query *3

98h

AAh

—

AAh

555h

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

Hi-ROM

Entry

55h

88h

A0h

80h

Hi-ROM

Program *4

PA

PD

AAh

555h

2AAh

555h

Hi-ROM

Erase *4

55h HRA 30h

AAAh

(HRBA)

555h

Word

Byte

555h

2AAh

555h

Hi-ROM

Exit *4

4

AAh

55h

90h XXXh 00h

—

(HRBA)

AAAh

(Continued)

10

MBM29DL32XTE/BE^-80/90/12

(Continued)

*1: This command is valid while Fast Mode.

*2: This command is valid while RESET = VID.

*3: The valid addresses are A⁶to A0.

*4: This command is valid while Hi-ROM mode.

Notes: 1. Address bits A¹¹to A20 = X = “H” or “L” for all address commands except or Program Address (PA), Sector

Address (SA), and Bank Address (BA).

2. Bus operations are defined in Tables 3 and 4.

3. RA =

PA =

Address of the memory location to be read

Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

Address of the sector to be erased. The combination of A²⁰, A19, A18, A17, A16, A15, A14, A13, and

A¹²will uniquely select any sector.

SA =

BA =

4. RD =

PD =

Bank Address (A¹⁵to A20)

Data read from location RA during read operation.

Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A⁶, A1, A0) = (0, 1, 0).

SD =

Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

6. HRA = Address of the Hi-ROM area

29DL32XTE (Top Boot Type)

Word Mode: 1F8000h to 1FFFFFh

Byte Mode: 3F0000h to 3FFFFFh

29DL32XBE (Bottom Boot Type) Word Mode: 000000h to 007FFFh

Byte Mode: 000000h to 00FFFFh

7. HRBA = Bank Address of the Hi-ROM area

29DL32XTE (Top Boot Type)

:A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 1

29DL32XBE (Bottom Boot Type) :A¹⁵= A¹⁶= A¹⁷= A¹⁸= A¹⁹= A²⁰= 0

8. The system should generate the following address patterns:

Word Mode: 555h or 2AAh to addresses A⁰to A10

Byte Mode: AAAh or 555h to addresses A–1 and A0 to A10

9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

11

MBM29DL32XTE/BE^-80/90/12

In case of applying V^IDon A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultaneous operation

can not be executed.

Table 6.1 MBM29DL321TE/BE Sector Group Protection Verify Autoselect Codes

*1

Type

A¹²to A²⁰

A⁶

A¹

A⁰

Code (HEX)

04h

A^-1

VIL

X

Manufacture’s Code

X

V^IL

VIL

Byte

Word

Byte

59h

MBM29DL321TE

X

V^IL

VIL

VIH

2259h

5Ah

Device

Code

VIL

X

MBM29DL321BE

V^IL

VIL

VIH

VIL

Word

225Ah

Sector Group

Addresses

01h^*2

Sector Group Protection

*1: A-1 is for Byte mode.

VIL

*2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

Table 6.2 Expanded Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A^-1/0

Manufacturer’s Code

04h

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(B)

59h A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

(W) 2259h

(B) 5Ah A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

MBM29DL321TE

0

1

0

1

0

Device

Code

MBM29DL321BE

(W) 225Ah 0

0

1

0

1

0

A^-1/0

01h

Sector Group Protection

(B) : Byte mode

(W): Word mode

Table 6.3 MBM29DL322TE/BE Sector Group Protection Verify Autoselect Codes

*1

Type

A¹²to A²⁰

A⁶

A¹

A⁰

A^-1

VIL

X

Code (HEX)

04h

Manufacture’s Code

X

V^IL

VIL

Byte

Word

Byte

55h

MBM29DL322TE

X

V^IL

VIL

VIH

2255h

56h

Device

Code

VIL

X

MBM29DL322BE

V^IL

VIL

VIH

VIL

Word

2256h

Sector group

addresses

Sector Group Protection

*1: A^-1is for Byte mode.

VIL

01h^*2

*2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

12

MBM29DL32XTE/BE^-80/90/12

Table 6.4 Expanded Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A^-1/0

Manufacturer’s Code

04h

0

1

0

1

0

1

0

1

0

1

0

1

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

(B)

55h A^-1

(W) 2255h 0

(B) 56h A^-1

(W) 2256h 0

MBM29DL322TE

0

1

0

1

0

Device

Code

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

MBM29DL322BE

0

1

0

1

0

A^-1/0

01h

Sector Group Protection

(B) : Byte mode

(W): Word mode

Table 6.5 MBM29DL323TE/BE Sector Group Protection Verify Autoselect Codes

*1

Type

A¹²to A²⁰

A⁶

A¹

A⁰

Code (HEX)

04h

A^-1

VIL

X

Manufacture’s Code

X

V^IL

VIL

Byte

Word

Byte

50h

MBM29DL323TE

X

V^IL

VIL

VIH

2250h

53h

Device

Code

VIL

X

MBM29DL323BE

V^IL

VIL

VIH

VIL

Word

2253h

Sector group

addresses

01h^*2

Sector Group Protection

*1: A^-1is for Byte mode.

VIL

*2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

Table 6.6 Expanded Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A^-1/0

Manufacturer’s Code

04h

0

1

0

1

0

1

0

1

0

1

(B)

50h A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

(W) 2250h 0

(B) 53h A^-1

(W) 2253h 0

MBM29DL323TE

0

1

0

1

0

Device

Code

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

MBM29DL323BE

0

1

0

1

0

A^-1/0

01h

Sector Group Protection

(B) : Byte mode

(W): Word mode

13

MBM29DL32XTE/BE^-80/90/12

Table 6.7 MBM29DL324TE/BE Sector Group Protection Verify Autoselect Codes

*1

Type

A¹²to A²⁰

A⁶

A¹

A⁰

Code (HEX)

04h

A^-1

Manufacture’s Code

X

V^IL

VIL

X

Byte

Word

Byte

5Ch

MBM29DL324TE

X

V^IL

VIL

VIH

225Ch

5Fh

Device

Code

VIL

X

MBM29DL324BE

V^IL

VIL

VIH

VIL

Word

225Fh

Sector group

addresses

01h^*2

Sector Group Protection

*1: A^-1is for Byte mode.

VIL

*2: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

Table 6.8 Expanded Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A^-1/0

Manufacturer’s Code

04h

0

1

0

1

0

1

0

1

0

1

0

1

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

(B) 5Ch A^-1

(W) 225Ch 0

(B) 5Fh A^-1

(W) 225Fh 0

MBM29DL324TE

0

1

0

1

0

Device

Code

HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

MBM29DL324BE

0

1

0

1

0

A^-1/0

01h

Sector Group Protection

(B) : Byte mode

(W): Word mode

14

MBM29DL32XTE/BE^-80/90/12

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

Table 7.1 Sector Address Tables (MBM29DL321TE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32

00000h to 0FFFFh

10000h to 1FFFFh

20000h to 2FFFFh

30000h to 3FFFFh

40000h to 4FFFFh

50000h to 5FFFFh

60000h to 6FFFFh

70000h to 7FFFFh

80000h to 8FFFFh

90000h to 9FFFFh

A0000h to AFFFFh

B0000h to BFFFFh

C0000h to CFFFFh

D0000h to DFFFFh

E0000h to EFFFFh

F0000h to FFFFFh

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

Bank 2 SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

(Continued)

15

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

1

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

SA48

Bank 2

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

8/4

3F0000h to 3F1FFFh 1F8000h to 1F8FFFh

3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FBFFFh 1FD000h to 1FDFFFh

3FC000h to 3FDFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

0

1

0

1

0

SA66

Bank 1

0

1

SA67

1

0

SA68

SA69

SA70

1

0

1

0

1

MBM29DL321TE Top Boot Sector Architecture

Note: The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH).

16

MBM29DL32XTE/BE^-80/90/12

Table 7.2 Sector Address Tables (MBM29DL321BE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

(Continued)

SA53

Bank 2

SA52

SA51

SA50

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

SA36

SA35

17

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

SA25

SA24

SA23

SA22

Bank 2 SA21

SA20

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

X

1

X

1

X

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 010000h to 01FFFFh 008000h to 00FFFFh

SA8

SA7

8/4

00E000h to 00FFFFh 007000h to 007FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00A000h to 00BFFFh 005000h to 005FFFh

008000h to 009FFFh 004000h to 004FFFh

006000h to 007FFFh 003000h to 003FFFh

004000h to 005FFFh 002000h to 002FFFh

002000h to 003FFFh 001000h to 001FFFh

000000h to 001FFFh 000000h to 000FFFh

SA6

1

0

SA5

1

0

1

SA4

Bank 1

1

0

SA3

0

1

SA2

SA1

SA0

0

1

0

1

0

MBM29DL321BE Bottom Boot Sector Architecture

Note : The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH).

18

MBM29DL32XTE/BE^-80/90/12

Table 8.1 Sector Address Tables (MBM29DL322TE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 000000h to 00FFFFh 000000h to 007FFFh

64/32 010000h to 01FFFFh 008000h to 00FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

Bank 2 SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

(Continued)

19

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA35

SA36

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

Bank 2 SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

Bank 1 SA63

SA64

8/4

3F0000h to 3F1FFFh 1F8000h to 1F8FFFh

3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FBFFFh 1FD000h to 1FDFFFh

3FC000h to 3FDFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

0

1

SA65

0

1

0

SA66

0

1

SA67

1

0

SA68

1

0

1

SA69

1

0

SA70

1

MBM29DL322TE Top Boot Sector Architecture

Note : The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH).

20

MBM29DL32XTE/BE^-80/90/12

Table 8.2 Sector Address Tables (MBM29DL322BE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

SA53

Bank 2

SA52

SA51

SA50

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

SA36

SA35

(Continued)

21

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

X

1

X

1

X

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 010000h to 01FFFFh 008000h to 00FFFFh

SA25

Bank 2

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

SA8

Bank 1 SA7

SA6

8/4

00E000h to 00FFFFh 007000h to 007FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00A000h to 00BFFFh 005000h to 005FFFh

008000h to 009FFFh 004000h to 004FFFh

006000h to 007FFFh 003000h to 003FFFh

004000h to 005FFFh 002000h to 002FFFh

002000h to 003FFFh 001000h to 001FFFh

000000h to 001FFFh 000000h to 000FFFh

1

0

SA5

1

0

1

SA4

1

0

SA3

0

1

SA2

0

1

0

SA1

0

1

SA0

0

MBM29DL322BE Bottom Boot Sector Architecture

Note: The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH).

22

MBM29DL32XTE/BE^-80/90/12

Table 9.1 Sector Address Tables (MBM29DL323TE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 000000h to 00FFFFh 000000h to 007FFFh

64/32 010000h to 01FFFFh 008000h to 00FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

Bank 2 SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

(Continued)

23

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA35

SA36

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

SA37

SA38

SA39

SA40

Bank 2 SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

Bank 1 SA59

SA60

SA61

SA62

SA63

8/4

3F0000h to 3F1FFFh 1F8000h to 1F8FFFh

3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FBFFFh 1FD000h to 1FDFFFh

3FC000h to 3FDFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

SA64

0

1

SA65

0

1

0

SA66

0

1

SA67

1

0

SA68

1

0

1

SA69

1

0

SA70

1

MBM29DL323TE Top Boot Sector Architecture

Note: The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH).

24

MBM29DL32XTE/BE^-80/90/12

Table 9.2 Sector Address Tables (MBM29DL323BE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

SA55

SA54

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

SA53

Bank 2

SA52

SA51

SA50

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

SA36

SA35

(Continued)

25

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA34

SA33

SA32

SA31

SA30

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

X

1

X

1

X

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 010000h to 01FFFFh 008000h to 00FFFFh

SA29

Bank 2

SA28

SA27

SA26

SA25

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

Bank 1 SA11

SA10

SA9

SA8

SA7

8/4

00E000h to 00FFFFh 007000h to 007FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00A000h to 00BFFFh 005000h to 005FFFh

008000h to 009FFFh 004000h to 004FFFh

006000h to 007FFFh 003000h to 003FFFh

004000h to 005FFFh 002000h to 002FFFh

002000h to 003FFFh 001000h to 001FFFh

000000h to 001FFFh 000000h to 000FFFh

SA6

1

0

SA5

1

0

1

SA4

1

0

SA3

0

1

SA2

0

1

0

SA1

0

1

SA0

0

MBM29DL323BE Bottom Boot Sector Architecture

Note : The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH).

26

MBM29DL32XTE/BE^-80/90/12

Table 10.1 Sector Address Tables (MBM29DL324TE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 000000h to 00FFFFh 000000h to 007FFFh

64/32 010000h to 01FFFFh 008000h to 00FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

SA15

Bank 2

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

Bank 1 SA33

SA34

(Continued)

27

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

X

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

SA52

Bank 1

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

8/4

3F0000h to 3F1FFFh 1F8000h to 1F8FFFh

3F2000h to 3F3FFFh 1F9000h to 1F9FFFh

3F4000h to 3F5FFFh 1FA000h to 1FAFFFh

3F6000h to 3F7FFFh 1FB000h to 1FBFFFh

3F8000h to 3F9FFFh 1FC000h to 1FCFFFh

3FA000h to 3FBFFFh 1FD000h to 1FDFFFh

3FC000h to 3FDFFFh 1FE000h to 1FEFFFh

3FE000h to 3FFFFFh 1FF000h to 1FFFFFh

0

1

0

1

0

1

0

1

0

1

0

1

MBM29DL324TE Top Boot Sector Architecture

Note: The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH).

28

MBM29DL32XTE/BE^-80/90/12

Table 10.2 Sector Address Tables (MBM29DL324BE)

Sector address

Bank address

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

SA70

SA69

SA68

SA67

SA66

SA65

SA64

SA63

SA62

SA61

SA60

SA59

SA58

SA57

SA56

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

SA55

Bank 2

SA54

SA53

SA52

SA51

SA50

SA49

SA48

SA47

SA46

SA45

SA44

SA43

SA42

SA41

SA40

SA39

SA38

SA37

Bank 1

SA36

SA35

(Continued)

29

MBM29DL32XTE/BE^-80/90/12

(Continued)

Sector address

Bank address

Sector

size

(Kbytes/

Kwords)

(×8)

Address range

(×16)

Address range

Bank Sector

A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²A¹¹

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

SA25

SA24

SA23

SA22

SA21

SA20

SA19

SA18

Bank 1 SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

X

1

X

1

X

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 010000h to 01FFFFh 008000h to 00FFFFh

SA8

SA7

8/4

00E000h to 00FFFFh 007000h to 007FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00A000h to 00BFFFh 005000h to 005FFFh

008000h to 009FFFh 004000h to 004FFFh

006000h to 007FFFh 003000h to 003FFFh

004000h to 005FFFh 002000h to 002FFFh

002000h to 003FFFh 001000h to 001FFFh

000000h to 001FFFh 000000h to 000FFFh

SA6

1

0

SA5

1

0

1

SA4

1

0

SA3

0

1

SA2

0

1

0

SA1

0

1

SA0

0

MBM29DL324BE Bottom Boot Sector Architecture

Note : The address range is A²⁰: A-1 if in byte mode (BYTE = VIL).

The address range is A20: A0 if in word mode (BYTE = VIH)

30

MBM29DL32XTE/BE^-80/90/12

Table 11.1 Sector Group Addresses (MBM29DL32XTE)

(Top Boot Block)

Sector group

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

0

A¹⁵

0

A¹⁴

A¹³

A¹²

Sectors

SGA0

0

X

SA0

0

1

SGA1

0

1

0

X

SA1 to SA3

1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

SA32 to SA35

SA36 to SA39

SA40 to SA43

SA44 to SA47

SA48 to SA51

SA52 to SA55

SA56 to SA59

SGA16

1

0

1

X

SA60 to SA62

1

0

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

1

31

MBM29DL32XTE/BE^-80/90/12

Table 11.2 Sector Group Addresses (MBM29DL32XBE)

(Bottom Boot Block)

Sector group

SGA0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

SGA8

0

1

0

X

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SGA23

SGA24

1

0

1

X

SA67 to SA69

SA70

1

0

1

32

MBM29DL32XTE/BE^-80/90/12

Table 12 Common Flash Memory Interface Code

DQ⁰to DQ¹⁵

6

DQ⁰to DQ¹⁵

Description

A⁰to A⁶

Description

A⁰to A

Query-unique ASCII string

“QRY”

10h

11h

12h

0051h

0052h

0059h

Query-unique ASCII string

“PRI”

40h

41h

42h

0050h

0052h

0049h

Primary OEM Command Set

2h: AMD/FJ standard type

13h

14h

0002h

0000h

Major version number, ASCII

Minor version number, ASCII

43h

44h

45h

0031h

0032h

0000h

Address for Primary

Extended Table

15h

16h

0040h

0000h

Address Sensitive Unlock

0h = Required

1h = Not Required

Alternate OEM Command

Set (00h = not applicable)

17h

18h

0000h

Erase Suspend

46h

47h

48h

0002h

0001h

0h = Not Supported

1h = To Read Only

2h = To Read & Write

Address for Alternate OEM

Extended Table

19h

1Ah

0000h

V^CCMin. (write/erase)

D7-4: V, D3-0: 100 mV

1Bh

0027h

Sector Protection

0h = Not Supported

X = Number of sectors in per

group

V^CCMax. (write/erase)

D7-4: V, D3-0: 100 mV

1Ch

0036h

VPP Min. voltage

V^PPMax. voltage

1Dh

1Eh

1Fh

0000h

0004h

Sector Temporary

Unprotection

00h = Not Supported

01h = Supported

Typical timeout per single

byte/word write 2^Nµs

Sector Protection Algorithm

49h

4Ah

0004h

00XXh

Typical timeout for Min. size

20h

21h

22h

23h

24h

25h

26h

27h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

0016h

buffer write 2^Nµs

Number of Sector for Bank 2

00h = Not Supported

Typical timeout per individual

block erase 2^Nms

3Fh = MBM29DL321TE

38h = MBM29DL322TE

30h = MBM29DL323TE

20h = MBM29DL324TE

3Fh = MBM29DL321BE

38h = MBM29DL322BE

30h = MBM29DL323BE

20h = MBM29DL324BE

Typical timeout for full chip

erase 2^Nms

Max. timeout for byte/word

write 2^Ntimes typical

Max. timeout for buffer write

2^Ntimes typical

Burst Mode Type

00h = Not Supported

4Bh

4Ch

4Dh

0000h

0085h

Max. timeout per individual

block erase 2^Ntimes typical

Page Mode Type

00h = Not Supported

Max. timeout for full chip

erase 2^Ntimes typical

Device Size = 2^Nbyte

ACC (Acceleration) Supply

Minimum

00h = Not Supported,

D7-4: V, D3-0: 100 mV

Flash Device Interface

description

28h

29h

0002h

0000h

Max. number of byte in

multi-byte write = 2^N

2Ah

2Bh

0000h

ACC (Acceleration) Supply

Maximum

4Eh

0095h

Number of Erase Block

Regions within device

2Ch

0002h

00h = Not Supported,

D7-4: V, D3-0: 100 mV

Erase Block Region 1

Information

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Boot Type

02h = MBM29DL32XBE

03h = MBM29DL32XTE

4Fh

50h

00XXh

0001h

Program Suspend

00h = Not Supported,

01h = Supported

Erase Block Region 2

Information

31h

32h

33h

34h

003Eh

0000h

0001h

33

MBM29DL32XTE/BE^-80/90/12

■ FUNCTIONAL DESCRIPTION

• Simultaneous Operation

MBM29DL32XTE/BE have feature, which is capability of reading data from one bank of memory while a program

or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the

conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank

selection can be selected by bank address (A15 to A20) with zero latency.

The MBM29DL321TE/BE have two banks which contain

Bank 1 (8KB × eight sectors) and Bank 2 (64KB × sixty-three sectors).

The MBM29DL322TE/BE have two banks which contain

Bank 1 (8KB × eight sectors, 64KB × seven sectors) and Bank 2 (64KB × fifty-six sectors).

The MBM29DL323TE/BE have two banks which contain

Bank 1 (8KB × eight sectors, 64KB × fifteen sectors) and Bank 2 (64KB × forty-eight sectors).

The MBM29DL324TE/BE have two banks which contain

Bank 1 (8KB × eight sectors, 64KB × thirty-one sectors) and Bank 2 (64KB × thirty-two sectors).

The simultaneous operation can not execute multi-function mode in the same bank. Table 13 shows combination

to be possible for simultaneous operation. (Refer to the Figure 11 Back-to-back Read/Write Timing Diagram.)

Table 13 Simultaneous Operation

Case

Bank 1 status

Read Mode

Bank 2 status

Read Mode

1

2

3

4

5

6

7

Read Mode

Autoselect Mode

Program Mode

Erase Mode *

Read Mode

Autoselect Mode

Program Mode

Erase Mode *

Read Mode

*: An erase operation may also be supended to read from or program to a sector not being erased.

• Read Mode

TheMBM29DL32XTE/BEhave twocontrolfunctionswhichmustbesatisfiedinordertoobtaindataattheoutputs.

CE is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after

power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”

34

MBM29DL32XTE/BE^-80/90/12

• Standby Mode

There are two ways to implement the standby mode on the MBM29DL32XTE/BE devices, one using both the

CE and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.

Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC

active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either

of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE

= “H” or “L”). Under this condition the current is consumed is less than 5 µA Max. Once the RESET pin is taken

high, the device requires tRH of wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

• Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

MBM29DL32XTE/BE data. This mode can be used effectively with an application requested low power con-

sumption such as handy terminals.

To activate this mode, MBM29DL32XTE/BE automatically switch themselves to low power mode when

MBM29DL32XTE/BE addresses remain stably during access fine of 150 ns. It is not necessary to control CE,

WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).

During simultaneous operation, V^CCactive current (ICC2) is required.

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,

the mode is canceled automatically and MBM29DL32XTE/BE read-out the data for changed addresses.

• Output Disable

With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins

to be in a high impedance state.

• Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the devices to be programmed with its corresponding programming algorithm. This mode is functional over the

entire temperature range of the devices.

To activate this mode, the programming equipment must force V^ID(11.5 V to 12.5 V) on address pin A9. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All

addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Tables 3 and 4.)

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29DL32XTE/BE are erased or programmed in a system without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 5. (Refer to Autoselect Command section.)

Byte 0 (A⁰= VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device

identifier code (MBM29DL321TE = 59h and MBM29DL321BE = 5Ah for ×8 mode; MBM29DL321TE = 2259h

and MBM29DL321BE = 225Ah for ×16 mode). (MBM29DL322TE = 55h and MBM29DL322BE = 56h for ×8

mode; MBM29DL322TE = 2255h and MBM29DL322BE = 2256h for ×16 mode). (MBM29DL323TE = 50h and

MBM29DL323BE = 53h for ×8 mode; MBM29DL323TE = 2250h and MBM29DL323BE = 2253h for ×16 mode).

(MBM29DL324TE = 5Ch and MBM29DL324BE = 5Fh for ×8 mode; MBM29DL324TE = 225Ch and

MBM29DL324BE = 225Fh for ×16 mode). These two bytes/words are given in the tables 11.1 to 11.8. All

identifiers for manufactures and device will exhibit odd parity with DQ⁷defined as the parity bit. In order to read

the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 6.1 to 6.8.)

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MBM29DL32XTE/BE^-80/90/12

• Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

• Sector Group Protection

The MBM29DL32XTE/BE feature hardware sector group protection. This feature will disable both program and

erase operations in any combination of twenty five sector groups of memory. (See Tables 11.1 and 11.2). The

sector group protection feature is enabled using programming equipment at the user’s site. The device is shipped

with all sector groups unprotected.

To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest

VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14,

A13, and A12) should be set to the sector to be protected. Tables 7.1 to 10.2 define the sector address for each

of the seventy one (71) individual sectors, and tables 11.1 and 11.2 define the sector group address for each of

the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge

of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held

constant during the WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13,

and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector.

Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except

for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer

and device codes. A-1 requires to apply to VIL on byte mode.

It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.

Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17,

A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected

sector group. See Tables 6.1 to 6.8 for Autoselect codes.

• Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the MBM29DL32XTE/BE

devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to

high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting

the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector

groups will be protected again. Refer to Figures 19 and 27.

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MBM29DL32XTE/BE^-80/90/12

• RESET

Hardware Reset

The MBM29DL32XTE/BE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse

requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset

to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware

reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please

note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 14 for the timing

diagram. Refer to Temporary Sector Group Unprotection for additional functionality.

• Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain boot sectors without using VID.

This function is one of two provided by the WP/ACC pin.

If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two

“outermost” 8K byte boot sectors independently of whether those sectors were protected or unprotected using

the method described in “Sector Protection/Unprotection”. The two outermost 8K byte boot sectors are the two

sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the

highest addresses in a top-boot-configured device.

(MBM29DL32XTE: SA69 and SA70, MBM29DL32XBE: SA0 and SA1)

If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot

sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two

sectors depends on whether they were last protected or unprotected using the method described in “Sector

protection/unprotection”.

• Accelerated Program Operation

MBM29DL32XTE/BE offers accelerated program operation which enables the programming in high speed.

If the system asserts V^ACCto the WP/ACC pin, the device automatically enters the acceleration mode and the

time required for program operation will reduce to about 60%. This function is primarily intended to allow high

speed program, so caution is needed as the sector group will temporarily be unprotected.

The system would use a fact program command sequence when programming during acceleration mode.

Set command to fast mode and reset command from fast mode are not necessary. When the device enters the

acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the WP/ACC pin returns the device to normal operation. Do not remove V^ACCfrom WP/

ACC pin while programming. See Figure 21.

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MBM29DL32XTE/BE^-80/90/12

■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the

read mode. Some commands are required Bank Address (BA) input. When command sequences are inputted

to bank being read, the commands have priority than reading. Table 5 defines the valid register command

sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the

Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands

are valid only while the Program operation is in progress. Moreover both Read/Reset commands are functionally

equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7

and DQ8 to DQ15 bits are ignored.

• Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-

processor read cycles retrieve array data from the memory. The devices remain enabled for reads until the

command register contents are altered.

The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

• Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-

grammers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage

onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write

cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device

codes can be read from the bank, and an actual data of memory cell can be read from the another bank.

Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read

cycle from address (BA)01h for ×16((BA)02h for ×8) returns the device code (MBM29DL321TE = 59h and

MBM29DL321BE = 5Ah for ×8 mode; MBM29DL321TE = 2259h and MBM29DL321BE = 225Ah for ×16 mode).

(MBM29DL322TE = 55h and MBM29DL322BE = 56h for ×8 mode; MBM29DL322TE = 2255h and

MBM29DL322BE = 2256h for ×16 mode). (MBM29DL323TE = 50h and MBM29DL323BE = 53h for ×8 mode;

MBM29DL323TE = 2250h and MBM29DL323BE = 2253h for ×16 mode). (MBM29DL324TE = 5Ch and

MBM29DL324BE = 5Fh for ×8 mode; MBM29DL324TE = 225Ch and MBM29DL324BE = 225Fh for ×16 mode).

(See Tables 6.1 to 6.8.)

All manufacturer and device codes will exhibit odd parity with DQ⁷defined as the parity bit. Sector state (protection

or unprotection) will be informed by address (BA)02h for ×16 ((BA)04h for ×8). Scanning the sector group

addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at

device output DQ0 for a protected sector group. The programming verification should be performed by verify

sector group protection on the protected sector. (See Tables 10 and 11.)

The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and

device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command

sequence into the register and then Autoselect command should be written into the bank to be read.

If the software (program code) for Autoselect command is stored into the Flash memory, the device and manu-

facture codes should be read from the other bank where is not contain the software.

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MBM29DL32XTE/BE^-80/90/12

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and

also to write the Autoselect command during the operation, execute it after writing Read/Reset command se-

quence.

• Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle

operation. There are two “unlock” write cycles. These are followed by the program set-up command and data

write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is

latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever

happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,

the system is not required to provide further controls or timings. The device will automatically provide adequate

internally generated program pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit),

or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 14,

Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by

the system at this particular instance of time. Hence, Data Polling must be performed at the memory location

which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the pro-

gramming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 22 illustrates the Embedded Program^TMAlgorithm using typical command strings and bus operations.

• Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit), or

RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the

device returns to read the mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

Figure 23 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

• Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.

Aftertime-outof“tTOW”fromtherisingedgeofthelastsectorerasecommand, thesectoreraseoperationwillbegin.

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MBM29DL32XTE/BE^-80/90/12

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 5. This sequence

is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than “t^TOW” otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this

condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW”

from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase

command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out

window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section

DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period

will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once

execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow

them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the

sector erase buffer may be done in any sequence and with any number of sectors (0 to 38).

Sector erase does not require the user to program the devices prior to erase. The devices automatically program

all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit), or

RY/BY.

The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status

section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at

an address within any of the sectors being erased.

Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector

Erase

In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not perform.

Figure 23 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

• Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if

written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command

(B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension

of the erase operation.

Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being

erasing or suspending should be set when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of “t^SPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the

RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must

use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been

suspended. Further writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, pro-

gramming in this mode is the same as programming in the regular Program mode except that the data must be

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MBM29DL32XTE/BE^-80/90/12

programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector

while the devices are in the erase-suspend-program mode will cause DQ²to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I

(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address

while DQ6 can be read from any address within bank being erase-suspended.

To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase

suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend

command can be written after the chip has resumed erasing.

• Extended Command

(1) Fast Mode

MBM29DL32XTE/BE has Fast Mode function. This mode dispenses with the initial two unclock cycles

required in the standard program command sequence by writing Fast Mode command into the command

register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in

standard program command. (Do not write erase command in this mode.) The read operation is also executed

after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command

register. The first cycle must contain the bank address. (Refer to the Figure 28.) The V^CCactive current is

required even CE = VIH during Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to

the Figure 28.)

(3) Extended Sector Group Protection

Inadditiontonormalsectorgroupprotection, theMBM29DL32XTE/BEhasExtendedSectorGroupProtection

as extended function. This function enable to protect sector group by forcing V^IDon RESET pin and write a

command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for

control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector

group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-

up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16,

A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend

to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector

group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group

addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write

a command (40h). Following the command write, a logical “1” at device output DQ0 will produce for protected

sector in the read operation. If the output data is logical “0”, please repeat to write extended sector group

protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer

to the Figures 20 and 29.)

(4) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software interro-

gation handshake which allows specific vendor-specified software algorithms to be used for entire families

of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible

software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. The bank address

should be set when writing this command. Then the device information can be read from the bank, and an

actual data of memory cell be read from the another bank. Following the command write, a read cycle from

specific address retrieves device information. Please note that output data of upper byte (DQ⁸to DQ15) is “0”

in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the

read/reset command sequence into the register. (See Table 12.)

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MBM29DL32XTE/BE^-80/90/12

• Hidden ROM (Hi-ROM) Region

The Hi-ROM feature provides a Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modifi-

cation of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.

The Hi-ROM region is 64K bytes in length and is stored at the same address of the 8KB ×8 sectors. The

MBM29DL32XTE occupies the address of the byte mode 3F0000h to 3FFFFFh (word mode 1F8000h to

1FFFFFh) and the MBM29DL32XBE type occupies the address of the byte mode 000000h to 00FFFFh (word

mode 000000h to 007FFFh). After the system has written the Enter Hi-ROM command sequence, the system

may read the Hi-ROM region by using the addresses normally occupied by the boot sectors. That is, the device

sends all commands that would normally be sent to the boot sectors to the Hi-ROM region. This mode of operation

continues until the system issues the Exit Hi-ROM command sequence, or until power is removed from the

device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors.

• Hidden ROM (Hi-ROM) Entry Command

MBM29DL32XTE/BE has a Hidden ROM area with One Time Protect function. This area is to enter the security

code and to unable the change of the code once set. Program/erase is possible in this area until it is protected.

However, once it is protected, it is impossible to unprotect, so please use this with caution.

Hidden ROM area is 64K Byte and in the same address area of 8KB sector. The address of top boot is 3F0000h

to 3FFFFFh at byte mode (1F8000h to 1FFFFFh at word mode) and the bottom boot is 000000h to 00FFFFh

at byte mode (000000h to 007FFFh at word mode). These areas are normally the boot block area (8KB ×8

sector). Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called

as Hidden ROM mode when the Hidden ROM area appears.

Sector other than the boot block area could be read during Hidden ROM mode. Read/program/erase of the

Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to

exit the Hidden ROM mode. The bank address of the Hidden ROM should be set on the third cycle of this reset

command sequence.

In case of MBM29DL321TE/BE, whose Bank 1 size is 0.5 Mbit, the simultaneous operation cannot execute

multi-function mode between the Hidden ROM area and Bank 2 Region.

• Hidden ROM (Hi-ROM) Program Command

To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden

ROM mode. This command is same as the program command in the past except to write the command during

Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7

data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address

other than the Hidden ROM area is selected to program, the data of the address will be changed.

• Hidden ROM (Hi-ROM) Erase Command

To erase the Hidden ROM area, write the Hidden ROM erase command sequence during Hidden ROM mode.

This command is same as the sector erase command in the past except to write the command during Hidden

ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling,

DQ6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address

other than the Hidden ROM area is selected, the data of the sector will be changed.

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MBM29DL32XTE/BE^-80/90/12

• Hidden ROM (Hi-ROM) Protect Command

There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup com-

mand(60h), set the sector address in the Hidden ROM area and (A⁶, A¹, A⁰) = (0,1,0), and write the sector group

protect command(60h) during the Hidden ROM mode. The same command sequence could be used because

except that it is in the Hidden ROM mode and that it does not apply high voltage to RESET pin, it is the same

as the extension sector group protect in the past. Please refer to “Function Explanation Extended Command

(3) Extended Sector Group Protection” for details of extension sector group protect setting.

The other is to apply high voltage (V^ID) to A9 and OE, set the sector address in the Hidden ROM area and (A⁶,

A¹, A⁰) = (0,1,0), and apply the write pulse during the Hidden ROM mode. To verify the protect circuit, apply high

voltage (V^ID) to A9, specify (A⁶, A¹, A⁰) = (0,1,0) and the sector address in the Hidden ROM area, and read.

When “1” appears to DQ0, the protect setting is completed. “0” will appear to DQ0 if it is not protected. Please

apply write pulse again. The same command sequence could be used for the above method because other than

the Hidden ROM mode, it is the same as the sector group protect in the past. Please refer to “Function Explanation

Sector Group Protection” for details of sector group protect setting

Other sector group will be effected if the address other than the Hidden ROM area is selected for the sector

group address, so please be careful. Once it is protected, protection can not be cancelled, so please pay closest

attention.

• Write Operation Status

Detailed in Table 14 are all the status flags that can determine the status of the bank for the current mode

operation. The read operation from the bank where is not operate Embedded Algorithm returns a data of memory

cell. These bits offer a method for determining whether a Embedded Algorithm is completed properly. The

information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively

read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is

consecutively read. This allows the user to determine which sectors are erasing and which are not.

The status flag is not output from bank (non-busy bank) not executing Embedded Algorithm. For example, there

is bank (busy bank) which is now executing Embedded Algorithm. When the read sequence is [1] <busy bank>,

[2] <non-busy bank>, [3] <busy bank>, the DQ⁶is toggling in the case of [1] and [3]. In case of [2], the data of

memory cell is outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled

in the [1] and [3].

In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is

outputted.

43

MBM29DL32XTE/BE^-80/90/12

Table 14 Hardware Sequence Flags

Status

Embedded Program Algorithm

Embedded Erase Algorithm

DQ⁷

DQ⁶

DQ⁵DQ³

DQ²

1

DQ⁷Toggle

0

1

0

1

Toggle

1

Toggle*

Erase Suspend Read

(Erase Suspended Sector)

0

Toggle

In Progress

Erase

Erase Suspend Read

Suspended

Data Data Data Data Data

(Non-Erase Suspended Sector)

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

DQ⁷Toggle

DQ7 Toggle

0

1*

Embedded Program Algorithm

Embedded Erase Algorithm

1

0

1

0

Toggle

N/A

Exceeded

Time Limits

Erase

Erase Suspend Program

Suspended

DQ⁷Toggle

1

0

N/A

(Non-Erase Suspended Sector)

Mode

*: Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle. Reading from non-erase

suspend sector address will indicate logic “1” at the DQ2 bit.

Notes :1.DQ0 and DQ1 are reserve pins for future use.

2.DQ4 is Fujitsu internal use only.

• DQ⁷

Data Polling

The MBM29DL32XTE/BE devices feature Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the

devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart

for Data Polling (DQ7) is shown in Figure 24.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased

and not a protected sector. Otherwise, the status may not be valid.

If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for

erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.

Once the Embedded Algorithm operation is close to being completed, the MBM29DL32XTE/BE data pins (DQ7)

may change asynchronously while the output enable (OE) is asserted low. This means that the devices are

driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time.

Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device

has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6

may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.

44

MBM29DL32XTE/BE^-80/90/12

TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm

or sector erase time-out. (See Table 14.)

See Figure 9 for the Data Polling timing specifications and diagrams.

• DQ⁶

Toggle Bit I

The MBM29DL32XTE/BE also feature the “Toggle Bit I” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop

toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs

and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ6 to toggle.

The system can use DQ⁶to determine whether a sector is actively erasing or is erase-suspended. When a bank

is actively erasing (that is, the Embedded Erase Algorithm is in progress), DQ6 toggles. When a bank enters the

Erase Suspend mode, DQ6 stops toggling. Successive read cycles during the erase-suspend-program cause

DQ6 to toggle.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

See Figure 10 for the Toggle Bit I timing specifications and diagrams.

• DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the devices under this

condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).

The OE and WE pins will control the output disable functions as described in Tables 3 and 4.

The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the

DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly

used. If this occurs, reset the device with command sequence.

• DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ³will

remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may

be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled

45

MBM29DL32XTE/BE^-80/90/12

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should

check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on

the second status check, the command may not have been accepted.

See Table 14: Hardware Sequence Flags.

• DQ²

Toggle Bit II

This toggle bit II, along with DQ⁶, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows:

For example, DQ²and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also Table 15 and Figure 12.

Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ2 toggles if this bit is read from an erasing sector.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

Table 15 Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Toggle (Note)

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

Erase-Suspend Program

DQ⁷

Toggle

1 (Note)

Note: Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle. Reading from non-

erase suspend sector address will indicate logic “1” at the DQ2 bit.

• RY/BY

Ready/Busy

The MBM29DL32XTE/BE provide a RY/BY open-drain output pin as a way to indicate to the host system that

the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are

busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/

write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase

commands. If the MBM29DL32XTE/BE are placed in an Erase Suspend mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate

a busy condition during the RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY

pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

46

MBM29DL32XTE/BE^-80/90/12

• Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL32XTE/BE devices. When

this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0

to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin

becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer

to Figures 15, 16 and 17 for the timing diagram.

• Data Protection

The MBM29DL32XTE/BE are designed to offer protection against accidental erasure or programming caused

by spurious system level signals that may exist during power transitions. During power up the devices automat-

ically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of

the memory contents only occurs after successful completion of specific multi-bus cycle command sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

• Low V^CCWrite Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than VLKO (Min.). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the

VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to

prevent unintentional writes when VCC is above VLKO (Min.).

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.

• Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

• Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

• Power-Up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

47

MBM29DL32XTE/BE^-80/90/12

■ ABSOLUTE MAXIMUM RATINGS (See WARNING)

Rating

Parameter

Symbol

Conditions

Unit

Min.

Max.

Storage Temperature

Tstg

T^A

–55

+125

°C

Ambient Temperature with

Power Applied

–40

–0.5

+85

VCC+0.5

+4.0

Voltage with Respect to

Ground All pins except A⁹,

OE, RESET (Note 1)

VIN, VOUT

V

Power Supply Voltage

(Note 1)

V^CC

A9, OE, and RESET

(Note 2)

VIN

–0.5

+13.0

+10.5

V

WP/ACC (Note 3)

Notes : 1. Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may

undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is

VCC +0.5V.Duringvoltagetransitions,inputorI/OpinsmayovershoottoVCC +2.0Vforperiodsofupto20ns.

2. Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and

RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input

and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET

pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.

3. Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may

undershoot V^SSto −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is

+10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Ambient Temperature

Power Supply Voltage

Symbol

T^A

Conditions

Unit

Min.

–20

Max.

+70

MBM29DL32XTE/BE-80

MBM29DL32XTE/BE-90/12

MBM29DL32XTE/BE-80

MBM29DL32XTE/BE-90/12

°C

V

–40

+85

+3.0

+2.7

+3.6

V^CC

V

Operating ranges define those limits between which the functionality of the devices are guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

48

MBM29DL32XTE/BE^-80/90/12

■ MAXIMUM OVERSHOOT / UNDERSHOOT

20 ns

+0.6 V

–0.5 V

–2.0 V

20 ns

Figure 1 Maximum Undershoot Waveform

20 ns

V ^CC+2.0 V

V CC +0.5 V

+2.0 V

20 ns

Figure 2 Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

V ^CC+0.5 V

20 ns

*: This waveform is applied for A9, OE, and RESET.

Figure 3 Maximum Overshoot Waveform 2

49

MBM29DL32XTE/BE^-80/90/12

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Min.

Parameter

Symbol

Conditions

Unit

Max.

+1.0

Input Leakage Current

I^LI

VIN = VSS to VCC, VCC = VCC Max.

VOUT = VSS to VCC, VCC = VCC Max.

–1.0

µA

Output Leakage Current

I^LO

VCC = VCC Max.

A⁹, OE, RESET = 12.5 V

A⁹, OE, RESET Inputs Leakage Current

ILIT

—

35

µA

Byte

16

18

7

CE = VIL, OE = VIH,

f = 5 MHz

Word

mA

V^CCActive Current (Note 1)

ICC1

Byte

CE = VIL, OE = VIH,

f = 1 MHz

Word

—

mA

7

V^CCActive Current (Note 2)

V^CCCurrent (Standby)

ICC2

ICC3

CE = VIL, OE = VIH

—

35

mA

VCC = VCC Max., CE = VCC ± 0.3 V,

RESET = VCC ± 0.3 V

5

µA

VCC = VCC Max.,WE/ACC = VCC ±

0.3 V, RESET = VSS ± 0.3 V

V^CCCurrent (Standby, Reset)

ICC4

—

µA

VCC = VCC Max., CE = VSS ± 0.3 V,

RESET = VCC ± 0.3 V

VIN = VCC ± 0.3 V or VSS ± 0.3 V

V^CCCurrent

(Automatic Sleep Mode) (Note 3)

I^CC5

5

µA

Byte

CE = VIL, OE = VIH

Word

—

51

53

51

53

VCC Active Current (Note 5)

(Read-While-Program)

I^CC6

mA

Byte

CE = VIL, OE = VIH

Word

V^CCActive Current (Note 5)

(Read-While-Erase)

I^CC7

V^CCActive Current

(Erase-Suspend-Program)

I^CC8

CE = VIL, OE = VIH

—

35

20

mA

VCC = VCC Max.

WP/ACC = VACC Max.

ACC Accelerated Program Current

IACC

Input Low Level

Input High Level

V^IL

—

–0.5

2.0

0.6

V

VIH

VCC+0.3

Voltage for WP/ACC Sector Protection/

Unprotection and Program Acceleration

V^ACC

V^ID

—

8.5

9.5

V

Voltage for Autoselect and Sector

Protection (A⁹, OE, RESET) (Note 4)

11.5

12.5

Output Low Voltage Level

Output High Voltage Level

Low VCC Lock-Out Voltage

V^OL

IOL = 4.0 mA, VCC = VCC Min.

IOH = –2.0 mA, VCC = VCC Min.

IOH = –100 µA

—

2.4

0.45

—

V

V^OH1

V^OH2

VLKO

VCC–0.4

2.3

—

2.5

Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component.

2. I^CCactive while Embedded Algorithm (program or erase) is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. Applicable for only VCC applying.

5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)

50

MBM29DL32XTE/BE^-80/90/12

2. AC Characteristics

• Read Only Operations Characteristics

Parameter

symbols

80

90

12

Description

Test setup

Unit

(Note) (Note) (Note)

JEDEC Standard

t^AVAV

t^AVQV

tRC

Read Cycle Time

—

Min.

Max.

80

90

120

ns

CE = VIL

OE = VIL

tACC

Address to Output Delay

tELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

OE = VIL Max.

80

30

25

90

35

30

120

50

ns

—

Max.

30

Output Hold Time from Addresses,

CE or OE, Whichever Occurs First

t^AXQX

—

tOH

—

Min.

Max.

0

20

5

0

20

5

0

20

5

ns

µs

ns

t^READY

RESET Pin Low to Read Mode

t^ELFL

tELFH

—

CE or BYTE Switching Low or High

Note: Test Conditions:

Output Load: 1 TTL gate and 30 pF (MBM29DL32XTE/BE-80)

1 TTL gate and 100 pF (MBM29DL32XTE/BE-90/12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output:1.5 V

3.3 V

IN3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diodes = IN3064

or Equivalent

Figure 4 Test Conditions

51

MBM29DL32XTE/BE^-80/90/12

• Write/Erase/Program Operations

Parameter symbols

Description

JEDEC Standard

80

90

12

Unit

t^AVAV

tWC

tAS

Write Cycle Time

Min.

80

0

90

0

120

0

ns

tAVWL

Address Setup Time

Address Setup Time to OE Low During

Toggle Bit Polling

—

t^WLAX

—

t^ASO

tAH

Min.

12

45

0

15

45

0

15

50

0

ns

Address Hold Time

Address Hold Time from CE or OE High

During Toggle Bit Polling

t^AHT

t^DVWH

t^WHDX

tDS

tDH

Data Setup Time

Data Hold Time

Min.

Typ.

Min.

30

0

35

0

50

0

ns

µs

s

Read

0

Output Enable

—

t^OEH

Hold Time

Toggle and Data Polling

10

20

0

10

20

0

10

20

0

—

t^CEPH

t^OEPH

tGHWL

tGHEL

tCS

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CE Setup Time

tGHWL

t^GHEL

t^ELWL

t^WLEL

tWHEH

t^EHWH

t^WLWH

tELEH

tWHWL

t^EHEL

tWHWH1

tWHWH2

—

0

tWS

WE Setup Time

0

tCH

CE Hold Time

0

tWH

WE Hold Time

0

tWP

Write Pulse Width

35

25

8

35

30

8

50

30

8

tCP

CE Pulse Width

tWPH

tCPH

Write Pulse Width High

CE Pulse Width High

tWHWH1

tWHWH2

t^VCS

Byte Programming Operation

Sector Erase Operation (Note 1)

VCC Setup Time

1

50

500

4

50

500

4

50

500

4

µs

ns

µs

—

tVIDR

tVACCR

t^VLHT

tWPP

t^OESP

Rise Time to VID (Note 2)

Voltage Transition Time (Note 2)

Write Pulse Width (Note 2)

OE Setup Time to WE Active (Note 2)

—

100

4

100

4

100

4

—

(Continued)

52

MBM29DL32XTE/BE^-80/90/12

(Continued)

Parameter symbols

JEDEC Standard

Description

80

90

12

Unit

—

t^CSP

t^RB

CE Setup Time to WE Active (Note 2)

Recover Time from RY/BY

Min.

Max.

4

0

4

0

4

µs

ns

µs

0

t^RP

RESET Pulse Width

500

200

30

80

90

80

50

20

500

200

30

90

50

20

500

200

40

t^RH

RESET High Level Period before Read

BYTE Switching Low to Output High-Z

BYTE Switching High to Output Active

Program/Erase Valid to RY/BY Delay

t^FLQZ

t^FHQV

t^BUSY

t^EOE

t^TOW

t^SPD

120

90

Delay Time from Embedded Output Enable Max.

120

50

Erase Time-Out Time

Min.

Erase Suspend Transition Time

Max.

20

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Group Protection operation.

53

MBM29DL32XTE/BE^-80/90/12

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

s

Word Programming Time

Byte Programming Time

—

16

8

360

300

µs

Excludes system-level

overhead

Excludes system-level

overhead

Chip Programming Time

Program/Erase Cycle

—

100

—

s

100,000

cycle

—

■ PIN CAPACITANCE

Parameter

symbol

Parameter description

Test setup

Typ.

Max.

Unit

C^IN

Input Capacitance

VIN = 0

VOUT = 0

VIN = 0

6

8.5

8

7.5

12

pF

C^OUT

C^IN2

Output Capacitance

Control Pin Capacitance

WP/ACC Pin Capacitance

11

C^IN3

21.5

22.5

Note: Test conditions TA = 25°C, f = 1.0 MHz

54

MBM29DL32XTE/BE^-80/90/12

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Changing

from H to L

May

Change

from L to H

Will Be

Changing

from L to H

“H” or “L”

Any Change

Permitted

Changing

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

“Off” State

tRC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tOH

tCE

High-Z

Outputs

Output Valid

Figure 5.1 AC Waveforms for Read Operations

55

MBM29DL32XTE/BE^-80/90/12

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Output Valid

Figure 5.2 AC Waveforms for Hardware Reset/Read Operations

56

MBM29DL32XTE/BE^-80/90/12

Data Polling

3rd Bus Cycle

Address

555h

PA

tWC

tRC

tAS

tAH

CE

tCH

tCS

tCE

OE

tWP

tWPH

tOE

tGHWL

tWHWH1

WE

tOH

tDS

tDH

A0h

PD

DQ7

DOUT

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 6 AC Waveforms for Alternate WE Controlled Program Operations

57

MBM29DL32XTE/BE^-80/90/12

3rd Bus Cycle

Data Polling

Address

WE

PA

555h

tWC

tAS

tAH

tWS

tWH

OE

CE

tGHEL

tCP

tCPH

tWHWH1

tDS

tDH

A0h

PD

DQ7

D^OUT

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 7 AC Waveforms for Alternate CE Controlled Program Operations

58

MBM29DL32XTE/BE^-80/90/12

2AAh

555h

Address

555h

2AAh

SA*

tWC

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

10h/

30h

AAh

55h

80h

AAh

55h

Data

tVCS

VCC

*: SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase.

Note: These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 8 AC Waveforms for Chip/Sector Erase Operations

59

MBM29DL32XTE/BE^-80/90/12

CE

tCH

tOE

tDF

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ0 to DQ6

Valid Data

DQ0 to DQ6

RY/BY

DQ⁰to DQ6 = Output Flag

tBUSY

tEOE

* : DQ7 = Valid Data (The device has completed the Embedded operation).

Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations

60

MBM29DL32XTE/BE^-80/90/12

Address

CE

tAHT tASO

tAHT tAS

tCEPH

WE

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

* : DQ6 stops toggling (The device has completed the Embedded operation).

Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

61

MBM29DL32XTE/BE^-80/90/12

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CE

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDS

tDH

tDF

Valid

Output

Valid

Output

Valid

Status

Intput

Output

(A0h)

(PD)

Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address of Bank 1.

BA2: Address of Bank 2.

Figure 11 Bank-to-bank Read/Write Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ6

DQ2

Toggle

DQ²and DQ6

with OE or CE

Note: DQ2 is read from the erase-suspended sector.

Figure 12 DQ²vs. DQ⁶

62

MBM29DL32XTE/BE^-80/90/12

CE

The rising edge of the last write pulse

WE

Entire programming

or erase operations

RY/BY

tBUSY

Figure 13 RY/BY Timing Diagram during Program/Erase Operations

WE

RESET

tRP

tRB

RY/BY

tREADY

Figure 14 RESET, RY/BY Timing Diagram

63

MBM29DL32XTE/BE^-80/90/12

CE

tCE

BYTE

Data Output

DQ0 to DQ14

Data Output

(DQ0 to DQ14)

(DQ⁰to DQ7)

tELFH

tFHQV

DQ¹⁵

DQ15/A-1

A-1

Figure 15 Timing Diagram for Word Mode Configuration

CE

BYTE

tELFL

DQ0 to DQ14

Data Output

(DQ⁰to DQ7)

Data Output

(DQ⁰to DQ14)

tACC

DQ15/A-1

DQ15

tFLQZ

A-1

Figure 16 Timing Diagram for Byte Mode Configuration

The falling edge of the last write signal

CE or WE

Input

Valid

BYTE

tAS

tAH

Figure 17 BYTE Timing Diagram for Write Operations

64

MBM29DL32XTE/BE^-80/90/12

A²⁰, A19, A18

A17, A16, A15

A14, A13, A12

SGAX

SGAY

A0

A1

A6

VID

3 V

A9

tVLHT

V^ID

3 V

OE

WE

CE

tVLHT

tWPP

tOESP

tCSP

Data

V^CC

01h

tVCS

tOE

SGAX: Sector Group Address for initial sector

SGAY : Sector Group Address for next sector

Note: A-1 is VIL on byte mode.

Figure 18 AC Waveforms for Sector Group Protection

65

MBM29DL32XTE/BE^-80/90/12

VCC

tVIDR

tVCS

tVLHT

VID

3 V

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

Figure 19 Temporary Sector Group Unprotection Timing Diagram

66

MBM29DL32XTE/BE^-80/90/12

VCC

tVCS

tVLHT

RESET

Add

tVIDR

tWC

SGAX

SGAY

A0

A¹

A6

CE

OE

TIME-OUT

tWP

WE

Data

60h

40h

01h

60h

tOE

SGAX: Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min.)

Figure 20 Extended Sector Group Protection Timing Diagram

67

MBM29DL32XTE/BE^-80/90/12

VCC

tVACCR

tVCS

tVLHT

VACC

3 V

WP/ACC

CE

WE

tVLHT

Program or Erase Command Sequence

Acceleration period

RY/BY

Figure 21 Accelerated Program Timing Diagram

68

MBM29DL32XTE/BE^-80/90/12

■ FLOW CHART

EMBEDDED ALGORITHMS

Start

Write Program Command

Sequence

(See below)

Data Polling Device

No

Last Address

?

Increment Address

Yes

Programming Completed

Program Command Sequence* (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

* : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 22 Embedded Program^TMAlgorithm

69

MBM29DL32XTE/BE^-80/90/12

EMBEDDED ALGORITHMS

Start

Write Erase Command

Sequence

(See below)

Data Polling or Toggle Bit

Successfully Completed

Erasure Completed

Individual Sector/Multiple Sector*

Chip Erase Command Sequence*

(Address/Command):

Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address/30h

Additional sector

erase commands

are optional.

Sector Address/30h

* : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 23 Embedded Erase^TMAlgorithm

70

MBM29DL32XTE/BE^-80/90/12

Start

Read

(DQ 0 to DQ 7)

Addr. = VA

VA = Byte address for programming

= Any of the sector addresses within

the sector being erased during

sector erase or multiple sector

erases operation

Yes

DQ 7 = Data?

No

= Any of the sector addresses within

the sector not being protected

during chip erase

No

DQ 5 = 1?

Yes

Read

(DQ 0 to DQ 7)

Addr. = VA

Yes

DQ 7 = Data?

No

Fail

Pass

Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 24 Data Polling Algorithm

71

MBM29DL32XTE/BE^-80/90/12

Start

Read

(DQ ⁰to DQ 7)

Addr. = VA

VA = Bank address being executed

Embedded Algorithm.

No

DQ 6 = Toggle

?

Yes

No

DQ 5 = 1?

Yes

Read

(DQ 0 to DQ 7)

Addr. = VA

No

DQ 6 = Toggle

?

Yes

Fail

Pass

Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as

DQ⁵changing to “1”.

Figure 25 Toggle Bit Algorithm

72

MBM29DL32XTE/BE^-80/90/12

Start

Setup Sector Group Addr.

(A20, A19, A18, A17, A16, A15, A14, A13, A12)

PLSCNT = 1

OE

=

V ID, A 9

V IL, RESET

V IL, A 1

= V ID,

A ⁶

=

CE

= V IH

A 0

=

V IH

Activate WE Pulse

Time out 100 µs

Increment PLSCNT

WE

= V IH, CE = OE = V IL

(A 9 should remain V ID

)

Read from Sector Group

(Addr. = SGA, A 0

A 1 V IH, A6 = V IL)*

=

V IL,

=

No

PLSCNT = 25?

Yes

Data = 01H?

Yes

Remove V ID from A 9

Write Reset Command

Protect Another Sector

Group ?

No

Device Failed

Remove V ID from A 9

Write Reset Command

Sector Group Protection

Completed

* : A-1 is VIL on byte mode.

Figure 26 Sector Group Protection Algorithm

73

MBM29DL32XTE/BE^-80/90/12

Start

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

(Note 2)

Notes: 1. All protected sector groups are unprotected.

2. All previously protected sector groups are protected once again.

Figure 27 Temporary Sector Group Unprotection Algorithm

74

MBM29DL32XTE/BE^-80/90/12

FAST MODE ALGORITHM

Start

555h/AAh

2AAh/55h

Set Fast Mode

555h/20h

XXXh/A0h

Program Address/Program Data

Data Polling Device

No

In Fast Program

Verify Byte?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

(BA)XXXh/90h

XXXh/F0h

Reset Fast Mode

Note: The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 28 Embedded Program^TMAlgorithm for Fast Mode

75

MBM29DL32XTE/BE^-80/90/12

Start

RESET = V^ID

Wait to 4 µs

Device is Operating in

Temporary Sector Group

Unprotection Mode

No

Extended Sector Group

Protection Entry?

Yes

To Setup Sector Group

Protection Write XXXh/60h

PLSCNT = 1

To Sector Group Protection

Write SGA/60h

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Time Out 250 µs

Increment PLSCNT

Setup Next Sector Group

Address

To Verify Sector Group

Protection Write SGA/40h

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Read from Sector Group

Address

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove VID from RESET

Write Reset Command

Protection Other Sector

Group ?

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Group Protection

Completed

Figure 29 Extended Sector Group Protection Algorithm

76

MBM29DL32XTE/BE^-80/90/12

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29DL32X

T

E

80

TN

PACKAGE TYPE

TN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

TR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PBT = Fine pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

MBM29DL32X

32Mega-bit (4M × 8-Bit or 2M × 16-Bit) CMOS Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to

be supported in volume for this device. Consult

the local Fujitsu sales office to confirm availability

of specific valid combinations and to check on

newly released combinations.

MBM29DL321TE/BE

MBM29DL322TE/BE

MBM29DL323TE/BE

MBM29DL324TE/BE

80

90

12

TN

TR

PBT

77

MBM29DL32XTE/BE^-80/90/12

■ PACKAGE DIMENSIONS

* Resin Protrusion. (Each Side: 0.15 (.006)Max)

48-pin plastic TSOP(I)

(FPT-48P-M19)

LEAD No.

1

48

Details of "A" part

INDEX

0.15(.006)

MAX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

20.00±0.20

(.787±.008)

* 12.00±0.20

(.472±.008)

*

18.40±0.20

(.724±.008)

11.50REF

(.453)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting height)

0.10±0.05

(.004±.002)

(STAND OFF)

0.50(.0197)

TYP

0.10(.004)

0.15±0.05

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

Dimensions in mm (inches)

C

2000 FUJITSU LIMITED F48029S-3c-4

* Resin Protrusion. (Each Side: 0.15 (.006)Max)

48-pin plastic TSOP(I)

(FPT-48P-M20)

LEAD No.

1

48

Details of "A" part

INDEX

0.15(.006)

MAX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

0.15±0.05

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

0.10±0.05

(.004±.002)

(STAND OFF)

0.50(.020)

TYP

0.10(.004)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

*

18.40±0.20

(.724±.008)

11.50(.453)REF

* 12.00±0.20(.472±.008)

(Mounting height)

20.00±0.20

(.787±.008)

C

Dimensions in mm (inches)

2000 FUJITSU LIMITED F48030S-3c-4

(Continued)

78

MBM29DL32XTE/BE^-80/90/12

(Continued)

63-pin plastic FBGA

(BGA-63P-M01)

11.00±0.10(.433±.004)

1.05 –⁺0⁰.^.1¹0⁵

(8.80(.346))

(7.20(.283))

.041 –⁺.^.0⁰0⁰4⁶

(Mounting height)

0.38±0.10

(.015±.004)

(Stand off)

(5.60(.220))

0.80(.031)TYP

8

7

6

5

4

3

2

1

(4.00(.157))

(5.60(.220))

7.00±0.10

(.276±.004)

M

L

K

J

H

G

F

E

D

C

B

A

INDEX AREA

INDEX BALL

63-Ø0.45±0.05

(63-Ø0.18±.002)

M

0.08(.003)

0.10(.004)

Dimensions in mm (inches)

C

1999 FUJITSU LIMITED B63001S-1C-1

79

MBM29DL32XTE/BE^-80/90/12

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0101

FUJITSU LIMITED Printed in Japan


型号：	MBM29DL323BE-90TR
厂家：	FUJITSU
描述：	32M (4M x 8/2M x 16) BIT Dual Operation 32M （ 4M ×8 / 2M ×16 ）位双操作内存集成电路光电二极管
文件：	总80页 (文件大小：1459K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29DL323BE-90TR [FUJITSU]

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