MBM29F016A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20844-4E

FLASH MEMORY

CMOS

16M (2M × 8) BIT

MBM29F016A^-70/-90/-12

■ FEATURES

• Single 5.0 V read, write, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Pinout and software compatible with single-power supply Flash

Superior inadvertent write protection

• 48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)

• Minimum 100,000 write/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

Uniform sectors of 64 K bytes each

Any combination of sectors can be erased. Also supports full chip erase.

• Embedded Erase™ Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program™ Algorithms

Automatically programs and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Low V^CCwrite inhibit ≤ 3.2 V

• Hardware RESET pin

Resets internal state machine to the read mode

• Erase Suspend/Resume

Supports reading or programming data to a sector not being erased

• Sector group protection

Hardware method that disables any combination of sector groups from write or erase operation (a sector group

consists of 4 adjacent sectors of 64 K bytes each)

• Temporary sector groups unprotection

Temporary sector unprotection via the RESET pin

Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.

MBM29F016A^-70/-90/-12

■ PACKAGE

48-pin Plastic TSOP(I)

Marking Side

48-pin Plastic TSOP(I)

Marking Side

(FPT-48P-M20)

(FPT-48P-M19)

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MBM29F016A^-70/-90/-12

■ GENERAL DESCRIPTION

The MBM29F016A is a 16 M-bit, 5.0 V-Only Flash memory organized as 2 M bytes of 8 bits each. The 2 M bytes

of data is divided into 32 sectors of 64 K bytes for flexible erase capability. The 8 bit of data will appear on DQ⁰

to DQ⁷. The MBM29F016A is offered in a 48-pin TSOP(I) package. This device is designed to be programmed

in-system with the standard system 5.0 V V^CCsupply. A 12.0 V V^PPis not required for program or erase operations.

The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29F016A offers access times between 70 ns and 120 ns allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls.

The MBM29F016A is command set compatible with JEDEC standard E²PROMs. Commands are written to the

command register using standard microprocessor write timings. Register contents serve as input to an internal

state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase operations. Reading data out of the device is similar to reading

from 12.0 V Flash or EPROM devices.

TheMBM29F016Aisprogrammedbyexecutingtheprogramcommandsequence. ThiswillinvoketheEmbedded

Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished

by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal

algorithm that automatically preprograms the array if it is not already programmed before executing the erase

operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to

be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1

second (if already completely preprogrammed). The MBM29F016A is erased when shipped from the factory.

The MBM29F016A device also features hardware sector group protection. This feature will disable both program

and erase operations in any combination of eight sector groups of memory. A sector group consists of four

adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31.

Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of

time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.

Thedevicefeaturessingle5.0Vpowersupplyoperationforbothreadandprogramfunctions.Internallygenerated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of

DQ⁷, or by the Toggle Bit I feature on DQ⁶or RY/BY output pin. Once the end of a program or erase cycle has

been completed, the device automatically resets to the read mode.

The MBM29F016A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded

Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into

the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs

during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read

mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu's Flash technology combines years of EPROM and E²PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29F016A memory electrically erases all bits within a sector

simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM

programming mechanism of hot electron injection.

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MBM29F016A^-70/-90/-12

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

• Thirty two 64 K byte sectors

• 8 sector groups each of which consists of 4 adjacent sectors in the following pattern; sectors 0-3, 4-7, 8-11,

12-15, 16-19, 20-23, 24-27, and 28-31

• Individual-sector or multiple-sector erase capability

• Sector group protection is user-definable

1FFFFFH

SA31

SA30

SA29

SA28

64 K byte

1EFFFFH

1DFFFFH

1CFFFFH

1BFFFFH

1AFFFFH

19FFFFH

18FFFFH

17FFFFH

16FFFFH

15FFFFH

14FFFFH

13FFFFH

12FFFFH

11FFFFH

10FFFFH

0FFFFFH

0EFFFFH

0DFFFFH

0CFFFFH

0BFFFFH

0AFFFFH

09FFFFH

08FFFFH

07FFFFH

06FFFFH

05FFFFH

04FFFFH

03FFFFH

02FFFFH

01FFFFH

00FFFFH

000000H

Sector

Group 7

32 Sectors Total

SA3

SA2

SA1

SA0

64 K byte

Sector

Group 0

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MBM29F016A^-70/-90/-12

■ PRODUCT LINE UP

Part No.

MBM29F016A

V^CC= 5.0 V ±5%

V^CC= 5.0 V ±10%

-70

—

-90

90

40

—

-12

120

50

Ordering Part No.

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

70

40

■ BLOCK DIAGRAM

DQ⁰to DQ⁷

V^CC

V^SS

RY/BY

Buffer

RY/BY

Erase Voltage

Generator

Input/Output

Buffers

WE

State

Control

RESET

Command

Register

Program Voltage

Generator

Chip Enable

Output Enable

STB

Data Latch

Logic

CE

OE

Y-Gating

Y-Decoder

X-Decoder

STB

Timer for

Program/Erase

Address

Latch

Low V^CCDetector

Cell Matrix

A⁰to A²⁰

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MBM29F016A^-70/-90/-12

■ CONNECTION DIAGRAMS

TSOP(I)

N.C.

A¹⁹

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

N.C.

A²⁰

N.C.

WE

OE

RY/BY

DQ⁷

DQ⁶

DQ⁵

DQ⁴

V^CC

2

(Marking Side)

3

A¹⁸

4

A¹⁷

5

A¹⁶

6

A¹⁵

7

A¹⁴

8

A¹³

9

A¹²

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

CE

MBM29F016A

Standard Pinout

V^CC

N.C.

RESET

A¹¹

V^SS

DQ³

DQ²

DQ¹

DQ⁰

A⁰

A¹⁰

A⁹

A⁸

A⁷

A⁶

A¹

A⁵

A²

A⁴

A³

N.C.

FPT-48P-M19

N.C.

A⁴

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

N.C.

A³

(Marking Side)

A⁵

A²

A⁶

A¹

A⁰

DQ⁰

DQ¹

DQ²

DQ³

V^SS

A⁷

A⁸

A⁹

A¹⁰

A¹¹

RESET

N.C.

V^CC

CE

MBM29F016A

Reverse Pinout

V^SS

V^CC

DQ⁴

DQ⁵

DQ⁶

DQ⁷

RY/BY

OE

WE

N.C.

A²⁰

A¹²

A¹³

A¹⁴

8

A¹⁵

7

A¹⁶

6

A¹⁷

5

A¹⁸

4

A¹⁹

3

N.C.

2

N.C.

1

FPT-48P-M20

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MBM29F016A^-70/-90/-12

■ LOGIC SYMBOL

Table 1 MBM29F016A Pin Configuration

Function

Address Inputs

Data Inputs/Outputs

Chip Enable

A⁰to A²⁰

DQ⁰to DQ⁷

CE

21

A⁰to A ²⁰

8

DQ⁰to DQ⁷

CE

OE

WE

OE

Output Enable

Write Enable

WE

RY/BY

Ready/Busy Output

RESET

RY/BY

Hardware Reset Pin/Sector Protection

Unlock

RESET

N.C.

V^SS

No Internal Connection

Device Ground

V^CC

Device Power Supply

Table 2 MBM29F016A User Bus Operations

Operation

Auto-Select Manufacturer Code (1)

Auto-Select Device Code (1)

Read (3)

CE

L

OE

L

WE

H

A⁰

L

A¹

L

A⁶

L

A⁹

V^ID

A⁹

X

DQ⁰to DQ⁷RESET

Code

D^OUT

H

V^ID

L

H

A⁰

X

L

H

A¹

X

A⁶

X

A⁶

X

L

Standby

H

L

X

HIGH-Z

D^IN

Output Disable

H

V^ID

L

H

X

Write (Program/Erase)

Enable Sector Group Protection (2)

Verify Sector Group Protection (2)

Temporary Sector Group Unprotection

Reset (Hardware)

L

A⁰

X

A¹

X

A⁹

V^ID

X

L

X

L

H

X

L

H

X

Code

X

HIGH-Z

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH,

= Pulse Input. See DC Characteristics for voltage levels.

Notes:1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to

Table 6.

2. Refer to the section on Sector Group Protection.

3. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

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MBM29F016A^-70/-90/-12

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29F016

A

-70

PFTN

PACKAGE TYPE

PFTN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

PFTR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

SPEED OPTION

See Product Selector Guide

A = Device Revision

DEVICE NUMBER/DESCRIPTION

MBM29F016

16 Mega-bit (2 M × 8-Bit) CMOS Flash Memory

5.0 V-only Read, Write, and Erase

64 K Byte (32 Sectors)

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MBM29F016A^-70/-90/-12

■ FUNCTIONAL DESCRIPTION

Read Mode

The MBM29F016A has two control functions which must be satisfied in order to obtain data at the outputs. CE

is the power control and should be used for a device selection. OE is the output control and should be used to

gate data to the output pins if a device is selected.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t^CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the

addresses have been stable for at least t^ACC-t^OEtime).

Standby Mode

There are two ways to implement the standby mode on the MBM29F016A device, one using both the CE and

RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V^CC±0.3 V.

Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with CE and

RESET pins held at V^IH. Under this condition the current is reduced to approximately 1 mA. During Embedded

Algorithm operation, V^CCActive current (I^CC2) is required even CE = V^IH. The device can be read with standard

access time (t^CE) from either of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V^SS±0.3 V (CE

= “H” or “L”). Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with

RESET pin held at V^IL(CE = “H” or “L”). Under this condition the current required is reduced to approximately

1 mA. Once the RESET pin is taken high, the device requires 500 ns of wake up time before outputs are valid

for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Output Disable

With the OE input at a logic high level (V^IH), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the device to be programmed with its corresponding programming algorithm. This mode is functional over the

entire temperature range of the device.

To activate this mode, the programming equipment must force V^ID(11.5 V to 12.5 V) on address pin A⁹. Two

identifier bytes may then be sequenced from the device outputs by toggling address A⁰from V^ILto V^IH. All

addresses are don't cares except A⁰, A¹, and A⁶. (See Table 3.)

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29F016A is erased or programmed in a system without access to high voltage on the A⁹pin. The command

sequence is illustrated in Table 6. (Refer to Autoselect Command section.)

Byte 0 (A⁰= V^IL) represents the manufacturer's code (Fujitsu = 04H) and byte 1 (A⁰= V^IH) represents the device

identifier code for MBM29F016A = ADH. These two bytes are given in the table 3. All identifiers for manufactures

and device will exhibit odd parity with DQ⁷defined as the parity bit. In order to read the proper device codes

when executing the Autoselect, A¹must be V^IL. (See Table 3.)

The Autoselect mode also facilitates the determination of sector group protection in the system. By performing

a read operation at the address location XX02H with the higher order address bits A¹⁸, A¹⁹and A²⁰set to the

desired sector group address, the device will return 01H for a protected sector group and 00H for a non-protected

sector group.

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MBM29F016A^-70/-90/-12

Table 3 MBM29F016A Sector Protection Verify Autoselect Codes

Code

(HEX)

Type

A¹⁸to A²⁰

A⁶

V^IL

A¹

V^IL

V^IH

A⁰

V^IL

V^IH

V^IL

DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Manufacture’s

Code

X

04H

ADH

01H*

0

1

0

1

0

1

0

1

0

1

Device Code

Sector Group

Protection

Sector Group

Addresses

* : Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

Table 4 Sector Address Table

A²⁰

0

1

A¹⁹

0

1

0

1

A¹⁸

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Address Range

SA0

SA1

000000H to 00FFFFH

010000H to 01FFFFH

020000H to 02FFFFH

030000H to 03FFFFH

040000H to 04FFFFH

050000H to 05FFFFH

060000H to 06FFFFH

070000H to 07FFFFH

080000H to 08FFFFH

090000H to 09FFFFH

0A0000H to 0AFFFFH

0B0000H to 0BFFFFH

0C0000H to 0CFFFFH

0D0000H to 0DFFFFH

0E0000H to 0EFFFFH

0F0000H to 0FFFFFH

100000H to 10FFFFH

110000H to 11FFFFH

120000H to 12FFFFH

130000H to 13FFFFH

140000H to 14FFFFH

150000H to 15FFFFH

160000H to 16FFFFH

170000H to 17FFFFH

180000H to 18FFFFH

190000H to 19FFFFH

1A0000H to 1AFFFFH

1B0000H to 1BFFFFH

1C0000H to 1CFFFFH

1D0000H to 1DFFFFH

1E0000H to 1EFFFFH

1F0000H to 1FFFFFH

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

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MBM29F016A^-70/-90/-12

Table 5 Sector Group Addresses

A²⁰

0

A¹⁹

0

A¹⁸

0

Sectors

SGA0

SGA1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SA0 to SA3

0

1

SA4 to SA7

0

1

0

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

0

1

0

1

0

1

0

1

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The

command register is written by bringing WE to V^IL, while CE is at V^ILand OE is at V^IH. Addresses are latched on

the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Group Protection

The MBM29F016A features hardware sector group protection. This feature will disable both program and erase

operations in any combination of eight sector groups of memory. Each sector group consists of four adjacent

sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see

Table 5). The sector group protection feature is enabled using programming equipment at the user's site. The

device is shipped with all sector groups unprotected.

To activate this mode, the programming equipment must force V^IDon address pin A⁹and control pin OE, (suggest

V^ID= 11.5 V), CE = V^IL. The sector addresses (A²⁰, A¹⁹, and A¹⁸) should be set to the sector to be protected.

Tables 4 and 5 define the sector address for each of the thirty two (32) individual sectors, and the sector group

address for each of the eight (8) individual group sectors. Programming of the protection circuitry begins on the

falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held

constant during the WE pulse. See figures 14 and 21 for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A⁹

with CE and OE at V^ILand WE at V^IH. Scanning the sector addresses (A²⁰, A¹⁹, and A¹⁸) while (A⁶, A¹, A⁰) = (0,

1, 0) will produce a logical “1” code at device output DQ⁰for a protected sector. Otherwise the device will produce

00H for unprotected sector. In this mode, the lower order addresses, except for A⁰, A¹, and A⁶are DON’T CARES.

Address locations with A¹= V^ILare reserved for Autoselect manufacturer and device codes.

It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.

Performing a read operation at the address location XX02H, where the higher order addresses (A²⁰, A¹⁹, and

A¹⁸) are the desired sector group address will produce a logical “1” at DQ⁰for a protected sector group. See

Table 3 for Autoselect codes.

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MBM29F016A^-70/-90/-12

Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the MBM29F016A device

in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high

voltage (12 V). During this mode, formerly protected sector groups can be programmed or erased by selecting

the sector group addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sector

groups will be protected again. Refer to Figures 14 and 21.

Table 6 MBM29F016A Command Definitions

Fourth Bus

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Sixth Bus

Read/Write

Cycle

Bus

Write

Cycles

Req'd

Write Cycle Write Cycle

Command

Sequence

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset*

Reset/Read*

Autoselect

1

3

4

6

XXXH F0H

—

RA

—

RD

—

555H AAH 2AAH 55H 555H F0H

555H AAH 2AAH 55H 555H 90H

555H AAH 2AAH 55H 555H A0H

Byte Program

Chip Erase

PA

PD

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Sector Erase

Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”), Data (B0H)

Sector Erase Resume Erase can be resumed after suspend with Addr (“H” or “L”), Data (30H)

Notes:1. Address bits A¹¹to A²⁰= X = “H” or “L” for all address commands except or Program Address (PA) and

Sector Address (SA).

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE pulse.

SA = Address of the sector to be erased. The combination of A²⁰, A¹⁹, A¹⁸, A¹⁷, and A¹⁶will uniquely select

any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

5. Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.

6. The system should generate the following address pattens: 555H or 2AAH to addresses A⁰to A¹⁰.

*: Either of the two reset commands will reset the device.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the device to the

read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both

Read/Reset commands are functionally equivalent, resetting the device to the read mode.

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MBM29F016A^-70/-90/-12

Read/Reset Command

The read or reset operation is initiated by writing the read/reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the

command register contents are altered.

The device will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the device resides in the target system. PROM

programmers typically access the signature codes by raising A⁹to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desirable system design practice.

The device contains an autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the autoselect command sequence into the command register.

Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read

cycle from address XX01H returns the device code ADH. (See Table 3).

All manufacturer and device codes will exhibit odd parity with the DQ⁷defined as the parity bit.

Sector state (protection or unprotection) will be informed by address XX02H.

Scanning the sector group addresses (A¹⁸, A¹⁹, A²⁰) while (A⁶, A¹, A⁰) = (0, 1, 0) will produce a logical “1” at

device output DQ⁰for a protected sector group.

To terminate the operation, it is necessary to write the read/reset command sequence into the register and also

to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.

Byte Programming

The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two

“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are

latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of

CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.

Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide

further controls or timings. The device will automatically provide adequate internally generated program pulses

and verify the programmed cell margin.

This automatic programming operation is completed when the data on DQ⁷is equivalent to data written to this

bitatwhichtimethedevicereturnstothereadmodeandaddressesarenolongerlatched. (SeeTable7, Hardware

Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system

at this particular instance of time. Data Polling must be performed at the memory location which is being

programmed.

Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the

programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 16 illustrates the Embedded Programming^TMAlgorithm using typical command strings and bus operations.

13

MBM29F016A^-70/-90/-12

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the device will automatically program and verify the entire memory for an all zero

data pattern prior to electrical erase. The system is not required to provide any controls or timings during these

operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates

when the data on DQ⁷is “1” (see Write Operation Status section) at which time the device returns to read the

mode.

Figure 17 illustrates the Embedded Erase™ Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of WE, while the command

(Data = 30H) is latched on the rising edge of WE. After time-out of 50 µs from the rising edge of the last sector

erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 6. This sequence

is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this

condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs

from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling

edge of the WE occurs within the 50 µs time-out window the timer is reset. (Monitor DQ³to determine if the

sector erase timer window is still open, see section DQ³, Sector Erase Timer.) Any command other than Sector

Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous

command string. Resetting the device once execution has begun will corrupt the data in that sector. In that case,

restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for

DQ³, Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with

any number of sectors (0 to 31).

Sector erase does not require the user to program the device prior to erase. The device automatically programs

all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the

remaining unselected sectors are not affected. The system is not required to provide any controls or timings

during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the data on DQ⁷is “1” (see Write Operation Status section)

at which time the device returns to the read mode. Data polling must be performed at an address within any of

the sectors being erased.

Figure 17 illustrates the Embedded Erase™ Algorithm using typical command strings and bus operations.

Erase Suspend

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

fromorprogramstoasectornotbeingerased. ThiscommandisapplicableONLYduringaSectorEraseoperation

which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written

during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command during

14

MBM29F016A^-70/-90/-12

the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase

operation.

AnyothercommandwrittenduringtheEraseSuspendmodewillbeignoredexcepttheEraseResumecommand.

Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when

writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of 15 µs to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY

output pin and the DQ⁷bit will be at logic “1”, and DQ⁶will stop toggling. The user must use the address of the

erasing sector for reading DQ⁶and DQ⁷to determine if the erase operation has been suspended. Further writes

of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ².)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate

command sequence for Byte Program. This program mode is known as the erase-suspend-program mode.

Again, programming in this mode is the same as programming in the regular Byte Program mode except that

the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-

suspended sector while the device is in the erase-suspend-program mode will cause DQ²to toggle. The end of

the erase-suspended program operation is detected by the RY/BY output pin, Data polling of DQ⁷, or by the

Toggle Bit I (DQ⁶) which is the same as the regular Byte Program operation. Note that DQ⁷must be read from

the Byte Program address while DQ⁶can be read from any address.

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

15

MBM29F016A^-70/-90/-12

Write Operation Status

Table 7 Hardware Sequence Flags

Status

DQ⁷

0

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

1

Toggle

Erase Suspend Read

(Erase Suspended Sector)

Toggle

(Note 1)

1

0

Data

0

Data

0

In Progress

Erase

Erase Suspend Read

(Non-Erase Suspended Sector)

Suspended

Mode

Data

DQ⁷

Data

Erase Suspend Program

(Non-Erase Suspended Sector)

Toggle

(Note 2)

1

(Note 3)

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ⁷

0

Toggle

1

0

1

N/A

Exceeded

Time Limits

Erase Suspend Program

Suspended

Mode

DQ⁷

Toggle

1

0

N/A

(Non-Erase Suspended Sector)

Notes:1. Performing successive read operations from the erase-suspended sector will cause DQ²to toggle.

2. Performing successive read operations from any address will cause DQ⁶to toggle.

3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic

“1” at the DQ²bit. However, successive reads from the erase-suspended sector will cause DQ²to toggle.

DQ⁷

Data Polling

The MBM29F016A device features Data Polling as a method to indicate to the host that the embedded algorithms

are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will

produce the complement of the data last written to DQ⁷. Upon completion of the Embedded Program Algorithm,

an attempt to read the device will produce the true data last written to DQ⁷. During the Embedded Erase™

Algorithm, an attempt to read the device will produce a “0” at the DQ⁷output. Upon completion of the Embedded

Erase Algorithm an attempt to read the device will produce a “1” at the DQ⁷output. The flowchart for Data Polling

(DQ⁷) is shown in Figure 18.

Data polling will also flag the entry into Erase Suspend. DQ⁷will switch “0” to “1” at the start of the Erase Suspend

mode. Please note that the address of an erasing sector must be applied in order to observe DQ⁷in the Erase

Suspend Mode.

During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside

of the suspend mode.

For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.

For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling

must be performed at sector address within any of the sectors being erased and not a sector that is within a

protected sector group. Otherwise, the status may not be valid.

Just prior to the completion of Embedded Algorithm operation DQ⁷may change asynchronously while the output

enable (OE) is asserted low. This means that the device is driving status information on DQ⁷at one instant of

time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ⁷

16

MBM29F016A^-70/-90/-12

output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations

and DQ⁷has a valid data, the data outputs on DQ⁰to DQ⁶may be still invalid. The valid data on DQ⁰to DQ⁷will

be read on the successive read attempts.

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase

Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See Table 7.)

See Figure 9 for the Data Polling timing specifications and diagrams.

DQ⁶

Toggle Bit I

The MBM29F016A also features the “Toggle Bit I” as a method to indicate to the host system that the embedded

algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the device at any address will result in DQ⁶toggling between one and zero. Once the Embedded Program or

Erase Algorithm cycle is completed, DQ⁶will stop toggling and valid data will be read on the next successive

attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four

write pulse sequence. For chip erase, and sector erase the Toggle Bit I is valid after the rising edge of the sixth

WE pulse in the six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of

the sector erase WE pulse. The Toggle Bit I is active during the sector erase time out.

In programming, if the sector being written to is protected, the Toggle Bit I will toggle for about 2 µs and then

stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for

the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about

100 µs and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ⁶to toggle. In addition, an Erase Suspend/Resume command will

cause DQ⁶to toggle.

See Figure 10 for the Toggle Bit I timing specifications and diagrams.

DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ⁵will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling DQ⁷, DQ⁶is the only operating function of the device under

this condition. The CE circuit will partially power down the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output disable functions as described in Table 2.

TheDQ⁵failureconditionmayalsoappearifausertriestoprograma1toalocationthatispreviouslyprogrammed

to 0. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the

system never reads a valid data on DQ⁷bit and DQ⁶never stops toggling. Once the device has exceeded timing

limits, the DQ⁵bit will indicate a “1.” Please note that this is not a device failure condition since the device was

incorrectly used. If this occurs, reset the device.

DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ³will

remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ³may

be used to determine if the sector erase timer window is still open. If DQ³is high (“1”) the internally controlled

17

MBM29F016A^-70/-90/-12

erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will

be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ³is low (“0”),

the device will accept additional sector erase commands. To insure the command has been accepted, the system

software should check the status of DQ³prior to and following each subsequent sector erase command. If DQ³

were high on the second status check, the command may not have been accepted.

Refer to Table 7: Hardware Sequence Flags.

DQ²

Toggle Bit II

This toggle bit II, along with DQ⁶, can be used to determine whether the device is in the Embedded Erase™

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase™ Algorithm. If

the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ²to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ²bit.

Mode

DQ⁷

0

DQ⁶

DQ²

1

Program

Erase

toggles

Erase Suspend Read (1)

(Erase-Suspended Sector)

1

toggles

1 (2)

Erase Suspend Program

DQ⁷(2)

toggles

Notes:1. These status flags apply when outputs are read from a sector that has been erase-suspended.

2. These status flags apply when outputs are read from the byte address of the non-erase suspended sector.

DQ⁶is different from DQ²in that DQ⁶toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ⁷, is summarized

as follows:

For example, DQ²and DQ⁶can be used together to determine the erase-suspend-read mode (DQ²toggles while

DQ⁶does not). See also Table 7 and Figure 15.

Furthermore, DQ²can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ²toggles if this bit is read from the erasing sector.

RY/BY

Ready/Busy

The MBM29F016A provides a RY/BY open-drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with

either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase

operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands

with the exception of the Erase Suspend command. If the MBM29F016A is placed in an Erase Suspend mode,

the RY/BY output will be high, by means of connecting with a pull-up resistor to V^CC.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during RESET pulse. Refer to Figure 11 for a detailed timing diagram. The RY/BY pin is pulled

high in standby mode.

18

MBM29F016A^-70/-90/-12

Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to V^CC.

RESET

Hardware Reset

The MBM29F016A device may be reset by driving the RESET pin to V^IL. The RESET pin must be kept low (V^IL)

for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to

the read mode 20 µs after the RESET pin is driven low. If a hardware reset occurs during a program operation,

the data at that particular location will be indeterminate.

When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be

accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the

RESET pin is taken high, the device requires t^RHof wake up time until outputs are valid for read access.

The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded

Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s

microprocessor to read the boot-up firmware from the Flash memory.

Data Protection

TheMBM29F016Aisdesignedtoofferprotectionagainstaccidentalerasureorprogrammingcausedbyspurious

system level signals that may exist during power transitions. During power up the device automatically resets

the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory

contents only occurs after successful completions of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting from V^CCpower-up

and power-down transitions or system noise.

Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for V^CCless

than 3.2 V (typically 3.7 V). If V^CC< V^LKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until

the V^CClevel is greater than V^LKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when V^CCis above 3.2 V.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = V^IL, CE = V^IHor WE = V^IH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = V^ILand OE = V^IHwill not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

19

MBM29F016A^-70/-90/-12

■ ABSOLUTE MAXIMUM RATINGS

Storage Temperature ........................................................................................–55°C to +125°C

Ambient Temperature with Power Applied ........................................................–40°C to +85°C

Voltage with Respect to Ground All pins except A⁹, OE, and RESET (Note 1).–2.0 V to +7.0 V

V^CC(Note 1) ......................................................................................................–2.0 V to +7.0 V

A⁹, OE, and RESET (Note 2) ............................................................................–2.0 V to +13.5 V

Notes:1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may negative

overshoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is V^CC

+0.5 V. During voltage transitions, outputs may positive overshoot to V^CC+2.0 V for periods up to 20 ns.

2. Minimum DC input voltage on A⁹, OE, and RESET pins are –0.5 V. During voltage transitions, A⁹, OE,

and RESET pins may negative overshoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC input

voltage on A⁹, OE, and RESET are +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. Voltage

difference between input voltage and power supply. (V^IN– V^CC) do not exceed 9 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Ambient Temperature (T^A)................................................................................ –40°C to +85°C

V^CCSupply Voltages

MBM29F016A-70............................................................................................ +4.75 V to +5.25 V

MBM29F016A-90/-12...................................................................................... +4.50 V to +5.50 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

20

MBM29F016A^-70/-90/-12

■ MAXIMUM OVERSHOOT

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 1 Maximum Negative Overshoot Waveform

20 ns

V^CC+2.0 V

V^CC+0.5 V

+2.0 V

20 ns

Figure 2 Maximum Positive Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

V^CC+0.5 V

20 ns

* : This waveform is applied for A⁹, OE, and RESET.

Figure 3 Maximum Positive Overshoot Waveform 2

21

MBM29F016A^-70/-90/-12

■ DC CHARACTERISTICS

Parameter

Parameter Description

Symbol

Test Conditions

Min.

—

Max.

±1.0

Unit

µA

I^LI

Input Leakage Current

Output Leakage Current

V^IN= V^SSto V^CC, V^CC= V^CCMax.

V^OUT= V^SSto V^CC,

V^CC= V^CCMax.

I^LO

—

µA

A⁹, OE, RESET Inputs Leakage V^CC= V^CCMax.

I^LIT

—

50

µA

Current

A⁹, OE, RESET = 12.5 V

I^CC1

I^CC2

V^CCActive Current (Note 1)

V^CCActive Current (Note 2)

CE = V^IL, OE = V^IH

—

40

45

mA

V^CC= V^CCMax., CE = V^IH

RESET = V^IH

—

1

5

1

5

mA

µA

I^CC3

V^CCCurrent (Standby)

V^CC= V^CCMax., CE = V^CC±0.3 V,

RESET = V^CC±0.3 V

V^CC= V^CCMax.

RESET = V^IL

mA

µA

I^CC4

V^CCCurrent (Standby, Reset)

V^CC= V^CCMax.

RESET = V^SS±0.3 V

V^IL

V^IH

Input Low Level

Input High Level

—

–0.5

2.0

0.8

V

V^CC+0.5

Voltage for Autoselect and Sector

Protection (A⁹, OE, RESET)

(Note 3, 4)

V^ID

—

11.5

12.5

V

V^OL

Output Low Voltage Level

Output High Voltage Level

Low V^CCLock-Out Voltage

I^OL= 12.0 mA, V^CC= V^CCMin.

I^OH= –2.5 mA, V^CC= V^CCMin.

I^OH= –100 µA

—

2.4

0.45

—

V

V^OH1

V^OH2

V^LKO

V^CC–0.4

3.2

—

4.2

Notes:1. The I^CCcurrent listed includes both the DC operating current and the frequency dependent component

(at 6 MHz). The frequency component typically is 2 mA/MHz, with OE at V^IH.

2. I^CCactive while Embedded Algorithm (program or erase) is in progress.

3. Applicable to sector protection function.

4. (V^ID– V^CC) do not exceed 9 V.

22

MBM29F016A^-70/-90/-12

■ AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

-70

-90

-12

Symbols

Description

Test Setup

Unit

(Note1) (Note2) (Note2)

JEDEC Standard

t^AVAV

t^AVQV

t^RC

Read Cycle Time

—

Min.

Max.

70

90

120

ns

CE = V^IL

OE = V^IL

t^ACC

Address to Output Delay

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CE

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output HIGH-Z

Output Enable to Output HIGH-Z

OE = V^ILMax.

70

40

20

90

40

20

120

50

ns

—

Max.

30

Output Hold Time From Addresses,

CE or OE, whichever occurs first

t^AXQX

t^OH

—

Min.

0

ns

—

t^READY

RESET Pin Low to Read Mode

Max.

20

µs

Note: 1. Test Conditions:

Output Load: 1 TTL gate and 30 pF

Note: 2. Test Conditions:

Output Load: 1 TTL gate and 100 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.45 V to 2.4 V

Timing measurement reference level

Input: 0.8 V and 2.0 V

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

Output: 0.8 V and 2.0 V

5.0 V

IN3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

C^L

Diodes = IN3064

or Equivalent

Note: 1. C^L= 30 pF including jig capacitance

2. C^L= 100 pF including jig capacitance

Figure 4 Test Conditions

23

MBM29F016A^-70/-90/-12

• Write/Erase/Program Operations

Parameter Symbols

MBM29F016A

-90

Description

Unit

JEDEC Standard

-70

70

0

-12

120

0

t^AVAV

t^AVWL

t^WLAX

t^DVWH

t^WHDX

—

t^WC

t^AS

Write Cycle Time

Min.

Typ.

90

0

ns

µs

Address Setup Time

Address Hold Time

Data Setup Time

t^AH

t^DS

t^DH

t^OES

45

30

0

45

0

50

0

Data Hold Time

Output Enable Setup Time

0

Output

Enable Hold

Time

Read

0

—

t^OEH

Toggle Bit I and Data Polling

10

0

10

0

10

0

t^GHWL

t^GHEL

t^ELWL

t^GHWL

t^GHEL

t^CS

Read Recover Time Before Write

CE Setup Time

0

t^WLEL

t^WHEH

t^EHWH

t^WLWH

t^ELEH

t^WS

WE Setup Time

0

t^CH

CE Hold Time

0

t^WH

WE Hold Time

0

t^WP

Write Pulse Width

35

20

8

45

20

8

50

20

8

t^CP

Write Pulse Width

t^WHWL

t^EHEL

t^WPH

t^CPH

t^WHWH1

Write Pulse Width High

Byte Programming Operation

t^WHWH1

Typ.

1

8

1

8

1

8

sec

t^WHWH2

Sector Erase Operation (Note 1)

Max.

—

t^VCS

t^VLHT

t^WPP

t^OESP

t^CSP

t^RB

V^CCSetup Time

Min.

50

4

50

4

50

4

µs

ns

Voltage Transition Time (Note 2)

Write Pulse Width (Note 2)

OE Setup Time to WE Active (Note 2)

CE Setup Time to WE Active (Note 2)

Recover Time from RY/BY

100

4

100

4

100

4

0

(Continued)

24

MBM29F016A^-70/-90/-12

(Continued)

Parameter Symbols

JEDEC Standard

MBM29F016A

Unit

Description

-70

500

50

-90

500

50

-12

500

50

—

t^RP

RESET Pulse Width

Min.

Max.

ns

t^RH

RESET Hold Time Before Read

t^BUSY

t^EOE

Program/Erase Valid to RY/BY Delay

70

90

120

50

40

Notes:1. This does not include the preprogramming time.

2. This timing is for Sector Protection operation.

25

MBM29F016A^-70/-90/-12

■ SWITCHING WAVEFORMS

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Changing

from H to L

May

Change

from L to H

Will Be

Changing

from L to H

“H” or “L”

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

“Off” State

t^RC

Addresses Stable

Addresses

t^ACC

CE

OE

t^DF

t^OE

t^OEH

WE

t^CE

t^OH

High-Z

Outputs

Output Valid

Figure 5 AC Waveforms for Read Operations

26

MBM29F016A^-70/-90/-12

3rd Bus Cycle

555H

Data Polling

Addresses

PA

t^AH

t^WC

t^RC

t^AS

t^CH

CE

t^GHWL

OE

t^WP

t^WHWH1

WE

t^WPH

t^CS

t^DF

t^DH

t^OE

D^OUT

A0H

PD

DQ⁷

Data

t^DS

t^OH

5.0 V

t^CE

Notes:1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

Figure 6 AC Waveforms for Alternate WE Controlled Program Operations

27

MBM29F016A^-70/-90/-12

3rd Bus Cycle

Data Polling

Addresses

555H

t^WC

PA

t^AH

PA

t^AS

t^WH

WE

t^GHEL

OE

CE

t^CP

t^WHWH1

t^CPH

t^WS

t^DH

DQ⁷

D^OUT

A0H

PD

Data

t^DS

5.0 V

Notes:1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

Figure 7 AC Waveforms for Alternate CE Controlled Program Operations

28

MBM29F016A^-70/-90/-12

t^AH

Addresses

555H

2AAH

t^AS

555H

2AAH

SA*

CE

t^GHWL

OE

t^WP

WE

t^CS

t^WPH

t^DH

Data

V^CC

AAH

55H

80H

AAH

55H

10H/30H

t^DS

t^VCS

* : SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.

Figure 8 AC Waveforms Chip/Sector Erase Operations

29

MBM29F016A^-70/-90/-12

t^CH

CE

t^DF

t^OE

OE

t^OEH

WE

t^CE

*

High-Z

DQ⁷=

Valid Data

DQ⁷

Data

DQ⁷

t^EOE

t^{WHWH1 or 2}

DQ⁰to DQ⁷

Valid Data

DQ⁰to DQ⁶

DQ⁰to DQ⁶= Output Flug

* : DQ⁷= Valid Data (The device has completed the Embedded operation.)

Figure 9 AC Waveforms for Data Polling During Embedded Algorithm Operations

CE

t^OEH

WE

OE

t^OES

*

DQ6 =

Stop Toggling

DQ⁰to DQ⁷

Valid

DQ⁶= Toggle

Data

DQ⁶= Toggle

DQ⁶

t^OE

* : DQ⁶stops toggling (The device has completed the Embedded operation.)

Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

30

MBM29F016A^-70/-90/-12

CE

The rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

t^BUSY

Figure 11 RY/BY Timing Diagram During Program/Erase Operations

WE

RESET

t^RP

t^READY

t^RB

RY/BY

Figure 12 RESET, RY/BY Timing Diagram

31

MBM29F016A^-70/-90/-12

A 20, A 19, A 18

SGAX

SGAY

A 0

A 1

A 6

12V

5V

A 9

tVLHT

12V

5V

OE

tVLHT

tWPP

WE

tOESP

tCSP

CE

Data

01H

tOE

tVCS

VCC

SGAX = Sector Group Address for initial sector

SGAY = Sector Group Address for next sector

Figure 13 AC Waveforms for Sector Group Protection Timing Diagram

32

MBM29F016A^-70/-90/-12

VCC

tVIDR

tVCS

tVLHT

VID

5 V

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

RY/BY

Unprotection period

Figure 14 Temporary Sector Group Unprotection Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ⁶

DQ²

Toggle

DQ²and DQ⁶

with OE

Note: DQ²is read from the erase-suspended sector.

Figure 15 DQ²vs. DQ⁶

33

MBM29F016A^-70/-90/-12

EMBEDDED ALGORITHMS

Start

Write Program Command

Sequence

(See Below)

Data Polling Device

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555H/AAH

2AAH/55H

555H/A0H

Program Address/Program Data

Figure 16 Embedded Program^TMAlgorithm

34

MBM29F016A^-70/-90/-12

Start

Write Erase Command

Sequece

(See Below)

Data Polling or Toggle Bit I

Successfully Completed

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

Sector Address/30H

Additional sector

erase commands

are optional.

Sector Address/30H

Note: To insure the command has been accepted, the system software should check the status

of DQ³prior to and following each subsequent sector erase command. If DQ³were high on

the second status check, the command may not have been accepted.

Figure 17 Embedded Erase™ Algorithm

35

MBM29F016A^-70/-90/-12

Start

Read Byte

(DQ⁰to DQ⁷)

Addr. = VA

VA = Address for programming

= Any of the sector addresses

within the sector being erased

during sector erase or multiple

erases operation.

Yes

DQ⁷= Data?

No

= Any of the sector group

addresses within the sector not

being protected during sector

erase or multiple sector erases

operation.

No

DQ⁵= 1?

Yes

Read Byte

(DQ⁰to DQ⁷)

Addr. = VA

Yes

DQ⁷= Data?

No

Fail

Pass

Note: DQ⁷is rechecked even if DQ⁵= “1” because DQ⁷may change simultaneously with DQ⁵.

Figure 18 Data Polling Algorithm

36

MBM29F016A^-70/-90/-12

Start

Read Byte

(DQ⁰to DQ⁷)

Addr. = “H” or “L”

No

DQ⁶= Toggle

?

Yes

No

DQ⁵= 1

?

Yes

Read Byte

(DQ⁰to DQ⁷)

Addr. = “H” or “L”

No

DQ⁶= Toggle

?

Yes

Fail

Pass

Note: DQ⁶is rechecked even if DQ⁵= “1” because DQ⁶may stop toggling at the same time as DQ⁵

changing to “1”.

Figure 19 Toggle Bit I Algorithm

37

MBM29F016A^-70/-90/-12

Start

Setup Sector Group Addr.

(A²⁰, A¹⁹, A¹⁸)

PLSCNT = 1

OE = V^ID, A⁹= V^ID,

CE = V^IL, RESET = V^IH

Increment PLSCNT

Activate WE Pulse

Time out 100 µs

WE = V^IH,CE = OE = V^IL,

(A⁹should remain V^ID)

Read from Sector Group

Addr. (A²⁰, A¹⁹, A¹⁸)

A¹= 1, A⁰= A⁶= 0

No

PLSCNT = 25?

Yes

No

Data = 01H?

Yes

Remove V^IDfrom A⁹

Write Reset Command

Protect Another Sector

Group?

No

Remove V^IDfrom A⁹

Device Failed

Write Reset Command

Sector Protection

Completed

Figure 20 Sector Group Protection Algorithm

38

MBM29F016A^-70/-90/-12

Start

RESET = V^ID

(Note 1)

Perform Erase or

Program Operations

RESET = V^IH

Temporary Sector Group

Unprotection Completed

(Note 2)

Notes:1. All Protected sector groups unprotected.

2. All previously protected sector groups are protected once again.

Figure 21 Temporary Sector Group Unprotection Algorithm

39

MBM29F016A^-70/-90/-12

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes 00H programming

prior to erasure

Sector Erase Time

—

1

8

sec

Excludes system-level

overhead

Byte Programming Time

—

8

150

µs

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

16.8

—

40

—

sec

100,000

cycles

■ TSOP(I) PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

C^IN

Input Capacitance

V^IN= 0

V^OUT= 0

V^IN= 0

8

9

10

pF

C^OUT

Output Capacitance

Control Pin Capacitance

C^IN2

Note: Test conditions T^A= 25°C, f = 1.0 MHz

40

MBM29F016A^-70/-90/-12

■ PACKAGE DIMENSIONS

*: Resin Protrusion. (Each Side:0.15(.006)MAX)

48-pin plastic TSOP(I)

(FPT-48P-M19)

LEAD No.

1

48

Details of "A" part

0.15(.006)

MAX

INDEX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

20.00±0.20

* 12.00±0.20

(.787±.008)

(.472±.008)

*18.40±0.20

(.724±.008)

11.50REF

(.460)

1.10−⁺0⁰.^.105⁰

.043−⁺.^.0⁰⁰02⁴

(Mounting height)

0.50(.0197)

TYP

0.05(0.02)MIN

STAND OFF

0.10(.004)

0.15±0.05

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

Dimensions in mm(inches)

C

1996 FUJITSU LIMITED F48029S-2C-2

(Continued)

41

MBM29F016A^-70/-90/-12

(Continued)

*: Resin Protrusion. (Each Side:0.15(.006)MAX)

48-pin plastic TSOP(I)

(FPT-48P-M20)

LEAD No.

1

48

Details of "A" part

INDEX

0.15(.006)

MAX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

0.15±0.10

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

0.50(.0197)

TYP

0.05(0.02)MIN

STAND OFF

0.10(.004)

1.10−⁺0⁰.^.105⁰

*18.40±0.20

(.724±.008)

11.50(.460)REF

* 12.00±0.20(.472±.008)

.043−⁺.^.0⁰⁰02⁴

(Mounting height)

20.00±0.20

(.787±.008)

C

Dimensions in mm(inches)

1996 FUJITSU LIMITED F48030S-2C-2

42

MBM29F016A^-70/-90/-12

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inhereut chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9903

FUJITSU LIMITED Printed in Japan

43


型号：	MBM29F016A
厂家：	FUJITSU
描述：	16M (2M X 8) BIT 16M （ 2M ×8 ）位
文件：	总43页 (文件大小：441K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29F016A [FUJITSU]

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