MBM29LV652UE-90_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20886-1E

FLASH MEMORY

CMOS

64M (4M × 16) BIT

MBM29LV652UE ^-90/12

■ GENERAL DESCRIPTION

The MBM29LV652UE is a 64M-bit, 3.0 V-only Flash memory organized as 4M words of 16 bits each. The device

is designed to MBM29LV652UEbe programmed in system with the standard system 3.0 V VCC supply. 12.0 V VPP

and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard

EPROM programmers.

To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable

(OE) controls.

The MBM29LV652UE is entirely command set compatible with JEDEC single-power-supply Flash standard.

Commands are written to the command register using standard microprocessor write timings. Register contents

serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also

internally latch addresses and data needed for the programming and erase operations.

Typically, each sector can be programmed and verified in about 0.5 seconds.

■ PRODUCT LINE UP

Part No.

V^CC= 3.3 V

MBM29LV652UE

+0.3 V

–0.3 V

90

—

Ordering Part No.

+0.6 V

–0.3 V

12

V^CC= 3.0 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

90

35

120

50

■ PACKAGES

63-pin plastic FBGA

BGA-63P-M02

MBM29LV652UE-90/12

(Continued)

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29LV652UE is erased when shipped from the factory.

Internally generated and regulated voltages are provided for the program and erase operations. A low VCC

detector automatically inhibits write operations on the loss of power. The end of program or erase is detected

by Data Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

The devices electrically erase all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The words

are programmed one word at a time using the EPROM programming mechanism of hot electron injection.

■ FEATURES

• 0.23 µm Process Technology

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standards

Uses same software commands with single-power supply Flash

• Address don’t care during the command sequence

• Industry-standard pinouts

63-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance

90 ns maximum access time

• Flexible sector architecture

One hundred twenty-eight 32K word sectors

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Hidden ROM (Hi-ROM) region

128 word of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• Ready/Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• ACC input pin

At V^ACC, increases program performance

• Embedded Erase^TM* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded program^TM* Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector group protection

Hardware method disables any combination of sector groups from program or erase operations

• Sector Group Protection Set function by Extended sector protect command

• Fast Programming Function by Extended Command

(Continued)

2

MBM29LV652UE-90/12

(Continued)

• Temporary sector group unprotection

Temporary sector group unprotection via the RESET pin

This feature allows code changes in previously locked sectors

• In accordance with CFI (Common Flash Memory Interface)

*: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

3

MBM29LV652UE-90/12

■ PIN ASSIGNMENT

FBGA

(TOP VIEW)

Marking Side

A8

B8

L8

M8

N.C.

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

N.C.

A13

A12

A14

A15

A16

Vccq

DQ15

Vss

N.C.

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

WE

RESET

A21

A19

DQ5

DQ12

Vcc

DQ4

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY

ACC

A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

CE

J2

K2

L2

M2

N.C.

OE

Vss

N.C.

A1

B1

L1

M1

N.C.

BGA-63P-M02

*:Peripheral balls on each corner are shorted together via the substrate but not connected to the die.

4

MBM29LV652UE-90/12

■ PIN DESCRIPTION

Table1 MBM29LV652UE Pin Configuration

A⁰to A21

DQ⁰to DQ15

CE

Function

Address Inputs

Data Inputs/Outputs

Chip Enable

OE

Output Enable

WE

Write Enable

RY/BY

Ready/Busy Output

Hardware Reset Pin/Temporary Sector

Group Unprotection

RESET

ACC

V^CCq

N.C.

V^SS

Program Acceleration

Output Buffer Power

No Internal Connection

Device Ground

V^CC

Device Power Supply

5

MBM29LV652UE-90/12

■ BLOCK DIAGRAM

DQ0 to DQ15

RY/BY

Buffers

VCC

VSS

Input/Output

Buffers

Erase Voltage

Generator

VCCq

WE

State

Control

RESET

Command

Register

ACC

Program Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data Latch

CE

OE

Y-Gating

Y-Decoder

X-Decoder

STB

Timer for

Program/Erase

Address

Latch

Cell Matrix

A0 to A21

6

MBM29LV652UE-90/12

■ LOGIC SYMBOL

22

A0 to A21

16

DQ 0 to DQ 15

RY/BY

CE

OE

WE

RESET

ACC

VCCq

7

MBM29LV652UE-90/12

■ DEVICE BUS OPERATION

Table2 MBM29LV652UE User Bus Operations

Operation

CE OE WE

A⁰

A¹

A⁶

A⁹

DQ⁰to DQ¹⁵RESET

Auto-Select Manufacture Code *¹

Auto-Select Device Code *¹

Read *³

L

H

L

X

L

H

X

H

L

H

A0

X

A⁰

L

VID

A9

X

Code

DOUT

H

VID

L

A1

X

A6

X

A6

L

Standby

X

H

VID

L

HIGH-Z

DIN

Output Disable

X

Write (Program/Erase)

A1

H

X

A9

VID

X

Enable Sector Group Protection *²*⁴

Verify Sector Group Protection *²*⁴

Temporary Sector Group Unprotection *⁵

Reset (Hardware)/Standby

X

H

X

L

Code

X

HIGH-Z

Legend: L = V^IL, H = VIH, X = VIL or VIH.

= Pulse input. See DC Characteristics for voltage levels.

*1: Manufacturer and device codes may also be accessed via a command register write sequence. See Table 3.

*2: Refer to the section on Sector Group Protection.

*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4: V^CC= 3.3 V ±10%

*5: It is also used for the extended sector group protection.

8

MBM29LV652UE-90/12

Table3 MBM29LV652UE Command Definitions

Fourth Bus

Read/Write

Cycle

Bus

Write

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Sixth Bus

Command

Sequence

Write Cycle Write Cycle

Cycles

Req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset

Autoselect

1

3

4

6

1

XXXh F0h

—

RA

—

RD

—

XXXh AAh XXXh 55h XXXh F0h

XXXh AAh XXXh 55h XXXh 90h

XXXh AAh XXXh 55h XXXh A0h

Program

PA

PD

Chip Erase

Sector Erase

Erase Suspend

Erase Resume

XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h XXXh 10h

XXXh AAh XXXh 55h XXXh 80h XXXh AAh XXXh 55h

SA

—

30h

—

XXXh B0h

XXXh 30h

—

Set to

Fast Mode

3

2

XXXh AAh XXXh 55h XXXh 20h

—

Fast

Program *1

XXXh A0h

PA

PD

—

Reset from Fast

Mode *1

XXXh 90h XXXh F0h

Extended Sector

Group Protection

*2

4

XXXh 60h SPA 60h SPA 40h SPA SD

—

Query *3

1

3

XXh 98h

—

Hi-ROM

Entry

XXXh AAh XXXh 55h XXXh 88h

XXXh AAh XXXh 55h XXXh A0h

Hi-ROM

Program *4

4

PA

PD

—

Hi-ROM

Exit *4

XXXh AAh XXXh 55h XXXh 90h XXXh 00h

9

MBM29LV652UE-90/12

*1: This command is valid while Fast Mode.

*2: This command is valid while RESET = VID.

*3: The valid addresses are A6 to A0.

*4: This command is valid while Hi-ROM mode.

Notes: 1. Address bits = X = “H” or “L” for all address commands except or Program Address (PA) and Sector

Address (SA).

2. Bus operations are defined in Table 2.

3. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of

the write pulse.

SA = Address of the sector to be erased. The combination of A²¹, A20, A19, A18, A17, A16 and A15 will

uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A⁶, A1, A0) = (0, 1, 0).

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

10

MBM29LV652UE-90/12

Table 4 .1 MBM29LV652UE Sector Group Protection Verify Autoselect Codes

Type

Manufacturer’s Code

A¹⁷to A²¹

A⁶

V^IL

A¹

VIL

A⁰

VIL

VIH

Code (HEX)

04h

X

Device Code MBM29LV652UE

Sector Group Protection

22D7h

Sector Group

Addresses

V^IL

VIH

VIL

01h *

*: Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

Table 4 .2 Expanded Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Manufacturer’s Code

Device

Code

04h

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MBM29LV652UE 22D7h

Code

Sector Group Protection

01h

11

MBM29LV652UE-90/12

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

Table 5 Sector Address Tables

Sector

Address

A²¹

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

Sector Size

Address Range

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32K words

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

(Continued)

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

12

MBM29LV652UE-90/12

(Continued)

Sector

Address

A²¹

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

Sector Size

Address Range

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32K words

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1FFFFFh

(Continued)

13

MBM29LV652UE-90/12

(Continued)

Sector

A²¹

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

Sector Size

Address Range

Address

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32K words

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

250000h to 257FFFh

258000h to 25FFFFh

260000h to 267FFFh

268000h to 26FFFFh

270000h to 277FFFh

278000h to 27FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

2A0000h to 2A7FFFh

2A8000h to 2AFFFFh

2B0000h to 2B7FFFh

2B8000h to 2BFFFFh

2C0000h to 2C7FFFh

2C8000h to 2CFFFFh

2D0000h to 2D7FFFh

2D8000h to 2DFFFFh

2E0000h to 2E7FFFh

2E8000h to 2EFFFFh

2F0000h to 2F7FFFh

2F8000h to 2FFFFFh

(Continued)

14

MBM29LV652UE-90/12

(Continued)

Sector

Address

A²¹

A²⁰

A¹⁹

A¹⁸

A¹⁷

A¹⁶

A¹⁵

Sector Size

Address Range

SA96

SA97

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32K words

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

350000h to 357FFFh

358000h to 35FFFFh

360000h to 367FFFh

368000h to 36FFFFh

370000h to 377FFFh

378000h to 37FFFFh

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

3A0000h to 3A7FFFh

3A8000h to 3AFFFFh

3B0000h to 3B7FFFh

3B8000h to 3BFFFFh

3C0000h to 3C7FFFh

3C8000h to 3CFFFFh

3D0000h to 3D7FFFh

3D8000h to 3DFFFFh

3E0000h to 3E7FFFh

3E8000h to 3EFFFFh

3F0000h to 3F7FFFh

3F8000h to 3FFFFFh

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

15

MBM29LV652UE-90/12

Table 6 Sector Group Address

Sector Group

Address

A²¹

A²⁰

A¹⁹

A¹⁸

A¹⁷

Sector Group Size

Sectors

SGA0

SGA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128K words

SA0 to SA3

SA4 to SA7

SGA2

SA8 to SA11

SGA3

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

SA32 to SA35

SA36 to SA39

SA40 to SA43

SA44 to SA47

SA48 to SA51

SA52 to SA55

SA56 to SA59

SA60 to SA63

SA64 to SA67

SA68 to SA71

SA72 to SA75

SA76 to SA79

SA80 to SA83

SA84 to SA87

SA88 to SA91

SA92 to SA95

SA96 to SA99

SA100 to SA103

SA104 to SA107

SA108 to SA111

SA112 to SA115

SA116 to SA119

SA120 to SA123

SA124 to SA127

SGA4

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

16

MBM29LV652UE-90/12

Table 7 Common Flash Memory Interface Code

DQ⁰to DQ¹⁵

6

DQ⁰to DQ¹⁵

Description

A⁰to A⁶

Description

A⁰to A

Query-unique ASCII string

“QRY”

10h

11h

12h

0051h

0052h

0059h

Erase Block Region 2

Information

31h

32h

33h

34h

0000h

Primary OEM Command Set

2h: AMD/FJ standard type

13h

14h

0002h

0000h

Query-unique ASCII string

“PRI”

40h

41h

42h

0050h

0052h

0049h

Address for Primary

Extended Table

15h

16h

0040h

0000h

Major version number, ASCII

Minor version number, ASCII

43h

44h

45h

0031h

0001h

Alternate OEM Command

Set (00h = not applicable)

17h

18h

0000h

Address for Alternate OEM

Extended Table

19h

1Ah

0000h

Address Sensitive Unlock

0h = Required

1h = Not Required

V^CCMin. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Bh

0027h

Erase Suspend

46h

47h

48h

0002h

0004h

0001h

0h = Not Supported

1h = To Read Only

2h = To Read & Write

V^CCMax. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Ch

0036h

VPP Min. voltage

V^PPMax. voltage

1Dh

1Eh

1Fh

0000h

0004h

Sector Protection

0h = Not Supported

X = Number of sectors in per

group

Typical timeout per single

byte/word write 2^Nµs

Typical timeout for Min. size

20h

21h

22h

23h

24h

25h

26h

27h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

0017h

Sector Temporary

Unprotection

00h = Not Supported

01h = Supported

buffer write 2^Nµs

Typical timeout per individual

block erase 2^Nms

Sector Protection Algorithm

49h

4Ah

0004h

0000h

Typical timeout for full chip

erase 2^Nms

Number of Sector for Bank 2

00h = Not Supported

Max. timeout for byte/word

write 2^Ntimes typical

Burst Mode Type

00h = Not Supported

4Bh

4Ch

4Dh

0000h

00B5h

Max. timeout for buffer write

2^Ntimes typical

Page Mode Type

00h = Not Supported

Max. timeout per individual

block erase 2^Ntimes typical

ACC (Acceleration) Supply

Minimum

00h = Not Supported,

D7-4: volt, D3-0: 100 mvolt

Max. timeout for full chip

erase 2^Ntimes typical

Device Size = 2^Nbyte

ACC (Acceleration) Supply

Maximum

00h = Not Supported,

D7-4: volt, D3-0: 100 mvolt

4Eh

00C5h

Flash Device Interface

description

28h

29h

0001h

0000h

Max. number of byte in

multi-byte write = 2^N

2Ah

2Bh

0000h

Number of Erase Block

Regions within device

2Ch

0001h

Erase Block Region 1

Information

2Dh

2Eh

2Fh

30h

007Fh

0000h

0001h

17

MBM29LV652UE-90/12

■ FUNCTIONAL DESCRIPTION

Read Mode

The MBM29LV652UE has two control functions which must be satisfied in order to obtain data at the outputs.

CE is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after

power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”.

Standby Mode

There are two ways to implement the standby mode on the MBM29LV652UE devices, one using both the CE

and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V.

Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC

active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either

of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ±0.3 V (CE

= “H” or “L”). Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is taken

high, the device requires tRH of wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

MBM29LV652UE data. This mode can be used effectively with an application requesting low power consumption

such as handy terminals.

To activate this mode, MBM29LV652UE automatically switch themselves to low power mode when

MBM29LV652UE addresses remain stable during access fine of 150 ns. It is not necessary to control CE, WE,

and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,

the mode is canceled automatically and MBM29LV652UE read-out the data for changed addresses.

Output Disable

With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the devices to be programmed with its corresponding programming algorithm. The Autoselect command may

also be used to check the status of write-protected sectors (see Tables 4.1 and 4.2). This mode is functional

over the entire temperature range of the devices.

To activate this mode, the programming equipment must force V^ID(11.5 V to 12.5 V) on address pin A9. Two

identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All

addresses are DON’T CARES except A0, A1, and A6. (See Table 2.)

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29LV652UE is erased or programmed in a system without access to high voltage on the A9 pin. The

command sequence is illustrated in Table 3. (Refer to Autoselect Command section.)

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MBM29LV652UE-90/12

Word 0 (A⁰= VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device

identifier code (MBM29LV652UE = 22D7h).These two words are given in the tables 4.1 to 4.2. All identifiers for

manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper

device codes when executing the autoselect, A1 must be VIL. (See Tables 4.1 to 4.2.)

In order to determine which sectors are write protected, A1 must be at VIH while running through the sector

addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 = 1).

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The

command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on

the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Group Protection

The MBM29LV652UE features hardware sector group protection. This feature will disable both program and

erase operations in any combination of thirty two sector groups of memory. (See Table 6). The sector group

protection feature is enabled using programming equipment at the user’s site. The device is shipped with all

sector groups unprotected.

To activate this mode, the programming equipment must force V^IDon address pin A9 and control pin OE, (suggest

VID = 11.5 V), CE = VIL and A0 = A6 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, and A17) should

be set to the sector to be protected. Table 5 defines the sector address for each of the one hundred twenty-eight

(128) individual sectors, and tables 2 defines the sector group address for each of the thirty-two (32) individual

group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is

terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse.

See figures 14 and 22 for sector group protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, and A17) while

(A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the

device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and

A6 areDON’TCARES. AddresslocationswithA1 =VIL arereservedforAutoselectmanufactureranddevicecodes.

It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.

Performing a read operation at the address location XX02h, where the higher order addresses (A²¹, A20, A19, A18,

and A17) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See

Tables 4.1 and 4.2 for Autoselect codes.

Temporary Sector Group Unprotection

ThisfeatureallowstemporaryunprotectionofpreviouslyprotectedsectorgroupsoftheMBM29LV652UEdevices

in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high

voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting

the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector

groups will be protected again. Refer to Figures 15 and 23.

This temporary sector group unprotect mode is disabled whenever the chip is in the Hidden ROM (Hi-ROM)

mode. This area can not be programmed within this mode. Moreover once this area is programmed, it is always

protected no matter in which mode.

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MBM29LV652UE-90/12

RESET

Hardware Reset Pin

The MBM29LV652UE devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse

requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset

to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

devices require an additional “tRH” before it will allow read access. When the RESET pin is low, the devices will

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware

reset occurs during a program or erase operation, the data at that particular location will be corrupted.

Accelerated Program Operation

MBM29LV652UE offers accelerated program operation which enables the programming in high speed. If the

system asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required

for program operation will reduce to about 50%. This function is primarily intended to allow high speed program,

so caution is needed as the sector group will temporarily be unprotected.

The system would use a fast program command sequence when programming during acceleration mode. Set

command to fast mode and reset command from fast mode is not necessary. When the device enters the

acceleration mode, the device automatically set to fast mode. Therefore, the present sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the ACC pin returns the device to normal operation. Do not remove VACC from the ACC pin

while programming. (See Figure 17)

20

MBM29LV652UE-90/12

■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect data values or writing them in the improper sequence will reset the devices to the read mode.

Table 3 defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume

(30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset

commands are functionally equivalent, resetting the device to the read mode. Please note that commands are

always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the

command register contents are altered.

The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the devices reside in the target system. PROM

programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write

cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be

read from the address, and an actual data of memory cell can be read from the another address.

Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read

cycle from address XX01h returns the device code (MBM29LV652UE = 22D7h).

AllmanufactureranddevicecodeswillexhibitoddparitywithDQ⁷definedastheparitybit. Sectorstate(protection

or unprotection) will be informed by address XX02h. Scanning the sector group addresses (A21, A20, A19, A18,

and A17) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group.

The programming verification should be performed by verify sector group protection on the protected sector.

(See Table 2.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and

also to write the Autoselect command during the operation, execute it after writing Read/Reset command

sequence.

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MBM29LV652UE-90/12

Word Programming

The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are

two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses

are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge

of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins

programming.UponexecutingtheEmbeddedProgramAlgorithmcommandsequence,thesystemisnotrequired

to provide further controls or timings. The device will automatically provide adequate internally generated

program pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ7 (Data Polling), and DQ6 (Toggle

Bit) or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being

programmed.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bitatwhichtimethedevicesreturntothereadmodeandaddressesarenolongerlatched. (SeeTable8, Hardware

Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by the system

at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being

programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the

programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1” Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0” Only

erase operations can convert “0”s to “1”s.

Figure 18 illustrates the Embedded Program^TMAlgorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), and DQ6 (Toggle Bit).

The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence

and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device

returns to read the mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

Figure 19 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first.

Aftertime-outof“tTOW”fromtherisingedgeofthelastsectorerasecommand, thesectoreraseoperationwillbegin.

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MBM29LV652UE-90/12

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 3. This sequence

is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than “t^TOW” otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this

condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “tTOW”

from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase

command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out

window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section

DQ³, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period

will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once

execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow

them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the

sector erase buffer may be done in any sequence and with any number of sectors (0 to 127).

Sector erase does not require the user to program the devices prior to erase. The devices automatically program

all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), and DQ6 (Toggle Bit)or

RY/BY.

The sector erase begins after the “t^TOW” time out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status

section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at

an address within any of the sectors being erased.

Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector

Erase

Figure 19 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if

written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command

(B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension

of the erase operation.

Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “Don’t Care” when

writting the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of “t^SPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/

BY output pin will be at Hi-z and the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use

the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been

suspended. Further writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ2.)

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MBM29LV652UE-90/12

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate

command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,

programming in this mode is the same as programming in the regular Program mode except that the data must

beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector

while the devices are in the erase-suspend-program mode will cause DQ²to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I

(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address

while DQ6 can be read from any address.

To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

Extended Command

(1) Fast Mode

MBM29LV652UE has Fast Mode function. This mode dispenses with the initial two unclock cycles required in

the standard program command sequence by writing Fast Mode command into the command register. In this

mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program

command. (Do not write erase command in this mode.) The read operation is also executed after exiting this

mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer

to the Figure 24.) The V^CCactive current is required even CE = VIH during Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to the

Figure 24.)

(3) Extended Sector Group Protection

In addition to normal sector group protection, the MBM29LV652UE has Extended Sector Group Protection as

extended function. This function enable to protect sector group by forcing V^IDon RESET pin and write a command

sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The

only RESET pin requires VID for sector group protection in this mode. The extended sector group protection

requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)

into the command register. Then, the sector group addresses pins (A21, A20, A19, A18, and A17) and (A6, A1, A0) =

(0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins),

and write extended sector group protection command (60h). A sector group is typically protected in 250 µs. To

verify programming of the protection circuitry, the sector group addresses pins (A21, A20, A19, A18, and A17) and

(A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical “1” at

device output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please

repeattowriteextendedsectorgroupprotectioncommand(60h)again. Toterminatetheoperation, itisnecessary

to set RESET pin to VIH. (Refer to the Figures 16 and 25.)

(4) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation

handshake which allows specific vendor-specified software algorithms to be used for entire families of devices.

This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software

support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. Following the command

write, a read cycle from specific address retrieves device information. Please note that output data of upper byte

(DQ⁸to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary

to write the read/reset command sequence into the register. (See Table 7.)

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MBM29LV652UE-90/12

Hidden ROM (Hi-ROM) Region

The Hi-ROM feature provides a Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the Hi-ROM region is programmed, any further

modification of that region is impossible. This ensures the security of the ESN once the product is shipped to

the field.

The Hi-ROM region is 128 words in length. After the system has written the Enter Hi-ROM command sequence,

it may read the Hidden ROM region by using device addresses A0 to A6 (A7 to A14 are “00”, A15 to A21 are don’t

care). That is, the device sends only program command that would normally be sent to the address to the Hi-

ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence,

or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to

sending commands to the address.

Hidden ROM (Hi-ROM) Entry Command

MBM29LV652UE has a Hidden ROM area with One Time Protect function. This area is to enter the security

code and to unable the change of the code once set. Program is possible in this area until it is protected. However,

once it is protected, it is impossible to unprotect, so please use this with caution.

Hidden ROM area is 128words in length. Write the Hidden ROM entry command sequence to enter the Hidden

ROM area. It is called as Hidden ROM mode when the Hidden ROM area appears. After the system has written

the Enter Hi-ROM command sequence, it may read the Hidden ROM region by using device addresses A⁰to A6

(A⁷to A14 are “00”, A15 to A21 are don’t care).

Read/program of the Hidden ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset

command sequence to exit the Hidden ROM mode.

Hidden ROM (Hi-ROM) Program Command

To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden

ROM mode. This command is same as the program command in the past except to write the command during

Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ⁷

data poling, DQ6 toggle bit and RY/BY pin.

Hidden ROM (Hi-ROM) Protect Command

There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup

command(60h), set the sector address to select (A⁶, A¹, A⁰) = (0,1,0) and Hidden ROM area and write the sector

group protect command(60h) during the Hidden ROM mode. Same command sequence could be used because

other then the Hidden ROM mode and that is does not apply high voltage to RESET pin, it is same as the

extension sector group protect in the past. Please refer "Function Explanation Extended Command (3)

Extentended Sector Group Protection" for details of extention sector group protect setting.

The other is to apply high voltage (V^ID) to A9 and OE, specify the sector address to select (A⁶, A¹, A⁰) = (0,1,0)

and Hidden ROM area, and apply the write pulse during the Hidden ROM mode. To verify the protect circuit,

apply high voltage (V^ID) to A9, specify (A⁶, A¹, A⁰) = (0,1,0) and the sector address to select the Hidden ROM

area, and read. When "1" appears to DQ0, the protect setting is completed. "0" will appear to DQ0 if it is not

protected. Please apply write pulse agian. Same command sequence could be used for the above method

because other then the Hidden ROM mode, it is same as the sector group protect in the past. Please refer

"Function Explanation Secor Group Protection" for details of sector group protect setting

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MBM29LV652UE-90/12

Once it is protected, protection can not be cancelled, so please pay closest attention.

Write Operation Status

Detailed in Table 8 are all the status flags that can be used to check the status of the device for current mode

operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information

on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then

the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively

read. This allows the user to determine which sectors are erasing and which are not.

Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is,

one available for read) is provided, then stored data can be read from the device. If the address of an erasing

sector (that is, one unavailable for read) is applied, the device will output its status bits.

Table 8 Hardware Sequence Flags

Status

DQ⁷

0

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

1

Toggle*

Erase Suspend Read

(Erase Suspended Sector)

1

0

Data

0

Data

0

Toggle

Data

1*

In Progress

Erase

Erase Suspend Read

Suspended

Data

DQ⁷

Data

(Non-Erase Suspended Sector)

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

Toggle

Embedded Program Algorithm

Embedded Erase Algorithm

DQ⁷

0

Toggle

1

0

1

N/A

Exceeded

Time Limits

Erase

Erase Suspend Program

Suspended

DQ⁷

Toggle

1

0

N/A

(Non-Erase Suspended Sector)

Mode

*: Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle. Reading from non-erase

suspend sector address will indicate logic “1” at the DQ2 bit.

Notes: 1. DQ0 and DQ1 are reserve pins for future use.

2. DQ4 is Fujitsu internal use only.

DQ⁷

Data Polling

The MBM29LV652UE devices feature Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the

devices will produce the complement of the data last written to DQ⁷. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart

for Data Polling (DQ7) is shown in Figure 20.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

26

MBM29LV652UE-90/12

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased

and not a protected sector. Otherwise, the status may not be valid.

Once the Embedded Algorithm operation is close to being completed, the MBM29LV652UE data pins (DQ7) may

change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving

status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time.

Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device

has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6

may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts.

TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm,EmbeddedEraseAlgorithm

or sector erase time-out. (See Table 8.)

See Figure 9 for the Data Polling timing specifications and diagram.

DQ⁶

Toggle Bit I

The MBM29LV652UE also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, theToggleBitIisvalidaftertherisingedgeofthefourthwritepulseinthefourwritepulsesequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop

toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs

and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ6 to toggle.

See Figure 10 for the Toggle Bit I timing specifications and diagram.

DQ⁵

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the devices under this

condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).

The OE and WE pins will control the output disable functions as described in Table 2.

The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ⁷bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the

DQ5 bit will indicate a “1”. Please note that this is not a device failure condition since the devices were incorrectly

used. If this occurs, reset the device with command sequence.

27

MBM29LV652UE-90/12

DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will

remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may

be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should

check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on

the second status check, the command may not have been accepted.

See Table 8 : Hardware Sequence Flags.

DQ²

Toggle Bit II

This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.

DQ⁶is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows:

For example, DQ²and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also Table 9 and Figure 11.

Furthermore, DQ²can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ2 toggles if this bit is read from an erasing sector.

Table 9 Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Toggle *

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

1 *

Erase-Suspend Program

DQ⁷

Toggle

*: Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle. Reading from non-erase

suspend sector address will indicate logic “1” at the DQ2 bit.

28

MBM29LV652UE-90/12

RY/BY

Ready/Busy

The MBM29LV652UE provide a RY/BY open-drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy

with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or

erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase

commands. If the MBM29LV652UE is placed in an Erase Suspend mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate

a busy condition during the RESET pulse. Refer to Figures 12 and 13 for a detailed timing diagram. The RY/BY

pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

Data Protection

The MBM29LV652UE is designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the devices automatically

reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the

memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The

devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and

power-down transitions or system noise.

Low V^CCWrite Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

thanVLKO (min).IfVCC <VLKO,thecommandregisterisdisabledandallinternalprogram/erasecircuitsaredisabled.

Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level

is greater than V^LKO. It is the users responsibility to ensure that the control pins are logically correct to prevent

unintentional writes when VCC is above VLKO (Min.).

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must

be a logical zero while OE is a logical one.

Power-up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to read mode on power-up.

29

MBM29LV652UE-90/12

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min.

–55

–40

Max.

+125

+85°

Storage Temperature

Tstg

T^A

°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground All Pins Except

A⁹, OE, ACC and RESET (Note 1)

VIN, VOUT

–0.5

VCC +0.5

+4.0

V

Power Supply Voltage

(Note 1)

V^CC

A9, OE, ACC, and RESET

(Note 2)

VIN

–0.5

–0.2

+13.0

+7.0

V

Power Supply Voltage

V^CCq

Notes: 1. Minimum DC voltage on input or l/O pins is −0.5 V. During voltage transitions, input or I/O pins may

undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC

+0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A9, OE, ACC and RESET pins is −0.5 V. During voltage transitions, A9,

OE, ACC, and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference

between input and supply voltage (V^IN−VCC) does not exceed 9.0 V. Maximum DC input voltage on A9,

OE, ACC, and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

T^A

Unit

Min.

–40

Max.

+85

Ambient Temperature

(-90/-12)

(-90)

°C

V

+3.0

+2.7

+3.6

Power Supply Voltage

(V^CC)

VCC

(-12)

V

Power Supply Voltage

(VCCq)

(-90/-12)

VCCq

+2.7

+3.6

V

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

30

MBM29LV652UE-90/12

■ MAXIMUM OVERSHOOT/UNDERSHOOT

20 ns

+0.6 V

–0.5 V

–2.0 V

20 ns

Figure 1 Maximum Undershoot Waveform

20 ns

VCC +2.0 V

V^CC+0.5 V

+2.0 V

20 ns

Figure 2 Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

VCC +0.5 V

20 ns

Note: This waveform is applied for A⁹, OE, ACC, and RESET.

Figure 3 Maximum Overshoot Waveform 2

31

MBM29LV652UE-90/12

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Parameter

Parameter Description

Symbol

Test Conditions

Min.

–1.0

—

Max.

+1.0

35

Unit

µA

V^IN= VSS to VCC, VCC = VCC Max.,

V^CCq = VCCq Max.

I^LI

I^LO

I^LIT

I^ACC

Input Leakage Current

Output Leakage Current

V^OUT= VSS to VCC, VCC = VCC Max.,

V^CCq = VCCq Max.

µA

A9, OE, RESET Inputs Leakage

Current

VCC = VCC Max.,

A⁹, OE, RESET = 12.5 V

µA

V^CC= VCC Max.,

ACC = V^ACCMax.

ACC Accelerated Program Current

—

20

mA

CE = VIL, OE = VIH, VCC = VCC Max.,

V^CCq = VCCq Max., f = 5 MHz

—

16

I^CC1

VCC Active Current (Note 1)

CE = VIL, OE = VIH, VCC = VCC Max.,

V^CCq = VCCq Max., f = 1 MHz

—

7

CE = VIL, OE = VIH, VCC = VCC Max.,

V^CCq = VCCq Max.

I^CC2

I^CC3

I^CC4

VCC Active Current (Note 2)

VCC Current (Standby)

—

40

V^CC= VCC Max., VCCq = VCCq Max.,

CE = VCC ±0.3 V,

RESET = VCC ±0.3 V

—

5

µA

V^CC= VCC Max., VCCq = VCCq Max.,

RESET = VSS ±0.3 V

VCC Current (Standby, RESET)

VCC = VCC Max., VCCq = VCCq Max.,

CE = VSS ±0.3 V,

RESET = VCC ±0.3 V,

VCC Current

(Automatic Sleep Mode) (Note 3)

I^CC5

—

5

µA

VIN = VCC ±0.3 V or VSS ±0.3 V

V^IL

VIH

Input Low Level

—

–0.5

2.0

0.6

VCC + 0.5

12.5

V

Input High Level

VACC

Voltage for Program Acceleration

11.5

Voltage for Autoselect, Sector

Protection (A⁹, OE, RESET) (Note 4)

V^ID

V^OL

—

11.5

—

12.5

0.45

—

V

I^OL= 4.0 mA, VCC = VCC Min.,

V^CCq = VCCq Min.

Output Low Voltage Level

I^OH= –2.0 mA, VCC = VCC Min.,

V^CCq = VCCq Min.

V^OH1

2.4

Output High Voltage Level

Low VCC Lock-Out Voltage

V^CCq –

0.4

IOH = –100 µA, VCC Min.,

VCCq = VCCq Min.

V^OH2

—

V

VLKO

—

2.3

2.5

Notes: 1. The lCC current listed includes both the DC operating current and the frequency dependent component.

2. l^CCactive while Embedded Erase or Embedded Program is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. Applicable for only VCC applying.

32

MBM29LV652UE-90/12

2. AC Characteristics

• Read Only Operations Characteristics

Parameter

Symbols

90

(Note)

12

(Note)

Description

Test Setup

Unit

JEDEC Standard

t^AVAV

t^AVQV

tRC

Read Cycle Time

—

Min.

Max.

90

120

ns

CE = VIL

OE = VIL

tACC

Address to Output Delay

tELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output HIGH-Z

Output Enable to Output HIGH-Z

OE = VIL Max.

90

35

30

120

50

ns

—

Max.

30

Output Hold Time From Address,

CE or OE, Whichever Occurs First

t^AXQX

—

tOH

—

Min.

0

ns

t^READY

RESET Pin Low to Read Mode

Max.

20

µs

Note: Test Conditions:

Output Load: 1 TTL gate and 30 pF (MBM29LV652UE-90)

1 TTL gate and 100 pF (MBM29LV652UE-12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output: 1.5 V

3.3 V

IN3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diodes = IN3064

or Equivalent

Figure 4 Test Conditions

33

MBM29LV652UE-90/12

• Write (Erase/Program) Operations

Parameter Symbols

JEDEC Standard

Description

90

12

Unit

t^AVAV

t^AVWL

t^WLAX

t^DVWH

t^WHDX

—

tWC

tAS

Write Cycle Time

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min.

Typ.

Min.

90

0

120

0

ns

µs

s

tAH

45

35

0

50

0

tDS

tDH

t^OES

Output Enable Setup Time

0

Read

0

—

t^OEH

Output Enable Hold Time

Toggle and Data Polling

10

0

10

0

t^GHWL

t^GHEL

t^ELWL

t^WLEL

t^WHEH

t^EHWH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

t^WHWH1

t^WHWH2

—

tGHWL

tGHEL

tCS

Read Recover Time Before Write

CE Setup Time

0

tWS

WE Setup Time

0

tCH

CE Hold Time

0

tWH

WE Hold Time

0

tWP

Write Pulse Width

35

30

16

1

50

30

16

1

tCP

CE Pulse Width

tWPH

tCPH

tWHWH1

tWHWH2

t^VCS

t^VIDR

t^VACCR

t^VLHT

t^WPP

t^OESP

t^CSP

t^RB

Write Pulse Width High

CE Pulse Width High

Word Programming Operation

Sector Erase Operation (Note 1)

VCC Setup Time

50

500

4

50

500

4

µs

ns

µs

ns

—

Rise Time to VID (Note 2)

Rise Time to VACC (Note 3)

Voltage Transition Time (Note 2)

Write Pulse Width (Note 2)

OE Setup Time to WE Active (Note 2)

CE Setup Time to WE Active (Note 2)

Recover Time From RY/BY

RESET Pulse Width

—

100

4

100

4

—

4

—

0

—

t^RP

500

(Continued)

34

MBM29LV652UE-90/12

(Continued)

Parameter Symbols

JEDEC Standard

Description

RESET Hold Time Before Read

90

12

Unit

—

t^RH

t^BOSY

t^EOE

t^TOW

t^SPD

Min.

Max.

Min.

200

90

200

90

ns

µs

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-out Time

120

50

20

Erase Suspend Transition Time

Max.

20

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Group Protection operation.

3. This timing is for Accelerated Program operation.

35

MBM29LV652UE-90/12

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

Programming Time

—

1

10

s

Excludes system-level

overhead

—

16

360

µs

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

200

—

s

100,000

cycle

—

■ PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

C^IN

Input Capacitance

VIN = 0

VOUT = 0

VIN = 0

6

8.5

8

7.5

12

10

20

pF

C^OUT

C^IN2

Output Capacitance

Control Pin Capacitance

ACC Pin Capacitance

C^IN3

15

Note: Test conditions TA = 25°C, f = 1.0 MHz

36

MBM29LV652UE-90/12

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Changing

from H to L

May

Change

from L to H

Will Be

Changing

from L to H

“H” or “L”

Any Change

Permitted

Changing

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

“Off” State

tRC

Addresses

Addresses Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tCE

tOH

High-Z

Outputs

Output Valid

Figure 5.1 Read Operation Timing Diagram

37

MBM29LV652UE-90/12

tRC

Addresses

Addresses Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Output Valid

Figure 5.2 Hardware Reset/Read Operation Timing Diagram

38

MBM29LV652UE-90/12

Data Polling

3rd Bus Cycle

Addresses

XXXh

PA

tWC

tRC

tAS

tAH

CE

tCH

tCS

tCE

OE

tWP

tWPH

tOE

tGHWL

tWHWH1

WE

tDF

tOH

tDS

tDH

A0h

PD

DQ7

DOUT

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

Figure 6 Alternate WE Controlled Program Operation Timing Diagram

39

MBM29LV652UE-90/12

3rd Bus Cycle

Data Polling

Addresses

XXXh

PA

tWC

tAS

tAH

WE

tWS

tWH

OE

tGHEL

tCP

tCPH

tWHWH1

CE

tDS

tDH

A0h

PD

DQ7

D ^OUT

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

Figure 7 Alternate CE Controlled Program Operation Timing Diagram

40

MBM29LV652UE-90/12

XXXh

Addresses

XXXh

SA *

tWC

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

10h/

30h

AAh

55h

80h

AAh

55h

Data

tVCS

V CC

* : SA is the sector address for Sector Erase. Addresses = XXXh for Chip Erase.

Figure 8 Chip/Sector Erase Operation Timing Diagram

41

MBM29LV652UE-90/12

CE

t

CH

t

OE

t DF

OE

t

OEH

WE

t

CE

*

High-Z

DQ7 =

Valid Data

Data

DQ7

DQ

7

t

WHWH1 or 2

DQ to DQ

Val⁰id Data⁶

DQ

0

to DQ

6

DQ

0

to DQ

6

= Output Flag

t

BUSY

t EOE

RY/BY

* : DQ7 = Valid Data (The device has completed the Embedded operation.)

Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram

CE

t^OEH

WE

OE

tOES

tDH

*

DQ⁶=

Stop Toggling

DQ⁰to DQ7

Data Valid

DQ⁶= Toggle

DQ6 = Toggle

Data (DQ⁰to DQ⁷)

DQ6

t^OE

* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)

Figure 10 Toggle Bit I during Embedded Algorithm Operation Timing Diagram

42

MBM29LV652UE-90/12

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ

6

2

Toggle

DQ

2

and DQ

6

with OE or CE

Note: DQ2 is read from the erase-suspended sector.

Figure 11 DQ²vs. DQ⁶

CE

The rising edge of the last write pulse

WE

Entire programming

or erase operations

RY/BY

t BUSY

Figure 12 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

WE

RESET

tRP

t RB

RY/BY

tREADY

Figure 13 RESET,RY/BY Timing Diagram

43

MBM29LV652UE-90/12

A²¹, A20, A19

SGAX

SGAY

A18, A17

A0

A1

A6

VID

3 V

A9

tVLHT

VID

3 V

OE

tVLHT

tWPP

WE

tOESP

tCSP

CE

Data

01h

tVCS

tOE

V^CC

SGAX = Sector Group Address for initial sector

SGAY = Sector Group Address for next sector

Figure 14 Sector Group Protection Timing Diagram

44

MBM29LV652UE-90/12

VCC

VID

tVIDR

tVCS

tVLHT

3 V

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

RY/BY

Unprotection period

Figure 15 Temporary Sector Group Unprotection Timing Diagram

45

MBM29LV652UE-90/12

VCC

tVCS

tVLHT

RESET

Add

tVIDR

tWC

SGAX

SGAY

A0

A¹

A6

CE

OE

TIME-OUT

tWP

WE

Data

60h

40h

01h

60h

tOE

SGAX: Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min.)

Figure 16 Extended Sector Group Protection Timing Diagram

46

MBM29LV652UE-90/12

VCC

tVACCR

tVCS

tVLHT

VACC

3 V

ACC

CE

WE

tVLHT

Program or Erase Command Sequence

Acceleration period

Figure 17 Accelerated Program Timing Diagram

47

MBM29LV652UE-90/12

■ FLOW CHART

EMBEDDED ALGORITHMS

Start

Write Program Command

Sequence

(See below)

Data Polling

Embeded

Program

Algorithm

in progress

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

XXXh/AAh

XXXh/55h

XXXh/A0h

Program Address/Program Data

Figure 18 Embedded Program^TMAlgorithm

48

MBM29LV652UE-90/12

EMBEDDED ALGORITHMS

Start

Write Erase Command

Sequence

(See below)

Data Polling

Embeded

Program

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Chip Erase Command Sequence

(Address/Command):

Erase Command Sequence

(Address/Command):

XXXh/AAh

XXXh/55h

XXXh/80h

XXXh/AAh

XXXh/55h

XXXh/10h

XXXh/AAh

XXXh/55h

XXXh/80h

XXXh/AAh

XXXh/55h

Sector Address/30h

Additional sector

erase commands

are optional.

Sector Address/30h

Figure 19 Embedded Erase^TMAlgorithm

49

MBM29LV652UE-90/12

Start

Read Byte

(DQ 7 to DQ0)

Addr. = VA

VA = Byte address for programming

= Any of the sector addresses within

the sector being erased during

sector erase or multiple sector

erases operation

Yes

DQ7 = Data?

No

= Any of the sector addresses within

the sector not being protected

during chip erase

No

DQ5 = 1?

Yes

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data?

No

Fail

Pass

Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 20 Data Polling Algorithm

50

MBM29LV652UE-90/12

Start

Read DQ7 to DQ0

*1

Read DQ7 to DQ0

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

*1,*2

Read (DQ

7

to DQ0)

Twice

No

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

*1: Reset togglebit twice to determine whether or not it is toggle.

*2: Recheck toggle bit because it may stop toggle as DQ5 changes to “1”.

Figure 21 Toggle Bit Algorithm

51

MBM29LV652UE-90/12

Start

Setup Sector Group Addr.

(A²¹, A20, A19, A18, A17)

PLSCNT = 1

OE

CE

A0

=

VID, A9

VIL, RESET

VIL, A1

= VID,

A⁶

=

= VIH

=

VIH

Activate WE Pulse

Time out 100 µs

Increment PLSCNT

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

(Addr. = SGA, A0

= VIL,

A1 VIH, A6 = VIL

=

)

No

PLSCNT = 25?

Yes

Data = 01h?

Yes

Remove VID from A9

Write Reset Command

Protect Another Sector

Group ?

No

Device Failed

Remove VID from A9

Write Reset Command

Sector Group Protection

Completed

Figure 22 Sector Group Protection Algorithm

52

MBM29LV652UE-90/12

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*2

*1: All protected sector groups are unprotected.

*2: All previously protected sector groups are protected once again.

Figure 23 Temporary Sector Group Unprotection Algorithm

53

MBM29LV652UE-90/12

Start

RESET = V^ID

Wait to 4 µs

Device is Operating in

Temporary Sector Group

Unprotection Mode

No

Extended Sector Group

Protection Entry?

Yes

To Setup Sector Group

Protection Write XXXh/60h

PLSCNT = 1

To Sector Group Protection

Write SGA/60h

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Time Out 250 µs

Increment PLSCNT

Setup Next Sector Group

Address

To Verify Sector Group

Protection Write SGA/40h

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Read from Sector Group

Address

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove VID from RESET

Write Reset Command

Protection Other Sector

Group?

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Group Protection

Completed

Figure 24 Extended Sector Group Protection Algorithm

54

MBM29LV652UE-90/12

FAST MODE ALGORITHM

Start

XXXh/AAh

XXXh/55h

XXXh/20h

XXXh/A0h

Set Fast Mode

Program Address/Program Data

Data Polling Device

No

In Fast Program

Verify Data?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

XXXh/90h

XXXh/F0h

Reset Fast Mode

Figure 25 Embedded Program^TMAlgorithm for Fast Mode

55

MBM29LV652UE-90/12

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29LV652U

E

90 TN

PACKAGE TYPE

PBT=63ball Fine pitch Ball Gind Array Package

(FBGA) Standard Pinout

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

DEVICE NUMBER/DESCRIPTION

MBM29LV652U

64 Mega-bit (4M × 16-Bit) CMOS Flash Memory

3.0 V-only Read, Program, and Erase

56

MBM29LV652UE-90/12

■ PACKAGE DIMENSIONS

63-pin plastic FBGA (I)

(BGA-63P-M02)

11.00±0.10(.433±.004)

1.05 –⁺0⁰.^.1¹0⁵

(8.80(.346))

(7.20(.283))

.041 –⁺.^.0⁰0⁰4⁶

(Mounting height)

0.38±0.10

(.015±.004)

(Stand off)

(5.60(.220))

0.80(.031)TYP

8

7

6

5

4

3

2

1

(4.00(.157))

(5.60(.220))

10.00±0.10

(.394±.004)

M

L

K

J

H

G

F

E

D

C

B

A

INDEX AREA

INDEX BALL

63-Ø0.45±0.05

(63-Ø0.18±.002)

M

0.08(.003)

0.10(.004)

Dimensions in mm (inches)

C

1999 FUJITSU LIMITED B63002S-1C-1

57

MBM29LV652UE-90/12

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0012

FUJITSU LIMITED Printed in Japan


型号：	MBM29LV652UE-90
厂家：	FUJITSU
描述：	64M (4M X 16) BIT 64M （ 4M ×16 ）位
文件：	总58页 (文件大小：534K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29LV652UE-90 [FUJITSU]

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