MBM29SL160BD-10PFTN_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20877-1E

FLASH MEMORY

CMOS

16M (2M × 8/1M × 16) BIT

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ FEATURES

• Single 1.8 V read, program, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E²PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

48-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance

100 ns maximum access time

• Sector erase architecture

Eight 4K word and thirty one 32K word sectors in word mode

Eight 8K byte and thirty one 64K byte sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• One Time Protect (OTP) region

256 Byte of OTP, accessible through a new “OTP Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At V^IL, allows protection of boot sectors, regardless of sector protection/unprotection status

At V^IH, allows removal of boot sector protection

At V^HH, increases program performance

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

(Continued)

Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

(Continued)

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Sector group protection

Hardware method disables any combination of sector groups from program or erase operations

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

• Temporary sector group unprotection

Temporary sector group unprotection via the RESET pin.

• In accordance with CFI (Common Flash Memory Interface)

■ PACKAGE

48-pin plastic TSOP (I)

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

48-ball FBGA

(BGA-48P-M13)

2

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ GENERAL DESCRIPTION

The MBM29SL160TD/BD are a 16M-bit, 1.8 V-only Flash memory organized as 2M bytes of 8 bits each or 1M

words of 16 bits each. The MBM29SL160TD/BD are offered in a 48-pin TSOP(I) and 48-ball FBGA Package.

These devices are designed to be programmed in-system with the standard system 1.8 V V^CCsupply. 12.0 V

V^PPand 5.0 V V^CCare not required for write or erase operations. The devices can also be reprogrammed in

standard EPROM programmers.

The standard MBM29SL160TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),

write enable (WE), and output enable (OE) controls.

The MBM29SL160TD/BD are pin and command set compatible with JEDEC standard E²PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29SL160TD/BD are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.7 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29SL160TD/BD are erased when shipped from the

factory.

The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ⁷,

by the Toggle Bit feature on DQ⁶, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E²PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29SL160TD/BD memories electrically erase the entire chip

or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one

byte/word at a time using the EPROM programming mechanism of hot electron injection.

3

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 1 .1 Sector Address Tables (MBM29SL160TD)

Sector

Size

(Kbytes/

Kwords)

Sector Address

(×8)

(×16)

Address Range

Sector

Address Range

A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

000000H to 00FFFFH 000000H to 007FFFH

010000H to 01FFFFH 008000H to 00FFFFH

020000H to 02FFFFH 010000H to 017FFFH

030000H to 03FFFFH 018000H to 01FFFFH

040000H to 04FFFFH 020000H to 027FFFH

050000H to 05FFFFH 028000H to 02FFFFH

060000H to 06FFFFH 030000H to 037FFFH

070000H to 07FFFFH 038000H to 03FFFFH

080000H to 08FFFFH 040000H to 048000H

090000H to 09FFFFH 048000H to 04FFFFH

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

64/32 0A0000H to 0AFFFFH 050000H to 058000H

64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH

64/32 0C0000H to 0CFFFFH 060000H to 068000H

64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH

64/32 0E0000H to 0EFFFFH 070000H to 078FFFH

64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH

64/32

64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

64/32 1E0000H to 1EFFFFH 0F0000H to 0F7000H

8/4

100000H to 10FFFFH 080000H to 088000H

110000H to 11FFFFH 088000H to 08FFFFH

120000H to 12FFFFH 090000H to 098000H

130000H to 13FFFFH 098000H to 09FFFFH

140000H to 14FFFFH 0A0000H to 0A7FFFH

150000H to 15FFFFH 0A8000H to 00AFFFH

160000H to 16FFFFH 0B0000H to 0B7000H

170000H to 17FFFFH 0B8000H to 0BFFFFH

180000H to 18FFFFH 0C0000H to 0C7FFFH

190000H to 19FFFFH 0C8000H to 0CFFFFH

1F0000H to 1F1FFFH 0F8000H to 0F8FFFH

1F2000H to 1F3FFFH 0F9000H to 0F9FFFH

1F4000H to 1F5FFFH 0FA000H to 0FAFFFH

1F6000H to 1F7FFFH 0FB000H to 0FBFFFH

1F8000H to 1F9FFFH 0FC000H to 0FCFFFH

1FA000H to 1FBFFFH 0FD000H to 0FDFFFH

1FC000H to 1FDFFFH 0FE000H to 0FEFFFH

1FE000H to 1FFFFFH 0FF000H to 0FFFFFH

0

1

0

1

0

1

0

1

0

1

0

1

Note: The address range is A¹⁹: A^-1if in byte mode (BYTE = V^IL).

The address range is A¹⁹: A⁰if in word mode (BYTE = V^IH)

4

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 1 .2 Sector Address Tables (MBM29SL160BD)

Sector

Size

(Kbytes/

Kwords)

Sector Address

(×8)

(×16)

Address Range

Sector

Address Range

A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA38

SA37

SA36

SA35

SA34

SA33

SA32

SA31

SA30

SA29

SA28

SA27

SA26

SA25

SA24

SA23

SA22

SA21

SA20

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

1

X

1

X

1

64/32 1F0000H to 1FFFFFH 0F8000H to 0FFFFFH

64/32 1E0000H to 1EFFFFH 0F0000H to 0F7FFFH

64/32 1D0000H to 1DFFFFH 0E8000H to 0EFFFFH

64/32 1C0000H to 1CFFFFH 0E0000H to 0E7FFFH

64/32 1B0000H to 1BFFFFH 0D8000H to 0DFFFFH

64/32 1A0000H to 1AFFFFH 0D0000H to 0D7FFFH

64/32

190000H to 19FFFFH 0C8000H to 0CFFFFH

180000H to 18FFFFH 0C0000H to 0C7FFFH

170000H to 17FFFFH 0B8000H to 0BFFFFH

160000H to 16FFFFH 0B0000H to 0B7FFFH

150000H to 15FFFFH 0A8000H to 0AFFFFH

140000H to 14FFFFH 0A0000H to 0A7FFFH

130000H to 13FFFFH 098000H to 09FFFFH

120000H to 12FFFFH 090000H to 097FFFH

110000H to 11FFFFH 088000H to 08FFFFH

100000H to 10FFFFH 080000H to 087FFFH

64/32 0F0000H to 0FFFFFH 078000H to 07FFFFH

64/32 0E0000H to 0EFFFFH 070000H to 077FFFH

64/32 0D0000H to 0DFFFFH 068000H to 06FFFFH

64/32 0C0000H to 0CFFFFH 060000H to 067FFFH

64/32 0B0000H to 0BFFFFH 058000H to 05FFFFH

64/32 0A0000H to 0AFFFFH 050000H to 057FFFH

64/32

8/4

090000H to 0FFFFFH 048000H to 04FFFFH

080000H to 08FFFFH 040000H to 047FFFH

070000H to 07FFFFH 038000H to 03FFFFH

060000H to 06FFFFH 030000H to 037FFFH

050000H to 05FFFFH 028000H to 02FFFFH

040000H to 04FFFFH 020000H to 027FFFH

030000H to 03FFFFH 018000H to 01FFFFH

020000H to 02FFFFH 010000H to 017FFFH

010000H to 01FFFFH 008000H to 008FFFH

00E000H to 00FFFFH 007000H to 007FFFH

00C000H to 00DFFFH 006000H to 006FFFH

00A000H to 00BFFFH 005000H to 005FFFH

008000H to 009FFFH 004000H to 004FFFH

006000H to 007FFFH 003000H to 003FFFH

004000H to 005FFFH 002000H to 002FFFH

002000H to 003FFFH 001000H to 001FFFH

000000H to 001FFFH 000000H to 000FFFH

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

1

0

1

0

1

0

1

0

1

0

1

0

SA0

Note: The address range is A¹⁹: A^-1if in byte mode (BYTE = V^IL).

The address range is A¹⁹: A⁰if in word mode (BYTE = V^IH).

5

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 2 .1 Sector Group Addresses (MBM29SL160TD)

(Top Boot Block)

Sector Group

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

A¹⁵

0

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

Sectors

SGA0

SA0

0

1

SGA1

1

0

SA1 to SA3

1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

X

0

X

0

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SGA8

0

1

SA28 to SA30

1

0

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

1

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 2 .2 Sector Group Addresses (MBM29SL160BD)

(Bottom Boot Block)

Sector Group

SGA0

A¹⁹

0

1

A¹⁸

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

X

SGA8

1

0

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

X

0

X

0

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SGA15

SGA16

0

1

SA35 to SA37

SA38

1

0

1

7

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ PRODUCT LINE UP

Part No.

MBM29SL160TD/MBM29SL160BD

Ordering Part No.

V^CC= 2.0 V±0.2V

-10

100

35

-12

120

50

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

■ BLOCK DIAGRAM

DQ 0 to DQ 15

RY/BY

Buffer

RY/BY

VCC

V_SS

Erase Voltage

Generator

Input/Output

Buffers

WE

State

Control

BYTE

RESET

Command

WP/ACC

Register

Program Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data Latch

CE

OE

Y-Decoder

Y-Gating

STB

Timer for

Program/Erase

Address

Latch

Low V^CCDetector

X-Decoder

Cell Matrix

A0

to A19

A_-1

8

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ CONNECTION DIAGRAMS

TSOP(I)

A15

A14

A13

A12

A11

A10

A9

A8

A¹⁹

1

2

3

4

5

6

7

8

A16

BYTE

V^SS

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

(Marking Side)

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE

9

N.C.

WE

RESET

N C

WP/ACC

RY/BY

A¹⁸

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MBM29SL160TD/MBM29SL160BD

Standard Pinout

A17

A7

A6

A5

A4

A3

A2

A1

V^SS

CE

A⁰

FPT-48P-M19

A1

A2

A3

A4

A5

A6

A7

A0

CE

V^SS

OE

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

(Marking Side)

DQ⁰

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

VCC

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ¹⁵/A^-1

VSS

A17

A18

RY/BY

WP/ACC

N.C.

RESET

WE

N.C.

A¹⁹

MBM29SL160TD/MBM29SL160BD

Reverse Pinout

A⁸

A9

A10

A11

A¹²

A13

A14

A15

BYTE

A¹⁶

FPT-48P-M20

9

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

(Continued)

FBGA

(TOP VIEW)

Marking side

A1 A2 A3 A4 A5 A6

B1 B2 B3 B4 B5 B6

C1 C2 C3

D1 D2 D3

E1 E2 E3

C4 C5 C6

D4 D5 D6

E4 E5 E6

F4 F5 F6

F1

F2 F3

G1 G2 G3 G4 G5 G6

H1 H2 H3 H4 H5

(BGA-48P-M03)

H6

A1

B1

C1

D1

E1

F1

G1

H1

A³

A2

B2

C2

D2

E2

F2

G2

H2

A⁷

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY

A4

WE

A5

A⁹

A6

B6

C6

D6

E6

F6

G6

H6

A¹³

A⁴

A¹⁷

A⁶

WP/ACC B4

RESET B5

A⁸

A¹²

A²

A¹⁸

C4

D4

E4

F4

G4

H4

N.C.

A¹⁹

C5

D5

E5

F5

G5

H5

A¹⁰

A¹⁴

A¹

A⁵

N.C.

DQ²

DQ¹⁰

DQ¹¹

DQ³

A¹¹

A¹⁵

A⁰

DQ⁰

DQ⁸

DQ⁹

DQ¹

DQ⁵

DQ¹²

V^CC

DQ⁷

DQ¹⁴

DQ¹³

DQ⁶

A¹⁶

CE

OE

V^SS

BYTE

DQ¹⁵/A^-1

V^SS

DQ⁴

10

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ LOGIC SYMBOL

Table 3 MBM29SL160TD/BD Pin Configuration

A^-1, A⁰to A¹⁹

DQ⁰to DQ¹⁵

CE

Function

A^–1

Address Inputs

Data Inputs/Outputs

Chip Enable

20

16 or 8

A⁰to A¹⁹

DQ⁰to DQ¹⁵

OE

Output Enable

CE

OE

WE

Write Enable

RY/BY

Ready/Busy Output

WE

RESET

BYTE

RY/BY

Hardware Reset Pin/Temporary Sector

Group Unprotection

RESET

BYTE

WP/ACC

Selects 8-bit or 16-bit mode

Hardware Write Protection/Program

Acceleration

WP/ACC

N.C.

V^SS

No Internal Connection

Device Ground

V^CC

Device Power Supply

11

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 4 MBM29SL160TD/BD User Bus Operations (BYTE = V^IH)

Operation

Auto-Select Manufacturer Code (1)

Auto-Select Device Code (1)

Read (3)

CE OE WE A⁰

A¹

L

A⁶

L

A⁹DQ⁰to DQ¹⁵RESET WP/ACC

L

H

L

X

L

H

X

H

L

H

A⁰

X

A⁰

L

V^ID

A⁹

X

Code

D^OUT

HIGH-Z

D^IN

H

V^ID

L

X

L

A¹

X

A⁶

X

A⁶

L

Standby

X

H

V^ID

L

Output Disable

X

Write (Program/Erase)

A¹

H

X

A⁹

V^ID

X

Enable Sector Group Protection (2), (4)

Verify Sector Group Protection (2), (4)

Temporary Sector Group Unprotection (5)

Reset (Hardware)/Standby

Boot Block Sector Write Protection

X

H

X

L

Code

X

HIGH-Z

X

Table 5 MBM29SL160TD/BD User Bus Operations (BYTE = V^IL)

DQ¹⁵/

Operation

CE OE WE

A⁰

A¹

A⁶

A⁹DQ⁰to DQ⁷RESET WP/ACC

A^-1

Auto-Select Manufacturer Code (1)

Auto-Select Device Code (1)

Read (3)

L

H

L

H

X

H

L

H

L

V^ID

A⁹

X

Code

D^OUT

H

X

L

A^-1

X

A⁰

X

A¹

X

A⁶

X

Standby

X

H

HIGH-Z

D^IN

Output Disable

X

Write (Program/Erase)

A^-1

A⁰

A¹

A⁶

A⁹

Enable Sector Group Protection

(2), (4)

L

X

V^ID

L

H

X

L

X

V^ID

X

Code

X

H

X

Verify Sector Group Protection

(2), (4)

H

X

Temporary Sector Group

Unprotection (5)

X

V^ID

Reset (Hardware)/Standby

X

HIGH-Z

X

L

X

L

Boot Block Sector Write Protection

X

Legend: L = V^IL, H = V^IH, X = V^ILor V^IH,

= Pulse input. See DC Characteristics for voltage levels.

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See

Table 7.

2. Refer to the section on Sector Group Protection.

3. WE can be V^ILif OE is V^IL, OE at V^IHinitiates the write operations.

4. V^CC= 2.0 V ± 10%

5. It is also used for the extended sector group protection.

12

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ FUNCTIONAL DESCRIPTION

Read Mode

TheMBM29SL160TD/BDhavetwocontrolfunctionswhichmustbesatisfiedinordertoobtaindataattheoutputs.

CE is the power control and should be used for a device selection. OE is the output control and should be used

to gate data to the output pins if a device is selected.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t^CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least t^ACC-t^OEtime.) When reading out a data without changing addresses after

power-up, it is necessary to input hardware reset or to change CE pin from “H” to “L”

Standby Mode

There are two ways to implement the standby mode on the MBM29SL160TD/BD devices, one using both the

CE and RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V^CC± 0.3 V.

Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, V^CC

active current (I^CC2) is required even CE = “H”. The device can be read with standard access time (t^CE) from either

of these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V^SS± 0.3 V (CE

= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken

high, the device requires t^RHof wake up time before outputs are valid for read access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

MBM29SL160TD/BD data. This mode can be used effectively with an application requested low power

consumption such as handy terminals.

To activate this mode, MBM29SL160TD/BD automatically switch themselves to low power mode when

MBM29SL160TD/BD addresses remain stably during access fine of 150 ns. It is not necessary to control CE,

WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).

During simultaneous operation, V^CCactive current (I^CC2) is required.

Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,

the mode is canceled automatically and MBM29SL160TD/BD read-out the data for changed addresses.

Output Disable

With the OE input at a logic high level (V^IH), output from the devices are disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer

and type. This mode is intended for use by programming equipment for the purpose of automatically matching

the devices to be programmed with its corresponding programming algorithm. This mode is functional over the

entire temperature range of the devices.

To activate this mode, the programming equipment must force V^ID(10 V to 11 V) on address pin A⁹. Two identifier

bytes may then be sequenced from the devices outputs by toggling address A⁰from V^ILto V^IH. All addresses are

DON’T CARES except A⁰, A¹, and A⁶(A^-1). (See Tables 4 and 5.)

13

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

The manufacturer and device codes may also be read via the command register, for instances when the

MBM29SL160TD/BD are erased or programmed in a system without access to high voltage on the A⁹pin. The

command sequence is illustrated in Table 7. (Refer to Autoselect Command section.)

Word 0 (A⁰= V^IL) represents the manufacturer’s code (Fujitsu = 04H) and word 1 (A⁰= V^IH) represents the device

identifier code (MBM29SL160TD = E4H and MBM29SL160BD = E7H for ×8 mode; MBM29SL160TD = 22E4H

and MBM29SL160BD = 22E7H for ×16 mode). These two bytes/words are given in the tables 6.1 to 6.2. All

identifiers for manufactures and device will exhibit odd parity with DQ⁷defined as the parity bit. In order to read

the proper device codes when executing the autoselect, A¹must be V^IL. (See Tables 6.1 to 6.2.)

Table 6 .1 MBM29SL160TD/BD Sector Group Protection Verify Autoselect Codes

*1

Type

A¹²to A¹⁹

A⁶

A¹

A⁰

A_-1

V^IL

X

Code (HEX)

04H

Manufacture’s Code

X

V^IL

Byte

Word

Byte

E4H

MBM29SL160TD

X

V^IL

V^IH

22E4H

E7H

Device

Code

V^IL

X

MBM29SL160BD

V^IL

V^IH

V^IL

Word

22E7H

Sector Group

Addresses

Sector Group Protection

*1: A^-1is for Byte mode.

V^IL

01H^*2

*2: Outputs 01H at protected sector group addresses and outputs 00H at unprotected sector group addresses.

Table 6 .2 Expanded Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A^-1/0

Manufacturer’s Code

04H

0

1

0

1

0

1

0

1

0

1

(B)

E4H A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1

(W) 22E4H

(B) E7H A^-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1

MBM29SL160TD

0

1

0

1

0

1

Device

Code

MBM29SL160BD

(W) 22E7H

01H

0

1

0

1

0

1

0

A^-1/0

Sector Group Protection

(B): Byte mode

(W): Word mode

14

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The

command register is written by bringing WE to V^IL, while CE is at V^ILand OE is at V^IH. Addresses are latched on

the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,

whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Group Protection

The MBM29SL160TD/BD feature hardware sector group protection. This feature will disable both program and

erase operations in any combination of seventeen sector groups of memory. (See Tables 2.1 and 2.2). The sector

group protection feature is enabled using programming equipment at the user’s site. The device is shipped with

all sector groups unprotected.

To activate this mode, the programming equipment must force V^IDon address pin A⁹and control pin OE, (suggest

V^ID= 10V to 11V), CE = V^ILand A⁰= A⁶= V^IL, A¹= V^IH. The sector group addresses (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴,

A¹³, and A¹²) should be set to the sector to be protected. Tables 1.1 and 1.2 define the sector address for each

of the thirty nine (39) individual sectors, and tables 2.1 and 2.2 define the sector group address for each of the

seventeen (17) individual group sectors. Programming of the protection circuitry begins on the falling edge of

the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant

during the WE pulse. See figures 16 and 25 for sector group protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A⁹

with CE and OE at V^ILand WE at V^IH. Scanning the sector group addresses (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and

A¹²) while (A⁶, A¹, A⁰) = (0, 1, 0) will produce a logical “1” code at device output DQ⁰for a protected sector.

Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except

for A⁰, A¹, and A⁶are DON’T CARES. Address locations with A¹= V^ILare reserved for Autoselect manufacturer

and device codes. A^-1requires to apply to V^ILon byte mode.

It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.

Performing a read operation at the address location XX02H, where the higher order addresses (A¹⁹, A¹⁸, A¹⁷,

A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²) are the desired sector group address will produce a logical “1” at DQ⁰for a protected

sector group. See Tables 6.1 and 6.2 for Autoselect codes.

Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the MBM29SL160TD/BD

devices in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to

high voltage (V^ID). During this mode, formerly protected sector groups can be programmed or erased by selecting

the sector group addresses. Once the V^IDis taken away from the RESET pin, all the previously protected sector

groups will be protected again. Refer to Figures 17 and 26.

15

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

RESET

Hardware Reset

The MBM29SL160TD/BD devices may be reset by driving the RESET pin to V^IL. The RESET pin has a pulse

requirement and has to be kept low (V^IL) for at least “t^RP” in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset

to the read mode “t^READY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

devices require an additional “t^RH” before it will allow read access. When the RESET pin is low, the devices will

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware

reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please

note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing

diagram. Refer to Temporary Sector Group Unprotection for additional functionality.

Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain boot sectors without using V^ID.

This function is one of two provided by the WP/ACC pin.

If the system asserts V^ILon the WP/ACC pin, the device disables program and erase functions in the two

“outermost” 8K byte boot sectors independently of whether those sectors were protected or unprotected using

the method described in “Sector Protection/Unprotection”. The two outermost 8K byte boot sectors are the two

sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the

highest addresses in a top-boot-congfigured device.

(MBM29SL160TD: SA37 and SA38, MBM29SL160BD: SA0 and SA1)

If the system asserts V^IHon the WP/ACC pin, the device reverts to whether the two outermost 8K byte boot

sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two

sectors depends on whether they were last protected or unprotected using the method described in “Sector

protection/unprotection”.

Accelerated Program Operation

ThedeviceoffersacceleratedprogramoperationsthroughtheACCfunction. Thisisoneoftwofunctionsprovided

by the WP/ACC pin. This function is primarily intended to allow faster factory throughput by 50 percent.

If the system asserts V^HHon this pin, the device automatically enters the after mentioned Fast mode, temporarily

unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program

operations. The system would use a two-cycle program command sequence as required by the Fast mode.

Removing V^HHfrom the WP/ACC pin returns the device to normal operation.

If you use this function, please contact a Fujitsu representative for more information.

16

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 7 MBM29SL160TD/BD Command Definitions

Fourth Bus

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Sixth Bus

Bus

Write

Cycles

Req’d

Read/Write

Cycle

Command

Sequence

Write Cycle Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Read/Reset

Autoselect

Program

1

3

4

6

XXXH F0H

—

RA

—

RD

—

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555H

AAH

2AAH

555H

2AAH

555H

2AAH

555H

2AAH

555H

2AAH

555H

—

555H

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

—

55H

F0H

90H

A0H

80H

AAAH

555H

AAH

—

AAAH

555H

AAH

PA

PD

—

AAAH

555H

AAH

555H

AAAH

555H

AAAH

—

2AAH

555H

2AAH

555H

—

555H

Chip Erase

Sector Erase

AAH

55H

10H

30H

AAAH

555H

AAH

SA

AAAH

Erase Suspend

Erase Resume

1

XXXH B0H

XXXH 30H

—

Word

555H

AAH

2AAH

555H

AAAH

Set to

3

2

4

1

3

4

55H

20H

—

Fast Mode

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

AAAH

XXXH

A0H

Fast

Program *1

PA

PD

—

XXXH

90H

XXXH

F0H

Reset from

Fast Mode *1

—

5

*

XXXH

Extended

Sector Group

Protection *2

XXXH 60H SPA 60H SPA 40H SPA SD

55H

Query *3

98H

AAH

—

AAH

555H

AAAH

555H

AAAH

555H

AAAH

2AAH

555H

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

555H

AAAH

OTP

Entry

55H

88H

A0H

—

OTP

Program *4

PA

PD

OTP

Exit *4

90H XXXH 00H

17

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Notes: 1. Address bits A¹¹to A¹⁹= X = “H” or “L” for all address commands except or Program Address (PA), Sector

Address (SA).

2. Bus operations are defined in Tables 4 and 5.

3. RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²will

uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5. SPA = Sector group address to be protected. Set sector group address (SGA) and (A⁶, A¹, A⁰) = (0, 1, 0).

SD = Sector group protection verify data. Output 01H at protected sector group addresses and output

00H at unprotected sector group addresses.

6. OTPA =Address of the OTP area

29SL160TD (Top Boot Type)

Word Mode: FFF7FH to FFFFFH

Byte Mode: 1FFEFFH to 1FFFFFH

29SL160BD (Bottom Boot Type) Word Mode: 00000H to 00080H

Byte Mode: 00000H to 00100H

*1: This command is valid while Fast Mode.

*2: This command is valid while RESET = V^ID.

*3: The valid addresses are A⁶to A⁰.

*4: This command is valid while OTP mode.

*5: The data "00H" is also acceptable.

7. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A⁰to A¹⁰

Byte Mode: AAAH or 555H to addresses A^–1and A⁰to A¹⁰

8. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

18

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the

read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both

Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that

commands are always written at DQ⁰to DQ⁷and DQ⁸to DQ¹⁵bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the

command register contents are altered.

The devices will automatically power-up in the Read/Reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the devices reside in the target system. PROM

programmers typically access the signature codes by raising A⁹to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the Autoselect command sequence into the command register.

Following the command write, a read cycle from address (XX)00H retrieves the manufacture code of 04H. A

read cycle from address (XX)01H for ×16((XX)02H for ×8) returns the device code (MBM29SL160TD = E4H and

MBM29SL160BD = E7H for ×8 mode; MBM29SL160TD = 22E4H and MBM29SL160BD = 22E7H for ×16 mode),

(See Tables 6.1 and 6.2.)

AllmanufactureranddevicecodeswillexhibitoddparitywithDQ⁷definedastheparitybit. Sectorstate(protection

or unprotection) will be informed by address (XX)02H for ×16 ((XX)04H for ×8). Scanning the sector group

addresses (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²) while (A⁶, A¹, A⁰) = (0, 1, 0) will produce a logical “1” at device

output DQ⁰for a protected sector group. The programming verification should be performed by verify sector

group protection on the protected sector. (See Tables 4 and 5.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and

also to write the Autoselect command during the operation, execute it after writing Read/Reset command

sequence.

Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle

operation. There are two “unlock” write cycles. These are followed by the program set-up command and data

write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is

latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever

happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,

the system is not required to provide further controls or timings. The device will automatically provide adequate

internally generated program pulses and verify the programmed cell margin.

19

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

The system can determine the status of the program operation by using DQ⁷(Data Polling), DQ⁶(Toggle Bit),

or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

The automatic programming operation is completed when the data on DQ⁷is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched. (See Table 13,

Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices be supplied by

the system at this particular instance of time. Hence, Data Polling must be performed at the memory location

which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during the

programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 21 illustrates the Embedded Program^TMAlgorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence the devices will automatically program and verify the entire memory for an all

zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ⁶(Toggle Bit), or

RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence and terminates when the data on DQ⁷is “1” (See Write Operation Status section.) at which time the

device returns to read the mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

Figure 22 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever

happens later, while the command (Data = 30H) is latched on the rising edge of CE or WE which happens first.

After time-out of 50µs from the rising edge of the last sector erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 7. This sequence

is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than 50µs otherwise that command will not be accepted and

erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this

condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50µs

from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase

command(s). If another falling edge of CEorWE, whichever happens first occurs within the 50µs time-out window

the timer is reset. (Monitor DQ³to determine if the sector erase timer window is still open, see section DQ³,

Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will

reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution

has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to

20

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector

erase buffer may be done in any sequence and with any number of sectors (0 to 38).

Sector erase does not require the user to program the devices prior to erase. The devices automatically program

all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing

a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ⁶(Toggle Bit), or

RY/BY.

The sector erase begins after the 50µs time out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and terminates when the data on DQ⁷is “1” (See Write Operation Status

section.) at which time the devices return to the read mode. Data polling and Toggle Bit must be performed at

an address within any of the sectors being erased.

Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector

Erase

Figure 22 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads

from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase

operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if

written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command

(B0H) during the Sector Erase time-out results in immediate termination of the time-out period and suspension

of the erase operation.

Writing the Erase Resume command (30H) resumes the erase operation. The address are DON’T CARES when

writing the Erase Suspend or Erase Resume command (30H).

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of 20µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the

RY/BY output pin will be at Hi-Z and the DQ⁷bit will be at logic “1”, and DQ⁶will stop toggling. The user must

use the address of the erasing sector for reading DQ⁶and DQ⁷to determine if the erase operation has been

suspended. Further writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from

sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ²to toggle. (See the section on DQ².)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate

command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,

programming in this mode is the same as programming in the regular Program mode except that the data must

beprogrammedtosectorsthatarenoterase-suspended. Successivelyreadingfromtheerase-suspendedsector

while the devices are in the erase-suspend-program mode will cause DQ²to toggle. The end of the erase-

suspended Program operation is detected by the RY/BY output pin, Data polling of DQ⁷or by the Toggle Bit I

(DQ⁶) which is the same as the regular Program operation. Note that DQ⁷must be read from the Program address

while DQ⁶can be read from any address.

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

21

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Extended Command

(1) Fast Mode

MBM29SL160TD/BD has Fast Mode function. This mode dispenses with the initial two unclock cycles

required in the standard program command sequence by writing Fast Mode command into the command

register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in

standardprogramcommand. (Donotwriteerasecommandinthismode.)Thereadoperationisalsoexecuted

afterexitingthismode. Toexitthismode, itisnecessarytowriteFastModeResetcommandintothecommand

register. (Refer to the Figure 27.) The V^CCactive current is required even CE = V^IHduring Fast Mode.

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to

the Figure 27.)

(3) Extended Sector Group Protection

In addition to normal sector group protection, the MBM29SL160TD/BD has Extended Sector Group

Protection as extended function. This function enable to protect sector group by forcing V^IDon RESET pin

and write a command sequence. Unlike conventional procedure, it is not necessary to force V^IDand control

timingforcontrolpins. TheonlyRESETpinrequiresV^IDforsectorgroupprotectioninthismode. Theextended

sector group protection requires V^IDon RESET pin. With this condition, the operation is initiated by writing

the set-up command (60H) into the command register. Then, the sector group addresses pins (A¹⁹, A¹⁸, A¹⁷,

A¹⁶, A¹⁵, A¹⁴, A¹³and A¹²) and (A⁶, A¹, A⁰) = (0, 1, 0) should be set to the sector group to be protected

(recommend to set V^ILfor the other addresses pins), and write extended sector group protection command

(60H). A sector group is typically protected in 150 µs. To verify programming of the protection circuitry, the

sector group addresses pins (A¹⁹, A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³and A¹²) and (A⁶, A¹, A⁰) = (0, 1, 0) should be set

and write a command (40H). Following the command write, a logical “1” at device output DQ⁰will produce

for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended

sector group protection command (60H) again. To terminate the operation, it is necessary to set RESET pin

to V^IH. (Refer to the Figures 19 and 28.)

(4) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software

interrogation handshake which allows specific vendor-specified software algorithms to be used for entire

families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward-

compatible software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98H) into the command register. Following the

command write, a read cycle from specific address retrives device information. Please note that output data

of upper byte (DQ⁸to DQ¹⁵) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate

operation, it is necessary to write the read/reset command sequence into the register. (See Table 15.)

22

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

One Time Protect (OTP) Region

The OTP feature provides a Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the OTP region is protected, any further modification

of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.

The OTP region is 256 bytes in length. The MBM29SL160TD occupies the address of the byte mode 1FFEFFH

to 1FFFFFH (word mode FFF7FH to FFFFFH) and the MBM29SL160BD type occupies the address of the byte

mode 00000H to 00100H (word mode 00000H to 00080H). After the system has written the Enter OTP command

sequence, the system may read the OTP region by using the addresses normally occupied by the boot sectors.

That is, the device sends all commands that would normally be sent to the boot sectors to the OTP region. This

mode of operation continues until the system issues the Exit OTP command sequence, or until power is removed

from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the

boot sectors.

If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more

information.

Write Operarion Status

Table 8 Hardware Sequence Flags

Status

DQ⁷

DQ⁶

DQ⁵DQ³

DQ²

Embedded Program Algorithm

DQ⁷Toggle

0

1

Toggle

(Note 2)

Embedded Erase Algorithm

0

1

Toggle

1

Erase Suspend Read

(Erase Suspended Sector)

0

Toggle

In Progress

Erase

Erase Suspend Read

Suspended

Data Data Data Data Data

(Non-Erase Suspended Sector)

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

Toggle

(Note 1)

1

DQ⁷

0

(Note 2)

Embedded Program Algorithm

Embedded Erase Algorithm

DQ⁷Toggle

Toggle

1

0

1

0

N/A

Exceeded

Time Limits

Erase

Erase Suspend Program

Suspended

DQ⁷Toggle

1

0

N/A

(Non-Erase Suspended Sector)

Mode

Notes: 1. Performing successive read operetions from any address will cause DQ⁶to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic "1" at the DQ²bit. However, successive reads from the erase-suspend sector will cause DQ²t o

toggle.

3. DQ⁰and DQ¹are reserve pins for future use.

4. DQ⁴is Fujitsu internal use only

23

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

DQ⁷

Data Polling

The MBM29SL160TD/BD devices feature Data Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the

devices will produce the complement of the data last written to DQ⁷. Upon completion of the Embedded Program

Algorithm, an attempt to read the device will produce the true data last written to DQ⁷. During the Embedded

Erase Algorithm, an attempt to read the device will produce a “0” at the DQ⁷output. Upon completion of the

Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ⁷output. The flowchart

for Data Polling (DQ⁷) is shown in Figure 23.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased

and not a protected sector. Otherwise, the status may not be valid.

Once the Embedded Algorithm operation is close to being completed, the MBM29SL160TD/BD data pins (DQ⁷)

may change asynchronously while the output enable (OE) is asserted low. This means that the devices are

driving status information on DQ⁷at one instant of time and then that byte’s valid data at the next instant of time.

Depending on when the system samples the DQ⁷output, it may read the status or valid data. Even if the device

has completed the Embedded Algorithm operation and DQ⁷has a valid data, the data outputs on DQ⁰to DQ⁶

may be still invalid. The valid data on DQ⁰to DQ⁷will be read on the successive read attempts.

TheDataPollingfeatureisonlyactiveduringtheEmbeddedProgrammingAlgorithm,EmbeddedEraseAlgorithm

or sector erase time-out. (See Table 8.)

See Figure 9 for the Data Polling timing specifications and diagrams.

DQ⁶

Toggle Bit I

The MBM29SL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from

the devices will result in DQ⁶toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ⁶will stop toggling and valid data will be read on the next successive attempts. During

programming, theToggleBitIisvalidaftertherisingedgeofthefourthwritepulseinthefourwritepulsesequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop

toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the

ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs

and then drop back into read mode, having changed none of the data.

Either CE or OE toggling will cause the DQ⁶to toggle. In addition, an Erase Suspend/Resume command will

cause the DQ⁶to toggle. See Figure 10 for the Toggle Bit I timing specifications and diagrams.

24

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ⁵will produce a “1”. This is a failure condition which indicates that the program or erase

cycle was not successfully completed. Data Polling is the only operating function of the devices under this

condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA).

The OE and WE pins will control the output disable functions as described in Tables 4 and 5.

The DQ⁵failure condition may also appear if a user tries to program a non blank location without erasing. In this

case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ⁷bit and DQ⁶never stops toggling. Once the devices have exceeded timing limits, the

DQ⁵bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly

used. If this occurs, reset the device with command sequence.

DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ³will

remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ³may

be used to determine if the sector erase timer window is still open. If DQ³is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or Toggle Bit I. If DQ³is low (“0”), the device will accept

additional sector erase commands. To insure the command has been accepted, the system software should

check the status of DQ³prior to and following each subsequent Sector Erase command. If DQ³were high on

the second status check, the command may not have been accepted.

See Table 8: Hardware Sequence Flags.

DQ²

Toggle Bit II

This toggle bit II, along with DQ⁶, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ²to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ²bit.

DQ⁶is different from DQ²in that DQ⁶toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ⁷, is summarized

as follows:

For example, DQ²and DQ⁶can be used together to determine if the erase-suspend-read mode is in progress.

(DQ²toggles while DQ⁶does not.) See also Table 9 and Figure 18.

Furthermore, DQ²can also be used to determine which sector is being erased. When the device is in the erase

mode, DQ²toggles if this bit is read from an erasing sector.

25

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 9 Toggle Bit Status

Mode

DQ⁷

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

Erase-Suspend Program

DQ⁷

Toggle (Note 1)

1 (Note 2)

Note: 1.Performing successive read operetions from any address will cause DQ⁶to toggle.

2.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic

"1" at the DQ²bit. However, successive reads from the erase-suspend sector will cause DQ²to toggle.

RY/BY

Ready/Busy

The MBM29SL160TD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that

the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are

busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/

write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase

commands. If the MBM29SL160TD/BD are placed in an Erase Suspend mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate

a busy condition during the RESET pulse. Refer to Figures 11 and 12 for a detailed timing diagram. The RY/BY

pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V^CC.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29SL160TD/BD devices. When

this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ⁰

to DQ¹⁵. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ¹⁵/A^-1pin

becomes the lowest address bit and DQ⁸to DQ¹⁴bits are tri-stated. However, the command bus cycle is always

an 8-bit operation and hence commands are written at DQ⁰to DQ⁷and the DQ⁸to DQ¹⁵bits are ignored. Refer

to Figures 13, 14 and 15 for the timing diagram.

Data Protection

The MBM29SL160TD/BD are designed to offer protection against accidental erasure or programming caused

by spurious system level signals that may exist during power transitions. During power up the devices

automatically reset the internal state machine in the Read mode. Also, with its control register architecture,

alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command

sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.

26

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = V^IL, CE = V^IH, or WE = V^IH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the devices with WE = CE = V^ILand OE = V^IHwill not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

27

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Table 10 Common Flash Memory Interface Code

DQ⁰to DQ¹⁵

Description

A⁰to A⁶

DQ⁰to DQ¹⁵

Description

A⁰to A⁶

Erase Block Region 2

Information29SL160

31h

32h

33h

34h

001Eh

0000h

0001h

Query-unique ASCII string

“QRY”

10h

11h

12h

0051h

0052h

0059h

Primary OEM Command Set

2h: AMD/FJ standard type

13h

14h

0002h

0000h

Query-unique ASCII string

“PRI”

40h

41h

42h

0050h

0052h

0049h

Address for Primary

Extended Table

15h

16h

0040h

0000h

Major version number, ASCII

Minor version number, ASCII

43h

44h

45h

0031h

0000h

Alternate OEM Command

Set (00h = not applicable)

17h

18h

0000h

Address Sensitive Unlock

0 = Required

1 = Not Required

Address for Alternate OEM

Extended Table

19h

1Ah

0000h

V^CCMin. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Bh

0018h

Erase Suspend

46h

47h

48h

0002h

0001h

0 = Not Supported

1 = To Read Only

2 = To Read & Write

V^CCMax. (write/erase)

D7-4: volt, D3-0: 100 mvolt

1Ch

0027h

V^PPMin. voltage

V^PPMax. voltage

1Dh

1Eh

1Fh

0000h

0004h

Sector Protection

0 = Not Supported

X = Number of sectors in per

group

Typical timeout per single

byte/word write 2^Nµs

Sector Temporary

Unprotection

00 = Not Supported

01 = Supported

Typical timeout for Min. size

20h

21h

22h

23h

24h

25h

26h

27h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

0015h

buffer write 2^Nµs

Typical timeout per individual

block erase 2^Nms

Sector Protection Algorithm

49h

4Ah

0004h

0000h

Typical timeout for full chip

erase 2^Nms

Number of Sector for Bank 2

00h = Not Supported

Max. timeout for byte/word

write 2^Ntimes typical

Burst Mode Type

00 = Not Supported

4Bh

4Ch

4Dh

0000h

0085h

Max. timeout for buffer write

2^Ntimes typical

Page Mode Type

00 = Not Supported

Max. timeout per individual

block erase 2^Ntimes typical

ACC (Acceleration) Supply

Minimum

00h = Not Supported,

D7-4: volt, D3-0: 100 mvolt

Max. timeout for full chip

erase 2^Ntimes typical

Device Size = 2^Nbyte

ACC (Acceleration) Supply

Maximum

00h = Not Supported,

D7-4: volt, D3-0: 100 mvolt

4Eh

4Fh

0095h

00XXh

Flash Device Interface

description

28h

29h

0002h

0000h

Max. number of byte in

multi-byte write = 2^N

2Ah

2Bh

0000h

Boot Type

02h = MBM29SL160BD

03h = MBM29SL160TD

Number of Erase Block

Regions within device

2Ch

0002h

Erase Block Region 1

Information

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

28

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Conditions

Unit

Min.

Max.

Storage Temperature

Tstg

T^A

—

–55

+125

°C

Ambient Temperature with Power

Applied

–40

+85

Voltage with respect to Ground

All pins except A⁹, OE, RESET

(Note 1)

V^IN, V^OUT

—

–0.5

V^CC+ 0.5

V

Power Supply Voltage (Note 1)

A⁹, OE, and RESET (Note 2)

WP/ACC

V^CC

V^IN

—

–0.5

+3.0

+11.0

+10.5

V

Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative

overshoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are V^CC

+0.5 V. During voltage transitions, outputs may positive overshoot to V^CC+2.0 V for periods of up to 20 ns.

2. Minimum DC input voltage on A⁹, OE and RESET pins are –0.5 V. During voltage transitions, A⁹, OE

and RESET pins may negative overshoot V^SSto –2.0 V for periods of up to 20 ns. Maximum DC input

voltage on A⁹, OE and RESET pins are +11.0 V which may positive overshoot to 12.0 V for periods of

up to 20 ns. Voltage difference between input voltage and supply voltage (V^IN– V^CC) do not exceed 9 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Conditions

Unit

Min.

–40

Max.

+85

Ambient Temperature

Power Supply Voltage

T^A

—

°C

V

V^CC

+1.8

+2.2

Operating ranges define those limits between which the functionality of the devices are guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

29

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ MAXIMUM OVERSHOOT

20 ns

0.2 × V CC

–0.5 V

–2.0 V

20 ns

Figure 1 Maximum Negative Overshoot Waveform

20 ns

V CC +2.0 V

V CC +0.5 V

0.8 × V ^CC

20 ns

Figure 2 Maximum Positive Overshoot Waveform 1

20 ns

+12.0 V

+11.0 V

V ^CC+0.5 V

20 ns

*: This waveform is applied for A9, OE, and RESET.

Figure 3 Maximum Positive Overshoot Waveform 2

30

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ DC CHARACTERISTICS

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Max.

Unit

I^LI

Input Leakage Current

Output Leakage Current

V^IN= V^SSto V^CC, V^CC= V^CCMax.

V^OUT= V^SSto V^CC, V^CC= V^CCMax.

–1.0

+1.0

µA

I^LO

A⁹, OE, RESET Inputs Leakage V^CC= V^CCMax.

I^LIT

I^LIA

—

35

20

µA

Current

A⁹, OE, RESET = 11 V

V^CC= V^CCMax.

WP/ACC = V^HHMax.

WP/ACC Inputs Leakage Current

mA

Byte

Word

Byte

25

15

25

CE = V^IL, OE = V^IH,

f=10 MHz

—

mA

I^CC1

V^CCActive Current (Note 1)

CE = V^IL, OE = V^IH,

f=5 MHz

Word

I^CC2

I^CC3

I^CC4

V^CCActive Current (Note 2)

V^CCCurrent (Standby)

CE = V^IL, OE = V^IH

—

mA

V^CC= V^CCMax., CE = V^CC± 0.3 V,

RESET = V^CC± 0.3 V

5

µA

V^CC= V^CCMax.,

RESET = V^SS± 0.3 V

V^CCCurrent (Standby, Reset)

—

µA

V^CC= V^CCMax., CE = V^SS± 0.3 V,

RESET = V^CC± 0.3 V

V^IN= V^CC± 0.3 V or V^SS± 0.3 V

V^CCCurrent

(Automatic Sleep Mode) (Note 3)

I^CC5

5

µA

V^IL

V^IH

Input Low Level

Input High Level

—

–0.5

0.2 x V^CC

V^CC+0.3

V

0.8 x V^CC

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Accelaration

V^ACC

—

8.5

10

9.5

11

V

Voltage for Autoselect and Sector

Protection (A⁹, OE, RESET)

(Note 4, 5)

V^ID

V^OL

V^OH

Output Low Voltage Level

Output High Voltage Level

I^OL= 0.1 mA, V^CC= V^CCMin.

—

0.1

—

V

I^OH= –100 µA

V^CC–0.1

Notes: 1. The I^CCcurrent listed includes both the DC operating current and the frequency dependent component.

2. I^CCactive while Embedded Algorithm (program or erase) is in progress.

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. This timing is for Sector Protection operation.

5. Applicable for only V^CCapplying.

31

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

Symbols

-10

(Note)

-12

(Note)

Description

Test Setup

Unit

JEDEC Standard

t^AVAV

t^AVQV

t^RC

Read Cycle Time

—

Min.

Max.

100

120

ns

CE = V^IL

OE = V^IL

t^ACC

Address to Output Delay

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CE

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

OE = V^ILMax.

100

35

120

50

ns

—

Max.

30

40

30

40

Output Hold Time From

Addresses,

t^AXQX

t^OH

—

Min.

0

ns

CE or OE, Whichever Occurs First

—

t^READY

RESET Pin Low to Read Mode

—

Max.

20

5

20

5

µs

t^ELFL

t^ELFH

CE or BYTE Switching Low or

High

ns

Notes: Test Conditions:

Output Load:1 TTL gate and 30 pF (MBM29SL160TD/BD-10)

1 TTL gate and 100 pF (MBM29SL160TD/BD-12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CC

Timing measurement reference level

Input: 0.5 x V^CC

Output: 0.5 x V^CC

V^CC

IN3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

C^L

Diodes = IN3064

or Equivalent

Notes: C^L= 30 pF including jig capacitance (MBM29SL160TD/BD-10)

C^L= 100 pF including jig capacitance (MBM29SL160TD/BD-12)

Figure 4 Test Conditions

32

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

• Write/Erase/Program Operations

Parameter Symbols

JEDEC Standard

Description

Write Cycle Time

-10

-12

Unit

t^AVAV

t^AVWL

t^WLAX

t^DVWH

t^WHDX

—

t^WC

t^AS

Min.

100

0

120

0

ns

Address Setup Time

Address Hold Time

Data Setup Time

t^AH

50

0

60

0

t^DS

t^DH

t^OES

Data Hold Time

Output Enable Setup Time

0

Output

Read

0

—

t^OEH

Enable Hold

Time

Toggle and Data Polling

Min.

10

ns

t^GHWL

t^GHEL

t^ELWL

t^WLEL

t^WHEH

t^EHWH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

t^WHWH1

t^WHWH2

—

t^GHWL

t^GHEL

t^CS

Read Recover Time Before Write

CE Setup Time

Min.

Typ.

Min.

0

ns

0

ns

t^WS

WE Setup Time

0

ns

t^CH

CE Hold Time

0

ns

t^WH

WE Hold Time

0

ns

t^WP

Write Pulse Width

50

30

10.6

1.5

50

500

4

60

30

10.6

1.5

50

500

4

ns

t^CP

CE Pulse Width

ns

t^WPH

t^CPH

t^WHWH1

t^WHWH2

t^VCS

t^VIDR

t^VACCR

t^VLHT

t^WPP

t^OESP

t^CSP

t^RB

Write Pulse Width High

CE Pulse Width High

ns

Byte Programming Operation

Sector Erase Operation (Note 1)

V^CCSetup Time

µs

sec

µs

—

Rise Time to V^ID(Note 2)

Rise Time to V^ACC

ns

—

ns

—

Voltage Transition Time (Note 2)

Write Pulse Width (Note 2)

OE Setup Time to WE Active (Note 2)

CE Setup Time to WE Active (Note 2)

Recover Time From RY/BY

RESET Pulse Width

µs

—

100

4

100

4

µs

—

µs

—

4

µs

—

0

ns

—

t^RP

500

200

500

200

—

t^RH

RESET Hold Time Before Read

ns

(Continued)

33

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

(Continued)

Parameter Symbols

Description

-10

-12

Unit

JEDEC Standard

—

t^FLQZ

t^FHQV

t^BUSY

t^EOE

t^PS

BYTE Switching Low to Output High-Z

BYTE Switching High to Output Active

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Power On/Off Timing

Max.

Min.

Max.

Min.

30

90

100

0

40

90

120

0

ns

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Group Protection operation.

34

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ SWITCHING WAVEFORMS

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Changing

from H to L

May

Change

from L to H

Will Be

Changing

from L to H

“H” or “L”

Any Change

Permitted

Changing

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

“Off” State

t RC

Addresses

Addresses Stable

t ACC

CE

OE

t OE

t DF

t OEH

WE

t CE

High-Z

Outputs

Output Valid

Figure 5.1 AC Waveforms for Read Operations

35

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

t RC

Addresses

Addresses Stable

t ACC

t RH

RESET

Outputs

t OH

High-Z

Output Valid

Figure 5.2 AC Waveforms for Hardware Reset/Read Operations

36

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Data Polling

3rd Bus Cycle

Addresses

555H

PA

t WC

t RC

t AS

t AH

CE

t CH

t CS

t CE

OE

t WP

t WPH

t OE

t GHWL

t WHWH1

WE

t OH

t DS

t DH

A0H

PD

DQ 7

D OUT

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 6 AC Waveforms for Alternate WE Controlled Program Operations

37

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

3rd Bus Cycle

Data Polling

Addresses

PA

555H

t WC

t AS

t AH

WE

t WS

t WH

OE

CE

t GHEL

t CP

t CPH

t WHWH1

t DS

t DH

A0H

PD

DQ 7

D ^OUT

Data

Notes: 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ⁷is the output of the complement of the data written to the device.

4. D^OUTis the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 7 AC Waveforms for Alternate CE Controlled Program Operations

38

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

2AAH

555H

Addresses

555H

2AAH

SA

t WC

t AS

t AH

CE

t CS

t CH

OE

t WP

t WPH

t GHWL

WE

t DS

t DH

10H/

30H

AAH

55H

80H

AAH

55H

Data

t VCS

V CC

Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte)

for Chip Erase.

2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 8 AC Waveforms Chip/Sector Erase Operations

39

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

CE

t CH

t OE

t DF

OE

t OEH

WE

t CE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

t WHWH1 or 2

DQ0 to DQ6

Valid Data

DQ0 to DQ6

DQ⁰to DQ6 = Output Flag

t EOE

* : DQ⁷= Valid Data (The device has completed the Embedded operation).

Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations

CE

tOEH

WE

tOES

OE

*

DQ ⁶=

Stop Toggling

DQ 6

Data

DQ 6 = Toggle

Valid

t^OE

* : DQ⁶stops toggling (The device has completed the Embedded operation).

Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

40

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

CE

The rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

t BUSY

Figure 11 RY/BY Timing Diagram during Program/Erase Operations

WE

RESET

tRP

t RB

RY/BY

tREADY

Figure 12 RESET/RY/BY Timing Diagram

41

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

CE

BYTE

Data Output

(DQ⁰to DQ⁷)

Data Output

(DQ⁰to DQ¹⁴)

DQ⁰to DQ¹⁴

t^ELFH

t^FHQV

DQ¹⁵

DQ¹⁵/A^-1

A^-1

Figure 13 Timing Diagram for Word Mode Configuration

CE

BYTE

t^ELFL

DQ⁰to DQ¹⁴

Data Output

(DQ⁰to DQ¹⁴)

Data Output

(DQ⁰to DQ⁷)

DQ¹⁵/A^-1

DQ¹⁵

A^-1

t^FLQZ

Figure 14 Timing Diagram for Byte Mode Configuration

The falling edge of the last write signal

CE or WE

Input

Valid

BYTE

t^SET

(tAS)

tHOLD (tAH)

Figure 15 BYTE Timing Diagram for Write Operations

42

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

A¹⁸, A17, A16

SAX

SAY

A15, A14

A13, A12

A0

A1

A6

VID

VIH

A9

t VLHT

V^ID

VIH

OE

WE

CE

t VLHT

t WPP

t OESP

t CSP

Data

V^CC

01H

t VCS

t OE

SGAX:Sector Group Address for initial sector

SGAY:Sector Group Address for next sector

Note: A^-1is V^ILon byte mode.

Figure 16 AC Waveforms for Sector Group Protection Timing Diagram

43

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

VCC

tVIDR

tVCS

VID

VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

RY/BY

Figure 17 Temporary Sector Group Unprotection Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ6

DQ2

Toggle

DQ²and DQ6

with OE

Note: DQ²is read from the erase-suspended sector.

Figure 18 DQ²vs. DQ⁶

44

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

V^CC

t^VCS

RESET

Add

t^VLHT

t^VIDR

SGAX

SGAY

A⁰

A¹

A⁶

CE

OE

TIME-OUT

t^WP

WE

Data

60H

40H

01H

60H

SGAX : Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 50 µs (min)

Figure 19 Extended Sector Group Protection Timing Diagram

45

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

t PS

RESET

VIH

VCC

1.8 V

0 V

Input Valid

Addresses

Data

Output Valid

t RH

t ACC

Figure 20 Power ON/OFF Timing Diagram

46

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

V^CC

t^VACCR

t^VCS

t^VLHT

V^ACC

V^IH

3V

WP/ACC

CE

WE

t^VLHT

Program Command Sequence

RY/BY

Accelerated Program

Figure 21 Accelerated Program Operation Timing Diagram

47

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

EMBEDDED ALGORITHMS

Start

Write Program Command

Sequence

(See below)

Data Polling Device

No

Last Address

?

Increment Address

Yes

Programming Completed

Program Command Sequence* (Address/Command):

555H/AAH

2AAH/55H

555H/A0H

Program Address/Program Data

* : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 22 Embedded Program^TMAlgorithm

48

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

EMBEDDED ALGORITHMS

Start

Write Erase Command

Sequence

(See below)

Data Polling or Toggle Bit

Successfully Completed

Erasure Completed

Individual Sector/Multiple Sector*

Chip Erase Command Sequence*

(Address/Command):

Erase Command Sequence

(Address/Command):

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

Sector Address/30H

Additional sector

erase commands

are optional.

Sector Address/30H

* : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 23 Embedded Erase^TMAlgorithm

49

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Start

Read

(DQ 0 to DQ 7)

Addr. = VA

VA = Byte address for programming

= Any of the sector addresses within

the sector being erased during

sector erase or multiple sector

erases operation

= Any of the sector addresses within

the sector not being protected

during chip erase

Yes

DQ 7 = Data?

No

DQ 5 = 1?

Yes

Read

(DQ 0 to DQ 7)

Addr. = VA

Yes

DQ 7 = Data?

No

Fail

Pass

Note: DQ⁷is rechecked even if DQ⁵= “1” because DQ⁷may change simultaneously with DQ⁵.

Figure 24 Data Polling Algorithm

50

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Start

Read

(DQ ⁰to DQ 7)

Addr. = "H" or "L"

No

DQ 6 = Toggle

?

Yes

No

DQ 5 = 1?

Yes

Read

(DQ 0 to DQ 7)

Addr. = VA

No

DQ 6 = Toggle

?

Yes

Fail

Pass

Note: DQ⁶is rechecked even if DQ⁵= “1” because DQ⁶may stop toggling at the same time as

DQ⁵changing to “1” .

Figure 25 Toggle Bit Algorithm

51

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Start

Setup Sector Addr.

(A18, A17, A16, A15, A14, A13, A12)

PLSCNT = 1

OE

=

V ID, A 9

V IL, RESET

V IL, A 1

= V ID,

A ⁶

=

CE

= V IH

A 0

=

V IH

Activate WE Pulse

Time out 100 µs

Increment PLSCNT

WE = V IH, CE = OE = V IL

(A 9 should remain V ID

)

Read from Sector

(Addr. = SA, A 0

= V IL,

A ¹V IH, A6 = V IL)*

=

No

PLSCNT = 25?

Yes

Data = 01H?

Yes

Remove V ID from A 9

Write Reset Command

Protect Another Sector?

No

Device Failed

Remove V ID from A 9

Write Reset Command

Sector Protection

Completed

* : A^-1is V^ILon byte mode.

Figure 26 Sector Protection Algorithm

52

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

Start

RESET = VID

(Note 1)

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector

Unprotection Completed

(Note 2)

Notes: 1. All protected sectors are unprotected.

2. All previously protected sectors are protected once again.

Figure 27 Temporary Sector Unprotection Algorithm

53

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

FAST MODE ALGORITHM

Start

555H/AAH

2AAH/55H

Set Fast Mode

555H/20H

XXXH/A0H

Program Address/Program Data

Data Polling Device

No

In Fast Program

Verify Byte?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

XXXH/90H

XXXH/F0H

Reset Fast Mode

* : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 28 Embedded Program^TMAlgorithm for Fast Mode

54

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

FAST MODE ALGORITHM

Start

RESET = V^ID

Wait to 4 µs

Device is Operating in

Temporary Sector

Unprotection Mode

No

Extended Sector

Protection Entry?

Yes

To Setup Sector Protection

Write XXXH/60H

PLSCNT = 1

To Sector Protection

Write SPA/60H

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Time Out 150 µs

Increment PLSCNT

To Verify Sector Protection

Write SPA/40H

Setup Next Sector Address

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

Read from Sector Address

(A⁰= V^IL, A¹= V^IH, A⁶= V^IL)

No

Data = 01H?

Yes

PLSCNT = 25?

Yes

Remove V^IDfrom RESET

Write Reset Command

Protection Other Sector

?

No

Remove V^IDfrom RESET

Write Reset Command

Device Failed

Sector Protection

Completed

Figure 29 Extended Sector Protection Algorithm

55

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1.5

20

sec

Word Programming Time

Byte Programming Time

—

14.6

10.6

360

300

µs

Excludes system-level

overhead

Excludes system-level

overhead

Chip Programming Time

—

15.4

—

160

—

sec

Program/Erase Cycle

100,000

cycles

—

Note:

■ TSOP(I) PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Test Setup

Typ.

Max.

Unit

C^IN

Input Capacitance

V^IN= 0

V^OUT= 0

V^IN= 0

7.5

8

9.5

10

13

pF

C^OUT

Output Capacitance

Control Pin Capacitance

C^IN2

8

Note: Test conditions T^A= 25°C, f = 1.0 MHz

■ FBGA PIN CAPACITANCE

Parameter

Parameter Description

Symbol

Test Setup

Typ.

Max.

Unit

C^IN

Input Capacitance

V^IN= 0

V^OUT= 0

V^IN= 0

7.5

8

9.5

10

13

pF

C^OUT

C^IN2

Output Capacitance

Control Pin Capacitance

8

Note: Test conditions T^A= 25°C, f = 1.0 MHz

56

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29SL160

T

D

-10

PFTN

PACKAGE TYPE

PFTN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

PFTR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PBT = 48-Ball Fine pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE

T = Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

MBM29SL160

16Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory

1.8 V-only Read, Program, and Erase

57

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

■ PACKAGE DIMENSIONS

48-pin plastic TSOP(I)

* Resin Protrusin. (Each Side: 0.15 (.006)Max)

(FPT-48P-M19)

LEAD No.

1

48

Details of "A" part

INDEX

0.15(.006)

MAX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

20.00±0.20

(.787±.008)

* 12.00±0.20

(.472±.008)

* 18.40±0.20

(.724±.008)

11.50REF

(.460)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting height

0.50(.0197)

TYP

0.05(0.02)MIN

(STAND OFF)

0.10(.004)

0.15±0.05

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

Dimensions in mm (inches)

C

1996 FUJITSU LIMITED F48029S-2C-2

(Continued)

58

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

(Continued)

48-pin plastic TSOP(I)

* Resin Protrusin. (Each Side: 0.15 (.006)Max)

(FPT-48P-M20)

LEAD No.

1

48

Details of "A" part

0.15(.006)

MAX

INDEX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

0.15±0.10

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

0.50(.0197)

TYP

0.05(0.02)MIN

(STAND OFF)

0.10(.004)

1.10 –⁺0⁰.^.0¹5⁰

* 18.40±0.20

11.50(.460)REF

* 12.00±0.20(.472±.008)

.043 –⁺.^.0⁰0⁰2⁴

(Mounting height)

(.724±.008)

20.00±0.20

(.787±.008)

Dimensions in mm (inches)

C

1996 FUJITSU LIMITED F48030S-2C-2

(Continued)

59

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

(Continued)

48-pin plastic FBGA

Note: The actual shape of corners may differ from the dimension.

(BGA-48P-M13)

9.00±0.20(.354±.008)

1.05 ⁺–0⁰.^.1¹0⁵.041 –⁺.^.0⁰0⁰4⁶

(Mounting height)

5.60(.221)

0.80(.031)TYP

0.38±0.10(.015±.004)

(Stand off)

6

5

4

3

2

1

8.00±0.20

(.315±.008)

4.00(.157)

INDEX

H

G

F

E

D

C

B

A

C0.25(.010)

48-Ø0.45±0.10

(48-.018±.004)

M

Ø0.08(.003)

0.10(.004)

Dimensions in mm (inches)

C

1998 FUJITSU LIMITED B480013S-1C-1

60

MBM29SL160TD^-10/-12/MBM29SL160BD^-10/-12

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

Fax: 81(44) 754-3329

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and

Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

measurement equipment, personal or household devices, etc.).

CAUTION:

Fax: (408) 922-9179

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded

(such as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

http://www.fmap.com.sg/

F9910

FUJITSU LIMITED Printed in Japan


型号：	MBM29SL160BD-10PFTN
厂家：	FUJITSU
描述：	16M (2M x 8/1M x 16) BIT 16M （ 2M ×8 / 1M ×16 ）位闪存存储内存集成电路光电二极管
文件：	总61页 (文件大小：675K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29SL160BD-10PFTN [FUJITSU]

相关型号：

MBM29SL160BD-10PFTR

MBM29SL160BD-12

MBM29SL160BD-12PBT

MBM29SL160BD-12PFTN

MBM29SL160BD-12PFTR

MBM29SL160TD

MBM29SL160TD-10

MBM29SL160TD-10PBT

MBM29SL160TD-10PFTN

MBM29SL160TD-10PFTR

MBM29SL160TD-12

MBM29SL160TD-12PBT