MB90335_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

Preliminary

2004.01.09

16-bit Proprietary Microcontroller

CMOS

R

MB90335 Series

MB90337/F337/V330A

■ DESCRIPTION

The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral

devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but

also MiniHost operation. It is equipped with functions that are suitable for personal computer peripheral devices

such as displays and audio devices, and control of mobile devices that support USB communications. While

inheriting the AT architecture of the F²MC* family, the instruction set supports the C language and extended

addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial

collection of improved bit manipulation instructions. In addition, long word processing is now available by intro-

ducing a 32-bit accumulator.

* : F²MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

■ FEATURES

• Clock

• Built-in oscillation circuit and PLL clock frequency multiplication circuit

• Oscillation clock

The machine clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)

Clock for USB is 48 MHz

Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable

• Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock

24 MHz and at operating V^CC= 3.3 V)

• The maximum memory space:16 MB

• 24-bit addressing

• Bank addressing

(Continued)

■ PACKAGE

64-pin plastic LQFP

(FPT-64P-M09)

Preliminary

2004.01.09

MB90335 Series

(Continued)

• Instruction system

Data types: Bit, Byte, Word, Long word

Addressing mode (23 types)

Enhanced high-precision computing with 32-bit accumulator

Enhance Multiply/Divide instructions with sign and the RETI instruction

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Instruction set symmetry and barrel shift instructions

• Program Patch Function (2 address pointer)

• 4-byte instruction queue

• Interrupt function

• Priority levels are programmable

• 20 interrupts

• Data transfer function

• Expanded intelligent I/O service function (EI²OS) : Maximum of 16 channels

• µDMAC : Maximum 16 channels

• Low Power Consumption Mode

• Sleep mode (with the CPU operating clock stopped)

• Time - base timer mode (with the oscillator clock and time - base timer operating)

• Stop mode (with the oscillator clock stopped)

• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)

• Package

• LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch)

• Process : CMOS technology

• Operation guaranteed temperature: −40 °C to +85 °C (0 °C to +70 °C when USB is in use)

2

Preliminary

2004.01.09

MB90335 Series

■ INTERNAL PERIPHERAL FUNCTION (RESOURCE)

• I/O port: Max 45 ports

• Time-base timer : 1channel

• Watchdog timer : 1 channel

• 16-bit reload timer : 1 channel

• Multi-functional timer

• 8/16-bit PPG timer (8-bit × 4 channels or 16-bit × 2 channels) the period and duty of the output pulse can be

set by the program.

• 16-bit PWC timer : 1 channel

Timer function and pulse width measurement function

• UART : 2 channels

• Equipped with Full duplex double buffer with 8-bit lenghth

• Asynchronous transfer or clock-synchronous serial (I/O extended serial) transfer can be set.

• Extended I/O serial interface: 1 channel

• DTP/External interrupt circuit (8 channels)

• Activate the extended intelligent I/O service by external interrupt input

• Interrupt output by external interrupt input

• Delayed interrupt output module

• Output an interrupt request for task switching

• USB : 1 channel

• USB function (conform to USB 2.0 Full Speed)

• Supports for Full Speed/Endpoint are specifiable up to six.

• Dual port RAM (The FIFO mode is supported).

• Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible

• USB Mini Host function

• I²C Interface : 1 channel

• Supports Intel SM bus standards and Phillips I²C bus standards

• Two-wire data transfer protocol specification

• Master and slave transmission/reception

Note : I²C licenae :

Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use,

these components in an I²C system provided that the system conforms to the I²C Standard Specification as

defined by Phillips.

3

Preliminary

2004.01.09

MB90335 Series

■ PRODUCT LINEUP

1. MB90335 Series

Part number

MB90V330A

For evaluation

No

MB90F337

MB90337

Built-in Mask ROM

Type

Built-in FLASH MEMORY

ROM capacity

RAM capacity

64 Kbyte

4 Kbyte

28 Kbyte

Emulator-specific

power supply *

Used bit

Number of basic instructions : 351 instructions

Minimum instruction execu- : 41.6 ns / at oscillation of 6 MHz

tion time

Addressing type

(When 4 times is used : Machine clock of 24 MHz)

: 23 types

CPU functions

Program Patch Function

maximum memory space

: For two address pointers

: 16 Mbyte

Ports

I/O Ports(CMOS) 45 ports

Equipped with full-duplex double buffer

Clock synchronous or asynchronous operation selectable.

It can also be used for I/O serial.

UART

Built-in special baud-rate generator

Built-in 2 channels

16-bit reload timer operation

Built-in 1 channel

16-bit reload timer

8/16-bit PPG timer (8-bit mode × 4 channels, 16-bit mode × 2 channels)

16-bit PWC timer × 1 channel

Multi-functional timer

8 channels

DTP/External interrupt

I²C

Interrupt factor : “L”→“H” edge /“H”→“L” edge /“L” level /“H” level selectable

1 channel

Extended I/O serial interface 1 channel

1 channel

USB

USB function (conform to USB 2.0 Full Speed)

USB Mini-HOST function

Withstand voltage of 5 V

6 ports (Excluding VBUS and I/O for I²C)

Low Power Consumption

Mode

Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode

Process

CMOS

Operating voltage VCC

3.3 V ± 0.3 V (at maximum machine clock 24 MHz)

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-

01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.

■ PACKAGES AND PRODUCT MODELS

Package

FPT-64P-M09 (LQFP-0.65 mm)

PGA-299C-A01 (PGA)

MB90337

MB90F337

MB90V330A

×

: Yes × : No

Note : For detailed information on each package, see “■ PACKAGE DIMENSIONS”.

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Preliminary

2004.01.09

MB90335 Series

■ PIN ASSIGNMENT

(TOP VIEW)

VBUS

Vss

1

2

3

4

5

6

7

8

9

48 Vss

47 X1

DVM

DVP

Vcc

46 X0

45 P24/PPG0

44 P23

43 P22

42 P21

41 P20

40 P17

39 P16

38 P15

37 P14

36 P13

35 P12

34 P11

33 P10

Vss

HVM

HVP

Vcc

HCONX 10

P42/SIN0 11

P43/SOT0 12

P44/SCK0 13

P45/SIN1 14

P46/SOT1 15

P47/SCK1 16

(FPT-64P-M09)

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Preliminary

2004.01.09

MB90335 Series

■ PIN DESCRIPTION

Pin no.

Circuit

Status at

reset/

function

Pin name

Function

type*

QFPM09

It is a terminal which connects the oscillator.

When connecting an external clock, leave the X1 pin side uncon-

nected.

Oscillation

status

46 , 47

23

X0, X1

RST

A

F

Reset input External reset input pin.

General purpose input/output port.

The ports can be set to be added with a pull-up resistor (RD00 to

RD07 = 1) by the pull-up resistor setting register (RDR0). (When

the power output is set, it is invalid.)

25 to 32 P00 to P07

I

General purpose input/output port.

The ports can be set to be added with a pull-up resistor (RD10 to

RD17 = 1) by the pull-up resistor setting register (RDR1). (When

the power output is set, it is invalid.)

33 to 40 P10 to P17

41 to 44 P20 to P23

D

General purpose input/output port.

Functions as output pins of PPG timers ch0.

General purpose input/output port.

P24

45

PPG0

P25 to P27

51 to 53

D

PPG1 to

PPG3

Functions as output pins of PPG timers ch1 to ch3.

P40

TIN0

P41

General purpose input/output port.

62

63

11

12

13

14

15

16

H

Function as event input pin of 16-bit reload timer.

General purpose input/output port.

Port input

(High-Z)

TOT0

P42

Function as output pin of 16-bit reload timer.

General purpose input/output port.

SIN0

P43

Functions as a data input pin for UART ch0.

General purpose input/output port.

SOT0

P44

Functions as a data output pin for UART ch0.

General purpose input/output port.

SCK0

P45

Functions as a clock I/O pin for UART ch0.

General purpose input/output port.

SIN1

P46

Functions as a data input pin for UART ch1.

General purpose input/output port.

SOT1

P47

Functions as a data output pin for UART ch1.

General purpose input/output port.

SCK1

P50

Functions as a clock I/O pin for UART ch1.

General purpose input/output port.

50

64

K

P51

General purpose input/output port.

17, 18

24

P52, P53

P54

General purpose input/output port.

* : For circuit information, see “■ I/O CIRCUIT TYPE”.

(Continued)

6

Preliminary

2004.01.09

MB90335 Series

(Continued)

Pin no.

Status at

reset/

function

Circuit

type*

Pin name

Function

QFPM09

P60, P61

INT0, INT1

P62

General purpose input/output port. (withstand voltage of 5 V)

Functions as the input pin for external interrupt ch0 and ch1.

General purpose input/output port. (withstand voltage of 5 V)

Functions as the input pin for external interrupt ch2.

Data input pin for simple serial IO.

54, 55

C

56

57

58

59

INT2

SIN

P63

General purpose input/output port. (withstand voltage of 5 V)

Functions as the input pin for external interrupt ch3.

Data output pin for simple serial IO

INT3

SOT

C

P64

General purpose input/output port. (withstand voltage of 5 V)

Functions as the input pin for external interrupt ch4.

Clock I/O pin for simple serial IO.

INT4

SCK

Port input

(High-Z)

P65

General purpose input/output port. (withstand voltage of 5 V)

Functions as the input pin for external interrupt ch5.

Functions as the PWC input pin.

INT5

PWC

P66

General purpose input/output port.

INT6

Functions as the input pin for external interrupt ch6.

60

C

Functions as the input/output pin for I²C interface clock. The port

output must be placed in High-Z state during I²C interface

operation.

SCL0

P67

General purpose input/output port.

INT7

Functions as the input pin for external interrupt ch7.

Functions as the I²C interface data input/output pin. The port out-

put must be placed in High-Z state during I²C interface operation.

61

C

SDA0

1

3

VBUS

DVM

DVP

C

J

VBUS input Status detection pin of USB cable.

USB function D − pin.

4

J

USB function D + pin.

USB Mini Host D − pin.

USB Mini Host D + pin.

USB input

(SUSPEND)

7

HVM

HVP

J

8

J

10

21, 22

20

5

HCONX

MD1, MD0

MD2

Vcc

E

B

G

High output External pull-up resistor connection pin.

Mode input

Input pin for selecting operation mode.

Power supply pin.

9

Vcc

49

2

Vcc

Power

supply

Vss

Power supply pin (GND).

6

Vss

Power supply pin (GND).

19

48

Vss

* : For circuit information, see “■ I/O CIRCUIT TYPE”.

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Preliminary

2004.01.09

MB90335 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistance :

approx. 1 MΩ

• With standby control

X1

X0

Clock input

A

Standby control signal

• CMOS hysteresis input

B

C

Hysteresis input

• Hysteresis input

• Nch open drain output

Nch

Nout

Hysteresis input

Standby control signal

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Pch

Nch

Pout

Nout

Note : • The I/O ports and internal

resources share one output

buffer for their outputs.

• The I/O port and internal

resources share one input buffer

for their input.

D

Hysteresis input

Standby control signal

• CMOS output

Pch

Nch

Pout

Nout

E

• CMOS hysteresis input with pull-up

• Resistor approx. 50 kΩ

F

Hysteresis input

• CMOS hysteresis input with pull-down

• Resistor approx. 50 kΩ

• FLASH product is not provided with

pull-down resistor.

G

(Continued)

8

Preliminary

2004.01.09

MB90335 Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Open drain control

signal

Pch

Nch

Pout

Nout

With open drain control signal

H

Hysteresis input

Standby control signal

• CMOS output

• CMOS input

CTL

(With input interception function at

standby)

Programmable pull-up

Resistor approx. 50 kΩ

Pch

Nch

Pout

I

Nout

CMOS input

Standby control signal

D + input

• USB I/O pin

D-input

+

D

Differential input

−

D

Full D + output

J

Full D-output

Low D + output

Low D-output

Direction

Speed

• CMOS output

• CMOS input

(With input interception function at

standby)

Pch

Nch

Pout

Nout

K

CMOS input

Standby control signal

9

Preliminary

2004.01.09

MB90335 Series

■ HANDLING DEVICES

1. Preventing latchup and turning on power supply

Latchup may occur on CMOS IC under the following conditions:

1. If a voltage higher than V^CCor lower than VSS is applied to input and output pins.

2. A voltage higher than the rated voltage is applied between V^CCand VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using CMOSICs, take great care to prevent the occurrence of latchup.

2. Treatment of unused pins

Leaving unused input pins open may cause a malfunction. These pins must therefore be set to a pull-up or pull-

down state.

3. About the attention when the external clock is used

• Using external clock

X0

OPEN

X1

4. Treatment of power supply pins (V^CC/V^SS)

When the device is provided with multiple VCC and VSS pins, be sure to connect all of the power pins to the power

supply and ground outside the device to reduce latch-up and unwanted radiation, prevent the strobe signal from

malfunctioning due to a rise of grand level, and to follow the standards of total output current for device design

reasons. The power supply source should be connected to the VCC and VSS of this device at the lowest possible

impedance. It is also advisable to connect a bypass capacitor of approximately 0.1 µF between VCC and VSS near

this device.

5. About crystal oscillator circuit

Noise near the X0/X1 pin may cause the device to malfunction. When designing the artwork for a PC board

using the microcontroller, it is strongly advisable to place the X0/X1 and crystal (ceramic) oscillator, and the

bypass capacitor leading to the ground as close to one another as possible and prevent their writing patterns

from crossing other patterns as possible be cause stable operation can be expected with such a layout.

6. Caution on Operations during PLL Clock Mode

Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the

microcontroller may continue to operate at the free-running frequency of the PLL internal automatic oscillator

circuit.Performance of this operation, however, cannot be guaranteed.

10

Preliminary

2004.01.09

MB90335 Series

7. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage

operating range. For stabilization reference, the supply voltage should be controlled so that VCC ripple variations

(peak-to-peak values) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply

voltage and the transient regulation does not exceed

0.1 V/ms at temporary changes such as power supply switching.

8. Writing to flash memory

For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.

For normal writing to flash memory, always make sure that the operating voltage V^CCis between 3.0 V and 3.6 V.

11

Preliminary

2004.01.09

MB90335 Series

■ BLOCK DIAGRAM

X0, X1

RST

MD0 to MD2

F²MC-16LX

CPU

Clock control

circuit

Interrupt

controller

8/16-bit PPG

timer

ch0 to ch3*

PPG0 to PPG3

RAM

ROM

PWC

16-bit PWC

SIN0, SIN1

SOT0, SOT1

SCK0, SCK1

UART/SIO

ch0, ch1

SIN

SOT

SCK

SIO

SCL0

SDA0

I2C

µDMAC

16-bit reload

timer

TOT0

TIN0

DVP

DVM

HVP

USB

(Function)

(Mini-HOST)

HVM

HCONX

VBUS

External interrupt

INT0 to INT7

I/O port (port 0, 1, 2, 4, 5, 6)

P00

P07

P10

P17

P20

P27

P40

P47

P50

P54

P60

P67

* : Channel for use in 8-bit mode. Two channels (ch1, ch3) are used in 16-bit mode.

Note : I/O ports share pins with peripheral resources.

For details, see “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.

Note also that pins used for peripheral resources cannot serve as I/O ports.

12

Preliminary

2004.01.09

MB90335 Series

■ MEMORY MAP

Single chip mode (ROM mirror function)

MB90V330A

MB90F337

MB90337

FFFFFFH

FF0000H

FFFFFFH

ROM (FF bank)

FF0000H

00FFFFH

ROM area

(image of FF bank)

ROM area

(image of FF bank)

ROM area

(image of FF bank)

008000H

007FFFH

008000H

007FFFH

Peripheral area

007900H

007100H

RAM area

(28 Kbytes)

001100H

RAM area

(4 Kbytes)

RAM area

(4 Kbytes)

Register

000100H

0000FBH

000100H

0000FBH

Peripheral area

000000H

Memory Map of MB90335 Series

Notes : • WhentheROMmirrorfunctionregisterhasbeenset, themirrorimagedataathigheraddresses(“FF8000^H

to FFFFFF^H” ) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00.

• For setting the ROM mirror function, see “16. ROM mirror function select module” in “■ PERIPHERAL

RESOURCES”.

Reference : • The ROM mirror function is for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in

bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be

reproduced in bank 00.

• When the C compiler small model is used, the data table mirror image can be shown at “008000^Hto

00FFFF^H” by storing the data table at “FF8000H to FFFFFFH”.

Therefore, data tables in the ROM area can be referenced without declaring the far addressing with

the pointer.

13

Preliminary

2004.01.09

MB90335 Series

■ F²MC^-16L CPU PROGRAMMING MODEL

• Dedicated register

AH

AL

Accumulator

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

DPR

Direct page register

PCB

DTB

USB

SSB

ADB

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

8 bit

16 bit

32 bit

• General purpose registers

MSB

LSB

16 bit

000180^H+ RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

R1

R0

R2

R4

R6

RW4

RW5

RW6

RW7

RL2

RL3

R3

R5

R7

• Processor status

15

13 12

ILM

8 7

0

PS

RP

CCR

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Preliminary

2004.01.09

MB90335 Series

■ I/O MAP

Register

abbreviation

Read/

Write

Address

Register

Port 0 Data Register

Resource name

Initial Value

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

PDR0

PDR1

PDR2

R/W

Port 0

Port 1

Port 2

XXXXXXXXB

Port 1 Data Register

Port 2 Data Register

Prohibited

PDR4

PDR5

PDR6

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

R/W

Port 4

Port 5

Port 6

XXXXXXXXB

- - - XXXXXB

XXXXXXXXB

000007H

to

00000FH

000010^H

000011H

000012H

000013H

000014^H

000015H

000016H

DDR0

DDR1

DDR2

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

R/W

Port 0

Port 1

Port 2

0 0 0 0 0 0 0 0B

DDR4

DDR5

DDR6

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

R/W

Port 4

Port 5

Port 6

0 0 0 0 0 0 0 0B

- - - 0 0 0 0 0B

0 0 0 0 0 0 0 0B

000017H

to

00001AH

Port 4

(OD control)

00001BH

ODR4

Port 4 Output Pin Register

R/W

0 0 0 0 0 0 0 0B

00001CH

00001DH

00001EH

00001FH

000020H

000021H

RDR0

RDR1

Port 0 Pull-up Resistance Register

R/W

Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B

Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B

Prohibited

SMR0

SCR0

Serial Mode Register ch0

R/W

R

0 0 1 0 0 0 0 0B

0 0 0 0 0 1 0 0B

Serial Control Register ch0

Serial Input Data Register ch0

Serial Output Data Register ch0

Serial Status Register ch0

SIDR0

SODR0

SSR0

UART0

000022H

XXXXXXXX^B

W

000023^H

000024H

000025H

000026H

000027H

R/W

0 0 0 0 1 0 0 0B

UTRLR0

UTCR0

SMR1

SCR1

UART Prescaler Reload Register ch0

0 0 0 0 0 0 0 0B

0 0 0 0 - 0 0 0B

0 0 1 0 0 0 0 0B

0 0 0 0 0 1 0 0B

Communication

Prescaler(UART0)

UART Prescaler Control Register ch0 R/W

Serial Mode Register ch1

R/W

R

Serial Control Register ch1

Serial Input Data Register ch1

Serial Output Data Register ch1

Serial Status Register ch1

SIDR1

SODR1

SSR1

UART1

000028H

000029H

XXXXXXXX^B

W

R/W

0 0 0 0 1 0 0 0B

(Continued)

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Preliminary

2004.01.09

MB90335 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

00002A^H

00002BH

UTRLR1

UTCR1

UART Prescaler Reload Register ch1

UART Prescaler Control Register ch1

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 - 0 0 0B

Communication

Prescaler(UART1)

00002CH

to

Prohibited

00003BH

00003C^H

00003DH

00003EH

00003FH

ENIR

EIRR

Interrupt/DTP Enable Register

R/W

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

Interrupt/DTP source Register

DTP/External

interrupt

Request Level Setting Register Lower

Request Level Setting Register Higher

ELVR

000040H

to

Prohibited

000045H

000046^H

000047H

000048H

000049H

00004AH

00004B^H

00004CH

00004DH

00004E^H

PPGC0

PPGC1

PPGC2

PPGC3

PPG0 Operation Mode Control Register R/W

PPG1 Operation Mode Control Register R/W

PPG2 Operation Mode Control Register R/W

PPG3 Operation Mode Control Register R/W

PPG ch0

PPG ch1

PPG ch2

PPG ch3

0X0 0 0XX1B

0X0 0 0 0 0 1B

0X0 0 0XX1B

0X0 0 0 0 0 1B

Prohibited

PPG01

PPG23

PPG0 and PPG1 Output Control Register R/W

Prohibited

PPG ch0/1

PPG ch2/3

0 0 0 0 0 0XXB

0 0 0 0 0 0 XXB

PPG2 and PPG3 Output Control Register R/W

00004FH

to

Prohibited

000057H

000058^H

000059H

00005AH

XXXX0 0 0 0^B

0 0 0 0 0 0 1 0B

XXXXXXXXB

SMCS

Serial Mode Control Status Register

Serial Data Register

R/W

Extended Serial

I/O

SDR

R/W

Communication Prescaler Control

Register

Communication

Prescaler

00005BH

SDCR

0XXX0 0 0 0B

00005CH

00005DH

00005EH

00005FH

000060H

000061H

000062^H

000063H

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 XB

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

- - - - - - 0 0B

PWCSR

PWC Control Status Register

R/W

16-bit

PWC Timer

PWCR

DIVR

PWC Data Buffer Register

PWC Dividing Ratio Register

R/W

Prohibited

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0B

XXXXXXXXB

(Continued)

TMCSR0

Timer control status Register

R/W

TMR0

TMRLR0

TMR0

16-bit Timer Register Lower

16-bit Reload Register Lower

16-bit Timer Register Higher

16-bit Reload Register Higher

R

W

R

16-bit Reload

Timer

000064H

000065H

TMRLR0

W

16

Preliminary

2004.01.09

MB90335 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name Initial Value

000066^H

to

Prohibited

00006EH

ROM Mirror

Function

Selection Module

ROM Mirroring Function Selection

Register

00006F^H

ROMM

W

- - - - - - 1 1B

000070H

000071H

000072H

000073H

000074H

IBSR0

IBCR0

ICCR0

IADR0

IDAR0

I²C Bus Status Register

I²C Bus Control Register

I²C Bus Clock Selection Register

I²C Bus Address Register

I²C Bus Data Register

R

0 0 0 0 0 0 0 0B

R/W

R/W I²C Bus Interface XX 0 XXXXXB

R/W

XXXXXXXXB

000075H

to

Prohibited

00009AH

DMA Descriptor Channel Specification

Register

00009B^H

DCSR

R/W

0 0 0 0 0 0 0 0B

µDMAC

00009CH

00009DH

DSRL

DSRH

DMA Status Register Lower

DMA Status Register Higher

R/W

0 0 0 0 0 0 0 0B

Program Address Detection Control

Status Register

Address Match

Detection

00009EH

00009FH

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0B

Delayed Interrupt Source generate/

release Register

R/W Delayed Interrupt - - - - - - - 0B

Low Power

0000A0H

LPMCR

CKSCR

Low Power Consumption Mode Register

R/W

Consumption

control circuit

0 0 0 1 1 0 0 0B

1 1 1 1 1 1 0 0B

0000A1H

0000A2H

0000A3^H

0000A4H

Clock Selection Register

Prohibited

Clock

DSSR

DMA Stop Status Register

R/W

µDMAC

0 0 0 0 0 0 0 0B

0000A5H

to

Prohibited

0000A7H

0000A8^H

0000A9H

0000AAH

0000AB^H

0000ACH

0000ADH

WDTC

TBTC

Watchdog Control Register

R/W Watchdog Timer X - XXX 1 1 1B

R/W Time-base Timer 1 - - 0 0 1 0 0B

Time-base Timer Control Register

Prohibited

DERL

DERH

DMA Enable Register Lower

DMA Enable Register Higher

R/W

0 0 0 0 0 0 0 0B

µDMAC

FLASH

MEMORY I/F

0000AEH

0000AFH

FMCR

Flash Memory Control Status Register

Prohibited

R/W

0 0 0 X 0 0 0 0B

(Continued)

17

Preliminary

2004.01.09

MB90335 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

0000B0^H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

0000C0H

0000C1H

0000C2H

0000C3H

0000C4H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

HCNT0

HCNT1

HIRQ

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

USB Host Control Register 0

USB Host Control Register 1

USB Host Interruption Register

USB Host Error Status Register

USB Host State Status Register

R/W

0 0 0 0 0 1 1 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 1B

0 0 0 0 0 0 0 0B

0 0 0 0 0 0 1 1B

XX 0 1 0 0 1 0B

Interrupt

Controller

HERR

HSTATE

USB SOF Interrupt FRAME compare

Register

0000C5H

HFCOMP

R/W

0 0 0 0 0 0 0 0B

0000C6H

0000C7H

0000C8H

0000C9H

0000CAH

0000CBH

0000CCH

0000CDH

0000CEH

0000CFH

0000D0^H

0000D1H

USB Retry Timer Setting Register 0

USB Retry Timer Setting Register 1

USB Retry Timer Setting Register 2

USB Host Address Register

USB EOF Setting Register 0

USB EOF Setting Register 1

USB FRAME Setting Register 0

USB FRAME Setting Register 1

USB Host Token End Point Register

Prohibited

R/W

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

XXXXXX 0 0B

X 0 0 0 0 0 0 0B

0 0 0 0 0 0 0 0B

XX 0 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

XXXXX 0 0 0B

0 0 0 0 0 0 0 0B

USB Mini HOST

HRTIMER

HADR

HEOF

HFRAME

HTOKEN

UDCC

UDC Control Register

R/W

USB function

1 0 1 0 0 0 0 0B

(Continued)

Prohibited

18

Preliminary

2004.01.09

MB90335 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

0000D2^H

0000D3H

0000D4H

0000D5H

0000D6H

0000D7H

0000D8H

0000D9H

0000DAH

0000DBH

0000DCH

0000DDH

0000DEH

0000DFH

0000E0H

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

0000E6H

0000E7H

0000E8H

0000E9H

0000EAH

0000EBH

0000ECH

0000EDH

0000EEH

0000EFH

0000F0H

0000F1H

0000F2H

0000F3H

0000F4H

0000F5H

0000F6H

0000F7H

0000F8H

0000F9H

R/W

R

X 1 0 0 0 0 0 0^B

XXXX 0 0 0 XB

0 0 0 0 0 0 0 0^B

0 1 1 0 0 0 0 1B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0B

XXXXXXXX^B

1 0 XXX 1 XXB

XXXXXXXX^B

1 0 0 XX 0 0 XB

XXXXXXXX^B

1 0 0 0 0 0 0 XB

XXXXXXXX^B

1 0 0 0 0 0 0 XB

XXXXXXXX^B

1 0 0 0 0 0 0 XB

XXXXXXXX^B

1 0 0 0 0 0 0 XB

XXXXXXXX^B

1 0 0 0 0 0 0 XB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

(Continued)

EP0C

EP1C

EP2C

EP3C

EP4C

EP5C

TMSP

EP0 Control Register

EP1 Control Register

EP2 Control Register

EP3 Control Register

EP4 Control Register

EP5 Control Register

Time Stamp Register

R/W

R

UDCS

UDCIE

UDC Status Register

Interrupt Enable Register

EP0IS

EP0OS

EP1S

EP0I Status Register

EP0O Status Register

EP1 Status Register

EP2 Status Register

EP3 Status Register

EP4 Status Register

EP5 Status Register

EP0 Data Register

EP1 Data Register

EP2 Data Register

EP3 Data Register

EP4 Data Register

USB Function

R/W

R

EP2S

R/W

R

EP3S

R/W

R

EP4S

R/W

R

EP5S

R/W

EP0DT

EP1DT

EP2DT

EP3DT

EP4DT

19

Preliminary

2004.01.09

MB90335 Series

Register

Address

Read/

Write

Register

EP5 Data Register

Resource name

Initial Value

abbreviation

0000FA^H

R/W

XXXXXXXXB

EP5DT

USB Function

0000FBH

0000FCH

to

0000FFH

Prohibited

RAM Area

000100H

to

001100H

Program Address Detection Register

ch0 Lower

001FF0H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

R/W

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

Program Address Detection Register

ch0 Middle

PADR0

PADR1

Program Address Detection Register

ch0 Higher

Address Match

Detection

Program Address Detection Register

ch1 Lower

Program Address Detection Register

ch1 Middle

Program Address Detection Register

ch1 Higher

007900H

007901H

007902H

007903H

007904H

007905H

007906H

007907H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PPG Reload Register Lower ch0

PPG Reload Register Higher ch0

PPG Reload Register Lower ch1

PPG Reload Register Higher ch1

PPG Reload Register Lower ch2

PPG Reload Register Higher ch2

PPG Reload Register Lower ch3

PPG Reload Register Higher ch3

R/W

XXXXXXXXB

PPG ch0

PPG ch1

PPG ch2

PPG ch3

007908H

to

Prohibited

00790BH

00790CH

00790DH

00790EH

FWR0

FWR1

SSR0

Flash Program Control Register 0

Flash Program Control Register 1

Sector Conversion Setting Register

R/W

Flash

0 0 0 0 0 0 0 0B

0 0 XXXXX0B

00790FH

to

Prohibited

00791FH

(Continued)

20

Preliminary

2004.01.09

MB90335 Series

(Continued)

Register

abbreviation

Read/

Write

Address

Register

Resource name Initial Value

007920^H

007921H

007922H

007923H

DBAPL

DBAPM

DBAPH

DMACS

DMA Buffer Address Pointer Lower 8-bit R/W

DMA Buffer Address Pointer Middle 8-bit R/W

DMA Buffer Address Pointer Higher 8-bit R/W

XXXXXXXXB

DMA Control Register

R/W

DMA I/O Register Address Pointer Lower

8-bit

µDMAC

007924H

007925H

DIOAL

DIOAH

R/W

XXXXXXXXB

DMA I/O Register Address Pointer

Higher 8-bit

R/W

007926H

007927H

DDCTL

DDCTH

DMA Data Counter Lower 8-bit

DMA Data Counter Higher 8-bit

R/W

XXXXXXXXB

007928H

to

Prohibited

007FFFH

• Explanation on read/write

R/W Read and write enabled

R

Read only

Write only

W

• Explanation of initial values

0

1

X

-

: Initial Value is “0”.

: Initial Value is “1”.

: Initial Value is undefined.

: Initial Value is undefined (None).

Note : No IO instruction can be used for registers located between 007900^Hto 007FFFH.

21

Preliminary

2004.01.09

MB90335 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interrupt control

Interrupt vector

EI²OS

support

Priori-

register

Interrupt source

µDMAC

ty

Address

ICR Address

Number*

Reset

×

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

#39

#40

#41

#42

08^HFFFFDCH

09^HFFFFD8H

0A^HFFFFD4H

0B^HFFFFD0H

0CH FFFFCCH

0DH FFFFC8H

0EH FFFFC4H

0FH FFFFC0H

10H FFFFBCH

High

INT 9 instruction

×

Exceptional treatment

×

USB Function1

0, 1

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

ICR06 0000B6H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

ICR13 0000BDH

ICR14 0000BEH

ICR15 0000BFH

USB Function2

2 to 6

USB Function3

×

USB Function4

USB Mini-HOST1

USB Mini-HOST2

I²C ch0

11H

12H

13H

FFFFB8H

FFFFB4H

FFFFB0H

DTP/External interrupt ch0/1

No

DTP/External interrupt ch2/3

×

14H FFFFACH

No

15H

16H

17H

FFFFA8H

FFFFA4H

FFFFA0H

DTP/External interrupt ch4/5

×

14

×

PWC/Reload timer ch0

DTP/External interrupt ch6/7

18H FFFF9CH

No

19H

1AH

1BH

FFFF98H

FFFF94H

FFFF90H

No

1CH FFFF8CH

1DH FFFF88H

No

PPG ch0/1

×

1EH

1FH

FFFF84H

FFFF80H

No

PPG ch2/3

20H FFFF7CH

No

21H

22H

23H

FFFF78H

FFFF74H

FFFF70H

No

24H FFFF6CH

UART (Send completed) ch0/ch1

Extended serial I/O

UART(Reception completed) ch0/ch1

Time-base timer

13

9

25H

26H

27H

FFFF68H

FFFF64H

FFFF60H

×

12

×

28H FFFF5CH

Flash memory status

Delayed interrupt output module

×

29H

2AH

FFFF58H

FFFF54H

×

Low

22

Preliminary

2004.01.09

MB90335 Series

: Available. EI²OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.

There is a stop demand.)

: Available (The interrupt request flag is cleared by the interrupt clear signal).

: Available when any interrupt source sharing ICR is not used.

× : Unavailable

• If the same interrupt control register (ICR) has two interrupt factors and the use of the EI²OS is permitted, the

EI²OS is activated when either of the factors is detected. As any interrupt other than the activation factor is

masked while the EI²OS is running, it is recommended that you should mask either of the interrupt requests

when using the EI²OS.

• The interrupt flag is cleared by the EI²OS interrupt clear signal for the resource that has two interrupt factors

in the same interrupt control register (ICR).

Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are

cleared by the µDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the

DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to " 0 " in the

appropriate resource, and take measures by software polling.

■ USB INTERRUPT FACTOR CONTENTS

USB interrupt factor

USB function 1

Details

End Point0-IN, EndPoint 0-OUT

USB function 2

End Point 1-5

USB function 3

VOFF, VON, SUSP, SOF, BRST, WKOP, COHF

SPIT

USB function 4

USB Mini-HOST1

USB Mini-HOST2

DIRQ, CHHIRQ, URIRQ, RWKIRQ

SOFIRQ, CMPIRQ

23

Preliminary

2004.01.09

MB90335 Series

■ PERIPHERAL RESOURCES

1. I/O port

• The I/O ports are used as general-purpose input/output ports (parallel I/O ports). MB90335 series model is

provided with 6 ports (45 inputs) . The ports function as input/output pins for peripheral functions also.

• An I/O port, using port data register (PDR) , outputs the output data to I/O pin and input a signal input to I/O

port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.

• The following table lists the I/O ports and the peripheral functions with which they share pins.

Port pin name Pin Name (Peripheral)

Peripheral Function that Shares Pin

Port 0

Port 1

P00 to P07

P10 to P17

P20 to P23

Port 2

P24 to P27

P40, P41

PPG0 to PPG3

TIN0, TOT0

8/16 bit PPG timer 0, 1

16-bit reload timer

Port 4

Port 5

SIN0, SOT0, SCK0,

SIN1, SOT1, SCK1

P42 to P47

UART0, 1

P50 to P54

P60, P61

INT0, INT1

External interrupt

INT2 to INT4,

SIN, SOT, SCK

P62 to P64

External interrupt, serial IO

External interrupt, PWC

Port 6

P65

INT5, PWC

P66, P67

INT6, INT7, SCL0, SDA0 External interrupt, I²C

24

Preliminary

2004.01.09

MB90335 Series

• Register list (port data register)

PDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 000000^H

XXXXXXXXB R/W*

P07

P06

P05

P04

P03

P02

P01

P00

PDR1

15

14

13

12

11

10

9

8

Address : 000001^H

P17

P16

P15

P14

P13

P12

P11

P10

PDR2

7

6

5

4

3

2

1

0

Address : 000002^H

P27

P26

P25

P24

P23

P22

P21

P20

PDR4

7

6

5

4

3

2

1

0

Address : 000004^H

P47

P46

P45

P44

P43

P42

P41

P40

PDR5

15

14

13

12

11

10

9

8

Address : 000005^H

- - - XXXXXB

R/W*

P54

P53

P52

P51

P50

PDR6

7

6

5

4

3

2

1

0

Address : 000006H

XXXXXXXXB R/W*

P67

P66

P65

P64

P63

P62

P61

P60

* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows:

• Input mode

Read : The level at the relevant pin is read.

Write : Data is written to the output latch.

• Output mode

Read : The data register latch value is read.

Write : Data is output to the relevant pin.

25

Preliminary

2004.01.09

MB90335 Series

• Register list (port direction register)

DDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 000010^H

00000000B

- - - 00000B

00000000B

R/W

D07

D06

D05

D04

D03

D02

D01

D 00

DDR1

15

14

13

12

11

10

9

8

Address : 000011^H

R/W

D17

D16

D15

D14

D13

D12

D11

D10

DDR2

7

6

5

4

3

2

1

0

Address : 000012^H

D27

D26

D25

D24

D23

D22

D21

D20

DDR4

7

6

5

4

3

2

1

0

Address : 000014^H

D47

D46

D45

D44

D43

D42

D41

D40

DDR5

15

14

13

12

11

10

9

8

Address : 000015^H

D54

D53

D52

D51

D50

DDR6

7

6

5

4

3

2

1

0

Address : 000016^H

D67

D66

D65

D64

D63

D62

D61

D60

•

When each pin is serving as a port, the corresponding pin is controlled as follows:

0 : Input mode

1 : Output mode

This bit becomes 0 after a reset.

Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits

manipulated by the instruction are set to prescribed values but those other bits in output registers which

have been set for input are rewritten to the current input values of the pins. When switching a pin from input

port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for

output.

• Register list (Port pull-up register)

RDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001C^H

00000000B

R/W

RD07

RD06

RD05

RD04

RD03

RD02

RD01

RD00

RDR1

15

14

13

12

11

10

9

8

Address : 00001D^H

00000000B

R/W

RD17

RD16

RD15

RD14

RD13

RD12

RD11

RD10

Controls the pull-up resistor in input mode.

0 : Without pull-up resistor in input mode.

1 : With Pull-up resistor in input mode.

Meaningless in output mode (without pull-up resistor) ./ The input/output register is decided by the setting of the

direction register (DDR) .

No pull-up resistor is used in stop mode (SPL = 1).

26

Preliminary

2004.01.09

MB90335 Series

• Register list (output pin register)

ODR4

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001BH

00000000B

R/W

OD47

OD46

OD45

OD44

OD43

OD42

OD41

OD40

Controls open-drain output in output mode.

0 : Serves as a standard output port in output mode.

1 : Serves as an open-drain output port in output mode.

Meaningless in input mode. (output High-Z) / The input/output register is decided by the setting of the direction

register (DDR) .

• Block diagram of port 0 pin and port1 pin

Pull-up resistor

setting register

(RDRx)

Built-in pull-up

resistor

PDRx read

Input

buffer

Port data

register

(PDRx)

I/O

decision circuit

Port

Output

buffer

PDRx

Write

Port direction

register

Standby control (LPMCR : SPL = “1”)

(DDRx)

• Block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin

Resource input

PDRx read

input

buffer

Port data

I/O

register

decision circuit

(PDRx)

Output

buffer

Port

PDRx

write

Port direction

register

(DDRx)

Standby control (LPMCR : SPL = “1”)

Resource output control signal

Release output

27

Preliminary

2004.01.09

MB90335 Series

2. Time-base timer

• The time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization

with the main clock (2 cycles of the oscillation clock HCLK).

• Four different time intervals can be selected, for each of which an interrupt request can be generated.

• Operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and

watchdog timer.

• Interval time of time-base timer

Internal count clock cycle

Interval time

2¹²/HCLK (Approx. 0.68 ms)

2¹⁴/HCLK (Approx. 2.7 ms)

2¹⁶/HCLK (Approx. 10.9 ms)

2¹⁹/HCLK (Approx. 87.4 ms)

2/HCLK (0.33 µs)

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

• Clock cycles supplied from time-base timer

Where to supply clock

Clock cycle

2¹³/HCLK (Approx. 1.36 ms)

2¹⁵/HCLK (Approx. 5.46 ms)

2¹⁷/HCLK (Approx. 21.84 ms)

2¹²/HCLK (Approx. 0.68 ms)

2¹⁴/HCLK (Approx. 2.7 ms)

2¹⁶/HCLK (Approx. 10.9 ms)

2¹⁹/HCLK (Approx. 87.4 ms)

Oscillation stabilization wait of

main clock

Watch dog timer

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

• Register list

Time-base timer control register (TBTC)

Initial Value

1--00100B

15

14

13

12

11

10

9

8

Address: 0000A9H

RESV

TBIE

TBOF

TBR

TBC1

TBC0

( R/W )

(

)

(

)

( R/W ) ( R/W )

( W )

( R/W ) ( R/W )

Note : For the conditions for clearing the time-base timer, refer to the chapter for the time-base timer in the hardware

manual.

28

Preliminary

2004.01.09

MB90335 Series

• Block Diagram

To

watchdog

timer

To PPG timer

Time-base timer counter

Dividing HCLK by 2

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

OF

Power-on reset

To clock controller

oscillation stabilizing

wait time selector

Stop mode start

Counter

clear control

circuit

CKSCR : MCS = 1→0*¹

Interval timer selector

TBOF clear

TBOF

set

Time-base timer control register (TBTC)

Time-base timer interrupt signal

RESV

TBIE TBOF TBR TBC1 TBC0

:Unused

OF :Overflow

HCLK :Oscillation clock

*1 :Switching the machine clock from main clock to PLL clock

Actual interrupt request number of time-base timer is as follows:

Interrupt request number:#40 (28^H)

29

Preliminary

2004.01.09

MB90335 Series

3. Watchdog timer

• The watchdog timer is a timer counter prepared in case programs run out of control.

• The watchdog timer is a 2-bit counter using the time-base timer as the count clock.

• When started, the watchdog timer resets the CPU if it is not cleared before the two-bit counter overflows.

• Interval time of watchdog timer

HCLK: Oscillation clock (6 MHz)

Min

Max

Clock cycle

Approx. 2.39 ms

Approx. 9.56 ms

Approx. 38.23 ms

Approx. 305.83 ms

Approx. 3.07 ms

Approx. 12.29 ms

Approx. 49.15 ms

Approx. 393.22 ms

2

¹⁴± 2¹¹/ HCLK

¹⁶± 2¹³/ HCLK

¹⁸± 2¹⁵/ HCLK

²¹± 2¹⁸/ HCLK

Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.

• The watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer. When

the device is operating with HCLK, therefore, clearing the time-base timer lengthens the watchdog reset

generation time interval.

• Event that stop the watchdog timer

1 : Stop due to a Power-on reset

2 : watchdog reset

• Clear factor of watch dog timer

1 : External reset input by RST pin

2 : Writing “0” to the software reset bit

3 : Writing “0” to the watchdog control bit (second and subsequent times)

4 : Transition to sleep mode (Clearing the watchdog timer, and suspend counting)

5 : Transition to time-base timer mode (Clearing the watchdog timer, and suspend counting)

6 : Transition to stop mode (Clearing the watchdog timer, and suspend counting)

• Register list

Watchdog timer control register (WDTC)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000A8^H

X-XXX111B

PONR

WRST

ERST

SRST

WTE

WT1

WT0

( R )

(

)

( R )

( W )

30

Preliminary

2004.01.09

MB90335 Series

• Block Diagram

Watchdog timer control register (WDTC)

PONR

WRST ERST SRST WTE WT1 WT0

2

Timer-base timer mode start

Sleep mode start

Watchdog timer

CLR and

start

CLR

To

internal

reset

generation

circuit

watchdog timer

reset

generation

circuit

Count clock

selector

Counter

clear control

circuit

2-bit

counter

Stop mode start

CLR

4

Clear

Time-base timer counter

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

Dividing HCLK by 2

HCLK: Oscillation clock

31

Preliminary

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MB90335 Series

4. 16 - bit Reload Timer

The 16-bit reload timer has the internal clock mode to be decrement in synchronization with three different

internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input

to the external pin. Either can be selected. This timer defines when the count value changes from 0000H to

FFFFH as an underflow. The timer therefore causes an underflow when the count reaches [reload register

setting +1]. Either mode can be selected for the count operation from the reload mode which repeats the count

by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count

at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to

correspond to the DTC.

• Register list

• Timer control status register

Timer control status register (Higher) (TMCSR0)

Initial Value

15

14

13

12

11

10

9

8

Address : 000063^H

XXXX0000B

CSL1

CSL0

MOD2 MOD1

(

)

(

)

(

)

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W )

Timer control status register (Lower) (TMCSR0)

Initial Value

00000000B

7

6

5

4

RELD

3

2

1

0

Address : 000062^H

MOD0 OUTE OUTL

INTE

UF

CNTE

TRG

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

• 16-bit timer register/16-bit reload register

TMR0/TMRLR0 (Higher)

Initial Value

15

14

13

12

11

10

9

8

Address : 000065^H

XXXXXXXXB

D15

D14

D13

D12

D11

D10

D09

D08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

TMR0/TMRLR0 (Lower)

Address : 000064H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

D07

D06

D05

D04

D03

D02

D01

D00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

32

Preliminary

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MB90335 Series

• Block Diagram

Internal data bus

TMRLR0

16-bit reload register

Reload

Reload signal

control circuit

TMR0

2

UF

16-bit timer register

CLK

Count clock generation circuit

Gate

input

Valid

clock

decision

circuit

Wait signal

3

Machine

clock φ

Prescaler

Clear

Trriger

Internal

clock

Output control circuit

CLK

Output signal

generation

circuit

Input

control

circuit

Clock

selector

EN

TOT0

TIN0

External clock

3

2

Select

signal

Operating

Control

circuit

Select

function

CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR0)

Interrupt

requestoutput

#23 (17^H)*1

*1 : Interrupt number

*2 : Underflow

33

Preliminary

2004.01.09

MB90335 Series

5. Multifunction timer

• The multifunction timer can be used for waveform output, input pulse width measurement, and external clock

cycle measurement.

• Configuration of a multi-functional timer

8/16 bit PPG timer

16 bit PWC timer

8 bit × 4 ch

(16 bit × 2 ch)

1 ch

• 8/16 bit PPG timer (8 bit : 4 channels, 16 bit : 2 channels)

8/16 bit PPG timer consists of a 8 bit down counter (PCNT) , PPG control register (PPGC0 to PPGC3) , PPG

clock control register (PCS01, PCS23) and PPG reload register (PRLL0 to PRLL3, PRLH0 to PRLH3) .

When used as an 8/16 bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an

arbitrary duty ratio at an arbitrary frequency.

• 8 bit PPG mode

Each channel operates as an independent 8 bit PPG.

• 8 bit prescaler + 8 bit PPG mode

Operates as an arbitrary-cycle 8 bit PPG with ch0 (ch2) operating as an 8 bit prescaler and ch2 (ch3) counted

by the borrow output of ch0 (ch2).

• 16 bit PPG mode

Operates as a 16 bit PPG with ch0 (ch2) and ch1 (ch3) connected.

• PPG Operation

The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of

pulse waveform) at an arbitrary frequency. Can also be used as a D/A converter by an external circuit.

34

Preliminary

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MB90335 Series

• Register list

PPG operation mode control register

(PPGC1/PPGC3)

Initial Value

15

14

13

12

11

10

9

8

000047^H

000049H

0X000001B

Reserved

Address :

PEN1

( R/W )

PE10

PIE1

PUF1

MD1

MD0

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(PPGC0/PPGC2)

000046H

Initial Value

0X000XX1B

7

6

5

4

3

2

1

0

Address :

Reserved

PEN0

( R/W )

PE0O

PIE0

PUF0

000048H

( R/W ) ( R/W ) ( R/W )

(

)

(

)

( R/W )

PPG output control register (PPG01/PPG23)

Initial Value

000000XXB

7

6

5

4

3

2

1

0

00004CH

00004EH

Reserved

Address :

PCS2

PCS1

PCS0

PCM2

PCM1 PCM0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PPG reload register

(PRLH0 to PRLH3)

007901^H

Initial Value

15

14

13

12

11

10

9

8

007903H

007905H

007907H

XXXXXXXX^B

D15

D14

D13

D12

D11

D10

D09

D08

Address :

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(PRLL0 to PRLL3)

007900^H

Initial Value

7

6

5

4

3

2

1

0

007902H

007904H

007906H

XXXXXXXX^B

Address :

D07

D06

D05

D04

D03

D02

D01

D00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

35

Preliminary

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MB90335 Series

• 8 bit PPG ch0/2 block diagram

Peripheral clock × 16

PPG 0/2 output enable

PPG 0/2 output latch

Peripheral clock × 8

Peripheral clock × 4

Peripheral clock × 2

Peripheral clock

PPG0/2

A/D converter

PEN0

S

PCNT

(down counter)

To interrupt

#30 (1E^H)*

#32 (20^H)*

R Q

IRQ

Count clock

selector

ch1/3/5 borrow

L/H selector

Timebase counter

output main clock × 512

PUF0

PIE0

L/H selector

PRLL

PRLHB

PPGC0

(operation mode control)

PRLL

L data bus

H data bus

* : Interrupt number

36

Preliminary

2004.01.09

MB90335 Series

• 8 bit PPG ch1/3 block diagram

Peripheral clock × 16

PPG 1/3 output enable

PPG 1/3 output latch

Peripheral clock × 8

Peripheral clock × 4

Peripheral clock × 2

Peripheral clock

PPG1/3

PEN1

S

R

PCNT0

(down counter)

To interrupt

#30 (1E^H)*

#32 (20H)*

Q

IRQ

Count clock

selector

L/H selector

Timebase counter

output main clock × 512

PUF1

PIE1

L/H selector

PRLL

PRLHB

PPGC0

(operation mode control)

PRLL

L data bus

H data bus

* : Interrupt number

37

Preliminary

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MB90335 Series

• PWC timer

The PWC timer is a 16 bit multifunction up-count timer capable of measuring the input signal pulse width.

• Register list

PWC control status register (PWCSR)

Initial Value

15

14

13

12

11

10

9

8

Address : 00005D^H

0000000XB

Reserved

STRT

STOP

EDIR

EDIE

OVIR

OVIE

ERR

( R/W ) ( R/W )

( R )

( R/W ) ( R/W ) ( R/W )

( R )

1

( R/W )

0

Initial Value

00000000B

7

6

5

4

3

2

Address : 00005C^H

CKS1

CKS0

PIS1

PIS0

S/C

MOD2 MOD1 MOD0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PWC data buffer register (PWCR)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00005FH

D15

D14

D13

D12

D11

D10

D9

D8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00005EH

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Ratio of dividing frequency control register (DIVR)

Initial Value

7

6

5

4

3

2

1

0

Address : 000060^H

------00B

DIV1

DIV0

(

)

(

)

(

)

(

)

(

)

(

)

( R/W ) ( R/W )

38

Preliminary

2004.01.09

MB90335 Series

• Block Diagram

PWCR read

Error

detection

ERR

PWCR

16

Internal clock

(Machine clock/4)

Reload

Data transfer

Over-

16

2²

flow

Clock

devider

16 bit up-count timer

2³

CKS1/CKS0

Timer

clear

Divider

clear

Control circuit

Count enable

Start edge

selection

Measurement

end edge

selection

Input

waveform

comparator

Divider ON/OFF

starting edge

Edge

detection

PWC

Measurement

termination edge

Measurement

termination interrupt

request

PIS0/PIS1

8-bit

divider

Overflow interrupt

request

CKS0/CKS1

ERR

15

Divide ratio

select

PWCSR

2

DIVR

39

Preliminary

2004.01.09

MB90335 Series

6. UART

Overview of UART

• UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop syn-

chronization) communications with external devices.

• It supports bi-directional communication (normal mode) and master/slave communication (multi-processor

mode: supported on master side only).

• An interrupt can be generated upon completion of reception, detection of a reception errror, or upon completion

of transmission. EI²OS is supported also.

• UART functions

UART, or a generic serial data communication interface that sends and receives serial data to and from other

CPU and peripherals, has the functions listed in following.

Function

Data buffer

Full-duplex double-buffered

• Clock synchronous (without start/stop bit)

• Clock asynchronous (start-stop synchronous)

Transmission mode

• Special-purpose baud-rate generator

Baud rate

It is optional from eight kinds.

• Baud rate by external clock (clock of SCK0/SCK1 terminal input)

• 8 bits or 7 bits (in the asynchronous normal mode only)

• 1 to 8 bits (in the synchronous mode only)

Data length

Signaling system

Non Return to Zero (NRZ) system

• Framing error

Reception error detection

• Overrun error

• Parity error (Not supported in operation mode 1)

• Receive interrupt (reception completed, reception error detected)

• Transmission interrupt (transmission completed)

• Both the transmission and reception support EI²OS.

Interrupt request

Master/slave type

communication function Capable of 1 (master) to n (slaves) communication (available just as master)

(multi processor mode)

Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.

UART operation modes

Data length

Operation mode

Synchronization

Stop bit length

Without parity

With parity

0

1

2

Normal mode

7 bits or 8 bits

Asynchronous

Synchronous

1 bit or 2 bits *²

No

Multi processor mode

Normal mode

8 + 1 *¹

8

: Setting disabled

*1 : + 1 is an address/data setting bit (A/D) which is used for communication control.

*2 : Only one bit can be detected as a stop bit at reception.

40

Preliminary

2004.01.09

MB90335 Series

• Register list

Serial mode register (SMR0, SMR1)

Initial Value

7

6

5

4

3

2

1

0

000020^H

000026H

Address :

00100000B

M2L0

MD1

MD0

SCKL

M2L2

M2L1

SCKE

SOE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Serial control register (SCR0, SCR1)

Initial Value

00000100B

15

14

P

13

12

11

10

9

8

000021H

Address :

PEN

SBL

CL

A/D

REC

RXE

TXE

000027H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( W )

( R/W ) ( R/W )

Serial input/output register (SIDR0, SIDR1 / SODR0, SODR1)

Initial Value

7

6

5

4

3

2

1

0

000022H

000028H

Address :

XXXXXXXX^B

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Serial data register (SSR0, SSR1)

Initial Value

00001000^B

15

14

13

12

11

10

9

8

000023H

000029H

Address :

PE

ORE

FRE

RDRF TDRE

BDS

RIE

TIE

( R )

( R/W ) ( R/W ) ( R/W )

UART prescaler reload register (UTRLR0, UTRLR1)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

000024H

00002AH

Address :

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

UART prescaler control register (UTCR0, UTCR1)

Initial Value

15

14

13

12

11

10

9

8

000025H

00002BH

Address :

0000-000^B

Reserved

MD

SRST

CKS

D10

D9

D8

( R/W ) ( R/W ) ( R/W ) ( R/W )

(

)

( R/W ) ( R/W ) ( R/W )

41

Preliminary

2004.01.09

MB90335 Series

・Block Diagram

Control bus

Reception interrupt

signal

#39 (27H)

Special-purpose

baud-rate generator

(UART prescaler

Transmission

clock

Send interrupt signal

#37 (25H)

control register

UTCR0, 1)

Clock

selector

Reception

clock

Reception

control

circuit

Transmission

control circuit

SCK0, SCK1

Start bit

Transmission

detection circuit

start circuit

Reception bit

counter

Transmission bit

counter

Transmission

parity counter

Reception parity

counter

SOT0, SOT1

Shift register for

reception

Shift register for

transmission

SIN0, SIN1

Reception

complete

SIDR0, SIDR1

SODR0, SODR1

Start

transmission

Receive status

decision circuit

Reception error

occurrence signal for

EI²OS (to CPU)

Internal data bus

MD1

MD0

PEN

P

SBL

PE

ORE

FRE

RDRF

TDRE

BDS

RIE

SCKL

M2L2

M2L1

M2L0

SCKE

SOE

SMR0,

SMR1

SCR0,

SCR1

SSR0,

SSR1

CL

A/D

REC

RXE

TXE

TIE

* : Interrupt number

42

Preliminary

2004.01.09

MB90335 Series

7. Extended I/O serial interface

The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit ×

1 channel configured clock synchronization scheme. LSB-first or MSB-first transfer mode can be selected for

data transfer.

There are two serial I/O operation modes available:

• Internal shift clock mode: Transfer data in synchronization with the internal clock.

• External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK).

By manipulating the general-purpose port sharing the external pin (SCK) in this

mode, data can also be transferred by a CPU instruction.

• Register list

Serial mode control status register (SMCS)

Initial Value

15

14

13

12

11

10

9

8

Address : 000059^H

00000010 B

SMD2 SMD1 SMD0

( R/W ) ( R/W ) ( R/W )

SIE

SIR

BUSY STOP

STRT

( R/W ) ( R/W )

( R/W )

( R/W ) ( R/W )

Initial Value

XXXX0000 B

7

6

5

4

3

2

1

0

Address : 000058^H

MODE

BDS

SOE

SCOE

(

)

(

)

(

)

( R/W )

(

)

( R/W )

Serial data register (SDR)

Address : 00005A^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Communication prescaler control register (SDCR)

Initial Value

0XXX0000B

15

14

13

12

11

10

9

8

Address : 00005B^H

MD

DIV3

DIV2

DIV1

DIV0

( R/W )

(

)

(

)

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W )

43

Preliminary

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MB90335 Series

• Block Diagram

Internal data bus

D7 to D0 (LSB first)

Transfer direction selection

Initial Value

(MSB first) D0 to D7

SIN

Read

Write

SDR (serial data register)

SOT

SCK

Shift clock counter

Control circuit

Internal clock

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

44

Preliminary

2004.01.09

MB90335 Series

2

8. I C Interface

The I²C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I²C

bus and has the following features.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Detecting transmitting direction function

• Start condition repeated generation and detection function

• Bus error detection function

• Register list

I²C bus status register (IBSR0)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 000070^H

BB

RSC

AL

LRB

TRX

AAS

GCA

FBT

( R )

I²C bus control register (IBCR0)

15

14

13

12

11

10

9

8

Initial Value

00000000B

Address : 000071H

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus clock selection register (ICCR0)

7

6

5

4

3

2

1

0

Initial Value

Address : 000072H

XXX0XXXXB

EN

CS4

CS3

CS2

CS1

CS0

(

)

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus address register (IADR0)

15

14

A6

13

A5

12

A4

11

A3

10

A2

9

8

Initial Value

XXXXXXXXB

Address : 000073^H

A1

A0

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus data register (IDAR0)

7

6

5

4

3

2

1

0

Initial Value

Address : 000074H

XXXXXXXXB

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

45

Preliminary

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MB90335 Series

• Block Diagram

ICCR

EN

2

I C enable

Peripheral clock

Clock devide 1

5

6

7

8

ICCR

CS4

CS3

Clock selector 1

Clock devide 2

CS2

CS1

CS0

Sync

2

4

8

16 32 64 128 256

Generating shift clock

Clock selector 2

Shift clock edge

change timing

IBSR

Bus busy

BB

Repeat start

RSC

LRB

TRX

Start stop condition

detection

Last Bit

Error

Send/receive

First Byte

FBT

AL

Arbitration lost detection

IBCR

BER

SCL0

SDA0

BEIE

INTE

INT

IRQ

Interrupt request

End

IBCR

SCC

Start

Master

MSS

ACK

Start stop condition

generation

ACK enable

GC-ACK enable

GCAA

IDAR

IBSR

AAS

Slave

Slave address

compare

Global call

GCA

IADR

46

Preliminary

2004.01.09

MB90335 Series

9. USB Function

The USB is an interface supporting the USB (Universal Serial Bus) communications protocol.

Feature of USB function

• Conform to USB 2.0 Full Speed

• FULL speed (12 Mbps) is supported.

• The device status is auto-answer.

• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16.

• Toggle check by data synchronization bit.

• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these

three commands can be processed the same way as the class vendor commands).

• The class vendor commands can be received as data and responded via firmware.

• Supports up to maximum six EndPoints (EndPoint0 is fixed to control transfer).

• Two transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for end point 0).

• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0).

• Capable of detection of connection and disconnection by monitoring the USB bus power line.

• Register list

UDC control register (UDCC)

7

6

5

4

3

2

1

0

Initial Value

10100000B

Address : 0000D0^H

Reserved

RST RESUM HCONX USTP

RFBK

PWC

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

EP0 control register (EP0C)

7

6

5

4

3

2

1

0

Initial Value

X1000000B

Address : 0000D2^H

Reserved

PKS0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XXXX0000B

Address : 0000D3H

Reserved Reserved STAL Reserved

(

)

(

)

(

)

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W )

EP1 control register (EP1C)

Address : 0000D4H

7

PKS1

6

PKS1

5

PKS1

4

PKS1

3

2

1

0

Initial Value

00000000B

PKS1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

01100001B

Address : 0000D5^H

EPEN

TYPE

DIR

DMAE NULE

STAL

PKS1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(Continued)

47

Preliminary

2004.01.09

MB90335 Series

EP2/3/4/5 control register (EP2C ～EP5C)

Initial Value

7

6

5

4

3

2

1

0

0000D6^H

0000D8H

0000DAH

0000DCH

Reserved

Address :

PKS2 5 PKS2 5 PKS2 5 PKS2 5 PKS2 5 PKS2 5 PKS2 5

01000000B

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

01100000B

15

14

13

12

11

10

9

8

0000D7^H

0000D9H

0000DBH

0000DDH

Reserved

EPEN

TYPE

DIR

DMAE NULE

STAL

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Time stamp register (TMSP)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000DE^H

TMSP

TMSP TMSP TMSP

TMSP

( R )

15

14

13

12

11

10

9

8

Initial Value

00000000B

Address : 0000DFH

TMSP TMSP

( R ) ( R )

TMSP

(

)

(

)

(

)

(

)

(

)

( R )

UDC status register (UDCS)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000E0^H

VOFF

VON

SUSP

SOF

BRST WKUP SETP

CONF

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Interrupt enable register (UDCIE)

15

14

13

12

11

10

9

8

Initial Value

00000000B

Address : 0000E1H

VOFFIE VONIE SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R ) ( R/W )

EP0I status register (EP0IS)

Address : 0000E2^H

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXXB

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

15

14

13

12

11

10

9

8

Initial Value

10XXX1XXB

Address : 0000E3H

BFINI DRQIIE

( R/W ) ( R/W )

DRQI

(

)

(

)

(

)

( R/W )

(

)

(

)

(Continued)

48

Preliminary

2004.01.09

MB90335 Series

(Continued)

EP0O status register (EP0OS)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000E4H

XXXXXXXXB

SIZE

(

)

( R )

15

14

13

12

11

10

9

8

Initial Value

100XX00XB

Address : 0000E5H

BFINI DRQOIE SPKIE

( R/W ) ( R/W ) ( R/W )

DRQO

SPK

(

)

(

)

( R/W ) ( R/W )

(

)

EP1 status register (EP1S)

Address : 0000E6H

Initial Value

XXXXXXXXB

7

6

5

4

3

2

1

0

SIZE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

1000000XB

Address : 0000E7H

BFINI DRQIE SPKIE

( R/W ) ( R/W ) ( R/W )

BUSY

DRQ

SPK

SIZE

(

)

( R )

( R/W ) ( R/W ) ( R/W )

EP2/3/4/5 status register (EP2S to EP5S)

Initial Value

7

6

5

4

SIZE

3

2

1

0

0000E8^H

0000EAH

0000ECH

0000EEH

Address :

XXXXXXXXB

SIZE

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

1000000XB

15

14

13

12

11

10

9

8

0000E9^H

0000EBH

0000EDH

0000EFH

BFINI DRQIE SPKIE

( R/W ) ( R/W ) ( R/W )

BUSY

DRQ

SPK

Address :

(

)

( R )

( R/W ) ( R/W )

(

)

EP0/1/2/3/4/5 data register (EP0DT to EP5DT)

0000F0H

0000F2H

0000F4H

0000F6H

0000F8H

0000FAH

Initial Value

7

6

5

4

BFDT

3

2

1

0

BFDT

Address :

XXXXXXXXB

BFDT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

0000F1H

0000F3H

0000F5^H

0000F7H

0000F9H

0000FBH

Initial Value

15

14

13

12

11

10

9

8

Address :

XXXXXXXXB

BFDT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

49

Preliminary

2004.01.09

MB90335 Series

10. USB Mini-HOST

USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred

to and from Device without PC intervention.

Feature of USB Mini-HOST

• Automatic detection of Low Speed/Full Speed transfer

• Low Speed/Full Speed transfer support

• Automatic detection of connection and cutting device

• Reset sending function support to USB-bus

• Support of IN/OUT/SETUP/SOF token

• In-token handshake packet automatic transmission (excluding STALL)

• Handshake packet automatic detection at out-token

• Supports a maximum packet length of 256 bytes

• Error (CRC error/toggle error/time-out) various supports

• Wake-Up function support

Differences between the USB HOST and USB Mini-HOST

HOST

Mini-HOST

Hub support

Transfer

×

Bulk transfer

Control transfer

Interrupt transfer

ISO transfer

Low Speed

×

Transfer speed

Full Speed

PRE packet support

SOF packet support

CRC error

Toggle error

Time-out

Error

Maximum packet < receive

data

Detection of connection and cutting of device

Transfer speed detection

: Supported

×

: Not supported

50

Preliminary

2004.01.09

MB90335 Series

• Register list

USB HOST control register 0 (HCONT0)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000C0^H

RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST

HOST

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB HOST control register 1 (HCONT1)

15

14

13

12

11

10

SOFSTEP CANCEL RETRY

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

9

8

Initial Value

00000001B

Address : 0000C1^H

Reserved Reserved Reserved Reserved Reserved

USB HOST interruption register (HIRQ)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000C2^H

Reserved

RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ

TCAN

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB HOST error status register (HERR)

15

14

13

12

11

10

9

8

Initial Value

00000011B

Address : 0000C3H

LSTSOF RERR TOUT

CRC TGERR STUFF

HS

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB HOST state status register (HSTATE)

7

6

5

4

3

2

1

0

Initial Value

XX010010B

Address : 0000C4^H

ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT

(

)

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W )

( R )

USB SOF interruption FRAME comparison register (HFCOMP)

15

14

13

12

11

10

9

8

Initial Value

00000000B

FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME

COMP COMP COMP COMP COMP COMP COMP COMP

Address : 0000C5^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB retry timer setting register 0/1/2 (HRTIMER)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000C6H

Address : 0000C7H

Address : 0000C8H

RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

00000000B

RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

7

6

5

4

3

2

1

0

Initial Value

XXXXXX00B

RTIMER2 RTIMER2

( R/W ) ( R/W )

(

)

(

)

(

)

(

)

(

)

(

)

(Continued)

51

Preliminary

2004.01.09

MB90335 Series

(Continued)

USB HOST address register (HADR)

15

14

13

12

11

10

9

8

Initial Value

Address : 0000C9^H

X0000000B

ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(

)

USB EOF setting register 0/1 (HEOF)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000CAH

Address : 0000CBH

EOF0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XX000000B

EOF1

(

)

(

)

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB FRAME setting register (HFRAME)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000CC^H

FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XXXXX000B

Address : 0000CDH

FRAME1 FRAME1 FRAME1

( R/W ) ( R/W ) ( R/W )

(

)

(

)

(

)

(

)

(

)

USB token end point register (HTOKEN)

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 0000CEH

TGGL TKNEN TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

52

Preliminary

2004.01.09

MB90335 Series

11. DTP/external interrupt circuit

Feature of DTP/external interrupt circuit

DTP (Data Transfer Peripheral)/external interrupt circuit detects the interrupt request input from the external

interrupt input terminal INT7 to INT0, and outputs the interrupt request.

• DTP/external interrupt circuit function

The DTP/external interrupt function outputs an interrupt request upon detection of the edge or level signal input

to the external interrupt input pins (INT7 to INT0).

If CPU accept the interrupt request, and if the extended intelligent I/O service (EI²OS) is enabled, branches to

the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI²OS.

And if EI²OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer

(DTP function) performed by EI²OS.

• Feature of DTP/external interrupt circuit

External interrupt

DTP function

8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK,

P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0)

Input pin

The detection level or the type of the edge for each terminals can be set in the

request level setting register (ELVR)

Interrupt source

Input of “H” level/ “L” level/rising edge/falling edge.

#18 (12^H) , #20 (14H) , #22 (16H) , #24 (18H)

Interrupt number

Interrupt control

Enabling/Prohibit the interrupt request output using the DTP/interrupt enable

register (ENIR)

Interrupt flag

Holding the interrupt source using the DTP/interrupt cause register (EIRR)

Process setting

Prohibit EI²OS (ICR: ISE=“0”)

Enable EI²OS (ICR: ISE=“1”)

Branched to the interrupt handling

routine

After an automatic data transfer by EI²OS,

Branched to the interrupt handling routine

Process

• Register list

Interrupt/DTP enable register (ENIR)

Initial Value

7

6

5

4

3

2

1

0

Address : 00003C^H

00000000B

EN7

EN6

EN5

(R/W)

EN4

(R/W)

EN3

(R/W)

EN2

(R/W)

EN1

(R/W)

EN0

(R/W)

Interrupt/DTP source register (EIRR)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00003DH

ER7

(R/W)

ER6

ER5

(R/W)

ER4

(R/W)

ER3

(R/W)

ER2

(R/W)

ER1

(R/W)

ER0

(R/W)

Request level setting register (ELVR)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00003EH

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

(R/W)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00003FH

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

(R/W)

53

Preliminary

2004.01.09

MB90335 Series

• Block Diagram

Request level setting register (ELVR)

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2

DTP/external interrupt input detection circuit

Selector

P60/INT0

P67/INT7

SDA0

Selector

P66/INT6

SCL0

P61/INT1

Selector

P62/INT2

P65/INT5

PWC

SIN

Selector

P64/INT4

SCK

P63/INT3

SOT

DTP/interrupt

source register

(EIRR)

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

Interrupt request signal

#18(12H)

#20(14H)

#22(16H)

#24(18H)

DTP/interrupt

enable register

(ENIR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

* : Interrupt number

54

Preliminary

2004.01.09

MB90335 Series

12. Interrupt controller

The interrupt control register is located inside the interrupt controller, it exists for every I/O having an interrupt

function. This register has the following functions.

• Setting of the interrupt levels of relevant peripheral

• Register list

Interrupt control register

Address：ICR01 : 0000B1^H

ICR03 : 0000B3H

ICR05 : 0000B5H

ICR07 : 0000B7H

ICR09 : 0000B9H

ICR11 : 0000BBH

ICR13 : 0000BDH

ICR15 : 0000BFH

15

14

13

12

11

10

9

8

ICR01, 03,

05, 07, 09,

11, 13, 15

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

( W )

( 0 )

( W )

( 0 )

( W )

( 0 )

( W )

( 0 )

( R/W ) ( R/W ) ( R/W ) ( R/W )

( 0 )

Read/Write →

Initial Value →

( 1 )

ICR00 : 0000B0^H

Address：ICR02 : 0000B2H

ICR04 : 0000B4H

ICR06 : 0000B6H

ICR08 : 0000B8H

ICR10 : 0000BAH

ICR12 : 0000BCH

ICR14 : 0000BEH

7

6

5

4

3

2

1

0

ICR00, 02,

04, 06, 08,

10, 12, 14

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

( W )

( 0 )

( W )

( 0 )

( W )

( 0 )

( W )

( 0 )

( R/W ) ( R/W ) ( R/W ) ( R/W )

( 0 ) ( 1 ) ( 1 ) ( 1 )

Read/Write →

Initial Value →

Note : Do not access interrupt control registers using any read modify write instruction because it causes a

malfunction.

• Block Diagram

3

32

Interrupt request

(peripheral resource)

IL2

IL1

IL0

3

Determine

priority

of

interrupt

3

(CPU)

Interrupt level

55

Preliminary

2004.01.09

MB90335 Series

13. µDMAC

µDMAC is simple DMA with the function equal with EI²OS. It has 16 channels DMA transfer channels with the

following features.

• Performs automatic data transfer between the peripheral resource (I/O) and memory

• The program execution of CPU stops in the DMA startup

• Capable of selecting whether to increment the transfer source and destination addresses

• DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register and

descriptor

• A STOP request is available for stopping DMA transfer from the resource

• Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA

status register is set and a termination interrupt is output to the transfer controller.

• Register list

DMA enable register higher (DERH)

Initial Value

15

14

13

12

11

10

9

8

Address : 0000AD^H

00000000B

EN15

EN14

EN13

EN12

EN11

EN10

EN9

EN8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA enable register lower (DERL)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 0000AC^H

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA stop status register (DSSR)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 0000A4H

STP7

STP6

STP5

STP4

STP3

STP2

STP1

STP0

STP8

STP15 STP14 STP13 STP12 STP11 STP10 STP9

*

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA status register higher (DSRH)

Initial Value

00000000B

15

14

13

12

11

10

9

8

Address : 00009D^H

DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9

DTE8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA status register lower (DSRL)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00009C^H

DTE7

DTE6

DTE5

DTE4

DTE3

DTE2

DTE1

DTE0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA descriptor channel specification register (DCSR)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00009BH

Reserved Reserved Reserved

STP

DCSR3 DCSR2 DCSR1 DCSR0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

* : The DSSR is lower when the STP bit of DCSR in the DSSR is 0.

The DSSR is upper when the STP bit of DCSR in the DSSR is 1.

(Continued)

56

Preliminary

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MB90335 Series

(Continued)

DMA buffer address pointer lower 8 bit (DBAPL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007920^H

XXXXXXXXB

DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA buffer address pointer middle 8 bit (DBAPM)

Initial Value

15

14

13

12

11

10

9

8

Address : 007921^H

XXXXXXXXB

DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA Buffer address pointer higher 8 bit (DBAPH)

Initial Value

7

6

5

4

3

2

1

0

Address : 007922^H

XXXXXXXXB

DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

ꢀ

DMA control register (DMACS)

Initial Value

15

14

13

12

IF

11

10

9

8

Address : 007923^H

XXXXXXXXB

RDY2

RDY1 BYTEL

BW

BF

DIR

SE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA I/O register address pointer lower 8 bit (DIOAL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007924^H

XXXXXXXXB

A07

A06

A05

A04

A03

A02

A01

A00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA I/O register address pointer higher 8 bit (DIOAH)

Initial Value

15

14

13

12

11

10

9

8

Address : 007925^H

XXXXXXXXB

A15

A14

A13

A12

A11

A10

A09

A08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA data counter lower 8 bit (DDCTL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007926H

XXXXXXXXB

B07

B06

B05

B04

B03

B02

B01

B00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA data counter higher 8 bit (DDCTH)

Initial Value

15

14

13

12

11

10

9

8

Address : 007927H

XXXXXXXXB

B15

B14

B13

B12

B11

B10

B09

B08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Note : The above register is switched for each channel depending on the DCSR.

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14. Address matching detection function

When the address is equal to the value set in the address detection register, the instruction code to be read into

the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9

instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the

program patch function is enabled.

Two address detection registers are provided, for each of which there is an interrupt enable bit. When the address

matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code

to be read into the CPU is forcibly replaced with the INT9 instruction code.

• Register list

• Program address detect register 0 to 2 (PADR0)

PADR0 (lower)

Initial Value

7

6

5

4

3

2

1

0

Address : 001FF0^H

XXXXXXXXB

(R/W)

PADR0 (middle)

Address : 001FF1^H

Initial Value

15

14

13

12

11

10

9

8

XXXXXXXXB

(R/W)

PADR0 (higher)

Address : 001FF2H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

(R/W)

• Program address detect register 3 to 5 (PADR1)

PADR1 (lower)

Initial Value

15

14

13

12

11

10

9

8

Address : 001FF3^H

XXXXXXXXB

(R/W)

PADR1 (middle)

Address : 001FF4H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXXB

(R/W)

PADR1 (higher)

Address : 001FF5^H

Initial Value

15

14

13

12

11

10

9

8

XXXXXXXXB

(R/W)

• Program address detect control status register (PACSR)

PACSR

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00009EH

Reserved

Reserved Reserved Reserved

Reserved

AD1E

AD0E

(R/W)

R/W : Readable and Writable

X

: Undefined

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MB90335 Series

15. Delay interrupt generator module

• The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware

interrupt can be generated by software.

• Function of delay interrupt generator module

Function and control

• Setting the R0 bit in the delayed interrupt request generate/cancel register to

1 (DIRR: R0 = 1) generates a interrupt request.

• Setting the R0 bit in the delayed interrupt request generate/cancel register to

Interrupt source

0 (DIRR: R0 = 0) cancels the interrupt request.

Interrupt control

Interrupt flag

• No setting of permission register is provided.

• Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0)

• Not ready for expanded intelligent I/O service (EI²OS).

EI²OS support

• Block Diagram

Internal data bus

R0

S Interrupt request

Interrupt

Delayed Interrupt source/release register (DIRR)

: Undefined bit

request

signal

R Latch

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MB90335 Series

16. ROM mirroring function selection module

• The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read

by accessing bank 00.

• ROM mirroring function selection module

Description

FFFFFF^Hto FF8000H in the FF bank can be read through 00FFFFH to 008000H in

Mirror setting address

the 00 bank.

Interrupt source

EI²OS support

• None

• Not ready for extended intelligent I/O service (EI²OS).

• Block Diagram

ROM mirror function selection register (ROMM)

Re-

served

MI

Address

Address area

00 bank

FF bank

Data

ROM

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MB90335 Series

17. Low power consumption (standby) mode

• The F²MC-16LX can be set to save power consumption by selecting and setting the low power consumption

mode.

• CPU operation mode and functional description

CPU

operating clock

Operation

mode

Description

Normally The CPU and peripheral resources operate at the clock frequency obtained by

run

PLL multiplication of the oscillator clock (HCLK) frequency.

Only peripheral resources operate at the clock frequency obtained by PLL

multiplication of the oscillator clock (HCLK) frequency.

Sleep

PLL clock

Time-base Only the time-base timer operates at the clock frequency obtained by PLL

timer

multiplication of the oscillator clock (HCLK) frequency.

The CPU and peripheral resources are suspended with the oscillator clock

stopped.

Stop

normally The CPU and peripheral resources operate at the clock frequency obtained by

run

dividing the oscillator clock (HCLK) frequency by two.

Only peripheral resources operate at the clock frequency obtained by dividing the

oscillator clock (HCLK) frequency by two.

Sleep

Main clock

Time-base Only the time-base timer operates at the clock frequency obtained by dividing the

timer

oscillator clock (HCLK) frequency by two.

The CPU and peripheral resources are suspended with the oscillator clock

stopped.

Stop

CPU intermittent Normally The halved or PLL-multiplied oscillator clock (HCLK) frequency is used for

operation mode

run

operation while being decimated in a certain period.

• Register list

Lowe power consumption mode control register (LPMCR)

Initial Value

00011000B

7

6

5

4

3

2

1

0

Address : 0000A0H

Reserved

STP

SLP

SPL

RST

TMD

CG1

CG0

( W )

( R/W )

( W )

( R/W ) ( R/W ) ( R/W ) ( R/W )

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MB90335 Series

18. Clock

The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The

internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on

source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation as PLL clock.

• Register list

Clock selection register (CKSCR)

Initial Value

15

14

13

12

11

10

9

8

Address : 0000A1H

11111100B

SCM

MCM

WS1

WS0

SCS

MCS

CS1

CS0

( R )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

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MB90335 Series

19. 512 Kbits flash memory

The description that follows applies to the flash memory built in the MB90F334; it is not applicable to evaluation

ROM or masked ROM.

The method of data write/erase to flash memory is following three types.

• Parallel writer

• Serial dedicated writer

• Write/erase by executing program

• Description of 512 Kbits flash memory

512 Kbits flash memory is located in FF^Hbank in the CPU memory map. Function of flash memory interface

circuit enables read and program access from CPU.

Write/erase to flash interface is executed by instruction from CPU via flash memory interface, so rewrite of

program and data is carried on in the mounting state effectively.

Data can be reprogrammed not only by program execution in existing RAM but by program execution in flash

memory by dual operation. The different banks (the upper and lower banks) can be used to execute an erase/

program and a read concurrently.

Also, erase/write and read in the defferent bank (Upper Bank/Lower Bank) is executed simultaneously.

• Features of 512 Kbits flash memory

• Sector configuration : 64 Kwords × 8 bits/32 words × 16 bits (4K × 4 + 16K × 2 + 4K × 4)

• Simultaneous execution of erase/write and read by 2-bank configuration

• Automatic program algorithm (Embeded Algorithm^TM*)

• Built-in deletion pause/deletion resume function

• Detection of programming/erasure completion using data polling and the toggle bit

• At least 10,000 times guaranteed

• Minimum flash read cycle time : 2 machine cycles

* : Embedded Algorithm^TMis a trade mark of Advanced Micro Devices Inc.

Note : The read function of manufacture code and device coad is not including.

Also, these code is not accessed by the command.

• Flash write/erase

• Flash memory can not execute write/erase and read by the same bank simultaneously.

• Data can be programmed/deleted into and erased from flash memory by executing either the program

residing in the flash memory or the one copied to RAM from the flash memory.

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MB90335 Series

• Sector configuration of flash memoly

Flash Memory CPU address Writer address *

FF0000H

FF0FFFH

FF1000H

FF1FFFH

FF2000H

FF2FFFH

FF3000H

FF3FFFH

FF4000H

FF7FFFH

FF8000H

FFBFFFH

FFC000H

FFCFFFH

FFD000H

FFDFFFH

FFE000H

FFEFFFH

FFF000H

FFFFFFH

70000H

70FFFH

71000H

71FFFH

72000H

72FFFH

73000H

73FFFH

74000H

77FFFH

78000H

78FFFH

7C000H

7CFFFH

7D000H

7DFFFH

7E000H

7EFFFH

7F000H

7FFFFH

SA0 (4 Kbyte)

SA1 (4 Kbyte)

SA2 (4 Kbyte)

SA3 (4 Kbyte)

SA4 (16 Kbyte)

SA5 (16 Kbyte)

SA6 (4 Kbyte)

SA7 (4 Kbyte)

SA8 (4 Kbyte)

SA9 (4Kbyte)

* : Flash memory writer address indicates the address equivalent to the CPU address when data is written

to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel

programmer are executed based on writer addresses.

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Preliminary

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MB90335 Series

• Register list

Flash memory control register (FMCS)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000AE^H

000X0000B

Reserved

INTE RDYINT

WE

RDY

LPM1

LPM0

( R/W ) ( R/W ) ( R/W )

( R )

( W )

( R/W )

( W )

( R/W )

Flash memory program control register (FWR0)

Initial Value

00000000B

7

6

5

4

3

2

1

0

Address : 00790C^H

SA7E

SA6E

SA5E

SA4E

SA3E

SA2E

SA1E

SA0E

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Flash memory program control register (FWR1)

Initial Value

00000000B

15

14

13

12

11

10

9

0

Address : 00790DH

SA9E

SA8E

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Sector conversion setting register (SSR0)

Initial Value

00XXXXX0B

7

6

5

4

3

2

1

0

Address : 00790EH

SEN0

( R/W ) ( R/W )

(

)

(

)

(

)

(

)

(

)

( R/W )

When writing to SSR0 register, write “0” except for SEN0.

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Preliminary

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MB90335 Series

• Standard configuration for Fujitsu standard serial on-board writing

The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corp.

is used for Fujitsu standard serial onboard writing.

Host interface cable (AZ201)

General-purpose common cable (AZ210)

Flash

microcontroller

programmer

+

CLK synchronous

RS232C

serial

MB90F337

user system

Memory card

Can operate standalone

Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the

flash microcontroller programmer (AF220, AF210, AF120 and AF110) , general-purpose common cable for

connection (AZ210) and connectors.

• Pins Used for Fujitsu Standard Serial On-board Programming

Function

Description

MD2,

The device enters the serial program mode by setting MD2 = 1,

MD1 = 1 and MD0 = 0.

Mode input pin

MD1, MD0

X0, X1

Because the internal CPU operation clock is set to be the 1 multiplication

PLL clock in the serial write mode, the internal operation clock frequency

is the same as the oscillation clock frequency.

Oscillation pin

P60, P61 Write program start pins

Input a Low level to P60 and a High level to P61.

RST

Reset input pin

SIN0

SOT0

SCK0

Serial data input pin

Serial data output pin

Serial clock input pin

UART0 is used as CLK synchronous mode.

In write mode, the pins used for the UART0 CLK synchronous mode are

SIN0, SOT0, and SCK0.

When supplying the write voltage (MB90F337 : 3.3 V±0.3 V) from the

user system, connection with the flash microcontroller programmer is

not necessary.

V^CC

V^SS

Power source input pin

GND Pin

When connecting, do not short-circuit with the user power supply.

Share GND with the flash microcontroller programmer.

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Preliminary

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MB90335 Series

The control circuit shown in the diagram is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the

user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash microcon-

troller programmer.

AF220/AF210/AF120/AF110

Write control pin

MB90F337 write control pin

10 kΩ

AF220/AF210/AF120/AF110

/TICS pin

User

Control circuit

The MB90F337 serial clock frequency that can be input is determined by the following expression • Use the

flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator

clock frequency to be used.

Imputable serial clock frequency = 0.125 × oscillation clock frequency.

• Maximum serial clock frequency

Maximum serial clock

Oscillation

clock

frequency

Maximum serial clock

frequency acceptable to the

microcontroller

Maximum serial clock

frequency that can be set

with the AF200

frequency that can be set

with the AF220/AF210/

AF120/AF110

At 6 MHz

750 kHz

500 kHz

• System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa

Digital Computer Corp.)

Part number

Function

AF220/AC4P Model with internal Ethernet interface

AF210/AC4P Standard model

/100 V to 220 V power adapter

Unit

AF120/AC4P Single key internal Ethernet interface mode

AF110/AC4P Single key model

AZ221

AZ210

FF201

AZ290

/P2

PC/AT RS232C cable for writer

Standard target probe (a) length : 1 m

Control module for Fujitsu F²MC-16LX flash microcontroller control module

Remote controller

2 MB PC Card (option) FLASH memory capacity to respond to 128 KB

4 MB PC Card (option) FLASH memory capacity to respond to 512 KB

/P4

Contact to : Yokogawa Digital Computer Corp. TEL : (81)-42-333-6224

Note : The AF200 flash micon programmer is a retired product, but it can be supported using control module FF201.

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MB90335 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VCC = 3.3 V, VSS = 0.0 V)

Remarks

Rating

Parameter

Symbol

Unit

Min

Max

Power supply voltage

V^CC

VSS − 0.3

VSS + 4.0

V

*1

Nch0.D

(Withstand voltage I/O of 5 V)

Input voltage

VI

VSS − 0.3

VSS + 6.0

V

− 0.5

VSS − 0.3

− 0.5

V^SS+ 4.5

VSS + 4.0

VSS + 4.5

10

V

USB I/O

*1

Output voltage

V^O

V

USB I/O

I^OL1

mA

Other than USB I/O*²

USB I/O*²

L level maximum output

current

IOL2

43

L level average output cur-

rent

IOLAV

ΣIOL

3

mA

*3

L level maximum total out-

put current

60

30

L level average total

output current

ΣI^OLAV

*4

I^OH1

− 10

− 43

mA

Other than USB I/O*²

USB I/O*²

H level maximum output

current

IOH2

H level average output cur-

rent

IOHAV

ΣI^OH

− 3

mA

*3

H level maximum total out-

put current

− 60

− 30

H level average total

output current

ΣIOHAV

*4

Power consumption

Pd

T^A

351

+ 85

mW Target value

Operating temperature

− 40

− 55

°C

+ 150

+ 125

Storage temperature

Tstg

°C

USB I/O

*1 : V^Iand VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some

means with external components, the ICLAMP rating supersedes the VI rating.

*2 : A peak value of an applicable one pin is specified as a maximum output current.

*3 : The average output current specifies the mean value of the current flowing in the relevant single pin during a

period of 100 ms.

*4 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins

during a period of 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

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MB90335 Series

2. Recommended Operating Conditions

(VSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3.0

Max

3.6

V

At normal operation (At USB is used)

At normal operation (At USB is unused)

Hold state of stop operation

CMOS input pin

Power supply voltage

Input H level voltage

V^CC

2.7

1.8

V^IH

V^IHS

VIHM

V^IHUSB

V^IL

0.7 VCC

0.8 VCC

VCC − 0.3

2.0

VCC + 0.3

0.3 VCC

0.2 VCC

VSS + 0.3

0.8

CMOS hysteresis input pin

MD input pin

USB input pin

VSS − 0.3

VSS

CMOS input pin

V^ILS

CMOS hysteresis input pin

MD input pin

Input L level voltage

VILM

VILUSB

USB input pin

Differential input

sensitivity

V^DI

0.2

0.8

V

USB input pin

Differential common

mode input voltage

range

VCM

2.5

V

USB input pin

Series resistance

R^S

T^A

25

− 40

0

30

Ω

Recommended value = 27 Ω at using USB

At USB is unused

+ 85

+ 70

°C

Operating

temperature

At USB is used

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

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Preliminary

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3. DC Characteristics

Sym-

(TA = − 40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Typ

Parameter

Pin name

Conditions

Unit Remarks

bol

Min

VCC − 0.5

2.8

Max

Vcc

Output pin of other

than P60 to P67, HVP, I^OH= −4.0 mA

HVM, DVP, DVM

Output

H level

voltage

V

V^OH

HVP, HVM, DVP, DVM RL = 15 kΩ ± 5%

3.6

Output pin of other

than HVP, HVM, DVP, I^OL= 4.0 mA

DVM

Output

L level

voltage

Vss + 0.4

0.3

Vss

V

V^OL

HVP, HVM, DVP, DVM RL = 1.5 kΩ ± 5%

0

V

Output pin of other

V^CC= 3.3 V,

than P60 to P67, HVP,

Vss < VI < VCC

− 10

10

µA

Input leak

current

I^IL

HVM, DVP, DVM

HVP, HVM, DVP, DVM

− 5

5

µA

kΩ

Pull-up

resistor

P00 to P07,

P10 to P17

VCC = 3.3 V,

Ta = + 25 °C

R^PULL

25

50

100

Open drain

output

I^LIODP60 to P67

0.1

10

µA

current

At USB

operating

Max 90 mA

(Target)

VCC = 3.3 V,

Internal frequency 24 MHz,

At normal operating

TBD

70

mA

At non-

operating

USB

(USTP = 0)

VCC = 3.3 V,

Internal frequency 24 MHz,

At normal operating

I^CC

mA

At non-

operating

USB

(USTP = 1)

VCC = 3.3 V,

Internal frequency 24 MHz,

At normal operating

TBD

mA

Power

supply

current

VCC

VCC = 3.3 V,

Internal frequency 24 MHz,

At sleep mode

ICCS

27

3.5

1

mA

VCC = 3.3 V,

Internal frequency 24 MHz,

At timer mode

mA

I^CTS

V^CC= 3.3 V,

Internal frequency 3 MHz,

At timer mode

Ta = +25 °C,

At Stop mode

I^CCH

1

5

µA

pF

kΩ

Input

capacitance

Other than Vcc and

Vss

C^IN

15

Pull-up

resistor

R^upRST

25

50

100

Note : P60 to P67 are N-ch open-drain pins usually used as CMOS.

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Preliminary

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MB90335 Series

4. AC Characteristics

(1) Clock input timing

(T^A= −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Sym-

bol

name

Parameter

Unit

Remarks

Min

Typ

Max

24

6

MHz External crystal oscillation

MHz External clock input

Clock frequency

fCH

X0, X1

6

166.7

ns External crystal oscillation

ns External clock input

Clock cycle time

t^HCYL

166.7

10

41.7

P^WH

PWL

A reference duty ratio is

30% to 70%.

Input clock pulse width

X0

ns

Input clock rise time and fall

time

tcr

tcf

5

ns At external clock

Internal operating clock

frequency

f^CP

3

24

MHz At main clock is used

ns At main clock is used

Internal operating clock

cycle time

tCP

42

333

• Clock timing

tHCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcr

tcf

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Preliminary

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MB90335 Series

• PLL operation guarantee range

Relation between internal operation clock frequency and power supply voltage

PLL operation guarantee range

3.6

3.0

2.7

Normal operation

assurance range

3

6

12

24

Internal clock fCP (MHz)

* : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V.

Relation between oscillation frequency and internal operation clock frequency

24

Multiply by 4

Multiply by 2

12

External clock

Multiply by 1

6

3

24

6

Oscillation clock FC (MHz)

The AC standards provide that the following measurement reference voltages.

• Output signal waveform

• Input signal waveform

Hysteresis input pin

Output pin

0.8 VCC

0.2 VCC

2.4 V

0.8 V

Hysteresis input/other than MD input pin

0.7 VCC

0.3 VCC

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Preliminary

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MB90335 Series

(2) Reset

(V^CC= 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Sym-

bol

name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

At normal operating,

At time base timer mode,

At main sleep mode,

At PLL sleep mode

500

ns

Reset input

time

tRSTL

RST

Oscillation time of

oscillator* + 500 ns

µs At stop mode

* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several

dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a

FAR/ceramic oscillator, and 0 milliseconds on an external clock.

• During normal operation, in time-base timer mode, in main sleep mode and in PLL sleep mode

t

RSTL

RST

0.2 VCC

• In stop mode

t

RSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal

operation

clock

Oscillation time

of oscillator

500 ns

Oscillation stabilization wait time

Execute instruction

Internal reset

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Preliminary

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MB90335 Series

(3) Power-on reset

(T^A= −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

Power supply rising time

t^R

VCC

30

ms

For repeated

operation

Power supply shutdown time

t^OFF

1

Notes : • V^CCmust be lower than 0.2 V before the power supply is turned on.

• The above standard is a value for performing a power - on reset.

• In the device, there are internal registers which is initialized only by a power-on reset. When the initial

ization of these items is expected, turn on the power supply according to the standards.

tR

2.7 V

0.2 V

VCC

0.2 V

tOFF

Sudden change of power supply voltage may activate the power-on reset function.

When changing the power supply voltage during operation as illustrated below, voltage fluctuation

should be minimized so that the voltage rises as smoothly as possible. When raising the power,

do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during

operation.

VCC

The rising edge should be 50 mV/ms

or less.

3.0 V

RAM data hold

VSS

74

Preliminary

2004.01.09

MB90335 Series

(4) UART0, UART1 I/O extended serial timing

(T^A= −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

SCKx

8 t^CP

ns

SCKx

SOTx

SCK ↓ → SOT delay time

− 80

100

60

80

Internal shiftc lock

Mode output pin is

C^L= 80 pF + 1 TTL

SCKx

SINx

Valid SIN → SCK ↑

ns

SCK ↑ → valid

SIN hold time

SCKx

SINx

Serial clock H pulse width

Serial clock L pulse width

t^SHSL

t^SLSH

SCKx, SINx

4 t^CP

ns

4 tCP

SCKx

SOTx

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

External shift clock

Mode output pin is

CL = 80 pF + 1 TTL

150

ns

SCKx

SINx

60

SCK ↑ → valid

SIN hold time

SCKx

SINx

Notes : • AC rating in CLK synchronous mode.

• C^Lis a load capacitance value on pins for testing.

• tCP is the machine cycle period (unit : ns) .

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

SOT

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SIN

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

75

Preliminary

2004.01.09

MB90335 Series

2

(5) I C timing

(V^CC= 3.3 V ± 0.3 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Sym-

bol

Pin Condi-

name tions

Parameter

Unit

Remarks

Min

Max

SCL clock frequency

f^SCL

0

100

kHz

Bus-free time between stop

and start conditions

t^BUS

4.7

µs

The first clock pulse is generated

immediately after the period.

Hold time (resend) start

t^HDSTA

4.0

µs

SCL clock “L” status hold time tLOW

SCL clock “H” status hold time t^HIGH

4.7

4.0

µs

Resend start condition setup

time

tSUSTA

4.7

µs

Data hold time

t^HDDAT

tSUDAT

tR

0

µs

ns

µs

Data set-up time

40

SDA and SCL signal rise time

SDA and SCL signal fall time

Stop condition setup time

1000

300

t^F

tSUSTO

4.0

0.8 VCC

SDA

0.2 VCC

tBUS

tR

_tHIGHtF

tLOW

tHDSTA

0.8 VCC

SCL

0.2 VCC

tHDSTA

tHDDAT

fSCL

tSUDAT

tSUSTA

tSUSTO

76

Preliminary

2004.01.09

MB90335 Series

(6) Timer Input Timing

(T^A= −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

t^TIWH

PWC

tTIWL

Input pulse width

4 tCP

ns

0.8 VCC

0.2 VCC

PWC

tTIWH

tTIWL

(7) Timer output timing

Parameter

(T^A= −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Sym-

bol

Condi-

Pin name

Unit

Remarks

tions

Min

Max

CLK ↑ → T^OUTchange time

PPG0 to PPG3 change time

tTO

PPGx

30

ns

2.4 V

CLK

PPGx

tTO

2.4 V

0.8 V

(8) Trigger Input Timing

(T^A= −40 °C to +85 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Condi-

tions

Parameter

Symbol

t^TRGH

Pin name

Unit

Remarks

Min

5 t^CP

1

Max

ns

At normal operating

At Stop mode

Input pulse width

INTx

tTRGL

µs

0.8 VCC

0.2 VCC

INTx

tTRGH

tTRGL

77

Preliminary

2004.01.09

MB90335 Series

5. USB characteristics

(TA = 0 °C to +70 °C, VCC = 3.3 V ± 0.3 V, VSS = 0.0 V)

Value

Sym

bol

Parameter

Symbol

Unit

Remarks

Min

Max

Input High level voltage

Input Low level voltage

Differential input sensitivity

V^IH

VIL

V^DI

2.0

V

0.8

Input

characteristics

0.2

0.8

2.8

0.0

1.3

4

V

Differential common mode range V^CM

2.5

3.6

0.3

2.0

20

V

Output High level voltage

Output Low level voltage

Cross over voltage

V^OH

V^OL

V^CRS

t^FR

V

IOH = −200 µA

IOL = 2 mA

V

ns

%

Ω

Full Speed

Low Speed

Full Speed

Low Speed

(TFR/TFF)

Rise time

Fall time

tLR

75

4

300

20

Output

characteristics

tFF

t^LF

75

90

80

28

300

t^RFM

tRLM

Z^DRV

111.11

125

Rising/falling time matching

Output registance

(TLR/TLF)

44

Including Rs = 27 Ω

• Data signal timing (Full Speed)

Fall time

Rise time

DVP/HVP

DVM/HVM

90%

Vcrs

10%

tFF

tFR

• Data signal timing (Low Speed)

Rise time

Fall time

HVP

90%

Vcrs

10%

HVM

tLF

tLR

78

Preliminary

2004.01.09

MB90335 Series

• Load condition (Full Speed)

Testing point

RS = 27 Ω

DVP/HVP

DVM/HVM

CL = 50 pF

RS = 27 Ω

Testing point

CL = 50 pF

• Load condition (Low Speed)

Testing point

RS = 27 Ω

HVP

HVM

CL = 50 pF 150 pF

Testing point

RS = 27 Ω

CL = 50 pF 150 pF

79

Preliminary

2004.01.09

MB90335 Series

■ ORDERING INFORMATION

• MB90335 Series

Part number

Package

Remarks

MB90F337PFM

MB90337PFM

64-pin plastic LQFP

(FPT-64P-M09)

80

Preliminary

2004.01.09

MB90335 Series

■ PACKAGE DIMENSION

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

64-pin plastic LQFP

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

*12.00±0.10(.472±.004)SQ

0.145±0.055

(.0057±.0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.25(.010)

INDEX

0~8˚

64

17

0.50±0.20

(.020±.008)

0.10±0.10

(.004±.004)

(Stand off)

"A"

1

16

0.60±0.15

(.024±.006)

0.65(.026)

0.32±0.05

(.013±.002)

M

0.13(.005)

C

2003 FUJITSU LIMITED F64018S-c-3-5

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

81

Preliminary

2004.01.09

MB90335 Series

MEMO

82

Preliminary

2004.01.09

MB90335 Series

MEMO

83

Preliminary

2004.01.09

MB90335 Series

FUJITSU LIMITED

For further information please contact:

Japan

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

FUJITSU LIMITED

Marketing Division

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94088-3470, U.S.A.

Tel: +1-408-737-5600

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Tel: +65-6281-0770

Fax: +65-6281-0220

http://www.fmal.fujitsu.com/

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

F0312

FUJITSU LIMITED Printed in Japan


型号：	MB90335
厂家：	FUJI ELECTRIC
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总84页 (文件大小：484K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90335 [FUJI]

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