GPCD2T020A-NnnV-HS03X [GENERALPLUS]
Two--channell Sound Conttrollller;
| 型号： | GPCD2T020A-NnnV-HS03X |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | Two--channell Sound Conttrollller |
| 文件： | 总26页 (文件大小：1174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCD2T020A
Two-channel Sound Controller
Nov. 16, 2018
Version 1.1
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCD2T020A
Table of Contents
PAGE
1. GENERAL DESCRIPTION......................................................................................................................................................................4
2. FEATURES .............................................................................................................................................................................................4
3. APPLICATION FIELD .............................................................................................................................................................................4
4. BLOCK DIAGRAM..................................................................................................................................................................................5
5. SIGNAL DESCRIPTION..........................................................................................................................................................................6
5.1. MAIN FUNCTION PIN ..........................................................................................................................................................................6
5.2. LQFP48 PACKAGE PIN ASSIGNMENT ..................................................................................................................................................7
5.2.1. GPCD2T020A (LQFP48-type1).............................................................................................................................................7
5.2.2. GPCD2T020A (LQFP48-type2).............................................................................................................................................9
5.3. SOP16 PACKAGE PIN ASSIGNMENT.................................................................................................................................................. 11
5.3.1. GPCD2T020A (HS032)....................................................................................................................................................... 11
5.3.2. GPCD2T020A (HS031).......................................................................................................................................................13
6. FUNCTION DESCRIPTION...................................................................................................................................................................15
6.1. SRAM............................................................................................................................................................................................15
6.2. ROM..............................................................................................................................................................................................15
6.3. LOW VOLTAGE RESET......................................................................................................................................................................15
6.4. INTERRUPT .....................................................................................................................................................................................15
6.5. HARDWARE PWMIO........................................................................................................................................................................15
6.6. I/O.................................................................................................................................................................................................15
6.7. TIMER/COUNTER (TIMER A/TIMER B/TIMER C)...................................................................................................................................15
6.8. SLEEP, WAKEUP AND WATCHDOG .....................................................................................................................................................15
6.8.1. Sleep and Wakeup..............................................................................................................................................................15
6.8.2. Watchdog............................................................................................................................................................................15
6.9. SPEECH AND PUSH-PULL .................................................................................................................................................................16
6.10.COMPARATOR .................................................................................................................................................................................16
6.11.CAPACITIVE TOUCH SENSOR (CTS) AND CTS TIMERS........................................................................................................................16
6.12.SPI CONTROLLER ...........................................................................................................................................................................16
7. ELECTRICAL SPECIFICATIONS..........................................................................................................................................................17
7.1. ABSOLUTE MAXIMUM RATINGS .........................................................................................................................................................17
7.2. DC CHARACTERISTICS (VDDIO/VDD_RGI=3.0V, TA=25℃) .............................................................................................................17
7.3. DC CHARACTERISTICS (VDDIO/VDD_RGI=4.5V, TA=25℃) .............................................................................................................18
7.4. DAC CHARACTERISTICS (VDDIO/VDD_RGI/AVDD =4.5V, RL=8Ω, F=1KHZ, TA=25℃).....................................................................18
7.5. REGULATOR CHARACTERISTICS (TA=25℃).......................................................................................................................................19
7.6. THE EROSC RELATIONSHIP BETWEEN ROSC AND FOSC (TA=25℃) ......................................................................................................19
7.7. THE EROSC RELATIONSHIP BETWEEN VDD AND FOSC (TA=25℃) ......................................................................................................19
7.8. THE IROSC RELATIONSHIP BETWEEN VDD AND FOSC (TA=25℃)........................................................................................................19
8. APPLICATION CIRCUITS.....................................................................................................................................................................20
8.1. GPCD2T020AAPPLICATION CIRCUIT WITH EXTERNAL ROSC MODE (ROSC-MODE)..............................................................................20
8.2. GPCD2T020AAPPLICATION CIRCUIT WITH 16MHZ X’TAL (XTAL-MODE).............................................................................................21
8.3. GPCD2T020A 32K X’TAL APPLICATION CIRCUIT ...............................................................................................................................22
9. PACKAGE/PAD LOCATIONS ...............................................................................................................................................................23
9.1. ORDERING INFORMATION .................................................................................................................................................................23
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GPCD2T020A
9.2. PACKAGE INFORMATION ...................................................................................................................................................................23
9.2.1. LQFP 48 .............................................................................................................................................................................23
9.2.2. SOP 16...............................................................................................................................................................................24
10.DISCLAIMER........................................................................................................................................................................................25
11. REVISION HISTORY.............................................................................................................................................................................26
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Version: 1.1
GPCD2T020A
2-CHANNEL SOUND CONTROLLER
1.GENERAL DESCRIPTION
GPCD2T020A series features a 64K-bytes factory programmed
OTP memory, maximum of 512-byte SRAM, three 12-bit timers,
20 general I/Os, and one 14-bit audio push-pull driver.
GPCD2T020A operates in a broad range of working voltage from
2.2V through 5.5V along with low voltage reset function. In
addition, a sleep mode is designed to save powers for those
applications with limited power resources available. In audio
processing, speech can be mixed into one output. A Serial
Peripheral Interface (SPI) controller is also included to facilitate
communication with other devices and components.
– 12 I/Os with high sink current
– Key wakeup/interrupt function
– 32.768KHz oscillator circuit for real time clock function
(X’tal or R-osc)
– Built-in R-oscillator (external resistor needed), X’tal or
internal R-oscillator (only 16MHz available for IOSC) for
system operating clock
– Internal time base generator
– Three 12-bit timers/counters, TMA with capture and
comparison function, TMB/TMC with comparison function
(Programmable and auto reload)
– Watchdog function
2.FEATURES
– 14-bit PUSH-PULL driver for driving speaker directly
– IR output
8-bit micro-processor
– 12 hardware PWMIOs
512-byte SRAM
– One SPI serial interface I/Os
64K-bytes factory programmed OTP memory
Operating voltage: 2.2V – 5.5V
Max. of CPU operating speed: 8.0MHz (Fosc=16MHz)
Five wakeup sources
– Hardware Touch function
– One set built-in comparator with PGA.
Sleep mode to reduce power consumption
17 IRQs & 6 NMI Interrupts
Internal built-in regulator to supply core power
Two software channels with noise filter for high quality sound
playback
3.APPLICATION FIELD
Talking instrument controller
General music synthesizer
General purpose controller
High-end toy controller
Intelligent education toy
And more
Low Voltage Detection
8-level (2.2V/ 2.4V/ 2.6V/ 2.8V/ 3.0V/ 3.2V/ 3.4/ 3.6V) voltage
detector
Low Voltage Reset
Peripherals
– 20 I/O pins (IOA[7:0], IOB[7:0], IOD[7:4])
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GPCD2T020A
4.BLOCK DIAGRAM
XI
Clock
Timer / Counter
2 software channel
CTS
XO
8-Bit controller
SRAM
CMPIO
RESETB
Regulator/LVR/POR
SPI
32K Clock
14-Bit
Audio PUSH-PULL
AUD0
AUN1
PWMIO
20 General I/O,IOA/IOB[7:0],IOD[7:4]
IOA0~7
IOB0~7
IOD4~7
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GPCD2T020A
5. SIGNAL DESCRIPTION
5.1. Main Function Pin
Mnemonic
Dedicate IO
Type
Description
VDDIO0
VSSIO0
VDDIO1
VSSIO1
P
G
P
Power for IOA/IOD
GND for all IOA/IOD
Power for IOB
G
GND for all IOB
IOA: bi-directional I/O ports
IOA0~IOA7
IOB0~IOB7
IOD4~IOD7
I/O
I/O
I/O
These pins can be programmed as wakeup I/O pins.
IOB: bi-directional I/O ports
These pins can be programmed as wakeup I/O pins.
IOD: bi-directional I/O ports
These pins can be programmed as wakeup I/O pins.
Regulator - related power
VDD_RGI
VSS
P
G
P
Positive supply for regulator
Ground for Regulator
VDD
Power output from regulator out
Clock (max. frequency: 16Mhz)
XI
O
Crystal input or connected to VDD through a resistor for ROSC
Crystal output
XO
O
Audio
AVDD
P
G
P
G
O
O
I
Power for amplifier
GND for amplifier
Power for DAC
GND for DAC
AVSS
AVDD_DAC
AVSS_DAC
AUD0
Audio output
AUD1
Audio output
ACIN
Microphone input
Other Signal
TEST
I
I
TEST Mode selection pin, NC for normal application
System reset pin (active low)
RESETB
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GPCD2T020A
5.2. LQFP48 Package Pin Assignment
5.2.1. GPCD2T020A (LQFP48-type1)
48 47 46 45 44 43 42 41 40 39 38 37
1
36
NC
NC
NC
NC
NC
AVSS/AVSS_DAC
IOD[7]
2
3
35
34
33
32
31
30
29
28
27
26
25
IOD[6]
4
IOD[5]
5
IOD[4]
NC
6
NC
NC
GPCD2T020A
7
NC
VDDIO1
IOB[0]
IOB[1]
IOB[2]
IOB[3]
8
NC
9
NC
10
11
12
VDDIO0
IOA[7]
IOA[6]
14 15 16 17 18 19 20 21 22 23 24
13
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GPCD2T020A
Pin No.
Mnemonic
Type
Description
(LQFP48)
Dedicate IO
VDDIO0
VSSIO0
27
40
8
P
G
P
Power for IOA/IOD
GND for all IOA/IOD
Power for IOB
VDDIO1
VSSIO1
40
G
GND for all IOB
IOA: bi-directional I/O ports
IOA0~IOA7
IOB0~IOB7
IOD4~IOD7
19~26
9~16
I/O
I/O
I/O
These pins can be programmed as wakeup I/O pins.
IOB: bi-directional I/O ports
These pins can be programmed as wakeup I/O pins.
IOD: bi-directional I/O ports
32~35
These pins can be programmed as wakeup I/O pins.
Regulator - related power
VDD_RGI
VSS
43
40
42
P
G
P
Positive supply for regulator
Ground for regulator
VDD
Power output from regulator out
Clock (Max. Freq. 16Mhz)
XI
46
47
O
O
Crystal input or connected to VDD through a resistor as ROSC
Crystal output
XO
Audio
AVDD
38
36
38
36
39
40
-
P
G
P
G
O
O
I
Power for amplifier
GND for amplifier
Power for DAC
GND for DAC
AVSS
AVDD_DAC
AVSS_DAC
AUD0
Audio output
AUD1
Audio output
ACIN
Microphone input
Other Signal
TEST
45
44
I
I
TEST Mode selection pin, NC for normal application
System reset pin (active low)
RESETB
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GPCD2T020A
5.2.2. GPCD2T020A (LQFP48-type2)
48 47 46 45 44 43 42 41 40 39 38 37
1
IOD[7]
IOD[6]
IOD[5]
IOD[4]
NC
36
XO
NC
NC
NC
NC
2
3
35
34
33
32
31
30
29
28
27
26
25
4
5
NC
6
NC
NC
GPCD2T020A
7
NC
NC
8
NC
9
VSS
NC
10
11
12
VDDIO0
IOA[7]
IOA[6]
VDDIO1
IOB[0]
IOB[1]
14 15 16 17 18 19 20 21 22 23 24
13
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GPCD2T020A
Pin No.
Mnemonic
Type
Description
(LQFP48)
Dedicate IO
VDDIO0
VSSIO0
27
28
10
28
P
G
P
Power for IOA/IOD
GND for all IOA/IOD
Power for IOB
VDDIO1
VSSIO1
G
GND for all IOB
IOA: bi-directional I/O ports
IOA0~IOA7
IOB0~IOB7
IOD4~IOD7
19~26
11~18
33~36
I/O
I/O
I/O
These pins can be programmed as wakeup I/O pins.
IOB: bi-directional I/O ports
These pins can be programmed as wakeup I/O pins.
IOD: bi-directional I/O ports
These pins can be programmed as wakeup I/O pins.
Regulator - related power
VDD_RGI
VSS
45
28
44
P
G
P
Positive supply for regulator
Ground for regulator
VDD
Power output from regulator out
Clock (Max. Freq. 16Mhz)
XI
48
1
O
O
Crystal input or connected to VDD through a resistor as ROSC
Crystal output
XO
Audio
AVDD
41
37,39
41
P
G
P
G
O
O
I
Power for amplifier
GND for amplifier
Power for DAC
GND for DAC
AVSS
AVDD_DAC
AVSS_DAC
AUD0
39
42
Audio output
AUD1
40
Audio output
ACIN
38
Microphone input
Other Signal
TEST
47
46
I
I
TEST Mode selection pin, NC for normal application
System reset pin (active low)
RESETB
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GPCD2T020A
5.3. SOP16 Package Pin Assignment
5.3.1. GPCD2T020A (HS032)
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GPCD2T020A
Pin No.
Mnemonic
Type
Description
(SOP16)
Dedicate IO
VDDIO0/VDDIO1
VSSIO0/VSSIO1
13
14
P
Power for IOA/IOB/IOD
GND for all IOA/IOB/IOD
IOA: bi-directional I/O ports
G
IOA1~2
2~3
I/O
I/O
These pins can be programmed as wakeup I/O pins.
IOB: bi-directional I/O ports
IOB0~IOB2
NC
15~16,1
4~5
These pins can be programmed as wakeup I/O pins.
NC NC
Regulator - related power
VDD_RGI
VSS
13
14
12
P
G
P
Positive supply for regulator
Ground for regulator
VDD
Power output from regulator out
Audio
AVDD
7
6,8
7
P
G
P
Power for amplifier
GND for amplifier
Power for DAC
GND for DAC
Audio output
AVSS
AVDD_DAC
AVSS_DAC
AUD0
8
G
O
O
10
9
AUD1
Audio output
Note1: only internal R-oscillator (only 16MHz available for IOSC) for system operating clock
Note2: without SPI application
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GPCD2T020A
5.3.2. GPCD2T020A (HS031)
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Version: 1.1
GPCD2T020A
Pin No.
Mnemonic
Type Description
(SOP16)
Dedicate IO
VDDIO0
8
10
7
P
P
G
Power for IOA/IOD
VDDIO1
Power for IOB
VSSIO0/VSSIO1
GND for all IOA/IOB/IOD
IOA: bi-directional I/O ports
IOA1~3, IOA6~7
IOB0~1, IOB5~7
16,1~4
I/O
I/O
These pins can be programmed as wakeup I/O pins.
IOB: bi-directional I/O ports
12,11,13~15
These pins can be programmed as wakeup I/O pins.
Regulator - related power
VDD_RGI
VSS
8
7
P
G
P
Positive supply for regulator
Ground for regulator
VDD
10
Power output from regulator out
Audio
AVDD
8
7
8
7
5
6
P
G
P
Power for amplifier
GND for amplifier
Power for DAC
GND for DAC
Audio output
AVSS
AVDD_DAC
AVSS_DAC
AUD0
G
O
O
AUD1
Audio output
Note1: Only internal R-oscillator (only 16MHz available for IOSC) for system operating clock
Note2: with SPI application
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GPCD2T020A
6. FUNCTION DESCRIPTION
6.1. SRAM
6.5. Hardware PWMIO
The 512-byte SRAM (including Stack) area is located in
$000000h~$0003FFh.
Hardware PWMIO supports 12 LED outputs (IOA[3:0],IOB[3:0],
IOD[7:4]) with 256-level brightness control. The clock source of
PWMIO can be selected by user’s request.
6.2. ROM
6.6. I/O
GPCD2T020A is equipped with 64K-bytes factory programmed
OTP memory.
The purpose of input and output ports is to communicate with
other devices.
Four programmable I/O ports are built-in,
6.3. Low Voltage Reset
including Port A, B, and D. All Ports are general I/O with
programmable wake-up capability and pull low function. In
addition to general I/O function, I/O also provides some special
functions in certain pins.
GPCD2T020A features an important feature, Low Voltage Reset
(LVR). With the LVR function, a reset signal is generated to
reset system when the operating voltage drops under LVR.
Without LVR, CPU becomes unstable and abnormal when
working voltage is too low.
6.7. Timer/Counter (Timer A/Timer B/Timer C)
Three 12-bit timers are embedded in GPCD2T020A: Timer A,
Timer B, and Timer C. These three timers all have 12-bit up
counter, a preloaded register, and programmable clock source.
Timer A/B can also be the clock source of the software channel
1/2 respectively. The clock source of each timer can be set
6.4. Interrupt
GPCD2T020A has two interrupt (INT) modes: IRQ (interrupt
Request) and NMI (Non-Mask Interrupt Request). The interrupt
controller controls 17 IRQs and 6 NMIs. A NMI cannot be
interrupted by any other IRQ.
individually.
Two clock sources, including CPU clock and
external clock, can be selected individually or their combination to
be timer’s clock source. Besides, capture and comparison
function are supported by TMA. Comparison is supported by
TMB and TMC.
Interrupt Source
Timer A
Interrupt Name
NMI_TIMER_A
NMI_TIMER_B
NMI_TIMER_C
NMI_D1024
NMI_D4096
NMI_EXT
Priority
NMI
Timer B
NMI
Timer C
NMI
CPU_CLOCK/1024
CPU_CLOCK/4096
EXT
NMI
6.8. Sleep, Wakeup and Watchdog
6.8.1. Sleep and Wakeup
NMI
NMI
Sleep mode is designed to save power by stopping clock while
device is not in use. When sleep acts, the device runs from
operating mode to standby mode. Waking up from sleep mode
turns system back to operating mode.
Timer A
IRQ_TIMER_A
IRQ_TIMER_B
IRQ_TIMER_C
IRQ_D1024
IRQ_D4096
IRQ_16Hz
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
Timer B
Timer C
CPU_CLOCK/1024
CPU_CLOCK/4096
16 Hz
(1) Sleep: After power on reset, IC starts working until a sleep
command is given. When a sleep signal is accepted, IC will
turn off system clock and enter sleep mode.
TBL
IRQ_TBL
(2) Wake-up: While a wakeup signal is generated, GPCD2T020A
is waking up from sleep mode. While wake-up is completed,
program counter will continue to execute the next command of
where entering sleep.
KEY
IRQ_KEY
EXT
IRQ_EXT
SPI
IRQ_SPI
QD1_F
IRQ_QD1_F
IRQ_QD1_B
IRQ_QD2_F
IRQ_QD2_B
IRQ_CTS_TMA
IRQ_CTS_TMB
IRQ_CMPIO
QD1_B
6.8.2. Watchdog
QD2_F
The purpose of watchdog is to monitor system’s operation
normally. Within a certain period, watchdog must be cleared.
It protects the system from incorrect code execution by generating
a system reset when software fails to clear watchdog flag within
around 0.67 seconds.
QD2_B
CTS_TMA
CTS_TMB
CMPIO
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GPCD2T020A
6.9. Speech and Push-Pull
SPICLK
GPCD2T020A uses two 14-bit software channels with noise filter
is also supported. There is one 14-bit PUSH-PULL driver for
direct audio output.
SPICSN
SPIRX
Q
MSB
MSB
LSB
LSB
Q
6.10. Comparator
A set of comparator is embedded in GPCD2T020A. Users can
using the comparator to sample specific signal.
SPITX
SPIOE
8 bits
6.11. Capacitive Touch Sensor (CTS) and CTS Timers
GPCD2T020A provides hardware Capacitive Touch Sensor. It is
provided that the ability to perform capacitive sensing, decision
making, responsive actions and other duties pertinent to the
system as well.
Master Mode, SPO = 0, SPH=1
6.12. SPI Controller
SPICLK
A
Serial Peripheral Interface (SPI) controller is built-in
SPICSN
SPIRX
GPCD2T020A to facilitate communicating with other devices and
components. There are four control signals on SPI including
SPITX(SDO), and SPIRX(SDI), SPICLK(SCK) and SPICSN; the
four signals are shared with PortA3, PorA2, PortA1 and PortA0 or
PortB7, PortB6, PortB5 and PortB4. While SPI module is
enabled by corresponding control bit. These four pins cannot be
GPIOs and any setting on corresponding GPIO control register will
have no effect. Four types of timing are supported as follows:
MSB
MSB
LSB
Q
SPITX
SPIOE
LSB
8 bits
Master Mode, SPO = 1, SPH=0
SPICLK
SPICSN
SPICLK
SPIRX
SPITX
MSB
MSB
LSB MSB
LSB MSB
SPICSN
SPIRX
Q
MSB
MSB
LSB
Q
8 bits
SPITX
SPIOE
LSB
SPIOE
8 bits
Master Mode, SPO = 0, SPH=0
Master Mode, SPO = 1, SPH=1
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GPCD2T020A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
DC Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
Symbol
V+
Ratings
< 7.0V
VIN
-0.5V to V+ + 0.5V
0℃ to +70℃
TA
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions
see DC Electrical Characteristics.
7.2. DC Characteristics (VDDIO/VDD_RGI=3.0V, TA=25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
For 2-battery
Min.
Typ.
Max.
Operating Voltage
VDD
IOP1
2.2
3.0
3.6
V
VDDIO/AVDD /VDD_RGI=3.0V FCPU
8MHz , PWM on, no load
=
=
Operating Current-1
-
-
8
6
11
8
mA
VDDIO/AVDD /VDD_RGI=3.0V FCPU
8MHz , PWM off, no load
Operating Current-2
IOP2
mA
Standby Current
ISTBY
FOSC
VIH
-
-
-
-
-
-
-
7
A
VDDIO/AVDD/VDD_RGI=3.0V
OSC Frequency
-
16
MHz VDDIO/AVDD/VDD_RGI=3.0V
Input High Level-1
Input Low Level-1
0.7*VDDIO
-
V
V
V
V
With Schmitt trigger
With Schmitt trigger
Without Schmitt trigger
Without Schmitt trigger
VDDIO/AVDD/VDD_RGI=3.0V,
VOH =2.1V
VIL
-
0.3*VDDIO
-
Input High Level-2
Input Low Level-2
VIH
0.6*VDDIO
-
VIL
0.4*VDDIO
Output High Current
(IOA/B, IOD[7:4])
IOH
IOL1
IOL2
RPL
RPL
RPH
3.5
7
5
10
20
800
80
80
6.5
13
mA
mA
Output Low Sink Current
(IOA/B[7:4])
VDDIO/AVDD/VDD_RGI=3.0V,
VOL =0.9V
Output Low Sink Current
(IOA/B[3:0], IOD[7:4])
Input Pull-Low Resistor-1
(IOA/B, IOD[7:4])
VDDIO/AVDD/VDD_RGI=3.0V,
VOL =0.9V
10
550
55
55
30
mA
VDDIO/AVDD/VDD_RGI=3.0V,
Vin=3.0V
1100
110
110
Kohm
Kohm
Kohm
Input Pull-Low Resistor-2
(IOA/B, IOD[7:4])
VDDIO/AVDD/VDD_RGI=3.0V,
Vin=3.0V
Input Pull-High Resistor
(IOA/B, IOD[7:4])
VDDIO/AVDD/VDD_RGI=3.0V,
Vin=VSS
IROSC16M Frequency
deviation for chip (lot
deviation) *
FI16M
-1
-
+1
%
VDDIO/AVDD/VDD_RGI=3.0V
IROSC16M Frequency
deviation for LQFP48
EROSC16M Frequency
deviation(lot deviation)
FI16M-LQFP48
FE16M
-3
-7
-
-
+3
+7
%
%
VDDIO/AVDD/VDD_RGI=3.0V
VDDIO/AVDD/VDD_RGI=3.0V
*Note: IROSC16M Frequency deviation is without epoxy on chip.
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GPCD2T020A
7.3. DC Characteristics (VDDIO/VDD_RGI=4.5V, TA=25℃)
Limit
Typ.
4.5
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
VDD
IOP1
2.2
5.5
V
For 3-battery
VDDIO/AVDD/VDD_RGI=4.5V FCPU
=
=
Operating Current-1
-
-
11
7
15
10
mA
8MHz , PWM on, no load
VDDIO/AVDD/VDD_RGI=4.5V FCPU
8MHz , PWM off, no load
Operating Current-2
IOP2
mA
Standby Current
ISTBY
FOSC
VIH
-
-
-
-
-
-
-
7
A
VDDIO/AVDD/VDD_RGI=4.5V
OSC Frequency
-
16
MHz VDDIO/AVDD/VDD_RGI=4.5V
Input High Level-1
Input Low Level-1
0.7*VDD
-
V
V
V
V
With Schmitt trigger
With Schmitt trigger
Without Schmitt trigger
Without Schmitt trigger
VDDIO/AVDD/VDD_RGI=4.5V,
VOH =3.15V
VIL
-
0.3*VDD
-
Input High Level-2
Input Low Level-2
VIH
0.6*VDD
-
VIL
0.4*VDD
Output High Current
(IOA/B, IOD[7:4])
IOH
IOL1
IOL2
RPL
RPL
RPH
7
14
20
550
55
55
10
20
13
26
mA
mA
Output Low Sink Current
(IOA/B[7:4])
VDDIO/AVDD/VDD_RGI=4.5V,
VOL =1.35V
Output Low Sink Current
(IOA/B[3:0], IOD[7:4])
Input Pull-Low Resistor-1
(IOA/B, IOD[7:4])
VDDIO/AVDD/VDD_RGI=4.5V,
VOL =1.35V
40
60
mA
VDDIO/AVDD/VDD_RGI=4.5V,
Vin=4.5V
800
80
1100
110
110
Kohm
Kohm
Kohm
Input Pull-Low Resistor-2
(IOA/B, IOD[7:4])
VDDIO/AVDD/VDD_RGI=4.5V,
Vin=4.5V
Input Pull-High Resistor
(IOA/B, IOD[7:4])
VDDIO/AVDD/VDD_RGI=4.5V,
Vin=VSS
80
IROSC16M Frequency
deviation for chip (lot
deviation)*
FI16M
-1
-
+1
%
VDDIO/AVDD/VDD_RGI=4.5V
IROSC16M Frequency
deviation for LQFP48
EROSC16M Frequency
deviation(lot deviation)
FI16M-LQFP48
FE16M
-3
-7
-
-
+3
+7
%
%
VDDIO/AVDD/VDD_RGI=4.5V
VDDIO/AVDD/VDD_RGI=4.5V
*Note: IROSC16M Frequency deviation is without epoxy on chip.
7.4. DAC Characteristics (VDDIO/VDD_RGI/AVDD =4.5V, RL=8Ω, f=1KHz, TA=25℃)
Limit
Characteristics
DAC Resolution
Symbol
Unit
Min.
Typ.
Max.
RESO
-
-
-
-
-
14
-
bit
%
THD+n(5V@0.7W)
Noise at No Signal
--
-
1
-100
-80
-
dBr A
dBr A
Dynamic Range (-60dB)
-
-
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GPCD2T020A
7.5. Regulator Characteristics (TA=25℃)
Limit
Characteristics
Input Voltage
Symbol
Unit
Test Condition
Min. Typ. Max.
VREGI
IREGO
2.1
-
-
5.5
40
V
mA
V
VDD_RGI (Regulator in )= 4.5V,△VDD (Regulator out) <100mV
Maximum Current Output
Output Voltage
-
V3_REGO 3.14
IREGS
3.3
2.5
3.47
-
VDD_RGI > 3.5V and V3_REGO is 3.3V
Standby Current
-
uA
7.6. The EROSC Relationship between ROSC and FOSC
7.8. The IROSC Relationship between VDD and FOSC
(TA=25℃)
(TA=25℃)
7.7. The EROSC Relationship between VDD and FOSC
(TA=25℃)
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GPCD2T020A
8. APPLICATION CIRCUITS
8.1. GPCD2T020A Application Circuit with External ROSC Mode (ROSC-mode)
Note*1: These capacitor values are for design guidance only. Adding 10uF and 0.1uF capacitors in parallel to each power group are recommended for noise
sensitive application. The recommended features are ESR=0.05~1Ω
Note*2: R1=33K ohm for 16MHz clock and R1=43K ohm for 12MHz clock.
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GPCD2T020A
8.2. GPCD2T020A Application Circuit with 16MHz X’tal (XTAL-mode)
Note*1: These capacitor values are for design guidance only. Adding 10uF and 0.1uF capacitors in parallel to each power group are recommended for noise
sensitive application. The recommended features are ESR=0.05~1Ω
Note*2: These capacitor values are for design guidance only. The recommended features are ESR=11.2~60K and C4=C5=18~28pF (including PCB parasitic
loading, for example, user should apply additional 12~22pF on XI and XO if PCB parasitic loading is 6pF)
Note*3: 16MHz X’tal or 12Mhz X’tal can be used for different speed applications.
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GPCD2T020A
8.3. GPCD2T020A 32K X’tal Application Circuit
25p C1*
32768Hz
IOB4
VSSB
IOB5
25p C2*
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~60K and C1=C2 =26~36pF (including PCB
parasitic loading, for example, user should apply additional 20~30pF on X32I and X32O if PCB parasitic loading is 6pF)
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GPCD2T020A
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
GPCD2T020A-NnnV-C
GPCD2T020A-NnnV-QL23x
GPCD2T020A-NnnV-HS03x
Chip form
Green Package – LQFP48
Green Package – SOP16
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 1 - 9, serial number).
9.2. Package Information
9.2.1. LQFP 48
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GPCD2T020A
9.2.2. SOP 16
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GPCD2T020A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPCD2T020A
11. REVISION HISTORY
Date
Revision #
Description
Page
Nov. 16, 2018
May 17, 2018
1.1
1.0
Modify Package SOP-16 information.
Original
11,13
26
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