GPCE063A [GENERALPLUS]
16-Bit Sound Controller with 32K X 16 Flash Memory;
| 型号： | GPCE063A |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 16-Bit Sound Controller with 32K X 16 Flash Memory |
| 文件： | 总29页 (文件大小：668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCE063A
16-Bit Sound Controller with
32K X 16 Flash Memory
Oct. 04, 2013
Version 1.8
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCE063A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 4
2. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
3. FEATURES.................................................................................................................................................................................................. 4
4. APPLICATION FIELD.................................................................................................................................................................................. 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. GPCE063A PAD ASSIGNMENT .............................................................................................................................................................. 6
5.2. GPCE064A PAD ASSIGNMENT .............................................................................................................................................................. 7
5.3. GPCE063A PIN MAP............................................................................................................................................................................ 8
5.4. GPCE064A PIN MAP............................................................................................................................................................................ 9
6. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 10
6.1. CPU ................................................................................................................................................................................................... 10
6.2. MEMORY ............................................................................................................................................................................................. 10
6.2.1. SRAM...................................................................................................................................................................................... 10
6.2.2. Flash Memory ......................................................................................................................................................................... 10
6.3. PLL, CLOCK, POWER MODE................................................................................................................................................................. 10
6.3.1. PLL (Phase Lock Loop)........................................................................................................................................................... 10
6.4. STANDBY MODE................................................................................................................................................................................... 10
6.5. LOW VOLTAGE DETECTION AND LOW VOLTAGE RESET............................................................................................................................11
6.5.1. Low Voltage Detection (LVD) ...................................................................................................................................................11
6.5.2. Low Voltage Reset...................................................................................................................................................................11
6.6. INTERRUPT...........................................................................................................................................................................................11
6.7. I/O.......................................................................................................................................................................................................11
6.8. SPECIAL FUNCTION IN PORT................................................................................................................................................................. 12
6.9. TIMER / COUNTER................................................................................................................................................................................ 13
6.9.1. IO PWM .................................................................................................................................................................................. 14
6.9.2. Timebase ................................................................................................................................................................................ 14
6.10.SLEEP MODE, WAKEUP, HALT MODE, AND WATCHDOG .......................................................................................................................... 14
6.10.1. Sleep and Wakeup Modes ................................................................................................................................................. 14
6.10.2. Watchdog Reset................................................................................................................................................................. 14
6.11.SOFT RESET PROTECTION ................................................................................................................................................................... 15
6.12.ADC (ANALOG TO DIGITAL CONVERTER) / DAC .................................................................................................................................... 15
6.13.SPI..................................................................................................................................................................................................... 15
6.14.AUDIO ALGORITHM............................................................................................................................................................................... 15
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 16
7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 16
7.2. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 4.5V (PORTA & B), TA = 25℃)...................................................................................... 16
7.3. DC CHARACTERISTICS (VDD = 3.3V, VDDIO = 3.3V (PORTA & B), TA = 25℃)...................................................................................... 16
7.4. ADC CHARACTERISTICS (VDD = 3.3V, TA = 25℃)................................................................................................................................ 16
7.5. DAC CHARACTERISTICS (VDD = 3.3V, TA = 25℃)................................................................................................................................ 16
7.6. PULL HIGH RESISTER AND VDDIO........................................................................................................................................................ 18
7.7. PULL LOW RESISTER AND VDDIO(NORMAL PAD) ................................................................................................................................. 18
7.8. PULL LOW RESISTER AND VDDIO(IOB[7:0] PAD WITH INPUT HIGH)....................................................................................................... 18
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GPCE063A
7.9. I/O OUTPUT HIGH CURRENT IOH AND VDDIO ...................................................................................................................................... 18
7.10.I/O OUTPUT LOW CURRENT IOL AND VDDIO(NORMAL PAD) ................................................................................................................... 18
7.11.I/O OUTPUT LOW CURRENT IOL AND VDDIO(HIGH DRIVING PAD)............................................................................................................ 18
7.12.DAC OUTPUT CURRENT IOLAND AVDD............................................................................................................................................... 19
8. APPLICATION CIRCUITS......................................................................................................................................................................... 20
8.1. APPLICATION CIRCUIT (1)..................................................................................................................................................................... 20
8.2. APPLICATION CIRCUIT (2)..................................................................................................................................................................... 21
8.3. APPLICATION CIRCUIT (3)..................................................................................................................................................................... 22
8.4. APPLICATION CIRCUIT (4)..................................................................................................................................................................... 23
8.5. APPLICATION CIRCUIT (5)..................................................................................................................................................................... 24
8.6. APPLICATION CIRCUIT (6)..................................................................................................................................................................... 25
8.7. APPLICATION CIRCUIT (7)..................................................................................................................................................................... 26
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 27
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 27
9.2. PACKAGE INFORMATION....................................................................................................................................................................... 27
10.DISCLAIMER............................................................................................................................................................................................. 28
11. REVISION HISTORY ................................................................................................................................................................................. 29
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Version: 1.8
GPCE063A
16-BIT SOUND CONTROLLER
WITH 32K X 16 FLASH MEMORY
1. GENERAL DESCRIPTION
3. FEATURES
The GPCE063A, a 16-bit architecture product, carries the newest
16-bit microprocessor, μ’nSP™ (pronounced as micro-n-SP),
developed by Sunplus Technology. This high processing speed
assures the μ’nSP™ is capable of handling complex digital signal
16-bit μ’nSP™ microprocessor
CPU clock: 0.16MHz - 49.152MHz
Operating voltage: 2.7V - 3.6V
Program Flash Operating voltage: 2.7V - 3.6V
IO PortA & B operating voltage: 2.7V - 5.5V
32K-word flash memory
processes easily and rapidly.
Therefore, GPCE063A is
applicable to the areas of digital sound process and voice
recognition. The operating voltage of 2.7V through 3.6V and
speed of 0.16MHz through 49.152MHz yield the GPCE063A to
be easily used in varieties of applications. The memory capacity
includes 32K-word flash memory plus a 2K-word working SRAM.
Other features include 32 programmable multi-functional I/Os,
three 16-bit timers/counters, 32768Hz Real Time Clock, Low
Voltage Reset/Detection, eight channels 12-bit ADC (one channel
built-in MIC amplifier with auto gain controller), 14-bit DAC output
and many others.
2K-word working SRAM
Software-based audio processing
Standby mode for power saving
Three 16-bit timers/counters
One 14-bit DAC output
32 general I/Os (bit programmable)
Key wakeup function (IOA0 - 15)
PLL feature for system clock
32768Hz Real Time Clock (RTC)
Eight channels of 12-bit AD converter
ADC external top reference voltage
Built-in microphone amplifier and AGC function
Low voltage reset and low voltage detection
Watchdog enable (option)
2. BLOCK DIAGRAM
Flash ROM
32K word
un'SP
ICE function for development and download into flash memory
Security function to protect code to be read and written
One SPI serial interface I/O
16-bits CPU
DAC
DAC
MICIN
PLL / System clock /
MICIP
MICO
OPI
AGC
V_MIC
X32I
Data retention > 10 years
AD Converter
MIC
X32O
Reset Function
AVREF_TOP
2K(word) Working
SRAM
TimeBase/WatchDog
16-bits Counter/Timer
/ Interrupt
4. APPLICATION FIELD
RESETB
SPI
Memory Mapping & Control
/ GPIO Special Function
/ PWM output
Voice recognition products
Intelligent interactive talking toys
Advanced educational toys
Kid’s learning products
General I/O Port
IOA[15:0]
IOB[15:0]
Kid’s storybook
General speech synthesizer
Long duration audio products
Recording / playback products
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GPCE063A
5. SIGNAL DESCRIPTIONS
Mnemonic
PORT A, Port B
IOA[15:0]
PIN No.
LQFP 64 PIN No. Type
Description
26-35, 38-43
28-37, 40-45
I/O IOA[15:0]: bi-directional I/O ports
It can be programmed as wakeup I/O pins
I/O IOB [15:0]: bi-directional I/O ports
IOB[15:0]
4-1, 57-54,
14-11, 8-5
6-3, 64-61,
16-13, 10-7
Power & GND
VDDIOA
VSSIOA
VDDIOB
VSSIOB
AVDD
36
37
9
38
39
11
12
25
23
54
53
P
G
P
G
P
G
P
G
Power vdd for Port A
Power gnd for Port A
Power vdd for Port B
10
23
21
47
46
Power gnd for Port B
Power vdd for AD,DA (3.3V)
Power gnd for AD,DA
AVSS
VDD
Power vdd for Core + PLL (3.3V)
Power gnd for Core + PLL
VSS
CLK SYSTEM/ ICE INTERFACE
X32I
45
44
52
51
I
32K Oscillator crystal input
32K Oscillator crystal output
X32O
OPTION
TEST
O
51
53
58
60
I
I
TEST Mode selection pin, high is test mode and low is normal mode
(Pad internal pull low)
TFLASH
TEST flash Mode selection pin, high is test mode and low is normal
mode (Pad internal pull low)
DAC
DAC
24
26
O
Audio DAC output
ADC
MICP
19
18
17
16
15
22
20
21
20
19
18
17
24
22
I
I
MIC amplifier input positive (Internal Floating)
MIC amplifier input negative (refer to application circuit)
MIC amplifier output (refer to application circuit)
Audio amplifier negative input (refer to application circuit)
AGC by pass filter (refer to application circuit)
Microphone power supply
MICN
MICOUT
OPI
O
I
AGC
IO
O
O
VMIC
VADREF
PLL
AVREF_DA reference pin
VCOIN
Other Signal
RESETB
ICE_EN
ICE_CLK
ICE_SDA
Total: 57 pads
25
27
I
PLL low pass filter input
52
50
48
49
59
57
55
56
I
I
I
System reset pin (active low) (internal 47Kohm pull high resistor)
ICE enable pin
ICE clock input pin
I/O ICE data pin
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GPCE063A
5.1. GPCE063A PAD Assignment
Important Note:
Please refer to pad assignment of both GPCE063A and GPCE064A, blue words mean their differences. Because there's some system
circuit in built-in regulator of GPCE064A, user must connect regulator power input VDD_REG to power input, and connect regulator
output VDD33_REG to capacitance 2.2uF even if there's no need to use this regulator.
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GPCE063A
5.2. GPCE064A PAD Assignment
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GPCE063A
5.3. GPCE063A PIN Map
Important Note:
Please refer to pad assignment of both GPCE063A and GPCE064A, blue words mean their differences. Because there's some system
circuit in built-in regulator of GPCE064A, user must connect regulator power input VDD_REG to power input, and connect regulator
output VDD33_REG to capacitance 2.2uF even if there's no need to use this regulator. Please take reference to GPCE064A data sheet
section 8.APPLICATION CIRCUITS.
LQFP64
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GPCE063A
5.4. GPCE064A PIN Map
LQFP64
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GPCE063A
6.FUNCTIONAL DESCRIPTIONS
6.1. CPU
6.2. Memory
6.2.1. SRAM
GPCE063A is equipped with a 16-bit μ’nSP™, the newest 16-bit
microprocessor by Sunplus and pronounced as micro-n-SP.
The amount of SRAM is 2K-word (including Stack), ranged from
$0000 through $07FF with access speed of two CPU clock
cycles.
Eight registers are involved in μ’nSP™: R1
-
R4
(General-purpose registers), PC (Program Counter), SP (Stack
Pointer), Base Pointer (BP) and SR (Segment Register). The
interrupts include three FIQs (Fast Interrupt Request) and eight
IRQs (Interrupt Request), plus one software-interrupt, BREAK.
Phase Lock Loop
Fosc/n
CPU Clock
FOSC
32768Hz X'tal
(PLL)
PLL OUT
24.576MHz(default)
20.48MHz
System Clock generator
n:1,2,4,8,16,32,64
(Default : Fosc/8)
32.768MHz
40.96MHz
49.152MHz
b2 b1 b0
b7
b6
b5
b7,b6,b5 of P_SystemClock(W )($2030H)
System clock frequency selection
of P_SystemClock(W )($2030H)
CPU clock frequency selection
6.2.2. Flash Memory
of RTC occurrence. In addition, GPCE063A supports 32768Hz
oscillator in normal mode and auto-power-saving mode. In
normal mode, 32768Hz OSC always runs at the highest power
consumption. In auto-power-saving mode, however, it runs in
normal mode for the first 7.5 seconds and changes back to
power-saving mode automatically to save powers.
Flash memory ($8000 ~ $FFFF) is a high-speed memory with
access speed of two CPU clock cycles. FLASH erase and
program functions must be used in IDE tools.
6.3. PLL, Clock, Power Mode
6.3.1. PLL (Phase Lock Loop)
6.4. Standby Mode
The purpose of PLL is to provide a base frequency (32768Hz)
and to pump the frequency from 20.48MHz to 49.152MHz for
system clock (FOSC). The default PLL frequency is 24.576MHz.
The GPCE063A features a power savings mode (or called
standby mode) for low power applications. To enter standby
mode, the desired key wakeup port (IOA[15:0]) must be
configured to input first. And read the Port_IOA_Data to latch
6.3.1.1. System Clock
the IOA state before entering the standby mode.
Also
Basically, the system clock is provided by PLL and programmed
by the Port_SystemClock (W) to determine the frequency of clock
for system. The default system clock FOSC = 24.576MHz and
CPU clock is FOSC/8 if not specified. The initial CPU clock is
Fosc/8 after system wakes up and to be adjusted to needed CPU
clock by programming the Port_SystemClock (W). This avoids
Flash ROM reading failure when system wakes up.
remember to enable the corresponding interrupt source(s) for
wakeup. After that, stop the CPU clock by writing $5555 into
Port_SystemSleep(W) to enter standby mode. In such mode,
SRAM and I/Os remain in the previous states until CPU being
awakened. The wakeup sources in GPCE063A include KEY
wake up (IOA[15:0]), RTC wakeup, and IRQ1 – IRQ7. After
GPCE063A is awakened, CPU will continue to execute the
program from the location it slept. Programmer can also enable
or disable the 32768Hz RTC when CPU is in standby mode.
6.3.1.2. 32768Hz RTC
The Real Time Clock (RTC) is normally used in watch, clock or
other time related products. A 2Hz-RTC (1/2 seconds) function
is loaded in GPCE063A. The RTC counts the timing as well as
to wake CPU up whenever RTC occurs. Since the RTC is
generated each 0.5 seconds, time can be traced by the numbers
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GPCE063A
6.5. Low Voltage Detection and Low Voltage Reset
6.5.1. Low Voltage Detection (LVD)
Interrupt Source Interrupt Name / FIQ Name IRQ Priority
512Hz
64Hz
16Hz
2Hz
IRQ6_512Hz/FIQ_512Hz
IRQ7_64Hz/FIQ_64Hz
IRQ7_16Hz_FIQ_16Hz
IRQ7_2Hz/FIQ_2Hz
10
11
The Low Voltage Detect (LVD) reports the circumstance of
present voltage. There are four LVD levels available: 2.6V, 2.8V,
12
13(Low)
3.0V, and 3.2V.
Those levels can be programmed via
P_LVD_Ctrl. As an example, suppose LVD is given to 2.8V.
When the voltage drops below 2.8V, the b12 of P_LVD_Ctrl is
read as HIGH. In such state, program can be designed to react
this condition.
6.7. I/O
Three I/O ports are built-in GPCE063A - PortA and PortB, total
has 32 bit-programmable I/Os. The PortA is a general purpose
I/O with programmable wakeup capability, i.e. IOA [15:0] is the
key wakeup port. To activate key wakeup function, latch data on
Port_IOA_Data and enable the key wakeup function. Wakeup is
triggered when PortA’s state is different from at the time latched.
Furthermore, the I/O ports can be operated at 5V level, higher
than the CPU core which is a 3V level system. Suppose system
operating voltage is running at 3.3V and VDDIO (power for I/O)
operates from 3.3V to 5.5V. In such condition, the I/O pad is
capable of operating from 0V through VDDIO. The following
diagram is an I/O schematic. Although data can be written into
the same register through Port_Data and Port_Buffer, they can
be read from different places, Buffer (R) and Data (R).
6.5.2. Low Voltage Reset
In addition to LVD, GPCE063A has another important function,
Low Voltage Reset (LVR). With the LVR function, a reset signal
is generated to reset system when the operating voltage drops
below LVR level. Without LVR, the CPU becomes unstable and
malfunctions when the operating voltage drops below LVR level.
The LVR will reset all functions to the initial operational (stable)
states when the voltage drops below LVR level.
6.6. Interrupt
The GPCE063A has 13 interrupt sources, grouped into two types,
FIQ (Fast Interrupt Request) and IRQ (Interrupt request). The
priority of FIQ is higher than IRQ. FIQ is the high-priority
interrupt while IRQ is the lower one. An IRQ can be interrupted
by a FIQ, but not by another IRQ. A FIQ cannot be interrupted
by any other interrupt sources.
Buffer(R)
Port_Data(W)
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
Control
logic
Interrupt Source Interrupt Name / FIQ Name IRQ Priority
Timer A
Timer B
Timer C
SPI
IRQ0_TMA/FIQ_TMA
IRQ1_TMB/FIQ_TMB
IRQ2_TMC/FIQ_TMC
IRQ3_SPI/FIQ_SPI
1(High)
Data(R)
2
3
4
5
6
7
8
9
In addition to a general purpose I/O port function, PortA/B also
shares/carries some special functions. A summary of PortA/B
special functions is listed as follows:
Key wakeup
EXT1
IRQ5_KEY/FIQ_KEY
IRQ5_EXT1/FIQ_EXT1
IRQ5_EXT2/FIQ_EXT2
IRQ6_4KHz/FIQ_4KHz
IRQ6_2KHz/FIQ_2KHz
EXT2
4096Hz
2048Hz
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GPCE063A
6.8. Special Function in Port
Port
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
Special Function
Function Description
Note
IO_PWM
IROUT
IO_PWM output
Refer to Timer section
IR Output
-
-
-
-
-
-
-
High driving I/O
High driving I/O
High driving I/O
High driving I/O
Feedback Input1
EXT1
-
-
-
-
-
-
-
-
-
Refer to below Example 1
Set IOA8 as floating input mode
IOA8
IOA9
External interrupt source 1 (negative edge triggered)
Work with IOA8 by adding a RC circuit between them
Feedback Output1
Set IOA9 as inverted output
to get an OSC to EXT1 interrupt
Feedback Input2
EXT2
-
External interrupt source 2 (negative edge triggered)
Work with IOA10 by adding a RC circuit between them
to get an OSC to EXT2 interrupts
SPI chip select
Refer to below Example 1
IOA10
IOA11
Set IOA10 as floating input mode
Feedback Output2
Set IOA11 as inverted output
IOA12
IOA13
IOA14
IOA15
IOB0
IOB1
IOB2
IOB3
IOB4
IOB5
IOB6
IOB7
SPI CS
SPI CK
SPI TX
SPI RX
AN0
Refer to SPI section
Refer to SPI section
Refer to SPI section
Refer to SPI section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
Refer to ADC section
SPI clock
SPI data output
SPI data input
ADC Channel 0
AN1
ADC Channel 1
AN2
ADC Channel 2
AN3
ADC Channel 3
AN4
ADC Channel 4
AN5
ADC Channel 5
AN6
ADC Channel 6
AN7
ADC Channel 7
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GPCE063A
PWM: Pulse Width Modulation
Refer to the above table, the configuration of IOA9, IOA10, IOA11,
and IOA12 involves feedback function in which an OSC
frequency can be obtained from EXT1 (EXT2) by simply adding a
RC circuit between IOA8 (IOA10) and IOA9 (IOA11).
Example to Timer A, sending a write signal into TMA_CNT, the
value of TMA_DATA (value=N) will reload into TMA_CNT and set
an appropriated clock source. Timer wills up-count from N, N+1,
N+2… 0XFFFF. An INT signal is generated at the moment of
timer rolling over from “0xFFFF” to “0x0000”, and an INT signal is
processed by INT controller immediately. At the same time, N
will be reloaded into TMA_CNT and start counting again.
6.9. Timer / Counter
GPCE063A provides three 16-bit timers/counters
- TimerA,
TimerB and TimerC or so called universal counters. The clock
sources of Timer A/B/C are from clock source Input 1 and clock
source Input 2 (see below table) which perform AND operation to
form the varieties of combinations. When timer overflows, a
timeout signal (TAOUT) is sent to CPU interrupt module to
generate a timer interrupt signal. In addition, Timer A/B/C
hardware interrupt events can be used to latch the DAC audio
output and trigger ADC conversion.
In Timer A, the clock Input 1 is a high frequency source and clock
Input 2 is a low frequency clock source. The combination of
clock Input
1
and
2
provides varieties of speeds to
TimerA/CounterA - “1” representing pass signal (not gating), and
“0” meaning timer deactivated. For instance, if Input 1=”1”, the
clock is depending on Input 2. If Input 1=”0”, the TimerA is
deactivated. The EXT1/ETX2 is the external clock source 1 and
external clock source 2.
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Generally speaking, the clock source A and C are fast clock
sources and source B comes from RTC system (32768Hz).
Therefore, clock source B can be utilized as a precise counter for
time counting, e.g., the 2Hz clock can be used for real time
counting.
TMXSEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Input 1
‘0’
Input 2
‘0’
‘1’
‘1’
FRTC
FPLL
EXT2
EXT2
64Hz
16Hz
2Hz
‘1’
EXT2
EXT2
EXT2
EXT2
FRTC
FRTC
FRTC
FRTC
FPLL
6.9.1. IO PWM
One IO PWMs which duty is selected from 1/16 to 14/16. The
following figure is an example of 3/16-duration cycle. The
PWMO waveform is made by selecting a pulse width through
Port_PWM_Ctrl. As a result, each 16 cycles will generate a
pulse width defined in control port. These PWM signals can be
applied for controlling the speed of motor or other devices.
64Hz
16Hz
2Hz
‘1’
64Hz
16Hz
2Hz
‘1’
FPLL
FPLL
FPLL
TimerA_Timeout
Tpwmo
Tduty
PWMO
6.9.2. Timebase
Wakeup Source
FIQ source
Timebase, generated by 32768Hz crystal oscillator, is
a
Timer A interrupt
Timer B interrupt
Timer C interrupt
SPI interrupt
combination of frequency selection. Furthermore, timebase
generates 4KHz, 2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt
sources (FIQ6/IRQ6, FIQ7/IRQ7) for Real-Time-Clock.
6.10. Sleep Mode, Wakeup, Halt Mode, and Watchdog
6.10.1. Sleep and Wakeup Modes
EXT1/EXT2/KEY
RTC
1) Sleep: After power-on reset, IC starts running until a sleep
command is issued. When a sleep command is
accepted, IC will turn the system clock (PLL) off.
After all, it enters sleep mode.
6.10.2. Watchdog Reset
The GPCE063A provides another important feature, watchdog
reset. With the watchdog function, a reset signal is generated to
reset system when watchdog counter is overflow and the flash
information block option of OPTION_WDOG_EN is enabled.
2) Wakeup: CPU awaking from sleep mode requires a wakeup
signal to turn the system clock (PLL) on. The
FIQ/IRQ signal makes CPU to complete the
wakeup process and initialization. The CPU
wakeup source is given in the following table.
The purpose of watchdog is to monitor whether the system
operates normally. Within a certain period, watchdog register
must be cleared. If it is not cleared, CPU assumes the program
has been running in an abnormal condition and therefore, the
CPU will reset the system to the initial state and start running the
program all over again.
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GPCE063A
6.11. Soft Reset Protection
through differential MIC Inputs (MICN, MICP). Moreover, an
external resistor can be applied to adjust microphone gain and
time of AGC operating. The AD needs to select source of line-in
Writing $5555 into P_System_Reset will reset the whole system,
same as hardware reset (pull low RESETB pin), except a flag will
set on in P_System_LVD_Ctrl(R/W).
before conversion.
reference .
The ADC take pad(AVDD) as voltage
6.12. ADC (Analog to Digital Converter) / DAC
6.13. SPI
The GPCE063A has eight channels of 12-bit ADC (Analog to
Digital Converter). The function of an ADC is to convert analog
signal to digital signal, e.g. a voltage level into a digital word.
The eight channels of ADC can be seven channels of line-in from
IOB [7:0] or one channel microphone (MIC) input through
amplifier and AGC controller. The MIC amplifier circuit is
capable of reducing common mode noise by transmitting signals
A
Serial Peripheral Interface (SPI) controller is built-in
GPCE063A to facilitate communicating with other devices and
components. There are four control signals on SPI - SPICS
(IOA12), SPICK (IOA13), SDI (IOA14), and SDO (IOA15).
6.14. Audio Algorithm
The following speech types can be used in GPCE063A: PCM,
SACM_DVR1600, SACM_DVR3200, and SACM_DVR4800.
For melody synthesis, GPCE063A supports SACM_MS01 (FM)
and SACM_MS02 (wave-table) synthesizers.
SACM_S200,
SACM_S480,
SACM_S530,
SACM_S720,
SACM_A1600, SACM_A1601, SACM_A3600, SACM_DVR520,
© Generalplus Technology Inc.
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GPCE063A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
V+
Ratings
< 4.0V
< 7.0V
DC Supply Voltage
PortA/B Pad Supply Voltage
Input Voltage Range
Operating Temperature
Storage Temperature
VIO
VIN
-0.5V to V+ + 0.5V
0℃ to +60℃
TA
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions
see DC Electrical Characteristics.
7.2. DC Characteristics (VDD = 3.3V, VDDIO = 4.5V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.7
3.3
3.6
V
-
F
OSC = 49.152MHz,
-
-
25
-
-
mA
AD, DAC disable, no load
2.0
μA
μA
V
Disable 32KHz crystal
Standby Current
ISTB
6.0
Enable 32KHz,Disable PLL(FOSC)
Input High Level
Input Low Level
VIH
VIL
0.7VDDIO
-
-
-
-
-
-
0.3VDDIO
V
Output DAC Current
(AUD1, AUD2)
IAUD
IOH
IOL
-
-
-
-4
-10
13
-
-
-
mA
mA
mA
For one channel DAC
VOH = 0.9VDDIO
Output High Current
Output Low Current
(PA[3:0], PB[7:0])
Output Low Current
(PA[7:4])
VOL = 0.1VDDIO
IOL
RPL
RPL
RPH
-
-
-
-
30
-
-
-
-
mA
KΩ
KΩ
KΩ
-
Input Pull-Low Resister
(PA15:0, PB15:8)
Input Pull-Low Resister
(PB[7:0])
110
900
100
VIN = VDDIO
VIN = VDDIO
VIN = VSS
Input Pull-High Resister
(PA15:0, PB15:0)
7.3. DC Characteristics (VDD = 3.3V, VDDIO = 3.3V (PortA & B), TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.7
3.3
3.6
V
-
F
OSC = 49.152MHz,
-
-
25
-
-
mA
AD, DAC disable, no load
2.0
μA
μA
V
Disable 32KHz crystal
Standby Current
ISTB
6.0
Enable 32KHz,Disable PLL(FOSC)
Input High Level
Input Low Level
Output DAC Current
(AUD1, AUD2)
VIH
VIL
0.7VDDIO
-
-
-
-
-
-
0.3VDDIO
V
IAUD
-
-3.0
16
-
mA
For one channel DAC
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Oct. 04, 2013
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GPCE063A
Limit
Typ.
-5.0
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Output High Current
Output Low Current
(PA[3:0], PB[7:0])
Output Low Current
(PA[7:4])
IOH
IOL
-
-
mA
mA
VOH = 0.9VDDIO
-
-
-
-
-
7
-
-
-
-
-
VOL = 0.1VDDIO
-
IOL
RPL
RPL
RPH
17
mA
KΩ
KΩ
KΩ
Input Pull-Low Resister
(PA15:0, PB15:8)
Input Pull-Low Resister
(PB[7:0])
190
1400
160
VIN = VDDIO
VIN = VDDIO
VIN = VSS
Input Pull-High Resister
(PA15:0, PB15:0)
7.4. ADC Characteristics (AVDD = 3.3V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Min.
Typ.
Max.
ADC LINE_IN Input Voltage Range from IOB[7:0]
ADC Microphone Input Voltage Range
Resolution of ADC
VINL (Note 1)
VINM
VSS-0.3
-
-
AVDD+0.3
V
VSS-0.3
AVDD+0.3
V
RESO
-
-
12
bits
Signal-to-Noise Plus Distortion of ADC from Line in
Effective Number of Bit
SINAD (Note 4)
ENOB (Note 5)
INL
-
56
9.0
±3.0
±1
-
dB
8.0
-
bits
LSB (Note 3)
LSB
Integral Non-Linearity of ADC
-
-
-
-
-
Differential Non-Linearity of ADC
AD Conversion Rate
DNL (Note 6)
FCONV
-
-
-
FCPU/256
42
Hz
Microphone Amplifier Gain (Note 7)
A MIC
dB
Note1: Internal protection diodes clamp the analog input to AVDD and VSS. These diodes allow the analog input to swing from (VSS-0.3V) to (AVDD+0.3V)
without causing damage to the devices.
Note2: LSB means Least Significant Bit. With VINL = 2.6V, 1LSB = 2.6V/2^12 = 0.635mV.
Note3: The SINAD testing condition at VINLp-p = 0.8*AVDD, FCONV = Fcpu/512 = 49MHz/256 = 192KHz, Fin=1.0KHz Sine waves at AVDD = 3.0V from the
IOB [7:0] input.
Note4: ENOB = (SINAD-1.76)/6.02.
Note5: The ADC of GPCE063A can guarantee 12 bits no missing code.
Note6: The microphone amplifier maximum gain = 15 * (60K/(1.5K+REXT) V/V. The REXT is external resistor between OPI and MICOUT. The gain is
132V/V (=42dB) when REXT is 5.1K.
7.5. DAC Characteristics (AVDD = 3.3V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Min.
Typ.
-
Max.
Resolution of DAC
RESO
SNR
-
-
-
-
14
bit
dB
Hz
dB
Signal to Noise Ratio of DAC
Sample Rate
84
-
-
400K
-
FS
THD+N at FS
FOUT = 1K Hz
-60
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GPCE063A
7.6. Pull High Resister and VDDIO
7.9. I/O Output High Current IOH and VDDIO
Output High Current vs VDDIO
Pull High Resister vs VDDIO
0
-3
300
250
200
150
100
50
-6
-9
-12
-15
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
VDDIO (V)
7.10. I/O Output Low Current IOL and VDDIO(Normal
Pad)
7.7. Pull Low Resister and VDDIO(Normal PAD)
Pull Low Resister vs VDDIO ( Normal PAD )
Output Low Current vs VDDIO
350
300
250
200
150
100
50
24.00
20.00
16.00
12.00
8.00
4.00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
0.00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
7.8. Pull Low Resister and VDDIO(IOB[7:0] PAD with
input high)
7.11. I/O Output Low Current IOL and VDDIO(High
driving pad)
Pull Low Resister vs VDDIO ( High Resister PAD )
3000
Output Low Current vs VDDIO ( High Driving IOA[7:4] )
2500
2000
1500
1000
500
40.00
30.00
20.00
10.00
0.00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDDIO (V)
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GPCE063A
7.12. DAC Output Current IOL and AVDD
DAC Output Current vs. AVDD
6.000
5.000
4.000
3.000
2.000
1.000
0.000
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
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GPCE063A
8. APPLICATION CIRCUITS
8.1. Application Circuit (1)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
© Generalplus Technology Inc.
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Version: 1.8
GPCE063A
8.2. Application Circuit (2)
1K
VMIC
10uF
3K
RESET
0.22uF
MICP
MICN
0.1uF
RESET
VDDH(3.6v)
MIC
0.22uF
100uF 0.1uF
3K
Speaker
0.1uF
1K
2
1
5
4
DAC
0.22uF
GPY0030B
MICOUT
OPI
270
0.027uF
10K
5.1K
0.1uF
5000pF
AGC
GPCE063A
470K
4.7uF
0.1uF
IOA[15:0]
IOA[15:0]
IOB[15:0]
IOB[15:0]
VADREF
X32I
VDDIO
VDD
20pF*
VDD(3.6v)
AVDD
32768Hz
20pF*
0.1uF
10uF
AVSS
VSS
X32O
VSSIO
VCOIN
3.3K
3300pF
0.1uF
GPCE063A Application Circuit (MIC_IN and GPY0030A audio amplifier, for 2-battery use only)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
© Generalplus Technology Inc.
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Version: 1.8
GPCE063A
8.3. Application Circuit (3)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
© Generalplus Technology Inc.
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Version: 1.8
GPCE063A
8.4. Application Circuit (4)
1K
VMIC
10uF
3K
3K
0.22uF
0.22uF
RESET
MICP
MICN
RESET
VDDH(3.6v)
0.1uF
MIC
Speaker
4.7uF
1K
DAC
0.22uF
MICOUT
OPI
5000pF
2K
5.1K
5000pF
GPCE063A
AGC
470K
4.7uF
0.1uF
IOA[15:0]
IOA[15:0]
IOB[15:0]
IOB[15:0]
VADREF
X32I
VDDIO
VDD
20pF*
VDD(3.6v)
AVDD
32768Hz
20pF*
0.1uF
10uF
AVSS
VSS
X32O
VSSIO
VCOIN
3.3K
3300pF
0.1uF
GPCE063A Application Circuit (MIC_IN and with BJT amplifier, for 2-battery use only)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
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Version: 1.8
GPCE063A
8.5. Application Circuit (5)
VMIC
RESET
MICP
MICN
0.1uF
VDDH(5.0v)
Speaker
RESET
4.7uF
1K
DAC
MICOUT
OPI
5000pF
2K
AGC
GPCE063A
IOA[15:0]
IOB[15:8]
VDDH(5.0v)
IOA[15:0]
IOB[15:8]
IOB[7:0]
IOB[7:0]
( 8-Channel Line In )
VADREF
0.1uF
VDDIO
VSSIO
0.1uF
10uF
20pF*
X32I
32768Hz
20pF*
VDD
VDD(3.3v)
VDDH(5.0v)
X32O
GPY0029B
AVDD
0.1uF
10uF
AVSS
VSS
VCOIN
3.3K
3300pF
0.1uF
GPCE063A Application Circuit(LINE_IN and with BJT amplifier,for 3-battery use only)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
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Version: 1.8
GPCE063A
8.6. Application Circuit (6)
VMIC
RESET
0.1uF
MICP
MICN
VDDH(3.6v)
RESET
Speaker
4.7uF
1K
DAC
MICOUT
OPI
5000pF
2K
AGC
GPCE063A
IOA[15:0]
IOA[15:0]
IOB[15:0]
IOB[7:0]
IOB[7:0]
( 8-Channel Line In )
IOB[15:0]
VADREF
X32I
0.1uF
VDDIO
VDD
20pF*
VDD(3.6v)
32768Hz
20pF*
AVDD
0.1uF
10uF
AVSS
VSS
X32O
VCOIN
VSSIO
3.3K
3300pF
0.1uF
GPCE063A Application Circuit(LINE_IN and with BJT amplifier,for 2-battery use only)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
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GPCE063A
8.7. Application Circuit (7)
RESET
0.1uF
VDDH(3.6v)
Speaker
RESET
4.7uF
1K
DAC
VDD(3.6v)
GENERALPLUS
USB PROBE
5000pF
2K
1
ICE_EN
ICE_SCK
ICE_SDA
Connect
GPCE063A
IOA[15:0]
IOB[15:0]
IOA[15:0]
IOB[15:0]
VADREF
X32I
0.1uF
VDDIO
VDD
20pF*
VDD(3.6v)
AVDD
32768Hz
20pF*
0.1uF
10uF
AVSS
VSS
X32O
VCOIN
VSSIO
3.3K
3300pF
0.1uF
GPCE063A Application Circuit(Flash ROM Download Interface)
Note*: These capacitor values are for design guidance only. The recommended 32K XTAL features are ESR=11.2~35K and CL1=CL2 =20~30pF (including
PCB parasitic loading, for example, user should apply additional 14~24pF on X32I and X32O if PCB parasitic loading is 6pF)
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GPCE063A
9. PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
GPCE063A-NnnV-C
Package Type
Chip form
GPCE063A-NnnV-QL02x
Halogen Free Package
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 1 - 9, serial number).
9.2. Package Information
LQFP 64 Outline Dimensions
Dimension in mm
Symbol
Min.
Typ.
-
Max.
1.60
0.15
1.45
0.27
0.16
A
A1
A2
b
-
0.05
1.35
0.17
0.09
-
1.40
0.22
-
c1
D
12.00
10.00
12.00
10.00
0.50 BSC.
D1
E
E1
e
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GPCE063A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or
alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
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Version: 1.8
GPCE063A
11. REVISION HISTORY
Date
Revision #
Description
Page
Oct 04, 2013
1.8
1. Add COMAIR logo to the cover page
2. update X32K crystal's capacitance note in application circuit
Modify 8.7 Application Circuit (7).
Nov. 18, 2011
Jan. 07, 2011
Oct. 13, 2010
Dec. 11, 2009
1.7
1.6
1.5
1.4
26
11
4
Modify 6.5.2 Low Voltage Reset and remove the timing diagram
Modify 3.FEATURES.
1. Modify 5.3 GPCE063A PIN Map.
2. Modify 6.9.1 IO PWM.
8
14
15
6
3. Modify 6.12 ADC (Analog to Digital Converter) / DAC.
1. Modify 5.1. GPCE063A Pad Assignment.
2. Add 5.2. GPCE064A Pad Assignment.
3. Modify 5.3 GPCE063A Pin Map.
4. Add 5.4 GPCE064A Pin Map.
Oct. 02, 2009
1.3
7
8
9
Aug. 17, 2009
1.2
1. Modify 3.FEATURES.
4
2. Modify 8.APPLICATION CIRCUITS.
Modify the Package Information in section 9.2.
Release to 1.0
18-24
25
27
15
Dec. 16, 2008
Aug. 01, 2008
Apr. 08, 2008
1.1
1.0
0.1
Original
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