GPCH4512A [GENERALPLUS]
4-channel Sound Controller;
| 型号： | GPCH4512A |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 4-channel Sound Controller |
| 文件： | 总20页 (文件大小：585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPCH4512A
4-channel Sound Controller
DEC. 01, 2008
Version 1.2
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPCH4512A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. FEATURES.................................................................................................................................................................................................. 3
3. APPLICATION FIELD.................................................................................................................................................................................. 3
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
5. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
5.1. PAD ASSIGNMENT ................................................................................................................................................................................. 6
5.2. PIN MAP - LQFP 128 ............................................................................................................................................................................ 7
5.3. PIN MAP - LQFP 44 .............................................................................................................................................................................. 8
6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 9
6.1. SRAM .................................................................................................................................................................................................. 9
6.2. ROM .................................................................................................................................................................................................... 9
6.3. LOW VOLTAGE RESET ............................................................................................................................................................................ 9
6.4. INTERRUPT............................................................................................................................................................................................ 9
6.5. I/O........................................................................................................................................................................................................ 9
6.5.1. I/O configuration........................................................................................................................................................................ 9
6.6. TIMER/COUNTER (TIMER A/TIMER B/TIMER C)...................................................................................................................................... 10
6.7. SLEEP, WAKEUP AND WATCHDOG ......................................................................................................................................................... 10
6.7.1. Sleep and Wakeup.................................................................................................................................................................. 10
6.7.2. Watchdog................................................................................................................................................................................ 10
6.8. SPEECH AND DAC ............................................................................................................................................................................... 10
7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 11
7.1. ABSOLUTE MAXIMUM RATINGS ..............................................................................................................................................................11
7.2. DC CHARACTERISTICS (VDD5/VDD5_4 = 3.0V, TA = 25℃)...................................................................................................................11
7.3. DC CHARACTERISTICS (VDD5/VDD5_4 = 5.0V, TA = 25℃)...................................................................................................................11
7.4. DAC CHARACTERISTICS (VDD5 = 3.0V, TA = 25℃).............................................................................................................................. 12
7.5. REGULATOR CHARACTERISTICS ( TA = 25℃) ........................................................................................................................................ 12
7.6. THE RELATIONSHIPS BETWEEN THE ROSC AND THE FOSC......................................................................................................................... 12
7.7. THE RELATIONSHIPS BETWEEN THE FOSC AND THE IOP............................................................................................................................ 12
7.8. THE RELATIONSHIPS BETWEEN THE IOP AND THE VDD ............................................................................................................................. 13
7.8.1. FCPU = 7.159 MHz. VDD = VDD5_4 .......................................................................................................................................... 13
7.9. THE RELATIONSHIPS BETWEEN THE IOH AND THE VDD ............................................................................................................................. 13
7.9.1. VOH = 0.9VDD............................................................................................................................................................................ 13
7.10.THE RELATIONSHIPS BETWEEN THE IOL AND THE VDD ............................................................................................................................. 13
7.10.1. VOL = 0.1VDD........................................................................................................................................................................ 13
8. APPLICATION CIRCUITS......................................................................................................................................................................... 14
8.1. GPCH4512AAPPLICATION CIRCUIT WITH ROSC OPTION........................................................................................................................ 14
8.2. GPCH4512AAPPLICATION CIRCUIT WITH CRYSTAL OPTION.................................................................................................................. 15
8.3. CURRENT MODE DAC SPEAKER DRIVER .............................................................................................................................................. 16
9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 17
9.1. ORDERING INFORMATION ..................................................................................................................................................................... 17
9.2. PACKAGE INFORMATION ....................................................................................................................................................................... 17
9.2.1. LQFP 128-QL09...................................................................................................................................................................... 17
9.2.2. LQFP 44-QL01........................................................................................................................................................................ 18
10.DISCLAIMER............................................................................................................................................................................................. 19
11. REVISION HISTORY ................................................................................................................................................................................. 20
© Generalplus Technology Inc.
Proprietary & Confidential
2
Dec. 01, 2008
Version: 1.2
GPCH4512A
4-channel Sound Controller
1.GENERAL DESCRIPTION
The GPCH4512A embedded with an 8-bit processor, 512K bytes
ROM chip, 512 bytes working SRAM, 3 set of 12-bit timers, 24
general I/Os, and 1 set of 12-bit DAC. The microprocessor can
implement software based on audio processing, functional control
and others. For audio processing, melody and speech can be
mixed into one output. The GPCH4512A implement a high
performance SPU voice engine to achieve 4 channel voice with
ADPCM/PCM. It operates over a wide voltage range from 2.4V
through 5.5V, and it includes a Low Voltage Reset to assure
system operating appropriately under low voltage condition. In
addition, GPCH4512A provide sleep mode for power savings. It
can be awaken from sleep mode by interrupt source or by IOA’s
state change.
10 IRQ & 6 NMI Interrupts
Watchdog function
Low Voltage Reset: 2.2V
24 general I/Os, including 8 general/special I/Os (All bit
programmable)
8-bit I/O with high sink current(20mA) for LED application
IOA with 1M pull low function to prevent current leakage from
error key touch
One 12-bit DAC outputs (D/A output: 4mA/channel)
SPU(Sound Processing Unit) engine can output audio data of
15-bit resolution with 12-bit DAC to perform high quality sound
IR PWM Output
4-channel SPU engine with ADPCM/PCM wave table
Tone color (Speech) with ADPCM algorithm to save memory
usage
2.FEATURES
Working Voltage: 2.4V - 5.5V
3.APPLICATION FIELD
CPU speed: 7.159MHz.
FOSC = 14.318MHz (2 x CPU clock)
ROM size: 512k bytes
Talking Instrument Controller
General Music Synthesizer
Industrial Controller
RAM size: 512 bytes. (Programmable RAM 384 bytes)
Three 12-bit timers/counters, TMA/TMB/TMC
(Programmable and Auto Reload)
Sleep mode to reduce power
High End Toy Controller
Intelligent Education Toys
and more
Key change wake up function
© Generalplus Technology Inc.
Proprietary & Confidential
3
Dec. 01, 2008
Version: 1.2
GPCH4512A
4.BLOCK DIAGRAM
12-bit Timer/Counter A
12-bit Timer/Counter B
12-bit Timer/Counter C
XI
512-
bytes
SRAM
8-BIT
CONTROLLER
XO
4 Channel SPU
DIGITAL MIXER
512K bytes ROM
LVR / RESET
RESET
DACOL
12-bit DAC X 1 OUTPUT
24 PIN GENERAL I/O PORT A,B,C
(IOB with SPECIAL FUNCTION)
IOA
0~7
IOC
0~7
IOB
0~7
© Generalplus Technology Inc.
Proprietary & Confidential
4
Dec. 01, 2008
Version: 1.2
GPCH4512A
5.SIGNAL DESCRIPTIONS
Name
PIN No.
LQFP 128
PIN No.
LQFP 44
PIN No.
Type
Description
Pull hi/low/float
IO PORT
IOA0~IOA7
IOB0~IOB7
IOC0~IOC7
Clock Related
XO
40~33
90~83
34~31, -
30~29, -
6~9, -
I/O
I/O
I/O
Bi-directional IO ports, can be wakeup pins
Bi-directional IO ports
-
-
-
32~29, 25~22 82~79, 75~72
2~5, 7~10
41~44, 23~26
Bi-directional IO ports
19
18
58
57
22
21
O
I
Oscillator Crystal output
-
XI
Oscillator crystal input/ROSC input
Pull-low
Power Pad
VDD
26
6, 28
11, 27
12
76
37, 78
47, 77
48
26
28
I
I
Positive supply for logic (from VDD3O)
Ground reference for logic and I/O pins
Positive supply for I/O pins(2.4~5.5 V)
Positive supply for DAC(from VDD3O)
Ground reference for DAC
-
-
-
-
-
-
-
-
VSS
VDD5_4, VDD5
VDDDAC3
VSSDAC
VDDREG
VSSREG
VDD3O
12, 27
13
I
I
14
51
15
I
16
53
17
I
Positive supply for REGULATOR(2.4~5.5 V)
Ground reference for regulator
17
54
18
I
15
52
16
O
3V power output from regulator
Others
RESETB
TEST
20
21
13
1
65
66
50
20
23
24
14
5
I
External reset pin(active low)
Test mode
Pull-hi
Pull-low
I
DACOL
O
O
Left DAC output
Sleep indicator
-
SLEEP
-
© Generalplus Technology Inc.
Proprietary & Confidential
5
Dec. 01, 2008
Version: 1.2
GPCH4512A
5.1. PAD Assignment
© Generalplus Technology Inc.
Proprietary & Confidential
6
Dec. 01, 2008
Version: 1.2
GPCH4512A
5.2. PIN Map - LQFP 128
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
IOB0
IOB1
IOB2
IOB3
VSS
VDD5
VDD
IOB4
IOB5
IOB6
IOB7
NC
LQFP 128
NC
NC
NC
SLEEP
NC
NC
IOC4
IOC5
IOC6
IOC7
NC
NC
NC
NC
NC
NC
NC
NC
TEST
RESETB
NC
NC
© Generalplus Technology Inc.
Proprietary & Confidential
7
Dec. 01, 2008
Version: 1.2
GPCH4512A
5.3. PIN Map - LQFP 44
NC
NC
NC
IOA1
IOA2
IOA3
IOB0
IOB1
VSS
NC
SLEEP
IOC4
LQFP 44
IOC5
VDD5
VDD
IOC6
IOC7
NC
NC
TEST
RESETB
NC
© Generalplus Technology Inc.
Proprietary & Confidential
8
Dec. 01, 2008
Version: 1.2
GPCH4512A
6. FUNCTIONAL DESCRIPTIONS
6.1. SRAM
Interrupt Source
KEY
Interrupt Name
Priority
IRQ8
The 512-byte SRAM (including Stack) area is located in
$000000~$0002FF.
IRQ_KEY
IRQ_EXT
IRQ_SPU
EXT
SPU
IRQ9
IRQ10
6.2. ROM
6.5. I/O
GPCH4512A can be selected to use internal ROM with 512k
bytes.
The purpose of input and output ports is to communicate with
other devices. Four programmable I/O ports are built-in,
6.3. Low Voltage Reset
including Port A, B, and C. The PortA is a general I/O with
programmable wake-up capability. In addition to general I/O
function, PortB also offers some special functions in certain pins.
Refer to Special Function in PortB. PortC0~7 provides large
sink current (20mA) for LED application.
The GPCH4512A provides another important feature, Low Voltage
Reset (LVR). Without LVR, the CPU may become unstable and
malfunctioning when operating voltage drops below 2.2V. It will
reset all functions to the initial operational (stable) states when the
voltage drops below 2.2V by LVR.
6.5.1. I/O configuration
6.4. Interrupt
The following diagram represents the I/O schematic.
The GPCH4512A has two interrupt (INT) modes: IRQ (interrupt
Request) and NMI (Non-Mask Interrupt Request). The interrupt
controller controls 10 IRQs and 6 NMIs. A NMI cannot be
interrupted by any other IRQs. An IRQ can be interrupted by a
NMI and by a high priority IRQ.
I/O A, B, C Schematic:
Buffer(R)
Port_Data(W)
Register
pull high
pull low
Port_Buffer(W)
Port_DIR(R/W)
Port_ATTR(R/W)
Pin pad
Interrupt Source
Timer A
Interrupt Name
NMI_TIMER_A
NMI_TIMER_B
NMI_TIMER_C
NMI_D1024
Priority
NMI
Control
logic
Timer B
NMI
Timer C
NMI
Data(R)
CPU_CLOCK/1024
KEY
NMI
NMI_KEY
NMI
EXT
NMI_EXT
NMI
Port_Data and Port_Buffer are written into the same register but
read from different nodes. The IOA [7:0] is the key wakeup port.
To activate key wakeup function, first latch data on IOA_Data and
enable the key wakeup function. Wakeup is triggered when the
PortA state is different from first latched data. In addition to a
general I/O port, PortB can be assigned to some special functions.
A summary of PortB special functions is listed as follows.
TIMER A
IRQ_TIMER_A
IRQ_TIMER_B
IRQ_TIMER_C
IRQ_D1024
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
TIMER B
TIMER C
CPU_CLOCK/1024
CPU_CLOCK/4096
CPU_CLOCK/262144
IRQ_D4096
IRQ_D262144
CPU_CLOCK/2097152 IRQ_D2097152
Special function in PortB
PortB
IOB5
IOB6
Special Function
PWMO IR
Function Description
Note
IR carrier frequency output
External interrupt source
Refer to Timer/Counter section
Negative edge trigger INT(default)
EXT
Feedback Output
Works with IOB7 by adding a RC circuit between
them to get an OSC to EXT interrupt
Schmitt Inverter Input
-
IOB7
Feedback Input
-
© Generalplus Technology Inc.
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9
Dec. 01, 2008
Version: 1.2
GPCH4512A
6.6. Timer/Counter (Timer A/Timer B/Timer C)
Three timers are embedded in GPCH4512A, TimerA, B and C.
All three timers have the same behavior which includes 12-bit up
counter and a preload register and programmable clock source.
Timer A can also be the clock source of the software channel.
The clock source of each timer can be set individually. Two clock
sources including CPU clock and external clock can be selected
individually or combined together for timer’s clock source.
Select
000
001
010
011
Input 1
‘1’
Input 2
‘0’
Function
Comment
Disable
Disable
Disable
Disable
‘1’
‘0’
FCPU
FCPU
‘1’
IOB6
‘1’
Duration count by FCPU
Timer by FCPU
Disable
Duration count by FCPU
Timer by FCPU
Disable
100
101
110
‘0’
‘1’
‘0’
Disable
Disable
‘1’
‘0’
Disable
Disable
111
‘1’
‘0’
Disable
Disable
6.7. Sleep, Wakeup and Watchdog
6.7.1. Sleep and Wakeup
otherwise, CPU assumes the program has been running in an
abnormal condition and therefore, CPU will reset the system to the
initial state and start running the program from program’s
beginning. It protects the system from incorrect code execution
by generating a system reset when the watchdog timer overflows
as a result of failure of software to clear the timer within 0.75s
second. Watchdog function can be removed by option.
Sleep mode is to save power by stopping clock running while
device is not in use. When sleep acts, the device runs from
operating mode to standby mode. Wake-up from sleep mode
means turning back to operating mode.
1). Sleep: After power on reset, IC starts working until a sleep
command is given. When a sleep signal is accepted, IC will
turn off system clock and enter sleep mode.
6.8. Speech and DAC
2). Wake-up: While an IRQ/NMI interrupt signal is generated,
GPCH4512A is waking up from sleep mode. While wake-up
completed, program counter will continue to execute the next
command.
The GPCH4512A uses a high performance SPU voice engine to
archive 8-channel voice with ADPCM/PCM. The SPU also
supports automatic zero-crossing concatenating function.
A
hardware multiplier is also embedded in this SPU for software
usage. The fixed address of RAM area $0000 - $003F is
designed as address pointers and a data buffer for the 4 channel
speech/melody generation. There is one 12-bit D/A with 4mA
driving current for audio output.
6.7.2. Watchdog
The purpose of watchdog is to monitor system’s operation
normally. Within a certain period, watchdog must be cleared;
© Generalplus Technology Inc.
Proprietary & Confidential
10
Dec. 01, 2008
Version: 1.2
GPCH4512A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Characteristics
Symbol
Ratings
DC Supply Voltage
V+
VIN
TA
< 7.0V
Input Voltage Range
Operating Temperature
Storage Temperature
-0.5V to V+ + 0.5V
0℃ to +60℃
-50℃ to +150℃
TSTO
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational
conditions see DC Electrical Characteristics.
7.2. DC Characteristics (VDD5/VDD5_4 = 3.0V, TA = 25℃)
Limit
Characteristics
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Operating Voltage
Operating Current
VDD
IOP
2.4
-
3.6
V
For 2-battery
CPU = 7.0MHz , no load, midi playing
F
-
9
-
mA
with inner ROM
Standby Current
OSC Frequency
Input High Level
Input Low Level
ISTB
FOSC
VIH
-
-
4.0
μA
MHZ
V
VDD5/VDD5_4 = 3.0V
-
0.7 VDD
VSS
-
-
15
VDD5/VDD5_4 = 3.0V
-
VDD
-
VIL
-
-2.0
-
0.3VDD
V
-
Audio Output Current
Output High Current
Output Low Current
(IOA7:0, IOB7:0)
Output Low Current
(IOC7:0)
IAUD
IOH
-
-
mA
mA
-
-4.3
VDD5/VDD5_4 = 3.0V, VOH = 2.7V
IOL1
IOL2
RPL
RPH
4.8
11
-
-
-
-
-
-
-
mA
mA
KΩ
KΩ
VDD5/VDD5_4 = 3.0V, VOL = 0.3V
VDD5/VDD5_4 = 3.0V, VOL = 0.3V
VIN = VDD5/VDD5_4
Input Pull-Low Resister
(PA7:0)
1500
180
Input Pull-High Resister
(PA7:0, PB7:0, PC7:0)
-
VIN = VSS
7.3. DC Characteristics (VDD5/VDD5_4 = 5.0V, TA = 25℃)
Limit
Typ.
-
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Operating Voltage
Operating Current
VDD
IOP
3.6
5.5
V
For 3-battery
F
CPU = 7.0MHz, no load, midi playing
-
10
-
mA
with inner ROM
Standby Current
OSC Frequency
ISTB
FOSC
VIH
-
-
-
5.0
μA
MHz
V
VDD5/VDD5_4 = 5.0V
-
0.7 VDD
VSS
-
15
VDD5/VDD5_4 = 5.0V
Input High Level
Input Low Level
-
VDD
-
VIL
-
0.3VDD
V
-
Audio Output Current
Output High Current
Output Low Current
(IOA7:0, IOB7:0)
IAUD
IOH
-4
-
-
-
mA
mA
-
-11.0
VDD5/VDD5_4 = 5.0V, VOH = 4.5V
IOL1
11
-
-
mA
VDD5/VDD5_4 = 5.0V, VOL = 0.5V
© Generalplus Technology Inc.
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Dec. 01, 2008
Version: 1.2
GPCH4512A
Limit
Typ.
Characteristics
Symbol
Unit
Test Condition
Min.
Max.
Output Low Current
(IOC7:0)
IOL2
RPL
RPH
24
-
-
mA
KΩ
KΩ
VDD5/VDD5_4 = 5.0V, VOL = 0.5V
VIN = VDD5/VDD5_4
VIN = VSS
Input Pull-Low Resister
(PA7:0)
-
-
810
105
-
-
Input Pull-High Resister
(PA7:0, PB7:0, PC7:0)
7.4. DAC Characteristics (VDD5 = 3.0V, TA = 25℃)
Limit
Characteristics
Resolution of DAC
Symbol
Unit
Min.
Typ.
-
Max.
RESO
-
-
-
-
-
12
bit
%
THD+N (f=1kHz)
Noise at no signal
Dynamic Range(-60dB)
Sample Rate
SNR
0.1
-84
-77
-
-
-
-
-
-
dBr A
dBr A
Hz
FS
400K
7.5. Regulator Characteristics ( TA = 25℃)
Limit
Typ.
4.5
-
Characteristics
Input Voltage
Symbol
Unit
Min.
2.4
-
Max.
5.5
30
VREGI
IREGO
VREGO
IRGES
V
mA
V
Maximum Current Output
Output Voltage
2.4
-
3
3.3
-
Standby Current
2.5
uA
7.6. The Relationships between the ROSC and the FOSC
7.7.The Relationships between the FOSC and the IOP
18
10
16
36, 15.637
9
8
7
6
5
39, 14.419
14
43, 13.354
47, 12.385
12
51, 11.097
56, 10.227
10
68, 8.451
8
75, 7.641
82, 6.966
91, 6.33
6
130, 4.477
130
4
30
50
70
90
110
3
5
7
9
11
13
15
(ROSC KΩ)
(FOSC MHz)
© Generalplus Technology Inc.
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Dec. 01, 2008
Version: 1.2
GPCH4512A
7.8. The Relationships between the IOP and the VDD
7.8.1. FCPU = 7.159 MHz. VDD = VDD5_4
7.10. The Relationships between the IOL and the VDD
7.10.1. VOL = 0.1VDD
12
10
8
30
25
20
15
10
5
IOA0~7
IOC0~7
6
4
2
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VDD(V)
VDD(V)
7.9. The Relationships between the IOH and the VDD
7.9.1. VOH = 0.9VDD
14
12
10
8
IOA0~7
6
4
2
0
0
1
2
3
4
5
6
VDD(V)
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Version: 1.2
GPCH4512A
8. APPLICATION CIRCUITS
8.1. GPCH4512A Application Circuit with ROSC Option
VDDB
VDD5
IOA0~7
IOA0~7
IOB0~7
IOC0~7
VDD5_4
C1
47u
VDDREG
IOB0~7
IOC0~7
VSS
VSSB
VSS
VSSREG
VSSDAC
RESETB
C3
Reset
0.1u
VDDB
C2
10u
C8 *
0.1u
VSSB
Speaker
SPN
VDD
CE
VDD3O
VDD
C7
47u
IOx
SPP
VSS
INN
GPY0030B
DACOL
VDDDAC3
VREF
0.22u
C5
R3
47K
C4
0.01u
R1
R2
1K
ACIN
470
XI
C6
0.1u
VSSB
XO
VSSB
GPCH4512A application circuit with Rosc option
Note*: This capacitor can be removed if there is good power line layout on PCB that no harm to sound quality.
Note: Important note to power connection:
(a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 and VDD5_4, 2.4V ~ 5.5V)
(b) VDD3O is internal regulator output that supplies power to VDD, VDDDAC3, etc. Connect VDD3O, VDD and VDDDAC3 all together.
(c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, etc.
(d) The built-in regulator can NOT be disabled, so user should NOT bypass this regulator.
(e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C8 close to VDDDAC3 pad.
© Generalplus Technology Inc.
Proprietary & Confidential
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Dec. 01, 2008
Version: 1.2
GPCH4512A
8.2. GPCH4512A Application Circuit with Crystal Option
VDDB
VDD5
IOA0~7
IOA0~7
IOB0~7
IOC0~7
VDD5_4
C1
47u
VDDREG
IOB0~7
IOC0~7
VSS
VSSB
VSS
VSSREG
VSSDAC
RESETB
C3
Reset
0.1u
VDDB
C2
10u
C10 **
0.1u
VSSB
Speaker
SPN
VDD
CE
VDD3O
VDD
C7
47u
IOx
SPP
VSS
INN
GPY0030B
DACOL
VDDDAC3
VREF
0.22u
C5
20p C8*
14.318MHz
20p C9*
C4
0.01u
R1
470
R2
1K
ACIN
XI
VSSB
C6
0.1u
VSSB
XO
VSSB
GPCH4512A application circuit with XTAL option
Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used.
Note**: This capacitor can be removed if there is good power line layout on PCB that no harm to sound quality.
Note: Important note to power connection:
(a) Battery or Power supply connects to VDDB (including VDDREG, VDD5 and VDD5_4, 2.4V ~ 5.5V)
(b) VDD3O is internal regulator output that supplies power to VDD, VDDDAC3, etc. Connect VDD3O, VDD and VDDDAC3 all together.
(c) VDDB should NOT be connected to VDD3O, VDD, VDDDAC3, etc.
(d) The built-in regulator can NOT be disabled, so user should NOT bypass this regulator.
(e) Recommended capacitor placement for power distribution on PCB: C1 close to battery, C2 close to VDD3O pad and C10 close to VDDDAC3 pad.
© Generalplus Technology Inc.
Proprietary & Confidential
15
Dec. 01, 2008
Version: 1.2
GPCH4512A
8.3. Current Mode DAC Speaker Driver
VDD
VDD
RB1: 10K ~ 50K
RB2: 820 ~ 1.5K
C1: 0.1 μ F ~ 1μ F
RB1: 680 ~ 1.5K
C1: 0.1μ F ~ 1μ
F
4 Ω ~ 8 Ω
32 Ω ~ 64 Ω
RB1
C1
DACOL
RB2
DACOL
8050
8050
C1
RB1
Figure 1
Figure 2
VDD
VDD
RB1: 2K~10K C1: 1μ F~10 μ F
RB2: ~ 1K C2: ~ 0.1μ F
RB1: 2K~10K C1: 1μ F~10μF
RB2: ~ 1K
C2: ~ 0.1μ F
4 Ω ~8 Ω
4 Ω ~64 Ω
RB1
C2
Enable
C2
RB1
DACOL
RB2
DACOL
RB2
8050
8050
C1
C1
Figure 3
Figure 4
VDD
RB1: ~ 360 Ω (Vol)
RE1: ~ 4.7 Ω
4 Ω ~64 Ω
DACOL
1N4148
8050
RE1
RB1
Figure 5
Figure 1: The simplest CKT uses with low impedance speaker. It has high operation current, but the cost is the cheapest.
Figure 2: It is the same as Figure 1 but a high impedance speaker is used.
Figure 3: The CKT has low pass filter. It can provide higher speech quality, but it always takes high operation current.
Figure 4: Improved version of Figure 3. The standby current can be controlled by enable pin.
Figure 5: The current mirror mode. It is able to control the volume. In addition, it has more stable and lower operation current than Figure 1-3.
© Generalplus Technology Inc.
Proprietary & Confidential
16
Dec. 01, 2008
Version: 1.2
GPCH4512A
9.PACKAGE/PAD LOCATIONS
9.1. Ordering Information
Product Number
Package Type
GPCH4512A-NnnV-C
Chip form
GPCH4512A-NnnV-QL09x
GPCH4512A-NnnV-QL01x
Halogen Free Package
Halogen Free Package
Note1: Code number is assigned for customer.
Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).
Note3: Package form number (x = 1 - 9, serial number).
Note4: LQFP44 only bonds 10 IO pads, so IR carrier/External interrupt/RC Feedback function is not supported
9.2. Package Information
9.2.1. LQFP 128-QL09
Dimension in Millimeter
Symbol
Min.
-
Typ.
Max.
1.60
0.15
1.45
0.23
0.20
A
A1
A2
b
-
0.05
1.35
0.13
0.09
-
1.40
0.16
c
-
D
16.00 BSC.
© Generalplus Technology Inc.
Proprietary & Confidential
17
Dec. 01, 2008
Version: 1.2
GPCH4512A
Dimension in Millimeter
Typ.
Symbol
Min.
Max.
D1
E
14.00 BSC.
16.00 BSC.
14.00 BSC.
0.40 BSC.
0.60
E1
e
L
0.45
0.75
L1
θ
1.00 REF
3.5∘
0∘
7∘
9.2.2. LQFP 44-QL01
Dimension in Millimeter
Symbol
Min.
-
Nom.
Max.
1.60
0.15
1.45
0.16
A
A1
A2
c1
D
-
0.05
1.35
0.09
-
1.40
-
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.80 BSC
0.37
D1
E
E1
e
b
0.30
0.45
0.45
0.75
L
0.60
L1
θ°
1.00 REF
3.5°
0°
7°
© Generalplus Technology Inc.
Proprietary & Confidential
18
Dec. 01, 2008
Version: 1.2
GPCH4512A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
19
Dec. 01, 2008
Version: 1.2
GPCH4512A
11. REVISION HISTORY
Date
Revision #
Description
Page
Dec. 01, 2008
1.2
1. Modify section 4. BLOCK DIAGRAM.
2. Modify 6.3 Low voltage reset.
4
9
3. Modify 7.4 DAC Characteristics.
4. Add 7.5 Regulator Characteristics.
12
12
14
15
16
5
5. Add note in section 8.1 Application circuits.
6. Add note in section 8.2 Application circuits.
7. Modify section 8.3 Current Mode DAC Speaker Driver.
Oct. 20, 2008
Apr. 11, 2008
1.1
1.0
1. Modify section 5. SIGNAL DESCRIPTIONS.
2. Modify section 7.2 DC Characteristics (VDD5/VDD5_4 = 3.0V, TA = 25℃).
3. Modify section 7.3 DC Characteristics (VDD5/VDD5_4 = 5.0V, TA = 25℃).
12
12
15, 16
17
22
4. Modify section 8.1 and 8.2 Application circuits.
5. Delete section 8.3 Generalplus Audio Driver GPY0030A.
Original
© Generalplus Technology Inc.
Proprietary & Confidential
20
Dec. 01, 2008
Version: 1.2
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