GPL87108A-NnnV-C [GENERALPLUS]
Low Power 660 Dots LCD Controller with 64KB ROM;
| 型号： | GPL87108A-NnnV-C |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | Low Power 660 Dots LCD Controller with 64KB ROM CD |
| 文件： | 总15页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GPL87108A
Low Power 660 Dots LCD Controller
with 64KB ROM
Mar. 15, 2016
Version 1.1
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPL87108A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3
2. FEATURES.................................................................................................................................................................................................. 3
3. BLOCK DIAGRAM ...................................................................................................................................................................................... 4
4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 5
4.1. PAD ASSIGNMENT ................................................................................................................................................................................. 6
5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 7
5.1. CPU ..................................................................................................................................................................................................... 7
5.2. CLOCK SOURCE..................................................................................................................................................................................... 7
5.3. ROM/RAM AREA .................................................................................................................................................................................. 7
5.4. STOP CLOCK MODE ............................................................................................................................................................................... 7
5.5. I/O PORTS............................................................................................................................................................................................. 7
5.6. RFC FUNCTION ..................................................................................................................................................................................... 7
5.7. LCD CONTROLLER ................................................................................................................................................................................ 8
5.8. LCD VOLTAGE GENERATION................................................................................................................................................................... 8
5.9. BUZZER DRIVER .................................................................................................................................................................................... 8
5.10.AUXILIARY CALCULATION HARDWARE ..................................................................................................................................................... 8
5.11.ANALOG BLOCK ..................................................................................................................................................................................... 8
5.12.MASK OPTIONS...................................................................................................................................................................................... 8
5.12.1. Low speed clock source selection........................................................................................................................................ 8
5.12.2. Watchdog timer .................................................................................................................................................................... 8
5.12.3. Operation voltage selection.................................................................................................................................................. 8
5.12.4. SEG53/PC3 pin share selection........................................................................................................................................... 9
5.12.5. SEG54/PC2 pin share selection........................................................................................................................................... 9
5.12.6. SEG55/PC1 pin share selection........................................................................................................................................... 9
5.12.7. SEG56/PC0 pin share selection........................................................................................................................................... 9
5.12.8. SEG57/PD5 pin share selection........................................................................................................................................... 9
5.12.9. SEG58/PD4 pin share selection........................................................................................................................................... 9
5.12.10. SEG59/PD3 pin share selection........................................................................................................................................... 9
5.13.MAP OF MEMORY................................................................................................................................................................................... 9
6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 10
6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 10
6.2. DC CHARACTERISTICS(TA = 25℃)....................................................................................................................................................... 10
7. APPLICATION CIRCUITS......................................................................................................................................................................... 12
8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 13
8.1. ORDERING INFORMATION ..................................................................................................................................................................... 13
9. DISCLAIMER............................................................................................................................................................................................. 14
10.REVISION HISTORY ................................................................................................................................................................................. 15
© Generalplus Technology Inc.
Proprietary & Confidential
2
Mar. 15, 2016
Version: 1.0
GPL87108A
LOW POWER 660 DOTS LCD CONTROLLER WITH 64KB ROM
1. GENERAL DESCRIPTION
Low standby current, ISTBY < 1uA @3.6V, 25℃
18 general I/O pins.
GPL87108A, a CMOS 8-bit microprocessor by Generalplus, offers
one of the highest cost/performance ratio LCD integrated circuits
in the industry, equipping RAM, ROM, I/Os, an interrupt controller,
and an automatic display controller/driver in a small device. Its
extraordinary features include capability of operating in low
voltage range from 1.2V ~ 3.6V as well as under a low power
condition that is suitable for solar cell environment. It also builds
-
PD[5:0](PD[5:3] share with SEG[57:59]; PD[1:0] share with
2 buzzers)
-
-
-
PC[3:0](shared with SEG[53:56])
PE[7:0]
Built-in 2 x RFC function (PD2 used as input, PD[5:3]
used as output)
LCD configurations: 11 coms x 60 segs (MAX) , 3x60, 4x60,
5x60, 6x60, 8x60, 9x60, 10x60, 4x64
in an internal power switch for
automatically and facilitates using solar cell and battery
co-operation in applications. This device is applicable for
a two-way power source
LCD 1/3 ,1/4 bias; 1/3, 1/4, 1/5, 1/6, 1/8, 1/9, 1/10, 1/11 duty
One 16-bit reloadable timer/counter
products such as low power calculator and products requiring
either only one solar cell or one battery application, or even
two-way power source.
Watchdog mode (~2 seconds)
Six interrupt sources:
TMBB, TMBA, 128Hz, 2KHz, Timer, EXT(PD2)
Power down mode
Wake-up sources: key input, TMBB, TMBA,128Hz, Timer
Built_in power switch for two way power source
2. FEATURES
Built-in 8-bit processor
-
-
-
15uA @ 3.6V, FCPU = 225KHz for operating mode
3 uA @ 3.6V, FCPU = 225KHz for halt mode
I stby < 1uA @ 1.5V
2432-byte SRAM
64K-byte ROM(include 2KB test code ROM size)
88-byte DPRAM
Built_in internal regulator for LCD operation, 5-level contrast
control
Built-in 225K/500K/1000K/1800KHz RC oscillator for system
operation
Built_in internal regulator for system operation
Built_in Low voltage reset to prevent unusual system operation
low voltage
-
-
Adjustable CPU clock speed: 1, 1/2, 1/4, 1/8, 1/16 for ROSC
1000K/1800KHz CPU clock speed can only be used at
operating voltage 1.8V ~ 3.6V
Note1: TMBB: 4KHz, 1KHz, 128Hz, 64Hz, 32Hz, 16Hz, 8Hz or 4Hz
Note2: TMBA: 2Hz or 1Hz
Built-in 30.72kHz RC oscillator & 32768Hz Crystal oscillator
circuit for timebase
Low operating voltage: 1.2 V – 1.8 V@0～70℃
1.8 V – 3.6 V@-20～70℃
© Generalplus Technology Inc.
Proprietary & Confidential
3
Mar. 15, 2016
Version: 1.0
GPL87108A
3. BLOCK DIAGRAM
VB
Power Saving Control
2432 B
RAM
Power Switch
VS
VDDSW
LVR
PC[3:0]
PD[5:0]
PE[7:0]
8-bit CPU
Internal Regulator
VREG
64 kB
ROM
ACON
PTEST
CUP[1:0]
VLCD
Generator
Interrupt
control
VLCD,V3X,
V2X,V1X
RC OSC
(HF/LF)
16 -bit
Timer/Counter
Watchdog Timer
X32I
XTAL32K
X32O
COM[10:0]
SEG[52:0]
11 Com * 60 Seg
LCD Drivers
© Generalplus Technology Inc.
Proprietary & Confidential
4
Aug. 01, 2011
Version: 1.0
GPL87108A
4. SIGNAL DESCRIPTIONS
Mnemonic
Type
Description
VS
I
I
Solar cell power input
Battery power input
Power switch output
Internal regulator output
Ground input
VB
VDDSW
VREG
O
O
I
VSS
COM[2:0]
COM[10:3]
SEG[52:0]
PD[5:0]
O
O
O
I/O
LCD driver common output
LCD driver common output. (COM[10:4] can be opted to SEG[57:63];COM3 can be opted to SEG56)
LCD driver segment output
GPIO I/O port. (PD[5:3] are shared with SEG[57:59]; PD[1:0] are shared with 2 buzzers)
In RFC application, PD[5:3] are used as pass-through (output) pin and connected to sensor.
PD2 is used as input-floating pin and connected to sensor & capacitor.
GPIO I/O port (shared with SEG[53:56])
PC[3:0]
PE[7:0]
ACON
PTEST
X32I
I/O
I/O
I
GPIO I/O port
Clear or system power on pin (active low) and 4ms de-bounce circuit inside
Test mode input pin (active high)
I
I
32768Hz crystal input
X32O
V1X
O
O
32768Hz crystal output
VLCD generator output
V2X
V3X
VLCD
CUP1
CUP2
I
Inputs for LCD bias settings
© Generalplus Technology Inc.
Proprietary & Confidential
5
Mar. 15, 2016
Version: 1.0
GPL87108A
4.1. PAD Assignment
Note1: This IC substrate should be connected to VSS or floated.
Note2: To ensure IC functions properly, please bond all of VDD and VSS pins.
Note3: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc.
Proprietary & Confidential
6
Mar. 15, 2016
Version: 1.0
GPL87108A
5. FUNCTIONAL DESCRIPTIONS
5.1. CPU
$60 through $9DF.
5.4. Stop Clock Mode
The 8-bit microprocessor in GPL87108A is a high performance
The GPL87108A provides
a
power saving mode for those
processor equipped with Accumulator, Program Counter,
X
applications required very low stand-by current. Users can
simply enable the wake-up sources to stop the CPU clock by
writing the STOP CLOCK Register ($09). By doing that, CPU will
enter standby mode, and RAM and I/Os remain at their previous
states until wakeup. There are five wake-up sources in the
GPL87108A: Port PortE wake-up, TMBA, TMBB, T128Hz, and
Timer wake-up. After GPL87108A wakes up, CPU will proceed to
the next state of sleep. Wake-up action will not affect RAM and
Register, Y Register, Stack pointer and Processor Status Register
(this is the same as the CPU6502 instruction structure).
5.2. Clock Source
The GPL87108A equips two groups of clock sources:
(1) A high speed frequency (RCHF) to support the entire system
operation. It provides four frequency options, 225KHz/
500KHz/ 1000KHz/ 1800KHz and can be selected by
Register $18H to fulfill the requirements for various
I/Os.
Note1: TMBB: 4KHz, 1KHz, 128Hz, 64Hz, 32Hz, 16Hz, 8Hz or 4Hz
Note2: TMBA: 2Hz or 1Hz
applications.
GPL87108A provides programmable CPU
clock speeds, 1, 1/2, 1/4, 1/8, or 1/16 of RCHF for power
saving.
5.5. I/O Ports
(2) A low speed frequency to control LCD frame rate and time
base timer. It comes from XTAL32K or IOSC30K selected
by mask option.
GPL87108A has three input/output ports: PortC, PortD, and PortE.
These port pins all equip some special features for key board scan.
In general, when an initial reset starts, all ports are used as a
general purpose input port. PortC, PortD, and PortE contain
three parts: data, direction and attribution registers. Please
follow the following table to set each I/O function with
corresponding bit in each port.
5.3. ROM/RAM Area
The GPL87108A provides 64K-byte ROM that can be defined as
the program area and its address locates from $4000 to $FFFF.
Its RAM consists of 2432 bytes (including Stack) at location from
PortC[3:0], PortD[5:0] , PortE[7:0]
Attribution
Direction
Data
Function
Input with pull-low
Pure Input
Description
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
General Purpose
I/O function
Output Low
Output High
Pad Floating
Special function
5.6. RFC Function
The RFC (Resistor to Frequency Converter) circuit contains a RC oscillation circuit and a 16-bit timer/counter to calculate the resistance of
temperature or humidity sensor relative to reference resistor. The circuit is shown below.
© Generalplus Technology Inc.
Proprietary & Confidential
7
Mar. 15, 2016
Version: 1.0
GPL87108A
PD5 floating control
RREF
RFCEN
PD5
PAD
PD4 floating control
RTH
PD4
PAD
16 bit Timer/Counter
PD3 floating control
8
RTEMP
PD3
PAD
8-Bit data bus
PD2
PAD
SMT
C1
5.7. LCD Controller
hardware allows some nibble operations to accomplish only at one
store and load instruction. The original data content should first
be stored at the register ($50, $51) and then, many decimal
operations, e.g. x10, /10 or nibble swap, can be obtained just by
executing reading instruction at the relative register ($52~5F). It
speeds up many decimal operations that originally require several
instructions for one operation.
GPL87108A contains a LCD controller/driver that provides the
capability of driving 11 commons and 60 segments LCD. To
reduce CPU loading, a display buffer is designed for mapping to
LCD. A LCD dot/pattern is set ON or OFF by programming the
corresponding bit of the display buffer. In addition, the LCD bias
can be programmed as 1/3 or 1/4. The available duty options are
1/3, 1/4, 1/5, 1/6, 1/8, 1/9, 1/10, and 1/11. The frame rate is set
to 85Hz at 1/9 duty, 77Hz at 1/10 duty, and 87Hz at 1/11 duty.
When selecting 1/3, 1/4, 1/6 or 1/8 duty, its frame rate is set to
80Hz. The frame rate is measured when low speed frequency
equals to 30.72KHz.
5.11. Analog Block
In addition to LCD controller and clock source, GPL87108A also
provides many low power and useful analog blocks. The built-in
power switch changes the power source automatically between
battery and solar cell, and it is helpful for two-way source that is a
common solution for many low power systems. The 1.2V/1.5V
internal regulator helps the whole system to be operative at low
current environment. Internal low voltage reset analog block
prevents the system away from abnormal operation at the voltage
under operation range.
5.8. LCD Voltage Generation
The GPL87108A offers a voltage regulator and a charge-pumping
circuit. Users can get the desired VLCD by changing the output
reference voltage (writing to register) of the voltage regulator.
Enabling the voltage regulator and charge-pumping circuit gets a
stable VLCD that will not be affected by VDD. The VLCD is
adjustable from 3V to 4.5V with 5 levels at 1/3bias, or 4.0V to 6.0V
with 5 levels at 1/4bias. It is suggested that VLCD must be
higher than VDD or abnormal operation will occur.
5.12. Mask Options
5.12.1. Low speed clock source selection
1). Rosc30K
2). X’TAL32K
5.9. Buzzer Driver
PD[1:0] can be used as buzzer output. When $16.b1 = b0 = ’1’,
PD.1 and PD.0 are set for buzzer output. Or else when b1 = b0
= ’0’, PD.1 and PD.0 are set to normal I/O. When counter
overflows, it will toggle PD.1 and PD.0 for driving buzzer.
5.12.2. Watchdog timer
1). Enabled
2). Disabled
5.12.3. Operation voltage selection
5.10. Auxiliary Calculation Hardware
1). 1.2V~1.8V
2). 1.8V~3.6V
GPL87108A contains auxiliary calculation hardware.
This
© Generalplus Technology Inc.
Proprietary & Confidential
8
Mar. 15, 2016
Version: 1.0
GPL87108A
5.12.4. SEG53/PC3 pin share selection
5.12.8. SEG57/PD5 pin share selection
1). Pin used as PC3
1). Pin used as PD5
2). Pin used as SEG53
2). Pin used as SEG57
5.12.5. SEG54/PC2 pin share selection
5.12.9. SEG58/PD4 pin share selection
1). Pin used as PC2
1). Pin used as PD4
2). Pin used as SEG54
2). Pin used as SEG58
5.12.6. SEG55/PC1 pin share selection
5.12.10. SEG59/PD3 pin share selection
1). Pin used as PC1
1). Pin used as PD3
2). Pin used as SEG55
2). Pin used as SEG59
5.12.7. SEG56/PC0 pin share selection
1). Pin used as PC0
2). Pin used as SEG56
5.13. Map of Memory
CPU View
$0000
Control Register
2432B SRAM
$005F
$0060
$09DF
$09E0
Unused
$3DFF
$3E00
ROM View
88B DPSRAM
Unused
0L
0H
1L
$00000 - $03FFF
$04000 - $07FFF
$08000 - $0BFFF
$0C000 - $0FFFF
0
1
$3EA7
$3FFF
$4000
1H
ROM
(Bank)L
$7FFF
$8000
2
ROM
(Bank)H
$BFFF
$C000
$C800
Test ROM(2KB)
ROM
Bank address $30H
$C000~$FFFF always mapping into 0L
0L
$FFDF
$FFFF
GP used & Vector
© Generalplus Technology Inc.
Proprietary & Confidential
9
Mar. 15, 2016
Version: 1.0
GPL87108A
6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics
DC Supply Voltage
Input Voltage Range
Symbol
V+
Ratings
-0.3~5 V
VIN
-0.3V to V+ + 0.3V
-20℃ to +70℃@1.8V~3.6V
0℃ to +70℃@1.2V~1.8V
-40℃ to +125℃
Operating Temperature
Storage Temperature
TOPR
TSTG
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions
see AC/DC Electrical Characteristics.
6.2. DC Characteristics(TA = 25℃)
Limit
Characteristics
Symbol
Unit Terminal
Test Condition
Min.
Typ.
Max.
1.2
-
1.8
Operation voltage select 1.2~1.8V
Operation voltage select 1.8~3.6V
Operating Voltage
VCC
VHS
V
V
V
VDDSW
VB,VS
VREG
1.8
-
3.6
Hysteresis voltage of power switch
Internal regulator output for logic
0.09
0.1
0.13
1.1
1.2
1.4
Operation voltage select 1.2~1.8V
Operation voltage select 1.8~3.6V
VREG
1.3
1.5
1.7
Input High Level
Input Low Level
VIH
VIL
Vddsw*0.7
-
Vddsw
V
V
PC,PD,PE
PC,PD,PE
-
-
Vddsw*0.3
2.0
0.4
4.0
1.0
8
-
-
-
-
-
-
-
-
-
Vddsw = 3.0V, VOH = 0.7*Vddsw
Vddsw = 1.5V, VOH = 0.7*Vddsw
Vddsw = 3.0V, VOL = 0.3*Vddsw
Vddsw = 1.5V, VOL = 0.3*Vddsw
Vddsw = 3.0V, VOH = 0.7*Vddsw
Vddsw = 1.5V, VOH = 0.7*Vddsw
Vddsw = 3.0V, VOL = 0.3*Vddsw
Vddsw = 1.5V, VOL = 0.3*Vddsw
1/3 bias, At 25 deg and -8.1mv/℃
Output High Current (I/O)
Output Sink Current (I/O)
Output High Current (Buzzer)
Output Sink Current (Buzzer)
IOH
IOL
IOH
IOL
mA
mA
mA
mA
V
-
PC,PD,PE
-
-
-
2
-
PD[1:0]
Vlcd
10
3
-
-
3.0~4.5
4.0~6.0
140
225
500
1000
1800
30.72
32.768
LCD Bias Voltage
Vlcd
RPL
-5%
+5%
1/4 bias,At 25 deg and -10.8mv/℃
VDD=1.2~3.6V
Pull low Resistance
50
210
K PC,PD,PE
-20%
+20%
Clock selected as 225kHz *2
Clock selected as 500kHz *2
High Frequency
Low Frequency
FH
kHz
-
-
Clock selected as 1000kHz *2
Clock selected as 1800kHz *2
-20%
-
+20%
-
Low speed clock select as IOSC30K
X32I,X32O Low speed clock select as XTAL32K
High Frequency =225kHz, CPU on,
LCD on, no load (VDD=3.6V)
FL
kHz
A
-
-
-
-
15
35
20
-
High Frequency =500kHz, CPU on,
LCD on, no load (VDD=3.6V)
A
A
A
Operating Current
IOP
High Frequency =1000kHz, CPU on,
LCD on, no load (VDD=3.6V)
65
-
High Frequency =1800kHz, CPU on,
LCD on, no load (VDD=3.6V)
100
-
© Generalplus Technology Inc.
Proprietary & Confidential
10
Mar. 15, 2016
Version: 1.0
GPL87108A
Limit
Typ.
Characteristics
Symbol
Unit Terminal
Test Condition
Min.
Max.
Low Frequency active, CPU off, LCD
Halt Current
IHALT
-
3.2
4
A
A
A
on, no load(VDD=3.6V) @50℃
Clock
off( VDD=3.6V) @25℃
Clock is stopped,
off( VDD=3.6V) @50℃
is
stopped,
LCD
LCD
-
-
-
-
1.0
1.5
Standby Current
ISTBY
Note1: Vlcd should be higher than VDD to prevent forward biasing the p-n junction of I/O output PMOS.
Note2: Only the main CPU frequency selected in confirmation sheet is guaranteed in the range of +/-20% variation, and the other frequencies may
be beyond the range of +/-20% variation.
For example, if 1800KHZ is selected as CPU frequency in confirmation sheet, 1800KHZ is varied in the range of +/-20%. The other frequencies such
as 225KHZ, 500KHZ, or 1000KHZ may beyond the range of +/-20% variation.
© Generalplus Technology Inc.
Proprietary & Confidential
11
Mar. 15, 2016
Version: 1.0
GPL87108A
7. APPLICATION CIRCUITS
LCD Panel (11x57)
PTEST
ACON
VDDSW
VS
0.1uF
VREG
0.1uF
VLCD
0.1uF
V3X
10uF
VB
0.1uF
V2X
GPL87108A
0.1uF
V1X
VSS
0.1
uF
CUP1
CUP2
12-20pF*1
X32I
32768Hz
X32O
12-20pF*1
I/O or key
matrix
Note: These capacitor values are for design reference only. Different capacitor values may be required for different crystal/resonator used.
© Generalplus Technology Inc.
Proprietary & Confidential
12
Mar. 15, 2016
Version: 1.0
GPL87108A
8. PACKAGE/PAD LOCATIONS
8.1. Ordering Information
Product Number
Package Type
Chip form
GPL87108A -NnnV-C
Note1: Code number (NnnV) is assigned for customer.
Note2: Code number (N = A-Z or 0-9, nn=00-99); version (V = A - Z)
© Generalplus Technology Inc.
Proprietary & Confidential
13
Mar. 15, 2016
Version: 1.0
GPL87108A
9. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc.
Proprietary & Confidential
14
Mar. 15, 2016
Version: 1.0
GPL87108A
10. REVISION HISTORY
Date
Revision #
Description
Page
10-11
15
Mar. 15, 2016
Aug. 01, 2011
1.1
1.0
modified section 6.2
1. modified features;
2. modified V4X to Vlcd in block diagram, signal description & PAD assignment;
3. modified section 5.7;
4. removed control register description at section 5.12;
5. modified section 6.1 & 6.2;
Original
Nov. 12, 2010
0.1
14
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Proprietary & Confidential
15
Mar. 15, 2016
Version: 1.0
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